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9f6c9258 DK |
1 | /* bnx2x_cmn.h: Broadcom Everest network driver. |
2 | * | |
5de92408 | 3 | * Copyright (c) 2007-2011 Broadcom Corporation |
9f6c9258 DK |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation. | |
8 | * | |
9 | * Maintained by: Eilon Greenstein <eilong@broadcom.com> | |
10 | * Written by: Eliezer Tamir | |
11 | * Based on code from Michael Chan's bnx2 driver | |
12 | * UDP CSUM errata workaround by Arik Gendelman | |
13 | * Slowpath and fastpath rework by Vladislav Zolotarov | |
14 | * Statistics and Link management by Yitchak Gertner | |
15 | * | |
16 | */ | |
17 | #ifndef BNX2X_CMN_H | |
18 | #define BNX2X_CMN_H | |
19 | ||
20 | #include <linux/types.h> | |
21 | #include <linux/netdevice.h> | |
22 | ||
23 | ||
24 | #include "bnx2x.h" | |
25 | ||
d6214d7a | 26 | extern int num_queues; |
9f6c9258 | 27 | |
b3b83c3f DK |
28 | /************************ Macros ********************************/ |
29 | #define BNX2X_PCI_FREE(x, y, size) \ | |
30 | do { \ | |
31 | if (x) { \ | |
32 | dma_free_coherent(&bp->pdev->dev, size, (void *)x, y); \ | |
33 | x = NULL; \ | |
34 | y = 0; \ | |
35 | } \ | |
36 | } while (0) | |
37 | ||
38 | #define BNX2X_FREE(x) \ | |
39 | do { \ | |
40 | if (x) { \ | |
41 | kfree((void *)x); \ | |
42 | x = NULL; \ | |
43 | } \ | |
44 | } while (0) | |
45 | ||
46 | #define BNX2X_PCI_ALLOC(x, y, size) \ | |
47 | do { \ | |
48 | x = dma_alloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL); \ | |
49 | if (x == NULL) \ | |
50 | goto alloc_mem_err; \ | |
51 | memset((void *)x, 0, size); \ | |
52 | } while (0) | |
53 | ||
54 | #define BNX2X_ALLOC(x, size) \ | |
55 | do { \ | |
56 | x = kzalloc(size, GFP_KERNEL); \ | |
57 | if (x == NULL) \ | |
58 | goto alloc_mem_err; \ | |
59 | } while (0) | |
60 | ||
9f6c9258 DK |
61 | /*********************** Interfaces **************************** |
62 | * Functions that need to be implemented by each driver version | |
63 | */ | |
64 | ||
65 | /** | |
e8920674 | 66 | * bnx2x_initial_phy_init - initialize link parameters structure variables. |
9f6c9258 | 67 | * |
e8920674 DK |
68 | * @bp: driver handle |
69 | * @load_mode: current mode | |
9f6c9258 DK |
70 | */ |
71 | u8 bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode); | |
72 | ||
73 | /** | |
e8920674 | 74 | * bnx2x_link_set - configure hw according to link parameters structure. |
9f6c9258 | 75 | * |
e8920674 | 76 | * @bp: driver handle |
9f6c9258 DK |
77 | */ |
78 | void bnx2x_link_set(struct bnx2x *bp); | |
79 | ||
80 | /** | |
e8920674 | 81 | * bnx2x_link_test - query link status. |
9f6c9258 | 82 | * |
e8920674 DK |
83 | * @bp: driver handle |
84 | * @is_serdes: bool | |
9f6c9258 | 85 | * |
e8920674 | 86 | * Returns 0 if link is UP. |
9f6c9258 | 87 | */ |
a22f0788 | 88 | u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes); |
9f6c9258 DK |
89 | |
90 | /** | |
e8920674 | 91 | * bnx2x__link_status_update - handles link status change. |
9f6c9258 | 92 | * |
e8920674 | 93 | * @bp: driver handle |
9f6c9258 DK |
94 | */ |
95 | void bnx2x__link_status_update(struct bnx2x *bp); | |
96 | ||
f85582f8 | 97 | /** |
e8920674 | 98 | * bnx2x_link_report - report link status to upper layer. |
f85582f8 | 99 | * |
e8920674 | 100 | * @bp: driver handle |
f85582f8 DK |
101 | */ |
102 | void bnx2x_link_report(struct bnx2x *bp); | |
103 | ||
2ae17f66 VZ |
104 | /* None-atomic version of bnx2x_link_report() */ |
105 | void __bnx2x_link_report(struct bnx2x *bp); | |
106 | ||
0793f83f | 107 | /** |
e8920674 | 108 | * bnx2x_get_mf_speed - calculate MF speed. |
0793f83f | 109 | * |
e8920674 | 110 | * @bp: driver handle |
0793f83f | 111 | * |
e8920674 | 112 | * Takes into account current linespeed and MF configuration. |
0793f83f DK |
113 | */ |
114 | u16 bnx2x_get_mf_speed(struct bnx2x *bp); | |
115 | ||
9f6c9258 | 116 | /** |
e8920674 | 117 | * bnx2x_msix_sp_int - MSI-X slowpath interrupt handler |
9f6c9258 | 118 | * |
e8920674 DK |
119 | * @irq: irq number |
120 | * @dev_instance: private instance | |
9f6c9258 DK |
121 | */ |
122 | irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance); | |
123 | ||
124 | /** | |
e8920674 | 125 | * bnx2x_interrupt - non MSI-X interrupt handler |
9f6c9258 | 126 | * |
e8920674 DK |
127 | * @irq: irq number |
128 | * @dev_instance: private instance | |
9f6c9258 DK |
129 | */ |
130 | irqreturn_t bnx2x_interrupt(int irq, void *dev_instance); | |
131 | #ifdef BCM_CNIC | |
132 | ||
133 | /** | |
e8920674 | 134 | * bnx2x_cnic_notify - send command to cnic driver |
9f6c9258 | 135 | * |
e8920674 DK |
136 | * @bp: driver handle |
137 | * @cmd: command | |
9f6c9258 DK |
138 | */ |
139 | int bnx2x_cnic_notify(struct bnx2x *bp, int cmd); | |
140 | ||
141 | /** | |
e8920674 | 142 | * bnx2x_setup_cnic_irq_info - provides cnic with IRQ information |
9f6c9258 | 143 | * |
e8920674 | 144 | * @bp: driver handle |
9f6c9258 DK |
145 | */ |
146 | void bnx2x_setup_cnic_irq_info(struct bnx2x *bp); | |
147 | #endif | |
148 | ||
149 | /** | |
e8920674 | 150 | * bnx2x_int_enable - enable HW interrupts. |
9f6c9258 | 151 | * |
e8920674 | 152 | * @bp: driver handle |
9f6c9258 DK |
153 | */ |
154 | void bnx2x_int_enable(struct bnx2x *bp); | |
155 | ||
156 | /** | |
e8920674 DK |
157 | * bnx2x_int_disable_sync - disable interrupts. |
158 | * | |
159 | * @bp: driver handle | |
160 | * @disable_hw: true, disable HW interrupts. | |
9f6c9258 | 161 | * |
e8920674 DK |
162 | * This function ensures that there are no |
163 | * ISRs or SP DPCs (sp_task) are running after it returns. | |
9f6c9258 DK |
164 | */ |
165 | void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw); | |
166 | ||
6891dd25 | 167 | /** |
e8920674 | 168 | * bnx2x_init_firmware - loads device firmware |
6891dd25 | 169 | * |
e8920674 | 170 | * @bp: driver handle |
6891dd25 DK |
171 | */ |
172 | int bnx2x_init_firmware(struct bnx2x *bp); | |
173 | ||
9f6c9258 | 174 | /** |
e8920674 | 175 | * bnx2x_init_hw - init HW blocks according to current initialization stage. |
9f6c9258 | 176 | * |
e8920674 DK |
177 | * @bp: driver handle |
178 | * @load_code: COMMON, PORT or FUNCTION | |
9f6c9258 DK |
179 | */ |
180 | int bnx2x_init_hw(struct bnx2x *bp, u32 load_code); | |
181 | ||
182 | /** | |
e8920674 DK |
183 | * bnx2x_nic_init - init driver internals. |
184 | * | |
185 | * @bp: driver handle | |
186 | * @load_code: COMMON, PORT or FUNCTION | |
187 | * | |
188 | * Initializes: | |
9f6c9258 DK |
189 | * - rings |
190 | * - status blocks | |
191 | * - etc. | |
9f6c9258 DK |
192 | */ |
193 | void bnx2x_nic_init(struct bnx2x *bp, u32 load_code); | |
194 | ||
195 | /** | |
e8920674 | 196 | * bnx2x_alloc_mem - allocate driver's memory. |
9f6c9258 | 197 | * |
e8920674 | 198 | * @bp: driver handle |
9f6c9258 DK |
199 | */ |
200 | int bnx2x_alloc_mem(struct bnx2x *bp); | |
201 | ||
202 | /** | |
e8920674 | 203 | * bnx2x_free_mem - release driver's memory. |
9f6c9258 | 204 | * |
e8920674 | 205 | * @bp: driver handle |
9f6c9258 DK |
206 | */ |
207 | void bnx2x_free_mem(struct bnx2x *bp); | |
208 | ||
209 | /** | |
e8920674 | 210 | * bnx2x_setup_client - setup eth client. |
9f6c9258 | 211 | * |
e8920674 DK |
212 | * @bp: driver handle |
213 | * @fp: pointer to fastpath structure | |
214 | * @is_leading: boolean | |
9f6c9258 | 215 | */ |
523224a3 DK |
216 | int bnx2x_setup_client(struct bnx2x *bp, struct bnx2x_fastpath *fp, |
217 | int is_leading); | |
9f6c9258 | 218 | |
9f6c9258 | 219 | /** |
e8920674 | 220 | * bnx2x_set_num_queues - set number of queues according to mode. |
9f6c9258 | 221 | * |
e8920674 | 222 | * @bp: driver handle |
9f6c9258 | 223 | */ |
d6214d7a | 224 | void bnx2x_set_num_queues(struct bnx2x *bp); |
9f6c9258 DK |
225 | |
226 | /** | |
e8920674 DK |
227 | * bnx2x_chip_cleanup - cleanup chip internals. |
228 | * | |
229 | * @bp: driver handle | |
230 | * @unload_mode: COMMON, PORT, FUNCTION | |
231 | * | |
9f6c9258 | 232 | * - Cleanup MAC configuration. |
e8920674 | 233 | * - Closes clients. |
9f6c9258 | 234 | * - etc. |
9f6c9258 DK |
235 | */ |
236 | void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode); | |
237 | ||
238 | /** | |
e8920674 | 239 | * bnx2x_acquire_hw_lock - acquire HW lock. |
9f6c9258 | 240 | * |
e8920674 DK |
241 | * @bp: driver handle |
242 | * @resource: resource bit which was locked | |
9f6c9258 DK |
243 | */ |
244 | int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource); | |
245 | ||
246 | /** | |
e8920674 | 247 | * bnx2x_release_hw_lock - release HW lock. |
9f6c9258 | 248 | * |
e8920674 DK |
249 | * @bp: driver handle |
250 | * @resource: resource bit which was locked | |
9f6c9258 DK |
251 | */ |
252 | int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource); | |
253 | ||
254 | /** | |
e8920674 DK |
255 | * bnx2x_set_eth_mac - configure eth MAC address in the HW |
256 | * | |
257 | * @bp: driver handle | |
258 | * @set: set or clear | |
9f6c9258 | 259 | * |
e8920674 | 260 | * Configures according to the value in netdev->dev_addr. |
9f6c9258 | 261 | */ |
523224a3 | 262 | void bnx2x_set_eth_mac(struct bnx2x *bp, int set); |
9f6c9258 | 263 | |
ec6ba945 VZ |
264 | #ifdef BCM_CNIC |
265 | /** | |
e8920674 | 266 | * bnx2x_set_fip_eth_mac_addr - Set/Clear FIP MAC(s) |
ec6ba945 | 267 | * |
e8920674 DK |
268 | * @bp: driver handle |
269 | * @set: set or clear the CAM entry | |
ec6ba945 | 270 | * |
e8920674 DK |
271 | * Used next enties in the CAM after the ETH MAC(s). |
272 | * This function will wait until the ramdord completion returns. | |
273 | * Return 0 if cussess, -ENODEV if ramrod doesn't return. | |
ec6ba945 VZ |
274 | */ |
275 | int bnx2x_set_fip_eth_mac_addr(struct bnx2x *bp, int set); | |
276 | ||
277 | /** | |
e8920674 | 278 | * bnx2x_set_all_enode_macs - Set/Clear ALL_ENODE mcast MAC. |
ec6ba945 | 279 | * |
e8920674 DK |
280 | * @bp: driver handle |
281 | * @set: set or clear | |
ec6ba945 VZ |
282 | */ |
283 | int bnx2x_set_all_enode_macs(struct bnx2x *bp, int set); | |
284 | #endif | |
285 | ||
9f6c9258 | 286 | /** |
e8920674 | 287 | * bnx2x_set_rx_mode - set MAC filtering configurations. |
9f6c9258 | 288 | * |
e8920674 | 289 | * @dev: netdevice |
9f6c9258 | 290 | * |
e8920674 | 291 | * called with netif_tx_lock from dev_mcast.c |
9f6c9258 DK |
292 | */ |
293 | void bnx2x_set_rx_mode(struct net_device *dev); | |
294 | ||
295 | /** | |
e8920674 | 296 | * bnx2x_set_storm_rx_mode - configure MAC filtering rules in a FW. |
9f6c9258 | 297 | * |
e8920674 | 298 | * @bp: driver handle |
9f6c9258 DK |
299 | */ |
300 | void bnx2x_set_storm_rx_mode(struct bnx2x *bp); | |
301 | ||
302 | /* Parity errors related */ | |
303 | void bnx2x_inc_load_cnt(struct bnx2x *bp); | |
304 | u32 bnx2x_dec_load_cnt(struct bnx2x *bp); | |
305 | bool bnx2x_chk_parity_attn(struct bnx2x *bp); | |
306 | bool bnx2x_reset_is_done(struct bnx2x *bp); | |
307 | void bnx2x_disable_close_the_gate(struct bnx2x *bp); | |
308 | ||
309 | /** | |
e8920674 | 310 | * bnx2x_stats_handle - perform statistics handling according to event. |
9f6c9258 | 311 | * |
e8920674 DK |
312 | * @bp: driver handle |
313 | * @event: bnx2x_stats_event | |
9f6c9258 DK |
314 | */ |
315 | void bnx2x_stats_handle(struct bnx2x *bp, enum bnx2x_stats_event event); | |
316 | ||
9f6c9258 | 317 | /** |
e8920674 | 318 | * bnx2x_sp_event - handle ramrods completion. |
9f6c9258 | 319 | * |
e8920674 DK |
320 | * @fp: fastpath handle for the event |
321 | * @rr_cqe: eth_rx_cqe | |
9f6c9258 | 322 | */ |
f85582f8 | 323 | void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe); |
9f6c9258 | 324 | |
523224a3 | 325 | /** |
e8920674 | 326 | * bnx2x_func_start - init function |
523224a3 | 327 | * |
e8920674 | 328 | * @bp: driver handle |
523224a3 | 329 | * |
e8920674 | 330 | * Must be called before sending CLIENT_SETUP for the first client. |
523224a3 DK |
331 | */ |
332 | int bnx2x_func_start(struct bnx2x *bp); | |
523224a3 DK |
333 | |
334 | /** | |
e8920674 | 335 | * bnx2x_ilt_set_info - prepare ILT configurations. |
523224a3 | 336 | * |
e8920674 | 337 | * @bp: driver handle |
523224a3 DK |
338 | */ |
339 | void bnx2x_ilt_set_info(struct bnx2x *bp); | |
9f6c9258 | 340 | |
e4901dde | 341 | /** |
e8920674 | 342 | * bnx2x_dcbx_init - initialize dcbx protocol. |
e4901dde | 343 | * |
e8920674 | 344 | * @bp: driver handle |
e4901dde VZ |
345 | */ |
346 | void bnx2x_dcbx_init(struct bnx2x *bp); | |
347 | ||
f85582f8 | 348 | /** |
e8920674 | 349 | * bnx2x_set_power_state - set power state to the requested value. |
f85582f8 | 350 | * |
e8920674 DK |
351 | * @bp: driver handle |
352 | * @state: required state D0 or D3hot | |
f85582f8 | 353 | * |
e8920674 | 354 | * Currently only D0 and D3hot are supported. |
f85582f8 DK |
355 | */ |
356 | int bnx2x_set_power_state(struct bnx2x *bp, pci_power_t state); | |
357 | ||
e3835b99 | 358 | /** |
e8920674 | 359 | * bnx2x_update_max_mf_config - update MAX part of MF configuration in HW. |
e3835b99 | 360 | * |
e8920674 DK |
361 | * @bp: driver handle |
362 | * @value: new value | |
e3835b99 DK |
363 | */ |
364 | void bnx2x_update_max_mf_config(struct bnx2x *bp, u32 value); | |
365 | ||
f85582f8 DK |
366 | /* dev_close main block */ |
367 | int bnx2x_nic_unload(struct bnx2x *bp, int unload_mode); | |
368 | ||
369 | /* dev_open main block */ | |
370 | int bnx2x_nic_load(struct bnx2x *bp, int load_mode); | |
371 | ||
372 | /* hard_xmit callback */ | |
373 | netdev_tx_t bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev); | |
374 | ||
8307fa3e VZ |
375 | /* select_queue callback */ |
376 | u16 bnx2x_select_queue(struct net_device *dev, struct sk_buff *skb); | |
377 | ||
f85582f8 DK |
378 | int bnx2x_change_mac_addr(struct net_device *dev, void *p); |
379 | ||
380 | /* NAPI poll Rx part */ | |
381 | int bnx2x_rx_int(struct bnx2x_fastpath *fp, int budget); | |
382 | ||
383 | /* NAPI poll Tx part */ | |
384 | int bnx2x_tx_int(struct bnx2x_fastpath *fp); | |
385 | ||
386 | /* suspend/resume callbacks */ | |
387 | int bnx2x_suspend(struct pci_dev *pdev, pm_message_t state); | |
388 | int bnx2x_resume(struct pci_dev *pdev); | |
389 | ||
390 | /* Release IRQ vectors */ | |
391 | void bnx2x_free_irq(struct bnx2x *bp); | |
392 | ||
b3b83c3f DK |
393 | void bnx2x_free_fp_mem(struct bnx2x *bp); |
394 | int bnx2x_alloc_fp_mem(struct bnx2x *bp); | |
395 | ||
f85582f8 DK |
396 | void bnx2x_init_rx_rings(struct bnx2x *bp); |
397 | void bnx2x_free_skbs(struct bnx2x *bp); | |
398 | void bnx2x_netif_stop(struct bnx2x *bp, int disable_hw); | |
399 | void bnx2x_netif_start(struct bnx2x *bp); | |
400 | ||
d6214d7a | 401 | /** |
e8920674 | 402 | * bnx2x_enable_msix - set msix configuration. |
d6214d7a | 403 | * |
e8920674 | 404 | * @bp: driver handle |
d6214d7a | 405 | * |
e8920674 DK |
406 | * fills msix_table, requests vectors, updates num_queues |
407 | * according to number of available vectors. | |
d6214d7a DK |
408 | */ |
409 | int bnx2x_enable_msix(struct bnx2x *bp); | |
410 | ||
411 | /** | |
e8920674 | 412 | * bnx2x_enable_msi - request msi mode from OS, updated internals accordingly |
d6214d7a | 413 | * |
e8920674 | 414 | * @bp: driver handle |
d6214d7a DK |
415 | */ |
416 | int bnx2x_enable_msi(struct bnx2x *bp); | |
417 | ||
d6214d7a | 418 | /** |
e8920674 | 419 | * bnx2x_poll - NAPI callback |
d6214d7a | 420 | * |
e8920674 DK |
421 | * @napi: napi structure |
422 | * @budget: | |
d6214d7a | 423 | * |
d6214d7a DK |
424 | */ |
425 | int bnx2x_poll(struct napi_struct *napi, int budget); | |
f85582f8 DK |
426 | |
427 | /** | |
e8920674 | 428 | * bnx2x_alloc_mem_bp - allocate memories outsize main driver structure |
f85582f8 | 429 | * |
e8920674 | 430 | * @bp: driver handle |
f85582f8 DK |
431 | */ |
432 | int __devinit bnx2x_alloc_mem_bp(struct bnx2x *bp); | |
e8920674 DK |
433 | |
434 | /** | |
435 | * bnx2x_free_mem_bp - release memories outsize main driver structure | |
436 | * | |
437 | * @bp: driver handle | |
438 | */ | |
f85582f8 DK |
439 | void bnx2x_free_mem_bp(struct bnx2x *bp); |
440 | ||
441 | /** | |
e8920674 | 442 | * bnx2x_change_mtu - change mtu netdev callback |
f85582f8 | 443 | * |
e8920674 DK |
444 | * @dev: net device |
445 | * @new_mtu: requested mtu | |
f85582f8 | 446 | * |
f85582f8 DK |
447 | */ |
448 | int bnx2x_change_mtu(struct net_device *dev, int new_mtu); | |
449 | ||
66371c44 MM |
450 | u32 bnx2x_fix_features(struct net_device *dev, u32 features); |
451 | int bnx2x_set_features(struct net_device *dev, u32 features); | |
452 | ||
f85582f8 | 453 | /** |
e8920674 | 454 | * bnx2x_tx_timeout - tx timeout netdev callback |
f85582f8 | 455 | * |
e8920674 | 456 | * @dev: net device |
f85582f8 DK |
457 | */ |
458 | void bnx2x_tx_timeout(struct net_device *dev); | |
459 | ||
9f6c9258 DK |
460 | static inline void bnx2x_update_fpsb_idx(struct bnx2x_fastpath *fp) |
461 | { | |
9f6c9258 | 462 | barrier(); /* status block is written to by the chip */ |
523224a3 | 463 | fp->fp_hc_idx = fp->sb_running_index[SM_RX_ID]; |
9f6c9258 DK |
464 | } |
465 | ||
466 | static inline void bnx2x_update_rx_prod(struct bnx2x *bp, | |
467 | struct bnx2x_fastpath *fp, | |
468 | u16 bd_prod, u16 rx_comp_prod, | |
469 | u16 rx_sge_prod) | |
470 | { | |
471 | struct ustorm_eth_rx_producers rx_prods = {0}; | |
472 | int i; | |
473 | ||
474 | /* Update producers */ | |
475 | rx_prods.bd_prod = bd_prod; | |
476 | rx_prods.cqe_prod = rx_comp_prod; | |
477 | rx_prods.sge_prod = rx_sge_prod; | |
478 | ||
479 | /* | |
480 | * Make sure that the BD and SGE data is updated before updating the | |
481 | * producers since FW might read the BD/SGE right after the producer | |
482 | * is updated. | |
483 | * This is only applicable for weak-ordered memory model archs such | |
484 | * as IA-64. The following barrier is also mandatory since FW will | |
485 | * assumes BDs must have buffers. | |
486 | */ | |
487 | wmb(); | |
488 | ||
489 | for (i = 0; i < sizeof(struct ustorm_eth_rx_producers)/4; i++) | |
523224a3 DK |
490 | REG_WR(bp, |
491 | BAR_USTRORM_INTMEM + fp->ustorm_rx_prods_offset + i*4, | |
9f6c9258 DK |
492 | ((u32 *)&rx_prods)[i]); |
493 | ||
494 | mmiowb(); /* keep prod updates ordered */ | |
495 | ||
496 | DP(NETIF_MSG_RX_STATUS, | |
497 | "queue[%d]: wrote bd_prod %u cqe_prod %u sge_prod %u\n", | |
498 | fp->index, bd_prod, rx_comp_prod, rx_sge_prod); | |
499 | } | |
500 | ||
f2e0899f DK |
501 | static inline void bnx2x_igu_ack_sb_gen(struct bnx2x *bp, u8 igu_sb_id, |
502 | u8 segment, u16 index, u8 op, | |
503 | u8 update, u32 igu_addr) | |
504 | { | |
505 | struct igu_regular cmd_data = {0}; | |
506 | ||
507 | cmd_data.sb_id_and_flags = | |
508 | ((index << IGU_REGULAR_SB_INDEX_SHIFT) | | |
509 | (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) | | |
510 | (update << IGU_REGULAR_BUPDATE_SHIFT) | | |
511 | (op << IGU_REGULAR_ENABLE_INT_SHIFT)); | |
512 | ||
513 | DP(NETIF_MSG_HW, "write 0x%08x to IGU addr 0x%x\n", | |
514 | cmd_data.sb_id_and_flags, igu_addr); | |
515 | REG_WR(bp, igu_addr, cmd_data.sb_id_and_flags); | |
516 | ||
517 | /* Make sure that ACK is written */ | |
518 | mmiowb(); | |
519 | barrier(); | |
520 | } | |
521 | ||
522 | static inline void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, | |
523 | u8 idu_sb_id, bool is_Pf) | |
524 | { | |
525 | u32 data, ctl, cnt = 100; | |
526 | u32 igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA; | |
527 | u32 igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL; | |
528 | u32 igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP + (idu_sb_id/32)*4; | |
529 | u32 sb_bit = 1 << (idu_sb_id%32); | |
530 | u32 func_encode = BP_FUNC(bp) | | |
531 | ((is_Pf == true ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT); | |
532 | u32 addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id; | |
533 | ||
534 | /* Not supported in BC mode */ | |
535 | if (CHIP_INT_MODE_IS_BC(bp)) | |
536 | return; | |
537 | ||
538 | data = (IGU_USE_REGISTER_cstorm_type_0_sb_cleanup | |
539 | << IGU_REGULAR_CLEANUP_TYPE_SHIFT) | | |
540 | IGU_REGULAR_CLEANUP_SET | | |
541 | IGU_REGULAR_BCLEANUP; | |
542 | ||
543 | ctl = addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT | | |
544 | func_encode << IGU_CTRL_REG_FID_SHIFT | | |
545 | IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT; | |
9f6c9258 | 546 | |
f2e0899f DK |
547 | DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n", |
548 | data, igu_addr_data); | |
549 | REG_WR(bp, igu_addr_data, data); | |
550 | mmiowb(); | |
551 | barrier(); | |
552 | DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n", | |
553 | ctl, igu_addr_ctl); | |
554 | REG_WR(bp, igu_addr_ctl, ctl); | |
555 | mmiowb(); | |
556 | barrier(); | |
9f6c9258 | 557 | |
f2e0899f DK |
558 | /* wait for clean up to finish */ |
559 | while (!(REG_RD(bp, igu_addr_ack) & sb_bit) && --cnt) | |
560 | msleep(20); | |
561 | ||
562 | ||
563 | if (!(REG_RD(bp, igu_addr_ack) & sb_bit)) { | |
564 | DP(NETIF_MSG_HW, "Unable to finish IGU cleanup: " | |
565 | "idu_sb_id %d offset %d bit %d (cnt %d)\n", | |
566 | idu_sb_id, idu_sb_id/32, idu_sb_id%32, cnt); | |
567 | } | |
568 | } | |
569 | ||
570 | static inline void bnx2x_hc_ack_sb(struct bnx2x *bp, u8 sb_id, | |
571 | u8 storm, u16 index, u8 op, u8 update) | |
9f6c9258 DK |
572 | { |
573 | u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 + | |
574 | COMMAND_REG_INT_ACK); | |
575 | struct igu_ack_register igu_ack; | |
576 | ||
577 | igu_ack.status_block_index = index; | |
578 | igu_ack.sb_id_and_flags = | |
579 | ((sb_id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) | | |
580 | (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) | | |
581 | (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) | | |
582 | (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT)); | |
583 | ||
584 | DP(BNX2X_MSG_OFF, "write 0x%08x to HC addr 0x%x\n", | |
585 | (*(u32 *)&igu_ack), hc_addr); | |
586 | REG_WR(bp, hc_addr, (*(u32 *)&igu_ack)); | |
587 | ||
588 | /* Make sure that ACK is written */ | |
589 | mmiowb(); | |
590 | barrier(); | |
591 | } | |
f2e0899f DK |
592 | |
593 | static inline void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment, | |
594 | u16 index, u8 op, u8 update) | |
595 | { | |
596 | u32 igu_addr = BAR_IGU_INTMEM + (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8; | |
597 | ||
598 | bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update, | |
599 | igu_addr); | |
600 | } | |
601 | ||
602 | static inline void bnx2x_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 storm, | |
603 | u16 index, u8 op, u8 update) | |
604 | { | |
605 | if (bp->common.int_block == INT_BLOCK_HC) | |
606 | bnx2x_hc_ack_sb(bp, igu_sb_id, storm, index, op, update); | |
607 | else { | |
608 | u8 segment; | |
609 | ||
610 | if (CHIP_INT_MODE_IS_BC(bp)) | |
611 | segment = storm; | |
612 | else if (igu_sb_id != bp->igu_dsb_id) | |
613 | segment = IGU_SEG_ACCESS_DEF; | |
614 | else if (storm == ATTENTION_ID) | |
615 | segment = IGU_SEG_ACCESS_ATTN; | |
616 | else | |
617 | segment = IGU_SEG_ACCESS_DEF; | |
618 | bnx2x_igu_ack_sb(bp, igu_sb_id, segment, index, op, update); | |
619 | } | |
620 | } | |
621 | ||
622 | static inline u16 bnx2x_hc_ack_int(struct bnx2x *bp) | |
9f6c9258 DK |
623 | { |
624 | u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 + | |
625 | COMMAND_REG_SIMD_MASK); | |
626 | u32 result = REG_RD(bp, hc_addr); | |
627 | ||
628 | DP(BNX2X_MSG_OFF, "read 0x%08x from HC addr 0x%x\n", | |
629 | result, hc_addr); | |
630 | ||
f2e0899f | 631 | barrier(); |
9f6c9258 DK |
632 | return result; |
633 | } | |
634 | ||
f2e0899f DK |
635 | static inline u16 bnx2x_igu_ack_int(struct bnx2x *bp) |
636 | { | |
637 | u32 igu_addr = (BAR_IGU_INTMEM + IGU_REG_SISR_MDPC_WMASK_LSB_UPPER*8); | |
638 | u32 result = REG_RD(bp, igu_addr); | |
639 | ||
640 | DP(NETIF_MSG_HW, "read 0x%08x from IGU addr 0x%x\n", | |
641 | result, igu_addr); | |
642 | ||
643 | barrier(); | |
644 | return result; | |
645 | } | |
646 | ||
647 | static inline u16 bnx2x_ack_int(struct bnx2x *bp) | |
648 | { | |
649 | barrier(); | |
650 | if (bp->common.int_block == INT_BLOCK_HC) | |
651 | return bnx2x_hc_ack_int(bp); | |
652 | else | |
653 | return bnx2x_igu_ack_int(bp); | |
654 | } | |
655 | ||
9f6c9258 DK |
656 | static inline int bnx2x_has_tx_work_unload(struct bnx2x_fastpath *fp) |
657 | { | |
658 | /* Tell compiler that consumer and producer can change */ | |
659 | barrier(); | |
807540ba | 660 | return fp->tx_pkt_prod != fp->tx_pkt_cons; |
9f6c9258 DK |
661 | } |
662 | ||
663 | static inline u16 bnx2x_tx_avail(struct bnx2x_fastpath *fp) | |
664 | { | |
665 | s16 used; | |
666 | u16 prod; | |
667 | u16 cons; | |
668 | ||
669 | prod = fp->tx_bd_prod; | |
670 | cons = fp->tx_bd_cons; | |
671 | ||
672 | /* NUM_TX_RINGS = number of "next-page" entries | |
673 | It will be used as a threshold */ | |
674 | used = SUB_S16(prod, cons) + (s16)NUM_TX_RINGS; | |
675 | ||
676 | #ifdef BNX2X_STOP_ON_ERROR | |
677 | WARN_ON(used < 0); | |
678 | WARN_ON(used > fp->bp->tx_ring_size); | |
679 | WARN_ON((fp->bp->tx_ring_size - used) > MAX_TX_AVAIL); | |
680 | #endif | |
681 | ||
682 | return (s16)(fp->bp->tx_ring_size) - used; | |
683 | } | |
684 | ||
685 | static inline int bnx2x_has_tx_work(struct bnx2x_fastpath *fp) | |
686 | { | |
687 | u16 hw_cons; | |
688 | ||
689 | /* Tell compiler that status block fields can change */ | |
690 | barrier(); | |
691 | hw_cons = le16_to_cpu(*fp->tx_cons_sb); | |
692 | return hw_cons != fp->tx_pkt_cons; | |
693 | } | |
694 | ||
523224a3 DK |
695 | static inline int bnx2x_has_rx_work(struct bnx2x_fastpath *fp) |
696 | { | |
697 | u16 rx_cons_sb; | |
698 | ||
699 | /* Tell compiler that status block fields can change */ | |
700 | barrier(); | |
701 | rx_cons_sb = le16_to_cpu(*fp->rx_cons_sb); | |
702 | if ((rx_cons_sb & MAX_RCQ_DESC_CNT) == MAX_RCQ_DESC_CNT) | |
703 | rx_cons_sb++; | |
704 | return (fp->rx_comp_cons != rx_cons_sb); | |
705 | } | |
f85582f8 | 706 | |
f2e0899f DK |
707 | /** |
708 | * disables tx from stack point of view | |
709 | * | |
e8920674 | 710 | * @bp: driver handle |
f2e0899f DK |
711 | */ |
712 | static inline void bnx2x_tx_disable(struct bnx2x *bp) | |
713 | { | |
714 | netif_tx_disable(bp->dev); | |
715 | netif_carrier_off(bp->dev); | |
716 | } | |
717 | ||
9f6c9258 DK |
718 | static inline void bnx2x_free_rx_sge(struct bnx2x *bp, |
719 | struct bnx2x_fastpath *fp, u16 index) | |
720 | { | |
721 | struct sw_rx_page *sw_buf = &fp->rx_page_ring[index]; | |
722 | struct page *page = sw_buf->page; | |
723 | struct eth_rx_sge *sge = &fp->rx_sge_ring[index]; | |
724 | ||
725 | /* Skip "next page" elements */ | |
726 | if (!page) | |
727 | return; | |
728 | ||
729 | dma_unmap_page(&bp->pdev->dev, dma_unmap_addr(sw_buf, mapping), | |
4bca60f4 | 730 | SGE_PAGE_SIZE*PAGES_PER_SGE, DMA_FROM_DEVICE); |
9f6c9258 DK |
731 | __free_pages(page, PAGES_PER_SGE_SHIFT); |
732 | ||
733 | sw_buf->page = NULL; | |
734 | sge->addr_hi = 0; | |
735 | sge->addr_lo = 0; | |
736 | } | |
737 | ||
d6214d7a DK |
738 | static inline void bnx2x_add_all_napi(struct bnx2x *bp) |
739 | { | |
740 | int i; | |
523224a3 | 741 | |
d6214d7a | 742 | /* Add NAPI objects */ |
ec6ba945 | 743 | for_each_napi_queue(bp, i) |
d6214d7a DK |
744 | netif_napi_add(bp->dev, &bnx2x_fp(bp, i, napi), |
745 | bnx2x_poll, BNX2X_NAPI_WEIGHT); | |
746 | } | |
523224a3 | 747 | |
d6214d7a DK |
748 | static inline void bnx2x_del_all_napi(struct bnx2x *bp) |
749 | { | |
750 | int i; | |
751 | ||
ec6ba945 | 752 | for_each_napi_queue(bp, i) |
d6214d7a DK |
753 | netif_napi_del(&bnx2x_fp(bp, i, napi)); |
754 | } | |
523224a3 | 755 | |
d6214d7a DK |
756 | static inline void bnx2x_disable_msi(struct bnx2x *bp) |
757 | { | |
758 | if (bp->flags & USING_MSIX_FLAG) { | |
759 | pci_disable_msix(bp->pdev); | |
760 | bp->flags &= ~USING_MSIX_FLAG; | |
761 | } else if (bp->flags & USING_MSI_FLAG) { | |
762 | pci_disable_msi(bp->pdev); | |
763 | bp->flags &= ~USING_MSI_FLAG; | |
764 | } | |
765 | } | |
766 | ||
767 | static inline int bnx2x_calc_num_queues(struct bnx2x *bp) | |
768 | { | |
769 | return num_queues ? | |
770 | min_t(int, num_queues, BNX2X_MAX_QUEUES(bp)) : | |
771 | min_t(int, num_online_cpus(), BNX2X_MAX_QUEUES(bp)); | |
772 | } | |
523224a3 DK |
773 | |
774 | static inline void bnx2x_clear_sge_mask_next_elems(struct bnx2x_fastpath *fp) | |
9f6c9258 | 775 | { |
523224a3 | 776 | int i, j; |
9f6c9258 | 777 | |
523224a3 DK |
778 | for (i = 1; i <= NUM_RX_SGE_PAGES; i++) { |
779 | int idx = RX_SGE_CNT * i - 1; | |
780 | ||
781 | for (j = 0; j < 2; j++) { | |
782 | SGE_MASK_CLEAR_BIT(fp, idx); | |
783 | idx--; | |
784 | } | |
785 | } | |
786 | } | |
787 | ||
788 | static inline void bnx2x_init_sge_ring_bit_mask(struct bnx2x_fastpath *fp) | |
789 | { | |
790 | /* Set the mask to all 1-s: it's faster to compare to 0 than to 0xf-s */ | |
791 | memset(fp->sge_mask, 0xff, | |
792 | (NUM_RX_SGE >> RX_SGE_MASK_ELEM_SHIFT)*sizeof(u64)); | |
793 | ||
794 | /* Clear the two last indices in the page to 1: | |
795 | these are the indices that correspond to the "next" element, | |
796 | hence will never be indicated and should be removed from | |
797 | the calculations. */ | |
798 | bnx2x_clear_sge_mask_next_elems(fp); | |
9f6c9258 DK |
799 | } |
800 | ||
801 | static inline int bnx2x_alloc_rx_sge(struct bnx2x *bp, | |
802 | struct bnx2x_fastpath *fp, u16 index) | |
803 | { | |
804 | struct page *page = alloc_pages(GFP_ATOMIC, PAGES_PER_SGE_SHIFT); | |
805 | struct sw_rx_page *sw_buf = &fp->rx_page_ring[index]; | |
806 | struct eth_rx_sge *sge = &fp->rx_sge_ring[index]; | |
807 | dma_addr_t mapping; | |
808 | ||
809 | if (unlikely(page == NULL)) | |
810 | return -ENOMEM; | |
811 | ||
812 | mapping = dma_map_page(&bp->pdev->dev, page, 0, | |
813 | SGE_PAGE_SIZE*PAGES_PER_SGE, DMA_FROM_DEVICE); | |
814 | if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) { | |
815 | __free_pages(page, PAGES_PER_SGE_SHIFT); | |
816 | return -ENOMEM; | |
817 | } | |
818 | ||
819 | sw_buf->page = page; | |
820 | dma_unmap_addr_set(sw_buf, mapping, mapping); | |
821 | ||
822 | sge->addr_hi = cpu_to_le32(U64_HI(mapping)); | |
823 | sge->addr_lo = cpu_to_le32(U64_LO(mapping)); | |
824 | ||
825 | return 0; | |
826 | } | |
f85582f8 | 827 | |
9f6c9258 DK |
828 | static inline int bnx2x_alloc_rx_skb(struct bnx2x *bp, |
829 | struct bnx2x_fastpath *fp, u16 index) | |
830 | { | |
831 | struct sk_buff *skb; | |
832 | struct sw_rx_bd *rx_buf = &fp->rx_buf_ring[index]; | |
833 | struct eth_rx_bd *rx_bd = &fp->rx_desc_ring[index]; | |
834 | dma_addr_t mapping; | |
835 | ||
a8c94b91 | 836 | skb = netdev_alloc_skb(bp->dev, fp->rx_buf_size); |
9f6c9258 DK |
837 | if (unlikely(skb == NULL)) |
838 | return -ENOMEM; | |
839 | ||
a8c94b91 | 840 | mapping = dma_map_single(&bp->pdev->dev, skb->data, fp->rx_buf_size, |
9f6c9258 DK |
841 | DMA_FROM_DEVICE); |
842 | if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) { | |
843 | dev_kfree_skb(skb); | |
844 | return -ENOMEM; | |
845 | } | |
846 | ||
847 | rx_buf->skb = skb; | |
848 | dma_unmap_addr_set(rx_buf, mapping, mapping); | |
849 | ||
850 | rx_bd->addr_hi = cpu_to_le32(U64_HI(mapping)); | |
851 | rx_bd->addr_lo = cpu_to_le32(U64_LO(mapping)); | |
852 | ||
853 | return 0; | |
854 | } | |
855 | ||
856 | /* note that we are not allocating a new skb, | |
857 | * we are just moving one from cons to prod | |
858 | * we are not creating a new mapping, | |
859 | * so there is no need to check for dma_mapping_error(). | |
860 | */ | |
861 | static inline void bnx2x_reuse_rx_skb(struct bnx2x_fastpath *fp, | |
749a8503 | 862 | u16 cons, u16 prod) |
9f6c9258 DK |
863 | { |
864 | struct bnx2x *bp = fp->bp; | |
865 | struct sw_rx_bd *cons_rx_buf = &fp->rx_buf_ring[cons]; | |
866 | struct sw_rx_bd *prod_rx_buf = &fp->rx_buf_ring[prod]; | |
867 | struct eth_rx_bd *cons_bd = &fp->rx_desc_ring[cons]; | |
868 | struct eth_rx_bd *prod_bd = &fp->rx_desc_ring[prod]; | |
869 | ||
870 | dma_sync_single_for_device(&bp->pdev->dev, | |
871 | dma_unmap_addr(cons_rx_buf, mapping), | |
872 | RX_COPY_THRESH, DMA_FROM_DEVICE); | |
873 | ||
874 | prod_rx_buf->skb = cons_rx_buf->skb; | |
875 | dma_unmap_addr_set(prod_rx_buf, mapping, | |
876 | dma_unmap_addr(cons_rx_buf, mapping)); | |
877 | *prod_bd = *cons_bd; | |
878 | } | |
f85582f8 | 879 | |
523224a3 DK |
880 | static inline void bnx2x_free_rx_sge_range(struct bnx2x *bp, |
881 | struct bnx2x_fastpath *fp, int last) | |
9f6c9258 | 882 | { |
523224a3 | 883 | int i; |
9f6c9258 | 884 | |
b3b83c3f DK |
885 | if (fp->disable_tpa) |
886 | return; | |
887 | ||
523224a3 DK |
888 | for (i = 0; i < last; i++) |
889 | bnx2x_free_rx_sge(bp, fp, i); | |
9f6c9258 DK |
890 | } |
891 | ||
9f6c9258 DK |
892 | static inline void bnx2x_free_tpa_pool(struct bnx2x *bp, |
893 | struct bnx2x_fastpath *fp, int last) | |
894 | { | |
895 | int i; | |
896 | ||
897 | for (i = 0; i < last; i++) { | |
898 | struct sw_rx_bd *rx_buf = &(fp->tpa_pool[i]); | |
899 | struct sk_buff *skb = rx_buf->skb; | |
900 | ||
901 | if (skb == NULL) { | |
902 | DP(NETIF_MSG_IFDOWN, "tpa bin %d empty on free\n", i); | |
903 | continue; | |
904 | } | |
905 | ||
906 | if (fp->tpa_state[i] == BNX2X_TPA_START) | |
907 | dma_unmap_single(&bp->pdev->dev, | |
908 | dma_unmap_addr(rx_buf, mapping), | |
a8c94b91 | 909 | fp->rx_buf_size, DMA_FROM_DEVICE); |
9f6c9258 DK |
910 | |
911 | dev_kfree_skb(skb); | |
912 | rx_buf->skb = NULL; | |
913 | } | |
914 | } | |
915 | ||
b3b83c3f | 916 | static inline void bnx2x_init_tx_ring_one(struct bnx2x_fastpath *fp) |
9f6c9258 | 917 | { |
b3b83c3f | 918 | int i; |
9f6c9258 | 919 | |
b3b83c3f DK |
920 | for (i = 1; i <= NUM_TX_RINGS; i++) { |
921 | struct eth_tx_next_bd *tx_next_bd = | |
922 | &fp->tx_desc_ring[TX_DESC_CNT * i - 1].next_bd; | |
9f6c9258 | 923 | |
b3b83c3f DK |
924 | tx_next_bd->addr_hi = |
925 | cpu_to_le32(U64_HI(fp->tx_desc_mapping + | |
926 | BCM_PAGE_SIZE*(i % NUM_TX_RINGS))); | |
927 | tx_next_bd->addr_lo = | |
928 | cpu_to_le32(U64_LO(fp->tx_desc_mapping + | |
929 | BCM_PAGE_SIZE*(i % NUM_TX_RINGS))); | |
930 | } | |
9f6c9258 | 931 | |
b3b83c3f DK |
932 | SET_FLAG(fp->tx_db.data.header.header, DOORBELL_HDR_DB_TYPE, 1); |
933 | fp->tx_db.data.zero_fill1 = 0; | |
934 | fp->tx_db.data.prod = 0; | |
9f6c9258 | 935 | |
b3b83c3f DK |
936 | fp->tx_pkt_prod = 0; |
937 | fp->tx_pkt_cons = 0; | |
938 | fp->tx_bd_prod = 0; | |
939 | fp->tx_bd_cons = 0; | |
940 | fp->tx_pkt = 0; | |
941 | } | |
9f6c9258 | 942 | |
b3b83c3f DK |
943 | static inline void bnx2x_init_tx_rings(struct bnx2x *bp) |
944 | { | |
945 | int i; | |
946 | ||
947 | for_each_tx_queue(bp, i) | |
948 | bnx2x_init_tx_ring_one(&bp->fp[i]); | |
9f6c9258 | 949 | } |
f85582f8 | 950 | |
523224a3 | 951 | static inline void bnx2x_set_next_page_rx_bd(struct bnx2x_fastpath *fp) |
9f6c9258 | 952 | { |
523224a3 | 953 | int i; |
9f6c9258 | 954 | |
523224a3 DK |
955 | for (i = 1; i <= NUM_RX_RINGS; i++) { |
956 | struct eth_rx_bd *rx_bd; | |
957 | ||
958 | rx_bd = &fp->rx_desc_ring[RX_DESC_CNT * i - 2]; | |
959 | rx_bd->addr_hi = | |
960 | cpu_to_le32(U64_HI(fp->rx_desc_mapping + | |
961 | BCM_PAGE_SIZE*(i % NUM_RX_RINGS))); | |
962 | rx_bd->addr_lo = | |
963 | cpu_to_le32(U64_LO(fp->rx_desc_mapping + | |
964 | BCM_PAGE_SIZE*(i % NUM_RX_RINGS))); | |
965 | } | |
9f6c9258 DK |
966 | } |
967 | ||
523224a3 DK |
968 | static inline void bnx2x_set_next_page_sgl(struct bnx2x_fastpath *fp) |
969 | { | |
970 | int i; | |
971 | ||
972 | for (i = 1; i <= NUM_RX_SGE_PAGES; i++) { | |
973 | struct eth_rx_sge *sge; | |
974 | ||
975 | sge = &fp->rx_sge_ring[RX_SGE_CNT * i - 2]; | |
976 | sge->addr_hi = | |
977 | cpu_to_le32(U64_HI(fp->rx_sge_mapping + | |
978 | BCM_PAGE_SIZE*(i % NUM_RX_SGE_PAGES))); | |
979 | ||
980 | sge->addr_lo = | |
981 | cpu_to_le32(U64_LO(fp->rx_sge_mapping + | |
982 | BCM_PAGE_SIZE*(i % NUM_RX_SGE_PAGES))); | |
983 | } | |
984 | } | |
985 | ||
986 | static inline void bnx2x_set_next_page_rx_cq(struct bnx2x_fastpath *fp) | |
987 | { | |
988 | int i; | |
989 | for (i = 1; i <= NUM_RCQ_RINGS; i++) { | |
990 | struct eth_rx_cqe_next_page *nextpg; | |
991 | ||
992 | nextpg = (struct eth_rx_cqe_next_page *) | |
993 | &fp->rx_comp_ring[RCQ_DESC_CNT * i - 1]; | |
994 | nextpg->addr_hi = | |
995 | cpu_to_le32(U64_HI(fp->rx_comp_mapping + | |
996 | BCM_PAGE_SIZE*(i % NUM_RCQ_RINGS))); | |
997 | nextpg->addr_lo = | |
998 | cpu_to_le32(U64_LO(fp->rx_comp_mapping + | |
999 | BCM_PAGE_SIZE*(i % NUM_RCQ_RINGS))); | |
1000 | } | |
1001 | } | |
1002 | ||
b3b83c3f DK |
1003 | /* Returns the number of actually allocated BDs */ |
1004 | static inline int bnx2x_alloc_rx_bds(struct bnx2x_fastpath *fp, | |
1005 | int rx_ring_size) | |
1006 | { | |
1007 | struct bnx2x *bp = fp->bp; | |
1008 | u16 ring_prod, cqe_ring_prod; | |
1009 | int i; | |
1010 | ||
1011 | fp->rx_comp_cons = 0; | |
1012 | cqe_ring_prod = ring_prod = 0; | |
1013 | ||
1014 | /* This routine is called only during fo init so | |
1015 | * fp->eth_q_stats.rx_skb_alloc_failed = 0 | |
1016 | */ | |
1017 | for (i = 0; i < rx_ring_size; i++) { | |
1018 | if (bnx2x_alloc_rx_skb(bp, fp, ring_prod) < 0) { | |
1019 | fp->eth_q_stats.rx_skb_alloc_failed++; | |
1020 | continue; | |
1021 | } | |
1022 | ring_prod = NEXT_RX_IDX(ring_prod); | |
1023 | cqe_ring_prod = NEXT_RCQ_IDX(cqe_ring_prod); | |
1024 | WARN_ON(ring_prod <= (i - fp->eth_q_stats.rx_skb_alloc_failed)); | |
1025 | } | |
1026 | ||
1027 | if (fp->eth_q_stats.rx_skb_alloc_failed) | |
1028 | BNX2X_ERR("was only able to allocate " | |
1029 | "%d rx skbs on queue[%d]\n", | |
1030 | (i - fp->eth_q_stats.rx_skb_alloc_failed), fp->index); | |
1031 | ||
1032 | fp->rx_bd_prod = ring_prod; | |
1033 | /* Limit the CQE producer by the CQE ring size */ | |
1034 | fp->rx_comp_prod = min_t(u16, NUM_RCQ_RINGS*RCQ_DESC_CNT, | |
1035 | cqe_ring_prod); | |
1036 | fp->rx_pkt = fp->rx_calls = 0; | |
1037 | ||
1038 | return i - fp->eth_q_stats.rx_skb_alloc_failed; | |
1039 | } | |
1040 | ||
ec6ba945 VZ |
1041 | #ifdef BCM_CNIC |
1042 | static inline void bnx2x_init_fcoe_fp(struct bnx2x *bp) | |
1043 | { | |
1044 | bnx2x_fcoe(bp, cl_id) = BNX2X_FCOE_ETH_CL_ID + | |
1045 | BP_E1HVN(bp) * NONE_ETH_CONTEXT_USE; | |
1046 | bnx2x_fcoe(bp, cid) = BNX2X_FCOE_ETH_CID; | |
1047 | bnx2x_fcoe(bp, fw_sb_id) = DEF_SB_ID; | |
1048 | bnx2x_fcoe(bp, igu_sb_id) = bp->igu_dsb_id; | |
1049 | bnx2x_fcoe(bp, bp) = bp; | |
1050 | bnx2x_fcoe(bp, state) = BNX2X_FP_STATE_CLOSED; | |
1051 | bnx2x_fcoe(bp, index) = FCOE_IDX; | |
1052 | bnx2x_fcoe(bp, rx_cons_sb) = BNX2X_FCOE_L2_RX_INDEX; | |
1053 | bnx2x_fcoe(bp, tx_cons_sb) = BNX2X_FCOE_L2_TX_INDEX; | |
1054 | /* qZone id equals to FW (per path) client id */ | |
1055 | bnx2x_fcoe(bp, cl_qzone_id) = bnx2x_fcoe(bp, cl_id) + | |
1056 | BP_PORT(bp)*(CHIP_IS_E2(bp) ? ETH_MAX_RX_CLIENTS_E2 : | |
1057 | ETH_MAX_RX_CLIENTS_E1H); | |
1058 | /* init shortcut */ | |
1059 | bnx2x_fcoe(bp, ustorm_rx_prods_offset) = CHIP_IS_E2(bp) ? | |
1060 | USTORM_RX_PRODS_E2_OFFSET(bnx2x_fcoe(bp, cl_qzone_id)) : | |
1061 | USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp), bnx2x_fcoe_fp(bp)->cl_id); | |
523224a3 | 1062 | |
ec6ba945 VZ |
1063 | } |
1064 | #endif | |
523224a3 DK |
1065 | |
1066 | static inline void __storm_memset_struct(struct bnx2x *bp, | |
1067 | u32 addr, size_t size, u32 *data) | |
1068 | { | |
1069 | int i; | |
1070 | for (i = 0; i < size/4; i++) | |
1071 | REG_WR(bp, addr + (i * 4), data[i]); | |
1072 | } | |
1073 | ||
1074 | static inline void storm_memset_mac_filters(struct bnx2x *bp, | |
1075 | struct tstorm_eth_mac_filter_config *mac_filters, | |
1076 | u16 abs_fid) | |
1077 | { | |
1078 | size_t size = sizeof(struct tstorm_eth_mac_filter_config); | |
1079 | ||
1080 | u32 addr = BAR_TSTRORM_INTMEM + | |
1081 | TSTORM_MAC_FILTER_CONFIG_OFFSET(abs_fid); | |
1082 | ||
1083 | __storm_memset_struct(bp, addr, size, (u32 *)mac_filters); | |
1084 | } | |
1085 | ||
1086 | static inline void storm_memset_cmng(struct bnx2x *bp, | |
1087 | struct cmng_struct_per_port *cmng, | |
1088 | u8 port) | |
1089 | { | |
3b7f817e DK |
1090 | size_t size = |
1091 | sizeof(struct rate_shaping_vars_per_port) + | |
1092 | sizeof(struct fairness_vars_per_port) + | |
1093 | sizeof(struct safc_struct_per_port) + | |
1094 | sizeof(struct pfc_struct_per_port); | |
523224a3 DK |
1095 | |
1096 | u32 addr = BAR_XSTRORM_INTMEM + | |
1097 | XSTORM_CMNG_PER_PORT_VARS_OFFSET(port); | |
1098 | ||
1099 | __storm_memset_struct(bp, addr, size, (u32 *)cmng); | |
3b7f817e DK |
1100 | |
1101 | addr += size + 4 /* SKIP DCB+LLFC */; | |
1102 | size = sizeof(struct cmng_struct_per_port) - | |
1103 | size /* written */ - 4 /*skipped*/; | |
1104 | ||
1105 | __storm_memset_struct(bp, addr, size, | |
1106 | (u32 *)(cmng->traffic_type_to_priority_cos)); | |
523224a3 | 1107 | } |
f85582f8 | 1108 | |
9f6c9258 DK |
1109 | /* HW Lock for shared dual port PHYs */ |
1110 | void bnx2x_acquire_phy_lock(struct bnx2x *bp); | |
1111 | void bnx2x_release_phy_lock(struct bnx2x *bp); | |
1112 | ||
faa6fcbb | 1113 | /** |
e8920674 | 1114 | * bnx2x_extract_max_cfg - extract MAX BW part from MF configuration. |
faa6fcbb | 1115 | * |
e8920674 DK |
1116 | * @bp: driver handle |
1117 | * @mf_cfg: MF configuration | |
faa6fcbb | 1118 | * |
faa6fcbb DK |
1119 | */ |
1120 | static inline u16 bnx2x_extract_max_cfg(struct bnx2x *bp, u32 mf_cfg) | |
1121 | { | |
1122 | u16 max_cfg = (mf_cfg & FUNC_MF_CFG_MAX_BW_MASK) >> | |
1123 | FUNC_MF_CFG_MAX_BW_SHIFT; | |
1124 | if (!max_cfg) { | |
1125 | BNX2X_ERR("Illegal configuration detected for Max BW - " | |
1126 | "using 100 instead\n"); | |
1127 | max_cfg = 100; | |
1128 | } | |
1129 | return max_cfg; | |
1130 | } | |
1131 | ||
9f6c9258 | 1132 | #endif /* BNX2X_CMN_H */ |