Commit | Line | Data |
---|---|---|
34f80b04 | 1 | /* bnx2x_main.c: Broadcom Everest network driver. |
a2fbb9ea | 2 | * |
5de92408 | 3 | * Copyright (c) 2007-2011 Broadcom Corporation |
a2fbb9ea ET |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation. | |
8 | * | |
24e3fcef EG |
9 | * Maintained by: Eilon Greenstein <eilong@broadcom.com> |
10 | * Written by: Eliezer Tamir | |
a2fbb9ea ET |
11 | * Based on code from Michael Chan's bnx2 driver |
12 | * UDP CSUM errata workaround by Arik Gendelman | |
ca00392c | 13 | * Slowpath and fastpath rework by Vladislav Zolotarov |
c14423fe | 14 | * Statistics and Link management by Yitchak Gertner |
a2fbb9ea ET |
15 | * |
16 | */ | |
17 | ||
a2fbb9ea ET |
18 | #include <linux/module.h> |
19 | #include <linux/moduleparam.h> | |
20 | #include <linux/kernel.h> | |
21 | #include <linux/device.h> /* for dev_info() */ | |
22 | #include <linux/timer.h> | |
23 | #include <linux/errno.h> | |
24 | #include <linux/ioport.h> | |
25 | #include <linux/slab.h> | |
a2fbb9ea ET |
26 | #include <linux/interrupt.h> |
27 | #include <linux/pci.h> | |
28 | #include <linux/init.h> | |
29 | #include <linux/netdevice.h> | |
30 | #include <linux/etherdevice.h> | |
31 | #include <linux/skbuff.h> | |
32 | #include <linux/dma-mapping.h> | |
33 | #include <linux/bitops.h> | |
34 | #include <linux/irq.h> | |
35 | #include <linux/delay.h> | |
36 | #include <asm/byteorder.h> | |
37 | #include <linux/time.h> | |
38 | #include <linux/ethtool.h> | |
39 | #include <linux/mii.h> | |
0c6671b0 | 40 | #include <linux/if_vlan.h> |
a2fbb9ea | 41 | #include <net/ip.h> |
619c5cb6 | 42 | #include <net/ipv6.h> |
a2fbb9ea ET |
43 | #include <net/tcp.h> |
44 | #include <net/checksum.h> | |
34f80b04 | 45 | #include <net/ip6_checksum.h> |
a2fbb9ea ET |
46 | #include <linux/workqueue.h> |
47 | #include <linux/crc32.h> | |
34f80b04 | 48 | #include <linux/crc32c.h> |
a2fbb9ea ET |
49 | #include <linux/prefetch.h> |
50 | #include <linux/zlib.h> | |
a2fbb9ea | 51 | #include <linux/io.h> |
45229b42 | 52 | #include <linux/stringify.h> |
7ab24bfd | 53 | #include <linux/vmalloc.h> |
a2fbb9ea | 54 | |
a2fbb9ea ET |
55 | #include "bnx2x.h" |
56 | #include "bnx2x_init.h" | |
94a78b79 | 57 | #include "bnx2x_init_ops.h" |
9f6c9258 | 58 | #include "bnx2x_cmn.h" |
e4901dde | 59 | #include "bnx2x_dcb.h" |
042181f5 | 60 | #include "bnx2x_sp.h" |
a2fbb9ea | 61 | |
94a78b79 VZ |
62 | #include <linux/firmware.h> |
63 | #include "bnx2x_fw_file_hdr.h" | |
64 | /* FW files */ | |
45229b42 BH |
65 | #define FW_FILE_VERSION \ |
66 | __stringify(BCM_5710_FW_MAJOR_VERSION) "." \ | |
67 | __stringify(BCM_5710_FW_MINOR_VERSION) "." \ | |
68 | __stringify(BCM_5710_FW_REVISION_VERSION) "." \ | |
69 | __stringify(BCM_5710_FW_ENGINEERING_VERSION) | |
560131f3 DK |
70 | #define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw" |
71 | #define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw" | |
f2e0899f | 72 | #define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw" |
94a78b79 | 73 | |
34f80b04 EG |
74 | /* Time in jiffies before concluding the transmitter is hung */ |
75 | #define TX_TIMEOUT (5*HZ) | |
a2fbb9ea | 76 | |
53a10565 | 77 | static char version[] __devinitdata = |
619c5cb6 | 78 | "Broadcom NetXtreme II 5771x/578xx 10/20-Gigabit Ethernet Driver " |
a2fbb9ea ET |
79 | DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n"; |
80 | ||
24e3fcef | 81 | MODULE_AUTHOR("Eliezer Tamir"); |
f2e0899f | 82 | MODULE_DESCRIPTION("Broadcom NetXtreme II " |
619c5cb6 VZ |
83 | "BCM57710/57711/57711E/" |
84 | "57712/57712_MF/57800/57800_MF/57810/57810_MF/" | |
85 | "57840/57840_MF Driver"); | |
a2fbb9ea ET |
86 | MODULE_LICENSE("GPL"); |
87 | MODULE_VERSION(DRV_MODULE_VERSION); | |
45229b42 BH |
88 | MODULE_FIRMWARE(FW_FILE_NAME_E1); |
89 | MODULE_FIRMWARE(FW_FILE_NAME_E1H); | |
f2e0899f | 90 | MODULE_FIRMWARE(FW_FILE_NAME_E2); |
a2fbb9ea | 91 | |
555f6c78 EG |
92 | static int multi_mode = 1; |
93 | module_param(multi_mode, int, 0); | |
ca00392c EG |
94 | MODULE_PARM_DESC(multi_mode, " Multi queue mode " |
95 | "(0 Disable; 1 Enable (default))"); | |
96 | ||
d6214d7a | 97 | int num_queues; |
54b9ddaa VZ |
98 | module_param(num_queues, int, 0); |
99 | MODULE_PARM_DESC(num_queues, " Number of queues for multi_mode=1" | |
100 | " (default is as a number of CPUs)"); | |
555f6c78 | 101 | |
19680c48 | 102 | static int disable_tpa; |
19680c48 | 103 | module_param(disable_tpa, int, 0); |
9898f86d | 104 | MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature"); |
8badd27a | 105 | |
9ee3d37b DK |
106 | #define INT_MODE_INTx 1 |
107 | #define INT_MODE_MSI 2 | |
8badd27a EG |
108 | static int int_mode; |
109 | module_param(int_mode, int, 0); | |
619c5cb6 | 110 | MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X " |
cdaa7cb8 | 111 | "(1 INT#x; 2 MSI)"); |
8badd27a | 112 | |
a18f5128 EG |
113 | static int dropless_fc; |
114 | module_param(dropless_fc, int, 0); | |
115 | MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring"); | |
116 | ||
9898f86d | 117 | static int poll; |
a2fbb9ea | 118 | module_param(poll, int, 0); |
9898f86d | 119 | MODULE_PARM_DESC(poll, " Use polling (for debug)"); |
8d5726c4 EG |
120 | |
121 | static int mrrs = -1; | |
122 | module_param(mrrs, int, 0); | |
123 | MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)"); | |
124 | ||
9898f86d | 125 | static int debug; |
a2fbb9ea | 126 | module_param(debug, int, 0); |
9898f86d EG |
127 | MODULE_PARM_DESC(debug, " Default debug msglevel"); |
128 | ||
a2fbb9ea | 129 | |
619c5cb6 VZ |
130 | |
131 | struct workqueue_struct *bnx2x_wq; | |
ec6ba945 | 132 | |
a2fbb9ea ET |
133 | enum bnx2x_board_type { |
134 | BCM57710 = 0, | |
619c5cb6 VZ |
135 | BCM57711, |
136 | BCM57711E, | |
137 | BCM57712, | |
138 | BCM57712_MF, | |
139 | BCM57800, | |
140 | BCM57800_MF, | |
141 | BCM57810, | |
142 | BCM57810_MF, | |
143 | BCM57840, | |
144 | BCM57840_MF | |
a2fbb9ea ET |
145 | }; |
146 | ||
34f80b04 | 147 | /* indexed by board_type, above */ |
53a10565 | 148 | static struct { |
a2fbb9ea ET |
149 | char *name; |
150 | } board_info[] __devinitdata = { | |
619c5cb6 VZ |
151 | { "Broadcom NetXtreme II BCM57710 10 Gigabit PCIe [Everest]" }, |
152 | { "Broadcom NetXtreme II BCM57711 10 Gigabit PCIe" }, | |
153 | { "Broadcom NetXtreme II BCM57711E 10 Gigabit PCIe" }, | |
154 | { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet" }, | |
155 | { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Multi Function" }, | |
156 | { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet" }, | |
157 | { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Multi Function" }, | |
158 | { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet" }, | |
159 | { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Multi Function" }, | |
160 | { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet" }, | |
161 | { "Broadcom NetXtreme II BCM57840 10/20 Gigabit " | |
162 | "Ethernet Multi Function"} | |
a2fbb9ea ET |
163 | }; |
164 | ||
619c5cb6 VZ |
165 | #ifndef PCI_DEVICE_ID_NX2_57710 |
166 | #define PCI_DEVICE_ID_NX2_57710 CHIP_NUM_57710 | |
167 | #endif | |
168 | #ifndef PCI_DEVICE_ID_NX2_57711 | |
169 | #define PCI_DEVICE_ID_NX2_57711 CHIP_NUM_57711 | |
170 | #endif | |
171 | #ifndef PCI_DEVICE_ID_NX2_57711E | |
172 | #define PCI_DEVICE_ID_NX2_57711E CHIP_NUM_57711E | |
173 | #endif | |
174 | #ifndef PCI_DEVICE_ID_NX2_57712 | |
175 | #define PCI_DEVICE_ID_NX2_57712 CHIP_NUM_57712 | |
176 | #endif | |
177 | #ifndef PCI_DEVICE_ID_NX2_57712_MF | |
178 | #define PCI_DEVICE_ID_NX2_57712_MF CHIP_NUM_57712_MF | |
179 | #endif | |
180 | #ifndef PCI_DEVICE_ID_NX2_57800 | |
181 | #define PCI_DEVICE_ID_NX2_57800 CHIP_NUM_57800 | |
182 | #endif | |
183 | #ifndef PCI_DEVICE_ID_NX2_57800_MF | |
184 | #define PCI_DEVICE_ID_NX2_57800_MF CHIP_NUM_57800_MF | |
185 | #endif | |
186 | #ifndef PCI_DEVICE_ID_NX2_57810 | |
187 | #define PCI_DEVICE_ID_NX2_57810 CHIP_NUM_57810 | |
188 | #endif | |
189 | #ifndef PCI_DEVICE_ID_NX2_57810_MF | |
190 | #define PCI_DEVICE_ID_NX2_57810_MF CHIP_NUM_57810_MF | |
191 | #endif | |
192 | #ifndef PCI_DEVICE_ID_NX2_57840 | |
193 | #define PCI_DEVICE_ID_NX2_57840 CHIP_NUM_57840 | |
194 | #endif | |
195 | #ifndef PCI_DEVICE_ID_NX2_57840_MF | |
196 | #define PCI_DEVICE_ID_NX2_57840_MF CHIP_NUM_57840_MF | |
197 | #endif | |
a3aa1884 | 198 | static DEFINE_PCI_DEVICE_TABLE(bnx2x_pci_tbl) = { |
e4ed7113 EG |
199 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 }, |
200 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 }, | |
201 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E }, | |
f2e0899f | 202 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 }, |
619c5cb6 VZ |
203 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF }, |
204 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 }, | |
205 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF }, | |
206 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 }, | |
207 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF }, | |
208 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840), BCM57840 }, | |
209 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF }, | |
a2fbb9ea ET |
210 | { 0 } |
211 | }; | |
212 | ||
213 | MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl); | |
214 | ||
215 | /**************************************************************************** | |
216 | * General service functions | |
217 | ****************************************************************************/ | |
218 | ||
619c5cb6 VZ |
219 | static inline void __storm_memset_dma_mapping(struct bnx2x *bp, |
220 | u32 addr, dma_addr_t mapping) | |
221 | { | |
222 | REG_WR(bp, addr, U64_LO(mapping)); | |
223 | REG_WR(bp, addr + 4, U64_HI(mapping)); | |
224 | } | |
225 | ||
226 | static inline void storm_memset_spq_addr(struct bnx2x *bp, | |
227 | dma_addr_t mapping, u16 abs_fid) | |
228 | { | |
229 | u32 addr = XSEM_REG_FAST_MEMORY + | |
230 | XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid); | |
231 | ||
232 | __storm_memset_dma_mapping(bp, addr, mapping); | |
233 | } | |
234 | ||
235 | static inline void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid, | |
236 | u16 pf_id) | |
523224a3 | 237 | { |
619c5cb6 VZ |
238 | REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid), |
239 | pf_id); | |
240 | REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid), | |
241 | pf_id); | |
242 | REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid), | |
243 | pf_id); | |
244 | REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid), | |
245 | pf_id); | |
523224a3 DK |
246 | } |
247 | ||
619c5cb6 VZ |
248 | static inline void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid, |
249 | u8 enable) | |
250 | { | |
251 | REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid), | |
252 | enable); | |
253 | REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid), | |
254 | enable); | |
255 | REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid), | |
256 | enable); | |
257 | REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid), | |
258 | enable); | |
259 | } | |
523224a3 DK |
260 | |
261 | static inline void storm_memset_eq_data(struct bnx2x *bp, | |
262 | struct event_ring_data *eq_data, | |
263 | u16 pfid) | |
264 | { | |
265 | size_t size = sizeof(struct event_ring_data); | |
266 | ||
267 | u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid); | |
268 | ||
269 | __storm_memset_struct(bp, addr, size, (u32 *)eq_data); | |
270 | } | |
271 | ||
272 | static inline void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod, | |
273 | u16 pfid) | |
274 | { | |
275 | u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid); | |
276 | REG_WR16(bp, addr, eq_prod); | |
277 | } | |
278 | ||
a2fbb9ea ET |
279 | /* used only at init |
280 | * locking is done by mcp | |
281 | */ | |
8d96286a | 282 | static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val) |
a2fbb9ea ET |
283 | { |
284 | pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr); | |
285 | pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val); | |
286 | pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, | |
287 | PCICFG_VENDOR_ID_OFFSET); | |
288 | } | |
289 | ||
a2fbb9ea ET |
290 | static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr) |
291 | { | |
292 | u32 val; | |
293 | ||
294 | pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr); | |
295 | pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val); | |
296 | pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, | |
297 | PCICFG_VENDOR_ID_OFFSET); | |
298 | ||
299 | return val; | |
300 | } | |
a2fbb9ea | 301 | |
f2e0899f DK |
302 | #define DMAE_DP_SRC_GRC "grc src_addr [%08x]" |
303 | #define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]" | |
304 | #define DMAE_DP_DST_GRC "grc dst_addr [%08x]" | |
305 | #define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]" | |
306 | #define DMAE_DP_DST_NONE "dst_addr [none]" | |
307 | ||
8d96286a | 308 | static void bnx2x_dp_dmae(struct bnx2x *bp, struct dmae_command *dmae, |
309 | int msglvl) | |
f2e0899f DK |
310 | { |
311 | u32 src_type = dmae->opcode & DMAE_COMMAND_SRC; | |
312 | ||
313 | switch (dmae->opcode & DMAE_COMMAND_DST) { | |
314 | case DMAE_CMD_DST_PCI: | |
315 | if (src_type == DMAE_CMD_SRC_PCI) | |
316 | DP(msglvl, "DMAE: opcode 0x%08x\n" | |
317 | "src [%x:%08x], len [%d*4], dst [%x:%08x]\n" | |
318 | "comp_addr [%x:%08x], comp_val 0x%08x\n", | |
319 | dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo, | |
320 | dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo, | |
321 | dmae->comp_addr_hi, dmae->comp_addr_lo, | |
322 | dmae->comp_val); | |
323 | else | |
324 | DP(msglvl, "DMAE: opcode 0x%08x\n" | |
325 | "src [%08x], len [%d*4], dst [%x:%08x]\n" | |
326 | "comp_addr [%x:%08x], comp_val 0x%08x\n", | |
327 | dmae->opcode, dmae->src_addr_lo >> 2, | |
328 | dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo, | |
329 | dmae->comp_addr_hi, dmae->comp_addr_lo, | |
330 | dmae->comp_val); | |
331 | break; | |
332 | case DMAE_CMD_DST_GRC: | |
333 | if (src_type == DMAE_CMD_SRC_PCI) | |
334 | DP(msglvl, "DMAE: opcode 0x%08x\n" | |
335 | "src [%x:%08x], len [%d*4], dst_addr [%08x]\n" | |
336 | "comp_addr [%x:%08x], comp_val 0x%08x\n", | |
337 | dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo, | |
338 | dmae->len, dmae->dst_addr_lo >> 2, | |
339 | dmae->comp_addr_hi, dmae->comp_addr_lo, | |
340 | dmae->comp_val); | |
341 | else | |
342 | DP(msglvl, "DMAE: opcode 0x%08x\n" | |
343 | "src [%08x], len [%d*4], dst [%08x]\n" | |
344 | "comp_addr [%x:%08x], comp_val 0x%08x\n", | |
345 | dmae->opcode, dmae->src_addr_lo >> 2, | |
346 | dmae->len, dmae->dst_addr_lo >> 2, | |
347 | dmae->comp_addr_hi, dmae->comp_addr_lo, | |
348 | dmae->comp_val); | |
349 | break; | |
350 | default: | |
351 | if (src_type == DMAE_CMD_SRC_PCI) | |
352 | DP(msglvl, "DMAE: opcode 0x%08x\n" | |
353 | DP_LEVEL "src_addr [%x:%08x] len [%d * 4] " | |
354 | "dst_addr [none]\n" | |
355 | DP_LEVEL "comp_addr [%x:%08x] comp_val 0x%08x\n", | |
356 | dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo, | |
357 | dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo, | |
358 | dmae->comp_val); | |
359 | else | |
360 | DP(msglvl, "DMAE: opcode 0x%08x\n" | |
361 | DP_LEVEL "src_addr [%08x] len [%d * 4] " | |
362 | "dst_addr [none]\n" | |
363 | DP_LEVEL "comp_addr [%x:%08x] comp_val 0x%08x\n", | |
364 | dmae->opcode, dmae->src_addr_lo >> 2, | |
365 | dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo, | |
366 | dmae->comp_val); | |
367 | break; | |
368 | } | |
369 | ||
370 | } | |
371 | ||
a2fbb9ea | 372 | /* copy command into DMAE command memory and set DMAE command go */ |
6c719d00 | 373 | void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx) |
a2fbb9ea ET |
374 | { |
375 | u32 cmd_offset; | |
376 | int i; | |
377 | ||
378 | cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx); | |
379 | for (i = 0; i < (sizeof(struct dmae_command)/4); i++) { | |
380 | REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i)); | |
381 | ||
ad8d3948 EG |
382 | DP(BNX2X_MSG_OFF, "DMAE cmd[%d].%d (0x%08x) : 0x%08x\n", |
383 | idx, i, cmd_offset + i*4, *(((u32 *)dmae) + i)); | |
a2fbb9ea ET |
384 | } |
385 | REG_WR(bp, dmae_reg_go_c[idx], 1); | |
386 | } | |
387 | ||
f2e0899f | 388 | u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type) |
a2fbb9ea | 389 | { |
f2e0899f DK |
390 | return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) | |
391 | DMAE_CMD_C_ENABLE); | |
392 | } | |
ad8d3948 | 393 | |
f2e0899f DK |
394 | u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode) |
395 | { | |
396 | return opcode & ~DMAE_CMD_SRC_RESET; | |
397 | } | |
ad8d3948 | 398 | |
f2e0899f DK |
399 | u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type, |
400 | bool with_comp, u8 comp_type) | |
401 | { | |
402 | u32 opcode = 0; | |
403 | ||
404 | opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) | | |
405 | (dst_type << DMAE_COMMAND_DST_SHIFT)); | |
ad8d3948 | 406 | |
f2e0899f DK |
407 | opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET); |
408 | ||
409 | opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0); | |
410 | opcode |= ((BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT) | | |
411 | (BP_E1HVN(bp) << DMAE_COMMAND_DST_VN_SHIFT)); | |
412 | opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT); | |
a2fbb9ea | 413 | |
a2fbb9ea | 414 | #ifdef __BIG_ENDIAN |
f2e0899f | 415 | opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP; |
a2fbb9ea | 416 | #else |
f2e0899f | 417 | opcode |= DMAE_CMD_ENDIANITY_DW_SWAP; |
a2fbb9ea | 418 | #endif |
f2e0899f DK |
419 | if (with_comp) |
420 | opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type); | |
421 | return opcode; | |
422 | } | |
423 | ||
8d96286a | 424 | static void bnx2x_prep_dmae_with_comp(struct bnx2x *bp, |
425 | struct dmae_command *dmae, | |
426 | u8 src_type, u8 dst_type) | |
f2e0899f DK |
427 | { |
428 | memset(dmae, 0, sizeof(struct dmae_command)); | |
429 | ||
430 | /* set the opcode */ | |
431 | dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type, | |
432 | true, DMAE_COMP_PCI); | |
433 | ||
434 | /* fill in the completion parameters */ | |
435 | dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp)); | |
436 | dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp)); | |
437 | dmae->comp_val = DMAE_COMP_VAL; | |
438 | } | |
439 | ||
440 | /* issue a dmae command over the init-channel and wailt for completion */ | |
8d96286a | 441 | static int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, |
442 | struct dmae_command *dmae) | |
f2e0899f DK |
443 | { |
444 | u32 *wb_comp = bnx2x_sp(bp, wb_comp); | |
5e374b5a | 445 | int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000; |
f2e0899f DK |
446 | int rc = 0; |
447 | ||
448 | DP(BNX2X_MSG_OFF, "data before [0x%08x 0x%08x 0x%08x 0x%08x]\n", | |
a2fbb9ea ET |
449 | bp->slowpath->wb_data[0], bp->slowpath->wb_data[1], |
450 | bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]); | |
a2fbb9ea | 451 | |
619c5cb6 VZ |
452 | /* |
453 | * Lock the dmae channel. Disable BHs to prevent a dead-lock | |
454 | * as long as this code is called both from syscall context and | |
455 | * from ndo_set_rx_mode() flow that may be called from BH. | |
456 | */ | |
6e30dd4e | 457 | spin_lock_bh(&bp->dmae_lock); |
5ff7b6d4 | 458 | |
f2e0899f | 459 | /* reset completion */ |
a2fbb9ea ET |
460 | *wb_comp = 0; |
461 | ||
f2e0899f DK |
462 | /* post the command on the channel used for initializations */ |
463 | bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp)); | |
a2fbb9ea | 464 | |
f2e0899f | 465 | /* wait for completion */ |
a2fbb9ea | 466 | udelay(5); |
f2e0899f | 467 | while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) { |
ad8d3948 EG |
468 | DP(BNX2X_MSG_OFF, "wb_comp 0x%08x\n", *wb_comp); |
469 | ||
ad8d3948 | 470 | if (!cnt) { |
c3eefaf6 | 471 | BNX2X_ERR("DMAE timeout!\n"); |
f2e0899f DK |
472 | rc = DMAE_TIMEOUT; |
473 | goto unlock; | |
a2fbb9ea | 474 | } |
ad8d3948 | 475 | cnt--; |
f2e0899f | 476 | udelay(50); |
a2fbb9ea | 477 | } |
f2e0899f DK |
478 | if (*wb_comp & DMAE_PCI_ERR_FLAG) { |
479 | BNX2X_ERR("DMAE PCI error!\n"); | |
480 | rc = DMAE_PCI_ERROR; | |
481 | } | |
482 | ||
483 | DP(BNX2X_MSG_OFF, "data after [0x%08x 0x%08x 0x%08x 0x%08x]\n", | |
484 | bp->slowpath->wb_data[0], bp->slowpath->wb_data[1], | |
485 | bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]); | |
ad8d3948 | 486 | |
f2e0899f | 487 | unlock: |
6e30dd4e | 488 | spin_unlock_bh(&bp->dmae_lock); |
f2e0899f DK |
489 | return rc; |
490 | } | |
491 | ||
492 | void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr, | |
493 | u32 len32) | |
494 | { | |
495 | struct dmae_command dmae; | |
496 | ||
497 | if (!bp->dmae_ready) { | |
498 | u32 *data = bnx2x_sp(bp, wb_data[0]); | |
499 | ||
500 | DP(BNX2X_MSG_OFF, "DMAE is not ready (dst_addr %08x len32 %d)" | |
501 | " using indirect\n", dst_addr, len32); | |
502 | bnx2x_init_ind_wr(bp, dst_addr, data, len32); | |
503 | return; | |
504 | } | |
505 | ||
506 | /* set opcode and fixed command fields */ | |
507 | bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC); | |
508 | ||
509 | /* fill in addresses and len */ | |
510 | dmae.src_addr_lo = U64_LO(dma_addr); | |
511 | dmae.src_addr_hi = U64_HI(dma_addr); | |
512 | dmae.dst_addr_lo = dst_addr >> 2; | |
513 | dmae.dst_addr_hi = 0; | |
514 | dmae.len = len32; | |
515 | ||
516 | bnx2x_dp_dmae(bp, &dmae, BNX2X_MSG_OFF); | |
517 | ||
518 | /* issue the command and wait for completion */ | |
519 | bnx2x_issue_dmae_with_comp(bp, &dmae); | |
a2fbb9ea ET |
520 | } |
521 | ||
c18487ee | 522 | void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32) |
a2fbb9ea | 523 | { |
5ff7b6d4 | 524 | struct dmae_command dmae; |
ad8d3948 EG |
525 | |
526 | if (!bp->dmae_ready) { | |
527 | u32 *data = bnx2x_sp(bp, wb_data[0]); | |
528 | int i; | |
529 | ||
530 | DP(BNX2X_MSG_OFF, "DMAE is not ready (src_addr %08x len32 %d)" | |
531 | " using indirect\n", src_addr, len32); | |
532 | for (i = 0; i < len32; i++) | |
533 | data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4); | |
534 | return; | |
535 | } | |
536 | ||
f2e0899f DK |
537 | /* set opcode and fixed command fields */ |
538 | bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI); | |
a2fbb9ea | 539 | |
f2e0899f | 540 | /* fill in addresses and len */ |
5ff7b6d4 EG |
541 | dmae.src_addr_lo = src_addr >> 2; |
542 | dmae.src_addr_hi = 0; | |
543 | dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data)); | |
544 | dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data)); | |
545 | dmae.len = len32; | |
ad8d3948 | 546 | |
f2e0899f | 547 | bnx2x_dp_dmae(bp, &dmae, BNX2X_MSG_OFF); |
ad8d3948 | 548 | |
f2e0899f DK |
549 | /* issue the command and wait for completion */ |
550 | bnx2x_issue_dmae_with_comp(bp, &dmae); | |
ad8d3948 EG |
551 | } |
552 | ||
8d96286a | 553 | static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr, |
554 | u32 addr, u32 len) | |
573f2035 | 555 | { |
02e3c6cb | 556 | int dmae_wr_max = DMAE_LEN32_WR_MAX(bp); |
573f2035 EG |
557 | int offset = 0; |
558 | ||
02e3c6cb | 559 | while (len > dmae_wr_max) { |
573f2035 | 560 | bnx2x_write_dmae(bp, phys_addr + offset, |
02e3c6cb VZ |
561 | addr + offset, dmae_wr_max); |
562 | offset += dmae_wr_max * 4; | |
563 | len -= dmae_wr_max; | |
573f2035 EG |
564 | } |
565 | ||
566 | bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len); | |
567 | } | |
568 | ||
ad8d3948 EG |
569 | /* used only for slowpath so not inlined */ |
570 | static void bnx2x_wb_wr(struct bnx2x *bp, int reg, u32 val_hi, u32 val_lo) | |
571 | { | |
572 | u32 wb_write[2]; | |
573 | ||
574 | wb_write[0] = val_hi; | |
575 | wb_write[1] = val_lo; | |
576 | REG_WR_DMAE(bp, reg, wb_write, 2); | |
a2fbb9ea | 577 | } |
a2fbb9ea | 578 | |
ad8d3948 EG |
579 | #ifdef USE_WB_RD |
580 | static u64 bnx2x_wb_rd(struct bnx2x *bp, int reg) | |
581 | { | |
582 | u32 wb_data[2]; | |
583 | ||
584 | REG_RD_DMAE(bp, reg, wb_data, 2); | |
585 | ||
586 | return HILO_U64(wb_data[0], wb_data[1]); | |
587 | } | |
588 | #endif | |
589 | ||
a2fbb9ea ET |
590 | static int bnx2x_mc_assert(struct bnx2x *bp) |
591 | { | |
a2fbb9ea | 592 | char last_idx; |
34f80b04 EG |
593 | int i, rc = 0; |
594 | u32 row0, row1, row2, row3; | |
595 | ||
596 | /* XSTORM */ | |
597 | last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM + | |
598 | XSTORM_ASSERT_LIST_INDEX_OFFSET); | |
599 | if (last_idx) | |
600 | BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); | |
601 | ||
602 | /* print the asserts */ | |
603 | for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { | |
604 | ||
605 | row0 = REG_RD(bp, BAR_XSTRORM_INTMEM + | |
606 | XSTORM_ASSERT_LIST_OFFSET(i)); | |
607 | row1 = REG_RD(bp, BAR_XSTRORM_INTMEM + | |
608 | XSTORM_ASSERT_LIST_OFFSET(i) + 4); | |
609 | row2 = REG_RD(bp, BAR_XSTRORM_INTMEM + | |
610 | XSTORM_ASSERT_LIST_OFFSET(i) + 8); | |
611 | row3 = REG_RD(bp, BAR_XSTRORM_INTMEM + | |
612 | XSTORM_ASSERT_LIST_OFFSET(i) + 12); | |
613 | ||
614 | if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { | |
615 | BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x" | |
616 | " 0x%08x 0x%08x 0x%08x\n", | |
617 | i, row3, row2, row1, row0); | |
618 | rc++; | |
619 | } else { | |
620 | break; | |
621 | } | |
622 | } | |
623 | ||
624 | /* TSTORM */ | |
625 | last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM + | |
626 | TSTORM_ASSERT_LIST_INDEX_OFFSET); | |
627 | if (last_idx) | |
628 | BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); | |
629 | ||
630 | /* print the asserts */ | |
631 | for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { | |
632 | ||
633 | row0 = REG_RD(bp, BAR_TSTRORM_INTMEM + | |
634 | TSTORM_ASSERT_LIST_OFFSET(i)); | |
635 | row1 = REG_RD(bp, BAR_TSTRORM_INTMEM + | |
636 | TSTORM_ASSERT_LIST_OFFSET(i) + 4); | |
637 | row2 = REG_RD(bp, BAR_TSTRORM_INTMEM + | |
638 | TSTORM_ASSERT_LIST_OFFSET(i) + 8); | |
639 | row3 = REG_RD(bp, BAR_TSTRORM_INTMEM + | |
640 | TSTORM_ASSERT_LIST_OFFSET(i) + 12); | |
641 | ||
642 | if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { | |
643 | BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x" | |
644 | " 0x%08x 0x%08x 0x%08x\n", | |
645 | i, row3, row2, row1, row0); | |
646 | rc++; | |
647 | } else { | |
648 | break; | |
649 | } | |
650 | } | |
651 | ||
652 | /* CSTORM */ | |
653 | last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM + | |
654 | CSTORM_ASSERT_LIST_INDEX_OFFSET); | |
655 | if (last_idx) | |
656 | BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); | |
657 | ||
658 | /* print the asserts */ | |
659 | for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { | |
660 | ||
661 | row0 = REG_RD(bp, BAR_CSTRORM_INTMEM + | |
662 | CSTORM_ASSERT_LIST_OFFSET(i)); | |
663 | row1 = REG_RD(bp, BAR_CSTRORM_INTMEM + | |
664 | CSTORM_ASSERT_LIST_OFFSET(i) + 4); | |
665 | row2 = REG_RD(bp, BAR_CSTRORM_INTMEM + | |
666 | CSTORM_ASSERT_LIST_OFFSET(i) + 8); | |
667 | row3 = REG_RD(bp, BAR_CSTRORM_INTMEM + | |
668 | CSTORM_ASSERT_LIST_OFFSET(i) + 12); | |
669 | ||
670 | if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { | |
671 | BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x" | |
672 | " 0x%08x 0x%08x 0x%08x\n", | |
673 | i, row3, row2, row1, row0); | |
674 | rc++; | |
675 | } else { | |
676 | break; | |
677 | } | |
678 | } | |
679 | ||
680 | /* USTORM */ | |
681 | last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM + | |
682 | USTORM_ASSERT_LIST_INDEX_OFFSET); | |
683 | if (last_idx) | |
684 | BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); | |
685 | ||
686 | /* print the asserts */ | |
687 | for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { | |
688 | ||
689 | row0 = REG_RD(bp, BAR_USTRORM_INTMEM + | |
690 | USTORM_ASSERT_LIST_OFFSET(i)); | |
691 | row1 = REG_RD(bp, BAR_USTRORM_INTMEM + | |
692 | USTORM_ASSERT_LIST_OFFSET(i) + 4); | |
693 | row2 = REG_RD(bp, BAR_USTRORM_INTMEM + | |
694 | USTORM_ASSERT_LIST_OFFSET(i) + 8); | |
695 | row3 = REG_RD(bp, BAR_USTRORM_INTMEM + | |
696 | USTORM_ASSERT_LIST_OFFSET(i) + 12); | |
697 | ||
698 | if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { | |
699 | BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x" | |
700 | " 0x%08x 0x%08x 0x%08x\n", | |
701 | i, row3, row2, row1, row0); | |
702 | rc++; | |
703 | } else { | |
704 | break; | |
a2fbb9ea ET |
705 | } |
706 | } | |
34f80b04 | 707 | |
a2fbb9ea ET |
708 | return rc; |
709 | } | |
c14423fe | 710 | |
7a25cc73 | 711 | void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl) |
a2fbb9ea | 712 | { |
7a25cc73 | 713 | u32 addr, val; |
a2fbb9ea | 714 | u32 mark, offset; |
4781bfad | 715 | __be32 data[9]; |
a2fbb9ea | 716 | int word; |
f2e0899f | 717 | u32 trace_shmem_base; |
2145a920 VZ |
718 | if (BP_NOMCP(bp)) { |
719 | BNX2X_ERR("NO MCP - can not dump\n"); | |
720 | return; | |
721 | } | |
7a25cc73 DK |
722 | netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n", |
723 | (bp->common.bc_ver & 0xff0000) >> 16, | |
724 | (bp->common.bc_ver & 0xff00) >> 8, | |
725 | (bp->common.bc_ver & 0xff)); | |
726 | ||
727 | val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER); | |
728 | if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER)) | |
729 | printk("%s" "MCP PC at 0x%x\n", lvl, val); | |
cdaa7cb8 | 730 | |
f2e0899f DK |
731 | if (BP_PATH(bp) == 0) |
732 | trace_shmem_base = bp->common.shmem_base; | |
733 | else | |
734 | trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr); | |
735 | addr = trace_shmem_base - 0x0800 + 4; | |
cdaa7cb8 | 736 | mark = REG_RD(bp, addr); |
f2e0899f DK |
737 | mark = (CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH) |
738 | + ((mark + 0x3) & ~0x3) - 0x08000000; | |
7a25cc73 | 739 | printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark); |
a2fbb9ea | 740 | |
7a25cc73 | 741 | printk("%s", lvl); |
f2e0899f | 742 | for (offset = mark; offset <= trace_shmem_base; offset += 0x8*4) { |
a2fbb9ea | 743 | for (word = 0; word < 8; word++) |
cdaa7cb8 | 744 | data[word] = htonl(REG_RD(bp, offset + 4*word)); |
a2fbb9ea | 745 | data[8] = 0x0; |
7995c64e | 746 | pr_cont("%s", (char *)data); |
a2fbb9ea | 747 | } |
cdaa7cb8 | 748 | for (offset = addr + 4; offset <= mark; offset += 0x8*4) { |
a2fbb9ea | 749 | for (word = 0; word < 8; word++) |
cdaa7cb8 | 750 | data[word] = htonl(REG_RD(bp, offset + 4*word)); |
a2fbb9ea | 751 | data[8] = 0x0; |
7995c64e | 752 | pr_cont("%s", (char *)data); |
a2fbb9ea | 753 | } |
7a25cc73 DK |
754 | printk("%s" "end of fw dump\n", lvl); |
755 | } | |
756 | ||
757 | static inline void bnx2x_fw_dump(struct bnx2x *bp) | |
758 | { | |
759 | bnx2x_fw_dump_lvl(bp, KERN_ERR); | |
a2fbb9ea ET |
760 | } |
761 | ||
6c719d00 | 762 | void bnx2x_panic_dump(struct bnx2x *bp) |
a2fbb9ea ET |
763 | { |
764 | int i; | |
523224a3 DK |
765 | u16 j; |
766 | struct hc_sp_status_block_data sp_sb_data; | |
767 | int func = BP_FUNC(bp); | |
768 | #ifdef BNX2X_STOP_ON_ERROR | |
769 | u16 start = 0, end = 0; | |
6383c0b3 | 770 | u8 cos; |
523224a3 | 771 | #endif |
a2fbb9ea | 772 | |
66e855f3 YG |
773 | bp->stats_state = STATS_STATE_DISABLED; |
774 | DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n"); | |
775 | ||
a2fbb9ea ET |
776 | BNX2X_ERR("begin crash dump -----------------\n"); |
777 | ||
8440d2b6 EG |
778 | /* Indices */ |
779 | /* Common */ | |
523224a3 | 780 | BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x)" |
619c5cb6 VZ |
781 | " spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n", |
782 | bp->def_idx, bp->def_att_idx, bp->attn_state, | |
783 | bp->spq_prod_idx, bp->stats_counter); | |
523224a3 DK |
784 | BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n", |
785 | bp->def_status_blk->atten_status_block.attn_bits, | |
786 | bp->def_status_blk->atten_status_block.attn_bits_ack, | |
787 | bp->def_status_blk->atten_status_block.status_block_id, | |
788 | bp->def_status_blk->atten_status_block.attn_bits_index); | |
789 | BNX2X_ERR(" def ("); | |
790 | for (i = 0; i < HC_SP_SB_MAX_INDICES; i++) | |
791 | pr_cont("0x%x%s", | |
792 | bp->def_status_blk->sp_sb.index_values[i], | |
793 | (i == HC_SP_SB_MAX_INDICES - 1) ? ") " : " "); | |
794 | ||
795 | for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++) | |
796 | *((u32 *)&sp_sb_data + i) = REG_RD(bp, BAR_CSTRORM_INTMEM + | |
797 | CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) + | |
798 | i*sizeof(u32)); | |
799 | ||
619c5cb6 | 800 | pr_cont("igu_sb_id(0x%x) igu_seg_id(0x%x) " |
523224a3 | 801 | "pf_id(0x%x) vnic_id(0x%x) " |
619c5cb6 VZ |
802 | "vf_id(0x%x) vf_valid (0x%x) " |
803 | "state(0x%x)\n", | |
523224a3 DK |
804 | sp_sb_data.igu_sb_id, |
805 | sp_sb_data.igu_seg_id, | |
806 | sp_sb_data.p_func.pf_id, | |
807 | sp_sb_data.p_func.vnic_id, | |
808 | sp_sb_data.p_func.vf_id, | |
619c5cb6 VZ |
809 | sp_sb_data.p_func.vf_valid, |
810 | sp_sb_data.state); | |
523224a3 | 811 | |
8440d2b6 | 812 | |
ec6ba945 | 813 | for_each_eth_queue(bp, i) { |
a2fbb9ea | 814 | struct bnx2x_fastpath *fp = &bp->fp[i]; |
523224a3 | 815 | int loop; |
f2e0899f | 816 | struct hc_status_block_data_e2 sb_data_e2; |
523224a3 DK |
817 | struct hc_status_block_data_e1x sb_data_e1x; |
818 | struct hc_status_block_sm *hc_sm_p = | |
619c5cb6 VZ |
819 | CHIP_IS_E1x(bp) ? |
820 | sb_data_e1x.common.state_machine : | |
821 | sb_data_e2.common.state_machine; | |
523224a3 | 822 | struct hc_index_data *hc_index_p = |
619c5cb6 VZ |
823 | CHIP_IS_E1x(bp) ? |
824 | sb_data_e1x.index_data : | |
825 | sb_data_e2.index_data; | |
6383c0b3 | 826 | u8 data_size, cos; |
523224a3 | 827 | u32 *sb_data_p; |
6383c0b3 | 828 | struct bnx2x_fp_txdata txdata; |
523224a3 DK |
829 | |
830 | /* Rx */ | |
cdaa7cb8 | 831 | BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x)" |
523224a3 | 832 | " rx_comp_prod(0x%x)" |
cdaa7cb8 | 833 | " rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n", |
8440d2b6 | 834 | i, fp->rx_bd_prod, fp->rx_bd_cons, |
523224a3 | 835 | fp->rx_comp_prod, |
66e855f3 | 836 | fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb)); |
cdaa7cb8 | 837 | BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x)" |
523224a3 | 838 | " fp_hc_idx(0x%x)\n", |
8440d2b6 | 839 | fp->rx_sge_prod, fp->last_max_sge, |
523224a3 | 840 | le16_to_cpu(fp->fp_hc_idx)); |
a2fbb9ea | 841 | |
523224a3 | 842 | /* Tx */ |
6383c0b3 AE |
843 | for_each_cos_in_tx_queue(fp, cos) |
844 | { | |
845 | txdata = fp->txdata[cos]; | |
846 | BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x)" | |
847 | " tx_bd_prod(0x%x) tx_bd_cons(0x%x)" | |
848 | " *tx_cons_sb(0x%x)\n", | |
849 | i, txdata.tx_pkt_prod, | |
850 | txdata.tx_pkt_cons, txdata.tx_bd_prod, | |
851 | txdata.tx_bd_cons, | |
852 | le16_to_cpu(*txdata.tx_cons_sb)); | |
853 | } | |
523224a3 | 854 | |
619c5cb6 VZ |
855 | loop = CHIP_IS_E1x(bp) ? |
856 | HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2; | |
523224a3 DK |
857 | |
858 | /* host sb data */ | |
859 | ||
ec6ba945 VZ |
860 | #ifdef BCM_CNIC |
861 | if (IS_FCOE_FP(fp)) | |
862 | continue; | |
863 | #endif | |
523224a3 DK |
864 | BNX2X_ERR(" run indexes ("); |
865 | for (j = 0; j < HC_SB_MAX_SM; j++) | |
866 | pr_cont("0x%x%s", | |
867 | fp->sb_running_index[j], | |
868 | (j == HC_SB_MAX_SM - 1) ? ")" : " "); | |
869 | ||
870 | BNX2X_ERR(" indexes ("); | |
871 | for (j = 0; j < loop; j++) | |
872 | pr_cont("0x%x%s", | |
873 | fp->sb_index_values[j], | |
874 | (j == loop - 1) ? ")" : " "); | |
875 | /* fw sb data */ | |
619c5cb6 VZ |
876 | data_size = CHIP_IS_E1x(bp) ? |
877 | sizeof(struct hc_status_block_data_e1x) : | |
878 | sizeof(struct hc_status_block_data_e2); | |
523224a3 | 879 | data_size /= sizeof(u32); |
619c5cb6 VZ |
880 | sb_data_p = CHIP_IS_E1x(bp) ? |
881 | (u32 *)&sb_data_e1x : | |
882 | (u32 *)&sb_data_e2; | |
523224a3 DK |
883 | /* copy sb data in here */ |
884 | for (j = 0; j < data_size; j++) | |
885 | *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM + | |
886 | CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) + | |
887 | j * sizeof(u32)); | |
888 | ||
619c5cb6 VZ |
889 | if (!CHIP_IS_E1x(bp)) { |
890 | pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) " | |
891 | "vnic_id(0x%x) same_igu_sb_1b(0x%x) " | |
892 | "state(0x%x)\n", | |
f2e0899f DK |
893 | sb_data_e2.common.p_func.pf_id, |
894 | sb_data_e2.common.p_func.vf_id, | |
895 | sb_data_e2.common.p_func.vf_valid, | |
896 | sb_data_e2.common.p_func.vnic_id, | |
619c5cb6 VZ |
897 | sb_data_e2.common.same_igu_sb_1b, |
898 | sb_data_e2.common.state); | |
f2e0899f | 899 | } else { |
619c5cb6 VZ |
900 | pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) " |
901 | "vnic_id(0x%x) same_igu_sb_1b(0x%x) " | |
902 | "state(0x%x)\n", | |
f2e0899f DK |
903 | sb_data_e1x.common.p_func.pf_id, |
904 | sb_data_e1x.common.p_func.vf_id, | |
905 | sb_data_e1x.common.p_func.vf_valid, | |
906 | sb_data_e1x.common.p_func.vnic_id, | |
619c5cb6 VZ |
907 | sb_data_e1x.common.same_igu_sb_1b, |
908 | sb_data_e1x.common.state); | |
f2e0899f | 909 | } |
523224a3 DK |
910 | |
911 | /* SB_SMs data */ | |
912 | for (j = 0; j < HC_SB_MAX_SM; j++) { | |
913 | pr_cont("SM[%d] __flags (0x%x) " | |
914 | "igu_sb_id (0x%x) igu_seg_id(0x%x) " | |
915 | "time_to_expire (0x%x) " | |
916 | "timer_value(0x%x)\n", j, | |
917 | hc_sm_p[j].__flags, | |
918 | hc_sm_p[j].igu_sb_id, | |
919 | hc_sm_p[j].igu_seg_id, | |
920 | hc_sm_p[j].time_to_expire, | |
921 | hc_sm_p[j].timer_value); | |
922 | } | |
923 | ||
924 | /* Indecies data */ | |
925 | for (j = 0; j < loop; j++) { | |
926 | pr_cont("INDEX[%d] flags (0x%x) " | |
927 | "timeout (0x%x)\n", j, | |
928 | hc_index_p[j].flags, | |
929 | hc_index_p[j].timeout); | |
930 | } | |
8440d2b6 | 931 | } |
a2fbb9ea | 932 | |
523224a3 | 933 | #ifdef BNX2X_STOP_ON_ERROR |
8440d2b6 EG |
934 | /* Rings */ |
935 | /* Rx */ | |
ec6ba945 | 936 | for_each_rx_queue(bp, i) { |
8440d2b6 | 937 | struct bnx2x_fastpath *fp = &bp->fp[i]; |
a2fbb9ea ET |
938 | |
939 | start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10); | |
940 | end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503); | |
8440d2b6 | 941 | for (j = start; j != end; j = RX_BD(j + 1)) { |
a2fbb9ea ET |
942 | u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j]; |
943 | struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j]; | |
944 | ||
c3eefaf6 EG |
945 | BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n", |
946 | i, j, rx_bd[1], rx_bd[0], sw_bd->skb); | |
a2fbb9ea ET |
947 | } |
948 | ||
3196a88a EG |
949 | start = RX_SGE(fp->rx_sge_prod); |
950 | end = RX_SGE(fp->last_max_sge); | |
8440d2b6 | 951 | for (j = start; j != end; j = RX_SGE(j + 1)) { |
7a9b2557 VZ |
952 | u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j]; |
953 | struct sw_rx_page *sw_page = &fp->rx_page_ring[j]; | |
954 | ||
c3eefaf6 EG |
955 | BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n", |
956 | i, j, rx_sge[1], rx_sge[0], sw_page->page); | |
7a9b2557 VZ |
957 | } |
958 | ||
a2fbb9ea ET |
959 | start = RCQ_BD(fp->rx_comp_cons - 10); |
960 | end = RCQ_BD(fp->rx_comp_cons + 503); | |
8440d2b6 | 961 | for (j = start; j != end; j = RCQ_BD(j + 1)) { |
a2fbb9ea ET |
962 | u32 *cqe = (u32 *)&fp->rx_comp_ring[j]; |
963 | ||
c3eefaf6 EG |
964 | BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n", |
965 | i, j, cqe[0], cqe[1], cqe[2], cqe[3]); | |
a2fbb9ea ET |
966 | } |
967 | } | |
968 | ||
8440d2b6 | 969 | /* Tx */ |
ec6ba945 | 970 | for_each_tx_queue(bp, i) { |
8440d2b6 | 971 | struct bnx2x_fastpath *fp = &bp->fp[i]; |
6383c0b3 AE |
972 | for_each_cos_in_tx_queue(fp, cos) { |
973 | struct bnx2x_fp_txdata *txdata = &fp->txdata[cos]; | |
974 | ||
975 | start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10); | |
976 | end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245); | |
977 | for (j = start; j != end; j = TX_BD(j + 1)) { | |
978 | struct sw_tx_bd *sw_bd = | |
979 | &txdata->tx_buf_ring[j]; | |
980 | ||
981 | BNX2X_ERR("fp%d: txdata %d, " | |
982 | "packet[%x]=[%p,%x]\n", | |
983 | i, cos, j, sw_bd->skb, | |
984 | sw_bd->first_bd); | |
985 | } | |
8440d2b6 | 986 | |
6383c0b3 AE |
987 | start = TX_BD(txdata->tx_bd_cons - 10); |
988 | end = TX_BD(txdata->tx_bd_cons + 254); | |
989 | for (j = start; j != end; j = TX_BD(j + 1)) { | |
990 | u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j]; | |
8440d2b6 | 991 | |
6383c0b3 AE |
992 | BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=" |
993 | "[%x:%x:%x:%x]\n", | |
994 | i, cos, j, tx_bd[0], tx_bd[1], | |
995 | tx_bd[2], tx_bd[3]); | |
996 | } | |
8440d2b6 EG |
997 | } |
998 | } | |
523224a3 | 999 | #endif |
34f80b04 | 1000 | bnx2x_fw_dump(bp); |
a2fbb9ea ET |
1001 | bnx2x_mc_assert(bp); |
1002 | BNX2X_ERR("end crash dump -----------------\n"); | |
a2fbb9ea ET |
1003 | } |
1004 | ||
619c5cb6 VZ |
1005 | /* |
1006 | * FLR Support for E2 | |
1007 | * | |
1008 | * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW | |
1009 | * initialization. | |
1010 | */ | |
1011 | #define FLR_WAIT_USEC 10000 /* 10 miliseconds */ | |
1012 | #define FLR_WAIT_INTERAVAL 50 /* usec */ | |
1013 | #define FLR_POLL_CNT (FLR_WAIT_USEC/FLR_WAIT_INTERAVAL) /* 200 */ | |
1014 | ||
1015 | struct pbf_pN_buf_regs { | |
1016 | int pN; | |
1017 | u32 init_crd; | |
1018 | u32 crd; | |
1019 | u32 crd_freed; | |
1020 | }; | |
1021 | ||
1022 | struct pbf_pN_cmd_regs { | |
1023 | int pN; | |
1024 | u32 lines_occup; | |
1025 | u32 lines_freed; | |
1026 | }; | |
1027 | ||
1028 | static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp, | |
1029 | struct pbf_pN_buf_regs *regs, | |
1030 | u32 poll_count) | |
1031 | { | |
1032 | u32 init_crd, crd, crd_start, crd_freed, crd_freed_start; | |
1033 | u32 cur_cnt = poll_count; | |
1034 | ||
1035 | crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed); | |
1036 | crd = crd_start = REG_RD(bp, regs->crd); | |
1037 | init_crd = REG_RD(bp, regs->init_crd); | |
1038 | ||
1039 | DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd); | |
1040 | DP(BNX2X_MSG_SP, "CREDIT[%d] : s:%x\n", regs->pN, crd); | |
1041 | DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed); | |
1042 | ||
1043 | while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) < | |
1044 | (init_crd - crd_start))) { | |
1045 | if (cur_cnt--) { | |
1046 | udelay(FLR_WAIT_INTERAVAL); | |
1047 | crd = REG_RD(bp, regs->crd); | |
1048 | crd_freed = REG_RD(bp, regs->crd_freed); | |
1049 | } else { | |
1050 | DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n", | |
1051 | regs->pN); | |
1052 | DP(BNX2X_MSG_SP, "CREDIT[%d] : c:%x\n", | |
1053 | regs->pN, crd); | |
1054 | DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n", | |
1055 | regs->pN, crd_freed); | |
1056 | break; | |
1057 | } | |
1058 | } | |
1059 | DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n", | |
1060 | poll_count-cur_cnt, FLR_WAIT_INTERAVAL, regs->pN); | |
1061 | } | |
1062 | ||
1063 | static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp, | |
1064 | struct pbf_pN_cmd_regs *regs, | |
1065 | u32 poll_count) | |
1066 | { | |
1067 | u32 occup, to_free, freed, freed_start; | |
1068 | u32 cur_cnt = poll_count; | |
1069 | ||
1070 | occup = to_free = REG_RD(bp, regs->lines_occup); | |
1071 | freed = freed_start = REG_RD(bp, regs->lines_freed); | |
1072 | ||
1073 | DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup); | |
1074 | DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed); | |
1075 | ||
1076 | while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) { | |
1077 | if (cur_cnt--) { | |
1078 | udelay(FLR_WAIT_INTERAVAL); | |
1079 | occup = REG_RD(bp, regs->lines_occup); | |
1080 | freed = REG_RD(bp, regs->lines_freed); | |
1081 | } else { | |
1082 | DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n", | |
1083 | regs->pN); | |
1084 | DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", | |
1085 | regs->pN, occup); | |
1086 | DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", | |
1087 | regs->pN, freed); | |
1088 | break; | |
1089 | } | |
1090 | } | |
1091 | DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n", | |
1092 | poll_count-cur_cnt, FLR_WAIT_INTERAVAL, regs->pN); | |
1093 | } | |
1094 | ||
1095 | static inline u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg, | |
1096 | u32 expected, u32 poll_count) | |
1097 | { | |
1098 | u32 cur_cnt = poll_count; | |
1099 | u32 val; | |
1100 | ||
1101 | while ((val = REG_RD(bp, reg)) != expected && cur_cnt--) | |
1102 | udelay(FLR_WAIT_INTERAVAL); | |
1103 | ||
1104 | return val; | |
1105 | } | |
1106 | ||
1107 | static inline int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg, | |
1108 | char *msg, u32 poll_cnt) | |
1109 | { | |
1110 | u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt); | |
1111 | if (val != 0) { | |
1112 | BNX2X_ERR("%s usage count=%d\n", msg, val); | |
1113 | return 1; | |
1114 | } | |
1115 | return 0; | |
1116 | } | |
1117 | ||
1118 | static u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp) | |
1119 | { | |
1120 | /* adjust polling timeout */ | |
1121 | if (CHIP_REV_IS_EMUL(bp)) | |
1122 | return FLR_POLL_CNT * 2000; | |
1123 | ||
1124 | if (CHIP_REV_IS_FPGA(bp)) | |
1125 | return FLR_POLL_CNT * 120; | |
1126 | ||
1127 | return FLR_POLL_CNT; | |
1128 | } | |
1129 | ||
1130 | static void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count) | |
1131 | { | |
1132 | struct pbf_pN_cmd_regs cmd_regs[] = { | |
1133 | {0, (CHIP_IS_E3B0(bp)) ? | |
1134 | PBF_REG_TQ_OCCUPANCY_Q0 : | |
1135 | PBF_REG_P0_TQ_OCCUPANCY, | |
1136 | (CHIP_IS_E3B0(bp)) ? | |
1137 | PBF_REG_TQ_LINES_FREED_CNT_Q0 : | |
1138 | PBF_REG_P0_TQ_LINES_FREED_CNT}, | |
1139 | {1, (CHIP_IS_E3B0(bp)) ? | |
1140 | PBF_REG_TQ_OCCUPANCY_Q1 : | |
1141 | PBF_REG_P1_TQ_OCCUPANCY, | |
1142 | (CHIP_IS_E3B0(bp)) ? | |
1143 | PBF_REG_TQ_LINES_FREED_CNT_Q1 : | |
1144 | PBF_REG_P1_TQ_LINES_FREED_CNT}, | |
1145 | {4, (CHIP_IS_E3B0(bp)) ? | |
1146 | PBF_REG_TQ_OCCUPANCY_LB_Q : | |
1147 | PBF_REG_P4_TQ_OCCUPANCY, | |
1148 | (CHIP_IS_E3B0(bp)) ? | |
1149 | PBF_REG_TQ_LINES_FREED_CNT_LB_Q : | |
1150 | PBF_REG_P4_TQ_LINES_FREED_CNT} | |
1151 | }; | |
1152 | ||
1153 | struct pbf_pN_buf_regs buf_regs[] = { | |
1154 | {0, (CHIP_IS_E3B0(bp)) ? | |
1155 | PBF_REG_INIT_CRD_Q0 : | |
1156 | PBF_REG_P0_INIT_CRD , | |
1157 | (CHIP_IS_E3B0(bp)) ? | |
1158 | PBF_REG_CREDIT_Q0 : | |
1159 | PBF_REG_P0_CREDIT, | |
1160 | (CHIP_IS_E3B0(bp)) ? | |
1161 | PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 : | |
1162 | PBF_REG_P0_INTERNAL_CRD_FREED_CNT}, | |
1163 | {1, (CHIP_IS_E3B0(bp)) ? | |
1164 | PBF_REG_INIT_CRD_Q1 : | |
1165 | PBF_REG_P1_INIT_CRD, | |
1166 | (CHIP_IS_E3B0(bp)) ? | |
1167 | PBF_REG_CREDIT_Q1 : | |
1168 | PBF_REG_P1_CREDIT, | |
1169 | (CHIP_IS_E3B0(bp)) ? | |
1170 | PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 : | |
1171 | PBF_REG_P1_INTERNAL_CRD_FREED_CNT}, | |
1172 | {4, (CHIP_IS_E3B0(bp)) ? | |
1173 | PBF_REG_INIT_CRD_LB_Q : | |
1174 | PBF_REG_P4_INIT_CRD, | |
1175 | (CHIP_IS_E3B0(bp)) ? | |
1176 | PBF_REG_CREDIT_LB_Q : | |
1177 | PBF_REG_P4_CREDIT, | |
1178 | (CHIP_IS_E3B0(bp)) ? | |
1179 | PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q : | |
1180 | PBF_REG_P4_INTERNAL_CRD_FREED_CNT}, | |
1181 | }; | |
1182 | ||
1183 | int i; | |
1184 | ||
1185 | /* Verify the command queues are flushed P0, P1, P4 */ | |
1186 | for (i = 0; i < ARRAY_SIZE(cmd_regs); i++) | |
1187 | bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count); | |
1188 | ||
1189 | ||
1190 | /* Verify the transmission buffers are flushed P0, P1, P4 */ | |
1191 | for (i = 0; i < ARRAY_SIZE(buf_regs); i++) | |
1192 | bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count); | |
1193 | } | |
1194 | ||
1195 | #define OP_GEN_PARAM(param) \ | |
1196 | (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM) | |
1197 | ||
1198 | #define OP_GEN_TYPE(type) \ | |
1199 | (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE) | |
1200 | ||
1201 | #define OP_GEN_AGG_VECT(index) \ | |
1202 | (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX) | |
1203 | ||
1204 | ||
1205 | static inline int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, | |
1206 | u32 poll_cnt) | |
1207 | { | |
1208 | struct sdm_op_gen op_gen = {0}; | |
1209 | ||
1210 | u32 comp_addr = BAR_CSTRORM_INTMEM + | |
1211 | CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func); | |
1212 | int ret = 0; | |
1213 | ||
1214 | if (REG_RD(bp, comp_addr)) { | |
1215 | BNX2X_ERR("Cleanup complete is not 0\n"); | |
1216 | return 1; | |
1217 | } | |
1218 | ||
1219 | op_gen.command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX); | |
1220 | op_gen.command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE); | |
1221 | op_gen.command |= OP_GEN_AGG_VECT(clnup_func); | |
1222 | op_gen.command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT; | |
1223 | ||
1224 | DP(BNX2X_MSG_SP, "FW Final cleanup\n"); | |
1225 | REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen.command); | |
1226 | ||
1227 | if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) { | |
1228 | BNX2X_ERR("FW final cleanup did not succeed\n"); | |
1229 | ret = 1; | |
1230 | } | |
1231 | /* Zero completion for nxt FLR */ | |
1232 | REG_WR(bp, comp_addr, 0); | |
1233 | ||
1234 | return ret; | |
1235 | } | |
1236 | ||
1237 | static inline u8 bnx2x_is_pcie_pending(struct pci_dev *dev) | |
1238 | { | |
1239 | int pos; | |
1240 | u16 status; | |
1241 | ||
77c98e6a | 1242 | pos = pci_pcie_cap(dev); |
619c5cb6 VZ |
1243 | if (!pos) |
1244 | return false; | |
1245 | ||
1246 | pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &status); | |
1247 | return status & PCI_EXP_DEVSTA_TRPND; | |
1248 | } | |
1249 | ||
1250 | /* PF FLR specific routines | |
1251 | */ | |
1252 | static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt) | |
1253 | { | |
1254 | ||
1255 | /* wait for CFC PF usage-counter to zero (includes all the VFs) */ | |
1256 | if (bnx2x_flr_clnup_poll_hw_counter(bp, | |
1257 | CFC_REG_NUM_LCIDS_INSIDE_PF, | |
1258 | "CFC PF usage counter timed out", | |
1259 | poll_cnt)) | |
1260 | return 1; | |
1261 | ||
1262 | ||
1263 | /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */ | |
1264 | if (bnx2x_flr_clnup_poll_hw_counter(bp, | |
1265 | DORQ_REG_PF_USAGE_CNT, | |
1266 | "DQ PF usage counter timed out", | |
1267 | poll_cnt)) | |
1268 | return 1; | |
1269 | ||
1270 | /* Wait for QM PF usage-counter to zero (until DQ cleanup) */ | |
1271 | if (bnx2x_flr_clnup_poll_hw_counter(bp, | |
1272 | QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp), | |
1273 | "QM PF usage counter timed out", | |
1274 | poll_cnt)) | |
1275 | return 1; | |
1276 | ||
1277 | /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */ | |
1278 | if (bnx2x_flr_clnup_poll_hw_counter(bp, | |
1279 | TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp), | |
1280 | "Timers VNIC usage counter timed out", | |
1281 | poll_cnt)) | |
1282 | return 1; | |
1283 | if (bnx2x_flr_clnup_poll_hw_counter(bp, | |
1284 | TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp), | |
1285 | "Timers NUM_SCANS usage counter timed out", | |
1286 | poll_cnt)) | |
1287 | return 1; | |
1288 | ||
1289 | /* Wait DMAE PF usage counter to zero */ | |
1290 | if (bnx2x_flr_clnup_poll_hw_counter(bp, | |
1291 | dmae_reg_go_c[INIT_DMAE_C(bp)], | |
1292 | "DMAE dommand register timed out", | |
1293 | poll_cnt)) | |
1294 | return 1; | |
1295 | ||
1296 | return 0; | |
1297 | } | |
1298 | ||
1299 | static void bnx2x_hw_enable_status(struct bnx2x *bp) | |
1300 | { | |
1301 | u32 val; | |
1302 | ||
1303 | val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF); | |
1304 | DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val); | |
1305 | ||
1306 | val = REG_RD(bp, PBF_REG_DISABLE_PF); | |
1307 | DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val); | |
1308 | ||
1309 | val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN); | |
1310 | DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val); | |
1311 | ||
1312 | val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN); | |
1313 | DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val); | |
1314 | ||
1315 | val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK); | |
1316 | DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val); | |
1317 | ||
1318 | val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR); | |
1319 | DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val); | |
1320 | ||
1321 | val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR); | |
1322 | DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val); | |
1323 | ||
1324 | val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER); | |
1325 | DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n", | |
1326 | val); | |
1327 | } | |
1328 | ||
1329 | static int bnx2x_pf_flr_clnup(struct bnx2x *bp) | |
1330 | { | |
1331 | u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp); | |
1332 | ||
1333 | DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp)); | |
1334 | ||
1335 | /* Re-enable PF target read access */ | |
1336 | REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); | |
1337 | ||
1338 | /* Poll HW usage counters */ | |
1339 | if (bnx2x_poll_hw_usage_counters(bp, poll_cnt)) | |
1340 | return -EBUSY; | |
1341 | ||
1342 | /* Zero the igu 'trailing edge' and 'leading edge' */ | |
1343 | ||
1344 | /* Send the FW cleanup command */ | |
1345 | if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt)) | |
1346 | return -EBUSY; | |
1347 | ||
1348 | /* ATC cleanup */ | |
1349 | ||
1350 | /* Verify TX hw is flushed */ | |
1351 | bnx2x_tx_hw_flushed(bp, poll_cnt); | |
1352 | ||
1353 | /* Wait 100ms (not adjusted according to platform) */ | |
1354 | msleep(100); | |
1355 | ||
1356 | /* Verify no pending pci transactions */ | |
1357 | if (bnx2x_is_pcie_pending(bp->pdev)) | |
1358 | BNX2X_ERR("PCIE Transactions still pending\n"); | |
1359 | ||
1360 | /* Debug */ | |
1361 | bnx2x_hw_enable_status(bp); | |
1362 | ||
1363 | /* | |
1364 | * Master enable - Due to WB DMAE writes performed before this | |
1365 | * register is re-initialized as part of the regular function init | |
1366 | */ | |
1367 | REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); | |
1368 | ||
1369 | return 0; | |
1370 | } | |
1371 | ||
f2e0899f | 1372 | static void bnx2x_hc_int_enable(struct bnx2x *bp) |
a2fbb9ea | 1373 | { |
34f80b04 | 1374 | int port = BP_PORT(bp); |
a2fbb9ea ET |
1375 | u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0; |
1376 | u32 val = REG_RD(bp, addr); | |
1377 | int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; | |
8badd27a | 1378 | int msi = (bp->flags & USING_MSI_FLAG) ? 1 : 0; |
a2fbb9ea ET |
1379 | |
1380 | if (msix) { | |
8badd27a EG |
1381 | val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | |
1382 | HC_CONFIG_0_REG_INT_LINE_EN_0); | |
a2fbb9ea ET |
1383 | val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | |
1384 | HC_CONFIG_0_REG_ATTN_BIT_EN_0); | |
8badd27a EG |
1385 | } else if (msi) { |
1386 | val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0; | |
1387 | val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | | |
1388 | HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | | |
1389 | HC_CONFIG_0_REG_ATTN_BIT_EN_0); | |
a2fbb9ea ET |
1390 | } else { |
1391 | val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | | |
615f8fd9 | 1392 | HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | |
a2fbb9ea ET |
1393 | HC_CONFIG_0_REG_INT_LINE_EN_0 | |
1394 | HC_CONFIG_0_REG_ATTN_BIT_EN_0); | |
615f8fd9 | 1395 | |
a0fd065c DK |
1396 | if (!CHIP_IS_E1(bp)) { |
1397 | DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n", | |
1398 | val, port, addr); | |
615f8fd9 | 1399 | |
a0fd065c | 1400 | REG_WR(bp, addr, val); |
615f8fd9 | 1401 | |
a0fd065c DK |
1402 | val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0; |
1403 | } | |
a2fbb9ea ET |
1404 | } |
1405 | ||
a0fd065c DK |
1406 | if (CHIP_IS_E1(bp)) |
1407 | REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF); | |
1408 | ||
8badd27a EG |
1409 | DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x) mode %s\n", |
1410 | val, port, addr, (msix ? "MSI-X" : (msi ? "MSI" : "INTx"))); | |
a2fbb9ea ET |
1411 | |
1412 | REG_WR(bp, addr, val); | |
37dbbf32 EG |
1413 | /* |
1414 | * Ensure that HC_CONFIG is written before leading/trailing edge config | |
1415 | */ | |
1416 | mmiowb(); | |
1417 | barrier(); | |
34f80b04 | 1418 | |
f2e0899f | 1419 | if (!CHIP_IS_E1(bp)) { |
34f80b04 | 1420 | /* init leading/trailing edge */ |
fb3bff17 | 1421 | if (IS_MF(bp)) { |
8badd27a | 1422 | val = (0xee0f | (1 << (BP_E1HVN(bp) + 4))); |
34f80b04 | 1423 | if (bp->port.pmf) |
4acac6a5 EG |
1424 | /* enable nig and gpio3 attention */ |
1425 | val |= 0x1100; | |
34f80b04 EG |
1426 | } else |
1427 | val = 0xffff; | |
1428 | ||
1429 | REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val); | |
1430 | REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val); | |
1431 | } | |
37dbbf32 EG |
1432 | |
1433 | /* Make sure that interrupts are indeed enabled from here on */ | |
1434 | mmiowb(); | |
a2fbb9ea ET |
1435 | } |
1436 | ||
f2e0899f DK |
1437 | static void bnx2x_igu_int_enable(struct bnx2x *bp) |
1438 | { | |
1439 | u32 val; | |
1440 | int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; | |
1441 | int msi = (bp->flags & USING_MSI_FLAG) ? 1 : 0; | |
1442 | ||
1443 | val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); | |
1444 | ||
1445 | if (msix) { | |
1446 | val &= ~(IGU_PF_CONF_INT_LINE_EN | | |
1447 | IGU_PF_CONF_SINGLE_ISR_EN); | |
1448 | val |= (IGU_PF_CONF_FUNC_EN | | |
1449 | IGU_PF_CONF_MSI_MSIX_EN | | |
1450 | IGU_PF_CONF_ATTN_BIT_EN); | |
1451 | } else if (msi) { | |
1452 | val &= ~IGU_PF_CONF_INT_LINE_EN; | |
1453 | val |= (IGU_PF_CONF_FUNC_EN | | |
1454 | IGU_PF_CONF_MSI_MSIX_EN | | |
1455 | IGU_PF_CONF_ATTN_BIT_EN | | |
1456 | IGU_PF_CONF_SINGLE_ISR_EN); | |
1457 | } else { | |
1458 | val &= ~IGU_PF_CONF_MSI_MSIX_EN; | |
1459 | val |= (IGU_PF_CONF_FUNC_EN | | |
1460 | IGU_PF_CONF_INT_LINE_EN | | |
1461 | IGU_PF_CONF_ATTN_BIT_EN | | |
1462 | IGU_PF_CONF_SINGLE_ISR_EN); | |
1463 | } | |
1464 | ||
1465 | DP(NETIF_MSG_INTR, "write 0x%x to IGU mode %s\n", | |
1466 | val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx"))); | |
1467 | ||
1468 | REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); | |
1469 | ||
1470 | barrier(); | |
1471 | ||
1472 | /* init leading/trailing edge */ | |
1473 | if (IS_MF(bp)) { | |
1474 | val = (0xee0f | (1 << (BP_E1HVN(bp) + 4))); | |
1475 | if (bp->port.pmf) | |
1476 | /* enable nig and gpio3 attention */ | |
1477 | val |= 0x1100; | |
1478 | } else | |
1479 | val = 0xffff; | |
1480 | ||
1481 | REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val); | |
1482 | REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val); | |
1483 | ||
1484 | /* Make sure that interrupts are indeed enabled from here on */ | |
1485 | mmiowb(); | |
1486 | } | |
1487 | ||
1488 | void bnx2x_int_enable(struct bnx2x *bp) | |
1489 | { | |
1490 | if (bp->common.int_block == INT_BLOCK_HC) | |
1491 | bnx2x_hc_int_enable(bp); | |
1492 | else | |
1493 | bnx2x_igu_int_enable(bp); | |
1494 | } | |
1495 | ||
1496 | static void bnx2x_hc_int_disable(struct bnx2x *bp) | |
a2fbb9ea | 1497 | { |
34f80b04 | 1498 | int port = BP_PORT(bp); |
a2fbb9ea ET |
1499 | u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0; |
1500 | u32 val = REG_RD(bp, addr); | |
1501 | ||
a0fd065c DK |
1502 | /* |
1503 | * in E1 we must use only PCI configuration space to disable | |
1504 | * MSI/MSIX capablility | |
1505 | * It's forbitten to disable IGU_PF_CONF_MSI_MSIX_EN in HC block | |
1506 | */ | |
1507 | if (CHIP_IS_E1(bp)) { | |
1508 | /* Since IGU_PF_CONF_MSI_MSIX_EN still always on | |
1509 | * Use mask register to prevent from HC sending interrupts | |
1510 | * after we exit the function | |
1511 | */ | |
1512 | REG_WR(bp, HC_REG_INT_MASK + port*4, 0); | |
1513 | ||
1514 | val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | | |
1515 | HC_CONFIG_0_REG_INT_LINE_EN_0 | | |
1516 | HC_CONFIG_0_REG_ATTN_BIT_EN_0); | |
1517 | } else | |
1518 | val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | | |
1519 | HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | | |
1520 | HC_CONFIG_0_REG_INT_LINE_EN_0 | | |
1521 | HC_CONFIG_0_REG_ATTN_BIT_EN_0); | |
a2fbb9ea ET |
1522 | |
1523 | DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n", | |
1524 | val, port, addr); | |
1525 | ||
8badd27a EG |
1526 | /* flush all outstanding writes */ |
1527 | mmiowb(); | |
1528 | ||
a2fbb9ea ET |
1529 | REG_WR(bp, addr, val); |
1530 | if (REG_RD(bp, addr) != val) | |
1531 | BNX2X_ERR("BUG! proper val not read from IGU!\n"); | |
1532 | } | |
1533 | ||
f2e0899f DK |
1534 | static void bnx2x_igu_int_disable(struct bnx2x *bp) |
1535 | { | |
1536 | u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); | |
1537 | ||
1538 | val &= ~(IGU_PF_CONF_MSI_MSIX_EN | | |
1539 | IGU_PF_CONF_INT_LINE_EN | | |
1540 | IGU_PF_CONF_ATTN_BIT_EN); | |
1541 | ||
1542 | DP(NETIF_MSG_INTR, "write %x to IGU\n", val); | |
1543 | ||
1544 | /* flush all outstanding writes */ | |
1545 | mmiowb(); | |
1546 | ||
1547 | REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); | |
1548 | if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val) | |
1549 | BNX2X_ERR("BUG! proper val not read from IGU!\n"); | |
1550 | } | |
1551 | ||
6383c0b3 | 1552 | void bnx2x_int_disable(struct bnx2x *bp) |
f2e0899f DK |
1553 | { |
1554 | if (bp->common.int_block == INT_BLOCK_HC) | |
1555 | bnx2x_hc_int_disable(bp); | |
1556 | else | |
1557 | bnx2x_igu_int_disable(bp); | |
1558 | } | |
1559 | ||
9f6c9258 | 1560 | void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw) |
a2fbb9ea | 1561 | { |
a2fbb9ea | 1562 | int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; |
8badd27a | 1563 | int i, offset; |
a2fbb9ea | 1564 | |
f8ef6e44 YG |
1565 | if (disable_hw) |
1566 | /* prevent the HW from sending interrupts */ | |
1567 | bnx2x_int_disable(bp); | |
a2fbb9ea ET |
1568 | |
1569 | /* make sure all ISRs are done */ | |
1570 | if (msix) { | |
8badd27a EG |
1571 | synchronize_irq(bp->msix_table[0].vector); |
1572 | offset = 1; | |
37b091ba MC |
1573 | #ifdef BCM_CNIC |
1574 | offset++; | |
1575 | #endif | |
ec6ba945 | 1576 | for_each_eth_queue(bp, i) |
754a2f52 | 1577 | synchronize_irq(bp->msix_table[offset++].vector); |
a2fbb9ea ET |
1578 | } else |
1579 | synchronize_irq(bp->pdev->irq); | |
1580 | ||
1581 | /* make sure sp_task is not running */ | |
1cf167f2 | 1582 | cancel_delayed_work(&bp->sp_task); |
3deb8167 | 1583 | cancel_delayed_work(&bp->period_task); |
1cf167f2 | 1584 | flush_workqueue(bnx2x_wq); |
a2fbb9ea ET |
1585 | } |
1586 | ||
34f80b04 | 1587 | /* fast path */ |
a2fbb9ea ET |
1588 | |
1589 | /* | |
34f80b04 | 1590 | * General service functions |
a2fbb9ea ET |
1591 | */ |
1592 | ||
72fd0718 VZ |
1593 | /* Return true if succeeded to acquire the lock */ |
1594 | static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource) | |
1595 | { | |
1596 | u32 lock_status; | |
1597 | u32 resource_bit = (1 << resource); | |
1598 | int func = BP_FUNC(bp); | |
1599 | u32 hw_lock_control_reg; | |
1600 | ||
1601 | DP(NETIF_MSG_HW, "Trying to take a lock on resource %d\n", resource); | |
1602 | ||
1603 | /* Validating that the resource is within range */ | |
1604 | if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { | |
1605 | DP(NETIF_MSG_HW, | |
1606 | "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n", | |
1607 | resource, HW_LOCK_MAX_RESOURCE_VALUE); | |
0fdf4d09 | 1608 | return false; |
72fd0718 VZ |
1609 | } |
1610 | ||
1611 | if (func <= 5) | |
1612 | hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8); | |
1613 | else | |
1614 | hw_lock_control_reg = | |
1615 | (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8); | |
1616 | ||
1617 | /* Try to acquire the lock */ | |
1618 | REG_WR(bp, hw_lock_control_reg + 4, resource_bit); | |
1619 | lock_status = REG_RD(bp, hw_lock_control_reg); | |
1620 | if (lock_status & resource_bit) | |
1621 | return true; | |
1622 | ||
1623 | DP(NETIF_MSG_HW, "Failed to get a lock on resource %d\n", resource); | |
1624 | return false; | |
1625 | } | |
1626 | ||
c9ee9206 VZ |
1627 | /** |
1628 | * bnx2x_get_leader_lock_resource - get the recovery leader resource id | |
1629 | * | |
1630 | * @bp: driver handle | |
1631 | * | |
1632 | * Returns the recovery leader resource id according to the engine this function | |
1633 | * belongs to. Currently only only 2 engines is supported. | |
1634 | */ | |
1635 | static inline int bnx2x_get_leader_lock_resource(struct bnx2x *bp) | |
1636 | { | |
1637 | if (BP_PATH(bp)) | |
1638 | return HW_LOCK_RESOURCE_RECOVERY_LEADER_1; | |
1639 | else | |
1640 | return HW_LOCK_RESOURCE_RECOVERY_LEADER_0; | |
1641 | } | |
1642 | ||
1643 | /** | |
1644 | * bnx2x_trylock_leader_lock- try to aquire a leader lock. | |
1645 | * | |
1646 | * @bp: driver handle | |
1647 | * | |
1648 | * Tries to aquire a leader lock for cuurent engine. | |
1649 | */ | |
1650 | static inline bool bnx2x_trylock_leader_lock(struct bnx2x *bp) | |
1651 | { | |
1652 | return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp)); | |
1653 | } | |
1654 | ||
993ac7b5 | 1655 | #ifdef BCM_CNIC |
619c5cb6 | 1656 | static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err); |
993ac7b5 | 1657 | #endif |
3196a88a | 1658 | |
619c5cb6 | 1659 | void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe) |
a2fbb9ea ET |
1660 | { |
1661 | struct bnx2x *bp = fp->bp; | |
1662 | int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data); | |
1663 | int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data); | |
619c5cb6 VZ |
1664 | enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX; |
1665 | struct bnx2x_queue_sp_obj *q_obj = &fp->q_obj; | |
a2fbb9ea | 1666 | |
34f80b04 | 1667 | DP(BNX2X_MSG_SP, |
a2fbb9ea | 1668 | "fp %d cid %d got ramrod #%d state is %x type is %d\n", |
0626b899 | 1669 | fp->index, cid, command, bp->state, |
34f80b04 | 1670 | rr_cqe->ramrod_cqe.ramrod_type); |
a2fbb9ea | 1671 | |
619c5cb6 VZ |
1672 | switch (command) { |
1673 | case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE): | |
1674 | DP(NETIF_MSG_IFUP, "got UPDATE ramrod. CID %d\n", cid); | |
1675 | drv_cmd = BNX2X_Q_CMD_UPDATE; | |
1676 | break; | |
1677 | case (RAMROD_CMD_ID_ETH_CLIENT_SETUP): | |
523224a3 | 1678 | DP(NETIF_MSG_IFUP, "got MULTI[%d] setup ramrod\n", cid); |
619c5cb6 | 1679 | drv_cmd = BNX2X_Q_CMD_SETUP; |
a2fbb9ea ET |
1680 | break; |
1681 | ||
6383c0b3 AE |
1682 | case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP): |
1683 | DP(NETIF_MSG_IFUP, "got MULTI[%d] tx-only setup ramrod\n", cid); | |
1684 | drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY; | |
1685 | break; | |
1686 | ||
619c5cb6 | 1687 | case (RAMROD_CMD_ID_ETH_HALT): |
523224a3 | 1688 | DP(NETIF_MSG_IFDOWN, "got MULTI[%d] halt ramrod\n", cid); |
619c5cb6 | 1689 | drv_cmd = BNX2X_Q_CMD_HALT; |
a2fbb9ea ET |
1690 | break; |
1691 | ||
619c5cb6 | 1692 | case (RAMROD_CMD_ID_ETH_TERMINATE): |
523224a3 | 1693 | DP(NETIF_MSG_IFDOWN, "got MULTI[%d] teminate ramrod\n", cid); |
619c5cb6 | 1694 | drv_cmd = BNX2X_Q_CMD_TERMINATE; |
a2fbb9ea ET |
1695 | break; |
1696 | ||
619c5cb6 VZ |
1697 | case (RAMROD_CMD_ID_ETH_EMPTY): |
1698 | DP(NETIF_MSG_IFDOWN, "got MULTI[%d] empty ramrod\n", cid); | |
1699 | drv_cmd = BNX2X_Q_CMD_EMPTY; | |
993ac7b5 | 1700 | break; |
619c5cb6 VZ |
1701 | |
1702 | default: | |
1703 | BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n", | |
1704 | command, fp->index); | |
1705 | return; | |
523224a3 | 1706 | } |
3196a88a | 1707 | |
619c5cb6 VZ |
1708 | if ((drv_cmd != BNX2X_Q_CMD_MAX) && |
1709 | q_obj->complete_cmd(bp, q_obj, drv_cmd)) | |
1710 | /* q_obj->complete_cmd() failure means that this was | |
1711 | * an unexpected completion. | |
1712 | * | |
1713 | * In this case we don't want to increase the bp->spq_left | |
1714 | * because apparently we haven't sent this command the first | |
1715 | * place. | |
1716 | */ | |
1717 | #ifdef BNX2X_STOP_ON_ERROR | |
1718 | bnx2x_panic(); | |
1719 | #else | |
1720 | return; | |
1721 | #endif | |
1722 | ||
8fe23fbd | 1723 | smp_mb__before_atomic_inc(); |
6e30dd4e | 1724 | atomic_inc(&bp->cq_spq_left); |
619c5cb6 VZ |
1725 | /* push the change in bp->spq_left and towards the memory */ |
1726 | smp_mb__after_atomic_inc(); | |
49d66772 | 1727 | |
523224a3 | 1728 | return; |
a2fbb9ea ET |
1729 | } |
1730 | ||
619c5cb6 VZ |
1731 | void bnx2x_update_rx_prod(struct bnx2x *bp, struct bnx2x_fastpath *fp, |
1732 | u16 bd_prod, u16 rx_comp_prod, u16 rx_sge_prod) | |
1733 | { | |
1734 | u32 start = BAR_USTRORM_INTMEM + fp->ustorm_rx_prods_offset; | |
1735 | ||
1736 | bnx2x_update_rx_prod_gen(bp, fp, bd_prod, rx_comp_prod, rx_sge_prod, | |
1737 | start); | |
1738 | } | |
1739 | ||
9f6c9258 | 1740 | irqreturn_t bnx2x_interrupt(int irq, void *dev_instance) |
a2fbb9ea | 1741 | { |
555f6c78 | 1742 | struct bnx2x *bp = netdev_priv(dev_instance); |
a2fbb9ea | 1743 | u16 status = bnx2x_ack_int(bp); |
34f80b04 | 1744 | u16 mask; |
ca00392c | 1745 | int i; |
6383c0b3 | 1746 | u8 cos; |
a2fbb9ea | 1747 | |
34f80b04 | 1748 | /* Return here if interrupt is shared and it's not for us */ |
a2fbb9ea ET |
1749 | if (unlikely(status == 0)) { |
1750 | DP(NETIF_MSG_INTR, "not our interrupt!\n"); | |
1751 | return IRQ_NONE; | |
1752 | } | |
f5372251 | 1753 | DP(NETIF_MSG_INTR, "got an interrupt status 0x%x\n", status); |
a2fbb9ea | 1754 | |
3196a88a EG |
1755 | #ifdef BNX2X_STOP_ON_ERROR |
1756 | if (unlikely(bp->panic)) | |
1757 | return IRQ_HANDLED; | |
1758 | #endif | |
1759 | ||
ec6ba945 | 1760 | for_each_eth_queue(bp, i) { |
ca00392c | 1761 | struct bnx2x_fastpath *fp = &bp->fp[i]; |
a2fbb9ea | 1762 | |
6383c0b3 | 1763 | mask = 0x2 << (fp->index + CNIC_PRESENT); |
ca00392c | 1764 | if (status & mask) { |
619c5cb6 | 1765 | /* Handle Rx or Tx according to SB id */ |
54b9ddaa | 1766 | prefetch(fp->rx_cons_sb); |
6383c0b3 AE |
1767 | for_each_cos_in_tx_queue(fp, cos) |
1768 | prefetch(fp->txdata[cos].tx_cons_sb); | |
523224a3 | 1769 | prefetch(&fp->sb_running_index[SM_RX_ID]); |
54b9ddaa | 1770 | napi_schedule(&bnx2x_fp(bp, fp->index, napi)); |
ca00392c EG |
1771 | status &= ~mask; |
1772 | } | |
a2fbb9ea ET |
1773 | } |
1774 | ||
993ac7b5 | 1775 | #ifdef BCM_CNIC |
523224a3 | 1776 | mask = 0x2; |
993ac7b5 MC |
1777 | if (status & (mask | 0x1)) { |
1778 | struct cnic_ops *c_ops = NULL; | |
1779 | ||
619c5cb6 VZ |
1780 | if (likely(bp->state == BNX2X_STATE_OPEN)) { |
1781 | rcu_read_lock(); | |
1782 | c_ops = rcu_dereference(bp->cnic_ops); | |
1783 | if (c_ops) | |
1784 | c_ops->cnic_handler(bp->cnic_data, NULL); | |
1785 | rcu_read_unlock(); | |
1786 | } | |
993ac7b5 MC |
1787 | |
1788 | status &= ~mask; | |
1789 | } | |
1790 | #endif | |
a2fbb9ea | 1791 | |
34f80b04 | 1792 | if (unlikely(status & 0x1)) { |
1cf167f2 | 1793 | queue_delayed_work(bnx2x_wq, &bp->sp_task, 0); |
a2fbb9ea ET |
1794 | |
1795 | status &= ~0x1; | |
1796 | if (!status) | |
1797 | return IRQ_HANDLED; | |
1798 | } | |
1799 | ||
cdaa7cb8 VZ |
1800 | if (unlikely(status)) |
1801 | DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n", | |
34f80b04 | 1802 | status); |
a2fbb9ea | 1803 | |
c18487ee | 1804 | return IRQ_HANDLED; |
a2fbb9ea ET |
1805 | } |
1806 | ||
c18487ee YR |
1807 | /* Link */ |
1808 | ||
1809 | /* | |
1810 | * General service functions | |
1811 | */ | |
a2fbb9ea | 1812 | |
9f6c9258 | 1813 | int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource) |
c18487ee YR |
1814 | { |
1815 | u32 lock_status; | |
1816 | u32 resource_bit = (1 << resource); | |
4a37fb66 YG |
1817 | int func = BP_FUNC(bp); |
1818 | u32 hw_lock_control_reg; | |
c18487ee | 1819 | int cnt; |
a2fbb9ea | 1820 | |
c18487ee YR |
1821 | /* Validating that the resource is within range */ |
1822 | if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { | |
1823 | DP(NETIF_MSG_HW, | |
1824 | "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n", | |
1825 | resource, HW_LOCK_MAX_RESOURCE_VALUE); | |
1826 | return -EINVAL; | |
1827 | } | |
a2fbb9ea | 1828 | |
4a37fb66 YG |
1829 | if (func <= 5) { |
1830 | hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8); | |
1831 | } else { | |
1832 | hw_lock_control_reg = | |
1833 | (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8); | |
1834 | } | |
1835 | ||
c18487ee | 1836 | /* Validating that the resource is not already taken */ |
4a37fb66 | 1837 | lock_status = REG_RD(bp, hw_lock_control_reg); |
c18487ee YR |
1838 | if (lock_status & resource_bit) { |
1839 | DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n", | |
1840 | lock_status, resource_bit); | |
1841 | return -EEXIST; | |
1842 | } | |
a2fbb9ea | 1843 | |
46230476 EG |
1844 | /* Try for 5 second every 5ms */ |
1845 | for (cnt = 0; cnt < 1000; cnt++) { | |
c18487ee | 1846 | /* Try to acquire the lock */ |
4a37fb66 YG |
1847 | REG_WR(bp, hw_lock_control_reg + 4, resource_bit); |
1848 | lock_status = REG_RD(bp, hw_lock_control_reg); | |
c18487ee YR |
1849 | if (lock_status & resource_bit) |
1850 | return 0; | |
a2fbb9ea | 1851 | |
c18487ee | 1852 | msleep(5); |
a2fbb9ea | 1853 | } |
c18487ee YR |
1854 | DP(NETIF_MSG_HW, "Timeout\n"); |
1855 | return -EAGAIN; | |
1856 | } | |
a2fbb9ea | 1857 | |
c9ee9206 VZ |
1858 | int bnx2x_release_leader_lock(struct bnx2x *bp) |
1859 | { | |
1860 | return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp)); | |
1861 | } | |
1862 | ||
9f6c9258 | 1863 | int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource) |
c18487ee YR |
1864 | { |
1865 | u32 lock_status; | |
1866 | u32 resource_bit = (1 << resource); | |
4a37fb66 YG |
1867 | int func = BP_FUNC(bp); |
1868 | u32 hw_lock_control_reg; | |
a2fbb9ea | 1869 | |
72fd0718 VZ |
1870 | DP(NETIF_MSG_HW, "Releasing a lock on resource %d\n", resource); |
1871 | ||
c18487ee YR |
1872 | /* Validating that the resource is within range */ |
1873 | if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { | |
1874 | DP(NETIF_MSG_HW, | |
1875 | "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n", | |
1876 | resource, HW_LOCK_MAX_RESOURCE_VALUE); | |
1877 | return -EINVAL; | |
1878 | } | |
1879 | ||
4a37fb66 YG |
1880 | if (func <= 5) { |
1881 | hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8); | |
1882 | } else { | |
1883 | hw_lock_control_reg = | |
1884 | (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8); | |
1885 | } | |
1886 | ||
c18487ee | 1887 | /* Validating that the resource is currently taken */ |
4a37fb66 | 1888 | lock_status = REG_RD(bp, hw_lock_control_reg); |
c18487ee YR |
1889 | if (!(lock_status & resource_bit)) { |
1890 | DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n", | |
1891 | lock_status, resource_bit); | |
1892 | return -EFAULT; | |
a2fbb9ea ET |
1893 | } |
1894 | ||
9f6c9258 DK |
1895 | REG_WR(bp, hw_lock_control_reg, resource_bit); |
1896 | return 0; | |
c18487ee | 1897 | } |
a2fbb9ea | 1898 | |
9f6c9258 | 1899 | |
4acac6a5 EG |
1900 | int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port) |
1901 | { | |
1902 | /* The GPIO should be swapped if swap register is set and active */ | |
1903 | int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && | |
1904 | REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; | |
1905 | int gpio_shift = gpio_num + | |
1906 | (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); | |
1907 | u32 gpio_mask = (1 << gpio_shift); | |
1908 | u32 gpio_reg; | |
1909 | int value; | |
1910 | ||
1911 | if (gpio_num > MISC_REGISTERS_GPIO_3) { | |
1912 | BNX2X_ERR("Invalid GPIO %d\n", gpio_num); | |
1913 | return -EINVAL; | |
1914 | } | |
1915 | ||
1916 | /* read GPIO value */ | |
1917 | gpio_reg = REG_RD(bp, MISC_REG_GPIO); | |
1918 | ||
1919 | /* get the requested pin value */ | |
1920 | if ((gpio_reg & gpio_mask) == gpio_mask) | |
1921 | value = 1; | |
1922 | else | |
1923 | value = 0; | |
1924 | ||
1925 | DP(NETIF_MSG_LINK, "pin %d value 0x%x\n", gpio_num, value); | |
1926 | ||
1927 | return value; | |
1928 | } | |
1929 | ||
17de50b7 | 1930 | int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port) |
c18487ee YR |
1931 | { |
1932 | /* The GPIO should be swapped if swap register is set and active */ | |
1933 | int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && | |
17de50b7 | 1934 | REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; |
c18487ee YR |
1935 | int gpio_shift = gpio_num + |
1936 | (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); | |
1937 | u32 gpio_mask = (1 << gpio_shift); | |
1938 | u32 gpio_reg; | |
a2fbb9ea | 1939 | |
c18487ee YR |
1940 | if (gpio_num > MISC_REGISTERS_GPIO_3) { |
1941 | BNX2X_ERR("Invalid GPIO %d\n", gpio_num); | |
1942 | return -EINVAL; | |
1943 | } | |
a2fbb9ea | 1944 | |
4a37fb66 | 1945 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); |
c18487ee YR |
1946 | /* read GPIO and mask except the float bits */ |
1947 | gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT); | |
a2fbb9ea | 1948 | |
c18487ee YR |
1949 | switch (mode) { |
1950 | case MISC_REGISTERS_GPIO_OUTPUT_LOW: | |
1951 | DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output low\n", | |
1952 | gpio_num, gpio_shift); | |
1953 | /* clear FLOAT and set CLR */ | |
1954 | gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); | |
1955 | gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS); | |
1956 | break; | |
a2fbb9ea | 1957 | |
c18487ee YR |
1958 | case MISC_REGISTERS_GPIO_OUTPUT_HIGH: |
1959 | DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output high\n", | |
1960 | gpio_num, gpio_shift); | |
1961 | /* clear FLOAT and set SET */ | |
1962 | gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); | |
1963 | gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS); | |
1964 | break; | |
a2fbb9ea | 1965 | |
17de50b7 | 1966 | case MISC_REGISTERS_GPIO_INPUT_HI_Z: |
c18487ee YR |
1967 | DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> input\n", |
1968 | gpio_num, gpio_shift); | |
1969 | /* set FLOAT */ | |
1970 | gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); | |
1971 | break; | |
a2fbb9ea | 1972 | |
c18487ee YR |
1973 | default: |
1974 | break; | |
a2fbb9ea ET |
1975 | } |
1976 | ||
c18487ee | 1977 | REG_WR(bp, MISC_REG_GPIO, gpio_reg); |
4a37fb66 | 1978 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); |
f1410647 | 1979 | |
c18487ee | 1980 | return 0; |
a2fbb9ea ET |
1981 | } |
1982 | ||
0d40f0d4 YR |
1983 | int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode) |
1984 | { | |
1985 | u32 gpio_reg = 0; | |
1986 | int rc = 0; | |
1987 | ||
1988 | /* Any port swapping should be handled by caller. */ | |
1989 | ||
1990 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); | |
1991 | /* read GPIO and mask except the float bits */ | |
1992 | gpio_reg = REG_RD(bp, MISC_REG_GPIO); | |
1993 | gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS); | |
1994 | gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS); | |
1995 | gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS); | |
1996 | ||
1997 | switch (mode) { | |
1998 | case MISC_REGISTERS_GPIO_OUTPUT_LOW: | |
1999 | DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins); | |
2000 | /* set CLR */ | |
2001 | gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS); | |
2002 | break; | |
2003 | ||
2004 | case MISC_REGISTERS_GPIO_OUTPUT_HIGH: | |
2005 | DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins); | |
2006 | /* set SET */ | |
2007 | gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS); | |
2008 | break; | |
2009 | ||
2010 | case MISC_REGISTERS_GPIO_INPUT_HI_Z: | |
2011 | DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins); | |
2012 | /* set FLOAT */ | |
2013 | gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS); | |
2014 | break; | |
2015 | ||
2016 | default: | |
2017 | BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode); | |
2018 | rc = -EINVAL; | |
2019 | break; | |
2020 | } | |
2021 | ||
2022 | if (rc == 0) | |
2023 | REG_WR(bp, MISC_REG_GPIO, gpio_reg); | |
2024 | ||
2025 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); | |
2026 | ||
2027 | return rc; | |
2028 | } | |
2029 | ||
4acac6a5 EG |
2030 | int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port) |
2031 | { | |
2032 | /* The GPIO should be swapped if swap register is set and active */ | |
2033 | int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && | |
2034 | REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; | |
2035 | int gpio_shift = gpio_num + | |
2036 | (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); | |
2037 | u32 gpio_mask = (1 << gpio_shift); | |
2038 | u32 gpio_reg; | |
2039 | ||
2040 | if (gpio_num > MISC_REGISTERS_GPIO_3) { | |
2041 | BNX2X_ERR("Invalid GPIO %d\n", gpio_num); | |
2042 | return -EINVAL; | |
2043 | } | |
2044 | ||
2045 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); | |
2046 | /* read GPIO int */ | |
2047 | gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT); | |
2048 | ||
2049 | switch (mode) { | |
2050 | case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR: | |
2051 | DP(NETIF_MSG_LINK, "Clear GPIO INT %d (shift %d) -> " | |
2052 | "output low\n", gpio_num, gpio_shift); | |
2053 | /* clear SET and set CLR */ | |
2054 | gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS); | |
2055 | gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS); | |
2056 | break; | |
2057 | ||
2058 | case MISC_REGISTERS_GPIO_INT_OUTPUT_SET: | |
2059 | DP(NETIF_MSG_LINK, "Set GPIO INT %d (shift %d) -> " | |
2060 | "output high\n", gpio_num, gpio_shift); | |
2061 | /* clear CLR and set SET */ | |
2062 | gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS); | |
2063 | gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS); | |
2064 | break; | |
2065 | ||
2066 | default: | |
2067 | break; | |
2068 | } | |
2069 | ||
2070 | REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg); | |
2071 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); | |
2072 | ||
2073 | return 0; | |
2074 | } | |
2075 | ||
c18487ee | 2076 | static int bnx2x_set_spio(struct bnx2x *bp, int spio_num, u32 mode) |
a2fbb9ea | 2077 | { |
c18487ee YR |
2078 | u32 spio_mask = (1 << spio_num); |
2079 | u32 spio_reg; | |
a2fbb9ea | 2080 | |
c18487ee YR |
2081 | if ((spio_num < MISC_REGISTERS_SPIO_4) || |
2082 | (spio_num > MISC_REGISTERS_SPIO_7)) { | |
2083 | BNX2X_ERR("Invalid SPIO %d\n", spio_num); | |
2084 | return -EINVAL; | |
a2fbb9ea ET |
2085 | } |
2086 | ||
4a37fb66 | 2087 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO); |
c18487ee YR |
2088 | /* read SPIO and mask except the float bits */ |
2089 | spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_REGISTERS_SPIO_FLOAT); | |
a2fbb9ea | 2090 | |
c18487ee | 2091 | switch (mode) { |
6378c025 | 2092 | case MISC_REGISTERS_SPIO_OUTPUT_LOW: |
c18487ee YR |
2093 | DP(NETIF_MSG_LINK, "Set SPIO %d -> output low\n", spio_num); |
2094 | /* clear FLOAT and set CLR */ | |
2095 | spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS); | |
2096 | spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_CLR_POS); | |
2097 | break; | |
a2fbb9ea | 2098 | |
6378c025 | 2099 | case MISC_REGISTERS_SPIO_OUTPUT_HIGH: |
c18487ee YR |
2100 | DP(NETIF_MSG_LINK, "Set SPIO %d -> output high\n", spio_num); |
2101 | /* clear FLOAT and set SET */ | |
2102 | spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS); | |
2103 | spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_SET_POS); | |
2104 | break; | |
a2fbb9ea | 2105 | |
c18487ee YR |
2106 | case MISC_REGISTERS_SPIO_INPUT_HI_Z: |
2107 | DP(NETIF_MSG_LINK, "Set SPIO %d -> input\n", spio_num); | |
2108 | /* set FLOAT */ | |
2109 | spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS); | |
2110 | break; | |
a2fbb9ea | 2111 | |
c18487ee YR |
2112 | default: |
2113 | break; | |
a2fbb9ea ET |
2114 | } |
2115 | ||
c18487ee | 2116 | REG_WR(bp, MISC_REG_SPIO, spio_reg); |
4a37fb66 | 2117 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO); |
c18487ee | 2118 | |
a2fbb9ea ET |
2119 | return 0; |
2120 | } | |
2121 | ||
9f6c9258 | 2122 | void bnx2x_calc_fc_adv(struct bnx2x *bp) |
a2fbb9ea | 2123 | { |
a22f0788 | 2124 | u8 cfg_idx = bnx2x_get_link_cfg_idx(bp); |
ad33ea3a EG |
2125 | switch (bp->link_vars.ieee_fc & |
2126 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) { | |
c18487ee | 2127 | case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE: |
a22f0788 | 2128 | bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause | |
f85582f8 | 2129 | ADVERTISED_Pause); |
c18487ee | 2130 | break; |
356e2385 | 2131 | |
c18487ee | 2132 | case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH: |
a22f0788 | 2133 | bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause | |
f85582f8 | 2134 | ADVERTISED_Pause); |
c18487ee | 2135 | break; |
356e2385 | 2136 | |
c18487ee | 2137 | case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC: |
a22f0788 | 2138 | bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause; |
c18487ee | 2139 | break; |
356e2385 | 2140 | |
c18487ee | 2141 | default: |
a22f0788 | 2142 | bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause | |
f85582f8 | 2143 | ADVERTISED_Pause); |
c18487ee YR |
2144 | break; |
2145 | } | |
2146 | } | |
f1410647 | 2147 | |
9f6c9258 | 2148 | u8 bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode) |
c18487ee | 2149 | { |
19680c48 EG |
2150 | if (!BP_NOMCP(bp)) { |
2151 | u8 rc; | |
a22f0788 YR |
2152 | int cfx_idx = bnx2x_get_link_cfg_idx(bp); |
2153 | u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx]; | |
19680c48 | 2154 | /* Initialize link parameters structure variables */ |
8c99e7b0 YR |
2155 | /* It is recommended to turn off RX FC for jumbo frames |
2156 | for better performance */ | |
f2e0899f | 2157 | if ((CHIP_IS_E1x(bp)) && (bp->dev->mtu > 5000)) |
c0700f90 | 2158 | bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX; |
8c99e7b0 | 2159 | else |
c0700f90 | 2160 | bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH; |
a2fbb9ea | 2161 | |
4a37fb66 | 2162 | bnx2x_acquire_phy_lock(bp); |
b5bf9068 | 2163 | |
a22f0788 | 2164 | if (load_mode == LOAD_DIAG) { |
de6eae1f | 2165 | bp->link_params.loopback_mode = LOOPBACK_XGXS; |
a22f0788 YR |
2166 | bp->link_params.req_line_speed[cfx_idx] = SPEED_10000; |
2167 | } | |
b5bf9068 | 2168 | |
19680c48 | 2169 | rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars); |
b5bf9068 | 2170 | |
4a37fb66 | 2171 | bnx2x_release_phy_lock(bp); |
a2fbb9ea | 2172 | |
3c96c68b EG |
2173 | bnx2x_calc_fc_adv(bp); |
2174 | ||
b5bf9068 EG |
2175 | if (CHIP_REV_IS_SLOW(bp) && bp->link_vars.link_up) { |
2176 | bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); | |
19680c48 | 2177 | bnx2x_link_report(bp); |
3deb8167 YR |
2178 | } else |
2179 | queue_delayed_work(bnx2x_wq, &bp->period_task, 0); | |
a22f0788 | 2180 | bp->link_params.req_line_speed[cfx_idx] = req_line_speed; |
19680c48 EG |
2181 | return rc; |
2182 | } | |
f5372251 | 2183 | BNX2X_ERR("Bootcode is missing - can not initialize link\n"); |
19680c48 | 2184 | return -EINVAL; |
a2fbb9ea ET |
2185 | } |
2186 | ||
9f6c9258 | 2187 | void bnx2x_link_set(struct bnx2x *bp) |
a2fbb9ea | 2188 | { |
19680c48 | 2189 | if (!BP_NOMCP(bp)) { |
4a37fb66 | 2190 | bnx2x_acquire_phy_lock(bp); |
54c2fb78 | 2191 | bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1); |
19680c48 | 2192 | bnx2x_phy_init(&bp->link_params, &bp->link_vars); |
4a37fb66 | 2193 | bnx2x_release_phy_lock(bp); |
a2fbb9ea | 2194 | |
19680c48 EG |
2195 | bnx2x_calc_fc_adv(bp); |
2196 | } else | |
f5372251 | 2197 | BNX2X_ERR("Bootcode is missing - can not set link\n"); |
c18487ee | 2198 | } |
a2fbb9ea | 2199 | |
c18487ee YR |
2200 | static void bnx2x__link_reset(struct bnx2x *bp) |
2201 | { | |
19680c48 | 2202 | if (!BP_NOMCP(bp)) { |
4a37fb66 | 2203 | bnx2x_acquire_phy_lock(bp); |
589abe3a | 2204 | bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1); |
4a37fb66 | 2205 | bnx2x_release_phy_lock(bp); |
19680c48 | 2206 | } else |
f5372251 | 2207 | BNX2X_ERR("Bootcode is missing - can not reset link\n"); |
c18487ee | 2208 | } |
a2fbb9ea | 2209 | |
a22f0788 | 2210 | u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes) |
c18487ee | 2211 | { |
2145a920 | 2212 | u8 rc = 0; |
a2fbb9ea | 2213 | |
2145a920 VZ |
2214 | if (!BP_NOMCP(bp)) { |
2215 | bnx2x_acquire_phy_lock(bp); | |
a22f0788 YR |
2216 | rc = bnx2x_test_link(&bp->link_params, &bp->link_vars, |
2217 | is_serdes); | |
2145a920 VZ |
2218 | bnx2x_release_phy_lock(bp); |
2219 | } else | |
2220 | BNX2X_ERR("Bootcode is missing - can not test link\n"); | |
a2fbb9ea | 2221 | |
c18487ee YR |
2222 | return rc; |
2223 | } | |
a2fbb9ea | 2224 | |
8a1c38d1 | 2225 | static void bnx2x_init_port_minmax(struct bnx2x *bp) |
34f80b04 | 2226 | { |
8a1c38d1 EG |
2227 | u32 r_param = bp->link_vars.line_speed / 8; |
2228 | u32 fair_periodic_timeout_usec; | |
2229 | u32 t_fair; | |
34f80b04 | 2230 | |
8a1c38d1 EG |
2231 | memset(&(bp->cmng.rs_vars), 0, |
2232 | sizeof(struct rate_shaping_vars_per_port)); | |
2233 | memset(&(bp->cmng.fair_vars), 0, sizeof(struct fairness_vars_per_port)); | |
34f80b04 | 2234 | |
8a1c38d1 EG |
2235 | /* 100 usec in SDM ticks = 25 since each tick is 4 usec */ |
2236 | bp->cmng.rs_vars.rs_periodic_timeout = RS_PERIODIC_TIMEOUT_USEC / 4; | |
34f80b04 | 2237 | |
8a1c38d1 EG |
2238 | /* this is the threshold below which no timer arming will occur |
2239 | 1.25 coefficient is for the threshold to be a little bigger | |
2240 | than the real time, to compensate for timer in-accuracy */ | |
2241 | bp->cmng.rs_vars.rs_threshold = | |
34f80b04 EG |
2242 | (RS_PERIODIC_TIMEOUT_USEC * r_param * 5) / 4; |
2243 | ||
8a1c38d1 EG |
2244 | /* resolution of fairness timer */ |
2245 | fair_periodic_timeout_usec = QM_ARB_BYTES / r_param; | |
2246 | /* for 10G it is 1000usec. for 1G it is 10000usec. */ | |
2247 | t_fair = T_FAIR_COEF / bp->link_vars.line_speed; | |
34f80b04 | 2248 | |
8a1c38d1 EG |
2249 | /* this is the threshold below which we won't arm the timer anymore */ |
2250 | bp->cmng.fair_vars.fair_threshold = QM_ARB_BYTES; | |
34f80b04 | 2251 | |
8a1c38d1 EG |
2252 | /* we multiply by 1e3/8 to get bytes/msec. |
2253 | We don't want the credits to pass a credit | |
2254 | of the t_fair*FAIR_MEM (algorithm resolution) */ | |
2255 | bp->cmng.fair_vars.upper_bound = r_param * t_fair * FAIR_MEM; | |
2256 | /* since each tick is 4 usec */ | |
2257 | bp->cmng.fair_vars.fairness_timeout = fair_periodic_timeout_usec / 4; | |
34f80b04 EG |
2258 | } |
2259 | ||
2691d51d EG |
2260 | /* Calculates the sum of vn_min_rates. |
2261 | It's needed for further normalizing of the min_rates. | |
2262 | Returns: | |
2263 | sum of vn_min_rates. | |
2264 | or | |
2265 | 0 - if all the min_rates are 0. | |
2266 | In the later case fainess algorithm should be deactivated. | |
2267 | If not all min_rates are zero then those that are zeroes will be set to 1. | |
2268 | */ | |
2269 | static void bnx2x_calc_vn_weight_sum(struct bnx2x *bp) | |
2270 | { | |
2271 | int all_zero = 1; | |
2691d51d EG |
2272 | int vn; |
2273 | ||
2274 | bp->vn_weight_sum = 0; | |
2275 | for (vn = VN_0; vn < E1HVN_MAX; vn++) { | |
f2e0899f | 2276 | u32 vn_cfg = bp->mf_config[vn]; |
2691d51d EG |
2277 | u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >> |
2278 | FUNC_MF_CFG_MIN_BW_SHIFT) * 100; | |
2279 | ||
2280 | /* Skip hidden vns */ | |
2281 | if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) | |
2282 | continue; | |
2283 | ||
2284 | /* If min rate is zero - set it to 1 */ | |
2285 | if (!vn_min_rate) | |
2286 | vn_min_rate = DEF_MIN_RATE; | |
2287 | else | |
2288 | all_zero = 0; | |
2289 | ||
2290 | bp->vn_weight_sum += vn_min_rate; | |
2291 | } | |
2292 | ||
30ae438b DK |
2293 | /* if ETS or all min rates are zeros - disable fairness */ |
2294 | if (BNX2X_IS_ETS_ENABLED(bp)) { | |
2295 | bp->cmng.flags.cmng_enables &= | |
2296 | ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN; | |
2297 | DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n"); | |
2298 | } else if (all_zero) { | |
b015e3d1 EG |
2299 | bp->cmng.flags.cmng_enables &= |
2300 | ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN; | |
2301 | DP(NETIF_MSG_IFUP, "All MIN values are zeroes" | |
2302 | " fairness will be disabled\n"); | |
2303 | } else | |
2304 | bp->cmng.flags.cmng_enables |= | |
2305 | CMNG_FLAGS_PER_PORT_FAIRNESS_VN; | |
2691d51d EG |
2306 | } |
2307 | ||
f2e0899f | 2308 | static void bnx2x_init_vn_minmax(struct bnx2x *bp, int vn) |
34f80b04 EG |
2309 | { |
2310 | struct rate_shaping_vars_per_vn m_rs_vn; | |
2311 | struct fairness_vars_per_vn m_fair_vn; | |
f2e0899f DK |
2312 | u32 vn_cfg = bp->mf_config[vn]; |
2313 | int func = 2*vn + BP_PORT(bp); | |
34f80b04 EG |
2314 | u16 vn_min_rate, vn_max_rate; |
2315 | int i; | |
2316 | ||
2317 | /* If function is hidden - set min and max to zeroes */ | |
2318 | if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) { | |
2319 | vn_min_rate = 0; | |
2320 | vn_max_rate = 0; | |
2321 | ||
2322 | } else { | |
faa6fcbb DK |
2323 | u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg); |
2324 | ||
34f80b04 EG |
2325 | vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >> |
2326 | FUNC_MF_CFG_MIN_BW_SHIFT) * 100; | |
faa6fcbb DK |
2327 | /* If fairness is enabled (not all min rates are zeroes) and |
2328 | if current min rate is zero - set it to 1. | |
2329 | This is a requirement of the algorithm. */ | |
f2e0899f | 2330 | if (bp->vn_weight_sum && (vn_min_rate == 0)) |
34f80b04 | 2331 | vn_min_rate = DEF_MIN_RATE; |
faa6fcbb DK |
2332 | |
2333 | if (IS_MF_SI(bp)) | |
2334 | /* maxCfg in percents of linkspeed */ | |
2335 | vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100; | |
2336 | else | |
2337 | /* maxCfg is absolute in 100Mb units */ | |
2338 | vn_max_rate = maxCfg * 100; | |
34f80b04 | 2339 | } |
f85582f8 | 2340 | |
8a1c38d1 | 2341 | DP(NETIF_MSG_IFUP, |
b015e3d1 | 2342 | "func %d: vn_min_rate %d vn_max_rate %d vn_weight_sum %d\n", |
8a1c38d1 | 2343 | func, vn_min_rate, vn_max_rate, bp->vn_weight_sum); |
34f80b04 EG |
2344 | |
2345 | memset(&m_rs_vn, 0, sizeof(struct rate_shaping_vars_per_vn)); | |
2346 | memset(&m_fair_vn, 0, sizeof(struct fairness_vars_per_vn)); | |
2347 | ||
2348 | /* global vn counter - maximal Mbps for this vn */ | |
2349 | m_rs_vn.vn_counter.rate = vn_max_rate; | |
2350 | ||
2351 | /* quota - number of bytes transmitted in this period */ | |
2352 | m_rs_vn.vn_counter.quota = | |
2353 | (vn_max_rate * RS_PERIODIC_TIMEOUT_USEC) / 8; | |
2354 | ||
8a1c38d1 | 2355 | if (bp->vn_weight_sum) { |
34f80b04 EG |
2356 | /* credit for each period of the fairness algorithm: |
2357 | number of bytes in T_FAIR (the vn share the port rate). | |
8a1c38d1 EG |
2358 | vn_weight_sum should not be larger than 10000, thus |
2359 | T_FAIR_COEF / (8 * vn_weight_sum) will always be greater | |
2360 | than zero */ | |
34f80b04 | 2361 | m_fair_vn.vn_credit_delta = |
cdaa7cb8 VZ |
2362 | max_t(u32, (vn_min_rate * (T_FAIR_COEF / |
2363 | (8 * bp->vn_weight_sum))), | |
ff80ee02 DK |
2364 | (bp->cmng.fair_vars.fair_threshold + |
2365 | MIN_ABOVE_THRESH)); | |
cdaa7cb8 | 2366 | DP(NETIF_MSG_IFUP, "m_fair_vn.vn_credit_delta %d\n", |
34f80b04 EG |
2367 | m_fair_vn.vn_credit_delta); |
2368 | } | |
2369 | ||
34f80b04 EG |
2370 | /* Store it to internal memory */ |
2371 | for (i = 0; i < sizeof(struct rate_shaping_vars_per_vn)/4; i++) | |
2372 | REG_WR(bp, BAR_XSTRORM_INTMEM + | |
2373 | XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func) + i * 4, | |
2374 | ((u32 *)(&m_rs_vn))[i]); | |
2375 | ||
2376 | for (i = 0; i < sizeof(struct fairness_vars_per_vn)/4; i++) | |
2377 | REG_WR(bp, BAR_XSTRORM_INTMEM + | |
2378 | XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func) + i * 4, | |
2379 | ((u32 *)(&m_fair_vn))[i]); | |
2380 | } | |
f85582f8 | 2381 | |
523224a3 DK |
2382 | static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp) |
2383 | { | |
2384 | if (CHIP_REV_IS_SLOW(bp)) | |
2385 | return CMNG_FNS_NONE; | |
fb3bff17 | 2386 | if (IS_MF(bp)) |
523224a3 DK |
2387 | return CMNG_FNS_MINMAX; |
2388 | ||
2389 | return CMNG_FNS_NONE; | |
2390 | } | |
2391 | ||
2ae17f66 | 2392 | void bnx2x_read_mf_cfg(struct bnx2x *bp) |
523224a3 | 2393 | { |
0793f83f | 2394 | int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1); |
523224a3 DK |
2395 | |
2396 | if (BP_NOMCP(bp)) | |
2397 | return; /* what should be the default bvalue in this case */ | |
2398 | ||
0793f83f DK |
2399 | /* For 2 port configuration the absolute function number formula |
2400 | * is: | |
2401 | * abs_func = 2 * vn + BP_PORT + BP_PATH | |
2402 | * | |
2403 | * and there are 4 functions per port | |
2404 | * | |
2405 | * For 4 port configuration it is | |
2406 | * abs_func = 4 * vn + 2 * BP_PORT + BP_PATH | |
2407 | * | |
2408 | * and there are 2 functions per port | |
2409 | */ | |
523224a3 | 2410 | for (vn = VN_0; vn < E1HVN_MAX; vn++) { |
0793f83f DK |
2411 | int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp); |
2412 | ||
2413 | if (func >= E1H_FUNC_MAX) | |
2414 | break; | |
2415 | ||
f2e0899f | 2416 | bp->mf_config[vn] = |
523224a3 DK |
2417 | MF_CFG_RD(bp, func_mf_config[func].config); |
2418 | } | |
2419 | } | |
2420 | ||
2421 | static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type) | |
2422 | { | |
2423 | ||
2424 | if (cmng_type == CMNG_FNS_MINMAX) { | |
2425 | int vn; | |
2426 | ||
2427 | /* clear cmng_enables */ | |
2428 | bp->cmng.flags.cmng_enables = 0; | |
2429 | ||
2430 | /* read mf conf from shmem */ | |
2431 | if (read_cfg) | |
2432 | bnx2x_read_mf_cfg(bp); | |
2433 | ||
2434 | /* Init rate shaping and fairness contexts */ | |
2435 | bnx2x_init_port_minmax(bp); | |
2436 | ||
2437 | /* vn_weight_sum and enable fairness if not 0 */ | |
2438 | bnx2x_calc_vn_weight_sum(bp); | |
2439 | ||
2440 | /* calculate and set min-max rate for each vn */ | |
c4154f25 DK |
2441 | if (bp->port.pmf) |
2442 | for (vn = VN_0; vn < E1HVN_MAX; vn++) | |
2443 | bnx2x_init_vn_minmax(bp, vn); | |
523224a3 DK |
2444 | |
2445 | /* always enable rate shaping and fairness */ | |
2446 | bp->cmng.flags.cmng_enables |= | |
2447 | CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN; | |
2448 | if (!bp->vn_weight_sum) | |
2449 | DP(NETIF_MSG_IFUP, "All MIN values are zeroes" | |
2450 | " fairness will be disabled\n"); | |
2451 | return; | |
2452 | } | |
2453 | ||
2454 | /* rate shaping and fairness are disabled */ | |
2455 | DP(NETIF_MSG_IFUP, | |
2456 | "rate shaping and fairness are disabled\n"); | |
2457 | } | |
34f80b04 | 2458 | |
523224a3 DK |
2459 | static inline void bnx2x_link_sync_notify(struct bnx2x *bp) |
2460 | { | |
2461 | int port = BP_PORT(bp); | |
2462 | int func; | |
2463 | int vn; | |
2464 | ||
2465 | /* Set the attention towards other drivers on the same port */ | |
2466 | for (vn = VN_0; vn < E1HVN_MAX; vn++) { | |
2467 | if (vn == BP_E1HVN(bp)) | |
2468 | continue; | |
2469 | ||
2470 | func = ((vn << 1) | port); | |
2471 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_0 + | |
2472 | (LINK_SYNC_ATTENTION_BIT_FUNC_0 + func)*4, 1); | |
2473 | } | |
2474 | } | |
8a1c38d1 | 2475 | |
c18487ee YR |
2476 | /* This function is called upon link interrupt */ |
2477 | static void bnx2x_link_attn(struct bnx2x *bp) | |
2478 | { | |
bb2a0f7a YG |
2479 | /* Make sure that we are synced with the current statistics */ |
2480 | bnx2x_stats_handle(bp, STATS_EVENT_STOP); | |
2481 | ||
c18487ee | 2482 | bnx2x_link_update(&bp->link_params, &bp->link_vars); |
a2fbb9ea | 2483 | |
bb2a0f7a YG |
2484 | if (bp->link_vars.link_up) { |
2485 | ||
1c06328c | 2486 | /* dropless flow control */ |
f2e0899f | 2487 | if (!CHIP_IS_E1(bp) && bp->dropless_fc) { |
1c06328c EG |
2488 | int port = BP_PORT(bp); |
2489 | u32 pause_enabled = 0; | |
2490 | ||
2491 | if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX) | |
2492 | pause_enabled = 1; | |
2493 | ||
2494 | REG_WR(bp, BAR_USTRORM_INTMEM + | |
ca00392c | 2495 | USTORM_ETH_PAUSE_ENABLED_OFFSET(port), |
1c06328c EG |
2496 | pause_enabled); |
2497 | } | |
2498 | ||
619c5cb6 | 2499 | if (bp->link_vars.mac_type != MAC_TYPE_EMAC) { |
bb2a0f7a YG |
2500 | struct host_port_stats *pstats; |
2501 | ||
2502 | pstats = bnx2x_sp(bp, port_stats); | |
619c5cb6 | 2503 | /* reset old mac stats */ |
bb2a0f7a YG |
2504 | memset(&(pstats->mac_stx[0]), 0, |
2505 | sizeof(struct mac_stx)); | |
2506 | } | |
f34d28ea | 2507 | if (bp->state == BNX2X_STATE_OPEN) |
bb2a0f7a YG |
2508 | bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); |
2509 | } | |
2510 | ||
f2e0899f DK |
2511 | if (bp->link_vars.link_up && bp->link_vars.line_speed) { |
2512 | int cmng_fns = bnx2x_get_cmng_fns_mode(bp); | |
8a1c38d1 | 2513 | |
f2e0899f DK |
2514 | if (cmng_fns != CMNG_FNS_NONE) { |
2515 | bnx2x_cmng_fns_init(bp, false, cmng_fns); | |
2516 | storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); | |
2517 | } else | |
2518 | /* rate shaping and fairness are disabled */ | |
2519 | DP(NETIF_MSG_IFUP, | |
2520 | "single function mode without fairness\n"); | |
34f80b04 | 2521 | } |
9fdc3e95 | 2522 | |
2ae17f66 VZ |
2523 | __bnx2x_link_report(bp); |
2524 | ||
9fdc3e95 DK |
2525 | if (IS_MF(bp)) |
2526 | bnx2x_link_sync_notify(bp); | |
c18487ee | 2527 | } |
a2fbb9ea | 2528 | |
9f6c9258 | 2529 | void bnx2x__link_status_update(struct bnx2x *bp) |
c18487ee | 2530 | { |
2ae17f66 | 2531 | if (bp->state != BNX2X_STATE_OPEN) |
c18487ee | 2532 | return; |
a2fbb9ea | 2533 | |
c18487ee | 2534 | bnx2x_link_status_update(&bp->link_params, &bp->link_vars); |
a2fbb9ea | 2535 | |
bb2a0f7a YG |
2536 | if (bp->link_vars.link_up) |
2537 | bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); | |
2538 | else | |
2539 | bnx2x_stats_handle(bp, STATS_EVENT_STOP); | |
2540 | ||
c18487ee YR |
2541 | /* indicate link status */ |
2542 | bnx2x_link_report(bp); | |
a2fbb9ea | 2543 | } |
a2fbb9ea | 2544 | |
34f80b04 EG |
2545 | static void bnx2x_pmf_update(struct bnx2x *bp) |
2546 | { | |
2547 | int port = BP_PORT(bp); | |
2548 | u32 val; | |
2549 | ||
2550 | bp->port.pmf = 1; | |
2551 | DP(NETIF_MSG_LINK, "pmf %d\n", bp->port.pmf); | |
2552 | ||
3deb8167 YR |
2553 | /* |
2554 | * We need the mb() to ensure the ordering between the writing to | |
2555 | * bp->port.pmf here and reading it from the bnx2x_periodic_task(). | |
2556 | */ | |
2557 | smp_mb(); | |
2558 | ||
2559 | /* queue a periodic task */ | |
2560 | queue_delayed_work(bnx2x_wq, &bp->period_task, 0); | |
2561 | ||
ef01854e DK |
2562 | bnx2x_dcbx_pmf_update(bp); |
2563 | ||
34f80b04 EG |
2564 | /* enable nig attention */ |
2565 | val = (0xff0f | (1 << (BP_E1HVN(bp) + 4))); | |
f2e0899f DK |
2566 | if (bp->common.int_block == INT_BLOCK_HC) { |
2567 | REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val); | |
2568 | REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val); | |
619c5cb6 | 2569 | } else if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
2570 | REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val); |
2571 | REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val); | |
2572 | } | |
bb2a0f7a YG |
2573 | |
2574 | bnx2x_stats_handle(bp, STATS_EVENT_PMF); | |
34f80b04 EG |
2575 | } |
2576 | ||
c18487ee | 2577 | /* end of Link */ |
a2fbb9ea ET |
2578 | |
2579 | /* slow path */ | |
2580 | ||
2581 | /* | |
2582 | * General service functions | |
2583 | */ | |
2584 | ||
2691d51d | 2585 | /* send the MCP a request, block until there is a reply */ |
a22f0788 | 2586 | u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param) |
2691d51d | 2587 | { |
f2e0899f | 2588 | int mb_idx = BP_FW_MB_IDX(bp); |
a5971d43 | 2589 | u32 seq; |
2691d51d EG |
2590 | u32 rc = 0; |
2591 | u32 cnt = 1; | |
2592 | u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10; | |
2593 | ||
c4ff7cbf | 2594 | mutex_lock(&bp->fw_mb_mutex); |
a5971d43 | 2595 | seq = ++bp->fw_seq; |
f2e0899f DK |
2596 | SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param); |
2597 | SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq)); | |
2598 | ||
754a2f52 DK |
2599 | DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n", |
2600 | (command | seq), param); | |
2691d51d EG |
2601 | |
2602 | do { | |
2603 | /* let the FW do it's magic ... */ | |
2604 | msleep(delay); | |
2605 | ||
f2e0899f | 2606 | rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header); |
2691d51d | 2607 | |
c4ff7cbf EG |
2608 | /* Give the FW up to 5 second (500*10ms) */ |
2609 | } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500)); | |
2691d51d EG |
2610 | |
2611 | DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n", | |
2612 | cnt*delay, rc, seq); | |
2613 | ||
2614 | /* is this a reply to our command? */ | |
2615 | if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK)) | |
2616 | rc &= FW_MSG_CODE_MASK; | |
2617 | else { | |
2618 | /* FW BUG! */ | |
2619 | BNX2X_ERR("FW failed to respond!\n"); | |
2620 | bnx2x_fw_dump(bp); | |
2621 | rc = 0; | |
2622 | } | |
c4ff7cbf | 2623 | mutex_unlock(&bp->fw_mb_mutex); |
2691d51d EG |
2624 | |
2625 | return rc; | |
2626 | } | |
2627 | ||
ec6ba945 VZ |
2628 | static u8 stat_counter_valid(struct bnx2x *bp, struct bnx2x_fastpath *fp) |
2629 | { | |
2630 | #ifdef BCM_CNIC | |
619c5cb6 VZ |
2631 | /* Statistics are not supported for CNIC Clients at the moment */ |
2632 | if (IS_FCOE_FP(fp)) | |
ec6ba945 VZ |
2633 | return false; |
2634 | #endif | |
2635 | return true; | |
2636 | } | |
2637 | ||
619c5cb6 VZ |
2638 | void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p) |
2639 | { | |
2640 | if (CHIP_IS_E1x(bp)) { | |
2641 | struct tstorm_eth_function_common_config tcfg = {0}; | |
2642 | ||
2643 | storm_memset_func_cfg(bp, &tcfg, p->func_id); | |
2644 | } | |
2645 | ||
2646 | /* Enable the function in the FW */ | |
2647 | storm_memset_vf_to_pf(bp, p->func_id, p->pf_id); | |
2648 | storm_memset_func_en(bp, p->func_id, 1); | |
2649 | ||
2650 | /* spq */ | |
2651 | if (p->func_flgs & FUNC_FLG_SPQ) { | |
2652 | storm_memset_spq_addr(bp, p->spq_map, p->func_id); | |
2653 | REG_WR(bp, XSEM_REG_FAST_MEMORY + | |
2654 | XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod); | |
2655 | } | |
2656 | } | |
2657 | ||
6383c0b3 AE |
2658 | /** |
2659 | * bnx2x_get_tx_only_flags - Return common flags | |
2660 | * | |
2661 | * @bp device handle | |
2662 | * @fp queue handle | |
2663 | * @zero_stats TRUE if statistics zeroing is needed | |
2664 | * | |
2665 | * Return the flags that are common for the Tx-only and not normal connections. | |
2666 | */ | |
2667 | static inline unsigned long bnx2x_get_common_flags(struct bnx2x *bp, | |
2668 | struct bnx2x_fastpath *fp, | |
2669 | bool zero_stats) | |
28912902 | 2670 | { |
619c5cb6 VZ |
2671 | unsigned long flags = 0; |
2672 | ||
2673 | /* PF driver will always initialize the Queue to an ACTIVE state */ | |
2674 | __set_bit(BNX2X_Q_FLG_ACTIVE, &flags); | |
28912902 | 2675 | |
6383c0b3 AE |
2676 | /* tx only connections collect statistics (on the same index as the |
2677 | * parent connection). The statistics are zeroed when the parent | |
2678 | * connection is initialized. | |
2679 | */ | |
2680 | if (stat_counter_valid(bp, fp)) { | |
2681 | __set_bit(BNX2X_Q_FLG_STATS, &flags); | |
2682 | if (zero_stats) | |
2683 | __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags); | |
2684 | } | |
2685 | ||
2686 | return flags; | |
2687 | } | |
2688 | ||
2689 | static inline unsigned long bnx2x_get_q_flags(struct bnx2x *bp, | |
2690 | struct bnx2x_fastpath *fp, | |
2691 | bool leading) | |
2692 | { | |
2693 | unsigned long flags = 0; | |
2694 | ||
619c5cb6 VZ |
2695 | /* calculate other queue flags */ |
2696 | if (IS_MF_SD(bp)) | |
2697 | __set_bit(BNX2X_Q_FLG_OV, &flags); | |
28912902 | 2698 | |
619c5cb6 VZ |
2699 | if (IS_FCOE_FP(fp)) |
2700 | __set_bit(BNX2X_Q_FLG_FCOE, &flags); | |
523224a3 DK |
2701 | |
2702 | if (!fp->disable_tpa) | |
619c5cb6 VZ |
2703 | __set_bit(BNX2X_Q_FLG_TPA, &flags); |
2704 | ||
619c5cb6 VZ |
2705 | if (leading) { |
2706 | __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags); | |
2707 | __set_bit(BNX2X_Q_FLG_MCAST, &flags); | |
2708 | } | |
523224a3 | 2709 | |
619c5cb6 VZ |
2710 | /* Always set HW VLAN stripping */ |
2711 | __set_bit(BNX2X_Q_FLG_VLAN, &flags); | |
523224a3 | 2712 | |
6383c0b3 AE |
2713 | |
2714 | return flags | bnx2x_get_common_flags(bp, fp, true); | |
523224a3 DK |
2715 | } |
2716 | ||
619c5cb6 | 2717 | static void bnx2x_pf_q_prep_general(struct bnx2x *bp, |
6383c0b3 AE |
2718 | struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init, |
2719 | u8 cos) | |
619c5cb6 VZ |
2720 | { |
2721 | gen_init->stat_id = bnx2x_stats_id(fp); | |
2722 | gen_init->spcl_id = fp->cl_id; | |
2723 | ||
2724 | /* Always use mini-jumbo MTU for FCoE L2 ring */ | |
2725 | if (IS_FCOE_FP(fp)) | |
2726 | gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU; | |
2727 | else | |
2728 | gen_init->mtu = bp->dev->mtu; | |
6383c0b3 AE |
2729 | |
2730 | gen_init->cos = cos; | |
619c5cb6 VZ |
2731 | } |
2732 | ||
2733 | static void bnx2x_pf_rx_q_prep(struct bnx2x *bp, | |
523224a3 | 2734 | struct bnx2x_fastpath *fp, struct rxq_pause_params *pause, |
619c5cb6 | 2735 | struct bnx2x_rxq_setup_params *rxq_init) |
523224a3 | 2736 | { |
619c5cb6 | 2737 | u8 max_sge = 0; |
523224a3 DK |
2738 | u16 sge_sz = 0; |
2739 | u16 tpa_agg_size = 0; | |
2740 | ||
523224a3 DK |
2741 | if (!fp->disable_tpa) { |
2742 | pause->sge_th_hi = 250; | |
2743 | pause->sge_th_lo = 150; | |
2744 | tpa_agg_size = min_t(u32, | |
2745 | (min_t(u32, 8, MAX_SKB_FRAGS) * | |
2746 | SGE_PAGE_SIZE * PAGES_PER_SGE), 0xffff); | |
2747 | max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >> | |
2748 | SGE_PAGE_SHIFT; | |
2749 | max_sge = ((max_sge + PAGES_PER_SGE - 1) & | |
2750 | (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT; | |
2751 | sge_sz = (u16)min_t(u32, SGE_PAGE_SIZE * PAGES_PER_SGE, | |
2752 | 0xffff); | |
2753 | } | |
2754 | ||
2755 | /* pause - not for e1 */ | |
2756 | if (!CHIP_IS_E1(bp)) { | |
2757 | pause->bd_th_hi = 350; | |
2758 | pause->bd_th_lo = 250; | |
2759 | pause->rcq_th_hi = 350; | |
2760 | pause->rcq_th_lo = 250; | |
619c5cb6 | 2761 | |
523224a3 DK |
2762 | pause->pri_map = 1; |
2763 | } | |
2764 | ||
2765 | /* rxq setup */ | |
523224a3 DK |
2766 | rxq_init->dscr_map = fp->rx_desc_mapping; |
2767 | rxq_init->sge_map = fp->rx_sge_mapping; | |
2768 | rxq_init->rcq_map = fp->rx_comp_mapping; | |
2769 | rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE; | |
a8c94b91 | 2770 | |
619c5cb6 VZ |
2771 | /* This should be a maximum number of data bytes that may be |
2772 | * placed on the BD (not including paddings). | |
2773 | */ | |
2774 | rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN - | |
2775 | IP_HEADER_ALIGNMENT_PADDING; | |
a8c94b91 | 2776 | |
523224a3 | 2777 | rxq_init->cl_qzone_id = fp->cl_qzone_id; |
523224a3 DK |
2778 | rxq_init->tpa_agg_sz = tpa_agg_size; |
2779 | rxq_init->sge_buf_sz = sge_sz; | |
2780 | rxq_init->max_sges_pkt = max_sge; | |
619c5cb6 VZ |
2781 | rxq_init->rss_engine_id = BP_FUNC(bp); |
2782 | ||
2783 | /* Maximum number or simultaneous TPA aggregation for this Queue. | |
2784 | * | |
2785 | * For PF Clients it should be the maximum avaliable number. | |
2786 | * VF driver(s) may want to define it to a smaller value. | |
2787 | */ | |
2788 | rxq_init->max_tpa_queues = | |
2789 | (CHIP_IS_E1(bp) ? ETH_MAX_AGGREGATION_QUEUES_E1 : | |
2790 | ETH_MAX_AGGREGATION_QUEUES_E1H_E2); | |
2791 | ||
523224a3 DK |
2792 | rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT; |
2793 | rxq_init->fw_sb_id = fp->fw_sb_id; | |
2794 | ||
ec6ba945 VZ |
2795 | if (IS_FCOE_FP(fp)) |
2796 | rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS; | |
2797 | else | |
6383c0b3 | 2798 | rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS; |
523224a3 DK |
2799 | } |
2800 | ||
619c5cb6 | 2801 | static void bnx2x_pf_tx_q_prep(struct bnx2x *bp, |
6383c0b3 AE |
2802 | struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init, |
2803 | u8 cos) | |
523224a3 | 2804 | { |
6383c0b3 AE |
2805 | txq_init->dscr_map = fp->txdata[cos].tx_desc_mapping; |
2806 | txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos; | |
523224a3 DK |
2807 | txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW; |
2808 | txq_init->fw_sb_id = fp->fw_sb_id; | |
ec6ba945 | 2809 | |
619c5cb6 VZ |
2810 | /* |
2811 | * set the tss leading client id for TX classfication == | |
2812 | * leading RSS client id | |
2813 | */ | |
2814 | txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id); | |
2815 | ||
ec6ba945 VZ |
2816 | if (IS_FCOE_FP(fp)) { |
2817 | txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS; | |
2818 | txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE; | |
2819 | } | |
523224a3 DK |
2820 | } |
2821 | ||
8d96286a | 2822 | static void bnx2x_pf_init(struct bnx2x *bp) |
523224a3 DK |
2823 | { |
2824 | struct bnx2x_func_init_params func_init = {0}; | |
523224a3 DK |
2825 | struct event_ring_data eq_data = { {0} }; |
2826 | u16 flags; | |
2827 | ||
619c5cb6 | 2828 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
2829 | /* reset IGU PF statistics: MSIX + ATTN */ |
2830 | /* PF */ | |
2831 | REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT + | |
2832 | BNX2X_IGU_STAS_MSG_VF_CNT*4 + | |
2833 | (CHIP_MODE_IS_4_PORT(bp) ? | |
2834 | BP_FUNC(bp) : BP_VN(bp))*4, 0); | |
2835 | /* ATTN */ | |
2836 | REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT + | |
2837 | BNX2X_IGU_STAS_MSG_VF_CNT*4 + | |
2838 | BNX2X_IGU_STAS_MSG_PF_CNT*4 + | |
2839 | (CHIP_MODE_IS_4_PORT(bp) ? | |
2840 | BP_FUNC(bp) : BP_VN(bp))*4, 0); | |
2841 | } | |
2842 | ||
523224a3 DK |
2843 | /* function setup flags */ |
2844 | flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ); | |
2845 | ||
619c5cb6 VZ |
2846 | /* This flag is relevant for E1x only. |
2847 | * E2 doesn't have a TPA configuration in a function level. | |
523224a3 | 2848 | */ |
619c5cb6 | 2849 | flags |= (bp->flags & TPA_ENABLE_FLAG) ? FUNC_FLG_TPA : 0; |
523224a3 DK |
2850 | |
2851 | func_init.func_flgs = flags; | |
2852 | func_init.pf_id = BP_FUNC(bp); | |
2853 | func_init.func_id = BP_FUNC(bp); | |
523224a3 DK |
2854 | func_init.spq_map = bp->spq_mapping; |
2855 | func_init.spq_prod = bp->spq_prod_idx; | |
2856 | ||
2857 | bnx2x_func_init(bp, &func_init); | |
2858 | ||
2859 | memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port)); | |
2860 | ||
2861 | /* | |
619c5cb6 VZ |
2862 | * Congestion management values depend on the link rate |
2863 | * There is no active link so initial link rate is set to 10 Gbps. | |
2864 | * When the link comes up The congestion management values are | |
2865 | * re-calculated according to the actual link rate. | |
2866 | */ | |
523224a3 DK |
2867 | bp->link_vars.line_speed = SPEED_10000; |
2868 | bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp)); | |
2869 | ||
2870 | /* Only the PMF sets the HW */ | |
2871 | if (bp->port.pmf) | |
2872 | storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); | |
2873 | ||
523224a3 DK |
2874 | /* init Event Queue */ |
2875 | eq_data.base_addr.hi = U64_HI(bp->eq_mapping); | |
2876 | eq_data.base_addr.lo = U64_LO(bp->eq_mapping); | |
2877 | eq_data.producer = bp->eq_prod; | |
2878 | eq_data.index_id = HC_SP_INDEX_EQ_CONS; | |
2879 | eq_data.sb_id = DEF_SB_ID; | |
2880 | storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp)); | |
2881 | } | |
2882 | ||
2883 | ||
2884 | static void bnx2x_e1h_disable(struct bnx2x *bp) | |
2885 | { | |
2886 | int port = BP_PORT(bp); | |
2887 | ||
619c5cb6 | 2888 | bnx2x_tx_disable(bp); |
523224a3 DK |
2889 | |
2890 | REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0); | |
523224a3 DK |
2891 | } |
2892 | ||
2893 | static void bnx2x_e1h_enable(struct bnx2x *bp) | |
2894 | { | |
2895 | int port = BP_PORT(bp); | |
2896 | ||
2897 | REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1); | |
2898 | ||
2899 | /* Tx queue should be only reenabled */ | |
2900 | netif_tx_wake_all_queues(bp->dev); | |
2901 | ||
2902 | /* | |
2903 | * Should not call netif_carrier_on since it will be called if the link | |
2904 | * is up when checking for link state | |
2905 | */ | |
2906 | } | |
2907 | ||
0793f83f DK |
2908 | /* called due to MCP event (on pmf): |
2909 | * reread new bandwidth configuration | |
2910 | * configure FW | |
2911 | * notify others function about the change | |
2912 | */ | |
2913 | static inline void bnx2x_config_mf_bw(struct bnx2x *bp) | |
2914 | { | |
2915 | if (bp->link_vars.link_up) { | |
2916 | bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX); | |
2917 | bnx2x_link_sync_notify(bp); | |
2918 | } | |
2919 | storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); | |
2920 | } | |
2921 | ||
2922 | static inline void bnx2x_set_mf_bw(struct bnx2x *bp) | |
2923 | { | |
2924 | bnx2x_config_mf_bw(bp); | |
2925 | bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0); | |
2926 | } | |
2927 | ||
523224a3 DK |
2928 | static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event) |
2929 | { | |
2930 | DP(BNX2X_MSG_MCP, "dcc_event 0x%x\n", dcc_event); | |
2931 | ||
2932 | if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) { | |
2933 | ||
2934 | /* | |
2935 | * This is the only place besides the function initialization | |
2936 | * where the bp->flags can change so it is done without any | |
2937 | * locks | |
2938 | */ | |
f2e0899f | 2939 | if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) { |
523224a3 DK |
2940 | DP(NETIF_MSG_IFDOWN, "mf_cfg function disabled\n"); |
2941 | bp->flags |= MF_FUNC_DIS; | |
2942 | ||
2943 | bnx2x_e1h_disable(bp); | |
2944 | } else { | |
2945 | DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n"); | |
2946 | bp->flags &= ~MF_FUNC_DIS; | |
2947 | ||
2948 | bnx2x_e1h_enable(bp); | |
2949 | } | |
2950 | dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF; | |
2951 | } | |
2952 | if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) { | |
0793f83f | 2953 | bnx2x_config_mf_bw(bp); |
523224a3 DK |
2954 | dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION; |
2955 | } | |
2956 | ||
2957 | /* Report results to MCP */ | |
2958 | if (dcc_event) | |
2959 | bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_FAILURE, 0); | |
2960 | else | |
2961 | bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_OK, 0); | |
2962 | } | |
2963 | ||
2964 | /* must be called under the spq lock */ | |
2965 | static inline struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp) | |
2966 | { | |
2967 | struct eth_spe *next_spe = bp->spq_prod_bd; | |
2968 | ||
2969 | if (bp->spq_prod_bd == bp->spq_last_bd) { | |
2970 | bp->spq_prod_bd = bp->spq; | |
2971 | bp->spq_prod_idx = 0; | |
2972 | DP(NETIF_MSG_TIMER, "end of spq\n"); | |
2973 | } else { | |
2974 | bp->spq_prod_bd++; | |
2975 | bp->spq_prod_idx++; | |
2976 | } | |
2977 | return next_spe; | |
2978 | } | |
2979 | ||
2980 | /* must be called under the spq lock */ | |
28912902 MC |
2981 | static inline void bnx2x_sp_prod_update(struct bnx2x *bp) |
2982 | { | |
2983 | int func = BP_FUNC(bp); | |
2984 | ||
2985 | /* Make sure that BD data is updated before writing the producer */ | |
2986 | wmb(); | |
2987 | ||
523224a3 | 2988 | REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func), |
f85582f8 | 2989 | bp->spq_prod_idx); |
28912902 MC |
2990 | mmiowb(); |
2991 | } | |
2992 | ||
619c5cb6 VZ |
2993 | /** |
2994 | * bnx2x_is_contextless_ramrod - check if the current command ends on EQ | |
2995 | * | |
2996 | * @cmd: command to check | |
2997 | * @cmd_type: command type | |
2998 | */ | |
2999 | static inline bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type) | |
3000 | { | |
3001 | if ((cmd_type == NONE_CONNECTION_TYPE) || | |
6383c0b3 | 3002 | (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) || |
619c5cb6 VZ |
3003 | (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) || |
3004 | (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) || | |
3005 | (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) || | |
3006 | (cmd == RAMROD_CMD_ID_ETH_SET_MAC) || | |
3007 | (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE)) | |
3008 | return true; | |
3009 | else | |
3010 | return false; | |
3011 | ||
3012 | } | |
3013 | ||
3014 | ||
3015 | /** | |
3016 | * bnx2x_sp_post - place a single command on an SP ring | |
3017 | * | |
3018 | * @bp: driver handle | |
3019 | * @command: command to place (e.g. SETUP, FILTER_RULES, etc.) | |
3020 | * @cid: SW CID the command is related to | |
3021 | * @data_hi: command private data address (high 32 bits) | |
3022 | * @data_lo: command private data address (low 32 bits) | |
3023 | * @cmd_type: command type (e.g. NONE, ETH) | |
3024 | * | |
3025 | * SP data is handled as if it's always an address pair, thus data fields are | |
3026 | * not swapped to little endian in upper functions. Instead this function swaps | |
3027 | * data as if it's two u32 fields. | |
3028 | */ | |
9f6c9258 | 3029 | int bnx2x_sp_post(struct bnx2x *bp, int command, int cid, |
619c5cb6 | 3030 | u32 data_hi, u32 data_lo, int cmd_type) |
a2fbb9ea | 3031 | { |
28912902 | 3032 | struct eth_spe *spe; |
523224a3 | 3033 | u16 type; |
619c5cb6 | 3034 | bool common = bnx2x_is_contextless_ramrod(command, cmd_type); |
a2fbb9ea | 3035 | |
a2fbb9ea ET |
3036 | #ifdef BNX2X_STOP_ON_ERROR |
3037 | if (unlikely(bp->panic)) | |
3038 | return -EIO; | |
3039 | #endif | |
3040 | ||
34f80b04 | 3041 | spin_lock_bh(&bp->spq_lock); |
a2fbb9ea | 3042 | |
6e30dd4e VZ |
3043 | if (common) { |
3044 | if (!atomic_read(&bp->eq_spq_left)) { | |
3045 | BNX2X_ERR("BUG! EQ ring full!\n"); | |
3046 | spin_unlock_bh(&bp->spq_lock); | |
3047 | bnx2x_panic(); | |
3048 | return -EBUSY; | |
3049 | } | |
3050 | } else if (!atomic_read(&bp->cq_spq_left)) { | |
3051 | BNX2X_ERR("BUG! SPQ ring full!\n"); | |
3052 | spin_unlock_bh(&bp->spq_lock); | |
3053 | bnx2x_panic(); | |
3054 | return -EBUSY; | |
a2fbb9ea | 3055 | } |
f1410647 | 3056 | |
28912902 MC |
3057 | spe = bnx2x_sp_get_next(bp); |
3058 | ||
a2fbb9ea | 3059 | /* CID needs port number to be encoded int it */ |
28912902 | 3060 | spe->hdr.conn_and_cmd_data = |
cdaa7cb8 VZ |
3061 | cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) | |
3062 | HW_CID(bp, cid)); | |
523224a3 | 3063 | |
619c5cb6 | 3064 | type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE; |
a2fbb9ea | 3065 | |
523224a3 DK |
3066 | type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) & |
3067 | SPE_HDR_FUNCTION_ID); | |
a2fbb9ea | 3068 | |
523224a3 DK |
3069 | spe->hdr.type = cpu_to_le16(type); |
3070 | ||
3071 | spe->data.update_data_addr.hi = cpu_to_le32(data_hi); | |
3072 | spe->data.update_data_addr.lo = cpu_to_le32(data_lo); | |
3073 | ||
3074 | /* stats ramrod has it's own slot on the spq */ | |
6e30dd4e | 3075 | if (command != RAMROD_CMD_ID_COMMON_STAT_QUERY) { |
619c5cb6 VZ |
3076 | /* |
3077 | * It's ok if the actual decrement is issued towards the memory | |
523224a3 DK |
3078 | * somewhere between the spin_lock and spin_unlock. Thus no |
3079 | * more explict memory barrier is needed. | |
3080 | */ | |
6e30dd4e VZ |
3081 | if (common) |
3082 | atomic_dec(&bp->eq_spq_left); | |
3083 | else | |
3084 | atomic_dec(&bp->cq_spq_left); | |
3085 | } | |
3086 | ||
a2fbb9ea | 3087 | |
cdaa7cb8 | 3088 | DP(BNX2X_MSG_SP/*NETIF_MSG_TIMER*/, |
523224a3 | 3089 | "SPQE[%x] (%x:%x) command %d hw_cid %x data (%x:%x) " |
6e30dd4e | 3090 | "type(0x%x) left (ETH, COMMON) (%x,%x)\n", |
cdaa7cb8 VZ |
3091 | bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping), |
3092 | (u32)(U64_LO(bp->spq_mapping) + | |
3093 | (void *)bp->spq_prod_bd - (void *)bp->spq), command, | |
6e30dd4e VZ |
3094 | HW_CID(bp, cid), data_hi, data_lo, type, |
3095 | atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left)); | |
cdaa7cb8 | 3096 | |
28912902 | 3097 | bnx2x_sp_prod_update(bp); |
34f80b04 | 3098 | spin_unlock_bh(&bp->spq_lock); |
a2fbb9ea ET |
3099 | return 0; |
3100 | } | |
3101 | ||
3102 | /* acquire split MCP access lock register */ | |
4a37fb66 | 3103 | static int bnx2x_acquire_alr(struct bnx2x *bp) |
a2fbb9ea | 3104 | { |
72fd0718 | 3105 | u32 j, val; |
34f80b04 | 3106 | int rc = 0; |
a2fbb9ea ET |
3107 | |
3108 | might_sleep(); | |
72fd0718 | 3109 | for (j = 0; j < 1000; j++) { |
a2fbb9ea ET |
3110 | val = (1UL << 31); |
3111 | REG_WR(bp, GRCBASE_MCP + 0x9c, val); | |
3112 | val = REG_RD(bp, GRCBASE_MCP + 0x9c); | |
3113 | if (val & (1L << 31)) | |
3114 | break; | |
3115 | ||
3116 | msleep(5); | |
3117 | } | |
a2fbb9ea | 3118 | if (!(val & (1L << 31))) { |
19680c48 | 3119 | BNX2X_ERR("Cannot acquire MCP access lock register\n"); |
a2fbb9ea ET |
3120 | rc = -EBUSY; |
3121 | } | |
3122 | ||
3123 | return rc; | |
3124 | } | |
3125 | ||
4a37fb66 YG |
3126 | /* release split MCP access lock register */ |
3127 | static void bnx2x_release_alr(struct bnx2x *bp) | |
a2fbb9ea | 3128 | { |
72fd0718 | 3129 | REG_WR(bp, GRCBASE_MCP + 0x9c, 0); |
a2fbb9ea ET |
3130 | } |
3131 | ||
523224a3 DK |
3132 | #define BNX2X_DEF_SB_ATT_IDX 0x0001 |
3133 | #define BNX2X_DEF_SB_IDX 0x0002 | |
3134 | ||
a2fbb9ea ET |
3135 | static inline u16 bnx2x_update_dsb_idx(struct bnx2x *bp) |
3136 | { | |
523224a3 | 3137 | struct host_sp_status_block *def_sb = bp->def_status_blk; |
a2fbb9ea ET |
3138 | u16 rc = 0; |
3139 | ||
3140 | barrier(); /* status block is written to by the chip */ | |
a2fbb9ea ET |
3141 | if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) { |
3142 | bp->def_att_idx = def_sb->atten_status_block.attn_bits_index; | |
523224a3 | 3143 | rc |= BNX2X_DEF_SB_ATT_IDX; |
a2fbb9ea | 3144 | } |
523224a3 DK |
3145 | |
3146 | if (bp->def_idx != def_sb->sp_sb.running_index) { | |
3147 | bp->def_idx = def_sb->sp_sb.running_index; | |
3148 | rc |= BNX2X_DEF_SB_IDX; | |
a2fbb9ea | 3149 | } |
523224a3 DK |
3150 | |
3151 | /* Do not reorder: indecies reading should complete before handling */ | |
3152 | barrier(); | |
a2fbb9ea ET |
3153 | return rc; |
3154 | } | |
3155 | ||
3156 | /* | |
3157 | * slow path service functions | |
3158 | */ | |
3159 | ||
3160 | static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted) | |
3161 | { | |
34f80b04 | 3162 | int port = BP_PORT(bp); |
a2fbb9ea ET |
3163 | u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : |
3164 | MISC_REG_AEU_MASK_ATTN_FUNC_0; | |
877e9aa4 ET |
3165 | u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 : |
3166 | NIG_REG_MASK_INTERRUPT_PORT0; | |
3fcaf2e5 | 3167 | u32 aeu_mask; |
87942b46 | 3168 | u32 nig_mask = 0; |
f2e0899f | 3169 | u32 reg_addr; |
a2fbb9ea | 3170 | |
a2fbb9ea ET |
3171 | if (bp->attn_state & asserted) |
3172 | BNX2X_ERR("IGU ERROR\n"); | |
3173 | ||
3fcaf2e5 EG |
3174 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); |
3175 | aeu_mask = REG_RD(bp, aeu_addr); | |
3176 | ||
a2fbb9ea | 3177 | DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n", |
3fcaf2e5 | 3178 | aeu_mask, asserted); |
72fd0718 | 3179 | aeu_mask &= ~(asserted & 0x3ff); |
3fcaf2e5 | 3180 | DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask); |
a2fbb9ea | 3181 | |
3fcaf2e5 EG |
3182 | REG_WR(bp, aeu_addr, aeu_mask); |
3183 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); | |
a2fbb9ea | 3184 | |
3fcaf2e5 | 3185 | DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state); |
a2fbb9ea | 3186 | bp->attn_state |= asserted; |
3fcaf2e5 | 3187 | DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state); |
a2fbb9ea ET |
3188 | |
3189 | if (asserted & ATTN_HARD_WIRED_MASK) { | |
3190 | if (asserted & ATTN_NIG_FOR_FUNC) { | |
a2fbb9ea | 3191 | |
a5e9a7cf EG |
3192 | bnx2x_acquire_phy_lock(bp); |
3193 | ||
877e9aa4 | 3194 | /* save nig interrupt mask */ |
87942b46 | 3195 | nig_mask = REG_RD(bp, nig_int_mask_addr); |
a2fbb9ea | 3196 | |
361c391e YR |
3197 | /* If nig_mask is not set, no need to call the update |
3198 | * function. | |
3199 | */ | |
3200 | if (nig_mask) { | |
3201 | REG_WR(bp, nig_int_mask_addr, 0); | |
3202 | ||
3203 | bnx2x_link_attn(bp); | |
3204 | } | |
a2fbb9ea ET |
3205 | |
3206 | /* handle unicore attn? */ | |
3207 | } | |
3208 | if (asserted & ATTN_SW_TIMER_4_FUNC) | |
3209 | DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n"); | |
3210 | ||
3211 | if (asserted & GPIO_2_FUNC) | |
3212 | DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n"); | |
3213 | ||
3214 | if (asserted & GPIO_3_FUNC) | |
3215 | DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n"); | |
3216 | ||
3217 | if (asserted & GPIO_4_FUNC) | |
3218 | DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n"); | |
3219 | ||
3220 | if (port == 0) { | |
3221 | if (asserted & ATTN_GENERAL_ATTN_1) { | |
3222 | DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n"); | |
3223 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0); | |
3224 | } | |
3225 | if (asserted & ATTN_GENERAL_ATTN_2) { | |
3226 | DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n"); | |
3227 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0); | |
3228 | } | |
3229 | if (asserted & ATTN_GENERAL_ATTN_3) { | |
3230 | DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n"); | |
3231 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0); | |
3232 | } | |
3233 | } else { | |
3234 | if (asserted & ATTN_GENERAL_ATTN_4) { | |
3235 | DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n"); | |
3236 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0); | |
3237 | } | |
3238 | if (asserted & ATTN_GENERAL_ATTN_5) { | |
3239 | DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n"); | |
3240 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0); | |
3241 | } | |
3242 | if (asserted & ATTN_GENERAL_ATTN_6) { | |
3243 | DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n"); | |
3244 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0); | |
3245 | } | |
3246 | } | |
3247 | ||
3248 | } /* if hardwired */ | |
3249 | ||
f2e0899f DK |
3250 | if (bp->common.int_block == INT_BLOCK_HC) |
3251 | reg_addr = (HC_REG_COMMAND_REG + port*32 + | |
3252 | COMMAND_REG_ATTN_BITS_SET); | |
3253 | else | |
3254 | reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8); | |
3255 | ||
3256 | DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted, | |
3257 | (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr); | |
3258 | REG_WR(bp, reg_addr, asserted); | |
a2fbb9ea ET |
3259 | |
3260 | /* now set back the mask */ | |
a5e9a7cf | 3261 | if (asserted & ATTN_NIG_FOR_FUNC) { |
87942b46 | 3262 | REG_WR(bp, nig_int_mask_addr, nig_mask); |
a5e9a7cf EG |
3263 | bnx2x_release_phy_lock(bp); |
3264 | } | |
a2fbb9ea ET |
3265 | } |
3266 | ||
fd4ef40d EG |
3267 | static inline void bnx2x_fan_failure(struct bnx2x *bp) |
3268 | { | |
3269 | int port = BP_PORT(bp); | |
b7737c9b | 3270 | u32 ext_phy_config; |
fd4ef40d | 3271 | /* mark the failure */ |
b7737c9b YR |
3272 | ext_phy_config = |
3273 | SHMEM_RD(bp, | |
3274 | dev_info.port_hw_config[port].external_phy_config); | |
3275 | ||
3276 | ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK; | |
3277 | ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE; | |
fd4ef40d | 3278 | SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config, |
b7737c9b | 3279 | ext_phy_config); |
fd4ef40d EG |
3280 | |
3281 | /* log the failure */ | |
cdaa7cb8 VZ |
3282 | netdev_err(bp->dev, "Fan Failure on Network Controller has caused" |
3283 | " the driver to shutdown the card to prevent permanent" | |
3284 | " damage. Please contact OEM Support for assistance\n"); | |
fd4ef40d | 3285 | } |
ab6ad5a4 | 3286 | |
877e9aa4 | 3287 | static inline void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn) |
a2fbb9ea | 3288 | { |
34f80b04 | 3289 | int port = BP_PORT(bp); |
877e9aa4 | 3290 | int reg_offset; |
d90d96ba | 3291 | u32 val; |
877e9aa4 | 3292 | |
34f80b04 EG |
3293 | reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : |
3294 | MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); | |
877e9aa4 | 3295 | |
34f80b04 | 3296 | if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) { |
877e9aa4 ET |
3297 | |
3298 | val = REG_RD(bp, reg_offset); | |
3299 | val &= ~AEU_INPUTS_ATTN_BITS_SPIO5; | |
3300 | REG_WR(bp, reg_offset, val); | |
3301 | ||
3302 | BNX2X_ERR("SPIO5 hw attention\n"); | |
3303 | ||
fd4ef40d | 3304 | /* Fan failure attention */ |
d90d96ba | 3305 | bnx2x_hw_reset_phy(&bp->link_params); |
fd4ef40d | 3306 | bnx2x_fan_failure(bp); |
877e9aa4 | 3307 | } |
34f80b04 | 3308 | |
3deb8167 | 3309 | if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) { |
589abe3a EG |
3310 | bnx2x_acquire_phy_lock(bp); |
3311 | bnx2x_handle_module_detect_int(&bp->link_params); | |
3312 | bnx2x_release_phy_lock(bp); | |
3313 | } | |
3314 | ||
34f80b04 EG |
3315 | if (attn & HW_INTERRUT_ASSERT_SET_0) { |
3316 | ||
3317 | val = REG_RD(bp, reg_offset); | |
3318 | val &= ~(attn & HW_INTERRUT_ASSERT_SET_0); | |
3319 | REG_WR(bp, reg_offset, val); | |
3320 | ||
3321 | BNX2X_ERR("FATAL HW block attention set0 0x%x\n", | |
0fc5d009 | 3322 | (u32)(attn & HW_INTERRUT_ASSERT_SET_0)); |
34f80b04 EG |
3323 | bnx2x_panic(); |
3324 | } | |
877e9aa4 ET |
3325 | } |
3326 | ||
3327 | static inline void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn) | |
3328 | { | |
3329 | u32 val; | |
3330 | ||
0626b899 | 3331 | if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) { |
877e9aa4 ET |
3332 | |
3333 | val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR); | |
3334 | BNX2X_ERR("DB hw attention 0x%x\n", val); | |
3335 | /* DORQ discard attention */ | |
3336 | if (val & 0x2) | |
3337 | BNX2X_ERR("FATAL error from DORQ\n"); | |
3338 | } | |
34f80b04 EG |
3339 | |
3340 | if (attn & HW_INTERRUT_ASSERT_SET_1) { | |
3341 | ||
3342 | int port = BP_PORT(bp); | |
3343 | int reg_offset; | |
3344 | ||
3345 | reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 : | |
3346 | MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1); | |
3347 | ||
3348 | val = REG_RD(bp, reg_offset); | |
3349 | val &= ~(attn & HW_INTERRUT_ASSERT_SET_1); | |
3350 | REG_WR(bp, reg_offset, val); | |
3351 | ||
3352 | BNX2X_ERR("FATAL HW block attention set1 0x%x\n", | |
0fc5d009 | 3353 | (u32)(attn & HW_INTERRUT_ASSERT_SET_1)); |
34f80b04 EG |
3354 | bnx2x_panic(); |
3355 | } | |
877e9aa4 ET |
3356 | } |
3357 | ||
3358 | static inline void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn) | |
3359 | { | |
3360 | u32 val; | |
3361 | ||
3362 | if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) { | |
3363 | ||
3364 | val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR); | |
3365 | BNX2X_ERR("CFC hw attention 0x%x\n", val); | |
3366 | /* CFC error attention */ | |
3367 | if (val & 0x2) | |
3368 | BNX2X_ERR("FATAL error from CFC\n"); | |
3369 | } | |
3370 | ||
3371 | if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) { | |
877e9aa4 | 3372 | val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0); |
619c5cb6 | 3373 | BNX2X_ERR("PXP hw attention-0 0x%x\n", val); |
877e9aa4 ET |
3374 | /* RQ_USDMDP_FIFO_OVERFLOW */ |
3375 | if (val & 0x18000) | |
3376 | BNX2X_ERR("FATAL error from PXP\n"); | |
619c5cb6 VZ |
3377 | |
3378 | if (!CHIP_IS_E1x(bp)) { | |
f2e0899f DK |
3379 | val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1); |
3380 | BNX2X_ERR("PXP hw attention-1 0x%x\n", val); | |
3381 | } | |
877e9aa4 | 3382 | } |
34f80b04 EG |
3383 | |
3384 | if (attn & HW_INTERRUT_ASSERT_SET_2) { | |
3385 | ||
3386 | int port = BP_PORT(bp); | |
3387 | int reg_offset; | |
3388 | ||
3389 | reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 : | |
3390 | MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2); | |
3391 | ||
3392 | val = REG_RD(bp, reg_offset); | |
3393 | val &= ~(attn & HW_INTERRUT_ASSERT_SET_2); | |
3394 | REG_WR(bp, reg_offset, val); | |
3395 | ||
3396 | BNX2X_ERR("FATAL HW block attention set2 0x%x\n", | |
0fc5d009 | 3397 | (u32)(attn & HW_INTERRUT_ASSERT_SET_2)); |
34f80b04 EG |
3398 | bnx2x_panic(); |
3399 | } | |
877e9aa4 ET |
3400 | } |
3401 | ||
3402 | static inline void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn) | |
3403 | { | |
34f80b04 EG |
3404 | u32 val; |
3405 | ||
877e9aa4 ET |
3406 | if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) { |
3407 | ||
34f80b04 EG |
3408 | if (attn & BNX2X_PMF_LINK_ASSERT) { |
3409 | int func = BP_FUNC(bp); | |
3410 | ||
3411 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); | |
f2e0899f DK |
3412 | bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp, |
3413 | func_mf_config[BP_ABS_FUNC(bp)].config); | |
3414 | val = SHMEM_RD(bp, | |
3415 | func_mb[BP_FW_MB_IDX(bp)].drv_status); | |
2691d51d EG |
3416 | if (val & DRV_STATUS_DCC_EVENT_MASK) |
3417 | bnx2x_dcc_event(bp, | |
3418 | (val & DRV_STATUS_DCC_EVENT_MASK)); | |
0793f83f DK |
3419 | |
3420 | if (val & DRV_STATUS_SET_MF_BW) | |
3421 | bnx2x_set_mf_bw(bp); | |
3422 | ||
2691d51d | 3423 | if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF)) |
34f80b04 EG |
3424 | bnx2x_pmf_update(bp); |
3425 | ||
e4901dde | 3426 | if (bp->port.pmf && |
785b9b1a SR |
3427 | (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) && |
3428 | bp->dcbx_enabled > 0) | |
e4901dde VZ |
3429 | /* start dcbx state machine */ |
3430 | bnx2x_dcbx_set_params(bp, | |
3431 | BNX2X_DCBX_STATE_NEG_RECEIVED); | |
3deb8167 YR |
3432 | if (bp->link_vars.periodic_flags & |
3433 | PERIODIC_FLAGS_LINK_EVENT) { | |
3434 | /* sync with link */ | |
3435 | bnx2x_acquire_phy_lock(bp); | |
3436 | bp->link_vars.periodic_flags &= | |
3437 | ~PERIODIC_FLAGS_LINK_EVENT; | |
3438 | bnx2x_release_phy_lock(bp); | |
3439 | if (IS_MF(bp)) | |
3440 | bnx2x_link_sync_notify(bp); | |
3441 | bnx2x_link_report(bp); | |
3442 | } | |
3443 | /* Always call it here: bnx2x_link_report() will | |
3444 | * prevent the link indication duplication. | |
3445 | */ | |
3446 | bnx2x__link_status_update(bp); | |
34f80b04 | 3447 | } else if (attn & BNX2X_MC_ASSERT_BITS) { |
877e9aa4 ET |
3448 | |
3449 | BNX2X_ERR("MC assert!\n"); | |
3450 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0); | |
3451 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0); | |
3452 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0); | |
3453 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0); | |
3454 | bnx2x_panic(); | |
3455 | ||
3456 | } else if (attn & BNX2X_MCP_ASSERT) { | |
3457 | ||
3458 | BNX2X_ERR("MCP assert!\n"); | |
3459 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0); | |
34f80b04 | 3460 | bnx2x_fw_dump(bp); |
877e9aa4 ET |
3461 | |
3462 | } else | |
3463 | BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn); | |
3464 | } | |
3465 | ||
3466 | if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) { | |
34f80b04 EG |
3467 | BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn); |
3468 | if (attn & BNX2X_GRC_TIMEOUT) { | |
f2e0899f DK |
3469 | val = CHIP_IS_E1(bp) ? 0 : |
3470 | REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN); | |
34f80b04 EG |
3471 | BNX2X_ERR("GRC time-out 0x%08x\n", val); |
3472 | } | |
3473 | if (attn & BNX2X_GRC_RSV) { | |
f2e0899f DK |
3474 | val = CHIP_IS_E1(bp) ? 0 : |
3475 | REG_RD(bp, MISC_REG_GRC_RSV_ATTN); | |
34f80b04 EG |
3476 | BNX2X_ERR("GRC reserved 0x%08x\n", val); |
3477 | } | |
877e9aa4 | 3478 | REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff); |
877e9aa4 ET |
3479 | } |
3480 | } | |
3481 | ||
c9ee9206 VZ |
3482 | /* |
3483 | * Bits map: | |
3484 | * 0-7 - Engine0 load counter. | |
3485 | * 8-15 - Engine1 load counter. | |
3486 | * 16 - Engine0 RESET_IN_PROGRESS bit. | |
3487 | * 17 - Engine1 RESET_IN_PROGRESS bit. | |
3488 | * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active function | |
3489 | * on the engine | |
3490 | * 19 - Engine1 ONE_IS_LOADED. | |
3491 | * 20 - Chip reset flow bit. When set none-leader must wait for both engines | |
3492 | * leader to complete (check for both RESET_IN_PROGRESS bits and not for | |
3493 | * just the one belonging to its engine). | |
3494 | * | |
3495 | */ | |
3496 | #define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1 | |
3497 | ||
3498 | #define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff | |
3499 | #define BNX2X_PATH0_LOAD_CNT_SHIFT 0 | |
3500 | #define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00 | |
3501 | #define BNX2X_PATH1_LOAD_CNT_SHIFT 8 | |
3502 | #define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000 | |
3503 | #define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000 | |
3504 | #define BNX2X_GLOBAL_RESET_BIT 0x00040000 | |
3505 | ||
3506 | /* | |
3507 | * Set the GLOBAL_RESET bit. | |
3508 | * | |
3509 | * Should be run under rtnl lock | |
3510 | */ | |
3511 | void bnx2x_set_reset_global(struct bnx2x *bp) | |
3512 | { | |
3513 | u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); | |
3514 | ||
3515 | REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT); | |
3516 | barrier(); | |
3517 | mmiowb(); | |
3518 | } | |
3519 | ||
3520 | /* | |
3521 | * Clear the GLOBAL_RESET bit. | |
3522 | * | |
3523 | * Should be run under rtnl lock | |
3524 | */ | |
3525 | static inline void bnx2x_clear_reset_global(struct bnx2x *bp) | |
3526 | { | |
3527 | u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); | |
3528 | ||
3529 | REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT)); | |
3530 | barrier(); | |
3531 | mmiowb(); | |
3532 | } | |
f85582f8 | 3533 | |
72fd0718 | 3534 | /* |
c9ee9206 VZ |
3535 | * Checks the GLOBAL_RESET bit. |
3536 | * | |
72fd0718 VZ |
3537 | * should be run under rtnl lock |
3538 | */ | |
c9ee9206 VZ |
3539 | static inline bool bnx2x_reset_is_global(struct bnx2x *bp) |
3540 | { | |
3541 | u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); | |
3542 | ||
3543 | DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val); | |
3544 | return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false; | |
3545 | } | |
3546 | ||
3547 | /* | |
3548 | * Clear RESET_IN_PROGRESS bit for the current engine. | |
3549 | * | |
3550 | * Should be run under rtnl lock | |
3551 | */ | |
72fd0718 VZ |
3552 | static inline void bnx2x_set_reset_done(struct bnx2x *bp) |
3553 | { | |
c9ee9206 VZ |
3554 | u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); |
3555 | u32 bit = BP_PATH(bp) ? | |
3556 | BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT; | |
3557 | ||
3558 | /* Clear the bit */ | |
3559 | val &= ~bit; | |
3560 | REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); | |
72fd0718 VZ |
3561 | barrier(); |
3562 | mmiowb(); | |
3563 | } | |
3564 | ||
3565 | /* | |
c9ee9206 VZ |
3566 | * Set RESET_IN_PROGRESS for the current engine. |
3567 | * | |
72fd0718 VZ |
3568 | * should be run under rtnl lock |
3569 | */ | |
c9ee9206 | 3570 | void bnx2x_set_reset_in_progress(struct bnx2x *bp) |
72fd0718 | 3571 | { |
c9ee9206 VZ |
3572 | u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); |
3573 | u32 bit = BP_PATH(bp) ? | |
3574 | BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT; | |
3575 | ||
3576 | /* Set the bit */ | |
3577 | val |= bit; | |
3578 | REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); | |
72fd0718 VZ |
3579 | barrier(); |
3580 | mmiowb(); | |
3581 | } | |
3582 | ||
3583 | /* | |
c9ee9206 | 3584 | * Checks the RESET_IN_PROGRESS bit for the given engine. |
72fd0718 VZ |
3585 | * should be run under rtnl lock |
3586 | */ | |
c9ee9206 | 3587 | bool bnx2x_reset_is_done(struct bnx2x *bp, int engine) |
72fd0718 | 3588 | { |
c9ee9206 VZ |
3589 | u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); |
3590 | u32 bit = engine ? | |
3591 | BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT; | |
3592 | ||
3593 | /* return false if bit is set */ | |
3594 | return (val & bit) ? false : true; | |
72fd0718 VZ |
3595 | } |
3596 | ||
3597 | /* | |
c9ee9206 VZ |
3598 | * Increment the load counter for the current engine. |
3599 | * | |
72fd0718 VZ |
3600 | * should be run under rtnl lock |
3601 | */ | |
c9ee9206 | 3602 | void bnx2x_inc_load_cnt(struct bnx2x *bp) |
72fd0718 | 3603 | { |
c9ee9206 VZ |
3604 | u32 val1, val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); |
3605 | u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK : | |
3606 | BNX2X_PATH0_LOAD_CNT_MASK; | |
3607 | u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT : | |
3608 | BNX2X_PATH0_LOAD_CNT_SHIFT; | |
72fd0718 VZ |
3609 | |
3610 | DP(NETIF_MSG_HW, "Old GEN_REG_VAL=0x%08x\n", val); | |
3611 | ||
c9ee9206 VZ |
3612 | /* get the current counter value */ |
3613 | val1 = (val & mask) >> shift; | |
3614 | ||
3615 | /* increment... */ | |
3616 | val1++; | |
3617 | ||
3618 | /* clear the old value */ | |
3619 | val &= ~mask; | |
3620 | ||
3621 | /* set the new one */ | |
3622 | val |= ((val1 << shift) & mask); | |
3623 | ||
3624 | REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); | |
72fd0718 VZ |
3625 | barrier(); |
3626 | mmiowb(); | |
3627 | } | |
3628 | ||
c9ee9206 VZ |
3629 | /** |
3630 | * bnx2x_dec_load_cnt - decrement the load counter | |
3631 | * | |
3632 | * @bp: driver handle | |
3633 | * | |
3634 | * Should be run under rtnl lock. | |
3635 | * Decrements the load counter for the current engine. Returns | |
3636 | * the new counter value. | |
72fd0718 | 3637 | */ |
9f6c9258 | 3638 | u32 bnx2x_dec_load_cnt(struct bnx2x *bp) |
72fd0718 | 3639 | { |
c9ee9206 VZ |
3640 | u32 val1, val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); |
3641 | u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK : | |
3642 | BNX2X_PATH0_LOAD_CNT_MASK; | |
3643 | u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT : | |
3644 | BNX2X_PATH0_LOAD_CNT_SHIFT; | |
72fd0718 VZ |
3645 | |
3646 | DP(NETIF_MSG_HW, "Old GEN_REG_VAL=0x%08x\n", val); | |
3647 | ||
c9ee9206 VZ |
3648 | /* get the current counter value */ |
3649 | val1 = (val & mask) >> shift; | |
3650 | ||
3651 | /* decrement... */ | |
3652 | val1--; | |
3653 | ||
3654 | /* clear the old value */ | |
3655 | val &= ~mask; | |
3656 | ||
3657 | /* set the new one */ | |
3658 | val |= ((val1 << shift) & mask); | |
3659 | ||
3660 | REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); | |
72fd0718 VZ |
3661 | barrier(); |
3662 | mmiowb(); | |
3663 | ||
3664 | return val1; | |
3665 | } | |
3666 | ||
3667 | /* | |
c9ee9206 VZ |
3668 | * Read the load counter for the current engine. |
3669 | * | |
72fd0718 VZ |
3670 | * should be run under rtnl lock |
3671 | */ | |
c9ee9206 | 3672 | static inline u32 bnx2x_get_load_cnt(struct bnx2x *bp, int engine) |
72fd0718 | 3673 | { |
c9ee9206 VZ |
3674 | u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK : |
3675 | BNX2X_PATH0_LOAD_CNT_MASK); | |
3676 | u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT : | |
3677 | BNX2X_PATH0_LOAD_CNT_SHIFT); | |
3678 | u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); | |
3679 | ||
3680 | DP(NETIF_MSG_HW, "GLOB_REG=0x%08x\n", val); | |
3681 | ||
3682 | val = (val & mask) >> shift; | |
3683 | ||
3684 | DP(NETIF_MSG_HW, "load_cnt for engine %d = %d\n", engine, val); | |
3685 | ||
3686 | return val; | |
72fd0718 VZ |
3687 | } |
3688 | ||
c9ee9206 VZ |
3689 | /* |
3690 | * Reset the load counter for the current engine. | |
3691 | * | |
3692 | * should be run under rtnl lock | |
3693 | */ | |
72fd0718 VZ |
3694 | static inline void bnx2x_clear_load_cnt(struct bnx2x *bp) |
3695 | { | |
c9ee9206 VZ |
3696 | u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); |
3697 | u32 mask = (BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK : | |
3698 | BNX2X_PATH0_LOAD_CNT_MASK); | |
3699 | ||
3700 | REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~mask)); | |
72fd0718 VZ |
3701 | } |
3702 | ||
3703 | static inline void _print_next_block(int idx, const char *blk) | |
3704 | { | |
3705 | if (idx) | |
3706 | pr_cont(", "); | |
3707 | pr_cont("%s", blk); | |
3708 | } | |
3709 | ||
c9ee9206 VZ |
3710 | static inline int bnx2x_check_blocks_with_parity0(u32 sig, int par_num, |
3711 | bool print) | |
72fd0718 VZ |
3712 | { |
3713 | int i = 0; | |
3714 | u32 cur_bit = 0; | |
3715 | for (i = 0; sig; i++) { | |
3716 | cur_bit = ((u32)0x1 << i); | |
3717 | if (sig & cur_bit) { | |
3718 | switch (cur_bit) { | |
3719 | case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR: | |
c9ee9206 VZ |
3720 | if (print) |
3721 | _print_next_block(par_num++, "BRB"); | |
72fd0718 VZ |
3722 | break; |
3723 | case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR: | |
c9ee9206 VZ |
3724 | if (print) |
3725 | _print_next_block(par_num++, "PARSER"); | |
72fd0718 VZ |
3726 | break; |
3727 | case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR: | |
c9ee9206 VZ |
3728 | if (print) |
3729 | _print_next_block(par_num++, "TSDM"); | |
72fd0718 VZ |
3730 | break; |
3731 | case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR: | |
c9ee9206 VZ |
3732 | if (print) |
3733 | _print_next_block(par_num++, | |
3734 | "SEARCHER"); | |
3735 | break; | |
3736 | case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR: | |
3737 | if (print) | |
3738 | _print_next_block(par_num++, "TCM"); | |
72fd0718 VZ |
3739 | break; |
3740 | case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR: | |
c9ee9206 VZ |
3741 | if (print) |
3742 | _print_next_block(par_num++, "TSEMI"); | |
3743 | break; | |
3744 | case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR: | |
3745 | if (print) | |
3746 | _print_next_block(par_num++, "XPB"); | |
72fd0718 VZ |
3747 | break; |
3748 | } | |
3749 | ||
3750 | /* Clear the bit */ | |
3751 | sig &= ~cur_bit; | |
3752 | } | |
3753 | } | |
3754 | ||
3755 | return par_num; | |
3756 | } | |
3757 | ||
c9ee9206 VZ |
3758 | static inline int bnx2x_check_blocks_with_parity1(u32 sig, int par_num, |
3759 | bool *global, bool print) | |
72fd0718 VZ |
3760 | { |
3761 | int i = 0; | |
3762 | u32 cur_bit = 0; | |
3763 | for (i = 0; sig; i++) { | |
3764 | cur_bit = ((u32)0x1 << i); | |
3765 | if (sig & cur_bit) { | |
3766 | switch (cur_bit) { | |
c9ee9206 VZ |
3767 | case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR: |
3768 | if (print) | |
3769 | _print_next_block(par_num++, "PBF"); | |
72fd0718 VZ |
3770 | break; |
3771 | case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR: | |
c9ee9206 VZ |
3772 | if (print) |
3773 | _print_next_block(par_num++, "QM"); | |
3774 | break; | |
3775 | case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR: | |
3776 | if (print) | |
3777 | _print_next_block(par_num++, "TM"); | |
72fd0718 VZ |
3778 | break; |
3779 | case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR: | |
c9ee9206 VZ |
3780 | if (print) |
3781 | _print_next_block(par_num++, "XSDM"); | |
3782 | break; | |
3783 | case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR: | |
3784 | if (print) | |
3785 | _print_next_block(par_num++, "XCM"); | |
72fd0718 VZ |
3786 | break; |
3787 | case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR: | |
c9ee9206 VZ |
3788 | if (print) |
3789 | _print_next_block(par_num++, "XSEMI"); | |
72fd0718 VZ |
3790 | break; |
3791 | case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR: | |
c9ee9206 VZ |
3792 | if (print) |
3793 | _print_next_block(par_num++, | |
3794 | "DOORBELLQ"); | |
3795 | break; | |
3796 | case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR: | |
3797 | if (print) | |
3798 | _print_next_block(par_num++, "NIG"); | |
72fd0718 VZ |
3799 | break; |
3800 | case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR: | |
c9ee9206 VZ |
3801 | if (print) |
3802 | _print_next_block(par_num++, | |
3803 | "VAUX PCI CORE"); | |
3804 | *global = true; | |
72fd0718 VZ |
3805 | break; |
3806 | case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR: | |
c9ee9206 VZ |
3807 | if (print) |
3808 | _print_next_block(par_num++, "DEBUG"); | |
72fd0718 VZ |
3809 | break; |
3810 | case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR: | |
c9ee9206 VZ |
3811 | if (print) |
3812 | _print_next_block(par_num++, "USDM"); | |
72fd0718 VZ |
3813 | break; |
3814 | case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR: | |
c9ee9206 VZ |
3815 | if (print) |
3816 | _print_next_block(par_num++, "USEMI"); | |
72fd0718 VZ |
3817 | break; |
3818 | case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR: | |
c9ee9206 VZ |
3819 | if (print) |
3820 | _print_next_block(par_num++, "UPB"); | |
72fd0718 VZ |
3821 | break; |
3822 | case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR: | |
c9ee9206 VZ |
3823 | if (print) |
3824 | _print_next_block(par_num++, "CSDM"); | |
72fd0718 VZ |
3825 | break; |
3826 | } | |
3827 | ||
3828 | /* Clear the bit */ | |
3829 | sig &= ~cur_bit; | |
3830 | } | |
3831 | } | |
3832 | ||
3833 | return par_num; | |
3834 | } | |
3835 | ||
c9ee9206 VZ |
3836 | static inline int bnx2x_check_blocks_with_parity2(u32 sig, int par_num, |
3837 | bool print) | |
72fd0718 VZ |
3838 | { |
3839 | int i = 0; | |
3840 | u32 cur_bit = 0; | |
3841 | for (i = 0; sig; i++) { | |
3842 | cur_bit = ((u32)0x1 << i); | |
3843 | if (sig & cur_bit) { | |
3844 | switch (cur_bit) { | |
3845 | case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR: | |
c9ee9206 VZ |
3846 | if (print) |
3847 | _print_next_block(par_num++, "CSEMI"); | |
72fd0718 VZ |
3848 | break; |
3849 | case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR: | |
c9ee9206 VZ |
3850 | if (print) |
3851 | _print_next_block(par_num++, "PXP"); | |
72fd0718 VZ |
3852 | break; |
3853 | case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR: | |
c9ee9206 VZ |
3854 | if (print) |
3855 | _print_next_block(par_num++, | |
72fd0718 VZ |
3856 | "PXPPCICLOCKCLIENT"); |
3857 | break; | |
3858 | case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR: | |
c9ee9206 VZ |
3859 | if (print) |
3860 | _print_next_block(par_num++, "CFC"); | |
72fd0718 VZ |
3861 | break; |
3862 | case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR: | |
c9ee9206 VZ |
3863 | if (print) |
3864 | _print_next_block(par_num++, "CDU"); | |
3865 | break; | |
3866 | case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR: | |
3867 | if (print) | |
3868 | _print_next_block(par_num++, "DMAE"); | |
72fd0718 VZ |
3869 | break; |
3870 | case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR: | |
c9ee9206 VZ |
3871 | if (print) |
3872 | _print_next_block(par_num++, "IGU"); | |
72fd0718 VZ |
3873 | break; |
3874 | case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR: | |
c9ee9206 VZ |
3875 | if (print) |
3876 | _print_next_block(par_num++, "MISC"); | |
72fd0718 VZ |
3877 | break; |
3878 | } | |
3879 | ||
3880 | /* Clear the bit */ | |
3881 | sig &= ~cur_bit; | |
3882 | } | |
3883 | } | |
3884 | ||
3885 | return par_num; | |
3886 | } | |
3887 | ||
c9ee9206 VZ |
3888 | static inline int bnx2x_check_blocks_with_parity3(u32 sig, int par_num, |
3889 | bool *global, bool print) | |
72fd0718 VZ |
3890 | { |
3891 | int i = 0; | |
3892 | u32 cur_bit = 0; | |
3893 | for (i = 0; sig; i++) { | |
3894 | cur_bit = ((u32)0x1 << i); | |
3895 | if (sig & cur_bit) { | |
3896 | switch (cur_bit) { | |
3897 | case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY: | |
c9ee9206 VZ |
3898 | if (print) |
3899 | _print_next_block(par_num++, "MCP ROM"); | |
3900 | *global = true; | |
72fd0718 VZ |
3901 | break; |
3902 | case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY: | |
c9ee9206 VZ |
3903 | if (print) |
3904 | _print_next_block(par_num++, | |
3905 | "MCP UMP RX"); | |
3906 | *global = true; | |
72fd0718 VZ |
3907 | break; |
3908 | case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY: | |
c9ee9206 VZ |
3909 | if (print) |
3910 | _print_next_block(par_num++, | |
3911 | "MCP UMP TX"); | |
3912 | *global = true; | |
72fd0718 VZ |
3913 | break; |
3914 | case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY: | |
c9ee9206 VZ |
3915 | if (print) |
3916 | _print_next_block(par_num++, | |
3917 | "MCP SCPAD"); | |
3918 | *global = true; | |
72fd0718 VZ |
3919 | break; |
3920 | } | |
3921 | ||
3922 | /* Clear the bit */ | |
3923 | sig &= ~cur_bit; | |
3924 | } | |
3925 | } | |
3926 | ||
3927 | return par_num; | |
3928 | } | |
3929 | ||
c9ee9206 VZ |
3930 | static inline bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print, |
3931 | u32 sig0, u32 sig1, u32 sig2, u32 sig3) | |
72fd0718 VZ |
3932 | { |
3933 | if ((sig0 & HW_PRTY_ASSERT_SET_0) || (sig1 & HW_PRTY_ASSERT_SET_1) || | |
3934 | (sig2 & HW_PRTY_ASSERT_SET_2) || (sig3 & HW_PRTY_ASSERT_SET_3)) { | |
3935 | int par_num = 0; | |
3936 | DP(NETIF_MSG_HW, "Was parity error: HW block parity attention: " | |
3937 | "[0]:0x%08x [1]:0x%08x " | |
3938 | "[2]:0x%08x [3]:0x%08x\n", | |
3939 | sig0 & HW_PRTY_ASSERT_SET_0, | |
3940 | sig1 & HW_PRTY_ASSERT_SET_1, | |
3941 | sig2 & HW_PRTY_ASSERT_SET_2, | |
3942 | sig3 & HW_PRTY_ASSERT_SET_3); | |
c9ee9206 VZ |
3943 | if (print) |
3944 | netdev_err(bp->dev, | |
3945 | "Parity errors detected in blocks: "); | |
3946 | par_num = bnx2x_check_blocks_with_parity0( | |
3947 | sig0 & HW_PRTY_ASSERT_SET_0, par_num, print); | |
3948 | par_num = bnx2x_check_blocks_with_parity1( | |
3949 | sig1 & HW_PRTY_ASSERT_SET_1, par_num, global, print); | |
3950 | par_num = bnx2x_check_blocks_with_parity2( | |
3951 | sig2 & HW_PRTY_ASSERT_SET_2, par_num, print); | |
3952 | par_num = bnx2x_check_blocks_with_parity3( | |
3953 | sig3 & HW_PRTY_ASSERT_SET_3, par_num, global, print); | |
3954 | if (print) | |
3955 | pr_cont("\n"); | |
72fd0718 VZ |
3956 | return true; |
3957 | } else | |
3958 | return false; | |
3959 | } | |
3960 | ||
c9ee9206 VZ |
3961 | /** |
3962 | * bnx2x_chk_parity_attn - checks for parity attentions. | |
3963 | * | |
3964 | * @bp: driver handle | |
3965 | * @global: true if there was a global attention | |
3966 | * @print: show parity attention in syslog | |
3967 | */ | |
3968 | bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print) | |
877e9aa4 | 3969 | { |
a2fbb9ea | 3970 | struct attn_route attn; |
72fd0718 VZ |
3971 | int port = BP_PORT(bp); |
3972 | ||
3973 | attn.sig[0] = REG_RD(bp, | |
3974 | MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + | |
3975 | port*4); | |
3976 | attn.sig[1] = REG_RD(bp, | |
3977 | MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + | |
3978 | port*4); | |
3979 | attn.sig[2] = REG_RD(bp, | |
3980 | MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + | |
3981 | port*4); | |
3982 | attn.sig[3] = REG_RD(bp, | |
3983 | MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + | |
3984 | port*4); | |
3985 | ||
c9ee9206 VZ |
3986 | return bnx2x_parity_attn(bp, global, print, attn.sig[0], attn.sig[1], |
3987 | attn.sig[2], attn.sig[3]); | |
72fd0718 VZ |
3988 | } |
3989 | ||
f2e0899f DK |
3990 | |
3991 | static inline void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn) | |
3992 | { | |
3993 | u32 val; | |
3994 | if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) { | |
3995 | ||
3996 | val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR); | |
3997 | BNX2X_ERR("PGLUE hw attention 0x%x\n", val); | |
3998 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR) | |
3999 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" | |
4000 | "ADDRESS_ERROR\n"); | |
4001 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR) | |
4002 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" | |
4003 | "INCORRECT_RCV_BEHAVIOR\n"); | |
4004 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) | |
4005 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" | |
4006 | "WAS_ERROR_ATTN\n"); | |
4007 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN) | |
4008 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" | |
4009 | "VF_LENGTH_VIOLATION_ATTN\n"); | |
4010 | if (val & | |
4011 | PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN) | |
4012 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" | |
4013 | "VF_GRC_SPACE_VIOLATION_ATTN\n"); | |
4014 | if (val & | |
4015 | PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN) | |
4016 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" | |
4017 | "VF_MSIX_BAR_VIOLATION_ATTN\n"); | |
4018 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN) | |
4019 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" | |
4020 | "TCPL_ERROR_ATTN\n"); | |
4021 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN) | |
4022 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" | |
4023 | "TCPL_IN_TWO_RCBS_ATTN\n"); | |
4024 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW) | |
4025 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" | |
4026 | "CSSNOOP_FIFO_OVERFLOW\n"); | |
4027 | } | |
4028 | if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) { | |
4029 | val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR); | |
4030 | BNX2X_ERR("ATC hw attention 0x%x\n", val); | |
4031 | if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR) | |
4032 | BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n"); | |
4033 | if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND) | |
4034 | BNX2X_ERR("ATC_ATC_INT_STS_REG" | |
4035 | "_ATC_TCPL_TO_NOT_PEND\n"); | |
4036 | if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS) | |
4037 | BNX2X_ERR("ATC_ATC_INT_STS_REG_" | |
4038 | "ATC_GPA_MULTIPLE_HITS\n"); | |
4039 | if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT) | |
4040 | BNX2X_ERR("ATC_ATC_INT_STS_REG_" | |
4041 | "ATC_RCPL_TO_EMPTY_CNT\n"); | |
4042 | if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR) | |
4043 | BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n"); | |
4044 | if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU) | |
4045 | BNX2X_ERR("ATC_ATC_INT_STS_REG_" | |
4046 | "ATC_IREQ_LESS_THAN_STU\n"); | |
4047 | } | |
4048 | ||
4049 | if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | | |
4050 | AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) { | |
4051 | BNX2X_ERR("FATAL parity attention set4 0x%x\n", | |
4052 | (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | | |
4053 | AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR))); | |
4054 | } | |
4055 | ||
4056 | } | |
4057 | ||
72fd0718 VZ |
4058 | static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted) |
4059 | { | |
4060 | struct attn_route attn, *group_mask; | |
34f80b04 | 4061 | int port = BP_PORT(bp); |
877e9aa4 | 4062 | int index; |
a2fbb9ea ET |
4063 | u32 reg_addr; |
4064 | u32 val; | |
3fcaf2e5 | 4065 | u32 aeu_mask; |
c9ee9206 | 4066 | bool global = false; |
a2fbb9ea ET |
4067 | |
4068 | /* need to take HW lock because MCP or other port might also | |
4069 | try to handle this event */ | |
4a37fb66 | 4070 | bnx2x_acquire_alr(bp); |
a2fbb9ea | 4071 | |
c9ee9206 VZ |
4072 | if (bnx2x_chk_parity_attn(bp, &global, true)) { |
4073 | #ifndef BNX2X_STOP_ON_ERROR | |
72fd0718 | 4074 | bp->recovery_state = BNX2X_RECOVERY_INIT; |
7be08a72 | 4075 | schedule_delayed_work(&bp->sp_rtnl_task, 0); |
72fd0718 VZ |
4076 | /* Disable HW interrupts */ |
4077 | bnx2x_int_disable(bp); | |
72fd0718 VZ |
4078 | /* In case of parity errors don't handle attentions so that |
4079 | * other function would "see" parity errors. | |
4080 | */ | |
c9ee9206 VZ |
4081 | #else |
4082 | bnx2x_panic(); | |
4083 | #endif | |
4084 | bnx2x_release_alr(bp); | |
72fd0718 VZ |
4085 | return; |
4086 | } | |
4087 | ||
a2fbb9ea ET |
4088 | attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4); |
4089 | attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4); | |
4090 | attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4); | |
4091 | attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4); | |
619c5cb6 | 4092 | if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
4093 | attn.sig[4] = |
4094 | REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4); | |
4095 | else | |
4096 | attn.sig[4] = 0; | |
4097 | ||
4098 | DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n", | |
4099 | attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]); | |
a2fbb9ea ET |
4100 | |
4101 | for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) { | |
4102 | if (deasserted & (1 << index)) { | |
72fd0718 | 4103 | group_mask = &bp->attn_group[index]; |
a2fbb9ea | 4104 | |
f2e0899f DK |
4105 | DP(NETIF_MSG_HW, "group[%d]: %08x %08x " |
4106 | "%08x %08x %08x\n", | |
4107 | index, | |
4108 | group_mask->sig[0], group_mask->sig[1], | |
4109 | group_mask->sig[2], group_mask->sig[3], | |
4110 | group_mask->sig[4]); | |
a2fbb9ea | 4111 | |
f2e0899f DK |
4112 | bnx2x_attn_int_deasserted4(bp, |
4113 | attn.sig[4] & group_mask->sig[4]); | |
877e9aa4 | 4114 | bnx2x_attn_int_deasserted3(bp, |
72fd0718 | 4115 | attn.sig[3] & group_mask->sig[3]); |
877e9aa4 | 4116 | bnx2x_attn_int_deasserted1(bp, |
72fd0718 | 4117 | attn.sig[1] & group_mask->sig[1]); |
877e9aa4 | 4118 | bnx2x_attn_int_deasserted2(bp, |
72fd0718 | 4119 | attn.sig[2] & group_mask->sig[2]); |
877e9aa4 | 4120 | bnx2x_attn_int_deasserted0(bp, |
72fd0718 | 4121 | attn.sig[0] & group_mask->sig[0]); |
a2fbb9ea ET |
4122 | } |
4123 | } | |
4124 | ||
4a37fb66 | 4125 | bnx2x_release_alr(bp); |
a2fbb9ea | 4126 | |
f2e0899f DK |
4127 | if (bp->common.int_block == INT_BLOCK_HC) |
4128 | reg_addr = (HC_REG_COMMAND_REG + port*32 + | |
4129 | COMMAND_REG_ATTN_BITS_CLR); | |
4130 | else | |
4131 | reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8); | |
a2fbb9ea ET |
4132 | |
4133 | val = ~deasserted; | |
f2e0899f DK |
4134 | DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val, |
4135 | (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr); | |
5c862848 | 4136 | REG_WR(bp, reg_addr, val); |
a2fbb9ea | 4137 | |
a2fbb9ea | 4138 | if (~bp->attn_state & deasserted) |
3fcaf2e5 | 4139 | BNX2X_ERR("IGU ERROR\n"); |
a2fbb9ea ET |
4140 | |
4141 | reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : | |
4142 | MISC_REG_AEU_MASK_ATTN_FUNC_0; | |
4143 | ||
3fcaf2e5 EG |
4144 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); |
4145 | aeu_mask = REG_RD(bp, reg_addr); | |
4146 | ||
4147 | DP(NETIF_MSG_HW, "aeu_mask %x newly deasserted %x\n", | |
4148 | aeu_mask, deasserted); | |
72fd0718 | 4149 | aeu_mask |= (deasserted & 0x3ff); |
3fcaf2e5 | 4150 | DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask); |
a2fbb9ea | 4151 | |
3fcaf2e5 EG |
4152 | REG_WR(bp, reg_addr, aeu_mask); |
4153 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); | |
a2fbb9ea ET |
4154 | |
4155 | DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state); | |
4156 | bp->attn_state &= ~deasserted; | |
4157 | DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state); | |
4158 | } | |
4159 | ||
4160 | static void bnx2x_attn_int(struct bnx2x *bp) | |
4161 | { | |
4162 | /* read local copy of bits */ | |
68d59484 EG |
4163 | u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block. |
4164 | attn_bits); | |
4165 | u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block. | |
4166 | attn_bits_ack); | |
a2fbb9ea ET |
4167 | u32 attn_state = bp->attn_state; |
4168 | ||
4169 | /* look for changed bits */ | |
4170 | u32 asserted = attn_bits & ~attn_ack & ~attn_state; | |
4171 | u32 deasserted = ~attn_bits & attn_ack & attn_state; | |
4172 | ||
4173 | DP(NETIF_MSG_HW, | |
4174 | "attn_bits %x attn_ack %x asserted %x deasserted %x\n", | |
4175 | attn_bits, attn_ack, asserted, deasserted); | |
4176 | ||
4177 | if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state)) | |
34f80b04 | 4178 | BNX2X_ERR("BAD attention state\n"); |
a2fbb9ea ET |
4179 | |
4180 | /* handle bits that were raised */ | |
4181 | if (asserted) | |
4182 | bnx2x_attn_int_asserted(bp, asserted); | |
4183 | ||
4184 | if (deasserted) | |
4185 | bnx2x_attn_int_deasserted(bp, deasserted); | |
4186 | } | |
4187 | ||
619c5cb6 VZ |
4188 | void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment, |
4189 | u16 index, u8 op, u8 update) | |
4190 | { | |
4191 | u32 igu_addr = BAR_IGU_INTMEM + (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8; | |
4192 | ||
4193 | bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update, | |
4194 | igu_addr); | |
4195 | } | |
4196 | ||
523224a3 DK |
4197 | static inline void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod) |
4198 | { | |
4199 | /* No memory barriers */ | |
4200 | storm_memset_eq_prod(bp, prod, BP_FUNC(bp)); | |
4201 | mmiowb(); /* keep prod updates ordered */ | |
4202 | } | |
4203 | ||
4204 | #ifdef BCM_CNIC | |
4205 | static int bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid, | |
4206 | union event_ring_elem *elem) | |
4207 | { | |
619c5cb6 VZ |
4208 | u8 err = elem->message.error; |
4209 | ||
523224a3 | 4210 | if (!bp->cnic_eth_dev.starting_cid || |
c3a8ce61 VZ |
4211 | (cid < bp->cnic_eth_dev.starting_cid && |
4212 | cid != bp->cnic_eth_dev.iscsi_l2_cid)) | |
523224a3 DK |
4213 | return 1; |
4214 | ||
4215 | DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid); | |
4216 | ||
619c5cb6 VZ |
4217 | if (unlikely(err)) { |
4218 | ||
523224a3 DK |
4219 | BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n", |
4220 | cid); | |
4221 | bnx2x_panic_dump(bp); | |
4222 | } | |
619c5cb6 | 4223 | bnx2x_cnic_cfc_comp(bp, cid, err); |
523224a3 DK |
4224 | return 0; |
4225 | } | |
4226 | #endif | |
4227 | ||
619c5cb6 VZ |
4228 | static inline void bnx2x_handle_mcast_eqe(struct bnx2x *bp) |
4229 | { | |
4230 | struct bnx2x_mcast_ramrod_params rparam; | |
4231 | int rc; | |
4232 | ||
4233 | memset(&rparam, 0, sizeof(rparam)); | |
4234 | ||
4235 | rparam.mcast_obj = &bp->mcast_obj; | |
4236 | ||
4237 | netif_addr_lock_bh(bp->dev); | |
4238 | ||
4239 | /* Clear pending state for the last command */ | |
4240 | bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw); | |
4241 | ||
4242 | /* If there are pending mcast commands - send them */ | |
4243 | if (bp->mcast_obj.check_pending(&bp->mcast_obj)) { | |
4244 | rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT); | |
4245 | if (rc < 0) | |
4246 | BNX2X_ERR("Failed to send pending mcast commands: %d\n", | |
4247 | rc); | |
4248 | } | |
4249 | ||
4250 | netif_addr_unlock_bh(bp->dev); | |
4251 | } | |
4252 | ||
4253 | static inline void bnx2x_handle_classification_eqe(struct bnx2x *bp, | |
4254 | union event_ring_elem *elem) | |
4255 | { | |
4256 | unsigned long ramrod_flags = 0; | |
4257 | int rc = 0; | |
4258 | u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK; | |
4259 | struct bnx2x_vlan_mac_obj *vlan_mac_obj; | |
4260 | ||
4261 | /* Always push next commands out, don't wait here */ | |
4262 | __set_bit(RAMROD_CONT, &ramrod_flags); | |
4263 | ||
4264 | switch (elem->message.data.eth_event.echo >> BNX2X_SWCID_SHIFT) { | |
4265 | case BNX2X_FILTER_MAC_PENDING: | |
4266 | #ifdef BCM_CNIC | |
4267 | if (cid == BNX2X_ISCSI_ETH_CID) | |
4268 | vlan_mac_obj = &bp->iscsi_l2_mac_obj; | |
4269 | else | |
4270 | #endif | |
4271 | vlan_mac_obj = &bp->fp[cid].mac_obj; | |
4272 | ||
4273 | break; | |
4274 | vlan_mac_obj = &bp->fp[cid].mac_obj; | |
4275 | ||
4276 | case BNX2X_FILTER_MCAST_PENDING: | |
4277 | /* This is only relevant for 57710 where multicast MACs are | |
4278 | * configured as unicast MACs using the same ramrod. | |
4279 | */ | |
4280 | bnx2x_handle_mcast_eqe(bp); | |
4281 | return; | |
4282 | default: | |
4283 | BNX2X_ERR("Unsupported classification command: %d\n", | |
4284 | elem->message.data.eth_event.echo); | |
4285 | return; | |
4286 | } | |
4287 | ||
4288 | rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags); | |
4289 | ||
4290 | if (rc < 0) | |
4291 | BNX2X_ERR("Failed to schedule new commands: %d\n", rc); | |
4292 | else if (rc > 0) | |
4293 | DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n"); | |
4294 | ||
4295 | } | |
4296 | ||
4297 | #ifdef BCM_CNIC | |
4298 | static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start); | |
4299 | #endif | |
4300 | ||
4301 | static inline void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp) | |
4302 | { | |
4303 | netif_addr_lock_bh(bp->dev); | |
4304 | ||
4305 | clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state); | |
4306 | ||
4307 | /* Send rx_mode command again if was requested */ | |
4308 | if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state)) | |
4309 | bnx2x_set_storm_rx_mode(bp); | |
4310 | #ifdef BCM_CNIC | |
4311 | else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, | |
4312 | &bp->sp_state)) | |
4313 | bnx2x_set_iscsi_eth_rx_mode(bp, true); | |
4314 | else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, | |
4315 | &bp->sp_state)) | |
4316 | bnx2x_set_iscsi_eth_rx_mode(bp, false); | |
4317 | #endif | |
4318 | ||
4319 | netif_addr_unlock_bh(bp->dev); | |
4320 | } | |
4321 | ||
4322 | static inline struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj( | |
4323 | struct bnx2x *bp, u32 cid) | |
4324 | { | |
6383c0b3 | 4325 | DP(BNX2X_MSG_SP, "retrieving fp from cid %d", cid); |
619c5cb6 VZ |
4326 | #ifdef BCM_CNIC |
4327 | if (cid == BNX2X_FCOE_ETH_CID) | |
4328 | return &bnx2x_fcoe(bp, q_obj); | |
4329 | else | |
4330 | #endif | |
6383c0b3 | 4331 | return &bnx2x_fp(bp, CID_TO_FP(cid), q_obj); |
619c5cb6 VZ |
4332 | } |
4333 | ||
523224a3 DK |
4334 | static void bnx2x_eq_int(struct bnx2x *bp) |
4335 | { | |
4336 | u16 hw_cons, sw_cons, sw_prod; | |
4337 | union event_ring_elem *elem; | |
4338 | u32 cid; | |
4339 | u8 opcode; | |
4340 | int spqe_cnt = 0; | |
619c5cb6 VZ |
4341 | struct bnx2x_queue_sp_obj *q_obj; |
4342 | struct bnx2x_func_sp_obj *f_obj = &bp->func_obj; | |
4343 | struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw; | |
523224a3 DK |
4344 | |
4345 | hw_cons = le16_to_cpu(*bp->eq_cons_sb); | |
4346 | ||
4347 | /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256. | |
4348 | * when we get the the next-page we nned to adjust so the loop | |
4349 | * condition below will be met. The next element is the size of a | |
4350 | * regular element and hence incrementing by 1 | |
4351 | */ | |
4352 | if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE) | |
4353 | hw_cons++; | |
4354 | ||
25985edc | 4355 | /* This function may never run in parallel with itself for a |
523224a3 DK |
4356 | * specific bp, thus there is no need in "paired" read memory |
4357 | * barrier here. | |
4358 | */ | |
4359 | sw_cons = bp->eq_cons; | |
4360 | sw_prod = bp->eq_prod; | |
4361 | ||
6e30dd4e VZ |
4362 | DP(BNX2X_MSG_SP, "EQ: hw_cons %u sw_cons %u bp->cq_spq_left %u\n", |
4363 | hw_cons, sw_cons, atomic_read(&bp->eq_spq_left)); | |
523224a3 DK |
4364 | |
4365 | for (; sw_cons != hw_cons; | |
4366 | sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) { | |
4367 | ||
4368 | ||
4369 | elem = &bp->eq_ring[EQ_DESC(sw_cons)]; | |
4370 | ||
4371 | cid = SW_CID(elem->message.data.cfc_del_event.cid); | |
4372 | opcode = elem->message.opcode; | |
4373 | ||
4374 | ||
4375 | /* handle eq element */ | |
4376 | switch (opcode) { | |
4377 | case EVENT_RING_OPCODE_STAT_QUERY: | |
619c5cb6 VZ |
4378 | DP(NETIF_MSG_TIMER, "got statistics comp event %d\n", |
4379 | bp->stats_comp++); | |
523224a3 DK |
4380 | /* nothing to do with stats comp */ |
4381 | continue; | |
4382 | ||
4383 | case EVENT_RING_OPCODE_CFC_DEL: | |
4384 | /* handle according to cid range */ | |
4385 | /* | |
4386 | * we may want to verify here that the bp state is | |
4387 | * HALTING | |
4388 | */ | |
4389 | DP(NETIF_MSG_IFDOWN, | |
4390 | "got delete ramrod for MULTI[%d]\n", cid); | |
4391 | #ifdef BCM_CNIC | |
4392 | if (!bnx2x_cnic_handle_cfc_del(bp, cid, elem)) | |
4393 | goto next_spqe; | |
4394 | #endif | |
619c5cb6 VZ |
4395 | q_obj = bnx2x_cid_to_q_obj(bp, cid); |
4396 | ||
4397 | if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL)) | |
4398 | break; | |
4399 | ||
4400 | ||
523224a3 DK |
4401 | |
4402 | goto next_spqe; | |
e4901dde VZ |
4403 | |
4404 | case EVENT_RING_OPCODE_STOP_TRAFFIC: | |
4405 | DP(NETIF_MSG_IFUP, "got STOP TRAFFIC\n"); | |
6debea87 DK |
4406 | if (f_obj->complete_cmd(bp, f_obj, |
4407 | BNX2X_F_CMD_TX_STOP)) | |
4408 | break; | |
e4901dde VZ |
4409 | bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED); |
4410 | goto next_spqe; | |
619c5cb6 | 4411 | |
e4901dde VZ |
4412 | case EVENT_RING_OPCODE_START_TRAFFIC: |
4413 | DP(NETIF_MSG_IFUP, "got START TRAFFIC\n"); | |
6debea87 DK |
4414 | if (f_obj->complete_cmd(bp, f_obj, |
4415 | BNX2X_F_CMD_TX_START)) | |
4416 | break; | |
e4901dde VZ |
4417 | bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED); |
4418 | goto next_spqe; | |
619c5cb6 VZ |
4419 | case EVENT_RING_OPCODE_FUNCTION_START: |
4420 | DP(NETIF_MSG_IFUP, "got FUNC_START ramrod\n"); | |
4421 | if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START)) | |
4422 | break; | |
4423 | ||
4424 | goto next_spqe; | |
4425 | ||
4426 | case EVENT_RING_OPCODE_FUNCTION_STOP: | |
4427 | DP(NETIF_MSG_IFDOWN, "got FUNC_STOP ramrod\n"); | |
4428 | if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP)) | |
4429 | break; | |
4430 | ||
4431 | goto next_spqe; | |
523224a3 DK |
4432 | } |
4433 | ||
4434 | switch (opcode | bp->state) { | |
619c5cb6 VZ |
4435 | case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | |
4436 | BNX2X_STATE_OPEN): | |
4437 | case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | | |
523224a3 | 4438 | BNX2X_STATE_OPENING_WAIT4_PORT): |
619c5cb6 VZ |
4439 | cid = elem->message.data.eth_event.echo & |
4440 | BNX2X_SWCID_MASK; | |
4441 | DP(NETIF_MSG_IFUP, "got RSS_UPDATE ramrod. CID %d\n", | |
4442 | cid); | |
4443 | rss_raw->clear_pending(rss_raw); | |
523224a3 DK |
4444 | break; |
4445 | ||
619c5cb6 VZ |
4446 | case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN): |
4447 | case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG): | |
4448 | case (EVENT_RING_OPCODE_SET_MAC | | |
523224a3 | 4449 | BNX2X_STATE_CLOSING_WAIT4_HALT): |
619c5cb6 VZ |
4450 | case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | |
4451 | BNX2X_STATE_OPEN): | |
4452 | case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | | |
4453 | BNX2X_STATE_DIAG): | |
4454 | case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | | |
4455 | BNX2X_STATE_CLOSING_WAIT4_HALT): | |
4456 | DP(NETIF_MSG_IFUP, "got (un)set mac ramrod\n"); | |
4457 | bnx2x_handle_classification_eqe(bp, elem); | |
523224a3 DK |
4458 | break; |
4459 | ||
619c5cb6 VZ |
4460 | case (EVENT_RING_OPCODE_MULTICAST_RULES | |
4461 | BNX2X_STATE_OPEN): | |
4462 | case (EVENT_RING_OPCODE_MULTICAST_RULES | | |
4463 | BNX2X_STATE_DIAG): | |
4464 | case (EVENT_RING_OPCODE_MULTICAST_RULES | | |
4465 | BNX2X_STATE_CLOSING_WAIT4_HALT): | |
4466 | DP(NETIF_MSG_IFUP, "got mcast ramrod\n"); | |
4467 | bnx2x_handle_mcast_eqe(bp); | |
523224a3 DK |
4468 | break; |
4469 | ||
619c5cb6 VZ |
4470 | case (EVENT_RING_OPCODE_FILTERS_RULES | |
4471 | BNX2X_STATE_OPEN): | |
4472 | case (EVENT_RING_OPCODE_FILTERS_RULES | | |
4473 | BNX2X_STATE_DIAG): | |
4474 | case (EVENT_RING_OPCODE_FILTERS_RULES | | |
523224a3 | 4475 | BNX2X_STATE_CLOSING_WAIT4_HALT): |
619c5cb6 VZ |
4476 | DP(NETIF_MSG_IFUP, "got rx_mode ramrod\n"); |
4477 | bnx2x_handle_rx_mode_eqe(bp); | |
523224a3 DK |
4478 | break; |
4479 | default: | |
4480 | /* unknown event log error and continue */ | |
619c5cb6 VZ |
4481 | BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n", |
4482 | elem->message.opcode, bp->state); | |
523224a3 DK |
4483 | } |
4484 | next_spqe: | |
4485 | spqe_cnt++; | |
4486 | } /* for */ | |
4487 | ||
8fe23fbd | 4488 | smp_mb__before_atomic_inc(); |
6e30dd4e | 4489 | atomic_add(spqe_cnt, &bp->eq_spq_left); |
523224a3 DK |
4490 | |
4491 | bp->eq_cons = sw_cons; | |
4492 | bp->eq_prod = sw_prod; | |
4493 | /* Make sure that above mem writes were issued towards the memory */ | |
4494 | smp_wmb(); | |
4495 | ||
4496 | /* update producer */ | |
4497 | bnx2x_update_eq_prod(bp, bp->eq_prod); | |
4498 | } | |
4499 | ||
a2fbb9ea ET |
4500 | static void bnx2x_sp_task(struct work_struct *work) |
4501 | { | |
1cf167f2 | 4502 | struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work); |
a2fbb9ea ET |
4503 | u16 status; |
4504 | ||
a2fbb9ea | 4505 | status = bnx2x_update_dsb_idx(bp); |
34f80b04 EG |
4506 | /* if (status == 0) */ |
4507 | /* BNX2X_ERR("spurious slowpath interrupt!\n"); */ | |
a2fbb9ea | 4508 | |
cdaa7cb8 | 4509 | DP(NETIF_MSG_INTR, "got a slowpath interrupt (status 0x%x)\n", status); |
a2fbb9ea | 4510 | |
877e9aa4 | 4511 | /* HW attentions */ |
523224a3 | 4512 | if (status & BNX2X_DEF_SB_ATT_IDX) { |
a2fbb9ea | 4513 | bnx2x_attn_int(bp); |
523224a3 | 4514 | status &= ~BNX2X_DEF_SB_ATT_IDX; |
cdaa7cb8 VZ |
4515 | } |
4516 | ||
523224a3 DK |
4517 | /* SP events: STAT_QUERY and others */ |
4518 | if (status & BNX2X_DEF_SB_IDX) { | |
ec6ba945 VZ |
4519 | #ifdef BCM_CNIC |
4520 | struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp); | |
523224a3 | 4521 | |
ec6ba945 | 4522 | if ((!NO_FCOE(bp)) && |
019dbb4c VZ |
4523 | (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) { |
4524 | /* | |
4525 | * Prevent local bottom-halves from running as | |
4526 | * we are going to change the local NAPI list. | |
4527 | */ | |
4528 | local_bh_disable(); | |
ec6ba945 | 4529 | napi_schedule(&bnx2x_fcoe(bp, napi)); |
019dbb4c VZ |
4530 | local_bh_enable(); |
4531 | } | |
ec6ba945 | 4532 | #endif |
523224a3 DK |
4533 | /* Handle EQ completions */ |
4534 | bnx2x_eq_int(bp); | |
4535 | ||
4536 | bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, | |
4537 | le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1); | |
4538 | ||
4539 | status &= ~BNX2X_DEF_SB_IDX; | |
cdaa7cb8 VZ |
4540 | } |
4541 | ||
4542 | if (unlikely(status)) | |
4543 | DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n", | |
4544 | status); | |
a2fbb9ea | 4545 | |
523224a3 DK |
4546 | bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID, |
4547 | le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1); | |
a2fbb9ea ET |
4548 | } |
4549 | ||
9f6c9258 | 4550 | irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance) |
a2fbb9ea ET |
4551 | { |
4552 | struct net_device *dev = dev_instance; | |
4553 | struct bnx2x *bp = netdev_priv(dev); | |
4554 | ||
523224a3 DK |
4555 | bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, |
4556 | IGU_INT_DISABLE, 0); | |
a2fbb9ea ET |
4557 | |
4558 | #ifdef BNX2X_STOP_ON_ERROR | |
4559 | if (unlikely(bp->panic)) | |
4560 | return IRQ_HANDLED; | |
4561 | #endif | |
4562 | ||
993ac7b5 MC |
4563 | #ifdef BCM_CNIC |
4564 | { | |
4565 | struct cnic_ops *c_ops; | |
4566 | ||
4567 | rcu_read_lock(); | |
4568 | c_ops = rcu_dereference(bp->cnic_ops); | |
4569 | if (c_ops) | |
4570 | c_ops->cnic_handler(bp->cnic_data, NULL); | |
4571 | rcu_read_unlock(); | |
4572 | } | |
4573 | #endif | |
1cf167f2 | 4574 | queue_delayed_work(bnx2x_wq, &bp->sp_task, 0); |
a2fbb9ea ET |
4575 | |
4576 | return IRQ_HANDLED; | |
4577 | } | |
4578 | ||
4579 | /* end of slow path */ | |
4580 | ||
619c5cb6 VZ |
4581 | |
4582 | void bnx2x_drv_pulse(struct bnx2x *bp) | |
4583 | { | |
4584 | SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb, | |
4585 | bp->fw_drv_pulse_wr_seq); | |
4586 | } | |
4587 | ||
4588 | ||
a2fbb9ea ET |
4589 | static void bnx2x_timer(unsigned long data) |
4590 | { | |
6383c0b3 | 4591 | u8 cos; |
a2fbb9ea ET |
4592 | struct bnx2x *bp = (struct bnx2x *) data; |
4593 | ||
4594 | if (!netif_running(bp->dev)) | |
4595 | return; | |
4596 | ||
a2fbb9ea ET |
4597 | if (poll) { |
4598 | struct bnx2x_fastpath *fp = &bp->fp[0]; | |
a2fbb9ea | 4599 | |
6383c0b3 AE |
4600 | for_each_cos_in_tx_queue(fp, cos) |
4601 | bnx2x_tx_int(bp, &fp->txdata[cos]); | |
b8ee8328 | 4602 | bnx2x_rx_int(fp, 1000); |
a2fbb9ea ET |
4603 | } |
4604 | ||
34f80b04 | 4605 | if (!BP_NOMCP(bp)) { |
f2e0899f | 4606 | int mb_idx = BP_FW_MB_IDX(bp); |
a2fbb9ea ET |
4607 | u32 drv_pulse; |
4608 | u32 mcp_pulse; | |
4609 | ||
4610 | ++bp->fw_drv_pulse_wr_seq; | |
4611 | bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK; | |
4612 | /* TBD - add SYSTEM_TIME */ | |
4613 | drv_pulse = bp->fw_drv_pulse_wr_seq; | |
619c5cb6 | 4614 | bnx2x_drv_pulse(bp); |
a2fbb9ea | 4615 | |
f2e0899f | 4616 | mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) & |
a2fbb9ea ET |
4617 | MCP_PULSE_SEQ_MASK); |
4618 | /* The delta between driver pulse and mcp response | |
4619 | * should be 1 (before mcp response) or 0 (after mcp response) | |
4620 | */ | |
4621 | if ((drv_pulse != mcp_pulse) && | |
4622 | (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) { | |
4623 | /* someone lost a heartbeat... */ | |
4624 | BNX2X_ERR("drv_pulse (0x%x) != mcp_pulse (0x%x)\n", | |
4625 | drv_pulse, mcp_pulse); | |
4626 | } | |
4627 | } | |
4628 | ||
f34d28ea | 4629 | if (bp->state == BNX2X_STATE_OPEN) |
bb2a0f7a | 4630 | bnx2x_stats_handle(bp, STATS_EVENT_UPDATE); |
a2fbb9ea | 4631 | |
a2fbb9ea ET |
4632 | mod_timer(&bp->timer, jiffies + bp->current_interval); |
4633 | } | |
4634 | ||
4635 | /* end of Statistics */ | |
4636 | ||
4637 | /* nic init */ | |
4638 | ||
4639 | /* | |
4640 | * nic init service functions | |
4641 | */ | |
4642 | ||
523224a3 | 4643 | static inline void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len) |
a2fbb9ea | 4644 | { |
523224a3 DK |
4645 | u32 i; |
4646 | if (!(len%4) && !(addr%4)) | |
4647 | for (i = 0; i < len; i += 4) | |
4648 | REG_WR(bp, addr + i, fill); | |
4649 | else | |
4650 | for (i = 0; i < len; i++) | |
4651 | REG_WR8(bp, addr + i, fill); | |
34f80b04 | 4652 | |
34f80b04 EG |
4653 | } |
4654 | ||
523224a3 DK |
4655 | /* helper: writes FP SP data to FW - data_size in dwords */ |
4656 | static inline void bnx2x_wr_fp_sb_data(struct bnx2x *bp, | |
4657 | int fw_sb_id, | |
4658 | u32 *sb_data_p, | |
4659 | u32 data_size) | |
34f80b04 | 4660 | { |
a2fbb9ea | 4661 | int index; |
523224a3 DK |
4662 | for (index = 0; index < data_size; index++) |
4663 | REG_WR(bp, BAR_CSTRORM_INTMEM + | |
4664 | CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) + | |
4665 | sizeof(u32)*index, | |
4666 | *(sb_data_p + index)); | |
4667 | } | |
a2fbb9ea | 4668 | |
523224a3 DK |
4669 | static inline void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id) |
4670 | { | |
4671 | u32 *sb_data_p; | |
4672 | u32 data_size = 0; | |
f2e0899f | 4673 | struct hc_status_block_data_e2 sb_data_e2; |
523224a3 | 4674 | struct hc_status_block_data_e1x sb_data_e1x; |
a2fbb9ea | 4675 | |
523224a3 | 4676 | /* disable the function first */ |
619c5cb6 | 4677 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f | 4678 | memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2)); |
619c5cb6 | 4679 | sb_data_e2.common.state = SB_DISABLED; |
f2e0899f DK |
4680 | sb_data_e2.common.p_func.vf_valid = false; |
4681 | sb_data_p = (u32 *)&sb_data_e2; | |
4682 | data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32); | |
4683 | } else { | |
4684 | memset(&sb_data_e1x, 0, | |
4685 | sizeof(struct hc_status_block_data_e1x)); | |
619c5cb6 | 4686 | sb_data_e1x.common.state = SB_DISABLED; |
f2e0899f DK |
4687 | sb_data_e1x.common.p_func.vf_valid = false; |
4688 | sb_data_p = (u32 *)&sb_data_e1x; | |
4689 | data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32); | |
4690 | } | |
523224a3 | 4691 | bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size); |
a2fbb9ea | 4692 | |
523224a3 DK |
4693 | bnx2x_fill(bp, BAR_CSTRORM_INTMEM + |
4694 | CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0, | |
4695 | CSTORM_STATUS_BLOCK_SIZE); | |
4696 | bnx2x_fill(bp, BAR_CSTRORM_INTMEM + | |
4697 | CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0, | |
4698 | CSTORM_SYNC_BLOCK_SIZE); | |
4699 | } | |
34f80b04 | 4700 | |
523224a3 DK |
4701 | /* helper: writes SP SB data to FW */ |
4702 | static inline void bnx2x_wr_sp_sb_data(struct bnx2x *bp, | |
4703 | struct hc_sp_status_block_data *sp_sb_data) | |
4704 | { | |
4705 | int func = BP_FUNC(bp); | |
4706 | int i; | |
4707 | for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++) | |
4708 | REG_WR(bp, BAR_CSTRORM_INTMEM + | |
4709 | CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) + | |
4710 | i*sizeof(u32), | |
4711 | *((u32 *)sp_sb_data + i)); | |
34f80b04 EG |
4712 | } |
4713 | ||
523224a3 | 4714 | static inline void bnx2x_zero_sp_sb(struct bnx2x *bp) |
34f80b04 EG |
4715 | { |
4716 | int func = BP_FUNC(bp); | |
523224a3 DK |
4717 | struct hc_sp_status_block_data sp_sb_data; |
4718 | memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data)); | |
a2fbb9ea | 4719 | |
619c5cb6 | 4720 | sp_sb_data.state = SB_DISABLED; |
523224a3 DK |
4721 | sp_sb_data.p_func.vf_valid = false; |
4722 | ||
4723 | bnx2x_wr_sp_sb_data(bp, &sp_sb_data); | |
4724 | ||
4725 | bnx2x_fill(bp, BAR_CSTRORM_INTMEM + | |
4726 | CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0, | |
4727 | CSTORM_SP_STATUS_BLOCK_SIZE); | |
4728 | bnx2x_fill(bp, BAR_CSTRORM_INTMEM + | |
4729 | CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0, | |
4730 | CSTORM_SP_SYNC_BLOCK_SIZE); | |
4731 | ||
4732 | } | |
4733 | ||
4734 | ||
4735 | static inline | |
4736 | void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm, | |
4737 | int igu_sb_id, int igu_seg_id) | |
4738 | { | |
4739 | hc_sm->igu_sb_id = igu_sb_id; | |
4740 | hc_sm->igu_seg_id = igu_seg_id; | |
4741 | hc_sm->timer_value = 0xFF; | |
4742 | hc_sm->time_to_expire = 0xFFFFFFFF; | |
a2fbb9ea ET |
4743 | } |
4744 | ||
8d96286a | 4745 | static void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid, |
523224a3 | 4746 | u8 vf_valid, int fw_sb_id, int igu_sb_id) |
a2fbb9ea | 4747 | { |
523224a3 DK |
4748 | int igu_seg_id; |
4749 | ||
f2e0899f | 4750 | struct hc_status_block_data_e2 sb_data_e2; |
523224a3 DK |
4751 | struct hc_status_block_data_e1x sb_data_e1x; |
4752 | struct hc_status_block_sm *hc_sm_p; | |
523224a3 DK |
4753 | int data_size; |
4754 | u32 *sb_data_p; | |
4755 | ||
f2e0899f DK |
4756 | if (CHIP_INT_MODE_IS_BC(bp)) |
4757 | igu_seg_id = HC_SEG_ACCESS_NORM; | |
4758 | else | |
4759 | igu_seg_id = IGU_SEG_ACCESS_NORM; | |
523224a3 DK |
4760 | |
4761 | bnx2x_zero_fp_sb(bp, fw_sb_id); | |
4762 | ||
619c5cb6 | 4763 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f | 4764 | memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2)); |
619c5cb6 | 4765 | sb_data_e2.common.state = SB_ENABLED; |
f2e0899f DK |
4766 | sb_data_e2.common.p_func.pf_id = BP_FUNC(bp); |
4767 | sb_data_e2.common.p_func.vf_id = vfid; | |
4768 | sb_data_e2.common.p_func.vf_valid = vf_valid; | |
4769 | sb_data_e2.common.p_func.vnic_id = BP_VN(bp); | |
4770 | sb_data_e2.common.same_igu_sb_1b = true; | |
4771 | sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping); | |
4772 | sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping); | |
4773 | hc_sm_p = sb_data_e2.common.state_machine; | |
f2e0899f DK |
4774 | sb_data_p = (u32 *)&sb_data_e2; |
4775 | data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32); | |
4776 | } else { | |
4777 | memset(&sb_data_e1x, 0, | |
4778 | sizeof(struct hc_status_block_data_e1x)); | |
619c5cb6 | 4779 | sb_data_e1x.common.state = SB_ENABLED; |
f2e0899f DK |
4780 | sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp); |
4781 | sb_data_e1x.common.p_func.vf_id = 0xff; | |
4782 | sb_data_e1x.common.p_func.vf_valid = false; | |
4783 | sb_data_e1x.common.p_func.vnic_id = BP_VN(bp); | |
4784 | sb_data_e1x.common.same_igu_sb_1b = true; | |
4785 | sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping); | |
4786 | sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping); | |
4787 | hc_sm_p = sb_data_e1x.common.state_machine; | |
f2e0899f DK |
4788 | sb_data_p = (u32 *)&sb_data_e1x; |
4789 | data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32); | |
4790 | } | |
523224a3 DK |
4791 | |
4792 | bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID], | |
4793 | igu_sb_id, igu_seg_id); | |
4794 | bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID], | |
4795 | igu_sb_id, igu_seg_id); | |
4796 | ||
4797 | DP(NETIF_MSG_HW, "Init FW SB %d\n", fw_sb_id); | |
4798 | ||
4799 | /* write indecies to HW */ | |
4800 | bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size); | |
4801 | } | |
4802 | ||
619c5cb6 | 4803 | static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id, |
523224a3 DK |
4804 | u16 tx_usec, u16 rx_usec) |
4805 | { | |
6383c0b3 | 4806 | bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS, |
523224a3 | 4807 | false, rx_usec); |
6383c0b3 AE |
4808 | bnx2x_update_coalesce_sb_index(bp, fw_sb_id, |
4809 | HC_INDEX_ETH_TX_CQ_CONS_COS0, false, | |
4810 | tx_usec); | |
4811 | bnx2x_update_coalesce_sb_index(bp, fw_sb_id, | |
4812 | HC_INDEX_ETH_TX_CQ_CONS_COS1, false, | |
4813 | tx_usec); | |
4814 | bnx2x_update_coalesce_sb_index(bp, fw_sb_id, | |
4815 | HC_INDEX_ETH_TX_CQ_CONS_COS2, false, | |
4816 | tx_usec); | |
523224a3 | 4817 | } |
f2e0899f | 4818 | |
523224a3 DK |
4819 | static void bnx2x_init_def_sb(struct bnx2x *bp) |
4820 | { | |
4821 | struct host_sp_status_block *def_sb = bp->def_status_blk; | |
4822 | dma_addr_t mapping = bp->def_status_blk_mapping; | |
4823 | int igu_sp_sb_index; | |
4824 | int igu_seg_id; | |
34f80b04 EG |
4825 | int port = BP_PORT(bp); |
4826 | int func = BP_FUNC(bp); | |
523224a3 | 4827 | int reg_offset; |
a2fbb9ea | 4828 | u64 section; |
523224a3 DK |
4829 | int index; |
4830 | struct hc_sp_status_block_data sp_sb_data; | |
4831 | memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data)); | |
4832 | ||
f2e0899f DK |
4833 | if (CHIP_INT_MODE_IS_BC(bp)) { |
4834 | igu_sp_sb_index = DEF_SB_IGU_ID; | |
4835 | igu_seg_id = HC_SEG_ACCESS_DEF; | |
4836 | } else { | |
4837 | igu_sp_sb_index = bp->igu_dsb_id; | |
4838 | igu_seg_id = IGU_SEG_ACCESS_DEF; | |
4839 | } | |
a2fbb9ea ET |
4840 | |
4841 | /* ATTN */ | |
523224a3 | 4842 | section = ((u64)mapping) + offsetof(struct host_sp_status_block, |
a2fbb9ea | 4843 | atten_status_block); |
523224a3 | 4844 | def_sb->atten_status_block.status_block_id = igu_sp_sb_index; |
a2fbb9ea | 4845 | |
49d66772 ET |
4846 | bp->attn_state = 0; |
4847 | ||
a2fbb9ea ET |
4848 | reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : |
4849 | MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); | |
34f80b04 | 4850 | for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) { |
523224a3 DK |
4851 | int sindex; |
4852 | /* take care of sig[0]..sig[4] */ | |
4853 | for (sindex = 0; sindex < 4; sindex++) | |
4854 | bp->attn_group[index].sig[sindex] = | |
4855 | REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index); | |
f2e0899f | 4856 | |
619c5cb6 | 4857 | if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
4858 | /* |
4859 | * enable5 is separate from the rest of the registers, | |
4860 | * and therefore the address skip is 4 | |
4861 | * and not 16 between the different groups | |
4862 | */ | |
4863 | bp->attn_group[index].sig[4] = REG_RD(bp, | |
4864 | reg_offset + 0x10 + 0x4*index); | |
4865 | else | |
4866 | bp->attn_group[index].sig[4] = 0; | |
a2fbb9ea ET |
4867 | } |
4868 | ||
f2e0899f DK |
4869 | if (bp->common.int_block == INT_BLOCK_HC) { |
4870 | reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L : | |
4871 | HC_REG_ATTN_MSG0_ADDR_L); | |
4872 | ||
4873 | REG_WR(bp, reg_offset, U64_LO(section)); | |
4874 | REG_WR(bp, reg_offset + 4, U64_HI(section)); | |
619c5cb6 | 4875 | } else if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
4876 | REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section)); |
4877 | REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section)); | |
4878 | } | |
a2fbb9ea | 4879 | |
523224a3 DK |
4880 | section = ((u64)mapping) + offsetof(struct host_sp_status_block, |
4881 | sp_sb); | |
a2fbb9ea | 4882 | |
523224a3 | 4883 | bnx2x_zero_sp_sb(bp); |
a2fbb9ea | 4884 | |
619c5cb6 | 4885 | sp_sb_data.state = SB_ENABLED; |
523224a3 DK |
4886 | sp_sb_data.host_sb_addr.lo = U64_LO(section); |
4887 | sp_sb_data.host_sb_addr.hi = U64_HI(section); | |
4888 | sp_sb_data.igu_sb_id = igu_sp_sb_index; | |
4889 | sp_sb_data.igu_seg_id = igu_seg_id; | |
4890 | sp_sb_data.p_func.pf_id = func; | |
f2e0899f | 4891 | sp_sb_data.p_func.vnic_id = BP_VN(bp); |
523224a3 | 4892 | sp_sb_data.p_func.vf_id = 0xff; |
a2fbb9ea | 4893 | |
523224a3 | 4894 | bnx2x_wr_sp_sb_data(bp, &sp_sb_data); |
49d66772 | 4895 | |
523224a3 | 4896 | bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0); |
a2fbb9ea ET |
4897 | } |
4898 | ||
9f6c9258 | 4899 | void bnx2x_update_coalesce(struct bnx2x *bp) |
a2fbb9ea | 4900 | { |
a2fbb9ea ET |
4901 | int i; |
4902 | ||
ec6ba945 | 4903 | for_each_eth_queue(bp, i) |
523224a3 | 4904 | bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id, |
423cfa7e | 4905 | bp->tx_ticks, bp->rx_ticks); |
a2fbb9ea ET |
4906 | } |
4907 | ||
a2fbb9ea ET |
4908 | static void bnx2x_init_sp_ring(struct bnx2x *bp) |
4909 | { | |
a2fbb9ea | 4910 | spin_lock_init(&bp->spq_lock); |
6e30dd4e | 4911 | atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING); |
a2fbb9ea | 4912 | |
a2fbb9ea | 4913 | bp->spq_prod_idx = 0; |
a2fbb9ea ET |
4914 | bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX; |
4915 | bp->spq_prod_bd = bp->spq; | |
4916 | bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT; | |
a2fbb9ea ET |
4917 | } |
4918 | ||
523224a3 | 4919 | static void bnx2x_init_eq_ring(struct bnx2x *bp) |
a2fbb9ea ET |
4920 | { |
4921 | int i; | |
523224a3 DK |
4922 | for (i = 1; i <= NUM_EQ_PAGES; i++) { |
4923 | union event_ring_elem *elem = | |
4924 | &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1]; | |
a2fbb9ea | 4925 | |
523224a3 DK |
4926 | elem->next_page.addr.hi = |
4927 | cpu_to_le32(U64_HI(bp->eq_mapping + | |
4928 | BCM_PAGE_SIZE * (i % NUM_EQ_PAGES))); | |
4929 | elem->next_page.addr.lo = | |
4930 | cpu_to_le32(U64_LO(bp->eq_mapping + | |
4931 | BCM_PAGE_SIZE*(i % NUM_EQ_PAGES))); | |
a2fbb9ea | 4932 | } |
523224a3 DK |
4933 | bp->eq_cons = 0; |
4934 | bp->eq_prod = NUM_EQ_DESC; | |
4935 | bp->eq_cons_sb = BNX2X_EQ_INDEX; | |
6e30dd4e VZ |
4936 | /* we want a warning message before it gets rought... */ |
4937 | atomic_set(&bp->eq_spq_left, | |
4938 | min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1); | |
a2fbb9ea ET |
4939 | } |
4940 | ||
619c5cb6 VZ |
4941 | |
4942 | /* called with netif_addr_lock_bh() */ | |
4943 | void bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id, | |
4944 | unsigned long rx_mode_flags, | |
4945 | unsigned long rx_accept_flags, | |
4946 | unsigned long tx_accept_flags, | |
4947 | unsigned long ramrod_flags) | |
ab532cf3 | 4948 | { |
619c5cb6 VZ |
4949 | struct bnx2x_rx_mode_ramrod_params ramrod_param; |
4950 | int rc; | |
4951 | ||
4952 | memset(&ramrod_param, 0, sizeof(ramrod_param)); | |
4953 | ||
4954 | /* Prepare ramrod parameters */ | |
4955 | ramrod_param.cid = 0; | |
4956 | ramrod_param.cl_id = cl_id; | |
4957 | ramrod_param.rx_mode_obj = &bp->rx_mode_obj; | |
4958 | ramrod_param.func_id = BP_FUNC(bp); | |
ab532cf3 | 4959 | |
619c5cb6 VZ |
4960 | ramrod_param.pstate = &bp->sp_state; |
4961 | ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING; | |
ab532cf3 | 4962 | |
619c5cb6 VZ |
4963 | ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata); |
4964 | ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata); | |
4965 | ||
4966 | set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state); | |
4967 | ||
4968 | ramrod_param.ramrod_flags = ramrod_flags; | |
4969 | ramrod_param.rx_mode_flags = rx_mode_flags; | |
4970 | ||
4971 | ramrod_param.rx_accept_flags = rx_accept_flags; | |
4972 | ramrod_param.tx_accept_flags = tx_accept_flags; | |
4973 | ||
4974 | rc = bnx2x_config_rx_mode(bp, &ramrod_param); | |
4975 | if (rc < 0) { | |
4976 | BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode); | |
4977 | return; | |
4978 | } | |
a2fbb9ea ET |
4979 | } |
4980 | ||
619c5cb6 VZ |
4981 | /* called with netif_addr_lock_bh() */ |
4982 | void bnx2x_set_storm_rx_mode(struct bnx2x *bp) | |
471de716 | 4983 | { |
619c5cb6 VZ |
4984 | unsigned long rx_mode_flags = 0, ramrod_flags = 0; |
4985 | unsigned long rx_accept_flags = 0, tx_accept_flags = 0; | |
471de716 | 4986 | |
619c5cb6 VZ |
4987 | #ifdef BCM_CNIC |
4988 | if (!NO_FCOE(bp)) | |
4989 | ||
4990 | /* Configure rx_mode of FCoE Queue */ | |
4991 | __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags); | |
4992 | #endif | |
4993 | ||
4994 | switch (bp->rx_mode) { | |
4995 | case BNX2X_RX_MODE_NONE: | |
4996 | /* | |
4997 | * 'drop all' supersedes any accept flags that may have been | |
4998 | * passed to the function. | |
4999 | */ | |
5000 | break; | |
5001 | case BNX2X_RX_MODE_NORMAL: | |
5002 | __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags); | |
5003 | __set_bit(BNX2X_ACCEPT_MULTICAST, &rx_accept_flags); | |
5004 | __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags); | |
5005 | ||
5006 | /* internal switching mode */ | |
5007 | __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags); | |
5008 | __set_bit(BNX2X_ACCEPT_MULTICAST, &tx_accept_flags); | |
5009 | __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags); | |
5010 | ||
5011 | break; | |
5012 | case BNX2X_RX_MODE_ALLMULTI: | |
5013 | __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags); | |
5014 | __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags); | |
5015 | __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags); | |
5016 | ||
5017 | /* internal switching mode */ | |
5018 | __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags); | |
5019 | __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags); | |
5020 | __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags); | |
5021 | ||
5022 | break; | |
5023 | case BNX2X_RX_MODE_PROMISC: | |
5024 | /* According to deffinition of SI mode, iface in promisc mode | |
5025 | * should receive matched and unmatched (in resolution of port) | |
5026 | * unicast packets. | |
5027 | */ | |
5028 | __set_bit(BNX2X_ACCEPT_UNMATCHED, &rx_accept_flags); | |
5029 | __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags); | |
5030 | __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags); | |
5031 | __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags); | |
5032 | ||
5033 | /* internal switching mode */ | |
5034 | __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags); | |
5035 | __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags); | |
5036 | ||
5037 | if (IS_MF_SI(bp)) | |
5038 | __set_bit(BNX2X_ACCEPT_ALL_UNICAST, &tx_accept_flags); | |
5039 | else | |
5040 | __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags); | |
5041 | ||
5042 | break; | |
5043 | default: | |
5044 | BNX2X_ERR("Unknown rx_mode: %d\n", bp->rx_mode); | |
5045 | return; | |
5046 | } | |
de832a55 | 5047 | |
619c5cb6 VZ |
5048 | if (bp->rx_mode != BNX2X_RX_MODE_NONE) { |
5049 | __set_bit(BNX2X_ACCEPT_ANY_VLAN, &rx_accept_flags); | |
5050 | __set_bit(BNX2X_ACCEPT_ANY_VLAN, &tx_accept_flags); | |
34f80b04 EG |
5051 | } |
5052 | ||
619c5cb6 VZ |
5053 | __set_bit(RAMROD_RX, &ramrod_flags); |
5054 | __set_bit(RAMROD_TX, &ramrod_flags); | |
5055 | ||
5056 | bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags, rx_accept_flags, | |
5057 | tx_accept_flags, ramrod_flags); | |
5058 | } | |
5059 | ||
5060 | static void bnx2x_init_internal_common(struct bnx2x *bp) | |
5061 | { | |
5062 | int i; | |
5063 | ||
0793f83f DK |
5064 | if (IS_MF_SI(bp)) |
5065 | /* | |
5066 | * In switch independent mode, the TSTORM needs to accept | |
5067 | * packets that failed classification, since approximate match | |
5068 | * mac addresses aren't written to NIG LLH | |
5069 | */ | |
5070 | REG_WR8(bp, BAR_TSTRORM_INTMEM + | |
5071 | TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 2); | |
619c5cb6 VZ |
5072 | else if (!CHIP_IS_E1(bp)) /* 57710 doesn't support MF */ |
5073 | REG_WR8(bp, BAR_TSTRORM_INTMEM + | |
5074 | TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 0); | |
0793f83f | 5075 | |
523224a3 DK |
5076 | /* Zero this manually as its initialization is |
5077 | currently missing in the initTool */ | |
5078 | for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++) | |
ca00392c | 5079 | REG_WR(bp, BAR_USTRORM_INTMEM + |
523224a3 | 5080 | USTORM_AGG_DATA_OFFSET + i * 4, 0); |
619c5cb6 | 5081 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
5082 | REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET, |
5083 | CHIP_INT_MODE_IS_BC(bp) ? | |
5084 | HC_IGU_BC_MODE : HC_IGU_NBC_MODE); | |
5085 | } | |
523224a3 | 5086 | } |
8a1c38d1 | 5087 | |
471de716 EG |
5088 | static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code) |
5089 | { | |
5090 | switch (load_code) { | |
5091 | case FW_MSG_CODE_DRV_LOAD_COMMON: | |
f2e0899f | 5092 | case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP: |
471de716 EG |
5093 | bnx2x_init_internal_common(bp); |
5094 | /* no break */ | |
5095 | ||
5096 | case FW_MSG_CODE_DRV_LOAD_PORT: | |
619c5cb6 | 5097 | /* nothing to do */ |
471de716 EG |
5098 | /* no break */ |
5099 | ||
5100 | case FW_MSG_CODE_DRV_LOAD_FUNCTION: | |
523224a3 DK |
5101 | /* internal memory per function is |
5102 | initialized inside bnx2x_pf_init */ | |
471de716 EG |
5103 | break; |
5104 | ||
5105 | default: | |
5106 | BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code); | |
5107 | break; | |
5108 | } | |
5109 | } | |
5110 | ||
619c5cb6 | 5111 | static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp) |
523224a3 | 5112 | { |
6383c0b3 | 5113 | return fp->bp->igu_base_sb + fp->index + CNIC_PRESENT; |
619c5cb6 | 5114 | } |
523224a3 | 5115 | |
619c5cb6 VZ |
5116 | static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp) |
5117 | { | |
6383c0b3 | 5118 | return fp->bp->base_fw_ndsb + fp->index + CNIC_PRESENT; |
619c5cb6 VZ |
5119 | } |
5120 | ||
5121 | static inline u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp) | |
5122 | { | |
5123 | if (CHIP_IS_E1x(fp->bp)) | |
5124 | return BP_L_ID(fp->bp) + fp->index; | |
5125 | else /* We want Client ID to be the same as IGU SB ID for 57712 */ | |
5126 | return bnx2x_fp_igu_sb_id(fp); | |
5127 | } | |
5128 | ||
6383c0b3 | 5129 | static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx) |
619c5cb6 VZ |
5130 | { |
5131 | struct bnx2x_fastpath *fp = &bp->fp[fp_idx]; | |
6383c0b3 | 5132 | u8 cos; |
619c5cb6 | 5133 | unsigned long q_type = 0; |
6383c0b3 | 5134 | u32 cids[BNX2X_MULTI_TX_COS] = { 0 }; |
523224a3 | 5135 | |
b3b83c3f | 5136 | fp->cid = fp_idx; |
619c5cb6 VZ |
5137 | fp->cl_id = bnx2x_fp_cl_id(fp); |
5138 | fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp); | |
5139 | fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp); | |
523224a3 | 5140 | /* qZone id equals to FW (per path) client id */ |
619c5cb6 VZ |
5141 | fp->cl_qzone_id = bnx2x_fp_qzone_id(fp); |
5142 | ||
523224a3 | 5143 | /* init shortcut */ |
619c5cb6 | 5144 | fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp); |
523224a3 DK |
5145 | /* Setup SB indicies */ |
5146 | fp->rx_cons_sb = BNX2X_RX_SB_INDEX; | |
523224a3 | 5147 | |
619c5cb6 VZ |
5148 | /* Configure Queue State object */ |
5149 | __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type); | |
5150 | __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type); | |
6383c0b3 AE |
5151 | |
5152 | BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS); | |
5153 | ||
5154 | /* init tx data */ | |
5155 | for_each_cos_in_tx_queue(fp, cos) { | |
5156 | bnx2x_init_txdata(bp, &fp->txdata[cos], | |
5157 | CID_COS_TO_TX_ONLY_CID(fp->cid, cos), | |
5158 | FP_COS_TO_TXQ(fp, cos), | |
5159 | BNX2X_TX_SB_INDEX_BASE + cos); | |
5160 | cids[cos] = fp->txdata[cos].cid; | |
5161 | } | |
5162 | ||
5163 | bnx2x_init_queue_obj(bp, &fp->q_obj, fp->cl_id, cids, fp->max_cos, | |
5164 | BP_FUNC(bp), bnx2x_sp(bp, q_rdata), | |
5165 | bnx2x_sp_mapping(bp, q_rdata), q_type); | |
619c5cb6 VZ |
5166 | |
5167 | /** | |
5168 | * Configure classification DBs: Always enable Tx switching | |
5169 | */ | |
5170 | bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX); | |
5171 | ||
523224a3 DK |
5172 | DP(NETIF_MSG_IFUP, "queue[%d]: bnx2x_init_sb(%p,%p) " |
5173 | "cl_id %d fw_sb %d igu_sb %d\n", | |
619c5cb6 | 5174 | fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id, |
523224a3 DK |
5175 | fp->igu_sb_id); |
5176 | bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false, | |
5177 | fp->fw_sb_id, fp->igu_sb_id); | |
5178 | ||
5179 | bnx2x_update_fpsb_idx(fp); | |
5180 | } | |
5181 | ||
9f6c9258 | 5182 | void bnx2x_nic_init(struct bnx2x *bp, u32 load_code) |
a2fbb9ea ET |
5183 | { |
5184 | int i; | |
5185 | ||
ec6ba945 | 5186 | for_each_eth_queue(bp, i) |
6383c0b3 | 5187 | bnx2x_init_eth_fp(bp, i); |
37b091ba | 5188 | #ifdef BCM_CNIC |
ec6ba945 VZ |
5189 | if (!NO_FCOE(bp)) |
5190 | bnx2x_init_fcoe_fp(bp); | |
523224a3 DK |
5191 | |
5192 | bnx2x_init_sb(bp, bp->cnic_sb_mapping, | |
5193 | BNX2X_VF_ID_INVALID, false, | |
619c5cb6 | 5194 | bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp)); |
523224a3 | 5195 | |
37b091ba | 5196 | #endif |
a2fbb9ea | 5197 | |
020c7e3f YR |
5198 | /* Initialize MOD_ABS interrupts */ |
5199 | bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id, | |
5200 | bp->common.shmem_base, bp->common.shmem2_base, | |
5201 | BP_PORT(bp)); | |
16119785 EG |
5202 | /* ensure status block indices were read */ |
5203 | rmb(); | |
5204 | ||
523224a3 | 5205 | bnx2x_init_def_sb(bp); |
5c862848 | 5206 | bnx2x_update_dsb_idx(bp); |
a2fbb9ea | 5207 | bnx2x_init_rx_rings(bp); |
523224a3 | 5208 | bnx2x_init_tx_rings(bp); |
a2fbb9ea | 5209 | bnx2x_init_sp_ring(bp); |
523224a3 | 5210 | bnx2x_init_eq_ring(bp); |
471de716 | 5211 | bnx2x_init_internal(bp, load_code); |
523224a3 | 5212 | bnx2x_pf_init(bp); |
0ef00459 EG |
5213 | bnx2x_stats_init(bp); |
5214 | ||
0ef00459 EG |
5215 | /* flush all before enabling interrupts */ |
5216 | mb(); | |
5217 | mmiowb(); | |
5218 | ||
615f8fd9 | 5219 | bnx2x_int_enable(bp); |
eb8da205 EG |
5220 | |
5221 | /* Check for SPIO5 */ | |
5222 | bnx2x_attn_int_deasserted0(bp, | |
5223 | REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) & | |
5224 | AEU_INPUTS_ATTN_BITS_SPIO5); | |
a2fbb9ea ET |
5225 | } |
5226 | ||
5227 | /* end of nic init */ | |
5228 | ||
5229 | /* | |
5230 | * gzip service functions | |
5231 | */ | |
5232 | ||
5233 | static int bnx2x_gunzip_init(struct bnx2x *bp) | |
5234 | { | |
1a983142 FT |
5235 | bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE, |
5236 | &bp->gunzip_mapping, GFP_KERNEL); | |
a2fbb9ea ET |
5237 | if (bp->gunzip_buf == NULL) |
5238 | goto gunzip_nomem1; | |
5239 | ||
5240 | bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL); | |
5241 | if (bp->strm == NULL) | |
5242 | goto gunzip_nomem2; | |
5243 | ||
7ab24bfd | 5244 | bp->strm->workspace = vmalloc(zlib_inflate_workspacesize()); |
a2fbb9ea ET |
5245 | if (bp->strm->workspace == NULL) |
5246 | goto gunzip_nomem3; | |
5247 | ||
5248 | return 0; | |
5249 | ||
5250 | gunzip_nomem3: | |
5251 | kfree(bp->strm); | |
5252 | bp->strm = NULL; | |
5253 | ||
5254 | gunzip_nomem2: | |
1a983142 FT |
5255 | dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf, |
5256 | bp->gunzip_mapping); | |
a2fbb9ea ET |
5257 | bp->gunzip_buf = NULL; |
5258 | ||
5259 | gunzip_nomem1: | |
cdaa7cb8 VZ |
5260 | netdev_err(bp->dev, "Cannot allocate firmware buffer for" |
5261 | " un-compression\n"); | |
a2fbb9ea ET |
5262 | return -ENOMEM; |
5263 | } | |
5264 | ||
5265 | static void bnx2x_gunzip_end(struct bnx2x *bp) | |
5266 | { | |
b3b83c3f | 5267 | if (bp->strm) { |
7ab24bfd | 5268 | vfree(bp->strm->workspace); |
b3b83c3f DK |
5269 | kfree(bp->strm); |
5270 | bp->strm = NULL; | |
5271 | } | |
a2fbb9ea ET |
5272 | |
5273 | if (bp->gunzip_buf) { | |
1a983142 FT |
5274 | dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf, |
5275 | bp->gunzip_mapping); | |
a2fbb9ea ET |
5276 | bp->gunzip_buf = NULL; |
5277 | } | |
5278 | } | |
5279 | ||
94a78b79 | 5280 | static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len) |
a2fbb9ea ET |
5281 | { |
5282 | int n, rc; | |
5283 | ||
5284 | /* check gzip header */ | |
94a78b79 VZ |
5285 | if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) { |
5286 | BNX2X_ERR("Bad gzip header\n"); | |
a2fbb9ea | 5287 | return -EINVAL; |
94a78b79 | 5288 | } |
a2fbb9ea ET |
5289 | |
5290 | n = 10; | |
5291 | ||
34f80b04 | 5292 | #define FNAME 0x8 |
a2fbb9ea ET |
5293 | |
5294 | if (zbuf[3] & FNAME) | |
5295 | while ((zbuf[n++] != 0) && (n < len)); | |
5296 | ||
94a78b79 | 5297 | bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n; |
a2fbb9ea ET |
5298 | bp->strm->avail_in = len - n; |
5299 | bp->strm->next_out = bp->gunzip_buf; | |
5300 | bp->strm->avail_out = FW_BUF_SIZE; | |
5301 | ||
5302 | rc = zlib_inflateInit2(bp->strm, -MAX_WBITS); | |
5303 | if (rc != Z_OK) | |
5304 | return rc; | |
5305 | ||
5306 | rc = zlib_inflate(bp->strm, Z_FINISH); | |
5307 | if ((rc != Z_OK) && (rc != Z_STREAM_END)) | |
7995c64e JP |
5308 | netdev_err(bp->dev, "Firmware decompression error: %s\n", |
5309 | bp->strm->msg); | |
a2fbb9ea ET |
5310 | |
5311 | bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out); | |
5312 | if (bp->gunzip_outlen & 0x3) | |
cdaa7cb8 VZ |
5313 | netdev_err(bp->dev, "Firmware decompression error:" |
5314 | " gunzip_outlen (%d) not aligned\n", | |
5315 | bp->gunzip_outlen); | |
a2fbb9ea ET |
5316 | bp->gunzip_outlen >>= 2; |
5317 | ||
5318 | zlib_inflateEnd(bp->strm); | |
5319 | ||
5320 | if (rc == Z_STREAM_END) | |
5321 | return 0; | |
5322 | ||
5323 | return rc; | |
5324 | } | |
5325 | ||
5326 | /* nic load/unload */ | |
5327 | ||
5328 | /* | |
34f80b04 | 5329 | * General service functions |
a2fbb9ea ET |
5330 | */ |
5331 | ||
5332 | /* send a NIG loopback debug packet */ | |
5333 | static void bnx2x_lb_pckt(struct bnx2x *bp) | |
5334 | { | |
a2fbb9ea | 5335 | u32 wb_write[3]; |
a2fbb9ea ET |
5336 | |
5337 | /* Ethernet source and destination addresses */ | |
a2fbb9ea ET |
5338 | wb_write[0] = 0x55555555; |
5339 | wb_write[1] = 0x55555555; | |
34f80b04 | 5340 | wb_write[2] = 0x20; /* SOP */ |
a2fbb9ea | 5341 | REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3); |
a2fbb9ea ET |
5342 | |
5343 | /* NON-IP protocol */ | |
a2fbb9ea ET |
5344 | wb_write[0] = 0x09000000; |
5345 | wb_write[1] = 0x55555555; | |
34f80b04 | 5346 | wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */ |
a2fbb9ea | 5347 | REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3); |
a2fbb9ea ET |
5348 | } |
5349 | ||
5350 | /* some of the internal memories | |
5351 | * are not directly readable from the driver | |
5352 | * to test them we send debug packets | |
5353 | */ | |
5354 | static int bnx2x_int_mem_test(struct bnx2x *bp) | |
5355 | { | |
5356 | int factor; | |
5357 | int count, i; | |
5358 | u32 val = 0; | |
5359 | ||
ad8d3948 | 5360 | if (CHIP_REV_IS_FPGA(bp)) |
a2fbb9ea | 5361 | factor = 120; |
ad8d3948 EG |
5362 | else if (CHIP_REV_IS_EMUL(bp)) |
5363 | factor = 200; | |
5364 | else | |
a2fbb9ea | 5365 | factor = 1; |
a2fbb9ea | 5366 | |
a2fbb9ea ET |
5367 | /* Disable inputs of parser neighbor blocks */ |
5368 | REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0); | |
5369 | REG_WR(bp, TCM_REG_PRS_IFEN, 0x0); | |
5370 | REG_WR(bp, CFC_REG_DEBUG0, 0x1); | |
3196a88a | 5371 | REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0); |
a2fbb9ea ET |
5372 | |
5373 | /* Write 0 to parser credits for CFC search request */ | |
5374 | REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0); | |
5375 | ||
5376 | /* send Ethernet packet */ | |
5377 | bnx2x_lb_pckt(bp); | |
5378 | ||
5379 | /* TODO do i reset NIG statistic? */ | |
5380 | /* Wait until NIG register shows 1 packet of size 0x10 */ | |
5381 | count = 1000 * factor; | |
5382 | while (count) { | |
34f80b04 | 5383 | |
a2fbb9ea ET |
5384 | bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2); |
5385 | val = *bnx2x_sp(bp, wb_data[0]); | |
a2fbb9ea ET |
5386 | if (val == 0x10) |
5387 | break; | |
5388 | ||
5389 | msleep(10); | |
5390 | count--; | |
5391 | } | |
5392 | if (val != 0x10) { | |
5393 | BNX2X_ERR("NIG timeout val = 0x%x\n", val); | |
5394 | return -1; | |
5395 | } | |
5396 | ||
5397 | /* Wait until PRS register shows 1 packet */ | |
5398 | count = 1000 * factor; | |
5399 | while (count) { | |
5400 | val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); | |
a2fbb9ea ET |
5401 | if (val == 1) |
5402 | break; | |
5403 | ||
5404 | msleep(10); | |
5405 | count--; | |
5406 | } | |
5407 | if (val != 0x1) { | |
5408 | BNX2X_ERR("PRS timeout val = 0x%x\n", val); | |
5409 | return -2; | |
5410 | } | |
5411 | ||
5412 | /* Reset and init BRB, PRS */ | |
34f80b04 | 5413 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03); |
a2fbb9ea | 5414 | msleep(50); |
34f80b04 | 5415 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03); |
a2fbb9ea | 5416 | msleep(50); |
619c5cb6 VZ |
5417 | bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON); |
5418 | bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON); | |
a2fbb9ea ET |
5419 | |
5420 | DP(NETIF_MSG_HW, "part2\n"); | |
5421 | ||
5422 | /* Disable inputs of parser neighbor blocks */ | |
5423 | REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0); | |
5424 | REG_WR(bp, TCM_REG_PRS_IFEN, 0x0); | |
5425 | REG_WR(bp, CFC_REG_DEBUG0, 0x1); | |
3196a88a | 5426 | REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0); |
a2fbb9ea ET |
5427 | |
5428 | /* Write 0 to parser credits for CFC search request */ | |
5429 | REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0); | |
5430 | ||
5431 | /* send 10 Ethernet packets */ | |
5432 | for (i = 0; i < 10; i++) | |
5433 | bnx2x_lb_pckt(bp); | |
5434 | ||
5435 | /* Wait until NIG register shows 10 + 1 | |
5436 | packets of size 11*0x10 = 0xb0 */ | |
5437 | count = 1000 * factor; | |
5438 | while (count) { | |
34f80b04 | 5439 | |
a2fbb9ea ET |
5440 | bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2); |
5441 | val = *bnx2x_sp(bp, wb_data[0]); | |
a2fbb9ea ET |
5442 | if (val == 0xb0) |
5443 | break; | |
5444 | ||
5445 | msleep(10); | |
5446 | count--; | |
5447 | } | |
5448 | if (val != 0xb0) { | |
5449 | BNX2X_ERR("NIG timeout val = 0x%x\n", val); | |
5450 | return -3; | |
5451 | } | |
5452 | ||
5453 | /* Wait until PRS register shows 2 packets */ | |
5454 | val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); | |
5455 | if (val != 2) | |
5456 | BNX2X_ERR("PRS timeout val = 0x%x\n", val); | |
5457 | ||
5458 | /* Write 1 to parser credits for CFC search request */ | |
5459 | REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1); | |
5460 | ||
5461 | /* Wait until PRS register shows 3 packets */ | |
5462 | msleep(10 * factor); | |
5463 | /* Wait until NIG register shows 1 packet of size 0x10 */ | |
5464 | val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); | |
5465 | if (val != 3) | |
5466 | BNX2X_ERR("PRS timeout val = 0x%x\n", val); | |
5467 | ||
5468 | /* clear NIG EOP FIFO */ | |
5469 | for (i = 0; i < 11; i++) | |
5470 | REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO); | |
5471 | val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY); | |
5472 | if (val != 1) { | |
5473 | BNX2X_ERR("clear of NIG failed\n"); | |
5474 | return -4; | |
5475 | } | |
5476 | ||
5477 | /* Reset and init BRB, PRS, NIG */ | |
5478 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03); | |
5479 | msleep(50); | |
5480 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03); | |
5481 | msleep(50); | |
619c5cb6 VZ |
5482 | bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON); |
5483 | bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON); | |
37b091ba | 5484 | #ifndef BCM_CNIC |
a2fbb9ea ET |
5485 | /* set NIC mode */ |
5486 | REG_WR(bp, PRS_REG_NIC_MODE, 1); | |
5487 | #endif | |
5488 | ||
5489 | /* Enable inputs of parser neighbor blocks */ | |
5490 | REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff); | |
5491 | REG_WR(bp, TCM_REG_PRS_IFEN, 0x1); | |
5492 | REG_WR(bp, CFC_REG_DEBUG0, 0x0); | |
3196a88a | 5493 | REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1); |
a2fbb9ea ET |
5494 | |
5495 | DP(NETIF_MSG_HW, "done\n"); | |
5496 | ||
5497 | return 0; /* OK */ | |
5498 | } | |
5499 | ||
4a33bc03 | 5500 | static void bnx2x_enable_blocks_attention(struct bnx2x *bp) |
a2fbb9ea ET |
5501 | { |
5502 | REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0); | |
619c5cb6 | 5503 | if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
5504 | REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40); |
5505 | else | |
5506 | REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0); | |
a2fbb9ea ET |
5507 | REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0); |
5508 | REG_WR(bp, CFC_REG_CFC_INT_MASK, 0); | |
f2e0899f DK |
5509 | /* |
5510 | * mask read length error interrupts in brb for parser | |
5511 | * (parsing unit and 'checksum and crc' unit) | |
5512 | * these errors are legal (PU reads fixed length and CAC can cause | |
5513 | * read length error on truncated packets) | |
5514 | */ | |
5515 | REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00); | |
a2fbb9ea ET |
5516 | REG_WR(bp, QM_REG_QM_INT_MASK, 0); |
5517 | REG_WR(bp, TM_REG_TM_INT_MASK, 0); | |
5518 | REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0); | |
5519 | REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0); | |
5520 | REG_WR(bp, XCM_REG_XCM_INT_MASK, 0); | |
34f80b04 EG |
5521 | /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */ |
5522 | /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */ | |
a2fbb9ea ET |
5523 | REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0); |
5524 | REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0); | |
5525 | REG_WR(bp, UCM_REG_UCM_INT_MASK, 0); | |
34f80b04 EG |
5526 | /* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */ |
5527 | /* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */ | |
a2fbb9ea ET |
5528 | REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0); |
5529 | REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0); | |
5530 | REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0); | |
5531 | REG_WR(bp, CCM_REG_CCM_INT_MASK, 0); | |
34f80b04 EG |
5532 | /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */ |
5533 | /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */ | |
f85582f8 | 5534 | |
34f80b04 EG |
5535 | if (CHIP_REV_IS_FPGA(bp)) |
5536 | REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x580000); | |
619c5cb6 | 5537 | else if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
5538 | REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, |
5539 | (PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF | |
5540 | | PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT | |
5541 | | PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN | |
5542 | | PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED | |
5543 | | PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED)); | |
34f80b04 EG |
5544 | else |
5545 | REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x480000); | |
a2fbb9ea ET |
5546 | REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0); |
5547 | REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0); | |
5548 | REG_WR(bp, TCM_REG_TCM_INT_MASK, 0); | |
34f80b04 | 5549 | /* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */ |
619c5cb6 VZ |
5550 | |
5551 | if (!CHIP_IS_E1x(bp)) | |
5552 | /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */ | |
5553 | REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff); | |
5554 | ||
a2fbb9ea ET |
5555 | REG_WR(bp, CDU_REG_CDU_INT_MASK, 0); |
5556 | REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0); | |
34f80b04 | 5557 | /* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */ |
4a33bc03 | 5558 | REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */ |
a2fbb9ea ET |
5559 | } |
5560 | ||
81f75bbf EG |
5561 | static void bnx2x_reset_common(struct bnx2x *bp) |
5562 | { | |
619c5cb6 VZ |
5563 | u32 val = 0x1400; |
5564 | ||
81f75bbf EG |
5565 | /* reset_common */ |
5566 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, | |
5567 | 0xd3ffff7f); | |
619c5cb6 VZ |
5568 | |
5569 | if (CHIP_IS_E3(bp)) { | |
5570 | val |= MISC_REGISTERS_RESET_REG_2_MSTAT0; | |
5571 | val |= MISC_REGISTERS_RESET_REG_2_MSTAT1; | |
5572 | } | |
5573 | ||
5574 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val); | |
5575 | } | |
5576 | ||
5577 | static void bnx2x_setup_dmae(struct bnx2x *bp) | |
5578 | { | |
5579 | bp->dmae_ready = 0; | |
5580 | spin_lock_init(&bp->dmae_lock); | |
81f75bbf EG |
5581 | } |
5582 | ||
573f2035 EG |
5583 | static void bnx2x_init_pxp(struct bnx2x *bp) |
5584 | { | |
5585 | u16 devctl; | |
5586 | int r_order, w_order; | |
5587 | ||
5588 | pci_read_config_word(bp->pdev, | |
77c98e6a | 5589 | bp->pdev->pcie_cap + PCI_EXP_DEVCTL, &devctl); |
573f2035 EG |
5590 | DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl); |
5591 | w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5); | |
5592 | if (bp->mrrs == -1) | |
5593 | r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12); | |
5594 | else { | |
5595 | DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs); | |
5596 | r_order = bp->mrrs; | |
5597 | } | |
5598 | ||
5599 | bnx2x_init_pxp_arb(bp, r_order, w_order); | |
5600 | } | |
fd4ef40d EG |
5601 | |
5602 | static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp) | |
5603 | { | |
2145a920 | 5604 | int is_required; |
fd4ef40d | 5605 | u32 val; |
2145a920 | 5606 | int port; |
fd4ef40d | 5607 | |
2145a920 VZ |
5608 | if (BP_NOMCP(bp)) |
5609 | return; | |
5610 | ||
5611 | is_required = 0; | |
fd4ef40d EG |
5612 | val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) & |
5613 | SHARED_HW_CFG_FAN_FAILURE_MASK; | |
5614 | ||
5615 | if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED) | |
5616 | is_required = 1; | |
5617 | ||
5618 | /* | |
5619 | * The fan failure mechanism is usually related to the PHY type since | |
5620 | * the power consumption of the board is affected by the PHY. Currently, | |
5621 | * fan is required for most designs with SFX7101, BCM8727 and BCM8481. | |
5622 | */ | |
5623 | else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE) | |
5624 | for (port = PORT_0; port < PORT_MAX; port++) { | |
fd4ef40d | 5625 | is_required |= |
d90d96ba YR |
5626 | bnx2x_fan_failure_det_req( |
5627 | bp, | |
5628 | bp->common.shmem_base, | |
a22f0788 | 5629 | bp->common.shmem2_base, |
d90d96ba | 5630 | port); |
fd4ef40d EG |
5631 | } |
5632 | ||
5633 | DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required); | |
5634 | ||
5635 | if (is_required == 0) | |
5636 | return; | |
5637 | ||
5638 | /* Fan failure is indicated by SPIO 5 */ | |
5639 | bnx2x_set_spio(bp, MISC_REGISTERS_SPIO_5, | |
5640 | MISC_REGISTERS_SPIO_INPUT_HI_Z); | |
5641 | ||
5642 | /* set to active low mode */ | |
5643 | val = REG_RD(bp, MISC_REG_SPIO_INT); | |
5644 | val |= ((1 << MISC_REGISTERS_SPIO_5) << | |
cdaa7cb8 | 5645 | MISC_REGISTERS_SPIO_INT_OLD_SET_POS); |
fd4ef40d EG |
5646 | REG_WR(bp, MISC_REG_SPIO_INT, val); |
5647 | ||
5648 | /* enable interrupt to signal the IGU */ | |
5649 | val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN); | |
5650 | val |= (1 << MISC_REGISTERS_SPIO_5); | |
5651 | REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val); | |
5652 | } | |
5653 | ||
f2e0899f DK |
5654 | static void bnx2x_pretend_func(struct bnx2x *bp, u8 pretend_func_num) |
5655 | { | |
5656 | u32 offset = 0; | |
5657 | ||
5658 | if (CHIP_IS_E1(bp)) | |
5659 | return; | |
5660 | if (CHIP_IS_E1H(bp) && (pretend_func_num >= E1H_FUNC_MAX)) | |
5661 | return; | |
5662 | ||
5663 | switch (BP_ABS_FUNC(bp)) { | |
5664 | case 0: | |
5665 | offset = PXP2_REG_PGL_PRETEND_FUNC_F0; | |
5666 | break; | |
5667 | case 1: | |
5668 | offset = PXP2_REG_PGL_PRETEND_FUNC_F1; | |
5669 | break; | |
5670 | case 2: | |
5671 | offset = PXP2_REG_PGL_PRETEND_FUNC_F2; | |
5672 | break; | |
5673 | case 3: | |
5674 | offset = PXP2_REG_PGL_PRETEND_FUNC_F3; | |
5675 | break; | |
5676 | case 4: | |
5677 | offset = PXP2_REG_PGL_PRETEND_FUNC_F4; | |
5678 | break; | |
5679 | case 5: | |
5680 | offset = PXP2_REG_PGL_PRETEND_FUNC_F5; | |
5681 | break; | |
5682 | case 6: | |
5683 | offset = PXP2_REG_PGL_PRETEND_FUNC_F6; | |
5684 | break; | |
5685 | case 7: | |
5686 | offset = PXP2_REG_PGL_PRETEND_FUNC_F7; | |
5687 | break; | |
5688 | default: | |
5689 | return; | |
5690 | } | |
5691 | ||
5692 | REG_WR(bp, offset, pretend_func_num); | |
5693 | REG_RD(bp, offset); | |
5694 | DP(NETIF_MSG_HW, "Pretending to func %d\n", pretend_func_num); | |
5695 | } | |
5696 | ||
c9ee9206 | 5697 | void bnx2x_pf_disable(struct bnx2x *bp) |
f2e0899f DK |
5698 | { |
5699 | u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); | |
5700 | val &= ~IGU_PF_CONF_FUNC_EN; | |
5701 | ||
5702 | REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); | |
5703 | REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0); | |
5704 | REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0); | |
5705 | } | |
5706 | ||
619c5cb6 VZ |
5707 | static inline void bnx2x__common_init_phy(struct bnx2x *bp) |
5708 | { | |
5709 | u32 shmem_base[2], shmem2_base[2]; | |
5710 | shmem_base[0] = bp->common.shmem_base; | |
5711 | shmem2_base[0] = bp->common.shmem2_base; | |
5712 | if (!CHIP_IS_E1x(bp)) { | |
5713 | shmem_base[1] = | |
5714 | SHMEM2_RD(bp, other_shmem_base_addr); | |
5715 | shmem2_base[1] = | |
5716 | SHMEM2_RD(bp, other_shmem2_base_addr); | |
5717 | } | |
5718 | bnx2x_acquire_phy_lock(bp); | |
5719 | bnx2x_common_init_phy(bp, shmem_base, shmem2_base, | |
5720 | bp->common.chip_id); | |
5721 | bnx2x_release_phy_lock(bp); | |
5722 | } | |
5723 | ||
5724 | /** | |
5725 | * bnx2x_init_hw_common - initialize the HW at the COMMON phase. | |
5726 | * | |
5727 | * @bp: driver handle | |
5728 | */ | |
5729 | static int bnx2x_init_hw_common(struct bnx2x *bp) | |
a2fbb9ea | 5730 | { |
619c5cb6 | 5731 | u32 val; |
a2fbb9ea | 5732 | |
f2e0899f | 5733 | DP(BNX2X_MSG_MCP, "starting common init func %d\n", BP_ABS_FUNC(bp)); |
a2fbb9ea | 5734 | |
81f75bbf | 5735 | bnx2x_reset_common(bp); |
34f80b04 | 5736 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff); |
a2fbb9ea | 5737 | |
619c5cb6 VZ |
5738 | val = 0xfffc; |
5739 | if (CHIP_IS_E3(bp)) { | |
5740 | val |= MISC_REGISTERS_RESET_REG_2_MSTAT0; | |
5741 | val |= MISC_REGISTERS_RESET_REG_2_MSTAT1; | |
5742 | } | |
5743 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val); | |
5744 | ||
5745 | bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON); | |
a2fbb9ea | 5746 | |
619c5cb6 VZ |
5747 | if (!CHIP_IS_E1x(bp)) { |
5748 | u8 abs_func_id; | |
f2e0899f DK |
5749 | |
5750 | /** | |
5751 | * 4-port mode or 2-port mode we need to turn of master-enable | |
5752 | * for everyone, after that, turn it back on for self. | |
5753 | * so, we disregard multi-function or not, and always disable | |
5754 | * for all functions on the given path, this means 0,2,4,6 for | |
5755 | * path 0 and 1,3,5,7 for path 1 | |
5756 | */ | |
619c5cb6 VZ |
5757 | for (abs_func_id = BP_PATH(bp); |
5758 | abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) { | |
5759 | if (abs_func_id == BP_ABS_FUNC(bp)) { | |
f2e0899f DK |
5760 | REG_WR(bp, |
5761 | PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, | |
5762 | 1); | |
5763 | continue; | |
5764 | } | |
5765 | ||
619c5cb6 | 5766 | bnx2x_pretend_func(bp, abs_func_id); |
f2e0899f DK |
5767 | /* clear pf enable */ |
5768 | bnx2x_pf_disable(bp); | |
5769 | bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); | |
5770 | } | |
5771 | } | |
a2fbb9ea | 5772 | |
619c5cb6 | 5773 | bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON); |
34f80b04 EG |
5774 | if (CHIP_IS_E1(bp)) { |
5775 | /* enable HW interrupt from PXP on USDM overflow | |
5776 | bit 16 on INT_MASK_0 */ | |
5777 | REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0); | |
5778 | } | |
a2fbb9ea | 5779 | |
619c5cb6 | 5780 | bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON); |
34f80b04 | 5781 | bnx2x_init_pxp(bp); |
a2fbb9ea ET |
5782 | |
5783 | #ifdef __BIG_ENDIAN | |
34f80b04 EG |
5784 | REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1); |
5785 | REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1); | |
5786 | REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1); | |
5787 | REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1); | |
5788 | REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1); | |
8badd27a EG |
5789 | /* make sure this value is 0 */ |
5790 | REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0); | |
34f80b04 EG |
5791 | |
5792 | /* REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */ | |
5793 | REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1); | |
5794 | REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1); | |
5795 | REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1); | |
5796 | REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1); | |
a2fbb9ea ET |
5797 | #endif |
5798 | ||
523224a3 DK |
5799 | bnx2x_ilt_init_page_size(bp, INITOP_SET); |
5800 | ||
34f80b04 EG |
5801 | if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp)) |
5802 | REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1); | |
a2fbb9ea | 5803 | |
34f80b04 EG |
5804 | /* let the HW do it's magic ... */ |
5805 | msleep(100); | |
5806 | /* finish PXP init */ | |
5807 | val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE); | |
5808 | if (val != 1) { | |
5809 | BNX2X_ERR("PXP2 CFG failed\n"); | |
5810 | return -EBUSY; | |
5811 | } | |
5812 | val = REG_RD(bp, PXP2_REG_RD_INIT_DONE); | |
5813 | if (val != 1) { | |
5814 | BNX2X_ERR("PXP2 RD_INIT failed\n"); | |
5815 | return -EBUSY; | |
5816 | } | |
a2fbb9ea | 5817 | |
f2e0899f DK |
5818 | /* Timers bug workaround E2 only. We need to set the entire ILT to |
5819 | * have entries with value "0" and valid bit on. | |
5820 | * This needs to be done by the first PF that is loaded in a path | |
5821 | * (i.e. common phase) | |
5822 | */ | |
619c5cb6 VZ |
5823 | if (!CHIP_IS_E1x(bp)) { |
5824 | /* In E2 there is a bug in the timers block that can cause function 6 / 7 | |
5825 | * (i.e. vnic3) to start even if it is marked as "scan-off". | |
5826 | * This occurs when a different function (func2,3) is being marked | |
5827 | * as "scan-off". Real-life scenario for example: if a driver is being | |
5828 | * load-unloaded while func6,7 are down. This will cause the timer to access | |
5829 | * the ilt, translate to a logical address and send a request to read/write. | |
5830 | * Since the ilt for the function that is down is not valid, this will cause | |
5831 | * a translation error which is unrecoverable. | |
5832 | * The Workaround is intended to make sure that when this happens nothing fatal | |
5833 | * will occur. The workaround: | |
5834 | * 1. First PF driver which loads on a path will: | |
5835 | * a. After taking the chip out of reset, by using pretend, | |
5836 | * it will write "0" to the following registers of | |
5837 | * the other vnics. | |
5838 | * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0); | |
5839 | * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0); | |
5840 | * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0); | |
5841 | * And for itself it will write '1' to | |
5842 | * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable | |
5843 | * dmae-operations (writing to pram for example.) | |
5844 | * note: can be done for only function 6,7 but cleaner this | |
5845 | * way. | |
5846 | * b. Write zero+valid to the entire ILT. | |
5847 | * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of | |
5848 | * VNIC3 (of that port). The range allocated will be the | |
5849 | * entire ILT. This is needed to prevent ILT range error. | |
5850 | * 2. Any PF driver load flow: | |
5851 | * a. ILT update with the physical addresses of the allocated | |
5852 | * logical pages. | |
5853 | * b. Wait 20msec. - note that this timeout is needed to make | |
5854 | * sure there are no requests in one of the PXP internal | |
5855 | * queues with "old" ILT addresses. | |
5856 | * c. PF enable in the PGLC. | |
5857 | * d. Clear the was_error of the PF in the PGLC. (could have | |
5858 | * occured while driver was down) | |
5859 | * e. PF enable in the CFC (WEAK + STRONG) | |
5860 | * f. Timers scan enable | |
5861 | * 3. PF driver unload flow: | |
5862 | * a. Clear the Timers scan_en. | |
5863 | * b. Polling for scan_on=0 for that PF. | |
5864 | * c. Clear the PF enable bit in the PXP. | |
5865 | * d. Clear the PF enable in the CFC (WEAK + STRONG) | |
5866 | * e. Write zero+valid to all ILT entries (The valid bit must | |
5867 | * stay set) | |
5868 | * f. If this is VNIC 3 of a port then also init | |
5869 | * first_timers_ilt_entry to zero and last_timers_ilt_entry | |
5870 | * to the last enrty in the ILT. | |
5871 | * | |
5872 | * Notes: | |
5873 | * Currently the PF error in the PGLC is non recoverable. | |
5874 | * In the future the there will be a recovery routine for this error. | |
5875 | * Currently attention is masked. | |
5876 | * Having an MCP lock on the load/unload process does not guarantee that | |
5877 | * there is no Timer disable during Func6/7 enable. This is because the | |
5878 | * Timers scan is currently being cleared by the MCP on FLR. | |
5879 | * Step 2.d can be done only for PF6/7 and the driver can also check if | |
5880 | * there is error before clearing it. But the flow above is simpler and | |
5881 | * more general. | |
5882 | * All ILT entries are written by zero+valid and not just PF6/7 | |
5883 | * ILT entries since in the future the ILT entries allocation for | |
5884 | * PF-s might be dynamic. | |
5885 | */ | |
f2e0899f DK |
5886 | struct ilt_client_info ilt_cli; |
5887 | struct bnx2x_ilt ilt; | |
5888 | memset(&ilt_cli, 0, sizeof(struct ilt_client_info)); | |
5889 | memset(&ilt, 0, sizeof(struct bnx2x_ilt)); | |
5890 | ||
b595076a | 5891 | /* initialize dummy TM client */ |
f2e0899f DK |
5892 | ilt_cli.start = 0; |
5893 | ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1; | |
5894 | ilt_cli.client_num = ILT_CLIENT_TM; | |
5895 | ||
5896 | /* Step 1: set zeroes to all ilt page entries with valid bit on | |
5897 | * Step 2: set the timers first/last ilt entry to point | |
5898 | * to the entire range to prevent ILT range error for 3rd/4th | |
619c5cb6 | 5899 | * vnic (this code assumes existance of the vnic) |
f2e0899f DK |
5900 | * |
5901 | * both steps performed by call to bnx2x_ilt_client_init_op() | |
5902 | * with dummy TM client | |
5903 | * | |
5904 | * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT | |
5905 | * and his brother are split registers | |
5906 | */ | |
5907 | bnx2x_pretend_func(bp, (BP_PATH(bp) + 6)); | |
5908 | bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR); | |
5909 | bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); | |
5910 | ||
5911 | REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN); | |
5912 | REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN); | |
5913 | REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1); | |
5914 | } | |
5915 | ||
5916 | ||
34f80b04 EG |
5917 | REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0); |
5918 | REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0); | |
a2fbb9ea | 5919 | |
619c5cb6 | 5920 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
5921 | int factor = CHIP_REV_IS_EMUL(bp) ? 1000 : |
5922 | (CHIP_REV_IS_FPGA(bp) ? 400 : 0); | |
619c5cb6 | 5923 | bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON); |
f2e0899f | 5924 | |
619c5cb6 | 5925 | bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON); |
f2e0899f DK |
5926 | |
5927 | /* let the HW do it's magic ... */ | |
5928 | do { | |
5929 | msleep(200); | |
5930 | val = REG_RD(bp, ATC_REG_ATC_INIT_DONE); | |
5931 | } while (factor-- && (val != 1)); | |
5932 | ||
5933 | if (val != 1) { | |
5934 | BNX2X_ERR("ATC_INIT failed\n"); | |
5935 | return -EBUSY; | |
5936 | } | |
5937 | } | |
5938 | ||
619c5cb6 | 5939 | bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON); |
a2fbb9ea | 5940 | |
34f80b04 EG |
5941 | /* clean the DMAE memory */ |
5942 | bp->dmae_ready = 1; | |
619c5cb6 VZ |
5943 | bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1); |
5944 | ||
5945 | bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON); | |
5946 | ||
5947 | bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON); | |
5948 | ||
5949 | bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON); | |
a2fbb9ea | 5950 | |
619c5cb6 | 5951 | bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON); |
a2fbb9ea | 5952 | |
34f80b04 EG |
5953 | bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3); |
5954 | bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3); | |
5955 | bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3); | |
5956 | bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3); | |
5957 | ||
619c5cb6 | 5958 | bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON); |
37b091ba | 5959 | |
f85582f8 | 5960 | |
523224a3 DK |
5961 | /* QM queues pointers table */ |
5962 | bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET); | |
5963 | ||
34f80b04 EG |
5964 | /* soft reset pulse */ |
5965 | REG_WR(bp, QM_REG_SOFT_RESET, 1); | |
5966 | REG_WR(bp, QM_REG_SOFT_RESET, 0); | |
a2fbb9ea | 5967 | |
37b091ba | 5968 | #ifdef BCM_CNIC |
619c5cb6 | 5969 | bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON); |
a2fbb9ea | 5970 | #endif |
a2fbb9ea | 5971 | |
619c5cb6 | 5972 | bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON); |
523224a3 | 5973 | REG_WR(bp, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT); |
619c5cb6 | 5974 | if (!CHIP_REV_IS_SLOW(bp)) |
34f80b04 EG |
5975 | /* enable hw interrupt from doorbell Q */ |
5976 | REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0); | |
a2fbb9ea | 5977 | |
619c5cb6 | 5978 | bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON); |
f2e0899f | 5979 | |
619c5cb6 | 5980 | bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON); |
26c8fa4d | 5981 | REG_WR(bp, PRS_REG_A_PRSU_20, 0xf); |
619c5cb6 | 5982 | |
f2e0899f | 5983 | if (!CHIP_IS_E1(bp)) |
619c5cb6 | 5984 | REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan); |
f85582f8 | 5985 | |
619c5cb6 VZ |
5986 | if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp)) |
5987 | /* Bit-map indicating which L2 hdrs may appear | |
5988 | * after the basic Ethernet header | |
5989 | */ | |
5990 | REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, | |
5991 | bp->path_has_ovlan ? 7 : 6); | |
a2fbb9ea | 5992 | |
619c5cb6 VZ |
5993 | bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON); |
5994 | bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON); | |
5995 | bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON); | |
5996 | bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON); | |
a2fbb9ea | 5997 | |
619c5cb6 VZ |
5998 | if (!CHIP_IS_E1x(bp)) { |
5999 | /* reset VFC memories */ | |
6000 | REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST, | |
6001 | VFC_MEMORIES_RST_REG_CAM_RST | | |
6002 | VFC_MEMORIES_RST_REG_RAM_RST); | |
6003 | REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST, | |
6004 | VFC_MEMORIES_RST_REG_CAM_RST | | |
6005 | VFC_MEMORIES_RST_REG_RAM_RST); | |
a2fbb9ea | 6006 | |
619c5cb6 VZ |
6007 | msleep(20); |
6008 | } | |
a2fbb9ea | 6009 | |
619c5cb6 VZ |
6010 | bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON); |
6011 | bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON); | |
6012 | bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON); | |
6013 | bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON); | |
f2e0899f | 6014 | |
34f80b04 EG |
6015 | /* sync semi rtc */ |
6016 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, | |
6017 | 0x80000000); | |
6018 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, | |
6019 | 0x80000000); | |
a2fbb9ea | 6020 | |
619c5cb6 VZ |
6021 | bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON); |
6022 | bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON); | |
6023 | bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON); | |
a2fbb9ea | 6024 | |
619c5cb6 VZ |
6025 | if (!CHIP_IS_E1x(bp)) |
6026 | REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, | |
6027 | bp->path_has_ovlan ? 7 : 6); | |
f2e0899f | 6028 | |
34f80b04 | 6029 | REG_WR(bp, SRC_REG_SOFT_RST, 1); |
f85582f8 | 6030 | |
619c5cb6 VZ |
6031 | bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON); |
6032 | ||
37b091ba MC |
6033 | #ifdef BCM_CNIC |
6034 | REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672); | |
6035 | REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc); | |
6036 | REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b); | |
6037 | REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a); | |
6038 | REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116); | |
6039 | REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b); | |
6040 | REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf); | |
6041 | REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09); | |
6042 | REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f); | |
6043 | REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7); | |
6044 | #endif | |
34f80b04 | 6045 | REG_WR(bp, SRC_REG_SOFT_RST, 0); |
a2fbb9ea | 6046 | |
34f80b04 EG |
6047 | if (sizeof(union cdu_context) != 1024) |
6048 | /* we currently assume that a context is 1024 bytes */ | |
cdaa7cb8 VZ |
6049 | dev_alert(&bp->pdev->dev, "please adjust the size " |
6050 | "of cdu_context(%ld)\n", | |
7995c64e | 6051 | (long)sizeof(union cdu_context)); |
a2fbb9ea | 6052 | |
619c5cb6 | 6053 | bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON); |
34f80b04 EG |
6054 | val = (4 << 24) + (0 << 12) + 1024; |
6055 | REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val); | |
a2fbb9ea | 6056 | |
619c5cb6 | 6057 | bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON); |
34f80b04 | 6058 | REG_WR(bp, CFC_REG_INIT_REG, 0x7FF); |
8d9c5f34 EG |
6059 | /* enable context validation interrupt from CFC */ |
6060 | REG_WR(bp, CFC_REG_CFC_INT_MASK, 0); | |
6061 | ||
6062 | /* set the thresholds to prevent CFC/CDU race */ | |
6063 | REG_WR(bp, CFC_REG_DEBUG0, 0x20020000); | |
a2fbb9ea | 6064 | |
619c5cb6 | 6065 | bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON); |
f2e0899f | 6066 | |
619c5cb6 | 6067 | if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp)) |
f2e0899f DK |
6068 | REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36); |
6069 | ||
619c5cb6 VZ |
6070 | bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON); |
6071 | bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON); | |
a2fbb9ea | 6072 | |
34f80b04 EG |
6073 | /* Reset PCIE errors for debug */ |
6074 | REG_WR(bp, 0x2814, 0xffffffff); | |
6075 | REG_WR(bp, 0x3820, 0xffffffff); | |
a2fbb9ea | 6076 | |
619c5cb6 | 6077 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
6078 | REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5, |
6079 | (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 | | |
6080 | PXPCS_TL_CONTROL_5_ERR_UNSPPORT)); | |
6081 | REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT, | |
6082 | (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 | | |
6083 | PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 | | |
6084 | PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2)); | |
6085 | REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT, | |
6086 | (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 | | |
6087 | PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 | | |
6088 | PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5)); | |
6089 | } | |
6090 | ||
619c5cb6 | 6091 | bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON); |
f2e0899f | 6092 | if (!CHIP_IS_E1(bp)) { |
619c5cb6 VZ |
6093 | /* in E3 this done in per-port section */ |
6094 | if (!CHIP_IS_E3(bp)) | |
6095 | REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp)); | |
f2e0899f | 6096 | } |
619c5cb6 VZ |
6097 | if (CHIP_IS_E1H(bp)) |
6098 | /* not applicable for E2 (and above ...) */ | |
6099 | REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp)); | |
34f80b04 EG |
6100 | |
6101 | if (CHIP_REV_IS_SLOW(bp)) | |
6102 | msleep(200); | |
6103 | ||
6104 | /* finish CFC init */ | |
6105 | val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10); | |
6106 | if (val != 1) { | |
6107 | BNX2X_ERR("CFC LL_INIT failed\n"); | |
6108 | return -EBUSY; | |
6109 | } | |
6110 | val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10); | |
6111 | if (val != 1) { | |
6112 | BNX2X_ERR("CFC AC_INIT failed\n"); | |
6113 | return -EBUSY; | |
6114 | } | |
6115 | val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10); | |
6116 | if (val != 1) { | |
6117 | BNX2X_ERR("CFC CAM_INIT failed\n"); | |
6118 | return -EBUSY; | |
6119 | } | |
6120 | REG_WR(bp, CFC_REG_DEBUG0, 0); | |
f1410647 | 6121 | |
f2e0899f DK |
6122 | if (CHIP_IS_E1(bp)) { |
6123 | /* read NIG statistic | |
6124 | to see if this is our first up since powerup */ | |
6125 | bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2); | |
6126 | val = *bnx2x_sp(bp, wb_data[0]); | |
34f80b04 | 6127 | |
f2e0899f DK |
6128 | /* do internal memory self test */ |
6129 | if ((val == 0) && bnx2x_int_mem_test(bp)) { | |
6130 | BNX2X_ERR("internal mem self test failed\n"); | |
6131 | return -EBUSY; | |
6132 | } | |
34f80b04 EG |
6133 | } |
6134 | ||
fd4ef40d EG |
6135 | bnx2x_setup_fan_failure_detection(bp); |
6136 | ||
34f80b04 EG |
6137 | /* clear PXP2 attentions */ |
6138 | REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0); | |
a2fbb9ea | 6139 | |
4a33bc03 | 6140 | bnx2x_enable_blocks_attention(bp); |
c9ee9206 | 6141 | bnx2x_enable_blocks_parity(bp); |
a2fbb9ea | 6142 | |
6bbca910 | 6143 | if (!BP_NOMCP(bp)) { |
619c5cb6 VZ |
6144 | if (CHIP_IS_E1x(bp)) |
6145 | bnx2x__common_init_phy(bp); | |
6bbca910 YR |
6146 | } else |
6147 | BNX2X_ERR("Bootcode is missing - can not initialize link\n"); | |
6148 | ||
34f80b04 EG |
6149 | return 0; |
6150 | } | |
a2fbb9ea | 6151 | |
619c5cb6 VZ |
6152 | /** |
6153 | * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase. | |
6154 | * | |
6155 | * @bp: driver handle | |
6156 | */ | |
6157 | static int bnx2x_init_hw_common_chip(struct bnx2x *bp) | |
6158 | { | |
6159 | int rc = bnx2x_init_hw_common(bp); | |
6160 | ||
6161 | if (rc) | |
6162 | return rc; | |
6163 | ||
6164 | /* In E2 2-PORT mode, same ext phy is used for the two paths */ | |
6165 | if (!BP_NOMCP(bp)) | |
6166 | bnx2x__common_init_phy(bp); | |
6167 | ||
6168 | return 0; | |
6169 | } | |
6170 | ||
523224a3 | 6171 | static int bnx2x_init_hw_port(struct bnx2x *bp) |
34f80b04 EG |
6172 | { |
6173 | int port = BP_PORT(bp); | |
619c5cb6 | 6174 | int init_phase = port ? PHASE_PORT1 : PHASE_PORT0; |
1c06328c | 6175 | u32 low, high; |
34f80b04 | 6176 | u32 val; |
a2fbb9ea | 6177 | |
619c5cb6 VZ |
6178 | bnx2x__link_reset(bp); |
6179 | ||
cdaa7cb8 | 6180 | DP(BNX2X_MSG_MCP, "starting port init port %d\n", port); |
34f80b04 EG |
6181 | |
6182 | REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0); | |
a2fbb9ea | 6183 | |
619c5cb6 VZ |
6184 | bnx2x_init_block(bp, BLOCK_MISC, init_phase); |
6185 | bnx2x_init_block(bp, BLOCK_PXP, init_phase); | |
6186 | bnx2x_init_block(bp, BLOCK_PXP2, init_phase); | |
ca00392c | 6187 | |
f2e0899f DK |
6188 | /* Timers bug workaround: disables the pf_master bit in pglue at |
6189 | * common phase, we need to enable it here before any dmae access are | |
6190 | * attempted. Therefore we manually added the enable-master to the | |
6191 | * port phase (it also happens in the function phase) | |
6192 | */ | |
619c5cb6 | 6193 | if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
6194 | REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); |
6195 | ||
619c5cb6 VZ |
6196 | bnx2x_init_block(bp, BLOCK_ATC, init_phase); |
6197 | bnx2x_init_block(bp, BLOCK_DMAE, init_phase); | |
6198 | bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase); | |
6199 | bnx2x_init_block(bp, BLOCK_QM, init_phase); | |
6200 | ||
6201 | bnx2x_init_block(bp, BLOCK_TCM, init_phase); | |
6202 | bnx2x_init_block(bp, BLOCK_UCM, init_phase); | |
6203 | bnx2x_init_block(bp, BLOCK_CCM, init_phase); | |
6204 | bnx2x_init_block(bp, BLOCK_XCM, init_phase); | |
a2fbb9ea | 6205 | |
523224a3 DK |
6206 | /* QM cid (connection) count */ |
6207 | bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET); | |
a2fbb9ea | 6208 | |
523224a3 | 6209 | #ifdef BCM_CNIC |
619c5cb6 | 6210 | bnx2x_init_block(bp, BLOCK_TM, init_phase); |
37b091ba MC |
6211 | REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20); |
6212 | REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31); | |
a2fbb9ea | 6213 | #endif |
cdaa7cb8 | 6214 | |
619c5cb6 | 6215 | bnx2x_init_block(bp, BLOCK_DORQ, init_phase); |
f2e0899f DK |
6216 | |
6217 | if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) { | |
619c5cb6 VZ |
6218 | bnx2x_init_block(bp, BLOCK_BRB1, init_phase); |
6219 | ||
6220 | if (IS_MF(bp)) | |
6221 | low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246); | |
6222 | else if (bp->dev->mtu > 4096) { | |
6223 | if (bp->flags & ONE_PORT_FLAG) | |
6224 | low = 160; | |
6225 | else { | |
6226 | val = bp->dev->mtu; | |
6227 | /* (24*1024 + val*4)/256 */ | |
6228 | low = 96 + (val/64) + | |
6229 | ((val % 64) ? 1 : 0); | |
6230 | } | |
6231 | } else | |
6232 | low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160); | |
6233 | high = low + 56; /* 14*1024/256 */ | |
f2e0899f DK |
6234 | REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low); |
6235 | REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high); | |
1c06328c | 6236 | } |
1c06328c | 6237 | |
619c5cb6 VZ |
6238 | if (CHIP_MODE_IS_4_PORT(bp)) |
6239 | REG_WR(bp, (BP_PORT(bp) ? | |
6240 | BRB1_REG_MAC_GUARANTIED_1 : | |
6241 | BRB1_REG_MAC_GUARANTIED_0), 40); | |
1c06328c | 6242 | |
ca00392c | 6243 | |
619c5cb6 VZ |
6244 | bnx2x_init_block(bp, BLOCK_PRS, init_phase); |
6245 | if (CHIP_IS_E3B0(bp)) | |
6246 | /* Ovlan exists only if we are in multi-function + | |
6247 | * switch-dependent mode, in switch-independent there | |
6248 | * is no ovlan headers | |
6249 | */ | |
6250 | REG_WR(bp, BP_PORT(bp) ? | |
6251 | PRS_REG_HDRS_AFTER_BASIC_PORT_1 : | |
6252 | PRS_REG_HDRS_AFTER_BASIC_PORT_0, | |
6253 | (bp->path_has_ovlan ? 7 : 6)); | |
356e2385 | 6254 | |
619c5cb6 VZ |
6255 | bnx2x_init_block(bp, BLOCK_TSDM, init_phase); |
6256 | bnx2x_init_block(bp, BLOCK_CSDM, init_phase); | |
6257 | bnx2x_init_block(bp, BLOCK_USDM, init_phase); | |
6258 | bnx2x_init_block(bp, BLOCK_XSDM, init_phase); | |
356e2385 | 6259 | |
619c5cb6 VZ |
6260 | bnx2x_init_block(bp, BLOCK_TSEM, init_phase); |
6261 | bnx2x_init_block(bp, BLOCK_USEM, init_phase); | |
6262 | bnx2x_init_block(bp, BLOCK_CSEM, init_phase); | |
6263 | bnx2x_init_block(bp, BLOCK_XSEM, init_phase); | |
34f80b04 | 6264 | |
619c5cb6 VZ |
6265 | bnx2x_init_block(bp, BLOCK_UPB, init_phase); |
6266 | bnx2x_init_block(bp, BLOCK_XPB, init_phase); | |
a2fbb9ea | 6267 | |
619c5cb6 VZ |
6268 | bnx2x_init_block(bp, BLOCK_PBF, init_phase); |
6269 | ||
6270 | if (CHIP_IS_E1x(bp)) { | |
f2e0899f DK |
6271 | /* configure PBF to work without PAUSE mtu 9000 */ |
6272 | REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0); | |
a2fbb9ea | 6273 | |
f2e0899f DK |
6274 | /* update threshold */ |
6275 | REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16)); | |
6276 | /* update init credit */ | |
6277 | REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22); | |
a2fbb9ea | 6278 | |
f2e0899f DK |
6279 | /* probe changes */ |
6280 | REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1); | |
6281 | udelay(50); | |
6282 | REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0); | |
6283 | } | |
a2fbb9ea | 6284 | |
37b091ba | 6285 | #ifdef BCM_CNIC |
619c5cb6 | 6286 | bnx2x_init_block(bp, BLOCK_SRC, init_phase); |
a2fbb9ea | 6287 | #endif |
619c5cb6 VZ |
6288 | bnx2x_init_block(bp, BLOCK_CDU, init_phase); |
6289 | bnx2x_init_block(bp, BLOCK_CFC, init_phase); | |
34f80b04 EG |
6290 | |
6291 | if (CHIP_IS_E1(bp)) { | |
6292 | REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); | |
6293 | REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); | |
6294 | } | |
619c5cb6 | 6295 | bnx2x_init_block(bp, BLOCK_HC, init_phase); |
34f80b04 | 6296 | |
619c5cb6 | 6297 | bnx2x_init_block(bp, BLOCK_IGU, init_phase); |
f2e0899f | 6298 | |
619c5cb6 | 6299 | bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase); |
34f80b04 EG |
6300 | /* init aeu_mask_attn_func_0/1: |
6301 | * - SF mode: bits 3-7 are masked. only bits 0-2 are in use | |
6302 | * - MF mode: bit 3 is masked. bits 0-2 are in use as in SF | |
6303 | * bits 4-7 are used for "per vn group attention" */ | |
e4901dde VZ |
6304 | val = IS_MF(bp) ? 0xF7 : 0x7; |
6305 | /* Enable DCBX attention for all but E1 */ | |
6306 | val |= CHIP_IS_E1(bp) ? 0 : 0x10; | |
6307 | REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val); | |
34f80b04 | 6308 | |
619c5cb6 VZ |
6309 | bnx2x_init_block(bp, BLOCK_NIG, init_phase); |
6310 | ||
6311 | if (!CHIP_IS_E1x(bp)) { | |
6312 | /* Bit-map indicating which L2 hdrs may appear after the | |
6313 | * basic Ethernet header | |
6314 | */ | |
6315 | REG_WR(bp, BP_PORT(bp) ? | |
6316 | NIG_REG_P1_HDRS_AFTER_BASIC : | |
6317 | NIG_REG_P0_HDRS_AFTER_BASIC, | |
6318 | IS_MF_SD(bp) ? 7 : 6); | |
6319 | ||
6320 | if (CHIP_IS_E3(bp)) | |
6321 | REG_WR(bp, BP_PORT(bp) ? | |
6322 | NIG_REG_LLH1_MF_MODE : | |
6323 | NIG_REG_LLH_MF_MODE, IS_MF(bp)); | |
6324 | } | |
6325 | if (!CHIP_IS_E3(bp)) | |
6326 | REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1); | |
34f80b04 | 6327 | |
f2e0899f | 6328 | if (!CHIP_IS_E1(bp)) { |
fb3bff17 | 6329 | /* 0x2 disable mf_ov, 0x1 enable */ |
34f80b04 | 6330 | REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4, |
0793f83f | 6331 | (IS_MF_SD(bp) ? 0x1 : 0x2)); |
34f80b04 | 6332 | |
619c5cb6 | 6333 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
6334 | val = 0; |
6335 | switch (bp->mf_mode) { | |
6336 | case MULTI_FUNCTION_SD: | |
6337 | val = 1; | |
6338 | break; | |
6339 | case MULTI_FUNCTION_SI: | |
6340 | val = 2; | |
6341 | break; | |
6342 | } | |
6343 | ||
6344 | REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE : | |
6345 | NIG_REG_LLH0_CLS_TYPE), val); | |
6346 | } | |
1c06328c EG |
6347 | { |
6348 | REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0); | |
6349 | REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0); | |
6350 | REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1); | |
6351 | } | |
34f80b04 EG |
6352 | } |
6353 | ||
619c5cb6 VZ |
6354 | |
6355 | /* If SPIO5 is set to generate interrupts, enable it for this port */ | |
6356 | val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN); | |
6357 | if (val & (1 << MISC_REGISTERS_SPIO_5)) { | |
4d295db0 EG |
6358 | u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : |
6359 | MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); | |
6360 | val = REG_RD(bp, reg_addr); | |
f1410647 | 6361 | val |= AEU_INPUTS_ATTN_BITS_SPIO5; |
4d295db0 | 6362 | REG_WR(bp, reg_addr, val); |
f1410647 | 6363 | } |
a2fbb9ea | 6364 | |
34f80b04 EG |
6365 | return 0; |
6366 | } | |
6367 | ||
34f80b04 EG |
6368 | static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr) |
6369 | { | |
6370 | int reg; | |
6371 | ||
f2e0899f | 6372 | if (CHIP_IS_E1(bp)) |
34f80b04 | 6373 | reg = PXP2_REG_RQ_ONCHIP_AT + index*8; |
f2e0899f DK |
6374 | else |
6375 | reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8; | |
34f80b04 EG |
6376 | |
6377 | bnx2x_wb_wr(bp, reg, ONCHIP_ADDR1(addr), ONCHIP_ADDR2(addr)); | |
6378 | } | |
6379 | ||
f2e0899f DK |
6380 | static inline void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id) |
6381 | { | |
619c5cb6 | 6382 | bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/); |
f2e0899f DK |
6383 | } |
6384 | ||
6385 | static inline void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func) | |
6386 | { | |
6387 | u32 i, base = FUNC_ILT_BASE(func); | |
6388 | for (i = base; i < base + ILT_PER_FUNC; i++) | |
6389 | bnx2x_ilt_wr(bp, i, 0); | |
6390 | } | |
6391 | ||
523224a3 | 6392 | static int bnx2x_init_hw_func(struct bnx2x *bp) |
34f80b04 EG |
6393 | { |
6394 | int port = BP_PORT(bp); | |
6395 | int func = BP_FUNC(bp); | |
619c5cb6 | 6396 | int init_phase = PHASE_PF0 + func; |
523224a3 DK |
6397 | struct bnx2x_ilt *ilt = BP_ILT(bp); |
6398 | u16 cdu_ilt_start; | |
8badd27a | 6399 | u32 addr, val; |
f4a66897 VZ |
6400 | u32 main_mem_base, main_mem_size, main_mem_prty_clr; |
6401 | int i, main_mem_width; | |
34f80b04 | 6402 | |
cdaa7cb8 | 6403 | DP(BNX2X_MSG_MCP, "starting func init func %d\n", func); |
34f80b04 | 6404 | |
619c5cb6 VZ |
6405 | /* FLR cleanup - hmmm */ |
6406 | if (!CHIP_IS_E1x(bp)) | |
6407 | bnx2x_pf_flr_clnup(bp); | |
6408 | ||
8badd27a | 6409 | /* set MSI reconfigure capability */ |
f2e0899f DK |
6410 | if (bp->common.int_block == INT_BLOCK_HC) { |
6411 | addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0); | |
6412 | val = REG_RD(bp, addr); | |
6413 | val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0; | |
6414 | REG_WR(bp, addr, val); | |
6415 | } | |
8badd27a | 6416 | |
619c5cb6 VZ |
6417 | bnx2x_init_block(bp, BLOCK_PXP, init_phase); |
6418 | bnx2x_init_block(bp, BLOCK_PXP2, init_phase); | |
6419 | ||
523224a3 DK |
6420 | ilt = BP_ILT(bp); |
6421 | cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start; | |
37b091ba | 6422 | |
523224a3 DK |
6423 | for (i = 0; i < L2_ILT_LINES(bp); i++) { |
6424 | ilt->lines[cdu_ilt_start + i].page = | |
6425 | bp->context.vcxt + (ILT_PAGE_CIDS * i); | |
6426 | ilt->lines[cdu_ilt_start + i].page_mapping = | |
6427 | bp->context.cxt_mapping + (CDU_ILT_PAGE_SZ * i); | |
6428 | /* cdu ilt pages are allocated manually so there's no need to | |
6429 | set the size */ | |
37b091ba | 6430 | } |
523224a3 | 6431 | bnx2x_ilt_init_op(bp, INITOP_SET); |
f85582f8 | 6432 | |
523224a3 DK |
6433 | #ifdef BCM_CNIC |
6434 | bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM); | |
37b091ba | 6435 | |
523224a3 DK |
6436 | /* T1 hash bits value determines the T1 number of entries */ |
6437 | REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS); | |
6438 | #endif | |
37b091ba | 6439 | |
523224a3 DK |
6440 | #ifndef BCM_CNIC |
6441 | /* set NIC mode */ | |
6442 | REG_WR(bp, PRS_REG_NIC_MODE, 1); | |
6443 | #endif /* BCM_CNIC */ | |
37b091ba | 6444 | |
619c5cb6 | 6445 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
6446 | u32 pf_conf = IGU_PF_CONF_FUNC_EN; |
6447 | ||
6448 | /* Turn on a single ISR mode in IGU if driver is going to use | |
6449 | * INT#x or MSI | |
6450 | */ | |
6451 | if (!(bp->flags & USING_MSIX_FLAG)) | |
6452 | pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN; | |
6453 | /* | |
6454 | * Timers workaround bug: function init part. | |
6455 | * Need to wait 20msec after initializing ILT, | |
6456 | * needed to make sure there are no requests in | |
6457 | * one of the PXP internal queues with "old" ILT addresses | |
6458 | */ | |
6459 | msleep(20); | |
6460 | /* | |
6461 | * Master enable - Due to WB DMAE writes performed before this | |
6462 | * register is re-initialized as part of the regular function | |
6463 | * init | |
6464 | */ | |
6465 | REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); | |
6466 | /* Enable the function in IGU */ | |
6467 | REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf); | |
6468 | } | |
6469 | ||
523224a3 | 6470 | bp->dmae_ready = 1; |
34f80b04 | 6471 | |
619c5cb6 | 6472 | bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase); |
523224a3 | 6473 | |
619c5cb6 | 6474 | if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
6475 | REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func); |
6476 | ||
619c5cb6 VZ |
6477 | bnx2x_init_block(bp, BLOCK_ATC, init_phase); |
6478 | bnx2x_init_block(bp, BLOCK_DMAE, init_phase); | |
6479 | bnx2x_init_block(bp, BLOCK_NIG, init_phase); | |
6480 | bnx2x_init_block(bp, BLOCK_SRC, init_phase); | |
6481 | bnx2x_init_block(bp, BLOCK_MISC, init_phase); | |
6482 | bnx2x_init_block(bp, BLOCK_TCM, init_phase); | |
6483 | bnx2x_init_block(bp, BLOCK_UCM, init_phase); | |
6484 | bnx2x_init_block(bp, BLOCK_CCM, init_phase); | |
6485 | bnx2x_init_block(bp, BLOCK_XCM, init_phase); | |
6486 | bnx2x_init_block(bp, BLOCK_TSEM, init_phase); | |
6487 | bnx2x_init_block(bp, BLOCK_USEM, init_phase); | |
6488 | bnx2x_init_block(bp, BLOCK_CSEM, init_phase); | |
6489 | bnx2x_init_block(bp, BLOCK_XSEM, init_phase); | |
6490 | ||
6491 | if (!CHIP_IS_E1x(bp)) | |
f2e0899f DK |
6492 | REG_WR(bp, QM_REG_PF_EN, 1); |
6493 | ||
619c5cb6 VZ |
6494 | if (!CHIP_IS_E1x(bp)) { |
6495 | REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); | |
6496 | REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); | |
6497 | REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); | |
6498 | REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); | |
6499 | } | |
6500 | bnx2x_init_block(bp, BLOCK_QM, init_phase); | |
6501 | ||
6502 | bnx2x_init_block(bp, BLOCK_TM, init_phase); | |
6503 | bnx2x_init_block(bp, BLOCK_DORQ, init_phase); | |
6504 | bnx2x_init_block(bp, BLOCK_BRB1, init_phase); | |
6505 | bnx2x_init_block(bp, BLOCK_PRS, init_phase); | |
6506 | bnx2x_init_block(bp, BLOCK_TSDM, init_phase); | |
6507 | bnx2x_init_block(bp, BLOCK_CSDM, init_phase); | |
6508 | bnx2x_init_block(bp, BLOCK_USDM, init_phase); | |
6509 | bnx2x_init_block(bp, BLOCK_XSDM, init_phase); | |
6510 | bnx2x_init_block(bp, BLOCK_UPB, init_phase); | |
6511 | bnx2x_init_block(bp, BLOCK_XPB, init_phase); | |
6512 | bnx2x_init_block(bp, BLOCK_PBF, init_phase); | |
6513 | if (!CHIP_IS_E1x(bp)) | |
f2e0899f DK |
6514 | REG_WR(bp, PBF_REG_DISABLE_PF, 0); |
6515 | ||
619c5cb6 | 6516 | bnx2x_init_block(bp, BLOCK_CDU, init_phase); |
523224a3 | 6517 | |
619c5cb6 | 6518 | bnx2x_init_block(bp, BLOCK_CFC, init_phase); |
34f80b04 | 6519 | |
619c5cb6 | 6520 | if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
6521 | REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1); |
6522 | ||
fb3bff17 | 6523 | if (IS_MF(bp)) { |
34f80b04 | 6524 | REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1); |
fb3bff17 | 6525 | REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->mf_ov); |
34f80b04 EG |
6526 | } |
6527 | ||
619c5cb6 | 6528 | bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase); |
523224a3 | 6529 | |
34f80b04 | 6530 | /* HC init per function */ |
f2e0899f DK |
6531 | if (bp->common.int_block == INT_BLOCK_HC) { |
6532 | if (CHIP_IS_E1H(bp)) { | |
6533 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); | |
6534 | ||
6535 | REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); | |
6536 | REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); | |
6537 | } | |
619c5cb6 | 6538 | bnx2x_init_block(bp, BLOCK_HC, init_phase); |
f2e0899f DK |
6539 | |
6540 | } else { | |
6541 | int num_segs, sb_idx, prod_offset; | |
6542 | ||
34f80b04 EG |
6543 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); |
6544 | ||
619c5cb6 | 6545 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
6546 | REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0); |
6547 | REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0); | |
6548 | } | |
6549 | ||
619c5cb6 | 6550 | bnx2x_init_block(bp, BLOCK_IGU, init_phase); |
f2e0899f | 6551 | |
619c5cb6 | 6552 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
6553 | int dsb_idx = 0; |
6554 | /** | |
6555 | * Producer memory: | |
6556 | * E2 mode: address 0-135 match to the mapping memory; | |
6557 | * 136 - PF0 default prod; 137 - PF1 default prod; | |
6558 | * 138 - PF2 default prod; 139 - PF3 default prod; | |
6559 | * 140 - PF0 attn prod; 141 - PF1 attn prod; | |
6560 | * 142 - PF2 attn prod; 143 - PF3 attn prod; | |
6561 | * 144-147 reserved. | |
6562 | * | |
6563 | * E1.5 mode - In backward compatible mode; | |
6564 | * for non default SB; each even line in the memory | |
6565 | * holds the U producer and each odd line hold | |
6566 | * the C producer. The first 128 producers are for | |
6567 | * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20 | |
6568 | * producers are for the DSB for each PF. | |
6569 | * Each PF has five segments: (the order inside each | |
6570 | * segment is PF0; PF1; PF2; PF3) - 128-131 U prods; | |
6571 | * 132-135 C prods; 136-139 X prods; 140-143 T prods; | |
6572 | * 144-147 attn prods; | |
6573 | */ | |
6574 | /* non-default-status-blocks */ | |
6575 | num_segs = CHIP_INT_MODE_IS_BC(bp) ? | |
6576 | IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS; | |
6577 | for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) { | |
6578 | prod_offset = (bp->igu_base_sb + sb_idx) * | |
6579 | num_segs; | |
6580 | ||
6581 | for (i = 0; i < num_segs; i++) { | |
6582 | addr = IGU_REG_PROD_CONS_MEMORY + | |
6583 | (prod_offset + i) * 4; | |
6584 | REG_WR(bp, addr, 0); | |
6585 | } | |
6586 | /* send consumer update with value 0 */ | |
6587 | bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx, | |
6588 | USTORM_ID, 0, IGU_INT_NOP, 1); | |
6589 | bnx2x_igu_clear_sb(bp, | |
6590 | bp->igu_base_sb + sb_idx); | |
6591 | } | |
6592 | ||
6593 | /* default-status-blocks */ | |
6594 | num_segs = CHIP_INT_MODE_IS_BC(bp) ? | |
6595 | IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS; | |
6596 | ||
6597 | if (CHIP_MODE_IS_4_PORT(bp)) | |
6598 | dsb_idx = BP_FUNC(bp); | |
6599 | else | |
6600 | dsb_idx = BP_E1HVN(bp); | |
6601 | ||
6602 | prod_offset = (CHIP_INT_MODE_IS_BC(bp) ? | |
6603 | IGU_BC_BASE_DSB_PROD + dsb_idx : | |
6604 | IGU_NORM_BASE_DSB_PROD + dsb_idx); | |
6605 | ||
6606 | for (i = 0; i < (num_segs * E1HVN_MAX); | |
6607 | i += E1HVN_MAX) { | |
6608 | addr = IGU_REG_PROD_CONS_MEMORY + | |
6609 | (prod_offset + i)*4; | |
6610 | REG_WR(bp, addr, 0); | |
6611 | } | |
6612 | /* send consumer update with 0 */ | |
6613 | if (CHIP_INT_MODE_IS_BC(bp)) { | |
6614 | bnx2x_ack_sb(bp, bp->igu_dsb_id, | |
6615 | USTORM_ID, 0, IGU_INT_NOP, 1); | |
6616 | bnx2x_ack_sb(bp, bp->igu_dsb_id, | |
6617 | CSTORM_ID, 0, IGU_INT_NOP, 1); | |
6618 | bnx2x_ack_sb(bp, bp->igu_dsb_id, | |
6619 | XSTORM_ID, 0, IGU_INT_NOP, 1); | |
6620 | bnx2x_ack_sb(bp, bp->igu_dsb_id, | |
6621 | TSTORM_ID, 0, IGU_INT_NOP, 1); | |
6622 | bnx2x_ack_sb(bp, bp->igu_dsb_id, | |
6623 | ATTENTION_ID, 0, IGU_INT_NOP, 1); | |
6624 | } else { | |
6625 | bnx2x_ack_sb(bp, bp->igu_dsb_id, | |
6626 | USTORM_ID, 0, IGU_INT_NOP, 1); | |
6627 | bnx2x_ack_sb(bp, bp->igu_dsb_id, | |
6628 | ATTENTION_ID, 0, IGU_INT_NOP, 1); | |
6629 | } | |
6630 | bnx2x_igu_clear_sb(bp, bp->igu_dsb_id); | |
6631 | ||
6632 | /* !!! these should become driver const once | |
6633 | rf-tool supports split-68 const */ | |
6634 | REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0); | |
6635 | REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0); | |
6636 | REG_WR(bp, IGU_REG_SB_MASK_LSB, 0); | |
6637 | REG_WR(bp, IGU_REG_SB_MASK_MSB, 0); | |
6638 | REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0); | |
6639 | REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0); | |
6640 | } | |
34f80b04 | 6641 | } |
34f80b04 | 6642 | |
c14423fe | 6643 | /* Reset PCIE errors for debug */ |
a2fbb9ea ET |
6644 | REG_WR(bp, 0x2114, 0xffffffff); |
6645 | REG_WR(bp, 0x2120, 0xffffffff); | |
523224a3 | 6646 | |
f4a66897 VZ |
6647 | if (CHIP_IS_E1x(bp)) { |
6648 | main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/ | |
6649 | main_mem_base = HC_REG_MAIN_MEMORY + | |
6650 | BP_PORT(bp) * (main_mem_size * 4); | |
6651 | main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR; | |
6652 | main_mem_width = 8; | |
6653 | ||
6654 | val = REG_RD(bp, main_mem_prty_clr); | |
6655 | if (val) | |
6656 | DP(BNX2X_MSG_MCP, "Hmmm... Parity errors in HC " | |
6657 | "block during " | |
6658 | "function init (0x%x)!\n", val); | |
6659 | ||
6660 | /* Clear "false" parity errors in MSI-X table */ | |
6661 | for (i = main_mem_base; | |
6662 | i < main_mem_base + main_mem_size * 4; | |
6663 | i += main_mem_width) { | |
6664 | bnx2x_read_dmae(bp, i, main_mem_width / 4); | |
6665 | bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), | |
6666 | i, main_mem_width / 4); | |
6667 | } | |
6668 | /* Clear HC parity attention */ | |
6669 | REG_RD(bp, main_mem_prty_clr); | |
6670 | } | |
6671 | ||
619c5cb6 VZ |
6672 | #ifdef BNX2X_STOP_ON_ERROR |
6673 | /* Enable STORMs SP logging */ | |
6674 | REG_WR8(bp, BAR_USTRORM_INTMEM + | |
6675 | USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); | |
6676 | REG_WR8(bp, BAR_TSTRORM_INTMEM + | |
6677 | TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); | |
6678 | REG_WR8(bp, BAR_CSTRORM_INTMEM + | |
6679 | CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); | |
6680 | REG_WR8(bp, BAR_XSTRORM_INTMEM + | |
6681 | XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); | |
6682 | #endif | |
6683 | ||
b7737c9b | 6684 | bnx2x_phy_probe(&bp->link_params); |
f85582f8 | 6685 | |
34f80b04 EG |
6686 | return 0; |
6687 | } | |
6688 | ||
a2fbb9ea | 6689 | |
9f6c9258 | 6690 | void bnx2x_free_mem(struct bnx2x *bp) |
a2fbb9ea | 6691 | { |
a2fbb9ea | 6692 | /* fastpath */ |
b3b83c3f | 6693 | bnx2x_free_fp_mem(bp); |
a2fbb9ea ET |
6694 | /* end of fastpath */ |
6695 | ||
6696 | BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping, | |
523224a3 | 6697 | sizeof(struct host_sp_status_block)); |
a2fbb9ea | 6698 | |
619c5cb6 VZ |
6699 | BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping, |
6700 | bp->fw_stats_data_sz + bp->fw_stats_req_sz); | |
6701 | ||
a2fbb9ea | 6702 | BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping, |
34f80b04 | 6703 | sizeof(struct bnx2x_slowpath)); |
a2fbb9ea | 6704 | |
523224a3 DK |
6705 | BNX2X_PCI_FREE(bp->context.vcxt, bp->context.cxt_mapping, |
6706 | bp->context.size); | |
6707 | ||
6708 | bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE); | |
6709 | ||
6710 | BNX2X_FREE(bp->ilt->lines); | |
f85582f8 | 6711 | |
37b091ba | 6712 | #ifdef BCM_CNIC |
619c5cb6 | 6713 | if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
6714 | BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping, |
6715 | sizeof(struct host_hc_status_block_e2)); | |
6716 | else | |
6717 | BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping, | |
6718 | sizeof(struct host_hc_status_block_e1x)); | |
f85582f8 | 6719 | |
523224a3 | 6720 | BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ); |
a2fbb9ea | 6721 | #endif |
f85582f8 | 6722 | |
7a9b2557 | 6723 | BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE); |
a2fbb9ea | 6724 | |
523224a3 DK |
6725 | BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping, |
6726 | BCM_PAGE_SIZE * NUM_EQ_PAGES); | |
619c5cb6 VZ |
6727 | } |
6728 | ||
6729 | static inline int bnx2x_alloc_fw_stats_mem(struct bnx2x *bp) | |
6730 | { | |
6731 | int num_groups; | |
6732 | ||
6733 | /* number of eth_queues */ | |
6734 | u8 num_queue_stats = BNX2X_NUM_ETH_QUEUES(bp); | |
6735 | ||
6736 | /* Total number of FW statistics requests = | |
6737 | * 1 for port stats + 1 for PF stats + num_eth_queues */ | |
6738 | bp->fw_stats_num = 2 + num_queue_stats; | |
523224a3 | 6739 | |
619c5cb6 VZ |
6740 | |
6741 | /* Request is built from stats_query_header and an array of | |
6742 | * stats_query_cmd_group each of which contains | |
6743 | * STATS_QUERY_CMD_COUNT rules. The real number or requests is | |
6744 | * configured in the stats_query_header. | |
6745 | */ | |
6746 | num_groups = (2 + num_queue_stats) / STATS_QUERY_CMD_COUNT + | |
6747 | (((2 + num_queue_stats) % STATS_QUERY_CMD_COUNT) ? 1 : 0); | |
6748 | ||
6749 | bp->fw_stats_req_sz = sizeof(struct stats_query_header) + | |
6750 | num_groups * sizeof(struct stats_query_cmd_group); | |
6751 | ||
6752 | /* Data for statistics requests + stats_conter | |
6753 | * | |
6754 | * stats_counter holds per-STORM counters that are incremented | |
6755 | * when STORM has finished with the current request. | |
6756 | */ | |
6757 | bp->fw_stats_data_sz = sizeof(struct per_port_stats) + | |
6758 | sizeof(struct per_pf_stats) + | |
6759 | sizeof(struct per_queue_stats) * num_queue_stats + | |
6760 | sizeof(struct stats_counter); | |
6761 | ||
6762 | BNX2X_PCI_ALLOC(bp->fw_stats, &bp->fw_stats_mapping, | |
6763 | bp->fw_stats_data_sz + bp->fw_stats_req_sz); | |
6764 | ||
6765 | /* Set shortcuts */ | |
6766 | bp->fw_stats_req = (struct bnx2x_fw_stats_req *)bp->fw_stats; | |
6767 | bp->fw_stats_req_mapping = bp->fw_stats_mapping; | |
6768 | ||
6769 | bp->fw_stats_data = (struct bnx2x_fw_stats_data *) | |
6770 | ((u8 *)bp->fw_stats + bp->fw_stats_req_sz); | |
6771 | ||
6772 | bp->fw_stats_data_mapping = bp->fw_stats_mapping + | |
6773 | bp->fw_stats_req_sz; | |
6774 | return 0; | |
6775 | ||
6776 | alloc_mem_err: | |
6777 | BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping, | |
6778 | bp->fw_stats_data_sz + bp->fw_stats_req_sz); | |
6779 | return -ENOMEM; | |
a2fbb9ea ET |
6780 | } |
6781 | ||
f2e0899f | 6782 | |
9f6c9258 | 6783 | int bnx2x_alloc_mem(struct bnx2x *bp) |
a2fbb9ea | 6784 | { |
523224a3 | 6785 | #ifdef BCM_CNIC |
619c5cb6 VZ |
6786 | if (!CHIP_IS_E1x(bp)) |
6787 | /* size = the status block + ramrod buffers */ | |
f2e0899f DK |
6788 | BNX2X_PCI_ALLOC(bp->cnic_sb.e2_sb, &bp->cnic_sb_mapping, |
6789 | sizeof(struct host_hc_status_block_e2)); | |
6790 | else | |
6791 | BNX2X_PCI_ALLOC(bp->cnic_sb.e1x_sb, &bp->cnic_sb_mapping, | |
6792 | sizeof(struct host_hc_status_block_e1x)); | |
8badd27a | 6793 | |
523224a3 DK |
6794 | /* allocate searcher T2 table */ |
6795 | BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ); | |
6796 | #endif | |
a2fbb9ea | 6797 | |
8badd27a | 6798 | |
523224a3 DK |
6799 | BNX2X_PCI_ALLOC(bp->def_status_blk, &bp->def_status_blk_mapping, |
6800 | sizeof(struct host_sp_status_block)); | |
a2fbb9ea | 6801 | |
523224a3 DK |
6802 | BNX2X_PCI_ALLOC(bp->slowpath, &bp->slowpath_mapping, |
6803 | sizeof(struct bnx2x_slowpath)); | |
a2fbb9ea | 6804 | |
619c5cb6 VZ |
6805 | /* Allocated memory for FW statistics */ |
6806 | if (bnx2x_alloc_fw_stats_mem(bp)) | |
6807 | goto alloc_mem_err; | |
6808 | ||
6383c0b3 | 6809 | bp->context.size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp); |
f85582f8 | 6810 | |
523224a3 DK |
6811 | BNX2X_PCI_ALLOC(bp->context.vcxt, &bp->context.cxt_mapping, |
6812 | bp->context.size); | |
65abd74d | 6813 | |
523224a3 | 6814 | BNX2X_ALLOC(bp->ilt->lines, sizeof(struct ilt_line) * ILT_MAX_LINES); |
65abd74d | 6815 | |
523224a3 DK |
6816 | if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC)) |
6817 | goto alloc_mem_err; | |
65abd74d | 6818 | |
9f6c9258 DK |
6819 | /* Slow path ring */ |
6820 | BNX2X_PCI_ALLOC(bp->spq, &bp->spq_mapping, BCM_PAGE_SIZE); | |
65abd74d | 6821 | |
523224a3 DK |
6822 | /* EQ */ |
6823 | BNX2X_PCI_ALLOC(bp->eq_ring, &bp->eq_mapping, | |
6824 | BCM_PAGE_SIZE * NUM_EQ_PAGES); | |
ab532cf3 | 6825 | |
b3b83c3f DK |
6826 | |
6827 | /* fastpath */ | |
6828 | /* need to be done at the end, since it's self adjusting to amount | |
6829 | * of memory available for RSS queues | |
6830 | */ | |
6831 | if (bnx2x_alloc_fp_mem(bp)) | |
6832 | goto alloc_mem_err; | |
9f6c9258 | 6833 | return 0; |
e1510706 | 6834 | |
9f6c9258 DK |
6835 | alloc_mem_err: |
6836 | bnx2x_free_mem(bp); | |
6837 | return -ENOMEM; | |
65abd74d YG |
6838 | } |
6839 | ||
a2fbb9ea ET |
6840 | /* |
6841 | * Init service functions | |
6842 | */ | |
a2fbb9ea | 6843 | |
619c5cb6 VZ |
6844 | int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac, |
6845 | struct bnx2x_vlan_mac_obj *obj, bool set, | |
6846 | int mac_type, unsigned long *ramrod_flags) | |
a2fbb9ea | 6847 | { |
619c5cb6 VZ |
6848 | int rc; |
6849 | struct bnx2x_vlan_mac_ramrod_params ramrod_param; | |
a2fbb9ea | 6850 | |
619c5cb6 | 6851 | memset(&ramrod_param, 0, sizeof(ramrod_param)); |
a2fbb9ea | 6852 | |
619c5cb6 VZ |
6853 | /* Fill general parameters */ |
6854 | ramrod_param.vlan_mac_obj = obj; | |
6855 | ramrod_param.ramrod_flags = *ramrod_flags; | |
a2fbb9ea | 6856 | |
619c5cb6 VZ |
6857 | /* Fill a user request section if needed */ |
6858 | if (!test_bit(RAMROD_CONT, ramrod_flags)) { | |
6859 | memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN); | |
a2fbb9ea | 6860 | |
619c5cb6 | 6861 | __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags); |
e3553b29 | 6862 | |
619c5cb6 VZ |
6863 | /* Set the command: ADD or DEL */ |
6864 | if (set) | |
6865 | ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD; | |
6866 | else | |
6867 | ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL; | |
a2fbb9ea ET |
6868 | } |
6869 | ||
619c5cb6 VZ |
6870 | rc = bnx2x_config_vlan_mac(bp, &ramrod_param); |
6871 | if (rc < 0) | |
6872 | BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del")); | |
6873 | return rc; | |
a2fbb9ea ET |
6874 | } |
6875 | ||
619c5cb6 VZ |
6876 | int bnx2x_del_all_macs(struct bnx2x *bp, |
6877 | struct bnx2x_vlan_mac_obj *mac_obj, | |
6878 | int mac_type, bool wait_for_comp) | |
e665bfda | 6879 | { |
619c5cb6 VZ |
6880 | int rc; |
6881 | unsigned long ramrod_flags = 0, vlan_mac_flags = 0; | |
0793f83f | 6882 | |
619c5cb6 VZ |
6883 | /* Wait for completion of requested */ |
6884 | if (wait_for_comp) | |
6885 | __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); | |
0793f83f | 6886 | |
619c5cb6 VZ |
6887 | /* Set the mac type of addresses we want to clear */ |
6888 | __set_bit(mac_type, &vlan_mac_flags); | |
0793f83f | 6889 | |
619c5cb6 VZ |
6890 | rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags); |
6891 | if (rc < 0) | |
6892 | BNX2X_ERR("Failed to delete MACs: %d\n", rc); | |
0793f83f | 6893 | |
619c5cb6 | 6894 | return rc; |
0793f83f DK |
6895 | } |
6896 | ||
619c5cb6 | 6897 | int bnx2x_set_eth_mac(struct bnx2x *bp, bool set) |
523224a3 | 6898 | { |
619c5cb6 | 6899 | unsigned long ramrod_flags = 0; |
e665bfda | 6900 | |
619c5cb6 | 6901 | DP(NETIF_MSG_IFUP, "Adding Eth MAC\n"); |
0793f83f | 6902 | |
619c5cb6 VZ |
6903 | __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); |
6904 | /* Eth MAC is set on RSS leading client (fp[0]) */ | |
6905 | return bnx2x_set_mac_one(bp, bp->dev->dev_addr, &bp->fp->mac_obj, set, | |
6906 | BNX2X_ETH_MAC, &ramrod_flags); | |
e665bfda | 6907 | } |
6e30dd4e | 6908 | |
619c5cb6 | 6909 | int bnx2x_setup_leading(struct bnx2x *bp) |
ec6ba945 | 6910 | { |
619c5cb6 | 6911 | return bnx2x_setup_queue(bp, &bp->fp[0], 1); |
993ac7b5 | 6912 | } |
a2fbb9ea | 6913 | |
d6214d7a | 6914 | /** |
e8920674 | 6915 | * bnx2x_set_int_mode - configure interrupt mode |
d6214d7a | 6916 | * |
e8920674 | 6917 | * @bp: driver handle |
d6214d7a | 6918 | * |
e8920674 | 6919 | * In case of MSI-X it will also try to enable MSI-X. |
d6214d7a | 6920 | */ |
9ee3d37b | 6921 | static void __devinit bnx2x_set_int_mode(struct bnx2x *bp) |
ca00392c | 6922 | { |
9ee3d37b | 6923 | switch (int_mode) { |
d6214d7a DK |
6924 | case INT_MODE_MSI: |
6925 | bnx2x_enable_msi(bp); | |
6926 | /* falling through... */ | |
6927 | case INT_MODE_INTx: | |
6383c0b3 | 6928 | bp->num_queues = 1 + NON_ETH_CONTEXT_USE; |
d6214d7a | 6929 | DP(NETIF_MSG_IFUP, "set number of queues to 1\n"); |
ca00392c | 6930 | break; |
d6214d7a DK |
6931 | default: |
6932 | /* Set number of queues according to bp->multi_mode value */ | |
6933 | bnx2x_set_num_queues(bp); | |
ca00392c | 6934 | |
d6214d7a DK |
6935 | DP(NETIF_MSG_IFUP, "set number of queues to %d\n", |
6936 | bp->num_queues); | |
ca00392c | 6937 | |
d6214d7a DK |
6938 | /* if we can't use MSI-X we only need one fp, |
6939 | * so try to enable MSI-X with the requested number of fp's | |
6940 | * and fallback to MSI or legacy INTx with one fp | |
6941 | */ | |
9ee3d37b | 6942 | if (bnx2x_enable_msix(bp)) { |
d6214d7a DK |
6943 | /* failed to enable MSI-X */ |
6944 | if (bp->multi_mode) | |
6945 | DP(NETIF_MSG_IFUP, | |
6946 | "Multi requested but failed to " | |
6947 | "enable MSI-X (%d), " | |
6948 | "set number of queues to %d\n", | |
6949 | bp->num_queues, | |
6383c0b3 AE |
6950 | 1 + NON_ETH_CONTEXT_USE); |
6951 | bp->num_queues = 1 + NON_ETH_CONTEXT_USE; | |
d6214d7a | 6952 | |
9ee3d37b | 6953 | /* Try to enable MSI */ |
d6214d7a DK |
6954 | if (!(bp->flags & DISABLE_MSI_FLAG)) |
6955 | bnx2x_enable_msi(bp); | |
6956 | } | |
9f6c9258 DK |
6957 | break; |
6958 | } | |
a2fbb9ea ET |
6959 | } |
6960 | ||
c2bff63f DK |
6961 | /* must be called prioir to any HW initializations */ |
6962 | static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp) | |
6963 | { | |
6964 | return L2_ILT_LINES(bp); | |
6965 | } | |
6966 | ||
523224a3 DK |
6967 | void bnx2x_ilt_set_info(struct bnx2x *bp) |
6968 | { | |
6969 | struct ilt_client_info *ilt_client; | |
6970 | struct bnx2x_ilt *ilt = BP_ILT(bp); | |
6971 | u16 line = 0; | |
6972 | ||
6973 | ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp)); | |
6974 | DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line); | |
6975 | ||
6976 | /* CDU */ | |
6977 | ilt_client = &ilt->clients[ILT_CLIENT_CDU]; | |
6978 | ilt_client->client_num = ILT_CLIENT_CDU; | |
6979 | ilt_client->page_size = CDU_ILT_PAGE_SZ; | |
6980 | ilt_client->flags = ILT_CLIENT_SKIP_MEM; | |
6981 | ilt_client->start = line; | |
619c5cb6 | 6982 | line += bnx2x_cid_ilt_lines(bp); |
523224a3 DK |
6983 | #ifdef BCM_CNIC |
6984 | line += CNIC_ILT_LINES; | |
6985 | #endif | |
6986 | ilt_client->end = line - 1; | |
6987 | ||
6988 | DP(BNX2X_MSG_SP, "ilt client[CDU]: start %d, end %d, psz 0x%x, " | |
6989 | "flags 0x%x, hw psz %d\n", | |
6990 | ilt_client->start, | |
6991 | ilt_client->end, | |
6992 | ilt_client->page_size, | |
6993 | ilt_client->flags, | |
6994 | ilog2(ilt_client->page_size >> 12)); | |
6995 | ||
6996 | /* QM */ | |
6997 | if (QM_INIT(bp->qm_cid_count)) { | |
6998 | ilt_client = &ilt->clients[ILT_CLIENT_QM]; | |
6999 | ilt_client->client_num = ILT_CLIENT_QM; | |
7000 | ilt_client->page_size = QM_ILT_PAGE_SZ; | |
7001 | ilt_client->flags = 0; | |
7002 | ilt_client->start = line; | |
7003 | ||
7004 | /* 4 bytes for each cid */ | |
7005 | line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4, | |
7006 | QM_ILT_PAGE_SZ); | |
7007 | ||
7008 | ilt_client->end = line - 1; | |
7009 | ||
7010 | DP(BNX2X_MSG_SP, "ilt client[QM]: start %d, end %d, psz 0x%x, " | |
7011 | "flags 0x%x, hw psz %d\n", | |
7012 | ilt_client->start, | |
7013 | ilt_client->end, | |
7014 | ilt_client->page_size, | |
7015 | ilt_client->flags, | |
7016 | ilog2(ilt_client->page_size >> 12)); | |
7017 | ||
7018 | } | |
7019 | /* SRC */ | |
7020 | ilt_client = &ilt->clients[ILT_CLIENT_SRC]; | |
7021 | #ifdef BCM_CNIC | |
7022 | ilt_client->client_num = ILT_CLIENT_SRC; | |
7023 | ilt_client->page_size = SRC_ILT_PAGE_SZ; | |
7024 | ilt_client->flags = 0; | |
7025 | ilt_client->start = line; | |
7026 | line += SRC_ILT_LINES; | |
7027 | ilt_client->end = line - 1; | |
7028 | ||
7029 | DP(BNX2X_MSG_SP, "ilt client[SRC]: start %d, end %d, psz 0x%x, " | |
7030 | "flags 0x%x, hw psz %d\n", | |
7031 | ilt_client->start, | |
7032 | ilt_client->end, | |
7033 | ilt_client->page_size, | |
7034 | ilt_client->flags, | |
7035 | ilog2(ilt_client->page_size >> 12)); | |
7036 | ||
7037 | #else | |
7038 | ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM); | |
7039 | #endif | |
9f6c9258 | 7040 | |
523224a3 DK |
7041 | /* TM */ |
7042 | ilt_client = &ilt->clients[ILT_CLIENT_TM]; | |
7043 | #ifdef BCM_CNIC | |
7044 | ilt_client->client_num = ILT_CLIENT_TM; | |
7045 | ilt_client->page_size = TM_ILT_PAGE_SZ; | |
7046 | ilt_client->flags = 0; | |
7047 | ilt_client->start = line; | |
7048 | line += TM_ILT_LINES; | |
7049 | ilt_client->end = line - 1; | |
7050 | ||
7051 | DP(BNX2X_MSG_SP, "ilt client[TM]: start %d, end %d, psz 0x%x, " | |
7052 | "flags 0x%x, hw psz %d\n", | |
7053 | ilt_client->start, | |
7054 | ilt_client->end, | |
7055 | ilt_client->page_size, | |
7056 | ilt_client->flags, | |
7057 | ilog2(ilt_client->page_size >> 12)); | |
9f6c9258 | 7058 | |
523224a3 DK |
7059 | #else |
7060 | ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM); | |
7061 | #endif | |
619c5cb6 | 7062 | BUG_ON(line > ILT_MAX_LINES); |
523224a3 | 7063 | } |
f85582f8 | 7064 | |
619c5cb6 VZ |
7065 | /** |
7066 | * bnx2x_pf_q_prep_init - prepare INIT transition parameters | |
7067 | * | |
7068 | * @bp: driver handle | |
7069 | * @fp: pointer to fastpath | |
7070 | * @init_params: pointer to parameters structure | |
7071 | * | |
7072 | * parameters configured: | |
7073 | * - HC configuration | |
7074 | * - Queue's CDU context | |
7075 | */ | |
7076 | static inline void bnx2x_pf_q_prep_init(struct bnx2x *bp, | |
7077 | struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params) | |
a2fbb9ea | 7078 | { |
6383c0b3 AE |
7079 | |
7080 | u8 cos; | |
619c5cb6 VZ |
7081 | /* FCoE Queue uses Default SB, thus has no HC capabilities */ |
7082 | if (!IS_FCOE_FP(fp)) { | |
7083 | __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags); | |
7084 | __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags); | |
7085 | ||
7086 | /* If HC is supporterd, enable host coalescing in the transition | |
7087 | * to INIT state. | |
7088 | */ | |
7089 | __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags); | |
7090 | __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags); | |
7091 | ||
7092 | /* HC rate */ | |
7093 | init_params->rx.hc_rate = bp->rx_ticks ? | |
7094 | (1000000 / bp->rx_ticks) : 0; | |
7095 | init_params->tx.hc_rate = bp->tx_ticks ? | |
7096 | (1000000 / bp->tx_ticks) : 0; | |
7097 | ||
7098 | /* FW SB ID */ | |
7099 | init_params->rx.fw_sb_id = init_params->tx.fw_sb_id = | |
7100 | fp->fw_sb_id; | |
7101 | ||
7102 | /* | |
7103 | * CQ index among the SB indices: FCoE clients uses the default | |
7104 | * SB, therefore it's different. | |
7105 | */ | |
6383c0b3 AE |
7106 | init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS; |
7107 | init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS; | |
619c5cb6 VZ |
7108 | } |
7109 | ||
6383c0b3 AE |
7110 | /* set maximum number of COSs supported by this queue */ |
7111 | init_params->max_cos = fp->max_cos; | |
7112 | ||
7113 | DP(BNX2X_MSG_SP, "fp: %d setting queue params max cos to: %d", | |
7114 | fp->index, init_params->max_cos); | |
7115 | ||
7116 | /* set the context pointers queue object */ | |
7117 | for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) | |
7118 | init_params->cxts[cos] = | |
7119 | &bp->context.vcxt[fp->txdata[cos].cid].eth; | |
619c5cb6 VZ |
7120 | } |
7121 | ||
6383c0b3 AE |
7122 | int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp, |
7123 | struct bnx2x_queue_state_params *q_params, | |
7124 | struct bnx2x_queue_setup_tx_only_params *tx_only_params, | |
7125 | int tx_index, bool leading) | |
7126 | { | |
7127 | memset(tx_only_params, 0, sizeof(*tx_only_params)); | |
7128 | ||
7129 | /* Set the command */ | |
7130 | q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY; | |
7131 | ||
7132 | /* Set tx-only QUEUE flags: don't zero statistics */ | |
7133 | tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false); | |
7134 | ||
7135 | /* choose the index of the cid to send the slow path on */ | |
7136 | tx_only_params->cid_index = tx_index; | |
7137 | ||
7138 | /* Set general TX_ONLY_SETUP parameters */ | |
7139 | bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index); | |
7140 | ||
7141 | /* Set Tx TX_ONLY_SETUP parameters */ | |
7142 | bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index); | |
7143 | ||
7144 | DP(BNX2X_MSG_SP, "preparing to send tx-only ramrod for connection:" | |
7145 | "cos %d, primary cid %d, cid %d, " | |
7146 | "client id %d, sp-client id %d, flags %lx", | |
7147 | tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX], | |
7148 | q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id, | |
7149 | tx_only_params->gen_params.spcl_id, tx_only_params->flags); | |
7150 | ||
7151 | /* send the ramrod */ | |
7152 | return bnx2x_queue_state_change(bp, q_params); | |
7153 | } | |
7154 | ||
7155 | ||
619c5cb6 VZ |
7156 | /** |
7157 | * bnx2x_setup_queue - setup queue | |
7158 | * | |
7159 | * @bp: driver handle | |
7160 | * @fp: pointer to fastpath | |
7161 | * @leading: is leading | |
7162 | * | |
7163 | * This function performs 2 steps in a Queue state machine | |
7164 | * actually: 1) RESET->INIT 2) INIT->SETUP | |
7165 | */ | |
7166 | ||
7167 | int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp, | |
7168 | bool leading) | |
7169 | { | |
7170 | struct bnx2x_queue_state_params q_params = {0}; | |
7171 | struct bnx2x_queue_setup_params *setup_params = | |
7172 | &q_params.params.setup; | |
6383c0b3 AE |
7173 | struct bnx2x_queue_setup_tx_only_params *tx_only_params = |
7174 | &q_params.params.tx_only; | |
a2fbb9ea | 7175 | int rc; |
6383c0b3 AE |
7176 | u8 tx_index; |
7177 | ||
7178 | DP(BNX2X_MSG_SP, "setting up queue %d", fp->index); | |
a2fbb9ea | 7179 | |
ec6ba945 VZ |
7180 | /* reset IGU state skip FCoE L2 queue */ |
7181 | if (!IS_FCOE_FP(fp)) | |
7182 | bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0, | |
523224a3 | 7183 | IGU_INT_ENABLE, 0); |
a2fbb9ea | 7184 | |
619c5cb6 VZ |
7185 | q_params.q_obj = &fp->q_obj; |
7186 | /* We want to wait for completion in this context */ | |
7187 | __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags); | |
a2fbb9ea | 7188 | |
619c5cb6 VZ |
7189 | /* Prepare the INIT parameters */ |
7190 | bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init); | |
ec6ba945 | 7191 | |
619c5cb6 VZ |
7192 | /* Set the command */ |
7193 | q_params.cmd = BNX2X_Q_CMD_INIT; | |
7194 | ||
7195 | /* Change the state to INIT */ | |
7196 | rc = bnx2x_queue_state_change(bp, &q_params); | |
7197 | if (rc) { | |
6383c0b3 | 7198 | BNX2X_ERR("Queue(%d) INIT failed\n", fp->index); |
619c5cb6 VZ |
7199 | return rc; |
7200 | } | |
ec6ba945 | 7201 | |
6383c0b3 AE |
7202 | DP(BNX2X_MSG_SP, "init complete"); |
7203 | ||
7204 | ||
619c5cb6 VZ |
7205 | /* Now move the Queue to the SETUP state... */ |
7206 | memset(setup_params, 0, sizeof(*setup_params)); | |
a2fbb9ea | 7207 | |
619c5cb6 VZ |
7208 | /* Set QUEUE flags */ |
7209 | setup_params->flags = bnx2x_get_q_flags(bp, fp, leading); | |
523224a3 | 7210 | |
619c5cb6 | 7211 | /* Set general SETUP parameters */ |
6383c0b3 AE |
7212 | bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params, |
7213 | FIRST_TX_COS_INDEX); | |
619c5cb6 | 7214 | |
6383c0b3 | 7215 | bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params, |
619c5cb6 VZ |
7216 | &setup_params->rxq_params); |
7217 | ||
6383c0b3 AE |
7218 | bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params, |
7219 | FIRST_TX_COS_INDEX); | |
619c5cb6 VZ |
7220 | |
7221 | /* Set the command */ | |
7222 | q_params.cmd = BNX2X_Q_CMD_SETUP; | |
7223 | ||
7224 | /* Change the state to SETUP */ | |
7225 | rc = bnx2x_queue_state_change(bp, &q_params); | |
6383c0b3 AE |
7226 | if (rc) { |
7227 | BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index); | |
7228 | return rc; | |
7229 | } | |
7230 | ||
7231 | /* loop through the relevant tx-only indices */ | |
7232 | for (tx_index = FIRST_TX_ONLY_COS_INDEX; | |
7233 | tx_index < fp->max_cos; | |
7234 | tx_index++) { | |
7235 | ||
7236 | /* prepare and send tx-only ramrod*/ | |
7237 | rc = bnx2x_setup_tx_only(bp, fp, &q_params, | |
7238 | tx_only_params, tx_index, leading); | |
7239 | if (rc) { | |
7240 | BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n", | |
7241 | fp->index, tx_index); | |
7242 | return rc; | |
7243 | } | |
7244 | } | |
523224a3 | 7245 | |
34f80b04 | 7246 | return rc; |
a2fbb9ea ET |
7247 | } |
7248 | ||
619c5cb6 | 7249 | static int bnx2x_stop_queue(struct bnx2x *bp, int index) |
a2fbb9ea | 7250 | { |
619c5cb6 | 7251 | struct bnx2x_fastpath *fp = &bp->fp[index]; |
6383c0b3 | 7252 | struct bnx2x_fp_txdata *txdata; |
619c5cb6 | 7253 | struct bnx2x_queue_state_params q_params = {0}; |
6383c0b3 AE |
7254 | int rc, tx_index; |
7255 | ||
7256 | DP(BNX2X_MSG_SP, "stopping queue %d cid %d", index, fp->cid); | |
a2fbb9ea | 7257 | |
619c5cb6 VZ |
7258 | q_params.q_obj = &fp->q_obj; |
7259 | /* We want to wait for completion in this context */ | |
7260 | __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags); | |
a2fbb9ea | 7261 | |
6383c0b3 AE |
7262 | |
7263 | /* close tx-only connections */ | |
7264 | for (tx_index = FIRST_TX_ONLY_COS_INDEX; | |
7265 | tx_index < fp->max_cos; | |
7266 | tx_index++){ | |
7267 | ||
7268 | /* ascertain this is a normal queue*/ | |
7269 | txdata = &fp->txdata[tx_index]; | |
7270 | ||
7271 | DP(BNX2X_MSG_SP, "stopping tx-only queue %d", | |
7272 | txdata->txq_index); | |
7273 | ||
7274 | /* send halt terminate on tx-only connection */ | |
7275 | q_params.cmd = BNX2X_Q_CMD_TERMINATE; | |
7276 | memset(&q_params.params.terminate, 0, | |
7277 | sizeof(q_params.params.terminate)); | |
7278 | q_params.params.terminate.cid_index = tx_index; | |
7279 | ||
7280 | rc = bnx2x_queue_state_change(bp, &q_params); | |
7281 | if (rc) | |
7282 | return rc; | |
7283 | ||
7284 | /* send halt terminate on tx-only connection */ | |
7285 | q_params.cmd = BNX2X_Q_CMD_CFC_DEL; | |
7286 | memset(&q_params.params.cfc_del, 0, | |
7287 | sizeof(q_params.params.cfc_del)); | |
7288 | q_params.params.cfc_del.cid_index = tx_index; | |
7289 | rc = bnx2x_queue_state_change(bp, &q_params); | |
7290 | if (rc) | |
7291 | return rc; | |
7292 | } | |
7293 | /* Stop the primary connection: */ | |
7294 | /* ...halt the connection */ | |
619c5cb6 VZ |
7295 | q_params.cmd = BNX2X_Q_CMD_HALT; |
7296 | rc = bnx2x_queue_state_change(bp, &q_params); | |
7297 | if (rc) | |
da5a662a | 7298 | return rc; |
a2fbb9ea | 7299 | |
6383c0b3 | 7300 | /* ...terminate the connection */ |
619c5cb6 | 7301 | q_params.cmd = BNX2X_Q_CMD_TERMINATE; |
6383c0b3 AE |
7302 | memset(&q_params.params.terminate, 0, |
7303 | sizeof(q_params.params.terminate)); | |
7304 | q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX; | |
619c5cb6 VZ |
7305 | rc = bnx2x_queue_state_change(bp, &q_params); |
7306 | if (rc) | |
523224a3 | 7307 | return rc; |
6383c0b3 | 7308 | /* ...delete cfc entry */ |
619c5cb6 | 7309 | q_params.cmd = BNX2X_Q_CMD_CFC_DEL; |
6383c0b3 AE |
7310 | memset(&q_params.params.cfc_del, 0, |
7311 | sizeof(q_params.params.cfc_del)); | |
7312 | q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX; | |
619c5cb6 | 7313 | return bnx2x_queue_state_change(bp, &q_params); |
523224a3 DK |
7314 | } |
7315 | ||
7316 | ||
34f80b04 EG |
7317 | static void bnx2x_reset_func(struct bnx2x *bp) |
7318 | { | |
7319 | int port = BP_PORT(bp); | |
7320 | int func = BP_FUNC(bp); | |
f2e0899f | 7321 | int i; |
523224a3 DK |
7322 | |
7323 | /* Disable the function in the FW */ | |
7324 | REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0); | |
7325 | REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0); | |
7326 | REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0); | |
7327 | REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0); | |
7328 | ||
7329 | /* FP SBs */ | |
ec6ba945 | 7330 | for_each_eth_queue(bp, i) { |
523224a3 | 7331 | struct bnx2x_fastpath *fp = &bp->fp[i]; |
619c5cb6 | 7332 | REG_WR8(bp, BAR_CSTRORM_INTMEM + |
6383c0b3 AE |
7333 | CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id), |
7334 | SB_DISABLED); | |
523224a3 DK |
7335 | } |
7336 | ||
619c5cb6 VZ |
7337 | #ifdef BCM_CNIC |
7338 | /* CNIC SB */ | |
7339 | REG_WR8(bp, BAR_CSTRORM_INTMEM + | |
7340 | CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(bnx2x_cnic_fw_sb_id(bp)), | |
7341 | SB_DISABLED); | |
7342 | #endif | |
523224a3 | 7343 | /* SP SB */ |
619c5cb6 | 7344 | REG_WR8(bp, BAR_CSTRORM_INTMEM + |
6383c0b3 AE |
7345 | CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func), |
7346 | SB_DISABLED); | |
523224a3 DK |
7347 | |
7348 | for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++) | |
7349 | REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func), | |
7350 | 0); | |
34f80b04 EG |
7351 | |
7352 | /* Configure IGU */ | |
f2e0899f DK |
7353 | if (bp->common.int_block == INT_BLOCK_HC) { |
7354 | REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); | |
7355 | REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); | |
7356 | } else { | |
7357 | REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0); | |
7358 | REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0); | |
7359 | } | |
34f80b04 | 7360 | |
37b091ba MC |
7361 | #ifdef BCM_CNIC |
7362 | /* Disable Timer scan */ | |
7363 | REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0); | |
7364 | /* | |
7365 | * Wait for at least 10ms and up to 2 second for the timers scan to | |
7366 | * complete | |
7367 | */ | |
7368 | for (i = 0; i < 200; i++) { | |
7369 | msleep(10); | |
7370 | if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4)) | |
7371 | break; | |
7372 | } | |
7373 | #endif | |
34f80b04 | 7374 | /* Clear ILT */ |
f2e0899f DK |
7375 | bnx2x_clear_func_ilt(bp, func); |
7376 | ||
7377 | /* Timers workaround bug for E2: if this is vnic-3, | |
7378 | * we need to set the entire ilt range for this timers. | |
7379 | */ | |
619c5cb6 | 7380 | if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) { |
f2e0899f DK |
7381 | struct ilt_client_info ilt_cli; |
7382 | /* use dummy TM client */ | |
7383 | memset(&ilt_cli, 0, sizeof(struct ilt_client_info)); | |
7384 | ilt_cli.start = 0; | |
7385 | ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1; | |
7386 | ilt_cli.client_num = ILT_CLIENT_TM; | |
7387 | ||
7388 | bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR); | |
7389 | } | |
7390 | ||
7391 | /* this assumes that reset_port() called before reset_func()*/ | |
619c5cb6 | 7392 | if (!CHIP_IS_E1x(bp)) |
f2e0899f | 7393 | bnx2x_pf_disable(bp); |
523224a3 DK |
7394 | |
7395 | bp->dmae_ready = 0; | |
34f80b04 EG |
7396 | } |
7397 | ||
7398 | static void bnx2x_reset_port(struct bnx2x *bp) | |
7399 | { | |
7400 | int port = BP_PORT(bp); | |
7401 | u32 val; | |
7402 | ||
619c5cb6 VZ |
7403 | /* Reset physical Link */ |
7404 | bnx2x__link_reset(bp); | |
7405 | ||
34f80b04 EG |
7406 | REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0); |
7407 | ||
7408 | /* Do not rcv packets to BRB */ | |
7409 | REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0); | |
7410 | /* Do not direct rcv packets that are not for MCP to the BRB */ | |
7411 | REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP : | |
7412 | NIG_REG_LLH0_BRB1_NOT_MCP), 0x0); | |
7413 | ||
7414 | /* Configure AEU */ | |
7415 | REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0); | |
7416 | ||
7417 | msleep(100); | |
7418 | /* Check for BRB port occupancy */ | |
7419 | val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4); | |
7420 | if (val) | |
7421 | DP(NETIF_MSG_IFDOWN, | |
33471629 | 7422 | "BRB1 is not empty %d blocks are occupied\n", val); |
34f80b04 EG |
7423 | |
7424 | /* TODO: Close Doorbell port? */ | |
7425 | } | |
7426 | ||
619c5cb6 | 7427 | static inline int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code) |
34f80b04 | 7428 | { |
619c5cb6 | 7429 | struct bnx2x_func_state_params func_params = {0}; |
34f80b04 | 7430 | |
619c5cb6 VZ |
7431 | /* Prepare parameters for function state transitions */ |
7432 | __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); | |
34f80b04 | 7433 | |
619c5cb6 VZ |
7434 | func_params.f_obj = &bp->func_obj; |
7435 | func_params.cmd = BNX2X_F_CMD_HW_RESET; | |
34f80b04 | 7436 | |
619c5cb6 | 7437 | func_params.params.hw_init.load_phase = load_code; |
49d66772 | 7438 | |
619c5cb6 | 7439 | return bnx2x_func_state_change(bp, &func_params); |
34f80b04 EG |
7440 | } |
7441 | ||
619c5cb6 | 7442 | static inline int bnx2x_func_stop(struct bnx2x *bp) |
ec6ba945 | 7443 | { |
619c5cb6 VZ |
7444 | struct bnx2x_func_state_params func_params = {0}; |
7445 | int rc; | |
228241eb | 7446 | |
619c5cb6 VZ |
7447 | /* Prepare parameters for function state transitions */ |
7448 | __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); | |
7449 | func_params.f_obj = &bp->func_obj; | |
7450 | func_params.cmd = BNX2X_F_CMD_STOP; | |
da5a662a | 7451 | |
619c5cb6 VZ |
7452 | /* |
7453 | * Try to stop the function the 'good way'. If fails (in case | |
7454 | * of a parity error during bnx2x_chip_cleanup()) and we are | |
7455 | * not in a debug mode, perform a state transaction in order to | |
7456 | * enable further HW_RESET transaction. | |
7457 | */ | |
7458 | rc = bnx2x_func_state_change(bp, &func_params); | |
7459 | if (rc) { | |
34f80b04 | 7460 | #ifdef BNX2X_STOP_ON_ERROR |
619c5cb6 | 7461 | return rc; |
34f80b04 | 7462 | #else |
619c5cb6 VZ |
7463 | BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry " |
7464 | "transaction\n"); | |
7465 | __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags); | |
7466 | return bnx2x_func_state_change(bp, &func_params); | |
34f80b04 | 7467 | #endif |
228241eb | 7468 | } |
a2fbb9ea | 7469 | |
619c5cb6 VZ |
7470 | return 0; |
7471 | } | |
523224a3 | 7472 | |
619c5cb6 VZ |
7473 | /** |
7474 | * bnx2x_send_unload_req - request unload mode from the MCP. | |
7475 | * | |
7476 | * @bp: driver handle | |
7477 | * @unload_mode: requested function's unload mode | |
7478 | * | |
7479 | * Return unload mode returned by the MCP: COMMON, PORT or FUNC. | |
7480 | */ | |
7481 | u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode) | |
7482 | { | |
7483 | u32 reset_code = 0; | |
7484 | int port = BP_PORT(bp); | |
3101c2bc | 7485 | |
619c5cb6 | 7486 | /* Select the UNLOAD request mode */ |
65abd74d YG |
7487 | if (unload_mode == UNLOAD_NORMAL) |
7488 | reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; | |
7489 | ||
7d0446c2 | 7490 | else if (bp->flags & NO_WOL_FLAG) |
65abd74d | 7491 | reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP; |
65abd74d | 7492 | |
7d0446c2 | 7493 | else if (bp->wol) { |
65abd74d YG |
7494 | u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; |
7495 | u8 *mac_addr = bp->dev->dev_addr; | |
7496 | u32 val; | |
7497 | /* The mac address is written to entries 1-4 to | |
7498 | preserve entry 0 which is used by the PMF */ | |
7499 | u8 entry = (BP_E1HVN(bp) + 1)*8; | |
7500 | ||
7501 | val = (mac_addr[0] << 8) | mac_addr[1]; | |
7502 | EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val); | |
7503 | ||
7504 | val = (mac_addr[2] << 24) | (mac_addr[3] << 16) | | |
7505 | (mac_addr[4] << 8) | mac_addr[5]; | |
7506 | EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val); | |
7507 | ||
7508 | reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN; | |
7509 | ||
7510 | } else | |
7511 | reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; | |
da5a662a | 7512 | |
619c5cb6 VZ |
7513 | /* Send the request to the MCP */ |
7514 | if (!BP_NOMCP(bp)) | |
7515 | reset_code = bnx2x_fw_command(bp, reset_code, 0); | |
7516 | else { | |
7517 | int path = BP_PATH(bp); | |
7518 | ||
7519 | DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d] " | |
7520 | "%d, %d, %d\n", | |
7521 | path, load_count[path][0], load_count[path][1], | |
7522 | load_count[path][2]); | |
7523 | load_count[path][0]--; | |
7524 | load_count[path][1 + port]--; | |
7525 | DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d] " | |
7526 | "%d, %d, %d\n", | |
7527 | path, load_count[path][0], load_count[path][1], | |
7528 | load_count[path][2]); | |
7529 | if (load_count[path][0] == 0) | |
7530 | reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON; | |
7531 | else if (load_count[path][1 + port] == 0) | |
7532 | reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT; | |
7533 | else | |
7534 | reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION; | |
7535 | } | |
7536 | ||
7537 | return reset_code; | |
7538 | } | |
7539 | ||
7540 | /** | |
7541 | * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP. | |
7542 | * | |
7543 | * @bp: driver handle | |
7544 | */ | |
7545 | void bnx2x_send_unload_done(struct bnx2x *bp) | |
7546 | { | |
7547 | /* Report UNLOAD_DONE to MCP */ | |
7548 | if (!BP_NOMCP(bp)) | |
7549 | bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0); | |
7550 | } | |
7551 | ||
6debea87 DK |
7552 | static inline int bnx2x_func_wait_started(struct bnx2x *bp) |
7553 | { | |
7554 | int tout = 50; | |
7555 | int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; | |
7556 | ||
7557 | if (!bp->port.pmf) | |
7558 | return 0; | |
7559 | ||
7560 | /* | |
7561 | * (assumption: No Attention from MCP at this stage) | |
7562 | * PMF probably in the middle of TXdisable/enable transaction | |
7563 | * 1. Sync IRS for default SB | |
7564 | * 2. Sync SP queue - this guarantes us that attention handling started | |
7565 | * 3. Wait, that TXdisable/enable transaction completes | |
7566 | * | |
7567 | * 1+2 guranty that if DCBx attention was scheduled it already changed | |
7568 | * pending bit of transaction from STARTED-->TX_STOPPED, if we alredy | |
7569 | * received complettion for the transaction the state is TX_STOPPED. | |
7570 | * State will return to STARTED after completion of TX_STOPPED-->STARTED | |
7571 | * transaction. | |
7572 | */ | |
7573 | ||
7574 | /* make sure default SB ISR is done */ | |
7575 | if (msix) | |
7576 | synchronize_irq(bp->msix_table[0].vector); | |
7577 | else | |
7578 | synchronize_irq(bp->pdev->irq); | |
7579 | ||
7580 | flush_workqueue(bnx2x_wq); | |
7581 | ||
7582 | while (bnx2x_func_get_state(bp, &bp->func_obj) != | |
7583 | BNX2X_F_STATE_STARTED && tout--) | |
7584 | msleep(20); | |
7585 | ||
7586 | if (bnx2x_func_get_state(bp, &bp->func_obj) != | |
7587 | BNX2X_F_STATE_STARTED) { | |
7588 | #ifdef BNX2X_STOP_ON_ERROR | |
7589 | return -EBUSY; | |
7590 | #else | |
7591 | /* | |
7592 | * Failed to complete the transaction in a "good way" | |
7593 | * Force both transactions with CLR bit | |
7594 | */ | |
7595 | struct bnx2x_func_state_params func_params = {0}; | |
7596 | ||
7597 | DP(BNX2X_MSG_SP, "Hmmm... unexpected function state! " | |
7598 | "Forcing STARTED-->TX_ST0PPED-->STARTED\n"); | |
7599 | ||
7600 | func_params.f_obj = &bp->func_obj; | |
7601 | __set_bit(RAMROD_DRV_CLR_ONLY, | |
7602 | &func_params.ramrod_flags); | |
7603 | ||
7604 | /* STARTED-->TX_ST0PPED */ | |
7605 | func_params.cmd = BNX2X_F_CMD_TX_STOP; | |
7606 | bnx2x_func_state_change(bp, &func_params); | |
7607 | ||
7608 | /* TX_ST0PPED-->STARTED */ | |
7609 | func_params.cmd = BNX2X_F_CMD_TX_START; | |
7610 | return bnx2x_func_state_change(bp, &func_params); | |
7611 | #endif | |
7612 | } | |
7613 | ||
7614 | return 0; | |
7615 | } | |
7616 | ||
619c5cb6 VZ |
7617 | void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode) |
7618 | { | |
7619 | int port = BP_PORT(bp); | |
6383c0b3 AE |
7620 | int i, rc = 0; |
7621 | u8 cos; | |
619c5cb6 VZ |
7622 | struct bnx2x_mcast_ramrod_params rparam = {0}; |
7623 | u32 reset_code; | |
7624 | ||
7625 | /* Wait until tx fastpath tasks complete */ | |
7626 | for_each_tx_queue(bp, i) { | |
7627 | struct bnx2x_fastpath *fp = &bp->fp[i]; | |
7628 | ||
6383c0b3 AE |
7629 | for_each_cos_in_tx_queue(fp, cos) |
7630 | rc = bnx2x_clean_tx_queue(bp, &fp->txdata[cos]); | |
619c5cb6 VZ |
7631 | #ifdef BNX2X_STOP_ON_ERROR |
7632 | if (rc) | |
7633 | return; | |
7634 | #endif | |
7635 | } | |
7636 | ||
7637 | /* Give HW time to discard old tx messages */ | |
7638 | usleep_range(1000, 1000); | |
7639 | ||
7640 | /* Clean all ETH MACs */ | |
7641 | rc = bnx2x_del_all_macs(bp, &bp->fp[0].mac_obj, BNX2X_ETH_MAC, false); | |
7642 | if (rc < 0) | |
7643 | BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc); | |
7644 | ||
7645 | /* Clean up UC list */ | |
7646 | rc = bnx2x_del_all_macs(bp, &bp->fp[0].mac_obj, BNX2X_UC_LIST_MAC, | |
7647 | true); | |
7648 | if (rc < 0) | |
7649 | BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: " | |
7650 | "%d\n", rc); | |
7651 | ||
7652 | /* Disable LLH */ | |
7653 | if (!CHIP_IS_E1(bp)) | |
7654 | REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0); | |
7655 | ||
7656 | /* Set "drop all" (stop Rx). | |
7657 | * We need to take a netif_addr_lock() here in order to prevent | |
7658 | * a race between the completion code and this code. | |
7659 | */ | |
7660 | netif_addr_lock_bh(bp->dev); | |
7661 | /* Schedule the rx_mode command */ | |
7662 | if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) | |
7663 | set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state); | |
7664 | else | |
7665 | bnx2x_set_storm_rx_mode(bp); | |
7666 | ||
7667 | /* Cleanup multicast configuration */ | |
7668 | rparam.mcast_obj = &bp->mcast_obj; | |
7669 | rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL); | |
7670 | if (rc < 0) | |
7671 | BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc); | |
7672 | ||
7673 | netif_addr_unlock_bh(bp->dev); | |
7674 | ||
7675 | ||
6debea87 DK |
7676 | |
7677 | /* | |
7678 | * Send the UNLOAD_REQUEST to the MCP. This will return if | |
7679 | * this function should perform FUNC, PORT or COMMON HW | |
7680 | * reset. | |
7681 | */ | |
7682 | reset_code = bnx2x_send_unload_req(bp, unload_mode); | |
7683 | ||
7684 | /* | |
7685 | * (assumption: No Attention from MCP at this stage) | |
7686 | * PMF probably in the middle of TXdisable/enable transaction | |
7687 | */ | |
7688 | rc = bnx2x_func_wait_started(bp); | |
7689 | if (rc) { | |
7690 | BNX2X_ERR("bnx2x_func_wait_started failed\n"); | |
7691 | #ifdef BNX2X_STOP_ON_ERROR | |
7692 | return; | |
7693 | #endif | |
7694 | } | |
7695 | ||
34f80b04 | 7696 | /* Close multi and leading connections |
619c5cb6 VZ |
7697 | * Completions for ramrods are collected in a synchronous way |
7698 | */ | |
523224a3 | 7699 | for_each_queue(bp, i) |
619c5cb6 | 7700 | if (bnx2x_stop_queue(bp, i)) |
523224a3 DK |
7701 | #ifdef BNX2X_STOP_ON_ERROR |
7702 | return; | |
7703 | #else | |
228241eb | 7704 | goto unload_error; |
523224a3 | 7705 | #endif |
619c5cb6 VZ |
7706 | /* If SP settings didn't get completed so far - something |
7707 | * very wrong has happen. | |
7708 | */ | |
7709 | if (!bnx2x_wait_sp_comp(bp, ~0x0UL)) | |
7710 | BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n"); | |
a2fbb9ea | 7711 | |
619c5cb6 VZ |
7712 | #ifndef BNX2X_STOP_ON_ERROR |
7713 | unload_error: | |
7714 | #endif | |
523224a3 | 7715 | rc = bnx2x_func_stop(bp); |
da5a662a | 7716 | if (rc) { |
523224a3 | 7717 | BNX2X_ERR("Function stop failed!\n"); |
da5a662a | 7718 | #ifdef BNX2X_STOP_ON_ERROR |
523224a3 | 7719 | return; |
523224a3 | 7720 | #endif |
34f80b04 | 7721 | } |
a2fbb9ea | 7722 | |
523224a3 DK |
7723 | /* Disable HW interrupts, NAPI */ |
7724 | bnx2x_netif_stop(bp, 1); | |
7725 | ||
7726 | /* Release IRQs */ | |
d6214d7a | 7727 | bnx2x_free_irq(bp); |
523224a3 | 7728 | |
a2fbb9ea | 7729 | /* Reset the chip */ |
619c5cb6 VZ |
7730 | rc = bnx2x_reset_hw(bp, reset_code); |
7731 | if (rc) | |
7732 | BNX2X_ERR("HW_RESET failed\n"); | |
a2fbb9ea | 7733 | |
356e2385 | 7734 | |
619c5cb6 VZ |
7735 | /* Report UNLOAD_DONE to MCP */ |
7736 | bnx2x_send_unload_done(bp); | |
72fd0718 VZ |
7737 | } |
7738 | ||
9f6c9258 | 7739 | void bnx2x_disable_close_the_gate(struct bnx2x *bp) |
72fd0718 VZ |
7740 | { |
7741 | u32 val; | |
7742 | ||
7743 | DP(NETIF_MSG_HW, "Disabling \"close the gates\"\n"); | |
7744 | ||
7745 | if (CHIP_IS_E1(bp)) { | |
7746 | int port = BP_PORT(bp); | |
7747 | u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : | |
7748 | MISC_REG_AEU_MASK_ATTN_FUNC_0; | |
7749 | ||
7750 | val = REG_RD(bp, addr); | |
7751 | val &= ~(0x300); | |
7752 | REG_WR(bp, addr, val); | |
619c5cb6 | 7753 | } else { |
72fd0718 VZ |
7754 | val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK); |
7755 | val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK | | |
7756 | MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK); | |
7757 | REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val); | |
7758 | } | |
7759 | } | |
7760 | ||
72fd0718 VZ |
7761 | /* Close gates #2, #3 and #4: */ |
7762 | static void bnx2x_set_234_gates(struct bnx2x *bp, bool close) | |
7763 | { | |
c9ee9206 | 7764 | u32 val; |
72fd0718 VZ |
7765 | |
7766 | /* Gates #2 and #4a are closed/opened for "not E1" only */ | |
7767 | if (!CHIP_IS_E1(bp)) { | |
7768 | /* #4 */ | |
c9ee9206 | 7769 | REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close); |
72fd0718 | 7770 | /* #2 */ |
c9ee9206 | 7771 | REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close); |
72fd0718 VZ |
7772 | } |
7773 | ||
7774 | /* #3 */ | |
c9ee9206 VZ |
7775 | if (CHIP_IS_E1x(bp)) { |
7776 | /* Prevent interrupts from HC on both ports */ | |
7777 | val = REG_RD(bp, HC_REG_CONFIG_1); | |
7778 | REG_WR(bp, HC_REG_CONFIG_1, | |
7779 | (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) : | |
7780 | (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1)); | |
7781 | ||
7782 | val = REG_RD(bp, HC_REG_CONFIG_0); | |
7783 | REG_WR(bp, HC_REG_CONFIG_0, | |
7784 | (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) : | |
7785 | (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0)); | |
7786 | } else { | |
7787 | /* Prevent incomming interrupts in IGU */ | |
7788 | val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION); | |
7789 | ||
7790 | REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, | |
7791 | (!close) ? | |
7792 | (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) : | |
7793 | (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE)); | |
7794 | } | |
72fd0718 VZ |
7795 | |
7796 | DP(NETIF_MSG_HW, "%s gates #2, #3 and #4\n", | |
7797 | close ? "closing" : "opening"); | |
7798 | mmiowb(); | |
7799 | } | |
7800 | ||
7801 | #define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */ | |
7802 | ||
7803 | static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val) | |
7804 | { | |
7805 | /* Do some magic... */ | |
7806 | u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb); | |
7807 | *magic_val = val & SHARED_MF_CLP_MAGIC; | |
7808 | MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC); | |
7809 | } | |
7810 | ||
e8920674 DK |
7811 | /** |
7812 | * bnx2x_clp_reset_done - restore the value of the `magic' bit. | |
72fd0718 | 7813 | * |
e8920674 DK |
7814 | * @bp: driver handle |
7815 | * @magic_val: old value of the `magic' bit. | |
72fd0718 VZ |
7816 | */ |
7817 | static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val) | |
7818 | { | |
7819 | /* Restore the `magic' bit value... */ | |
72fd0718 VZ |
7820 | u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb); |
7821 | MF_CFG_WR(bp, shared_mf_config.clp_mb, | |
7822 | (val & (~SHARED_MF_CLP_MAGIC)) | magic_val); | |
7823 | } | |
7824 | ||
f85582f8 | 7825 | /** |
e8920674 | 7826 | * bnx2x_reset_mcp_prep - prepare for MCP reset. |
72fd0718 | 7827 | * |
e8920674 DK |
7828 | * @bp: driver handle |
7829 | * @magic_val: old value of 'magic' bit. | |
7830 | * | |
7831 | * Takes care of CLP configurations. | |
72fd0718 VZ |
7832 | */ |
7833 | static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val) | |
7834 | { | |
7835 | u32 shmem; | |
7836 | u32 validity_offset; | |
7837 | ||
7838 | DP(NETIF_MSG_HW, "Starting\n"); | |
7839 | ||
7840 | /* Set `magic' bit in order to save MF config */ | |
7841 | if (!CHIP_IS_E1(bp)) | |
7842 | bnx2x_clp_reset_prep(bp, magic_val); | |
7843 | ||
7844 | /* Get shmem offset */ | |
7845 | shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR); | |
7846 | validity_offset = offsetof(struct shmem_region, validity_map[0]); | |
7847 | ||
7848 | /* Clear validity map flags */ | |
7849 | if (shmem > 0) | |
7850 | REG_WR(bp, shmem + validity_offset, 0); | |
7851 | } | |
7852 | ||
7853 | #define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */ | |
7854 | #define MCP_ONE_TIMEOUT 100 /* 100 ms */ | |
7855 | ||
e8920674 DK |
7856 | /** |
7857 | * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT | |
72fd0718 | 7858 | * |
e8920674 | 7859 | * @bp: driver handle |
72fd0718 VZ |
7860 | */ |
7861 | static inline void bnx2x_mcp_wait_one(struct bnx2x *bp) | |
7862 | { | |
7863 | /* special handling for emulation and FPGA, | |
7864 | wait 10 times longer */ | |
7865 | if (CHIP_REV_IS_SLOW(bp)) | |
7866 | msleep(MCP_ONE_TIMEOUT*10); | |
7867 | else | |
7868 | msleep(MCP_ONE_TIMEOUT); | |
7869 | } | |
7870 | ||
1b6e2ceb DK |
7871 | /* |
7872 | * initializes bp->common.shmem_base and waits for validity signature to appear | |
7873 | */ | |
7874 | static int bnx2x_init_shmem(struct bnx2x *bp) | |
72fd0718 | 7875 | { |
1b6e2ceb DK |
7876 | int cnt = 0; |
7877 | u32 val = 0; | |
72fd0718 | 7878 | |
1b6e2ceb DK |
7879 | do { |
7880 | bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR); | |
7881 | if (bp->common.shmem_base) { | |
7882 | val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]); | |
7883 | if (val & SHR_MEM_VALIDITY_MB) | |
7884 | return 0; | |
7885 | } | |
72fd0718 | 7886 | |
1b6e2ceb | 7887 | bnx2x_mcp_wait_one(bp); |
72fd0718 | 7888 | |
1b6e2ceb | 7889 | } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT)); |
72fd0718 | 7890 | |
1b6e2ceb | 7891 | BNX2X_ERR("BAD MCP validity signature\n"); |
72fd0718 | 7892 | |
1b6e2ceb DK |
7893 | return -ENODEV; |
7894 | } | |
72fd0718 | 7895 | |
1b6e2ceb DK |
7896 | static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val) |
7897 | { | |
7898 | int rc = bnx2x_init_shmem(bp); | |
72fd0718 | 7899 | |
72fd0718 VZ |
7900 | /* Restore the `magic' bit value */ |
7901 | if (!CHIP_IS_E1(bp)) | |
7902 | bnx2x_clp_reset_done(bp, magic_val); | |
7903 | ||
7904 | return rc; | |
7905 | } | |
7906 | ||
7907 | static void bnx2x_pxp_prep(struct bnx2x *bp) | |
7908 | { | |
7909 | if (!CHIP_IS_E1(bp)) { | |
7910 | REG_WR(bp, PXP2_REG_RD_START_INIT, 0); | |
7911 | REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0); | |
72fd0718 VZ |
7912 | mmiowb(); |
7913 | } | |
7914 | } | |
7915 | ||
7916 | /* | |
7917 | * Reset the whole chip except for: | |
7918 | * - PCIE core | |
7919 | * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by | |
7920 | * one reset bit) | |
7921 | * - IGU | |
7922 | * - MISC (including AEU) | |
7923 | * - GRC | |
7924 | * - RBCN, RBCP | |
7925 | */ | |
c9ee9206 | 7926 | static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global) |
72fd0718 VZ |
7927 | { |
7928 | u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2; | |
c9ee9206 VZ |
7929 | u32 global_bits2; |
7930 | ||
7931 | /* | |
7932 | * Bits that have to be set in reset_mask2 if we want to reset 'global' | |
7933 | * (per chip) blocks. | |
7934 | */ | |
7935 | global_bits2 = | |
7936 | MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU | | |
7937 | MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE; | |
72fd0718 VZ |
7938 | |
7939 | not_reset_mask1 = | |
7940 | MISC_REGISTERS_RESET_REG_1_RST_HC | | |
7941 | MISC_REGISTERS_RESET_REG_1_RST_PXPV | | |
7942 | MISC_REGISTERS_RESET_REG_1_RST_PXP; | |
7943 | ||
7944 | not_reset_mask2 = | |
c9ee9206 | 7945 | MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO | |
72fd0718 VZ |
7946 | MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE | |
7947 | MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE | | |
7948 | MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE | | |
7949 | MISC_REGISTERS_RESET_REG_2_RST_RBCN | | |
7950 | MISC_REGISTERS_RESET_REG_2_RST_GRC | | |
7951 | MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE | | |
7952 | MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B; | |
7953 | ||
7954 | reset_mask1 = 0xffffffff; | |
7955 | ||
7956 | if (CHIP_IS_E1(bp)) | |
7957 | reset_mask2 = 0xffff; | |
7958 | else | |
7959 | reset_mask2 = 0x1ffff; | |
7960 | ||
c9ee9206 VZ |
7961 | if (CHIP_IS_E3(bp)) { |
7962 | reset_mask2 |= MISC_REGISTERS_RESET_REG_2_MSTAT0; | |
7963 | reset_mask2 |= MISC_REGISTERS_RESET_REG_2_MSTAT1; | |
7964 | } | |
7965 | ||
7966 | /* Don't reset global blocks unless we need to */ | |
7967 | if (!global) | |
7968 | reset_mask2 &= ~global_bits2; | |
7969 | ||
7970 | /* | |
7971 | * In case of attention in the QM, we need to reset PXP | |
7972 | * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM | |
7973 | * because otherwise QM reset would release 'close the gates' shortly | |
7974 | * before resetting the PXP, then the PSWRQ would send a write | |
7975 | * request to PGLUE. Then when PXP is reset, PGLUE would try to | |
7976 | * read the payload data from PSWWR, but PSWWR would not | |
7977 | * respond. The write queue in PGLUE would stuck, dmae commands | |
7978 | * would not return. Therefore it's important to reset the second | |
7979 | * reset register (containing the | |
7980 | * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the | |
7981 | * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM | |
7982 | * bit). | |
7983 | */ | |
72fd0718 VZ |
7984 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, |
7985 | reset_mask2 & (~not_reset_mask2)); | |
7986 | ||
c9ee9206 VZ |
7987 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, |
7988 | reset_mask1 & (~not_reset_mask1)); | |
7989 | ||
72fd0718 VZ |
7990 | barrier(); |
7991 | mmiowb(); | |
7992 | ||
72fd0718 | 7993 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, reset_mask2); |
c9ee9206 | 7994 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1); |
72fd0718 VZ |
7995 | mmiowb(); |
7996 | } | |
7997 | ||
c9ee9206 VZ |
7998 | /** |
7999 | * bnx2x_er_poll_igu_vq - poll for pending writes bit. | |
8000 | * It should get cleared in no more than 1s. | |
8001 | * | |
8002 | * @bp: driver handle | |
8003 | * | |
8004 | * It should get cleared in no more than 1s. Returns 0 if | |
8005 | * pending writes bit gets cleared. | |
8006 | */ | |
8007 | static int bnx2x_er_poll_igu_vq(struct bnx2x *bp) | |
8008 | { | |
8009 | u32 cnt = 1000; | |
8010 | u32 pend_bits = 0; | |
8011 | ||
8012 | do { | |
8013 | pend_bits = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS); | |
8014 | ||
8015 | if (pend_bits == 0) | |
8016 | break; | |
8017 | ||
8018 | usleep_range(1000, 1000); | |
8019 | } while (cnt-- > 0); | |
8020 | ||
8021 | if (cnt <= 0) { | |
8022 | BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n", | |
8023 | pend_bits); | |
8024 | return -EBUSY; | |
8025 | } | |
8026 | ||
8027 | return 0; | |
8028 | } | |
8029 | ||
8030 | static int bnx2x_process_kill(struct bnx2x *bp, bool global) | |
72fd0718 VZ |
8031 | { |
8032 | int cnt = 1000; | |
8033 | u32 val = 0; | |
8034 | u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2; | |
8035 | ||
8036 | ||
8037 | /* Empty the Tetris buffer, wait for 1s */ | |
8038 | do { | |
8039 | sr_cnt = REG_RD(bp, PXP2_REG_RD_SR_CNT); | |
8040 | blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT); | |
8041 | port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0); | |
8042 | port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1); | |
8043 | pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2); | |
8044 | if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) && | |
8045 | ((port_is_idle_0 & 0x1) == 0x1) && | |
8046 | ((port_is_idle_1 & 0x1) == 0x1) && | |
8047 | (pgl_exp_rom2 == 0xffffffff)) | |
8048 | break; | |
c9ee9206 | 8049 | usleep_range(1000, 1000); |
72fd0718 VZ |
8050 | } while (cnt-- > 0); |
8051 | ||
8052 | if (cnt <= 0) { | |
8053 | DP(NETIF_MSG_HW, "Tetris buffer didn't get empty or there" | |
8054 | " are still" | |
8055 | " outstanding read requests after 1s!\n"); | |
8056 | DP(NETIF_MSG_HW, "sr_cnt=0x%08x, blk_cnt=0x%08x," | |
8057 | " port_is_idle_0=0x%08x," | |
8058 | " port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n", | |
8059 | sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, | |
8060 | pgl_exp_rom2); | |
8061 | return -EAGAIN; | |
8062 | } | |
8063 | ||
8064 | barrier(); | |
8065 | ||
8066 | /* Close gates #2, #3 and #4 */ | |
8067 | bnx2x_set_234_gates(bp, true); | |
8068 | ||
c9ee9206 VZ |
8069 | /* Poll for IGU VQs for 57712 and newer chips */ |
8070 | if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp)) | |
8071 | return -EAGAIN; | |
8072 | ||
8073 | ||
72fd0718 VZ |
8074 | /* TBD: Indicate that "process kill" is in progress to MCP */ |
8075 | ||
8076 | /* Clear "unprepared" bit */ | |
8077 | REG_WR(bp, MISC_REG_UNPREPARED, 0); | |
8078 | barrier(); | |
8079 | ||
8080 | /* Make sure all is written to the chip before the reset */ | |
8081 | mmiowb(); | |
8082 | ||
8083 | /* Wait for 1ms to empty GLUE and PCI-E core queues, | |
8084 | * PSWHST, GRC and PSWRD Tetris buffer. | |
8085 | */ | |
c9ee9206 | 8086 | usleep_range(1000, 1000); |
72fd0718 VZ |
8087 | |
8088 | /* Prepare to chip reset: */ | |
8089 | /* MCP */ | |
c9ee9206 VZ |
8090 | if (global) |
8091 | bnx2x_reset_mcp_prep(bp, &val); | |
72fd0718 VZ |
8092 | |
8093 | /* PXP */ | |
8094 | bnx2x_pxp_prep(bp); | |
8095 | barrier(); | |
8096 | ||
8097 | /* reset the chip */ | |
c9ee9206 | 8098 | bnx2x_process_kill_chip_reset(bp, global); |
72fd0718 VZ |
8099 | barrier(); |
8100 | ||
8101 | /* Recover after reset: */ | |
8102 | /* MCP */ | |
c9ee9206 | 8103 | if (global && bnx2x_reset_mcp_comp(bp, val)) |
72fd0718 VZ |
8104 | return -EAGAIN; |
8105 | ||
c9ee9206 VZ |
8106 | /* TBD: Add resetting the NO_MCP mode DB here */ |
8107 | ||
72fd0718 VZ |
8108 | /* PXP */ |
8109 | bnx2x_pxp_prep(bp); | |
8110 | ||
8111 | /* Open the gates #2, #3 and #4 */ | |
8112 | bnx2x_set_234_gates(bp, false); | |
8113 | ||
8114 | /* TBD: IGU/AEU preparation bring back the AEU/IGU to a | |
8115 | * reset state, re-enable attentions. */ | |
8116 | ||
a2fbb9ea ET |
8117 | return 0; |
8118 | } | |
8119 | ||
c9ee9206 | 8120 | int bnx2x_leader_reset(struct bnx2x *bp) |
72fd0718 VZ |
8121 | { |
8122 | int rc = 0; | |
c9ee9206 VZ |
8123 | bool global = bnx2x_reset_is_global(bp); |
8124 | ||
72fd0718 | 8125 | /* Try to recover after the failure */ |
c9ee9206 VZ |
8126 | if (bnx2x_process_kill(bp, global)) { |
8127 | netdev_err(bp->dev, "Something bad had happen on engine %d! " | |
8128 | "Aii!\n", BP_PATH(bp)); | |
72fd0718 VZ |
8129 | rc = -EAGAIN; |
8130 | goto exit_leader_reset; | |
8131 | } | |
8132 | ||
c9ee9206 VZ |
8133 | /* |
8134 | * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver | |
8135 | * state. | |
8136 | */ | |
72fd0718 | 8137 | bnx2x_set_reset_done(bp); |
c9ee9206 VZ |
8138 | if (global) |
8139 | bnx2x_clear_reset_global(bp); | |
72fd0718 VZ |
8140 | |
8141 | exit_leader_reset: | |
8142 | bp->is_leader = 0; | |
c9ee9206 VZ |
8143 | bnx2x_release_leader_lock(bp); |
8144 | smp_mb(); | |
72fd0718 VZ |
8145 | return rc; |
8146 | } | |
8147 | ||
c9ee9206 VZ |
8148 | static inline void bnx2x_recovery_failed(struct bnx2x *bp) |
8149 | { | |
8150 | netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n"); | |
8151 | ||
8152 | /* Disconnect this device */ | |
8153 | netif_device_detach(bp->dev); | |
8154 | ||
8155 | /* | |
8156 | * Block ifup for all function on this engine until "process kill" | |
8157 | * or power cycle. | |
8158 | */ | |
8159 | bnx2x_set_reset_in_progress(bp); | |
8160 | ||
8161 | /* Shut down the power */ | |
8162 | bnx2x_set_power_state(bp, PCI_D3hot); | |
8163 | ||
8164 | bp->recovery_state = BNX2X_RECOVERY_FAILED; | |
8165 | ||
8166 | smp_mb(); | |
8167 | } | |
8168 | ||
8169 | /* | |
8170 | * Assumption: runs under rtnl lock. This together with the fact | |
6383c0b3 | 8171 | * that it's called only from bnx2x_sp_rtnl() ensure that it |
72fd0718 VZ |
8172 | * will never be called when netif_running(bp->dev) is false. |
8173 | */ | |
8174 | static void bnx2x_parity_recover(struct bnx2x *bp) | |
8175 | { | |
c9ee9206 VZ |
8176 | bool global = false; |
8177 | ||
72fd0718 VZ |
8178 | DP(NETIF_MSG_HW, "Handling parity\n"); |
8179 | while (1) { | |
8180 | switch (bp->recovery_state) { | |
8181 | case BNX2X_RECOVERY_INIT: | |
8182 | DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n"); | |
c9ee9206 VZ |
8183 | bnx2x_chk_parity_attn(bp, &global, false); |
8184 | ||
72fd0718 | 8185 | /* Try to get a LEADER_LOCK HW lock */ |
c9ee9206 VZ |
8186 | if (bnx2x_trylock_leader_lock(bp)) { |
8187 | bnx2x_set_reset_in_progress(bp); | |
8188 | /* | |
8189 | * Check if there is a global attention and if | |
8190 | * there was a global attention, set the global | |
8191 | * reset bit. | |
8192 | */ | |
8193 | ||
8194 | if (global) | |
8195 | bnx2x_set_reset_global(bp); | |
8196 | ||
72fd0718 | 8197 | bp->is_leader = 1; |
c9ee9206 | 8198 | } |
72fd0718 VZ |
8199 | |
8200 | /* Stop the driver */ | |
8201 | /* If interface has been removed - break */ | |
8202 | if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY)) | |
8203 | return; | |
8204 | ||
8205 | bp->recovery_state = BNX2X_RECOVERY_WAIT; | |
c9ee9206 VZ |
8206 | |
8207 | /* | |
8208 | * Reset MCP command sequence number and MCP mail box | |
8209 | * sequence as we are going to reset the MCP. | |
8210 | */ | |
8211 | if (global) { | |
8212 | bp->fw_seq = 0; | |
8213 | bp->fw_drv_pulse_wr_seq = 0; | |
8214 | } | |
8215 | ||
8216 | /* Ensure "is_leader", MCP command sequence and | |
8217 | * "recovery_state" update values are seen on other | |
8218 | * CPUs. | |
72fd0718 | 8219 | */ |
c9ee9206 | 8220 | smp_mb(); |
72fd0718 VZ |
8221 | break; |
8222 | ||
8223 | case BNX2X_RECOVERY_WAIT: | |
8224 | DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n"); | |
8225 | if (bp->is_leader) { | |
c9ee9206 VZ |
8226 | int other_engine = BP_PATH(bp) ? 0 : 1; |
8227 | u32 other_load_counter = | |
8228 | bnx2x_get_load_cnt(bp, other_engine); | |
8229 | u32 load_counter = | |
8230 | bnx2x_get_load_cnt(bp, BP_PATH(bp)); | |
8231 | global = bnx2x_reset_is_global(bp); | |
8232 | ||
8233 | /* | |
8234 | * In case of a parity in a global block, let | |
8235 | * the first leader that performs a | |
8236 | * leader_reset() reset the global blocks in | |
8237 | * order to clear global attentions. Otherwise | |
8238 | * the the gates will remain closed for that | |
8239 | * engine. | |
8240 | */ | |
8241 | if (load_counter || | |
8242 | (global && other_load_counter)) { | |
72fd0718 VZ |
8243 | /* Wait until all other functions get |
8244 | * down. | |
8245 | */ | |
7be08a72 | 8246 | schedule_delayed_work(&bp->sp_rtnl_task, |
72fd0718 VZ |
8247 | HZ/10); |
8248 | return; | |
8249 | } else { | |
8250 | /* If all other functions got down - | |
8251 | * try to bring the chip back to | |
8252 | * normal. In any case it's an exit | |
8253 | * point for a leader. | |
8254 | */ | |
c9ee9206 VZ |
8255 | if (bnx2x_leader_reset(bp)) { |
8256 | bnx2x_recovery_failed(bp); | |
72fd0718 VZ |
8257 | return; |
8258 | } | |
8259 | ||
c9ee9206 VZ |
8260 | /* If we are here, means that the |
8261 | * leader has succeeded and doesn't | |
8262 | * want to be a leader any more. Try | |
8263 | * to continue as a none-leader. | |
8264 | */ | |
8265 | break; | |
72fd0718 VZ |
8266 | } |
8267 | } else { /* non-leader */ | |
c9ee9206 | 8268 | if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) { |
72fd0718 VZ |
8269 | /* Try to get a LEADER_LOCK HW lock as |
8270 | * long as a former leader may have | |
8271 | * been unloaded by the user or | |
8272 | * released a leadership by another | |
8273 | * reason. | |
8274 | */ | |
c9ee9206 | 8275 | if (bnx2x_trylock_leader_lock(bp)) { |
72fd0718 VZ |
8276 | /* I'm a leader now! Restart a |
8277 | * switch case. | |
8278 | */ | |
8279 | bp->is_leader = 1; | |
8280 | break; | |
8281 | } | |
8282 | ||
7be08a72 | 8283 | schedule_delayed_work(&bp->sp_rtnl_task, |
72fd0718 VZ |
8284 | HZ/10); |
8285 | return; | |
8286 | ||
c9ee9206 VZ |
8287 | } else { |
8288 | /* | |
8289 | * If there was a global attention, wait | |
8290 | * for it to be cleared. | |
8291 | */ | |
8292 | if (bnx2x_reset_is_global(bp)) { | |
8293 | schedule_delayed_work( | |
7be08a72 AE |
8294 | &bp->sp_rtnl_task, |
8295 | HZ/10); | |
c9ee9206 VZ |
8296 | return; |
8297 | } | |
8298 | ||
8299 | if (bnx2x_nic_load(bp, LOAD_NORMAL)) | |
8300 | bnx2x_recovery_failed(bp); | |
8301 | else { | |
8302 | bp->recovery_state = | |
8303 | BNX2X_RECOVERY_DONE; | |
8304 | smp_mb(); | |
8305 | } | |
8306 | ||
72fd0718 VZ |
8307 | return; |
8308 | } | |
8309 | } | |
8310 | default: | |
8311 | return; | |
8312 | } | |
8313 | } | |
8314 | } | |
8315 | ||
8316 | /* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is | |
8317 | * scheduled on a general queue in order to prevent a dead lock. | |
8318 | */ | |
7be08a72 | 8319 | static void bnx2x_sp_rtnl_task(struct work_struct *work) |
34f80b04 | 8320 | { |
7be08a72 | 8321 | struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work); |
34f80b04 EG |
8322 | |
8323 | rtnl_lock(); | |
8324 | ||
8325 | if (!netif_running(bp->dev)) | |
7be08a72 AE |
8326 | goto sp_rtnl_exit; |
8327 | ||
6383c0b3 AE |
8328 | if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state)) |
8329 | bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos); | |
8330 | ||
7be08a72 AE |
8331 | /* if stop on error is defined no recovery flows should be executed */ |
8332 | #ifdef BNX2X_STOP_ON_ERROR | |
8333 | BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined " | |
8334 | "so reset not done to allow debug dump,\n" | |
8335 | "you will need to reboot when done\n"); | |
8336 | goto sp_rtnl_exit; | |
8337 | #endif | |
34f80b04 | 8338 | |
7be08a72 AE |
8339 | if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) { |
8340 | /* | |
8341 | * Clear TX_TIMEOUT bit as we are going to reset the function | |
8342 | * anyway. | |
8343 | */ | |
8344 | smp_mb__before_clear_bit(); | |
8345 | clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state); | |
8346 | smp_mb__after_clear_bit(); | |
72fd0718 | 8347 | bnx2x_parity_recover(bp); |
7be08a72 AE |
8348 | } else if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, |
8349 | &bp->sp_rtnl_state)){ | |
72fd0718 VZ |
8350 | bnx2x_nic_unload(bp, UNLOAD_NORMAL); |
8351 | bnx2x_nic_load(bp, LOAD_NORMAL); | |
8352 | } | |
34f80b04 | 8353 | |
7be08a72 | 8354 | sp_rtnl_exit: |
34f80b04 EG |
8355 | rtnl_unlock(); |
8356 | } | |
8357 | ||
a2fbb9ea ET |
8358 | /* end of nic load/unload */ |
8359 | ||
3deb8167 YR |
8360 | static void bnx2x_period_task(struct work_struct *work) |
8361 | { | |
8362 | struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work); | |
8363 | ||
8364 | if (!netif_running(bp->dev)) | |
8365 | goto period_task_exit; | |
8366 | ||
8367 | if (CHIP_REV_IS_SLOW(bp)) { | |
8368 | BNX2X_ERR("period task called on emulation, ignoring\n"); | |
8369 | goto period_task_exit; | |
8370 | } | |
8371 | ||
8372 | bnx2x_acquire_phy_lock(bp); | |
8373 | /* | |
8374 | * The barrier is needed to ensure the ordering between the writing to | |
8375 | * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and | |
8376 | * the reading here. | |
8377 | */ | |
8378 | smp_mb(); | |
8379 | if (bp->port.pmf) { | |
8380 | bnx2x_period_func(&bp->link_params, &bp->link_vars); | |
8381 | ||
8382 | /* Re-queue task in 1 sec */ | |
8383 | queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ); | |
8384 | } | |
8385 | ||
8386 | bnx2x_release_phy_lock(bp); | |
8387 | period_task_exit: | |
8388 | return; | |
8389 | } | |
8390 | ||
a2fbb9ea ET |
8391 | /* |
8392 | * Init service functions | |
8393 | */ | |
8394 | ||
8d96286a | 8395 | static u32 bnx2x_get_pretend_reg(struct bnx2x *bp) |
f2e0899f DK |
8396 | { |
8397 | u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0; | |
8398 | u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base; | |
8399 | return base + (BP_ABS_FUNC(bp)) * stride; | |
f1ef27ef EG |
8400 | } |
8401 | ||
f2e0899f | 8402 | static void bnx2x_undi_int_disable_e1h(struct bnx2x *bp) |
f1ef27ef | 8403 | { |
f2e0899f | 8404 | u32 reg = bnx2x_get_pretend_reg(bp); |
f1ef27ef EG |
8405 | |
8406 | /* Flush all outstanding writes */ | |
8407 | mmiowb(); | |
8408 | ||
8409 | /* Pretend to be function 0 */ | |
8410 | REG_WR(bp, reg, 0); | |
f2e0899f | 8411 | REG_RD(bp, reg); /* Flush the GRC transaction (in the chip) */ |
f1ef27ef EG |
8412 | |
8413 | /* From now we are in the "like-E1" mode */ | |
8414 | bnx2x_int_disable(bp); | |
8415 | ||
8416 | /* Flush all outstanding writes */ | |
8417 | mmiowb(); | |
8418 | ||
f2e0899f DK |
8419 | /* Restore the original function */ |
8420 | REG_WR(bp, reg, BP_ABS_FUNC(bp)); | |
8421 | REG_RD(bp, reg); | |
f1ef27ef EG |
8422 | } |
8423 | ||
f2e0899f | 8424 | static inline void bnx2x_undi_int_disable(struct bnx2x *bp) |
f1ef27ef | 8425 | { |
f2e0899f | 8426 | if (CHIP_IS_E1(bp)) |
f1ef27ef | 8427 | bnx2x_int_disable(bp); |
f2e0899f DK |
8428 | else |
8429 | bnx2x_undi_int_disable_e1h(bp); | |
f1ef27ef EG |
8430 | } |
8431 | ||
34f80b04 EG |
8432 | static void __devinit bnx2x_undi_unload(struct bnx2x *bp) |
8433 | { | |
8434 | u32 val; | |
8435 | ||
8436 | /* Check if there is any driver already loaded */ | |
8437 | val = REG_RD(bp, MISC_REG_UNPREPARED); | |
8438 | if (val == 0x1) { | |
8439 | /* Check if it is the UNDI driver | |
8440 | * UNDI driver initializes CID offset for normal bell to 0x7 | |
8441 | */ | |
4a37fb66 | 8442 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_UNDI); |
34f80b04 EG |
8443 | val = REG_RD(bp, DORQ_REG_NORM_CID_OFST); |
8444 | if (val == 0x7) { | |
8445 | u32 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; | |
f2e0899f DK |
8446 | /* save our pf_num */ |
8447 | int orig_pf_num = bp->pf_num; | |
619c5cb6 VZ |
8448 | int port; |
8449 | u32 swap_en, swap_val, value; | |
34f80b04 | 8450 | |
b4661739 EG |
8451 | /* clear the UNDI indication */ |
8452 | REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0); | |
8453 | ||
34f80b04 EG |
8454 | BNX2X_DEV_INFO("UNDI is active! reset device\n"); |
8455 | ||
8456 | /* try unload UNDI on port 0 */ | |
f2e0899f | 8457 | bp->pf_num = 0; |
da5a662a | 8458 | bp->fw_seq = |
f2e0899f | 8459 | (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) & |
da5a662a | 8460 | DRV_MSG_SEQ_NUMBER_MASK); |
a22f0788 | 8461 | reset_code = bnx2x_fw_command(bp, reset_code, 0); |
34f80b04 EG |
8462 | |
8463 | /* if UNDI is loaded on the other port */ | |
8464 | if (reset_code != FW_MSG_CODE_DRV_UNLOAD_COMMON) { | |
8465 | ||
da5a662a | 8466 | /* send "DONE" for previous unload */ |
a22f0788 YR |
8467 | bnx2x_fw_command(bp, |
8468 | DRV_MSG_CODE_UNLOAD_DONE, 0); | |
da5a662a VZ |
8469 | |
8470 | /* unload UNDI on port 1 */ | |
f2e0899f | 8471 | bp->pf_num = 1; |
da5a662a | 8472 | bp->fw_seq = |
f2e0899f | 8473 | (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) & |
da5a662a VZ |
8474 | DRV_MSG_SEQ_NUMBER_MASK); |
8475 | reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; | |
8476 | ||
a22f0788 | 8477 | bnx2x_fw_command(bp, reset_code, 0); |
34f80b04 EG |
8478 | } |
8479 | ||
b4661739 EG |
8480 | /* now it's safe to release the lock */ |
8481 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_UNDI); | |
8482 | ||
f2e0899f | 8483 | bnx2x_undi_int_disable(bp); |
619c5cb6 | 8484 | port = BP_PORT(bp); |
da5a662a VZ |
8485 | |
8486 | /* close input traffic and wait for it */ | |
8487 | /* Do not rcv packets to BRB */ | |
619c5cb6 VZ |
8488 | REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_DRV_MASK : |
8489 | NIG_REG_LLH0_BRB1_DRV_MASK), 0x0); | |
da5a662a VZ |
8490 | /* Do not direct rcv packets that are not for MCP to |
8491 | * the BRB */ | |
619c5cb6 VZ |
8492 | REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP : |
8493 | NIG_REG_LLH0_BRB1_NOT_MCP), 0x0); | |
da5a662a | 8494 | /* clear AEU */ |
619c5cb6 VZ |
8495 | REG_WR(bp, (port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : |
8496 | MISC_REG_AEU_MASK_ATTN_FUNC_0), 0); | |
da5a662a VZ |
8497 | msleep(10); |
8498 | ||
8499 | /* save NIG port swap info */ | |
8500 | swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); | |
8501 | swap_en = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); | |
34f80b04 EG |
8502 | /* reset device */ |
8503 | REG_WR(bp, | |
8504 | GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, | |
da5a662a | 8505 | 0xd3ffffff); |
619c5cb6 VZ |
8506 | |
8507 | value = 0x1400; | |
8508 | if (CHIP_IS_E3(bp)) { | |
8509 | value |= MISC_REGISTERS_RESET_REG_2_MSTAT0; | |
8510 | value |= MISC_REGISTERS_RESET_REG_2_MSTAT1; | |
8511 | } | |
8512 | ||
34f80b04 EG |
8513 | REG_WR(bp, |
8514 | GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, | |
619c5cb6 VZ |
8515 | value); |
8516 | ||
da5a662a VZ |
8517 | /* take the NIG out of reset and restore swap values */ |
8518 | REG_WR(bp, | |
8519 | GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, | |
8520 | MISC_REGISTERS_RESET_REG_1_RST_NIG); | |
8521 | REG_WR(bp, NIG_REG_PORT_SWAP, swap_val); | |
8522 | REG_WR(bp, NIG_REG_STRAP_OVERRIDE, swap_en); | |
8523 | ||
8524 | /* send unload done to the MCP */ | |
a22f0788 | 8525 | bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0); |
da5a662a VZ |
8526 | |
8527 | /* restore our func and fw_seq */ | |
f2e0899f | 8528 | bp->pf_num = orig_pf_num; |
da5a662a | 8529 | bp->fw_seq = |
f2e0899f | 8530 | (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) & |
da5a662a | 8531 | DRV_MSG_SEQ_NUMBER_MASK); |
b4661739 EG |
8532 | } else |
8533 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_UNDI); | |
34f80b04 EG |
8534 | } |
8535 | } | |
8536 | ||
8537 | static void __devinit bnx2x_get_common_hwinfo(struct bnx2x *bp) | |
8538 | { | |
8539 | u32 val, val2, val3, val4, id; | |
72ce58c3 | 8540 | u16 pmc; |
34f80b04 EG |
8541 | |
8542 | /* Get the chip revision id and number. */ | |
8543 | /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */ | |
8544 | val = REG_RD(bp, MISC_REG_CHIP_NUM); | |
8545 | id = ((val & 0xffff) << 16); | |
8546 | val = REG_RD(bp, MISC_REG_CHIP_REV); | |
8547 | id |= ((val & 0xf) << 12); | |
8548 | val = REG_RD(bp, MISC_REG_CHIP_METAL); | |
8549 | id |= ((val & 0xff) << 4); | |
5a40e08e | 8550 | val = REG_RD(bp, MISC_REG_BOND_ID); |
34f80b04 EG |
8551 | id |= (val & 0xf); |
8552 | bp->common.chip_id = id; | |
523224a3 DK |
8553 | |
8554 | /* Set doorbell size */ | |
8555 | bp->db_size = (1 << BNX2X_DB_SHIFT); | |
8556 | ||
619c5cb6 | 8557 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
8558 | val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR); |
8559 | if ((val & 1) == 0) | |
8560 | val = REG_RD(bp, MISC_REG_PORT4MODE_EN); | |
8561 | else | |
8562 | val = (val >> 1) & 1; | |
8563 | BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" : | |
8564 | "2_PORT_MODE"); | |
8565 | bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE : | |
8566 | CHIP_2_PORT_MODE; | |
8567 | ||
8568 | if (CHIP_MODE_IS_4_PORT(bp)) | |
8569 | bp->pfid = (bp->pf_num >> 1); /* 0..3 */ | |
8570 | else | |
8571 | bp->pfid = (bp->pf_num & 0x6); /* 0, 2, 4, 6 */ | |
8572 | } else { | |
8573 | bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */ | |
8574 | bp->pfid = bp->pf_num; /* 0..7 */ | |
8575 | } | |
8576 | ||
f2e0899f DK |
8577 | bp->link_params.chip_id = bp->common.chip_id; |
8578 | BNX2X_DEV_INFO("chip ID is 0x%x\n", id); | |
523224a3 | 8579 | |
1c06328c EG |
8580 | val = (REG_RD(bp, 0x2874) & 0x55); |
8581 | if ((bp->common.chip_id & 0x1) || | |
8582 | (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) { | |
8583 | bp->flags |= ONE_PORT_FLAG; | |
8584 | BNX2X_DEV_INFO("single port device\n"); | |
8585 | } | |
8586 | ||
34f80b04 | 8587 | val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4); |
754a2f52 | 8588 | bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE << |
34f80b04 EG |
8589 | (val & MCPR_NVM_CFG4_FLASH_SIZE)); |
8590 | BNX2X_DEV_INFO("flash_size 0x%x (%d)\n", | |
8591 | bp->common.flash_size, bp->common.flash_size); | |
8592 | ||
1b6e2ceb DK |
8593 | bnx2x_init_shmem(bp); |
8594 | ||
619c5cb6 VZ |
8595 | |
8596 | ||
f2e0899f DK |
8597 | bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ? |
8598 | MISC_REG_GENERIC_CR_1 : | |
8599 | MISC_REG_GENERIC_CR_0)); | |
1b6e2ceb | 8600 | |
34f80b04 | 8601 | bp->link_params.shmem_base = bp->common.shmem_base; |
a22f0788 | 8602 | bp->link_params.shmem2_base = bp->common.shmem2_base; |
2691d51d EG |
8603 | BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n", |
8604 | bp->common.shmem_base, bp->common.shmem2_base); | |
34f80b04 | 8605 | |
f2e0899f | 8606 | if (!bp->common.shmem_base) { |
34f80b04 EG |
8607 | BNX2X_DEV_INFO("MCP not active\n"); |
8608 | bp->flags |= NO_MCP_FLAG; | |
8609 | return; | |
8610 | } | |
8611 | ||
34f80b04 | 8612 | bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config); |
35b19ba5 | 8613 | BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config); |
34f80b04 EG |
8614 | |
8615 | bp->link_params.hw_led_mode = ((bp->common.hw_config & | |
8616 | SHARED_HW_CFG_LED_MODE_MASK) >> | |
8617 | SHARED_HW_CFG_LED_MODE_SHIFT); | |
8618 | ||
c2c8b03e EG |
8619 | bp->link_params.feature_config_flags = 0; |
8620 | val = SHMEM_RD(bp, dev_info.shared_feature_config.config); | |
8621 | if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED) | |
8622 | bp->link_params.feature_config_flags |= | |
8623 | FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED; | |
8624 | else | |
8625 | bp->link_params.feature_config_flags &= | |
8626 | ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED; | |
8627 | ||
34f80b04 EG |
8628 | val = SHMEM_RD(bp, dev_info.bc_rev) >> 8; |
8629 | bp->common.bc_ver = val; | |
8630 | BNX2X_DEV_INFO("bc_ver %X\n", val); | |
8631 | if (val < BNX2X_BC_VER) { | |
8632 | /* for now only warn | |
8633 | * later we might need to enforce this */ | |
f2e0899f DK |
8634 | BNX2X_ERR("This driver needs bc_ver %X but found %X, " |
8635 | "please upgrade BC\n", BNX2X_BC_VER, val); | |
34f80b04 | 8636 | } |
4d295db0 | 8637 | bp->link_params.feature_config_flags |= |
a22f0788 | 8638 | (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ? |
f85582f8 DK |
8639 | FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0; |
8640 | ||
a22f0788 YR |
8641 | bp->link_params.feature_config_flags |= |
8642 | (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ? | |
8643 | FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0; | |
72ce58c3 | 8644 | |
85242eea YR |
8645 | bp->link_params.feature_config_flags |= |
8646 | (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ? | |
8647 | FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0; | |
8648 | ||
f9a3ebbe DK |
8649 | pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_PMC, &pmc); |
8650 | bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG; | |
8651 | ||
72ce58c3 | 8652 | BNX2X_DEV_INFO("%sWoL capable\n", |
f5372251 | 8653 | (bp->flags & NO_WOL_FLAG) ? "not " : ""); |
34f80b04 EG |
8654 | |
8655 | val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num); | |
8656 | val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]); | |
8657 | val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]); | |
8658 | val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]); | |
8659 | ||
cdaa7cb8 VZ |
8660 | dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n", |
8661 | val, val2, val3, val4); | |
34f80b04 EG |
8662 | } |
8663 | ||
f2e0899f DK |
8664 | #define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID) |
8665 | #define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR) | |
8666 | ||
8667 | static void __devinit bnx2x_get_igu_cam_info(struct bnx2x *bp) | |
8668 | { | |
8669 | int pfid = BP_FUNC(bp); | |
8670 | int vn = BP_E1HVN(bp); | |
8671 | int igu_sb_id; | |
8672 | u32 val; | |
6383c0b3 | 8673 | u8 fid, igu_sb_cnt = 0; |
f2e0899f DK |
8674 | |
8675 | bp->igu_base_sb = 0xff; | |
f2e0899f | 8676 | if (CHIP_INT_MODE_IS_BC(bp)) { |
6383c0b3 | 8677 | igu_sb_cnt = bp->igu_sb_cnt; |
f2e0899f DK |
8678 | bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) * |
8679 | FP_SB_MAX_E1x; | |
8680 | ||
8681 | bp->igu_dsb_id = E1HVN_MAX * FP_SB_MAX_E1x + | |
8682 | (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn); | |
8683 | ||
8684 | return; | |
8685 | } | |
8686 | ||
8687 | /* IGU in normal mode - read CAM */ | |
8688 | for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE; | |
8689 | igu_sb_id++) { | |
8690 | val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4); | |
8691 | if (!(val & IGU_REG_MAPPING_MEMORY_VALID)) | |
8692 | continue; | |
8693 | fid = IGU_FID(val); | |
8694 | if ((fid & IGU_FID_ENCODE_IS_PF)) { | |
8695 | if ((fid & IGU_FID_PF_NUM_MASK) != pfid) | |
8696 | continue; | |
8697 | if (IGU_VEC(val) == 0) | |
8698 | /* default status block */ | |
8699 | bp->igu_dsb_id = igu_sb_id; | |
8700 | else { | |
8701 | if (bp->igu_base_sb == 0xff) | |
8702 | bp->igu_base_sb = igu_sb_id; | |
6383c0b3 | 8703 | igu_sb_cnt++; |
f2e0899f DK |
8704 | } |
8705 | } | |
8706 | } | |
619c5cb6 | 8707 | |
6383c0b3 AE |
8708 | #ifdef CONFIG_PCI_MSI |
8709 | /* | |
8710 | * It's expected that number of CAM entries for this functions is equal | |
8711 | * to the number evaluated based on the MSI-X table size. We want a | |
8712 | * harsh warning if these values are different! | |
619c5cb6 | 8713 | */ |
6383c0b3 AE |
8714 | WARN_ON(bp->igu_sb_cnt != igu_sb_cnt); |
8715 | #endif | |
619c5cb6 | 8716 | |
6383c0b3 | 8717 | if (igu_sb_cnt == 0) |
f2e0899f DK |
8718 | BNX2X_ERR("CAM configuration error\n"); |
8719 | } | |
8720 | ||
34f80b04 EG |
8721 | static void __devinit bnx2x_link_settings_supported(struct bnx2x *bp, |
8722 | u32 switch_cfg) | |
a2fbb9ea | 8723 | { |
a22f0788 YR |
8724 | int cfg_size = 0, idx, port = BP_PORT(bp); |
8725 | ||
8726 | /* Aggregation of supported attributes of all external phys */ | |
8727 | bp->port.supported[0] = 0; | |
8728 | bp->port.supported[1] = 0; | |
b7737c9b YR |
8729 | switch (bp->link_params.num_phys) { |
8730 | case 1: | |
a22f0788 YR |
8731 | bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported; |
8732 | cfg_size = 1; | |
8733 | break; | |
b7737c9b | 8734 | case 2: |
a22f0788 YR |
8735 | bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported; |
8736 | cfg_size = 1; | |
8737 | break; | |
8738 | case 3: | |
8739 | if (bp->link_params.multi_phy_config & | |
8740 | PORT_HW_CFG_PHY_SWAPPED_ENABLED) { | |
8741 | bp->port.supported[1] = | |
8742 | bp->link_params.phy[EXT_PHY1].supported; | |
8743 | bp->port.supported[0] = | |
8744 | bp->link_params.phy[EXT_PHY2].supported; | |
8745 | } else { | |
8746 | bp->port.supported[0] = | |
8747 | bp->link_params.phy[EXT_PHY1].supported; | |
8748 | bp->port.supported[1] = | |
8749 | bp->link_params.phy[EXT_PHY2].supported; | |
8750 | } | |
8751 | cfg_size = 2; | |
8752 | break; | |
b7737c9b | 8753 | } |
a2fbb9ea | 8754 | |
a22f0788 | 8755 | if (!(bp->port.supported[0] || bp->port.supported[1])) { |
b7737c9b | 8756 | BNX2X_ERR("NVRAM config error. BAD phy config." |
a22f0788 | 8757 | "PHY1 config 0x%x, PHY2 config 0x%x\n", |
b7737c9b | 8758 | SHMEM_RD(bp, |
a22f0788 YR |
8759 | dev_info.port_hw_config[port].external_phy_config), |
8760 | SHMEM_RD(bp, | |
8761 | dev_info.port_hw_config[port].external_phy_config2)); | |
a2fbb9ea | 8762 | return; |
f85582f8 | 8763 | } |
a2fbb9ea | 8764 | |
619c5cb6 VZ |
8765 | if (CHIP_IS_E3(bp)) |
8766 | bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR); | |
8767 | else { | |
8768 | switch (switch_cfg) { | |
8769 | case SWITCH_CFG_1G: | |
8770 | bp->port.phy_addr = REG_RD( | |
8771 | bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10); | |
8772 | break; | |
8773 | case SWITCH_CFG_10G: | |
8774 | bp->port.phy_addr = REG_RD( | |
8775 | bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18); | |
8776 | break; | |
8777 | default: | |
8778 | BNX2X_ERR("BAD switch_cfg link_config 0x%x\n", | |
8779 | bp->port.link_config[0]); | |
8780 | return; | |
8781 | } | |
a2fbb9ea | 8782 | } |
619c5cb6 | 8783 | BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr); |
a22f0788 YR |
8784 | /* mask what we support according to speed_cap_mask per configuration */ |
8785 | for (idx = 0; idx < cfg_size; idx++) { | |
8786 | if (!(bp->link_params.speed_cap_mask[idx] & | |
c18487ee | 8787 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) |
a22f0788 | 8788 | bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half; |
a2fbb9ea | 8789 | |
a22f0788 | 8790 | if (!(bp->link_params.speed_cap_mask[idx] & |
c18487ee | 8791 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL)) |
a22f0788 | 8792 | bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full; |
a2fbb9ea | 8793 | |
a22f0788 | 8794 | if (!(bp->link_params.speed_cap_mask[idx] & |
c18487ee | 8795 | PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)) |
a22f0788 | 8796 | bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half; |
a2fbb9ea | 8797 | |
a22f0788 | 8798 | if (!(bp->link_params.speed_cap_mask[idx] & |
c18487ee | 8799 | PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL)) |
a22f0788 | 8800 | bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full; |
a2fbb9ea | 8801 | |
a22f0788 | 8802 | if (!(bp->link_params.speed_cap_mask[idx] & |
c18487ee | 8803 | PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) |
a22f0788 | 8804 | bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half | |
f85582f8 | 8805 | SUPPORTED_1000baseT_Full); |
a2fbb9ea | 8806 | |
a22f0788 | 8807 | if (!(bp->link_params.speed_cap_mask[idx] & |
c18487ee | 8808 | PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)) |
a22f0788 | 8809 | bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full; |
a2fbb9ea | 8810 | |
a22f0788 | 8811 | if (!(bp->link_params.speed_cap_mask[idx] & |
c18487ee | 8812 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) |
a22f0788 YR |
8813 | bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full; |
8814 | ||
8815 | } | |
a2fbb9ea | 8816 | |
a22f0788 YR |
8817 | BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0], |
8818 | bp->port.supported[1]); | |
a2fbb9ea ET |
8819 | } |
8820 | ||
34f80b04 | 8821 | static void __devinit bnx2x_link_settings_requested(struct bnx2x *bp) |
a2fbb9ea | 8822 | { |
a22f0788 YR |
8823 | u32 link_config, idx, cfg_size = 0; |
8824 | bp->port.advertising[0] = 0; | |
8825 | bp->port.advertising[1] = 0; | |
8826 | switch (bp->link_params.num_phys) { | |
8827 | case 1: | |
8828 | case 2: | |
8829 | cfg_size = 1; | |
8830 | break; | |
8831 | case 3: | |
8832 | cfg_size = 2; | |
8833 | break; | |
8834 | } | |
8835 | for (idx = 0; idx < cfg_size; idx++) { | |
8836 | bp->link_params.req_duplex[idx] = DUPLEX_FULL; | |
8837 | link_config = bp->port.link_config[idx]; | |
8838 | switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) { | |
f85582f8 | 8839 | case PORT_FEATURE_LINK_SPEED_AUTO: |
a22f0788 YR |
8840 | if (bp->port.supported[idx] & SUPPORTED_Autoneg) { |
8841 | bp->link_params.req_line_speed[idx] = | |
8842 | SPEED_AUTO_NEG; | |
8843 | bp->port.advertising[idx] |= | |
8844 | bp->port.supported[idx]; | |
f85582f8 DK |
8845 | } else { |
8846 | /* force 10G, no AN */ | |
a22f0788 YR |
8847 | bp->link_params.req_line_speed[idx] = |
8848 | SPEED_10000; | |
8849 | bp->port.advertising[idx] |= | |
8850 | (ADVERTISED_10000baseT_Full | | |
f85582f8 | 8851 | ADVERTISED_FIBRE); |
a22f0788 | 8852 | continue; |
f85582f8 DK |
8853 | } |
8854 | break; | |
a2fbb9ea | 8855 | |
f85582f8 | 8856 | case PORT_FEATURE_LINK_SPEED_10M_FULL: |
a22f0788 YR |
8857 | if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) { |
8858 | bp->link_params.req_line_speed[idx] = | |
8859 | SPEED_10; | |
8860 | bp->port.advertising[idx] |= | |
8861 | (ADVERTISED_10baseT_Full | | |
f85582f8 DK |
8862 | ADVERTISED_TP); |
8863 | } else { | |
754a2f52 | 8864 | BNX2X_ERR("NVRAM config error. " |
f85582f8 DK |
8865 | "Invalid link_config 0x%x" |
8866 | " speed_cap_mask 0x%x\n", | |
8867 | link_config, | |
a22f0788 | 8868 | bp->link_params.speed_cap_mask[idx]); |
f85582f8 DK |
8869 | return; |
8870 | } | |
8871 | break; | |
a2fbb9ea | 8872 | |
f85582f8 | 8873 | case PORT_FEATURE_LINK_SPEED_10M_HALF: |
a22f0788 YR |
8874 | if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) { |
8875 | bp->link_params.req_line_speed[idx] = | |
8876 | SPEED_10; | |
8877 | bp->link_params.req_duplex[idx] = | |
8878 | DUPLEX_HALF; | |
8879 | bp->port.advertising[idx] |= | |
8880 | (ADVERTISED_10baseT_Half | | |
f85582f8 DK |
8881 | ADVERTISED_TP); |
8882 | } else { | |
754a2f52 | 8883 | BNX2X_ERR("NVRAM config error. " |
f85582f8 DK |
8884 | "Invalid link_config 0x%x" |
8885 | " speed_cap_mask 0x%x\n", | |
8886 | link_config, | |
8887 | bp->link_params.speed_cap_mask[idx]); | |
8888 | return; | |
8889 | } | |
8890 | break; | |
a2fbb9ea | 8891 | |
f85582f8 DK |
8892 | case PORT_FEATURE_LINK_SPEED_100M_FULL: |
8893 | if (bp->port.supported[idx] & | |
8894 | SUPPORTED_100baseT_Full) { | |
a22f0788 YR |
8895 | bp->link_params.req_line_speed[idx] = |
8896 | SPEED_100; | |
8897 | bp->port.advertising[idx] |= | |
8898 | (ADVERTISED_100baseT_Full | | |
f85582f8 DK |
8899 | ADVERTISED_TP); |
8900 | } else { | |
754a2f52 | 8901 | BNX2X_ERR("NVRAM config error. " |
f85582f8 DK |
8902 | "Invalid link_config 0x%x" |
8903 | " speed_cap_mask 0x%x\n", | |
8904 | link_config, | |
8905 | bp->link_params.speed_cap_mask[idx]); | |
8906 | return; | |
8907 | } | |
8908 | break; | |
a2fbb9ea | 8909 | |
f85582f8 DK |
8910 | case PORT_FEATURE_LINK_SPEED_100M_HALF: |
8911 | if (bp->port.supported[idx] & | |
8912 | SUPPORTED_100baseT_Half) { | |
8913 | bp->link_params.req_line_speed[idx] = | |
8914 | SPEED_100; | |
8915 | bp->link_params.req_duplex[idx] = | |
8916 | DUPLEX_HALF; | |
a22f0788 YR |
8917 | bp->port.advertising[idx] |= |
8918 | (ADVERTISED_100baseT_Half | | |
f85582f8 DK |
8919 | ADVERTISED_TP); |
8920 | } else { | |
754a2f52 | 8921 | BNX2X_ERR("NVRAM config error. " |
cdaa7cb8 VZ |
8922 | "Invalid link_config 0x%x" |
8923 | " speed_cap_mask 0x%x\n", | |
a22f0788 YR |
8924 | link_config, |
8925 | bp->link_params.speed_cap_mask[idx]); | |
f85582f8 DK |
8926 | return; |
8927 | } | |
8928 | break; | |
a2fbb9ea | 8929 | |
f85582f8 | 8930 | case PORT_FEATURE_LINK_SPEED_1G: |
a22f0788 YR |
8931 | if (bp->port.supported[idx] & |
8932 | SUPPORTED_1000baseT_Full) { | |
8933 | bp->link_params.req_line_speed[idx] = | |
8934 | SPEED_1000; | |
8935 | bp->port.advertising[idx] |= | |
8936 | (ADVERTISED_1000baseT_Full | | |
f85582f8 DK |
8937 | ADVERTISED_TP); |
8938 | } else { | |
754a2f52 | 8939 | BNX2X_ERR("NVRAM config error. " |
cdaa7cb8 VZ |
8940 | "Invalid link_config 0x%x" |
8941 | " speed_cap_mask 0x%x\n", | |
a22f0788 YR |
8942 | link_config, |
8943 | bp->link_params.speed_cap_mask[idx]); | |
f85582f8 DK |
8944 | return; |
8945 | } | |
8946 | break; | |
a2fbb9ea | 8947 | |
f85582f8 | 8948 | case PORT_FEATURE_LINK_SPEED_2_5G: |
a22f0788 YR |
8949 | if (bp->port.supported[idx] & |
8950 | SUPPORTED_2500baseX_Full) { | |
8951 | bp->link_params.req_line_speed[idx] = | |
8952 | SPEED_2500; | |
8953 | bp->port.advertising[idx] |= | |
8954 | (ADVERTISED_2500baseX_Full | | |
34f80b04 | 8955 | ADVERTISED_TP); |
f85582f8 | 8956 | } else { |
754a2f52 | 8957 | BNX2X_ERR("NVRAM config error. " |
cdaa7cb8 VZ |
8958 | "Invalid link_config 0x%x" |
8959 | " speed_cap_mask 0x%x\n", | |
a22f0788 | 8960 | link_config, |
f85582f8 DK |
8961 | bp->link_params.speed_cap_mask[idx]); |
8962 | return; | |
8963 | } | |
8964 | break; | |
a2fbb9ea | 8965 | |
f85582f8 | 8966 | case PORT_FEATURE_LINK_SPEED_10G_CX4: |
a22f0788 YR |
8967 | if (bp->port.supported[idx] & |
8968 | SUPPORTED_10000baseT_Full) { | |
8969 | bp->link_params.req_line_speed[idx] = | |
8970 | SPEED_10000; | |
8971 | bp->port.advertising[idx] |= | |
8972 | (ADVERTISED_10000baseT_Full | | |
34f80b04 | 8973 | ADVERTISED_FIBRE); |
f85582f8 | 8974 | } else { |
754a2f52 | 8975 | BNX2X_ERR("NVRAM config error. " |
cdaa7cb8 VZ |
8976 | "Invalid link_config 0x%x" |
8977 | " speed_cap_mask 0x%x\n", | |
a22f0788 | 8978 | link_config, |
f85582f8 DK |
8979 | bp->link_params.speed_cap_mask[idx]); |
8980 | return; | |
8981 | } | |
8982 | break; | |
3c9ada22 YR |
8983 | case PORT_FEATURE_LINK_SPEED_20G: |
8984 | bp->link_params.req_line_speed[idx] = SPEED_20000; | |
a2fbb9ea | 8985 | |
3c9ada22 | 8986 | break; |
f85582f8 | 8987 | default: |
754a2f52 DK |
8988 | BNX2X_ERR("NVRAM config error. " |
8989 | "BAD link speed link_config 0x%x\n", | |
8990 | link_config); | |
f85582f8 DK |
8991 | bp->link_params.req_line_speed[idx] = |
8992 | SPEED_AUTO_NEG; | |
8993 | bp->port.advertising[idx] = | |
8994 | bp->port.supported[idx]; | |
8995 | break; | |
8996 | } | |
a2fbb9ea | 8997 | |
a22f0788 | 8998 | bp->link_params.req_flow_ctrl[idx] = (link_config & |
34f80b04 | 8999 | PORT_FEATURE_FLOW_CONTROL_MASK); |
a22f0788 YR |
9000 | if ((bp->link_params.req_flow_ctrl[idx] == |
9001 | BNX2X_FLOW_CTRL_AUTO) && | |
9002 | !(bp->port.supported[idx] & SUPPORTED_Autoneg)) { | |
9003 | bp->link_params.req_flow_ctrl[idx] = | |
9004 | BNX2X_FLOW_CTRL_NONE; | |
9005 | } | |
a2fbb9ea | 9006 | |
a22f0788 YR |
9007 | BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl" |
9008 | " 0x%x advertising 0x%x\n", | |
9009 | bp->link_params.req_line_speed[idx], | |
9010 | bp->link_params.req_duplex[idx], | |
9011 | bp->link_params.req_flow_ctrl[idx], | |
9012 | bp->port.advertising[idx]); | |
9013 | } | |
a2fbb9ea ET |
9014 | } |
9015 | ||
e665bfda MC |
9016 | static void __devinit bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi) |
9017 | { | |
9018 | mac_hi = cpu_to_be16(mac_hi); | |
9019 | mac_lo = cpu_to_be32(mac_lo); | |
9020 | memcpy(mac_buf, &mac_hi, sizeof(mac_hi)); | |
9021 | memcpy(mac_buf + sizeof(mac_hi), &mac_lo, sizeof(mac_lo)); | |
9022 | } | |
9023 | ||
34f80b04 | 9024 | static void __devinit bnx2x_get_port_hwinfo(struct bnx2x *bp) |
a2fbb9ea | 9025 | { |
34f80b04 | 9026 | int port = BP_PORT(bp); |
589abe3a | 9027 | u32 config; |
6f38ad93 | 9028 | u32 ext_phy_type, ext_phy_config; |
a2fbb9ea | 9029 | |
c18487ee | 9030 | bp->link_params.bp = bp; |
34f80b04 | 9031 | bp->link_params.port = port; |
c18487ee | 9032 | |
c18487ee | 9033 | bp->link_params.lane_config = |
a2fbb9ea | 9034 | SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config); |
4d295db0 | 9035 | |
a22f0788 | 9036 | bp->link_params.speed_cap_mask[0] = |
a2fbb9ea ET |
9037 | SHMEM_RD(bp, |
9038 | dev_info.port_hw_config[port].speed_capability_mask); | |
a22f0788 YR |
9039 | bp->link_params.speed_cap_mask[1] = |
9040 | SHMEM_RD(bp, | |
9041 | dev_info.port_hw_config[port].speed_capability_mask2); | |
9042 | bp->port.link_config[0] = | |
a2fbb9ea ET |
9043 | SHMEM_RD(bp, dev_info.port_feature_config[port].link_config); |
9044 | ||
a22f0788 YR |
9045 | bp->port.link_config[1] = |
9046 | SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2); | |
c2c8b03e | 9047 | |
a22f0788 YR |
9048 | bp->link_params.multi_phy_config = |
9049 | SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config); | |
3ce2c3f9 EG |
9050 | /* If the device is capable of WoL, set the default state according |
9051 | * to the HW | |
9052 | */ | |
4d295db0 | 9053 | config = SHMEM_RD(bp, dev_info.port_feature_config[port].config); |
3ce2c3f9 EG |
9054 | bp->wol = (!(bp->flags & NO_WOL_FLAG) && |
9055 | (config & PORT_FEATURE_WOL_ENABLED)); | |
9056 | ||
f85582f8 | 9057 | BNX2X_DEV_INFO("lane_config 0x%08x " |
a22f0788 | 9058 | "speed_cap_mask0 0x%08x link_config0 0x%08x\n", |
c18487ee | 9059 | bp->link_params.lane_config, |
a22f0788 YR |
9060 | bp->link_params.speed_cap_mask[0], |
9061 | bp->port.link_config[0]); | |
a2fbb9ea | 9062 | |
a22f0788 | 9063 | bp->link_params.switch_cfg = (bp->port.link_config[0] & |
f85582f8 | 9064 | PORT_FEATURE_CONNECTED_SWITCH_MASK); |
b7737c9b | 9065 | bnx2x_phy_probe(&bp->link_params); |
c18487ee | 9066 | bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg); |
a2fbb9ea ET |
9067 | |
9068 | bnx2x_link_settings_requested(bp); | |
9069 | ||
01cd4528 EG |
9070 | /* |
9071 | * If connected directly, work with the internal PHY, otherwise, work | |
9072 | * with the external PHY | |
9073 | */ | |
b7737c9b YR |
9074 | ext_phy_config = |
9075 | SHMEM_RD(bp, | |
9076 | dev_info.port_hw_config[port].external_phy_config); | |
9077 | ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config); | |
01cd4528 | 9078 | if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) |
b7737c9b | 9079 | bp->mdio.prtad = bp->port.phy_addr; |
01cd4528 EG |
9080 | |
9081 | else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) && | |
9082 | (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)) | |
9083 | bp->mdio.prtad = | |
b7737c9b | 9084 | XGXS_EXT_PHY_ADDR(ext_phy_config); |
5866df6d YR |
9085 | |
9086 | /* | |
9087 | * Check if hw lock is required to access MDC/MDIO bus to the PHY(s) | |
9088 | * In MF mode, it is set to cover self test cases | |
9089 | */ | |
9090 | if (IS_MF(bp)) | |
9091 | bp->port.need_hw_lock = 1; | |
9092 | else | |
9093 | bp->port.need_hw_lock = bnx2x_hw_lock_required(bp, | |
9094 | bp->common.shmem_base, | |
9095 | bp->common.shmem2_base); | |
0793f83f | 9096 | } |
01cd4528 | 9097 | |
2ba45142 VZ |
9098 | #ifdef BCM_CNIC |
9099 | static void __devinit bnx2x_get_cnic_info(struct bnx2x *bp) | |
9100 | { | |
9101 | u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp, | |
9102 | drv_lic_key[BP_PORT(bp)].max_iscsi_conn); | |
9103 | u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp, | |
9104 | drv_lic_key[BP_PORT(bp)].max_fcoe_conn); | |
9105 | ||
9106 | /* Get the number of maximum allowed iSCSI and FCoE connections */ | |
9107 | bp->cnic_eth_dev.max_iscsi_conn = | |
9108 | (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >> | |
9109 | BNX2X_MAX_ISCSI_INIT_CONN_SHIFT; | |
9110 | ||
9111 | bp->cnic_eth_dev.max_fcoe_conn = | |
9112 | (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >> | |
9113 | BNX2X_MAX_FCOE_INIT_CONN_SHIFT; | |
9114 | ||
9115 | BNX2X_DEV_INFO("max_iscsi_conn 0x%x max_fcoe_conn 0x%x\n", | |
9116 | bp->cnic_eth_dev.max_iscsi_conn, | |
9117 | bp->cnic_eth_dev.max_fcoe_conn); | |
9118 | ||
9119 | /* If mamimum allowed number of connections is zero - | |
9120 | * disable the feature. | |
9121 | */ | |
9122 | if (!bp->cnic_eth_dev.max_iscsi_conn) | |
9123 | bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG; | |
9124 | ||
9125 | if (!bp->cnic_eth_dev.max_fcoe_conn) | |
9126 | bp->flags |= NO_FCOE_FLAG; | |
9127 | } | |
9128 | #endif | |
9129 | ||
0793f83f DK |
9130 | static void __devinit bnx2x_get_mac_hwinfo(struct bnx2x *bp) |
9131 | { | |
9132 | u32 val, val2; | |
9133 | int func = BP_ABS_FUNC(bp); | |
9134 | int port = BP_PORT(bp); | |
2ba45142 VZ |
9135 | #ifdef BCM_CNIC |
9136 | u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac; | |
9137 | u8 *fip_mac = bp->fip_mac; | |
9138 | #endif | |
0793f83f | 9139 | |
619c5cb6 VZ |
9140 | /* Zero primary MAC configuration */ |
9141 | memset(bp->dev->dev_addr, 0, ETH_ALEN); | |
9142 | ||
0793f83f DK |
9143 | if (BP_NOMCP(bp)) { |
9144 | BNX2X_ERROR("warning: random MAC workaround active\n"); | |
9145 | random_ether_addr(bp->dev->dev_addr); | |
9146 | } else if (IS_MF(bp)) { | |
9147 | val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper); | |
9148 | val = MF_CFG_RD(bp, func_mf_config[func].mac_lower); | |
9149 | if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) && | |
9150 | (val != FUNC_MF_CFG_LOWERMAC_DEFAULT)) | |
9151 | bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2); | |
37b091ba MC |
9152 | |
9153 | #ifdef BCM_CNIC | |
2ba45142 VZ |
9154 | /* iSCSI and FCoE NPAR MACs: if there is no either iSCSI or |
9155 | * FCoE MAC then the appropriate feature should be disabled. | |
9156 | */ | |
0793f83f DK |
9157 | if (IS_MF_SI(bp)) { |
9158 | u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg); | |
9159 | if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) { | |
9160 | val2 = MF_CFG_RD(bp, func_ext_config[func]. | |
9161 | iscsi_mac_addr_upper); | |
9162 | val = MF_CFG_RD(bp, func_ext_config[func]. | |
9163 | iscsi_mac_addr_lower); | |
2ba45142 | 9164 | bnx2x_set_mac_buf(iscsi_mac, val, val2); |
619c5cb6 VZ |
9165 | BNX2X_DEV_INFO("Read iSCSI MAC: " |
9166 | BNX2X_MAC_FMT"\n", | |
9167 | BNX2X_MAC_PRN_LIST(iscsi_mac)); | |
2ba45142 VZ |
9168 | } else |
9169 | bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG; | |
9170 | ||
9171 | if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) { | |
9172 | val2 = MF_CFG_RD(bp, func_ext_config[func]. | |
9173 | fcoe_mac_addr_upper); | |
9174 | val = MF_CFG_RD(bp, func_ext_config[func]. | |
9175 | fcoe_mac_addr_lower); | |
2ba45142 | 9176 | bnx2x_set_mac_buf(fip_mac, val, val2); |
619c5cb6 VZ |
9177 | BNX2X_DEV_INFO("Read FCoE L2 MAC to " |
9178 | BNX2X_MAC_FMT"\n", | |
9179 | BNX2X_MAC_PRN_LIST(fip_mac)); | |
2ba45142 | 9180 | |
2ba45142 VZ |
9181 | } else |
9182 | bp->flags |= NO_FCOE_FLAG; | |
0793f83f | 9183 | } |
37b091ba | 9184 | #endif |
0793f83f DK |
9185 | } else { |
9186 | /* in SF read MACs from port configuration */ | |
9187 | val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper); | |
9188 | val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower); | |
9189 | bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2); | |
9190 | ||
9191 | #ifdef BCM_CNIC | |
9192 | val2 = SHMEM_RD(bp, dev_info.port_hw_config[port]. | |
9193 | iscsi_mac_upper); | |
9194 | val = SHMEM_RD(bp, dev_info.port_hw_config[port]. | |
9195 | iscsi_mac_lower); | |
2ba45142 | 9196 | bnx2x_set_mac_buf(iscsi_mac, val, val2); |
0793f83f DK |
9197 | #endif |
9198 | } | |
9199 | ||
9200 | memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN); | |
9201 | memcpy(bp->dev->perm_addr, bp->dev->dev_addr, ETH_ALEN); | |
9202 | ||
ec6ba945 | 9203 | #ifdef BCM_CNIC |
2ba45142 | 9204 | /* Set the FCoE MAC in modes other then MF_SI */ |
ec6ba945 VZ |
9205 | if (!CHIP_IS_E1x(bp)) { |
9206 | if (IS_MF_SD(bp)) | |
2ba45142 VZ |
9207 | memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN); |
9208 | else if (!IS_MF(bp)) | |
9209 | memcpy(fip_mac, iscsi_mac, ETH_ALEN); | |
ec6ba945 | 9210 | } |
426b9241 DK |
9211 | |
9212 | /* Disable iSCSI if MAC configuration is | |
9213 | * invalid. | |
9214 | */ | |
9215 | if (!is_valid_ether_addr(iscsi_mac)) { | |
9216 | bp->flags |= NO_ISCSI_FLAG; | |
9217 | memset(iscsi_mac, 0, ETH_ALEN); | |
9218 | } | |
9219 | ||
9220 | /* Disable FCoE if MAC configuration is | |
9221 | * invalid. | |
9222 | */ | |
9223 | if (!is_valid_ether_addr(fip_mac)) { | |
9224 | bp->flags |= NO_FCOE_FLAG; | |
9225 | memset(bp->fip_mac, 0, ETH_ALEN); | |
9226 | } | |
ec6ba945 | 9227 | #endif |
619c5cb6 VZ |
9228 | |
9229 | if (!is_valid_ether_addr(bp->dev->dev_addr)) | |
9230 | dev_err(&bp->pdev->dev, | |
9231 | "bad Ethernet MAC address configuration: " | |
9232 | BNX2X_MAC_FMT", change it manually before bringing up " | |
9233 | "the appropriate network interface\n", | |
9234 | BNX2X_MAC_PRN_LIST(bp->dev->dev_addr)); | |
34f80b04 EG |
9235 | } |
9236 | ||
9237 | static int __devinit bnx2x_get_hwinfo(struct bnx2x *bp) | |
9238 | { | |
0793f83f | 9239 | int /*abs*/func = BP_ABS_FUNC(bp); |
b8ee8328 | 9240 | int vn; |
0793f83f | 9241 | u32 val = 0; |
34f80b04 | 9242 | int rc = 0; |
a2fbb9ea | 9243 | |
34f80b04 | 9244 | bnx2x_get_common_hwinfo(bp); |
a2fbb9ea | 9245 | |
6383c0b3 AE |
9246 | /* |
9247 | * initialize IGU parameters | |
9248 | */ | |
f2e0899f DK |
9249 | if (CHIP_IS_E1x(bp)) { |
9250 | bp->common.int_block = INT_BLOCK_HC; | |
9251 | ||
9252 | bp->igu_dsb_id = DEF_SB_IGU_ID; | |
9253 | bp->igu_base_sb = 0; | |
f2e0899f DK |
9254 | } else { |
9255 | bp->common.int_block = INT_BLOCK_IGU; | |
9256 | val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION); | |
619c5cb6 VZ |
9257 | |
9258 | if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) { | |
9259 | int tout = 5000; | |
9260 | ||
9261 | BNX2X_DEV_INFO("FORCING Normal Mode\n"); | |
9262 | ||
9263 | val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN); | |
9264 | REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val); | |
9265 | REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f); | |
9266 | ||
9267 | while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) { | |
9268 | tout--; | |
9269 | usleep_range(1000, 1000); | |
9270 | } | |
9271 | ||
9272 | if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) { | |
9273 | dev_err(&bp->pdev->dev, | |
9274 | "FORCING Normal Mode failed!!!\n"); | |
9275 | return -EPERM; | |
9276 | } | |
9277 | } | |
9278 | ||
f2e0899f | 9279 | if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) { |
619c5cb6 | 9280 | BNX2X_DEV_INFO("IGU Backward Compatible Mode\n"); |
f2e0899f DK |
9281 | bp->common.int_block |= INT_BLOCK_MODE_BW_COMP; |
9282 | } else | |
619c5cb6 | 9283 | BNX2X_DEV_INFO("IGU Normal Mode\n"); |
523224a3 | 9284 | |
f2e0899f DK |
9285 | bnx2x_get_igu_cam_info(bp); |
9286 | ||
9287 | } | |
619c5cb6 VZ |
9288 | |
9289 | /* | |
9290 | * set base FW non-default (fast path) status block id, this value is | |
9291 | * used to initialize the fw_sb_id saved on the fp/queue structure to | |
9292 | * determine the id used by the FW. | |
9293 | */ | |
9294 | if (CHIP_IS_E1x(bp)) | |
9295 | bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp); | |
9296 | else /* | |
9297 | * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of | |
9298 | * the same queue are indicated on the same IGU SB). So we prefer | |
9299 | * FW and IGU SBs to be the same value. | |
9300 | */ | |
9301 | bp->base_fw_ndsb = bp->igu_base_sb; | |
9302 | ||
9303 | BNX2X_DEV_INFO("igu_dsb_id %d igu_base_sb %d igu_sb_cnt %d\n" | |
9304 | "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb, | |
9305 | bp->igu_sb_cnt, bp->base_fw_ndsb); | |
f2e0899f DK |
9306 | |
9307 | /* | |
9308 | * Initialize MF configuration | |
9309 | */ | |
523224a3 | 9310 | |
fb3bff17 DK |
9311 | bp->mf_ov = 0; |
9312 | bp->mf_mode = 0; | |
f2e0899f | 9313 | vn = BP_E1HVN(bp); |
0793f83f | 9314 | |
f2e0899f | 9315 | if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) { |
619c5cb6 VZ |
9316 | BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n", |
9317 | bp->common.shmem2_base, SHMEM2_RD(bp, size), | |
9318 | (u32)offsetof(struct shmem2_region, mf_cfg_addr)); | |
9319 | ||
f2e0899f DK |
9320 | if (SHMEM2_HAS(bp, mf_cfg_addr)) |
9321 | bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr); | |
9322 | else | |
9323 | bp->common.mf_cfg_base = bp->common.shmem_base + | |
523224a3 DK |
9324 | offsetof(struct shmem_region, func_mb) + |
9325 | E1H_FUNC_MAX * sizeof(struct drv_func_mb); | |
0793f83f DK |
9326 | /* |
9327 | * get mf configuration: | |
25985edc | 9328 | * 1. existence of MF configuration |
0793f83f DK |
9329 | * 2. MAC address must be legal (check only upper bytes) |
9330 | * for Switch-Independent mode; | |
9331 | * OVLAN must be legal for Switch-Dependent mode | |
9332 | * 3. SF_MODE configures specific MF mode | |
9333 | */ | |
9334 | if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) { | |
9335 | /* get mf configuration */ | |
9336 | val = SHMEM_RD(bp, | |
9337 | dev_info.shared_feature_config.config); | |
9338 | val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK; | |
9339 | ||
9340 | switch (val) { | |
9341 | case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT: | |
9342 | val = MF_CFG_RD(bp, func_mf_config[func]. | |
9343 | mac_upper); | |
9344 | /* check for legal mac (upper bytes)*/ | |
9345 | if (val != 0xffff) { | |
9346 | bp->mf_mode = MULTI_FUNCTION_SI; | |
9347 | bp->mf_config[vn] = MF_CFG_RD(bp, | |
9348 | func_mf_config[func].config); | |
9349 | } else | |
619c5cb6 VZ |
9350 | BNX2X_DEV_INFO("illegal MAC address " |
9351 | "for SI\n"); | |
0793f83f DK |
9352 | break; |
9353 | case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED: | |
9354 | /* get OV configuration */ | |
9355 | val = MF_CFG_RD(bp, | |
9356 | func_mf_config[FUNC_0].e1hov_tag); | |
9357 | val &= FUNC_MF_CFG_E1HOV_TAG_MASK; | |
9358 | ||
9359 | if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) { | |
9360 | bp->mf_mode = MULTI_FUNCTION_SD; | |
9361 | bp->mf_config[vn] = MF_CFG_RD(bp, | |
9362 | func_mf_config[func].config); | |
9363 | } else | |
754a2f52 | 9364 | BNX2X_DEV_INFO("illegal OV for SD\n"); |
0793f83f DK |
9365 | break; |
9366 | default: | |
9367 | /* Unknown configuration: reset mf_config */ | |
9368 | bp->mf_config[vn] = 0; | |
754a2f52 | 9369 | BNX2X_DEV_INFO("unkown MF mode 0x%x\n", val); |
0793f83f DK |
9370 | } |
9371 | } | |
a2fbb9ea | 9372 | |
2691d51d | 9373 | BNX2X_DEV_INFO("%s function mode\n", |
fb3bff17 | 9374 | IS_MF(bp) ? "multi" : "single"); |
2691d51d | 9375 | |
0793f83f DK |
9376 | switch (bp->mf_mode) { |
9377 | case MULTI_FUNCTION_SD: | |
9378 | val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) & | |
9379 | FUNC_MF_CFG_E1HOV_TAG_MASK; | |
2691d51d | 9380 | if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) { |
fb3bff17 | 9381 | bp->mf_ov = val; |
619c5cb6 VZ |
9382 | bp->path_has_ovlan = true; |
9383 | ||
9384 | BNX2X_DEV_INFO("MF OV for func %d is %d " | |
9385 | "(0x%04x)\n", func, bp->mf_ov, | |
9386 | bp->mf_ov); | |
2691d51d | 9387 | } else { |
619c5cb6 VZ |
9388 | dev_err(&bp->pdev->dev, |
9389 | "No valid MF OV for func %d, " | |
9390 | "aborting\n", func); | |
9391 | return -EPERM; | |
34f80b04 | 9392 | } |
0793f83f DK |
9393 | break; |
9394 | case MULTI_FUNCTION_SI: | |
9395 | BNX2X_DEV_INFO("func %d is in MF " | |
9396 | "switch-independent mode\n", func); | |
9397 | break; | |
9398 | default: | |
9399 | if (vn) { | |
619c5cb6 VZ |
9400 | dev_err(&bp->pdev->dev, |
9401 | "VN %d is in a single function mode, " | |
9402 | "aborting\n", vn); | |
9403 | return -EPERM; | |
2691d51d | 9404 | } |
0793f83f | 9405 | break; |
34f80b04 | 9406 | } |
0793f83f | 9407 | |
619c5cb6 VZ |
9408 | /* check if other port on the path needs ovlan: |
9409 | * Since MF configuration is shared between ports | |
9410 | * Possible mixed modes are only | |
9411 | * {SF, SI} {SF, SD} {SD, SF} {SI, SF} | |
9412 | */ | |
9413 | if (CHIP_MODE_IS_4_PORT(bp) && | |
9414 | !bp->path_has_ovlan && | |
9415 | !IS_MF(bp) && | |
9416 | bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) { | |
9417 | u8 other_port = !BP_PORT(bp); | |
9418 | u8 other_func = BP_PATH(bp) + 2*other_port; | |
9419 | val = MF_CFG_RD(bp, | |
9420 | func_mf_config[other_func].e1hov_tag); | |
9421 | if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) | |
9422 | bp->path_has_ovlan = true; | |
9423 | } | |
34f80b04 | 9424 | } |
a2fbb9ea | 9425 | |
f2e0899f DK |
9426 | /* adjust igu_sb_cnt to MF for E1x */ |
9427 | if (CHIP_IS_E1x(bp) && IS_MF(bp)) | |
523224a3 DK |
9428 | bp->igu_sb_cnt /= E1HVN_MAX; |
9429 | ||
619c5cb6 VZ |
9430 | /* port info */ |
9431 | bnx2x_get_port_hwinfo(bp); | |
f2e0899f | 9432 | |
34f80b04 | 9433 | if (!BP_NOMCP(bp)) { |
f2e0899f DK |
9434 | bp->fw_seq = |
9435 | (SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) & | |
9436 | DRV_MSG_SEQ_NUMBER_MASK); | |
34f80b04 EG |
9437 | BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq); |
9438 | } | |
9439 | ||
0793f83f DK |
9440 | /* Get MAC addresses */ |
9441 | bnx2x_get_mac_hwinfo(bp); | |
a2fbb9ea | 9442 | |
2ba45142 VZ |
9443 | #ifdef BCM_CNIC |
9444 | bnx2x_get_cnic_info(bp); | |
9445 | #endif | |
9446 | ||
619c5cb6 VZ |
9447 | /* Get current FW pulse sequence */ |
9448 | if (!BP_NOMCP(bp)) { | |
9449 | int mb_idx = BP_FW_MB_IDX(bp); | |
9450 | ||
9451 | bp->fw_drv_pulse_wr_seq = | |
9452 | (SHMEM_RD(bp, func_mb[mb_idx].drv_pulse_mb) & | |
9453 | DRV_PULSE_SEQ_MASK); | |
9454 | BNX2X_DEV_INFO("drv_pulse 0x%x\n", bp->fw_drv_pulse_wr_seq); | |
9455 | } | |
9456 | ||
34f80b04 EG |
9457 | return rc; |
9458 | } | |
9459 | ||
34f24c7f VZ |
9460 | static void __devinit bnx2x_read_fwinfo(struct bnx2x *bp) |
9461 | { | |
9462 | int cnt, i, block_end, rodi; | |
9463 | char vpd_data[BNX2X_VPD_LEN+1]; | |
9464 | char str_id_reg[VENDOR_ID_LEN+1]; | |
9465 | char str_id_cap[VENDOR_ID_LEN+1]; | |
9466 | u8 len; | |
9467 | ||
9468 | cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_data); | |
9469 | memset(bp->fw_ver, 0, sizeof(bp->fw_ver)); | |
9470 | ||
9471 | if (cnt < BNX2X_VPD_LEN) | |
9472 | goto out_not_found; | |
9473 | ||
9474 | i = pci_vpd_find_tag(vpd_data, 0, BNX2X_VPD_LEN, | |
9475 | PCI_VPD_LRDT_RO_DATA); | |
9476 | if (i < 0) | |
9477 | goto out_not_found; | |
9478 | ||
9479 | ||
9480 | block_end = i + PCI_VPD_LRDT_TAG_SIZE + | |
9481 | pci_vpd_lrdt_size(&vpd_data[i]); | |
9482 | ||
9483 | i += PCI_VPD_LRDT_TAG_SIZE; | |
9484 | ||
9485 | if (block_end > BNX2X_VPD_LEN) | |
9486 | goto out_not_found; | |
9487 | ||
9488 | rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end, | |
9489 | PCI_VPD_RO_KEYWORD_MFR_ID); | |
9490 | if (rodi < 0) | |
9491 | goto out_not_found; | |
9492 | ||
9493 | len = pci_vpd_info_field_size(&vpd_data[rodi]); | |
9494 | ||
9495 | if (len != VENDOR_ID_LEN) | |
9496 | goto out_not_found; | |
9497 | ||
9498 | rodi += PCI_VPD_INFO_FLD_HDR_SIZE; | |
9499 | ||
9500 | /* vendor specific info */ | |
9501 | snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL); | |
9502 | snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL); | |
9503 | if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) || | |
9504 | !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) { | |
9505 | ||
9506 | rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end, | |
9507 | PCI_VPD_RO_KEYWORD_VENDOR0); | |
9508 | if (rodi >= 0) { | |
9509 | len = pci_vpd_info_field_size(&vpd_data[rodi]); | |
9510 | ||
9511 | rodi += PCI_VPD_INFO_FLD_HDR_SIZE; | |
9512 | ||
9513 | if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) { | |
9514 | memcpy(bp->fw_ver, &vpd_data[rodi], len); | |
9515 | bp->fw_ver[len] = ' '; | |
9516 | } | |
9517 | } | |
9518 | return; | |
9519 | } | |
9520 | out_not_found: | |
9521 | return; | |
9522 | } | |
9523 | ||
619c5cb6 VZ |
9524 | static void __devinit bnx2x_set_modes_bitmap(struct bnx2x *bp) |
9525 | { | |
9526 | u32 flags = 0; | |
9527 | ||
9528 | if (CHIP_REV_IS_FPGA(bp)) | |
9529 | SET_FLAGS(flags, MODE_FPGA); | |
9530 | else if (CHIP_REV_IS_EMUL(bp)) | |
9531 | SET_FLAGS(flags, MODE_EMUL); | |
9532 | else | |
9533 | SET_FLAGS(flags, MODE_ASIC); | |
9534 | ||
9535 | if (CHIP_MODE_IS_4_PORT(bp)) | |
9536 | SET_FLAGS(flags, MODE_PORT4); | |
9537 | else | |
9538 | SET_FLAGS(flags, MODE_PORT2); | |
9539 | ||
9540 | if (CHIP_IS_E2(bp)) | |
9541 | SET_FLAGS(flags, MODE_E2); | |
9542 | else if (CHIP_IS_E3(bp)) { | |
9543 | SET_FLAGS(flags, MODE_E3); | |
9544 | if (CHIP_REV(bp) == CHIP_REV_Ax) | |
9545 | SET_FLAGS(flags, MODE_E3_A0); | |
6383c0b3 AE |
9546 | else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/ |
9547 | SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3); | |
619c5cb6 VZ |
9548 | } |
9549 | ||
9550 | if (IS_MF(bp)) { | |
9551 | SET_FLAGS(flags, MODE_MF); | |
9552 | switch (bp->mf_mode) { | |
9553 | case MULTI_FUNCTION_SD: | |
9554 | SET_FLAGS(flags, MODE_MF_SD); | |
9555 | break; | |
9556 | case MULTI_FUNCTION_SI: | |
9557 | SET_FLAGS(flags, MODE_MF_SI); | |
9558 | break; | |
9559 | } | |
9560 | } else | |
9561 | SET_FLAGS(flags, MODE_SF); | |
9562 | ||
9563 | #if defined(__LITTLE_ENDIAN) | |
9564 | SET_FLAGS(flags, MODE_LITTLE_ENDIAN); | |
9565 | #else /*(__BIG_ENDIAN)*/ | |
9566 | SET_FLAGS(flags, MODE_BIG_ENDIAN); | |
9567 | #endif | |
9568 | INIT_MODE_FLAGS(bp) = flags; | |
9569 | } | |
9570 | ||
34f80b04 EG |
9571 | static int __devinit bnx2x_init_bp(struct bnx2x *bp) |
9572 | { | |
f2e0899f | 9573 | int func; |
87942b46 | 9574 | int timer_interval; |
34f80b04 EG |
9575 | int rc; |
9576 | ||
34f80b04 | 9577 | mutex_init(&bp->port.phy_mutex); |
c4ff7cbf | 9578 | mutex_init(&bp->fw_mb_mutex); |
bb7e95c8 | 9579 | spin_lock_init(&bp->stats_lock); |
993ac7b5 MC |
9580 | #ifdef BCM_CNIC |
9581 | mutex_init(&bp->cnic_mutex); | |
9582 | #endif | |
a2fbb9ea | 9583 | |
1cf167f2 | 9584 | INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task); |
7be08a72 | 9585 | INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task); |
3deb8167 | 9586 | INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task); |
34f80b04 | 9587 | rc = bnx2x_get_hwinfo(bp); |
619c5cb6 VZ |
9588 | if (rc) |
9589 | return rc; | |
34f80b04 | 9590 | |
619c5cb6 VZ |
9591 | bnx2x_set_modes_bitmap(bp); |
9592 | ||
9593 | rc = bnx2x_alloc_mem_bp(bp); | |
9594 | if (rc) | |
9595 | return rc; | |
523224a3 | 9596 | |
34f24c7f | 9597 | bnx2x_read_fwinfo(bp); |
f2e0899f DK |
9598 | |
9599 | func = BP_FUNC(bp); | |
9600 | ||
34f80b04 EG |
9601 | /* need to reset chip if undi was active */ |
9602 | if (!BP_NOMCP(bp)) | |
9603 | bnx2x_undi_unload(bp); | |
9604 | ||
9605 | if (CHIP_REV_IS_FPGA(bp)) | |
cdaa7cb8 | 9606 | dev_err(&bp->pdev->dev, "FPGA detected\n"); |
34f80b04 EG |
9607 | |
9608 | if (BP_NOMCP(bp) && (func == 0)) | |
cdaa7cb8 VZ |
9609 | dev_err(&bp->pdev->dev, "MCP disabled, " |
9610 | "must load devices in order!\n"); | |
34f80b04 | 9611 | |
555f6c78 | 9612 | bp->multi_mode = multi_mode; |
555f6c78 | 9613 | |
7a9b2557 VZ |
9614 | /* Set TPA flags */ |
9615 | if (disable_tpa) { | |
9616 | bp->flags &= ~TPA_ENABLE_FLAG; | |
9617 | bp->dev->features &= ~NETIF_F_LRO; | |
9618 | } else { | |
9619 | bp->flags |= TPA_ENABLE_FLAG; | |
9620 | bp->dev->features |= NETIF_F_LRO; | |
9621 | } | |
5d7cd496 | 9622 | bp->disable_tpa = disable_tpa; |
7a9b2557 | 9623 | |
a18f5128 EG |
9624 | if (CHIP_IS_E1(bp)) |
9625 | bp->dropless_fc = 0; | |
9626 | else | |
9627 | bp->dropless_fc = dropless_fc; | |
9628 | ||
8d5726c4 | 9629 | bp->mrrs = mrrs; |
7a9b2557 | 9630 | |
34f80b04 | 9631 | bp->tx_ring_size = MAX_TX_AVAIL; |
34f80b04 | 9632 | |
7d323bfd | 9633 | /* make sure that the numbers are in the right granularity */ |
523224a3 DK |
9634 | bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR; |
9635 | bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR; | |
34f80b04 | 9636 | |
87942b46 EG |
9637 | timer_interval = (CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ); |
9638 | bp->current_interval = (poll ? poll : timer_interval); | |
34f80b04 EG |
9639 | |
9640 | init_timer(&bp->timer); | |
9641 | bp->timer.expires = jiffies + bp->current_interval; | |
9642 | bp->timer.data = (unsigned long) bp; | |
9643 | bp->timer.function = bnx2x_timer; | |
9644 | ||
785b9b1a | 9645 | bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON); |
e4901dde VZ |
9646 | bnx2x_dcbx_init_params(bp); |
9647 | ||
619c5cb6 VZ |
9648 | #ifdef BCM_CNIC |
9649 | if (CHIP_IS_E1x(bp)) | |
9650 | bp->cnic_base_cl_id = FP_SB_MAX_E1x; | |
9651 | else | |
9652 | bp->cnic_base_cl_id = FP_SB_MAX_E2; | |
9653 | #endif | |
9654 | ||
6383c0b3 AE |
9655 | /* multiple tx priority */ |
9656 | if (CHIP_IS_E1x(bp)) | |
9657 | bp->max_cos = BNX2X_MULTI_TX_COS_E1X; | |
9658 | if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp)) | |
9659 | bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0; | |
9660 | if (CHIP_IS_E3B0(bp)) | |
9661 | bp->max_cos = BNX2X_MULTI_TX_COS_E3B0; | |
9662 | ||
34f80b04 | 9663 | return rc; |
a2fbb9ea ET |
9664 | } |
9665 | ||
a2fbb9ea | 9666 | |
de0c62db DK |
9667 | /**************************************************************************** |
9668 | * General service functions | |
9669 | ****************************************************************************/ | |
a2fbb9ea | 9670 | |
619c5cb6 VZ |
9671 | /* |
9672 | * net_device service functions | |
9673 | */ | |
9674 | ||
bb2a0f7a | 9675 | /* called with rtnl_lock */ |
a2fbb9ea ET |
9676 | static int bnx2x_open(struct net_device *dev) |
9677 | { | |
9678 | struct bnx2x *bp = netdev_priv(dev); | |
c9ee9206 VZ |
9679 | bool global = false; |
9680 | int other_engine = BP_PATH(bp) ? 0 : 1; | |
9681 | u32 other_load_counter, load_counter; | |
a2fbb9ea | 9682 | |
6eccabb3 EG |
9683 | netif_carrier_off(dev); |
9684 | ||
a2fbb9ea ET |
9685 | bnx2x_set_power_state(bp, PCI_D0); |
9686 | ||
c9ee9206 VZ |
9687 | other_load_counter = bnx2x_get_load_cnt(bp, other_engine); |
9688 | load_counter = bnx2x_get_load_cnt(bp, BP_PATH(bp)); | |
9689 | ||
9690 | /* | |
9691 | * If parity had happen during the unload, then attentions | |
9692 | * and/or RECOVERY_IN_PROGRES may still be set. In this case we | |
9693 | * want the first function loaded on the current engine to | |
9694 | * complete the recovery. | |
9695 | */ | |
9696 | if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) || | |
9697 | bnx2x_chk_parity_attn(bp, &global, true)) | |
72fd0718 | 9698 | do { |
c9ee9206 VZ |
9699 | /* |
9700 | * If there are attentions and they are in a global | |
9701 | * blocks, set the GLOBAL_RESET bit regardless whether | |
9702 | * it will be this function that will complete the | |
9703 | * recovery or not. | |
72fd0718 | 9704 | */ |
c9ee9206 VZ |
9705 | if (global) |
9706 | bnx2x_set_reset_global(bp); | |
72fd0718 | 9707 | |
c9ee9206 VZ |
9708 | /* |
9709 | * Only the first function on the current engine should | |
9710 | * try to recover in open. In case of attentions in | |
9711 | * global blocks only the first in the chip should try | |
9712 | * to recover. | |
72fd0718 | 9713 | */ |
c9ee9206 VZ |
9714 | if ((!load_counter && |
9715 | (!global || !other_load_counter)) && | |
9716 | bnx2x_trylock_leader_lock(bp) && | |
9717 | !bnx2x_leader_reset(bp)) { | |
9718 | netdev_info(bp->dev, "Recovered in open\n"); | |
72fd0718 VZ |
9719 | break; |
9720 | } | |
9721 | ||
c9ee9206 | 9722 | /* recovery has failed... */ |
72fd0718 | 9723 | bnx2x_set_power_state(bp, PCI_D3hot); |
c9ee9206 | 9724 | bp->recovery_state = BNX2X_RECOVERY_FAILED; |
72fd0718 | 9725 | |
c9ee9206 | 9726 | netdev_err(bp->dev, "Recovery flow hasn't been properly" |
72fd0718 VZ |
9727 | " completed yet. Try again later. If u still see this" |
9728 | " message after a few retries then power cycle is" | |
c9ee9206 | 9729 | " required.\n"); |
72fd0718 VZ |
9730 | |
9731 | return -EAGAIN; | |
9732 | } while (0); | |
72fd0718 VZ |
9733 | |
9734 | bp->recovery_state = BNX2X_RECOVERY_DONE; | |
bb2a0f7a | 9735 | return bnx2x_nic_load(bp, LOAD_OPEN); |
a2fbb9ea ET |
9736 | } |
9737 | ||
bb2a0f7a | 9738 | /* called with rtnl_lock */ |
a2fbb9ea ET |
9739 | static int bnx2x_close(struct net_device *dev) |
9740 | { | |
a2fbb9ea ET |
9741 | struct bnx2x *bp = netdev_priv(dev); |
9742 | ||
9743 | /* Unload the driver, release IRQs */ | |
bb2a0f7a | 9744 | bnx2x_nic_unload(bp, UNLOAD_CLOSE); |
c9ee9206 VZ |
9745 | |
9746 | /* Power off */ | |
d3dbfee0 | 9747 | bnx2x_set_power_state(bp, PCI_D3hot); |
a2fbb9ea ET |
9748 | |
9749 | return 0; | |
9750 | } | |
9751 | ||
619c5cb6 VZ |
9752 | static inline int bnx2x_init_mcast_macs_list(struct bnx2x *bp, |
9753 | struct bnx2x_mcast_ramrod_params *p) | |
6e30dd4e | 9754 | { |
619c5cb6 VZ |
9755 | int mc_count = netdev_mc_count(bp->dev); |
9756 | struct bnx2x_mcast_list_elem *mc_mac = | |
9757 | kzalloc(sizeof(*mc_mac) * mc_count, GFP_ATOMIC); | |
9758 | struct netdev_hw_addr *ha; | |
6e30dd4e | 9759 | |
619c5cb6 VZ |
9760 | if (!mc_mac) |
9761 | return -ENOMEM; | |
6e30dd4e | 9762 | |
619c5cb6 | 9763 | INIT_LIST_HEAD(&p->mcast_list); |
6e30dd4e | 9764 | |
619c5cb6 VZ |
9765 | netdev_for_each_mc_addr(ha, bp->dev) { |
9766 | mc_mac->mac = bnx2x_mc_addr(ha); | |
9767 | list_add_tail(&mc_mac->link, &p->mcast_list); | |
9768 | mc_mac++; | |
6e30dd4e | 9769 | } |
619c5cb6 VZ |
9770 | |
9771 | p->mcast_list_len = mc_count; | |
9772 | ||
9773 | return 0; | |
6e30dd4e VZ |
9774 | } |
9775 | ||
619c5cb6 VZ |
9776 | static inline void bnx2x_free_mcast_macs_list( |
9777 | struct bnx2x_mcast_ramrod_params *p) | |
9778 | { | |
9779 | struct bnx2x_mcast_list_elem *mc_mac = | |
9780 | list_first_entry(&p->mcast_list, struct bnx2x_mcast_list_elem, | |
9781 | link); | |
9782 | ||
9783 | WARN_ON(!mc_mac); | |
9784 | kfree(mc_mac); | |
9785 | } | |
9786 | ||
9787 | /** | |
9788 | * bnx2x_set_uc_list - configure a new unicast MACs list. | |
9789 | * | |
9790 | * @bp: driver handle | |
6e30dd4e | 9791 | * |
619c5cb6 | 9792 | * We will use zero (0) as a MAC type for these MACs. |
6e30dd4e | 9793 | */ |
619c5cb6 | 9794 | static inline int bnx2x_set_uc_list(struct bnx2x *bp) |
6e30dd4e | 9795 | { |
619c5cb6 | 9796 | int rc; |
6e30dd4e | 9797 | struct net_device *dev = bp->dev; |
6e30dd4e | 9798 | struct netdev_hw_addr *ha; |
619c5cb6 VZ |
9799 | struct bnx2x_vlan_mac_obj *mac_obj = &bp->fp->mac_obj; |
9800 | unsigned long ramrod_flags = 0; | |
6e30dd4e | 9801 | |
619c5cb6 VZ |
9802 | /* First schedule a cleanup up of old configuration */ |
9803 | rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false); | |
9804 | if (rc < 0) { | |
9805 | BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc); | |
9806 | return rc; | |
9807 | } | |
6e30dd4e VZ |
9808 | |
9809 | netdev_for_each_uc_addr(ha, dev) { | |
619c5cb6 VZ |
9810 | rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true, |
9811 | BNX2X_UC_LIST_MAC, &ramrod_flags); | |
9812 | if (rc < 0) { | |
9813 | BNX2X_ERR("Failed to schedule ADD operations: %d\n", | |
9814 | rc); | |
9815 | return rc; | |
6e30dd4e VZ |
9816 | } |
9817 | } | |
9818 | ||
619c5cb6 VZ |
9819 | /* Execute the pending commands */ |
9820 | __set_bit(RAMROD_CONT, &ramrod_flags); | |
9821 | return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */, | |
9822 | BNX2X_UC_LIST_MAC, &ramrod_flags); | |
6e30dd4e VZ |
9823 | } |
9824 | ||
619c5cb6 | 9825 | static inline int bnx2x_set_mc_list(struct bnx2x *bp) |
6e30dd4e | 9826 | { |
619c5cb6 VZ |
9827 | struct net_device *dev = bp->dev; |
9828 | struct bnx2x_mcast_ramrod_params rparam = {0}; | |
9829 | int rc = 0; | |
6e30dd4e | 9830 | |
619c5cb6 | 9831 | rparam.mcast_obj = &bp->mcast_obj; |
6e30dd4e | 9832 | |
619c5cb6 VZ |
9833 | /* first, clear all configured multicast MACs */ |
9834 | rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL); | |
9835 | if (rc < 0) { | |
9836 | BNX2X_ERR("Failed to clear multicast " | |
9837 | "configuration: %d\n", rc); | |
9838 | return rc; | |
9839 | } | |
6e30dd4e | 9840 | |
619c5cb6 VZ |
9841 | /* then, configure a new MACs list */ |
9842 | if (netdev_mc_count(dev)) { | |
9843 | rc = bnx2x_init_mcast_macs_list(bp, &rparam); | |
9844 | if (rc) { | |
9845 | BNX2X_ERR("Failed to create multicast MACs " | |
9846 | "list: %d\n", rc); | |
9847 | return rc; | |
9848 | } | |
6e30dd4e | 9849 | |
619c5cb6 VZ |
9850 | /* Now add the new MACs */ |
9851 | rc = bnx2x_config_mcast(bp, &rparam, | |
9852 | BNX2X_MCAST_CMD_ADD); | |
9853 | if (rc < 0) | |
9854 | BNX2X_ERR("Failed to set a new multicast " | |
9855 | "configuration: %d\n", rc); | |
6e30dd4e | 9856 | |
619c5cb6 VZ |
9857 | bnx2x_free_mcast_macs_list(&rparam); |
9858 | } | |
6e30dd4e | 9859 | |
619c5cb6 | 9860 | return rc; |
6e30dd4e VZ |
9861 | } |
9862 | ||
6e30dd4e | 9863 | |
619c5cb6 | 9864 | /* If bp->state is OPEN, should be called with netif_addr_lock_bh() */ |
9f6c9258 | 9865 | void bnx2x_set_rx_mode(struct net_device *dev) |
34f80b04 EG |
9866 | { |
9867 | struct bnx2x *bp = netdev_priv(dev); | |
9868 | u32 rx_mode = BNX2X_RX_MODE_NORMAL; | |
34f80b04 EG |
9869 | |
9870 | if (bp->state != BNX2X_STATE_OPEN) { | |
9871 | DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state); | |
9872 | return; | |
9873 | } | |
9874 | ||
619c5cb6 | 9875 | DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags); |
34f80b04 EG |
9876 | |
9877 | if (dev->flags & IFF_PROMISC) | |
9878 | rx_mode = BNX2X_RX_MODE_PROMISC; | |
619c5cb6 VZ |
9879 | else if ((dev->flags & IFF_ALLMULTI) || |
9880 | ((netdev_mc_count(dev) > BNX2X_MAX_MULTICAST) && | |
9881 | CHIP_IS_E1(bp))) | |
34f80b04 | 9882 | rx_mode = BNX2X_RX_MODE_ALLMULTI; |
6e30dd4e VZ |
9883 | else { |
9884 | /* some multicasts */ | |
619c5cb6 | 9885 | if (bnx2x_set_mc_list(bp) < 0) |
6e30dd4e | 9886 | rx_mode = BNX2X_RX_MODE_ALLMULTI; |
34f80b04 | 9887 | |
619c5cb6 | 9888 | if (bnx2x_set_uc_list(bp) < 0) |
6e30dd4e | 9889 | rx_mode = BNX2X_RX_MODE_PROMISC; |
34f80b04 EG |
9890 | } |
9891 | ||
9892 | bp->rx_mode = rx_mode; | |
619c5cb6 VZ |
9893 | |
9894 | /* Schedule the rx_mode command */ | |
9895 | if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) { | |
9896 | set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state); | |
9897 | return; | |
9898 | } | |
9899 | ||
34f80b04 EG |
9900 | bnx2x_set_storm_rx_mode(bp); |
9901 | } | |
9902 | ||
c18487ee | 9903 | /* called with rtnl_lock */ |
01cd4528 EG |
9904 | static int bnx2x_mdio_read(struct net_device *netdev, int prtad, |
9905 | int devad, u16 addr) | |
a2fbb9ea | 9906 | { |
01cd4528 EG |
9907 | struct bnx2x *bp = netdev_priv(netdev); |
9908 | u16 value; | |
9909 | int rc; | |
a2fbb9ea | 9910 | |
01cd4528 EG |
9911 | DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n", |
9912 | prtad, devad, addr); | |
a2fbb9ea | 9913 | |
01cd4528 EG |
9914 | /* The HW expects different devad if CL22 is used */ |
9915 | devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad; | |
c18487ee | 9916 | |
01cd4528 | 9917 | bnx2x_acquire_phy_lock(bp); |
e10bc84d | 9918 | rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value); |
01cd4528 EG |
9919 | bnx2x_release_phy_lock(bp); |
9920 | DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc); | |
a2fbb9ea | 9921 | |
01cd4528 EG |
9922 | if (!rc) |
9923 | rc = value; | |
9924 | return rc; | |
9925 | } | |
a2fbb9ea | 9926 | |
01cd4528 EG |
9927 | /* called with rtnl_lock */ |
9928 | static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad, | |
9929 | u16 addr, u16 value) | |
9930 | { | |
9931 | struct bnx2x *bp = netdev_priv(netdev); | |
01cd4528 EG |
9932 | int rc; |
9933 | ||
9934 | DP(NETIF_MSG_LINK, "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x," | |
9935 | " value 0x%x\n", prtad, devad, addr, value); | |
9936 | ||
01cd4528 EG |
9937 | /* The HW expects different devad if CL22 is used */ |
9938 | devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad; | |
a2fbb9ea | 9939 | |
01cd4528 | 9940 | bnx2x_acquire_phy_lock(bp); |
e10bc84d | 9941 | rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value); |
01cd4528 EG |
9942 | bnx2x_release_phy_lock(bp); |
9943 | return rc; | |
9944 | } | |
c18487ee | 9945 | |
01cd4528 EG |
9946 | /* called with rtnl_lock */ |
9947 | static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) | |
9948 | { | |
9949 | struct bnx2x *bp = netdev_priv(dev); | |
9950 | struct mii_ioctl_data *mdio = if_mii(ifr); | |
a2fbb9ea | 9951 | |
01cd4528 EG |
9952 | DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n", |
9953 | mdio->phy_id, mdio->reg_num, mdio->val_in); | |
a2fbb9ea | 9954 | |
01cd4528 EG |
9955 | if (!netif_running(dev)) |
9956 | return -EAGAIN; | |
9957 | ||
9958 | return mdio_mii_ioctl(&bp->mdio, mdio, cmd); | |
a2fbb9ea ET |
9959 | } |
9960 | ||
257ddbda | 9961 | #ifdef CONFIG_NET_POLL_CONTROLLER |
a2fbb9ea ET |
9962 | static void poll_bnx2x(struct net_device *dev) |
9963 | { | |
9964 | struct bnx2x *bp = netdev_priv(dev); | |
9965 | ||
9966 | disable_irq(bp->pdev->irq); | |
9967 | bnx2x_interrupt(bp->pdev->irq, dev); | |
9968 | enable_irq(bp->pdev->irq); | |
9969 | } | |
9970 | #endif | |
9971 | ||
c64213cd SH |
9972 | static const struct net_device_ops bnx2x_netdev_ops = { |
9973 | .ndo_open = bnx2x_open, | |
9974 | .ndo_stop = bnx2x_close, | |
9975 | .ndo_start_xmit = bnx2x_start_xmit, | |
8307fa3e | 9976 | .ndo_select_queue = bnx2x_select_queue, |
6e30dd4e | 9977 | .ndo_set_rx_mode = bnx2x_set_rx_mode, |
c64213cd SH |
9978 | .ndo_set_mac_address = bnx2x_change_mac_addr, |
9979 | .ndo_validate_addr = eth_validate_addr, | |
9980 | .ndo_do_ioctl = bnx2x_ioctl, | |
9981 | .ndo_change_mtu = bnx2x_change_mtu, | |
66371c44 MM |
9982 | .ndo_fix_features = bnx2x_fix_features, |
9983 | .ndo_set_features = bnx2x_set_features, | |
c64213cd | 9984 | .ndo_tx_timeout = bnx2x_tx_timeout, |
257ddbda | 9985 | #ifdef CONFIG_NET_POLL_CONTROLLER |
c64213cd SH |
9986 | .ndo_poll_controller = poll_bnx2x, |
9987 | #endif | |
6383c0b3 AE |
9988 | .ndo_setup_tc = bnx2x_setup_tc, |
9989 | ||
c64213cd SH |
9990 | }; |
9991 | ||
619c5cb6 VZ |
9992 | static inline int bnx2x_set_coherency_mask(struct bnx2x *bp) |
9993 | { | |
9994 | struct device *dev = &bp->pdev->dev; | |
9995 | ||
9996 | if (dma_set_mask(dev, DMA_BIT_MASK(64)) == 0) { | |
9997 | bp->flags |= USING_DAC_FLAG; | |
9998 | if (dma_set_coherent_mask(dev, DMA_BIT_MASK(64)) != 0) { | |
9999 | dev_err(dev, "dma_set_coherent_mask failed, " | |
10000 | "aborting\n"); | |
10001 | return -EIO; | |
10002 | } | |
10003 | } else if (dma_set_mask(dev, DMA_BIT_MASK(32)) != 0) { | |
10004 | dev_err(dev, "System does not support DMA, aborting\n"); | |
10005 | return -EIO; | |
10006 | } | |
10007 | ||
10008 | return 0; | |
10009 | } | |
10010 | ||
34f80b04 | 10011 | static int __devinit bnx2x_init_dev(struct pci_dev *pdev, |
619c5cb6 VZ |
10012 | struct net_device *dev, |
10013 | unsigned long board_type) | |
a2fbb9ea ET |
10014 | { |
10015 | struct bnx2x *bp; | |
10016 | int rc; | |
10017 | ||
10018 | SET_NETDEV_DEV(dev, &pdev->dev); | |
10019 | bp = netdev_priv(dev); | |
10020 | ||
34f80b04 EG |
10021 | bp->dev = dev; |
10022 | bp->pdev = pdev; | |
a2fbb9ea | 10023 | bp->flags = 0; |
f2e0899f | 10024 | bp->pf_num = PCI_FUNC(pdev->devfn); |
a2fbb9ea ET |
10025 | |
10026 | rc = pci_enable_device(pdev); | |
10027 | if (rc) { | |
cdaa7cb8 VZ |
10028 | dev_err(&bp->pdev->dev, |
10029 | "Cannot enable PCI device, aborting\n"); | |
a2fbb9ea ET |
10030 | goto err_out; |
10031 | } | |
10032 | ||
10033 | if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { | |
cdaa7cb8 VZ |
10034 | dev_err(&bp->pdev->dev, |
10035 | "Cannot find PCI device base address, aborting\n"); | |
a2fbb9ea ET |
10036 | rc = -ENODEV; |
10037 | goto err_out_disable; | |
10038 | } | |
10039 | ||
10040 | if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) { | |
cdaa7cb8 VZ |
10041 | dev_err(&bp->pdev->dev, "Cannot find second PCI device" |
10042 | " base address, aborting\n"); | |
a2fbb9ea ET |
10043 | rc = -ENODEV; |
10044 | goto err_out_disable; | |
10045 | } | |
10046 | ||
34f80b04 EG |
10047 | if (atomic_read(&pdev->enable_cnt) == 1) { |
10048 | rc = pci_request_regions(pdev, DRV_MODULE_NAME); | |
10049 | if (rc) { | |
cdaa7cb8 VZ |
10050 | dev_err(&bp->pdev->dev, |
10051 | "Cannot obtain PCI resources, aborting\n"); | |
34f80b04 EG |
10052 | goto err_out_disable; |
10053 | } | |
a2fbb9ea | 10054 | |
34f80b04 EG |
10055 | pci_set_master(pdev); |
10056 | pci_save_state(pdev); | |
10057 | } | |
a2fbb9ea ET |
10058 | |
10059 | bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM); | |
10060 | if (bp->pm_cap == 0) { | |
cdaa7cb8 VZ |
10061 | dev_err(&bp->pdev->dev, |
10062 | "Cannot find power management capability, aborting\n"); | |
a2fbb9ea ET |
10063 | rc = -EIO; |
10064 | goto err_out_release; | |
10065 | } | |
10066 | ||
77c98e6a JM |
10067 | if (!pci_is_pcie(pdev)) { |
10068 | dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n"); | |
a2fbb9ea ET |
10069 | rc = -EIO; |
10070 | goto err_out_release; | |
10071 | } | |
10072 | ||
619c5cb6 VZ |
10073 | rc = bnx2x_set_coherency_mask(bp); |
10074 | if (rc) | |
a2fbb9ea | 10075 | goto err_out_release; |
a2fbb9ea | 10076 | |
34f80b04 EG |
10077 | dev->mem_start = pci_resource_start(pdev, 0); |
10078 | dev->base_addr = dev->mem_start; | |
10079 | dev->mem_end = pci_resource_end(pdev, 0); | |
a2fbb9ea ET |
10080 | |
10081 | dev->irq = pdev->irq; | |
10082 | ||
275f165f | 10083 | bp->regview = pci_ioremap_bar(pdev, 0); |
a2fbb9ea | 10084 | if (!bp->regview) { |
cdaa7cb8 VZ |
10085 | dev_err(&bp->pdev->dev, |
10086 | "Cannot map register space, aborting\n"); | |
a2fbb9ea ET |
10087 | rc = -ENOMEM; |
10088 | goto err_out_release; | |
10089 | } | |
10090 | ||
a2fbb9ea ET |
10091 | bnx2x_set_power_state(bp, PCI_D0); |
10092 | ||
34f80b04 EG |
10093 | /* clean indirect addresses */ |
10094 | pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, | |
10095 | PCICFG_VENDOR_ID_OFFSET); | |
10096 | REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0 + BP_PORT(bp)*16, 0); | |
10097 | REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0 + BP_PORT(bp)*16, 0); | |
10098 | REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0 + BP_PORT(bp)*16, 0); | |
10099 | REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0 + BP_PORT(bp)*16, 0); | |
a2fbb9ea | 10100 | |
619c5cb6 VZ |
10101 | /** |
10102 | * Enable internal target-read (in case we are probed after PF FLR). | |
10103 | * Must be done prior to any BAR read access | |
10104 | */ | |
10105 | REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); | |
10106 | ||
72fd0718 VZ |
10107 | /* Reset the load counter */ |
10108 | bnx2x_clear_load_cnt(bp); | |
10109 | ||
34f80b04 | 10110 | dev->watchdog_timeo = TX_TIMEOUT; |
a2fbb9ea | 10111 | |
c64213cd | 10112 | dev->netdev_ops = &bnx2x_netdev_ops; |
de0c62db | 10113 | bnx2x_set_ethtool_ops(dev); |
5316bc0b | 10114 | |
66371c44 MM |
10115 | dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | |
10116 | NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | | |
10117 | NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_HW_VLAN_TX; | |
10118 | ||
10119 | dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | | |
10120 | NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA; | |
10121 | ||
10122 | dev->features |= dev->hw_features | NETIF_F_HW_VLAN_RX; | |
5316bc0b | 10123 | if (bp->flags & USING_DAC_FLAG) |
66371c44 | 10124 | dev->features |= NETIF_F_HIGHDMA; |
a2fbb9ea | 10125 | |
538dd2e3 MB |
10126 | /* Add Loopback capability to the device */ |
10127 | dev->hw_features |= NETIF_F_LOOPBACK; | |
10128 | ||
98507672 | 10129 | #ifdef BCM_DCBNL |
785b9b1a SR |
10130 | dev->dcbnl_ops = &bnx2x_dcbnl_ops; |
10131 | #endif | |
10132 | ||
01cd4528 EG |
10133 | /* get_port_hwinfo() will set prtad and mmds properly */ |
10134 | bp->mdio.prtad = MDIO_PRTAD_NONE; | |
10135 | bp->mdio.mmds = 0; | |
10136 | bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; | |
10137 | bp->mdio.dev = dev; | |
10138 | bp->mdio.mdio_read = bnx2x_mdio_read; | |
10139 | bp->mdio.mdio_write = bnx2x_mdio_write; | |
10140 | ||
a2fbb9ea ET |
10141 | return 0; |
10142 | ||
a2fbb9ea | 10143 | err_out_release: |
34f80b04 EG |
10144 | if (atomic_read(&pdev->enable_cnt) == 1) |
10145 | pci_release_regions(pdev); | |
a2fbb9ea ET |
10146 | |
10147 | err_out_disable: | |
10148 | pci_disable_device(pdev); | |
10149 | pci_set_drvdata(pdev, NULL); | |
10150 | ||
10151 | err_out: | |
10152 | return rc; | |
10153 | } | |
10154 | ||
37f9ce62 EG |
10155 | static void __devinit bnx2x_get_pcie_width_speed(struct bnx2x *bp, |
10156 | int *width, int *speed) | |
25047950 ET |
10157 | { |
10158 | u32 val = REG_RD(bp, PCICFG_OFFSET + PCICFG_LINK_CONTROL); | |
10159 | ||
37f9ce62 | 10160 | *width = (val & PCICFG_LINK_WIDTH) >> PCICFG_LINK_WIDTH_SHIFT; |
25047950 | 10161 | |
37f9ce62 EG |
10162 | /* return value of 1=2.5GHz 2=5GHz */ |
10163 | *speed = (val & PCICFG_LINK_SPEED) >> PCICFG_LINK_SPEED_SHIFT; | |
25047950 | 10164 | } |
37f9ce62 | 10165 | |
6891dd25 | 10166 | static int bnx2x_check_firmware(struct bnx2x *bp) |
94a78b79 | 10167 | { |
37f9ce62 | 10168 | const struct firmware *firmware = bp->firmware; |
94a78b79 VZ |
10169 | struct bnx2x_fw_file_hdr *fw_hdr; |
10170 | struct bnx2x_fw_file_section *sections; | |
94a78b79 | 10171 | u32 offset, len, num_ops; |
37f9ce62 | 10172 | u16 *ops_offsets; |
94a78b79 | 10173 | int i; |
37f9ce62 | 10174 | const u8 *fw_ver; |
94a78b79 VZ |
10175 | |
10176 | if (firmware->size < sizeof(struct bnx2x_fw_file_hdr)) | |
10177 | return -EINVAL; | |
10178 | ||
10179 | fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data; | |
10180 | sections = (struct bnx2x_fw_file_section *)fw_hdr; | |
10181 | ||
10182 | /* Make sure none of the offsets and sizes make us read beyond | |
10183 | * the end of the firmware data */ | |
10184 | for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) { | |
10185 | offset = be32_to_cpu(sections[i].offset); | |
10186 | len = be32_to_cpu(sections[i].len); | |
10187 | if (offset + len > firmware->size) { | |
cdaa7cb8 VZ |
10188 | dev_err(&bp->pdev->dev, |
10189 | "Section %d length is out of bounds\n", i); | |
94a78b79 VZ |
10190 | return -EINVAL; |
10191 | } | |
10192 | } | |
10193 | ||
10194 | /* Likewise for the init_ops offsets */ | |
10195 | offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset); | |
10196 | ops_offsets = (u16 *)(firmware->data + offset); | |
10197 | num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op); | |
10198 | ||
10199 | for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) { | |
10200 | if (be16_to_cpu(ops_offsets[i]) > num_ops) { | |
cdaa7cb8 VZ |
10201 | dev_err(&bp->pdev->dev, |
10202 | "Section offset %d is out of bounds\n", i); | |
94a78b79 VZ |
10203 | return -EINVAL; |
10204 | } | |
10205 | } | |
10206 | ||
10207 | /* Check FW version */ | |
10208 | offset = be32_to_cpu(fw_hdr->fw_version.offset); | |
10209 | fw_ver = firmware->data + offset; | |
10210 | if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) || | |
10211 | (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) || | |
10212 | (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) || | |
10213 | (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) { | |
cdaa7cb8 VZ |
10214 | dev_err(&bp->pdev->dev, |
10215 | "Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n", | |
94a78b79 VZ |
10216 | fw_ver[0], fw_ver[1], fw_ver[2], |
10217 | fw_ver[3], BCM_5710_FW_MAJOR_VERSION, | |
10218 | BCM_5710_FW_MINOR_VERSION, | |
10219 | BCM_5710_FW_REVISION_VERSION, | |
10220 | BCM_5710_FW_ENGINEERING_VERSION); | |
ab6ad5a4 | 10221 | return -EINVAL; |
94a78b79 VZ |
10222 | } |
10223 | ||
10224 | return 0; | |
10225 | } | |
10226 | ||
ab6ad5a4 | 10227 | static inline void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n) |
94a78b79 | 10228 | { |
ab6ad5a4 EG |
10229 | const __be32 *source = (const __be32 *)_source; |
10230 | u32 *target = (u32 *)_target; | |
94a78b79 | 10231 | u32 i; |
94a78b79 VZ |
10232 | |
10233 | for (i = 0; i < n/4; i++) | |
10234 | target[i] = be32_to_cpu(source[i]); | |
10235 | } | |
10236 | ||
10237 | /* | |
10238 | Ops array is stored in the following format: | |
10239 | {op(8bit), offset(24bit, big endian), data(32bit, big endian)} | |
10240 | */ | |
ab6ad5a4 | 10241 | static inline void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n) |
94a78b79 | 10242 | { |
ab6ad5a4 EG |
10243 | const __be32 *source = (const __be32 *)_source; |
10244 | struct raw_op *target = (struct raw_op *)_target; | |
94a78b79 | 10245 | u32 i, j, tmp; |
94a78b79 | 10246 | |
ab6ad5a4 | 10247 | for (i = 0, j = 0; i < n/8; i++, j += 2) { |
94a78b79 VZ |
10248 | tmp = be32_to_cpu(source[j]); |
10249 | target[i].op = (tmp >> 24) & 0xff; | |
cdaa7cb8 VZ |
10250 | target[i].offset = tmp & 0xffffff; |
10251 | target[i].raw_data = be32_to_cpu(source[j + 1]); | |
94a78b79 VZ |
10252 | } |
10253 | } | |
ab6ad5a4 | 10254 | |
523224a3 DK |
10255 | /** |
10256 | * IRO array is stored in the following format: | |
10257 | * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) } | |
10258 | */ | |
10259 | static inline void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n) | |
10260 | { | |
10261 | const __be32 *source = (const __be32 *)_source; | |
10262 | struct iro *target = (struct iro *)_target; | |
10263 | u32 i, j, tmp; | |
10264 | ||
10265 | for (i = 0, j = 0; i < n/sizeof(struct iro); i++) { | |
10266 | target[i].base = be32_to_cpu(source[j]); | |
10267 | j++; | |
10268 | tmp = be32_to_cpu(source[j]); | |
10269 | target[i].m1 = (tmp >> 16) & 0xffff; | |
10270 | target[i].m2 = tmp & 0xffff; | |
10271 | j++; | |
10272 | tmp = be32_to_cpu(source[j]); | |
10273 | target[i].m3 = (tmp >> 16) & 0xffff; | |
10274 | target[i].size = tmp & 0xffff; | |
10275 | j++; | |
10276 | } | |
10277 | } | |
10278 | ||
ab6ad5a4 | 10279 | static inline void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n) |
94a78b79 | 10280 | { |
ab6ad5a4 EG |
10281 | const __be16 *source = (const __be16 *)_source; |
10282 | u16 *target = (u16 *)_target; | |
94a78b79 | 10283 | u32 i; |
94a78b79 VZ |
10284 | |
10285 | for (i = 0; i < n/2; i++) | |
10286 | target[i] = be16_to_cpu(source[i]); | |
10287 | } | |
10288 | ||
7995c64e JP |
10289 | #define BNX2X_ALLOC_AND_SET(arr, lbl, func) \ |
10290 | do { \ | |
10291 | u32 len = be32_to_cpu(fw_hdr->arr.len); \ | |
10292 | bp->arr = kmalloc(len, GFP_KERNEL); \ | |
10293 | if (!bp->arr) { \ | |
10294 | pr_err("Failed to allocate %d bytes for "#arr"\n", len); \ | |
10295 | goto lbl; \ | |
10296 | } \ | |
10297 | func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \ | |
10298 | (u8 *)bp->arr, len); \ | |
10299 | } while (0) | |
94a78b79 | 10300 | |
6891dd25 | 10301 | int bnx2x_init_firmware(struct bnx2x *bp) |
94a78b79 | 10302 | { |
45229b42 | 10303 | const char *fw_file_name; |
94a78b79 | 10304 | struct bnx2x_fw_file_hdr *fw_hdr; |
45229b42 | 10305 | int rc; |
94a78b79 | 10306 | |
94a78b79 | 10307 | if (CHIP_IS_E1(bp)) |
45229b42 | 10308 | fw_file_name = FW_FILE_NAME_E1; |
cdaa7cb8 | 10309 | else if (CHIP_IS_E1H(bp)) |
45229b42 | 10310 | fw_file_name = FW_FILE_NAME_E1H; |
619c5cb6 | 10311 | else if (!CHIP_IS_E1x(bp)) |
f2e0899f | 10312 | fw_file_name = FW_FILE_NAME_E2; |
cdaa7cb8 | 10313 | else { |
6891dd25 | 10314 | BNX2X_ERR("Unsupported chip revision\n"); |
cdaa7cb8 VZ |
10315 | return -EINVAL; |
10316 | } | |
94a78b79 | 10317 | |
6891dd25 | 10318 | BNX2X_DEV_INFO("Loading %s\n", fw_file_name); |
94a78b79 | 10319 | |
6891dd25 | 10320 | rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev); |
94a78b79 | 10321 | if (rc) { |
6891dd25 | 10322 | BNX2X_ERR("Can't load firmware file %s\n", fw_file_name); |
94a78b79 VZ |
10323 | goto request_firmware_exit; |
10324 | } | |
10325 | ||
10326 | rc = bnx2x_check_firmware(bp); | |
10327 | if (rc) { | |
6891dd25 | 10328 | BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name); |
94a78b79 VZ |
10329 | goto request_firmware_exit; |
10330 | } | |
10331 | ||
10332 | fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data; | |
10333 | ||
10334 | /* Initialize the pointers to the init arrays */ | |
10335 | /* Blob */ | |
10336 | BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n); | |
10337 | ||
10338 | /* Opcodes */ | |
10339 | BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops); | |
10340 | ||
10341 | /* Offsets */ | |
ab6ad5a4 EG |
10342 | BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err, |
10343 | be16_to_cpu_n); | |
94a78b79 VZ |
10344 | |
10345 | /* STORMs firmware */ | |
573f2035 EG |
10346 | INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data + |
10347 | be32_to_cpu(fw_hdr->tsem_int_table_data.offset); | |
10348 | INIT_TSEM_PRAM_DATA(bp) = bp->firmware->data + | |
10349 | be32_to_cpu(fw_hdr->tsem_pram_data.offset); | |
10350 | INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data + | |
10351 | be32_to_cpu(fw_hdr->usem_int_table_data.offset); | |
10352 | INIT_USEM_PRAM_DATA(bp) = bp->firmware->data + | |
10353 | be32_to_cpu(fw_hdr->usem_pram_data.offset); | |
10354 | INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data + | |
10355 | be32_to_cpu(fw_hdr->xsem_int_table_data.offset); | |
10356 | INIT_XSEM_PRAM_DATA(bp) = bp->firmware->data + | |
10357 | be32_to_cpu(fw_hdr->xsem_pram_data.offset); | |
10358 | INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data + | |
10359 | be32_to_cpu(fw_hdr->csem_int_table_data.offset); | |
10360 | INIT_CSEM_PRAM_DATA(bp) = bp->firmware->data + | |
10361 | be32_to_cpu(fw_hdr->csem_pram_data.offset); | |
523224a3 DK |
10362 | /* IRO */ |
10363 | BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro); | |
94a78b79 VZ |
10364 | |
10365 | return 0; | |
ab6ad5a4 | 10366 | |
523224a3 DK |
10367 | iro_alloc_err: |
10368 | kfree(bp->init_ops_offsets); | |
94a78b79 VZ |
10369 | init_offsets_alloc_err: |
10370 | kfree(bp->init_ops); | |
10371 | init_ops_alloc_err: | |
10372 | kfree(bp->init_data); | |
10373 | request_firmware_exit: | |
10374 | release_firmware(bp->firmware); | |
10375 | ||
10376 | return rc; | |
10377 | } | |
10378 | ||
619c5cb6 VZ |
10379 | static void bnx2x_release_firmware(struct bnx2x *bp) |
10380 | { | |
10381 | kfree(bp->init_ops_offsets); | |
10382 | kfree(bp->init_ops); | |
10383 | kfree(bp->init_data); | |
10384 | release_firmware(bp->firmware); | |
10385 | } | |
10386 | ||
10387 | ||
10388 | static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = { | |
10389 | .init_hw_cmn_chip = bnx2x_init_hw_common_chip, | |
10390 | .init_hw_cmn = bnx2x_init_hw_common, | |
10391 | .init_hw_port = bnx2x_init_hw_port, | |
10392 | .init_hw_func = bnx2x_init_hw_func, | |
10393 | ||
10394 | .reset_hw_cmn = bnx2x_reset_common, | |
10395 | .reset_hw_port = bnx2x_reset_port, | |
10396 | .reset_hw_func = bnx2x_reset_func, | |
10397 | ||
10398 | .gunzip_init = bnx2x_gunzip_init, | |
10399 | .gunzip_end = bnx2x_gunzip_end, | |
10400 | ||
10401 | .init_fw = bnx2x_init_firmware, | |
10402 | .release_fw = bnx2x_release_firmware, | |
10403 | }; | |
10404 | ||
10405 | void bnx2x__init_func_obj(struct bnx2x *bp) | |
10406 | { | |
10407 | /* Prepare DMAE related driver resources */ | |
10408 | bnx2x_setup_dmae(bp); | |
10409 | ||
10410 | bnx2x_init_func_obj(bp, &bp->func_obj, | |
10411 | bnx2x_sp(bp, func_rdata), | |
10412 | bnx2x_sp_mapping(bp, func_rdata), | |
10413 | &bnx2x_func_sp_drv); | |
10414 | } | |
10415 | ||
10416 | /* must be called after sriov-enable */ | |
6383c0b3 | 10417 | static inline int bnx2x_set_qm_cid_count(struct bnx2x *bp) |
523224a3 | 10418 | { |
6383c0b3 | 10419 | int cid_count = BNX2X_L2_CID_COUNT(bp); |
94a78b79 | 10420 | |
523224a3 DK |
10421 | #ifdef BCM_CNIC |
10422 | cid_count += CNIC_CID_MAX; | |
10423 | #endif | |
10424 | return roundup(cid_count, QM_CID_ROUND); | |
10425 | } | |
f85582f8 | 10426 | |
619c5cb6 | 10427 | /** |
6383c0b3 | 10428 | * bnx2x_get_num_none_def_sbs - return the number of none default SBs |
619c5cb6 VZ |
10429 | * |
10430 | * @dev: pci device | |
10431 | * | |
10432 | */ | |
6383c0b3 | 10433 | static inline int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev) |
619c5cb6 VZ |
10434 | { |
10435 | int pos; | |
10436 | u16 control; | |
10437 | ||
10438 | pos = pci_find_capability(pdev, PCI_CAP_ID_MSIX); | |
6383c0b3 AE |
10439 | |
10440 | /* | |
10441 | * If MSI-X is not supported - return number of SBs needed to support | |
10442 | * one fast path queue: one FP queue + SB for CNIC | |
10443 | */ | |
619c5cb6 | 10444 | if (!pos) |
6383c0b3 | 10445 | return 1 + CNIC_PRESENT; |
619c5cb6 | 10446 | |
6383c0b3 AE |
10447 | /* |
10448 | * The value in the PCI configuration space is the index of the last | |
10449 | * entry, namely one less than the actual size of the table, which is | |
10450 | * exactly what we want to return from this function: number of all SBs | |
10451 | * without the default SB. | |
10452 | */ | |
619c5cb6 | 10453 | pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &control); |
6383c0b3 | 10454 | return control & PCI_MSIX_FLAGS_QSIZE; |
619c5cb6 VZ |
10455 | } |
10456 | ||
a2fbb9ea ET |
10457 | static int __devinit bnx2x_init_one(struct pci_dev *pdev, |
10458 | const struct pci_device_id *ent) | |
10459 | { | |
a2fbb9ea ET |
10460 | struct net_device *dev = NULL; |
10461 | struct bnx2x *bp; | |
37f9ce62 | 10462 | int pcie_width, pcie_speed; |
6383c0b3 AE |
10463 | int rc, max_non_def_sbs; |
10464 | int rx_count, tx_count, rss_count; | |
10465 | /* | |
10466 | * An estimated maximum supported CoS number according to the chip | |
10467 | * version. | |
10468 | * We will try to roughly estimate the maximum number of CoSes this chip | |
10469 | * may support in order to minimize the memory allocated for Tx | |
10470 | * netdev_queue's. This number will be accurately calculated during the | |
10471 | * initialization of bp->max_cos based on the chip versions AND chip | |
10472 | * revision in the bnx2x_init_bp(). | |
10473 | */ | |
10474 | u8 max_cos_est = 0; | |
523224a3 | 10475 | |
f2e0899f DK |
10476 | switch (ent->driver_data) { |
10477 | case BCM57710: | |
10478 | case BCM57711: | |
10479 | case BCM57711E: | |
6383c0b3 AE |
10480 | max_cos_est = BNX2X_MULTI_TX_COS_E1X; |
10481 | break; | |
10482 | ||
f2e0899f | 10483 | case BCM57712: |
619c5cb6 | 10484 | case BCM57712_MF: |
6383c0b3 AE |
10485 | max_cos_est = BNX2X_MULTI_TX_COS_E2_E3A0; |
10486 | break; | |
10487 | ||
619c5cb6 VZ |
10488 | case BCM57800: |
10489 | case BCM57800_MF: | |
10490 | case BCM57810: | |
10491 | case BCM57810_MF: | |
10492 | case BCM57840: | |
10493 | case BCM57840_MF: | |
6383c0b3 | 10494 | max_cos_est = BNX2X_MULTI_TX_COS_E3B0; |
f2e0899f | 10495 | break; |
a2fbb9ea | 10496 | |
f2e0899f DK |
10497 | default: |
10498 | pr_err("Unknown board_type (%ld), aborting\n", | |
10499 | ent->driver_data); | |
870634b0 | 10500 | return -ENODEV; |
f2e0899f DK |
10501 | } |
10502 | ||
6383c0b3 AE |
10503 | max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev); |
10504 | ||
10505 | /* !!! FIXME !!! | |
10506 | * Do not allow the maximum SB count to grow above 16 | |
10507 | * since Special CIDs starts from 16*BNX2X_MULTI_TX_COS=48. | |
10508 | * We will use the FP_SB_MAX_E1x macro for this matter. | |
10509 | */ | |
10510 | max_non_def_sbs = min_t(int, FP_SB_MAX_E1x, max_non_def_sbs); | |
10511 | ||
10512 | WARN_ON(!max_non_def_sbs); | |
10513 | ||
10514 | /* Maximum number of RSS queues: one IGU SB goes to CNIC */ | |
10515 | rss_count = max_non_def_sbs - CNIC_PRESENT; | |
10516 | ||
10517 | /* Maximum number of netdev Rx queues: RSS + FCoE L2 */ | |
10518 | rx_count = rss_count + FCOE_PRESENT; | |
10519 | ||
10520 | /* | |
10521 | * Maximum number of netdev Tx queues: | |
10522 | * Maximum TSS queues * Maximum supported number of CoS + FCoE L2 | |
10523 | */ | |
10524 | tx_count = MAX_TXQS_PER_COS * max_cos_est + FCOE_PRESENT; | |
f85582f8 | 10525 | |
a2fbb9ea | 10526 | /* dev zeroed in init_etherdev */ |
6383c0b3 | 10527 | dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count); |
34f80b04 | 10528 | if (!dev) { |
cdaa7cb8 | 10529 | dev_err(&pdev->dev, "Cannot allocate net device\n"); |
a2fbb9ea | 10530 | return -ENOMEM; |
34f80b04 | 10531 | } |
a2fbb9ea | 10532 | |
a2fbb9ea | 10533 | bp = netdev_priv(dev); |
a2fbb9ea | 10534 | |
6383c0b3 AE |
10535 | DP(NETIF_MSG_DRV, "Allocated netdev with %d tx and %d rx queues\n", |
10536 | tx_count, rx_count); | |
df4770de | 10537 | |
6383c0b3 AE |
10538 | bp->igu_sb_cnt = max_non_def_sbs; |
10539 | bp->msg_enable = debug; | |
10540 | pci_set_drvdata(pdev, dev); | |
523224a3 | 10541 | |
619c5cb6 | 10542 | rc = bnx2x_init_dev(pdev, dev, ent->driver_data); |
a2fbb9ea ET |
10543 | if (rc < 0) { |
10544 | free_netdev(dev); | |
10545 | return rc; | |
10546 | } | |
10547 | ||
6383c0b3 | 10548 | DP(NETIF_MSG_DRV, "max_non_def_sbs %d", max_non_def_sbs); |
619c5cb6 | 10549 | |
34f80b04 | 10550 | rc = bnx2x_init_bp(bp); |
693fc0d1 EG |
10551 | if (rc) |
10552 | goto init_one_exit; | |
10553 | ||
6383c0b3 AE |
10554 | /* |
10555 | * Map doorbels here as we need the real value of bp->max_cos which | |
10556 | * is initialized in bnx2x_init_bp(). | |
10557 | */ | |
10558 | bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2), | |
10559 | min_t(u64, BNX2X_DB_SIZE(bp), | |
10560 | pci_resource_len(pdev, 2))); | |
10561 | if (!bp->doorbells) { | |
10562 | dev_err(&bp->pdev->dev, | |
10563 | "Cannot map doorbell space, aborting\n"); | |
10564 | rc = -ENOMEM; | |
10565 | goto init_one_exit; | |
10566 | } | |
10567 | ||
523224a3 | 10568 | /* calc qm_cid_count */ |
6383c0b3 | 10569 | bp->qm_cid_count = bnx2x_set_qm_cid_count(bp); |
523224a3 | 10570 | |
ec6ba945 VZ |
10571 | #ifdef BCM_CNIC |
10572 | /* disable FCOE L2 queue for E1x*/ | |
10573 | if (CHIP_IS_E1x(bp)) | |
10574 | bp->flags |= NO_FCOE_FLAG; | |
10575 | ||
10576 | #endif | |
10577 | ||
25985edc | 10578 | /* Configure interrupt mode: try to enable MSI-X/MSI if |
d6214d7a DK |
10579 | * needed, set bp->num_queues appropriately. |
10580 | */ | |
10581 | bnx2x_set_int_mode(bp); | |
10582 | ||
10583 | /* Add all NAPI objects */ | |
10584 | bnx2x_add_all_napi(bp); | |
10585 | ||
b340007f VZ |
10586 | rc = register_netdev(dev); |
10587 | if (rc) { | |
10588 | dev_err(&pdev->dev, "Cannot register net device\n"); | |
10589 | goto init_one_exit; | |
10590 | } | |
10591 | ||
ec6ba945 VZ |
10592 | #ifdef BCM_CNIC |
10593 | if (!NO_FCOE(bp)) { | |
10594 | /* Add storage MAC address */ | |
10595 | rtnl_lock(); | |
10596 | dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN); | |
10597 | rtnl_unlock(); | |
10598 | } | |
10599 | #endif | |
10600 | ||
37f9ce62 | 10601 | bnx2x_get_pcie_width_speed(bp, &pcie_width, &pcie_speed); |
d6214d7a | 10602 | |
cdaa7cb8 VZ |
10603 | netdev_info(dev, "%s (%c%d) PCI-E x%d %s found at mem %lx," |
10604 | " IRQ %d, ", board_info[ent->driver_data].name, | |
10605 | (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4), | |
f2e0899f DK |
10606 | pcie_width, |
10607 | ((!CHIP_IS_E2(bp) && pcie_speed == 2) || | |
10608 | (CHIP_IS_E2(bp) && pcie_speed == 1)) ? | |
10609 | "5GHz (Gen2)" : "2.5GHz", | |
cdaa7cb8 VZ |
10610 | dev->base_addr, bp->pdev->irq); |
10611 | pr_cont("node addr %pM\n", dev->dev_addr); | |
c016201c | 10612 | |
a2fbb9ea | 10613 | return 0; |
34f80b04 EG |
10614 | |
10615 | init_one_exit: | |
10616 | if (bp->regview) | |
10617 | iounmap(bp->regview); | |
10618 | ||
10619 | if (bp->doorbells) | |
10620 | iounmap(bp->doorbells); | |
10621 | ||
10622 | free_netdev(dev); | |
10623 | ||
10624 | if (atomic_read(&pdev->enable_cnt) == 1) | |
10625 | pci_release_regions(pdev); | |
10626 | ||
10627 | pci_disable_device(pdev); | |
10628 | pci_set_drvdata(pdev, NULL); | |
10629 | ||
10630 | return rc; | |
a2fbb9ea ET |
10631 | } |
10632 | ||
10633 | static void __devexit bnx2x_remove_one(struct pci_dev *pdev) | |
10634 | { | |
10635 | struct net_device *dev = pci_get_drvdata(pdev); | |
228241eb ET |
10636 | struct bnx2x *bp; |
10637 | ||
10638 | if (!dev) { | |
cdaa7cb8 | 10639 | dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n"); |
228241eb ET |
10640 | return; |
10641 | } | |
228241eb | 10642 | bp = netdev_priv(dev); |
a2fbb9ea | 10643 | |
ec6ba945 VZ |
10644 | #ifdef BCM_CNIC |
10645 | /* Delete storage MAC address */ | |
10646 | if (!NO_FCOE(bp)) { | |
10647 | rtnl_lock(); | |
10648 | dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN); | |
10649 | rtnl_unlock(); | |
10650 | } | |
10651 | #endif | |
10652 | ||
98507672 SR |
10653 | #ifdef BCM_DCBNL |
10654 | /* Delete app tlvs from dcbnl */ | |
10655 | bnx2x_dcbnl_update_applist(bp, true); | |
10656 | #endif | |
10657 | ||
a2fbb9ea ET |
10658 | unregister_netdev(dev); |
10659 | ||
d6214d7a DK |
10660 | /* Delete all NAPI objects */ |
10661 | bnx2x_del_all_napi(bp); | |
10662 | ||
084d6cbb VZ |
10663 | /* Power on: we can't let PCI layer write to us while we are in D3 */ |
10664 | bnx2x_set_power_state(bp, PCI_D0); | |
10665 | ||
d6214d7a DK |
10666 | /* Disable MSI/MSI-X */ |
10667 | bnx2x_disable_msi(bp); | |
f85582f8 | 10668 | |
084d6cbb VZ |
10669 | /* Power off */ |
10670 | bnx2x_set_power_state(bp, PCI_D3hot); | |
10671 | ||
72fd0718 | 10672 | /* Make sure RESET task is not scheduled before continuing */ |
7be08a72 | 10673 | cancel_delayed_work_sync(&bp->sp_rtnl_task); |
72fd0718 | 10674 | |
a2fbb9ea ET |
10675 | if (bp->regview) |
10676 | iounmap(bp->regview); | |
10677 | ||
10678 | if (bp->doorbells) | |
10679 | iounmap(bp->doorbells); | |
10680 | ||
523224a3 DK |
10681 | bnx2x_free_mem_bp(bp); |
10682 | ||
a2fbb9ea | 10683 | free_netdev(dev); |
34f80b04 EG |
10684 | |
10685 | if (atomic_read(&pdev->enable_cnt) == 1) | |
10686 | pci_release_regions(pdev); | |
10687 | ||
a2fbb9ea ET |
10688 | pci_disable_device(pdev); |
10689 | pci_set_drvdata(pdev, NULL); | |
10690 | } | |
10691 | ||
f8ef6e44 YG |
10692 | static int bnx2x_eeh_nic_unload(struct bnx2x *bp) |
10693 | { | |
10694 | int i; | |
10695 | ||
10696 | bp->state = BNX2X_STATE_ERROR; | |
10697 | ||
10698 | bp->rx_mode = BNX2X_RX_MODE_NONE; | |
10699 | ||
619c5cb6 VZ |
10700 | #ifdef BCM_CNIC |
10701 | bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD); | |
10702 | #endif | |
10703 | /* Stop Tx */ | |
10704 | bnx2x_tx_disable(bp); | |
10705 | ||
f8ef6e44 YG |
10706 | bnx2x_netif_stop(bp, 0); |
10707 | ||
10708 | del_timer_sync(&bp->timer); | |
619c5cb6 VZ |
10709 | |
10710 | bnx2x_stats_handle(bp, STATS_EVENT_STOP); | |
f8ef6e44 YG |
10711 | |
10712 | /* Release IRQs */ | |
d6214d7a | 10713 | bnx2x_free_irq(bp); |
f8ef6e44 | 10714 | |
f8ef6e44 YG |
10715 | /* Free SKBs, SGEs, TPA pool and driver internals */ |
10716 | bnx2x_free_skbs(bp); | |
523224a3 | 10717 | |
ec6ba945 | 10718 | for_each_rx_queue(bp, i) |
f8ef6e44 | 10719 | bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE); |
d6214d7a | 10720 | |
f8ef6e44 YG |
10721 | bnx2x_free_mem(bp); |
10722 | ||
10723 | bp->state = BNX2X_STATE_CLOSED; | |
10724 | ||
619c5cb6 VZ |
10725 | netif_carrier_off(bp->dev); |
10726 | ||
f8ef6e44 YG |
10727 | return 0; |
10728 | } | |
10729 | ||
10730 | static void bnx2x_eeh_recover(struct bnx2x *bp) | |
10731 | { | |
10732 | u32 val; | |
10733 | ||
10734 | mutex_init(&bp->port.phy_mutex); | |
10735 | ||
10736 | bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR); | |
10737 | bp->link_params.shmem_base = bp->common.shmem_base; | |
10738 | BNX2X_DEV_INFO("shmem offset is 0x%x\n", bp->common.shmem_base); | |
10739 | ||
10740 | if (!bp->common.shmem_base || | |
10741 | (bp->common.shmem_base < 0xA0000) || | |
10742 | (bp->common.shmem_base >= 0xC0000)) { | |
10743 | BNX2X_DEV_INFO("MCP not active\n"); | |
10744 | bp->flags |= NO_MCP_FLAG; | |
10745 | return; | |
10746 | } | |
10747 | ||
10748 | val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]); | |
10749 | if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) | |
10750 | != (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) | |
10751 | BNX2X_ERR("BAD MCP validity signature\n"); | |
10752 | ||
10753 | if (!BP_NOMCP(bp)) { | |
f2e0899f DK |
10754 | bp->fw_seq = |
10755 | (SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) & | |
10756 | DRV_MSG_SEQ_NUMBER_MASK); | |
f8ef6e44 YG |
10757 | BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq); |
10758 | } | |
10759 | } | |
10760 | ||
493adb1f WX |
10761 | /** |
10762 | * bnx2x_io_error_detected - called when PCI error is detected | |
10763 | * @pdev: Pointer to PCI device | |
10764 | * @state: The current pci connection state | |
10765 | * | |
10766 | * This function is called after a PCI bus error affecting | |
10767 | * this device has been detected. | |
10768 | */ | |
10769 | static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev, | |
10770 | pci_channel_state_t state) | |
10771 | { | |
10772 | struct net_device *dev = pci_get_drvdata(pdev); | |
10773 | struct bnx2x *bp = netdev_priv(dev); | |
10774 | ||
10775 | rtnl_lock(); | |
10776 | ||
10777 | netif_device_detach(dev); | |
10778 | ||
07ce50e4 DN |
10779 | if (state == pci_channel_io_perm_failure) { |
10780 | rtnl_unlock(); | |
10781 | return PCI_ERS_RESULT_DISCONNECT; | |
10782 | } | |
10783 | ||
493adb1f | 10784 | if (netif_running(dev)) |
f8ef6e44 | 10785 | bnx2x_eeh_nic_unload(bp); |
493adb1f WX |
10786 | |
10787 | pci_disable_device(pdev); | |
10788 | ||
10789 | rtnl_unlock(); | |
10790 | ||
10791 | /* Request a slot reset */ | |
10792 | return PCI_ERS_RESULT_NEED_RESET; | |
10793 | } | |
10794 | ||
10795 | /** | |
10796 | * bnx2x_io_slot_reset - called after the PCI bus has been reset | |
10797 | * @pdev: Pointer to PCI device | |
10798 | * | |
10799 | * Restart the card from scratch, as if from a cold-boot. | |
10800 | */ | |
10801 | static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev) | |
10802 | { | |
10803 | struct net_device *dev = pci_get_drvdata(pdev); | |
10804 | struct bnx2x *bp = netdev_priv(dev); | |
10805 | ||
10806 | rtnl_lock(); | |
10807 | ||
10808 | if (pci_enable_device(pdev)) { | |
10809 | dev_err(&pdev->dev, | |
10810 | "Cannot re-enable PCI device after reset\n"); | |
10811 | rtnl_unlock(); | |
10812 | return PCI_ERS_RESULT_DISCONNECT; | |
10813 | } | |
10814 | ||
10815 | pci_set_master(pdev); | |
10816 | pci_restore_state(pdev); | |
10817 | ||
10818 | if (netif_running(dev)) | |
10819 | bnx2x_set_power_state(bp, PCI_D0); | |
10820 | ||
10821 | rtnl_unlock(); | |
10822 | ||
10823 | return PCI_ERS_RESULT_RECOVERED; | |
10824 | } | |
10825 | ||
10826 | /** | |
10827 | * bnx2x_io_resume - called when traffic can start flowing again | |
10828 | * @pdev: Pointer to PCI device | |
10829 | * | |
10830 | * This callback is called when the error recovery driver tells us that | |
10831 | * its OK to resume normal operation. | |
10832 | */ | |
10833 | static void bnx2x_io_resume(struct pci_dev *pdev) | |
10834 | { | |
10835 | struct net_device *dev = pci_get_drvdata(pdev); | |
10836 | struct bnx2x *bp = netdev_priv(dev); | |
10837 | ||
72fd0718 | 10838 | if (bp->recovery_state != BNX2X_RECOVERY_DONE) { |
754a2f52 DK |
10839 | netdev_err(bp->dev, "Handling parity error recovery. " |
10840 | "Try again later\n"); | |
72fd0718 VZ |
10841 | return; |
10842 | } | |
10843 | ||
493adb1f WX |
10844 | rtnl_lock(); |
10845 | ||
f8ef6e44 YG |
10846 | bnx2x_eeh_recover(bp); |
10847 | ||
493adb1f | 10848 | if (netif_running(dev)) |
f8ef6e44 | 10849 | bnx2x_nic_load(bp, LOAD_NORMAL); |
493adb1f WX |
10850 | |
10851 | netif_device_attach(dev); | |
10852 | ||
10853 | rtnl_unlock(); | |
10854 | } | |
10855 | ||
10856 | static struct pci_error_handlers bnx2x_err_handler = { | |
10857 | .error_detected = bnx2x_io_error_detected, | |
356e2385 EG |
10858 | .slot_reset = bnx2x_io_slot_reset, |
10859 | .resume = bnx2x_io_resume, | |
493adb1f WX |
10860 | }; |
10861 | ||
a2fbb9ea | 10862 | static struct pci_driver bnx2x_pci_driver = { |
493adb1f WX |
10863 | .name = DRV_MODULE_NAME, |
10864 | .id_table = bnx2x_pci_tbl, | |
10865 | .probe = bnx2x_init_one, | |
10866 | .remove = __devexit_p(bnx2x_remove_one), | |
10867 | .suspend = bnx2x_suspend, | |
10868 | .resume = bnx2x_resume, | |
10869 | .err_handler = &bnx2x_err_handler, | |
a2fbb9ea ET |
10870 | }; |
10871 | ||
10872 | static int __init bnx2x_init(void) | |
10873 | { | |
dd21ca6d SG |
10874 | int ret; |
10875 | ||
7995c64e | 10876 | pr_info("%s", version); |
938cf541 | 10877 | |
1cf167f2 EG |
10878 | bnx2x_wq = create_singlethread_workqueue("bnx2x"); |
10879 | if (bnx2x_wq == NULL) { | |
7995c64e | 10880 | pr_err("Cannot create workqueue\n"); |
1cf167f2 EG |
10881 | return -ENOMEM; |
10882 | } | |
10883 | ||
dd21ca6d SG |
10884 | ret = pci_register_driver(&bnx2x_pci_driver); |
10885 | if (ret) { | |
7995c64e | 10886 | pr_err("Cannot register driver\n"); |
dd21ca6d SG |
10887 | destroy_workqueue(bnx2x_wq); |
10888 | } | |
10889 | return ret; | |
a2fbb9ea ET |
10890 | } |
10891 | ||
10892 | static void __exit bnx2x_cleanup(void) | |
10893 | { | |
10894 | pci_unregister_driver(&bnx2x_pci_driver); | |
1cf167f2 EG |
10895 | |
10896 | destroy_workqueue(bnx2x_wq); | |
a2fbb9ea ET |
10897 | } |
10898 | ||
3deb8167 YR |
10899 | void bnx2x_notify_link_changed(struct bnx2x *bp) |
10900 | { | |
10901 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1); | |
10902 | } | |
10903 | ||
a2fbb9ea ET |
10904 | module_init(bnx2x_init); |
10905 | module_exit(bnx2x_cleanup); | |
10906 | ||
993ac7b5 | 10907 | #ifdef BCM_CNIC |
619c5cb6 VZ |
10908 | /** |
10909 | * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s). | |
10910 | * | |
10911 | * @bp: driver handle | |
10912 | * @set: set or clear the CAM entry | |
10913 | * | |
10914 | * This function will wait until the ramdord completion returns. | |
10915 | * Return 0 if success, -ENODEV if ramrod doesn't return. | |
10916 | */ | |
10917 | static inline int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp) | |
10918 | { | |
10919 | unsigned long ramrod_flags = 0; | |
10920 | ||
10921 | __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); | |
10922 | return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac, | |
10923 | &bp->iscsi_l2_mac_obj, true, | |
10924 | BNX2X_ISCSI_ETH_MAC, &ramrod_flags); | |
10925 | } | |
993ac7b5 MC |
10926 | |
10927 | /* count denotes the number of new completions we have seen */ | |
10928 | static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count) | |
10929 | { | |
10930 | struct eth_spe *spe; | |
10931 | ||
10932 | #ifdef BNX2X_STOP_ON_ERROR | |
10933 | if (unlikely(bp->panic)) | |
10934 | return; | |
10935 | #endif | |
10936 | ||
10937 | spin_lock_bh(&bp->spq_lock); | |
c2bff63f | 10938 | BUG_ON(bp->cnic_spq_pending < count); |
993ac7b5 MC |
10939 | bp->cnic_spq_pending -= count; |
10940 | ||
993ac7b5 | 10941 | |
c2bff63f DK |
10942 | for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) { |
10943 | u16 type = (le16_to_cpu(bp->cnic_kwq_cons->hdr.type) | |
10944 | & SPE_HDR_CONN_TYPE) >> | |
10945 | SPE_HDR_CONN_TYPE_SHIFT; | |
619c5cb6 VZ |
10946 | u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data) |
10947 | >> SPE_HDR_CMD_ID_SHIFT) & 0xff; | |
c2bff63f DK |
10948 | |
10949 | /* Set validation for iSCSI L2 client before sending SETUP | |
10950 | * ramrod | |
10951 | */ | |
10952 | if (type == ETH_CONNECTION_TYPE) { | |
c2bff63f | 10953 | if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP) |
619c5cb6 VZ |
10954 | bnx2x_set_ctx_validation(bp, &bp->context. |
10955 | vcxt[BNX2X_ISCSI_ETH_CID].eth, | |
10956 | BNX2X_ISCSI_ETH_CID); | |
c2bff63f DK |
10957 | } |
10958 | ||
619c5cb6 VZ |
10959 | /* |
10960 | * There may be not more than 8 L2, not more than 8 L5 SPEs | |
10961 | * and in the air. We also check that number of outstanding | |
6e30dd4e VZ |
10962 | * COMMON ramrods is not more than the EQ and SPQ can |
10963 | * accommodate. | |
c2bff63f | 10964 | */ |
6e30dd4e VZ |
10965 | if (type == ETH_CONNECTION_TYPE) { |
10966 | if (!atomic_read(&bp->cq_spq_left)) | |
10967 | break; | |
10968 | else | |
10969 | atomic_dec(&bp->cq_spq_left); | |
10970 | } else if (type == NONE_CONNECTION_TYPE) { | |
10971 | if (!atomic_read(&bp->eq_spq_left)) | |
c2bff63f DK |
10972 | break; |
10973 | else | |
6e30dd4e | 10974 | atomic_dec(&bp->eq_spq_left); |
ec6ba945 VZ |
10975 | } else if ((type == ISCSI_CONNECTION_TYPE) || |
10976 | (type == FCOE_CONNECTION_TYPE)) { | |
c2bff63f DK |
10977 | if (bp->cnic_spq_pending >= |
10978 | bp->cnic_eth_dev.max_kwqe_pending) | |
10979 | break; | |
10980 | else | |
10981 | bp->cnic_spq_pending++; | |
10982 | } else { | |
10983 | BNX2X_ERR("Unknown SPE type: %d\n", type); | |
10984 | bnx2x_panic(); | |
993ac7b5 | 10985 | break; |
c2bff63f | 10986 | } |
993ac7b5 MC |
10987 | |
10988 | spe = bnx2x_sp_get_next(bp); | |
10989 | *spe = *bp->cnic_kwq_cons; | |
10990 | ||
993ac7b5 MC |
10991 | DP(NETIF_MSG_TIMER, "pending on SPQ %d, on KWQ %d count %d\n", |
10992 | bp->cnic_spq_pending, bp->cnic_kwq_pending, count); | |
10993 | ||
10994 | if (bp->cnic_kwq_cons == bp->cnic_kwq_last) | |
10995 | bp->cnic_kwq_cons = bp->cnic_kwq; | |
10996 | else | |
10997 | bp->cnic_kwq_cons++; | |
10998 | } | |
10999 | bnx2x_sp_prod_update(bp); | |
11000 | spin_unlock_bh(&bp->spq_lock); | |
11001 | } | |
11002 | ||
11003 | static int bnx2x_cnic_sp_queue(struct net_device *dev, | |
11004 | struct kwqe_16 *kwqes[], u32 count) | |
11005 | { | |
11006 | struct bnx2x *bp = netdev_priv(dev); | |
11007 | int i; | |
11008 | ||
11009 | #ifdef BNX2X_STOP_ON_ERROR | |
11010 | if (unlikely(bp->panic)) | |
11011 | return -EIO; | |
11012 | #endif | |
11013 | ||
11014 | spin_lock_bh(&bp->spq_lock); | |
11015 | ||
11016 | for (i = 0; i < count; i++) { | |
11017 | struct eth_spe *spe = (struct eth_spe *)kwqes[i]; | |
11018 | ||
11019 | if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT) | |
11020 | break; | |
11021 | ||
11022 | *bp->cnic_kwq_prod = *spe; | |
11023 | ||
11024 | bp->cnic_kwq_pending++; | |
11025 | ||
11026 | DP(NETIF_MSG_TIMER, "L5 SPQE %x %x %x:%x pos %d\n", | |
11027 | spe->hdr.conn_and_cmd_data, spe->hdr.type, | |
523224a3 DK |
11028 | spe->data.update_data_addr.hi, |
11029 | spe->data.update_data_addr.lo, | |
993ac7b5 MC |
11030 | bp->cnic_kwq_pending); |
11031 | ||
11032 | if (bp->cnic_kwq_prod == bp->cnic_kwq_last) | |
11033 | bp->cnic_kwq_prod = bp->cnic_kwq; | |
11034 | else | |
11035 | bp->cnic_kwq_prod++; | |
11036 | } | |
11037 | ||
11038 | spin_unlock_bh(&bp->spq_lock); | |
11039 | ||
11040 | if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending) | |
11041 | bnx2x_cnic_sp_post(bp, 0); | |
11042 | ||
11043 | return i; | |
11044 | } | |
11045 | ||
11046 | static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl) | |
11047 | { | |
11048 | struct cnic_ops *c_ops; | |
11049 | int rc = 0; | |
11050 | ||
11051 | mutex_lock(&bp->cnic_mutex); | |
13707f9e ED |
11052 | c_ops = rcu_dereference_protected(bp->cnic_ops, |
11053 | lockdep_is_held(&bp->cnic_mutex)); | |
993ac7b5 MC |
11054 | if (c_ops) |
11055 | rc = c_ops->cnic_ctl(bp->cnic_data, ctl); | |
11056 | mutex_unlock(&bp->cnic_mutex); | |
11057 | ||
11058 | return rc; | |
11059 | } | |
11060 | ||
11061 | static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl) | |
11062 | { | |
11063 | struct cnic_ops *c_ops; | |
11064 | int rc = 0; | |
11065 | ||
11066 | rcu_read_lock(); | |
11067 | c_ops = rcu_dereference(bp->cnic_ops); | |
11068 | if (c_ops) | |
11069 | rc = c_ops->cnic_ctl(bp->cnic_data, ctl); | |
11070 | rcu_read_unlock(); | |
11071 | ||
11072 | return rc; | |
11073 | } | |
11074 | ||
11075 | /* | |
11076 | * for commands that have no data | |
11077 | */ | |
9f6c9258 | 11078 | int bnx2x_cnic_notify(struct bnx2x *bp, int cmd) |
993ac7b5 MC |
11079 | { |
11080 | struct cnic_ctl_info ctl = {0}; | |
11081 | ||
11082 | ctl.cmd = cmd; | |
11083 | ||
11084 | return bnx2x_cnic_ctl_send(bp, &ctl); | |
11085 | } | |
11086 | ||
619c5cb6 | 11087 | static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err) |
993ac7b5 | 11088 | { |
619c5cb6 | 11089 | struct cnic_ctl_info ctl = {0}; |
993ac7b5 MC |
11090 | |
11091 | /* first we tell CNIC and only then we count this as a completion */ | |
11092 | ctl.cmd = CNIC_CTL_COMPLETION_CMD; | |
11093 | ctl.data.comp.cid = cid; | |
619c5cb6 | 11094 | ctl.data.comp.error = err; |
993ac7b5 MC |
11095 | |
11096 | bnx2x_cnic_ctl_send_bh(bp, &ctl); | |
c2bff63f | 11097 | bnx2x_cnic_sp_post(bp, 0); |
993ac7b5 MC |
11098 | } |
11099 | ||
619c5cb6 VZ |
11100 | |
11101 | /* Called with netif_addr_lock_bh() taken. | |
11102 | * Sets an rx_mode config for an iSCSI ETH client. | |
11103 | * Doesn't block. | |
11104 | * Completion should be checked outside. | |
11105 | */ | |
11106 | static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start) | |
11107 | { | |
11108 | unsigned long accept_flags = 0, ramrod_flags = 0; | |
11109 | u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX); | |
11110 | int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED; | |
11111 | ||
11112 | if (start) { | |
11113 | /* Start accepting on iSCSI L2 ring. Accept all multicasts | |
11114 | * because it's the only way for UIO Queue to accept | |
11115 | * multicasts (in non-promiscuous mode only one Queue per | |
11116 | * function will receive multicast packets (leading in our | |
11117 | * case). | |
11118 | */ | |
11119 | __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags); | |
11120 | __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags); | |
11121 | __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags); | |
11122 | __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags); | |
11123 | ||
11124 | /* Clear STOP_PENDING bit if START is requested */ | |
11125 | clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state); | |
11126 | ||
11127 | sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED; | |
11128 | } else | |
11129 | /* Clear START_PENDING bit if STOP is requested */ | |
11130 | clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state); | |
11131 | ||
11132 | if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) | |
11133 | set_bit(sched_state, &bp->sp_state); | |
11134 | else { | |
11135 | __set_bit(RAMROD_RX, &ramrod_flags); | |
11136 | bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0, | |
11137 | ramrod_flags); | |
11138 | } | |
11139 | } | |
11140 | ||
11141 | ||
993ac7b5 MC |
11142 | static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl) |
11143 | { | |
11144 | struct bnx2x *bp = netdev_priv(dev); | |
11145 | int rc = 0; | |
11146 | ||
11147 | switch (ctl->cmd) { | |
11148 | case DRV_CTL_CTXTBL_WR_CMD: { | |
11149 | u32 index = ctl->data.io.offset; | |
11150 | dma_addr_t addr = ctl->data.io.dma_addr; | |
11151 | ||
11152 | bnx2x_ilt_wr(bp, index, addr); | |
11153 | break; | |
11154 | } | |
11155 | ||
c2bff63f DK |
11156 | case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: { |
11157 | int count = ctl->data.credit.credit_count; | |
993ac7b5 MC |
11158 | |
11159 | bnx2x_cnic_sp_post(bp, count); | |
11160 | break; | |
11161 | } | |
11162 | ||
11163 | /* rtnl_lock is held. */ | |
11164 | case DRV_CTL_START_L2_CMD: { | |
619c5cb6 VZ |
11165 | struct cnic_eth_dev *cp = &bp->cnic_eth_dev; |
11166 | unsigned long sp_bits = 0; | |
11167 | ||
11168 | /* Configure the iSCSI classification object */ | |
11169 | bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj, | |
11170 | cp->iscsi_l2_client_id, | |
11171 | cp->iscsi_l2_cid, BP_FUNC(bp), | |
11172 | bnx2x_sp(bp, mac_rdata), | |
11173 | bnx2x_sp_mapping(bp, mac_rdata), | |
11174 | BNX2X_FILTER_MAC_PENDING, | |
11175 | &bp->sp_state, BNX2X_OBJ_TYPE_RX, | |
11176 | &bp->macs_pool); | |
ec6ba945 | 11177 | |
523224a3 | 11178 | /* Set iSCSI MAC address */ |
619c5cb6 VZ |
11179 | rc = bnx2x_set_iscsi_eth_mac_addr(bp); |
11180 | if (rc) | |
11181 | break; | |
523224a3 DK |
11182 | |
11183 | mmiowb(); | |
11184 | barrier(); | |
11185 | ||
619c5cb6 VZ |
11186 | /* Start accepting on iSCSI L2 ring */ |
11187 | ||
11188 | netif_addr_lock_bh(dev); | |
11189 | bnx2x_set_iscsi_eth_rx_mode(bp, true); | |
11190 | netif_addr_unlock_bh(dev); | |
11191 | ||
11192 | /* bits to wait on */ | |
11193 | __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits); | |
11194 | __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits); | |
11195 | ||
11196 | if (!bnx2x_wait_sp_comp(bp, sp_bits)) | |
11197 | BNX2X_ERR("rx_mode completion timed out!\n"); | |
523224a3 | 11198 | |
993ac7b5 MC |
11199 | break; |
11200 | } | |
11201 | ||
11202 | /* rtnl_lock is held. */ | |
11203 | case DRV_CTL_STOP_L2_CMD: { | |
619c5cb6 | 11204 | unsigned long sp_bits = 0; |
993ac7b5 | 11205 | |
523224a3 | 11206 | /* Stop accepting on iSCSI L2 ring */ |
619c5cb6 VZ |
11207 | netif_addr_lock_bh(dev); |
11208 | bnx2x_set_iscsi_eth_rx_mode(bp, false); | |
11209 | netif_addr_unlock_bh(dev); | |
11210 | ||
11211 | /* bits to wait on */ | |
11212 | __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits); | |
11213 | __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits); | |
11214 | ||
11215 | if (!bnx2x_wait_sp_comp(bp, sp_bits)) | |
11216 | BNX2X_ERR("rx_mode completion timed out!\n"); | |
523224a3 DK |
11217 | |
11218 | mmiowb(); | |
11219 | barrier(); | |
11220 | ||
11221 | /* Unset iSCSI L2 MAC */ | |
619c5cb6 VZ |
11222 | rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj, |
11223 | BNX2X_ISCSI_ETH_MAC, true); | |
993ac7b5 MC |
11224 | break; |
11225 | } | |
c2bff63f DK |
11226 | case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: { |
11227 | int count = ctl->data.credit.credit_count; | |
11228 | ||
11229 | smp_mb__before_atomic_inc(); | |
6e30dd4e | 11230 | atomic_add(count, &bp->cq_spq_left); |
c2bff63f DK |
11231 | smp_mb__after_atomic_inc(); |
11232 | break; | |
11233 | } | |
993ac7b5 MC |
11234 | |
11235 | default: | |
11236 | BNX2X_ERR("unknown command %x\n", ctl->cmd); | |
11237 | rc = -EINVAL; | |
11238 | } | |
11239 | ||
11240 | return rc; | |
11241 | } | |
11242 | ||
9f6c9258 | 11243 | void bnx2x_setup_cnic_irq_info(struct bnx2x *bp) |
993ac7b5 MC |
11244 | { |
11245 | struct cnic_eth_dev *cp = &bp->cnic_eth_dev; | |
11246 | ||
11247 | if (bp->flags & USING_MSIX_FLAG) { | |
11248 | cp->drv_state |= CNIC_DRV_STATE_USING_MSIX; | |
11249 | cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX; | |
11250 | cp->irq_arr[0].vector = bp->msix_table[1].vector; | |
11251 | } else { | |
11252 | cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX; | |
11253 | cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX; | |
11254 | } | |
619c5cb6 | 11255 | if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
11256 | cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb; |
11257 | else | |
11258 | cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb; | |
11259 | ||
619c5cb6 VZ |
11260 | cp->irq_arr[0].status_blk_num = bnx2x_cnic_fw_sb_id(bp); |
11261 | cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp); | |
993ac7b5 MC |
11262 | cp->irq_arr[1].status_blk = bp->def_status_blk; |
11263 | cp->irq_arr[1].status_blk_num = DEF_SB_ID; | |
523224a3 | 11264 | cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID; |
993ac7b5 MC |
11265 | |
11266 | cp->num_irq = 2; | |
11267 | } | |
11268 | ||
11269 | static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops, | |
11270 | void *data) | |
11271 | { | |
11272 | struct bnx2x *bp = netdev_priv(dev); | |
11273 | struct cnic_eth_dev *cp = &bp->cnic_eth_dev; | |
11274 | ||
11275 | if (ops == NULL) | |
11276 | return -EINVAL; | |
11277 | ||
993ac7b5 MC |
11278 | bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL); |
11279 | if (!bp->cnic_kwq) | |
11280 | return -ENOMEM; | |
11281 | ||
11282 | bp->cnic_kwq_cons = bp->cnic_kwq; | |
11283 | bp->cnic_kwq_prod = bp->cnic_kwq; | |
11284 | bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT; | |
11285 | ||
11286 | bp->cnic_spq_pending = 0; | |
11287 | bp->cnic_kwq_pending = 0; | |
11288 | ||
11289 | bp->cnic_data = data; | |
11290 | ||
11291 | cp->num_irq = 0; | |
619c5cb6 | 11292 | cp->drv_state |= CNIC_DRV_STATE_REGD; |
523224a3 | 11293 | cp->iro_arr = bp->iro_arr; |
993ac7b5 | 11294 | |
993ac7b5 | 11295 | bnx2x_setup_cnic_irq_info(bp); |
c2bff63f | 11296 | |
993ac7b5 MC |
11297 | rcu_assign_pointer(bp->cnic_ops, ops); |
11298 | ||
11299 | return 0; | |
11300 | } | |
11301 | ||
11302 | static int bnx2x_unregister_cnic(struct net_device *dev) | |
11303 | { | |
11304 | struct bnx2x *bp = netdev_priv(dev); | |
11305 | struct cnic_eth_dev *cp = &bp->cnic_eth_dev; | |
11306 | ||
11307 | mutex_lock(&bp->cnic_mutex); | |
993ac7b5 MC |
11308 | cp->drv_state = 0; |
11309 | rcu_assign_pointer(bp->cnic_ops, NULL); | |
11310 | mutex_unlock(&bp->cnic_mutex); | |
11311 | synchronize_rcu(); | |
11312 | kfree(bp->cnic_kwq); | |
11313 | bp->cnic_kwq = NULL; | |
11314 | ||
11315 | return 0; | |
11316 | } | |
11317 | ||
11318 | struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev) | |
11319 | { | |
11320 | struct bnx2x *bp = netdev_priv(dev); | |
11321 | struct cnic_eth_dev *cp = &bp->cnic_eth_dev; | |
11322 | ||
2ba45142 VZ |
11323 | /* If both iSCSI and FCoE are disabled - return NULL in |
11324 | * order to indicate CNIC that it should not try to work | |
11325 | * with this device. | |
11326 | */ | |
11327 | if (NO_ISCSI(bp) && NO_FCOE(bp)) | |
11328 | return NULL; | |
11329 | ||
993ac7b5 MC |
11330 | cp->drv_owner = THIS_MODULE; |
11331 | cp->chip_id = CHIP_ID(bp); | |
11332 | cp->pdev = bp->pdev; | |
11333 | cp->io_base = bp->regview; | |
11334 | cp->io_base2 = bp->doorbells; | |
11335 | cp->max_kwqe_pending = 8; | |
523224a3 | 11336 | cp->ctx_blk_size = CDU_ILT_PAGE_SZ; |
c2bff63f DK |
11337 | cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) + |
11338 | bnx2x_cid_ilt_lines(bp); | |
993ac7b5 | 11339 | cp->ctx_tbl_len = CNIC_ILT_LINES; |
c2bff63f | 11340 | cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS; |
993ac7b5 MC |
11341 | cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue; |
11342 | cp->drv_ctl = bnx2x_drv_ctl; | |
11343 | cp->drv_register_cnic = bnx2x_register_cnic; | |
11344 | cp->drv_unregister_cnic = bnx2x_unregister_cnic; | |
ec6ba945 | 11345 | cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID; |
619c5cb6 VZ |
11346 | cp->iscsi_l2_client_id = |
11347 | bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX); | |
c2bff63f DK |
11348 | cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID; |
11349 | ||
2ba45142 VZ |
11350 | if (NO_ISCSI_OOO(bp)) |
11351 | cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO; | |
11352 | ||
11353 | if (NO_ISCSI(bp)) | |
11354 | cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI; | |
11355 | ||
11356 | if (NO_FCOE(bp)) | |
11357 | cp->drv_state |= CNIC_DRV_STATE_NO_FCOE; | |
11358 | ||
c2bff63f DK |
11359 | DP(BNX2X_MSG_SP, "page_size %d, tbl_offset %d, tbl_lines %d, " |
11360 | "starting cid %d\n", | |
11361 | cp->ctx_blk_size, | |
11362 | cp->ctx_tbl_offset, | |
11363 | cp->ctx_tbl_len, | |
11364 | cp->starting_cid); | |
993ac7b5 MC |
11365 | return cp; |
11366 | } | |
11367 | EXPORT_SYMBOL(bnx2x_cnic_probe); | |
11368 | ||
11369 | #endif /* BCM_CNIC */ | |
94a78b79 | 11370 |