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bnx2x: Multiple concurrent l2 traffic classes
[deliverable/linux.git] / drivers / net / bnx2x / bnx2x_main.c
CommitLineData
34f80b04 1/* bnx2x_main.c: Broadcom Everest network driver.
a2fbb9ea 2 *
5de92408 3 * Copyright (c) 2007-2011 Broadcom Corporation
a2fbb9ea
ET		 4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
24e3fcef
EG		 9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
a2fbb9ea
ET		 11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
ca00392c 13 * Slowpath and fastpath rework by Vladislav Zolotarov
c14423fe 14 * Statistics and Link management by Yitchak Gertner
a2fbb9ea
ET		 15 *
16 */
17
a2fbb9ea
ET		 18#include <linux/module.h>
19#include <linux/moduleparam.h>
20#include <linux/kernel.h>
21#include <linux/device.h> /* for dev_info() */
22#include <linux/timer.h>
23#include <linux/errno.h>
24#include <linux/ioport.h>
25#include <linux/slab.h>
a2fbb9ea
ET		 26#include <linux/interrupt.h>
27#include <linux/pci.h>
28#include <linux/init.h>
29#include <linux/netdevice.h>
30#include <linux/etherdevice.h>
31#include <linux/skbuff.h>
32#include <linux/dma-mapping.h>
33#include <linux/bitops.h>
34#include <linux/irq.h>
35#include <linux/delay.h>
36#include <asm/byteorder.h>
37#include <linux/time.h>
38#include <linux/ethtool.h>
39#include <linux/mii.h>
0c6671b0 40#include <linux/if_vlan.h>
a2fbb9ea 41#include <net/ip.h>
619c5cb6 42#include <net/ipv6.h>
a2fbb9ea
ET		 43#include <net/tcp.h>
44#include <net/checksum.h>
34f80b04 45#include <net/ip6_checksum.h>
a2fbb9ea
ET		 46#include <linux/workqueue.h>
47#include <linux/crc32.h>
34f80b04 48#include <linux/crc32c.h>
a2fbb9ea
ET		 49#include <linux/prefetch.h>
50#include <linux/zlib.h>
a2fbb9ea 51#include <linux/io.h>
45229b42 52#include <linux/stringify.h>
7ab24bfd 53#include <linux/vmalloc.h>
a2fbb9ea 54
a2fbb9ea
ET		 55#include "bnx2x.h"
56#include "bnx2x_init.h"
94a78b79 57#include "bnx2x_init_ops.h"
9f6c9258 58#include "bnx2x_cmn.h"
e4901dde 59#include "bnx2x_dcb.h"
042181f5 60#include "bnx2x_sp.h"
a2fbb9ea 61
94a78b79
VZ		 62#include <linux/firmware.h>
63#include "bnx2x_fw_file_hdr.h"
64/* FW files */
45229b42
BH		 65#define FW_FILE_VERSION \
66 __stringify(BCM_5710_FW_MAJOR_VERSION) "." \
67 __stringify(BCM_5710_FW_MINOR_VERSION) "." \
68 __stringify(BCM_5710_FW_REVISION_VERSION) "." \
69 __stringify(BCM_5710_FW_ENGINEERING_VERSION)
560131f3
DK		 70#define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
71#define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
f2e0899f 72#define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
94a78b79 73
34f80b04
EG		 74/* Time in jiffies before concluding the transmitter is hung */
75#define TX_TIMEOUT (5*HZ)
a2fbb9ea 76
53a10565 77static char version[] __devinitdata =
619c5cb6 78 "Broadcom NetXtreme II 5771x/578xx 10/20-Gigabit Ethernet Driver "
a2fbb9ea
ET		 79 DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
80
24e3fcef 81MODULE_AUTHOR("Eliezer Tamir");
f2e0899f 82MODULE_DESCRIPTION("Broadcom NetXtreme II "
619c5cb6
VZ		 83 "BCM57710/57711/57711E/"
84 "57712/57712_MF/57800/57800_MF/57810/57810_MF/"
85 "57840/57840_MF Driver");
a2fbb9ea
ET		 86MODULE_LICENSE("GPL");
87MODULE_VERSION(DRV_MODULE_VERSION);
45229b42
BH		 88MODULE_FIRMWARE(FW_FILE_NAME_E1);
89MODULE_FIRMWARE(FW_FILE_NAME_E1H);
f2e0899f 90MODULE_FIRMWARE(FW_FILE_NAME_E2);
a2fbb9ea 91
555f6c78
EG		 92static int multi_mode = 1;
93module_param(multi_mode, int, 0);
ca00392c
EG		 94MODULE_PARM_DESC(multi_mode, " Multi queue mode "
95 "(0 Disable; 1 Enable (default))");
96
d6214d7a 97int num_queues;
54b9ddaa
VZ		 98module_param(num_queues, int, 0);
99MODULE_PARM_DESC(num_queues, " Number of queues for multi_mode=1"
100 " (default is as a number of CPUs)");
555f6c78 101
19680c48 102static int disable_tpa;
19680c48 103module_param(disable_tpa, int, 0);
9898f86d 104MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
8badd27a 105
9ee3d37b
DK		 106#define INT_MODE_INTx 1
107#define INT_MODE_MSI 2
8badd27a
EG		 108static int int_mode;
109module_param(int_mode, int, 0);
619c5cb6 110MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X "
cdaa7cb8 111 "(1 INT#x; 2 MSI)");
8badd27a 112
a18f5128
EG		 113static int dropless_fc;
114module_param(dropless_fc, int, 0);
115MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring");
116
9898f86d 117static int poll;
a2fbb9ea 118module_param(poll, int, 0);
9898f86d 119MODULE_PARM_DESC(poll, " Use polling (for debug)");
8d5726c4
EG		 120
121static int mrrs = -1;
122module_param(mrrs, int, 0);
123MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
124
9898f86d 125static int debug;
a2fbb9ea 126module_param(debug, int, 0);
9898f86d
EG		 127MODULE_PARM_DESC(debug, " Default debug msglevel");
128
a2fbb9ea 129
619c5cb6
VZ		 130
131struct workqueue_struct *bnx2x_wq;
ec6ba945 132
a2fbb9ea
ET		 133enum bnx2x_board_type {
134 BCM57710 = 0,
619c5cb6
VZ		 135 BCM57711,
136 BCM57711E,
137 BCM57712,
138 BCM57712_MF,
139 BCM57800,
140 BCM57800_MF,
141 BCM57810,
142 BCM57810_MF,
143 BCM57840,
144 BCM57840_MF
a2fbb9ea
ET		 145};
146
34f80b04 147/* indexed by board_type, above */
53a10565 148static struct {
a2fbb9ea
ET		 149 char *name;
150} board_info[] __devinitdata = {
619c5cb6
VZ		 151 { "Broadcom NetXtreme II BCM57710 10 Gigabit PCIe [Everest]" },
152 { "Broadcom NetXtreme II BCM57711 10 Gigabit PCIe" },
153 { "Broadcom NetXtreme II BCM57711E 10 Gigabit PCIe" },
154 { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet" },
155 { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Multi Function" },
156 { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet" },
157 { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Multi Function" },
158 { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet" },
159 { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Multi Function" },
160 { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet" },
161 { "Broadcom NetXtreme II BCM57840 10/20 Gigabit "
162 "Ethernet Multi Function"}
a2fbb9ea
ET		 163};
164
619c5cb6
VZ		 165#ifndef PCI_DEVICE_ID_NX2_57710
166#define PCI_DEVICE_ID_NX2_57710 CHIP_NUM_57710
167#endif
168#ifndef PCI_DEVICE_ID_NX2_57711
169#define PCI_DEVICE_ID_NX2_57711 CHIP_NUM_57711
170#endif
171#ifndef PCI_DEVICE_ID_NX2_57711E
172#define PCI_DEVICE_ID_NX2_57711E CHIP_NUM_57711E
173#endif
174#ifndef PCI_DEVICE_ID_NX2_57712
175#define PCI_DEVICE_ID_NX2_57712 CHIP_NUM_57712
176#endif
177#ifndef PCI_DEVICE_ID_NX2_57712_MF
178#define PCI_DEVICE_ID_NX2_57712_MF CHIP_NUM_57712_MF
179#endif
180#ifndef PCI_DEVICE_ID_NX2_57800
181#define PCI_DEVICE_ID_NX2_57800 CHIP_NUM_57800
182#endif
183#ifndef PCI_DEVICE_ID_NX2_57800_MF
184#define PCI_DEVICE_ID_NX2_57800_MF CHIP_NUM_57800_MF
185#endif
186#ifndef PCI_DEVICE_ID_NX2_57810
187#define PCI_DEVICE_ID_NX2_57810 CHIP_NUM_57810
188#endif
189#ifndef PCI_DEVICE_ID_NX2_57810_MF
190#define PCI_DEVICE_ID_NX2_57810_MF CHIP_NUM_57810_MF
191#endif
192#ifndef PCI_DEVICE_ID_NX2_57840
193#define PCI_DEVICE_ID_NX2_57840 CHIP_NUM_57840
194#endif
195#ifndef PCI_DEVICE_ID_NX2_57840_MF
196#define PCI_DEVICE_ID_NX2_57840_MF CHIP_NUM_57840_MF
197#endif
a3aa1884 198static DEFINE_PCI_DEVICE_TABLE(bnx2x_pci_tbl) = {
e4ed7113
EG		 199 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 },
200 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 },
201 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E },
f2e0899f 202 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 },
619c5cb6
VZ		 203 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF },
204 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 },
205 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF },
206 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 },
207 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF },
208 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840), BCM57840 },
209 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF },
a2fbb9ea
ET		 210 { 0 }
211};
212
213MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
214
215/****************************************************************************
216* General service functions
217****************************************************************************/
218
619c5cb6
VZ		 219static inline void __storm_memset_dma_mapping(struct bnx2x *bp,
220 u32 addr, dma_addr_t mapping)
221{
222 REG_WR(bp, addr, U64_LO(mapping));
223 REG_WR(bp, addr + 4, U64_HI(mapping));
224}
225
226static inline void storm_memset_spq_addr(struct bnx2x *bp,
227 dma_addr_t mapping, u16 abs_fid)
228{
229 u32 addr = XSEM_REG_FAST_MEMORY +
230 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid);
231
232 __storm_memset_dma_mapping(bp, addr, mapping);
233}
234
235static inline void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
236 u16 pf_id)
523224a3 237{
619c5cb6
VZ		 238 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
239 pf_id);
240 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
241 pf_id);
242 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
243 pf_id);
244 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
245 pf_id);
523224a3
DK		 246}
247
619c5cb6
VZ		 248static inline void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
249 u8 enable)
250{
251 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
252 enable);
253 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
254 enable);
255 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
256 enable);
257 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
258 enable);
259}
523224a3
DK		 260
261static inline void storm_memset_eq_data(struct bnx2x *bp,
262 struct event_ring_data *eq_data,
263 u16 pfid)
264{
265 size_t size = sizeof(struct event_ring_data);
266
267 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid);
268
269 __storm_memset_struct(bp, addr, size, (u32 *)eq_data);
270}
271
272static inline void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod,
273 u16 pfid)
274{
275 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid);
276 REG_WR16(bp, addr, eq_prod);
277}
278
a2fbb9ea
ET		 279/* used only at init
280 * locking is done by mcp
281 */
8d96286a 282static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
a2fbb9ea
ET		 283{
284 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
285 pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
286 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
287 PCICFG_VENDOR_ID_OFFSET);
288}
289
a2fbb9ea
ET		 290static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
291{
292 u32 val;
293
294 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
295 pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
296 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
297 PCICFG_VENDOR_ID_OFFSET);
298
299 return val;
300}
a2fbb9ea 301
f2e0899f
DK		 302#define DMAE_DP_SRC_GRC "grc src_addr [%08x]"
303#define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]"
304#define DMAE_DP_DST_GRC "grc dst_addr [%08x]"
305#define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]"
306#define DMAE_DP_DST_NONE "dst_addr [none]"
307
8d96286a 308static void bnx2x_dp_dmae(struct bnx2x *bp, struct dmae_command *dmae,
309 int msglvl)
f2e0899f
DK		 310{
311 u32 src_type = dmae->opcode & DMAE_COMMAND_SRC;
312
313 switch (dmae->opcode & DMAE_COMMAND_DST) {
314 case DMAE_CMD_DST_PCI:
315 if (src_type == DMAE_CMD_SRC_PCI)
316 DP(msglvl, "DMAE: opcode 0x%08x\n"
317 "src [%x:%08x], len [%d*4], dst [%x:%08x]\n"
318 "comp_addr [%x:%08x], comp_val 0x%08x\n",
319 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
320 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
321 dmae->comp_addr_hi, dmae->comp_addr_lo,
322 dmae->comp_val);
323 else
324 DP(msglvl, "DMAE: opcode 0x%08x\n"
325 "src [%08x], len [%d*4], dst [%x:%08x]\n"
326 "comp_addr [%x:%08x], comp_val 0x%08x\n",
327 dmae->opcode, dmae->src_addr_lo >> 2,
328 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
329 dmae->comp_addr_hi, dmae->comp_addr_lo,
330 dmae->comp_val);
331 break;
332 case DMAE_CMD_DST_GRC:
333 if (src_type == DMAE_CMD_SRC_PCI)
334 DP(msglvl, "DMAE: opcode 0x%08x\n"
335 "src [%x:%08x], len [%d*4], dst_addr [%08x]\n"
336 "comp_addr [%x:%08x], comp_val 0x%08x\n",
337 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
338 dmae->len, dmae->dst_addr_lo >> 2,
339 dmae->comp_addr_hi, dmae->comp_addr_lo,
340 dmae->comp_val);
341 else
342 DP(msglvl, "DMAE: opcode 0x%08x\n"
343 "src [%08x], len [%d*4], dst [%08x]\n"
344 "comp_addr [%x:%08x], comp_val 0x%08x\n",
345 dmae->opcode, dmae->src_addr_lo >> 2,
346 dmae->len, dmae->dst_addr_lo >> 2,
347 dmae->comp_addr_hi, dmae->comp_addr_lo,
348 dmae->comp_val);
349 break;
350 default:
351 if (src_type == DMAE_CMD_SRC_PCI)
352 DP(msglvl, "DMAE: opcode 0x%08x\n"
353 DP_LEVEL "src_addr [%x:%08x] len [%d * 4] "
354 "dst_addr [none]\n"
355 DP_LEVEL "comp_addr [%x:%08x] comp_val 0x%08x\n",
356 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
357 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
358 dmae->comp_val);
359 else
360 DP(msglvl, "DMAE: opcode 0x%08x\n"
361 DP_LEVEL "src_addr [%08x] len [%d * 4] "
362 "dst_addr [none]\n"
363 DP_LEVEL "comp_addr [%x:%08x] comp_val 0x%08x\n",
364 dmae->opcode, dmae->src_addr_lo >> 2,
365 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
366 dmae->comp_val);
367 break;
368 }
369
370}
371
a2fbb9ea 372/* copy command into DMAE command memory and set DMAE command go */
6c719d00 373void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx)
a2fbb9ea
ET		 374{
375 u32 cmd_offset;
376 int i;
377
378 cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
379 for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
380 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
381
ad8d3948
EG		 382 DP(BNX2X_MSG_OFF, "DMAE cmd[%d].%d (0x%08x) : 0x%08x\n",
383 idx, i, cmd_offset + i*4, *(((u32 *)dmae) + i));
a2fbb9ea
ET		 384 }
385 REG_WR(bp, dmae_reg_go_c[idx], 1);
386}
387
f2e0899f 388u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type)
a2fbb9ea 389{
f2e0899f
DK		 390 return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
391 DMAE_CMD_C_ENABLE);
392}
ad8d3948 393
f2e0899f
DK		 394u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode)
395{
396 return opcode & ~DMAE_CMD_SRC_RESET;
397}
ad8d3948 398
f2e0899f
DK		 399u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
400 bool with_comp, u8 comp_type)
401{
402 u32 opcode = 0;
403
404 opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
405 (dst_type << DMAE_COMMAND_DST_SHIFT));
ad8d3948 406
f2e0899f
DK		 407 opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET);
408
409 opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
410 opcode |= ((BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT) |
411 (BP_E1HVN(bp) << DMAE_COMMAND_DST_VN_SHIFT));
412 opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
a2fbb9ea 413
a2fbb9ea 414#ifdef __BIG_ENDIAN
f2e0899f 415 opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
a2fbb9ea 416#else
f2e0899f 417 opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
a2fbb9ea 418#endif
f2e0899f
DK		 419 if (with_comp)
420 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
421 return opcode;
422}
423
8d96286a 424static void bnx2x_prep_dmae_with_comp(struct bnx2x *bp,
425 struct dmae_command *dmae,
426 u8 src_type, u8 dst_type)
f2e0899f
DK		 427{
428 memset(dmae, 0, sizeof(struct dmae_command));
429
430 /* set the opcode */
431 dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type,
432 true, DMAE_COMP_PCI);
433
434 /* fill in the completion parameters */
435 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
436 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
437 dmae->comp_val = DMAE_COMP_VAL;
438}
439
440/* issue a dmae command over the init-channel and wailt for completion */
8d96286a 441static int bnx2x_issue_dmae_with_comp(struct bnx2x *bp,
442 struct dmae_command *dmae)
f2e0899f
DK		 443{
444 u32 *wb_comp = bnx2x_sp(bp, wb_comp);
5e374b5a 445 int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000;
f2e0899f
DK		 446 int rc = 0;
447
448 DP(BNX2X_MSG_OFF, "data before [0x%08x 0x%08x 0x%08x 0x%08x]\n",
a2fbb9ea
ET		 449 bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
450 bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
a2fbb9ea 451
619c5cb6
VZ		 452 /*
453 * Lock the dmae channel. Disable BHs to prevent a dead-lock
454 * as long as this code is called both from syscall context and
455 * from ndo_set_rx_mode() flow that may be called from BH.
456 */
6e30dd4e 457 spin_lock_bh(&bp->dmae_lock);
5ff7b6d4 458
f2e0899f 459 /* reset completion */
a2fbb9ea
ET		 460 *wb_comp = 0;
461
f2e0899f
DK		 462 /* post the command on the channel used for initializations */
463 bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
a2fbb9ea 464
f2e0899f 465 /* wait for completion */
a2fbb9ea 466 udelay(5);
f2e0899f 467 while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
ad8d3948
EG		 468 DP(BNX2X_MSG_OFF, "wb_comp 0x%08x\n", *wb_comp);
469
ad8d3948 470 if (!cnt) {
c3eefaf6 471 BNX2X_ERR("DMAE timeout!\n");
f2e0899f
DK		 472 rc = DMAE_TIMEOUT;
473 goto unlock;
a2fbb9ea 474 }
ad8d3948 475 cnt--;
f2e0899f 476 udelay(50);
a2fbb9ea 477 }
f2e0899f
DK		 478 if (*wb_comp & DMAE_PCI_ERR_FLAG) {
479 BNX2X_ERR("DMAE PCI error!\n");
480 rc = DMAE_PCI_ERROR;
481 }
482
483 DP(BNX2X_MSG_OFF, "data after [0x%08x 0x%08x 0x%08x 0x%08x]\n",
484 bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
485 bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
ad8d3948 486
f2e0899f 487unlock:
6e30dd4e 488 spin_unlock_bh(&bp->dmae_lock);
f2e0899f
DK		 489 return rc;
490}
491
492void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
493 u32 len32)
494{
495 struct dmae_command dmae;
496
497 if (!bp->dmae_ready) {
498 u32 *data = bnx2x_sp(bp, wb_data[0]);
499
500 DP(BNX2X_MSG_OFF, "DMAE is not ready (dst_addr %08x len32 %d)"
501 " using indirect\n", dst_addr, len32);
502 bnx2x_init_ind_wr(bp, dst_addr, data, len32);
503 return;
504 }
505
506 /* set opcode and fixed command fields */
507 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
508
509 /* fill in addresses and len */
510 dmae.src_addr_lo = U64_LO(dma_addr);
511 dmae.src_addr_hi = U64_HI(dma_addr);
512 dmae.dst_addr_lo = dst_addr >> 2;
513 dmae.dst_addr_hi = 0;
514 dmae.len = len32;
515
516 bnx2x_dp_dmae(bp, &dmae, BNX2X_MSG_OFF);
517
518 /* issue the command and wait for completion */
519 bnx2x_issue_dmae_with_comp(bp, &dmae);
a2fbb9ea
ET		 520}
521
c18487ee 522void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
a2fbb9ea 523{
5ff7b6d4 524 struct dmae_command dmae;
ad8d3948
EG		 525
526 if (!bp->dmae_ready) {
527 u32 *data = bnx2x_sp(bp, wb_data[0]);
528 int i;
529
530 DP(BNX2X_MSG_OFF, "DMAE is not ready (src_addr %08x len32 %d)"
531 " using indirect\n", src_addr, len32);
532 for (i = 0; i < len32; i++)
533 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
534 return;
535 }
536
f2e0899f
DK		 537 /* set opcode and fixed command fields */
538 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
a2fbb9ea 539
f2e0899f 540 /* fill in addresses and len */
5ff7b6d4
EG		 541 dmae.src_addr_lo = src_addr >> 2;
542 dmae.src_addr_hi = 0;
543 dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
544 dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
545 dmae.len = len32;
ad8d3948 546
f2e0899f 547 bnx2x_dp_dmae(bp, &dmae, BNX2X_MSG_OFF);
ad8d3948 548
f2e0899f
DK		 549 /* issue the command and wait for completion */
550 bnx2x_issue_dmae_with_comp(bp, &dmae);
ad8d3948
EG		 551}
552
8d96286a 553static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
554 u32 addr, u32 len)
573f2035 555{
02e3c6cb 556 int dmae_wr_max = DMAE_LEN32_WR_MAX(bp);
573f2035
EG		 557 int offset = 0;
558
02e3c6cb 559 while (len > dmae_wr_max) {
573f2035 560 bnx2x_write_dmae(bp, phys_addr + offset,
02e3c6cb
VZ		 561 addr + offset, dmae_wr_max);
562 offset += dmae_wr_max * 4;
563 len -= dmae_wr_max;
573f2035
EG		 564 }
565
566 bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
567}
568
ad8d3948
EG		 569/* used only for slowpath so not inlined */
570static void bnx2x_wb_wr(struct bnx2x *bp, int reg, u32 val_hi, u32 val_lo)
571{
572 u32 wb_write[2];
573
574 wb_write[0] = val_hi;
575 wb_write[1] = val_lo;
576 REG_WR_DMAE(bp, reg, wb_write, 2);
a2fbb9ea 577}
a2fbb9ea 578
ad8d3948
EG		 579#ifdef USE_WB_RD
580static u64 bnx2x_wb_rd(struct bnx2x *bp, int reg)
581{
582 u32 wb_data[2];
583
584 REG_RD_DMAE(bp, reg, wb_data, 2);
585
586 return HILO_U64(wb_data[0], wb_data[1]);
587}
588#endif
589
a2fbb9ea
ET		 590static int bnx2x_mc_assert(struct bnx2x *bp)
591{
a2fbb9ea 592 char last_idx;
34f80b04
EG		 593 int i, rc = 0;
594 u32 row0, row1, row2, row3;
595
596 /* XSTORM */
597 last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM +
598 XSTORM_ASSERT_LIST_INDEX_OFFSET);
599 if (last_idx)
600 BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
601
602 /* print the asserts */
603 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
604
605 row0 = REG_RD(bp, BAR_XSTRORM_INTMEM +
606 XSTORM_ASSERT_LIST_OFFSET(i));
607 row1 = REG_RD(bp, BAR_XSTRORM_INTMEM +
608 XSTORM_ASSERT_LIST_OFFSET(i) + 4);
609 row2 = REG_RD(bp, BAR_XSTRORM_INTMEM +
610 XSTORM_ASSERT_LIST_OFFSET(i) + 8);
611 row3 = REG_RD(bp, BAR_XSTRORM_INTMEM +
612 XSTORM_ASSERT_LIST_OFFSET(i) + 12);
613
614 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
615 BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x"
616 " 0x%08x 0x%08x 0x%08x\n",
617 i, row3, row2, row1, row0);
618 rc++;
619 } else {
620 break;
621 }
622 }
623
624 /* TSTORM */
625 last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM +
626 TSTORM_ASSERT_LIST_INDEX_OFFSET);
627 if (last_idx)
628 BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
629
630 /* print the asserts */
631 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
632
633 row0 = REG_RD(bp, BAR_TSTRORM_INTMEM +
634 TSTORM_ASSERT_LIST_OFFSET(i));
635 row1 = REG_RD(bp, BAR_TSTRORM_INTMEM +
636 TSTORM_ASSERT_LIST_OFFSET(i) + 4);
637 row2 = REG_RD(bp, BAR_TSTRORM_INTMEM +
638 TSTORM_ASSERT_LIST_OFFSET(i) + 8);
639 row3 = REG_RD(bp, BAR_TSTRORM_INTMEM +
640 TSTORM_ASSERT_LIST_OFFSET(i) + 12);
641
642 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
643 BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x"
644 " 0x%08x 0x%08x 0x%08x\n",
645 i, row3, row2, row1, row0);
646 rc++;
647 } else {
648 break;
649 }
650 }
651
652 /* CSTORM */
653 last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM +
654 CSTORM_ASSERT_LIST_INDEX_OFFSET);
655 if (last_idx)
656 BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
657
658 /* print the asserts */
659 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
660
661 row0 = REG_RD(bp, BAR_CSTRORM_INTMEM +
662 CSTORM_ASSERT_LIST_OFFSET(i));
663 row1 = REG_RD(bp, BAR_CSTRORM_INTMEM +
664 CSTORM_ASSERT_LIST_OFFSET(i) + 4);
665 row2 = REG_RD(bp, BAR_CSTRORM_INTMEM +
666 CSTORM_ASSERT_LIST_OFFSET(i) + 8);
667 row3 = REG_RD(bp, BAR_CSTRORM_INTMEM +
668 CSTORM_ASSERT_LIST_OFFSET(i) + 12);
669
670 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
671 BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x"
672 " 0x%08x 0x%08x 0x%08x\n",
673 i, row3, row2, row1, row0);
674 rc++;
675 } else {
676 break;
677 }
678 }
679
680 /* USTORM */
681 last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM +
682 USTORM_ASSERT_LIST_INDEX_OFFSET);
683 if (last_idx)
684 BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
685
686 /* print the asserts */
687 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
688
689 row0 = REG_RD(bp, BAR_USTRORM_INTMEM +
690 USTORM_ASSERT_LIST_OFFSET(i));
691 row1 = REG_RD(bp, BAR_USTRORM_INTMEM +
692 USTORM_ASSERT_LIST_OFFSET(i) + 4);
693 row2 = REG_RD(bp, BAR_USTRORM_INTMEM +
694 USTORM_ASSERT_LIST_OFFSET(i) + 8);
695 row3 = REG_RD(bp, BAR_USTRORM_INTMEM +
696 USTORM_ASSERT_LIST_OFFSET(i) + 12);
697
698 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
699 BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x"
700 " 0x%08x 0x%08x 0x%08x\n",
701 i, row3, row2, row1, row0);
702 rc++;
703 } else {
704 break;
a2fbb9ea
ET		 705 }
706 }
34f80b04 707
a2fbb9ea
ET		 708 return rc;
709}
c14423fe 710
7a25cc73 711void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl)
a2fbb9ea 712{
7a25cc73 713 u32 addr, val;
a2fbb9ea 714 u32 mark, offset;
4781bfad 715 __be32 data[9];
a2fbb9ea 716 int word;
f2e0899f 717 u32 trace_shmem_base;
2145a920
VZ		 718 if (BP_NOMCP(bp)) {
719 BNX2X_ERR("NO MCP - can not dump\n");
720 return;
721 }
7a25cc73
DK		 722 netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n",
723 (bp->common.bc_ver & 0xff0000) >> 16,
724 (bp->common.bc_ver & 0xff00) >> 8,
725 (bp->common.bc_ver & 0xff));
726
727 val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER);
728 if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER))
729 printk("%s" "MCP PC at 0x%x\n", lvl, val);
cdaa7cb8 730
f2e0899f
DK		 731 if (BP_PATH(bp) == 0)
732 trace_shmem_base = bp->common.shmem_base;
733 else
734 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr);
735 addr = trace_shmem_base - 0x0800 + 4;
cdaa7cb8 736 mark = REG_RD(bp, addr);
f2e0899f
DK		 737 mark = (CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH)
738 + ((mark + 0x3) & ~0x3) - 0x08000000;
7a25cc73 739 printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark);
a2fbb9ea 740
7a25cc73 741 printk("%s", lvl);
f2e0899f 742 for (offset = mark; offset <= trace_shmem_base; offset += 0x8*4) {
a2fbb9ea 743 for (word = 0; word < 8; word++)
cdaa7cb8 744 data[word] = htonl(REG_RD(bp, offset + 4*word));
a2fbb9ea 745 data[8] = 0x0;
7995c64e 746 pr_cont("%s", (char *)data);
a2fbb9ea 747 }
cdaa7cb8 748 for (offset = addr + 4; offset <= mark; offset += 0x8*4) {
a2fbb9ea 749 for (word = 0; word < 8; word++)
cdaa7cb8 750 data[word] = htonl(REG_RD(bp, offset + 4*word));
a2fbb9ea 751 data[8] = 0x0;
7995c64e 752 pr_cont("%s", (char *)data);
a2fbb9ea 753 }
7a25cc73
DK		 754 printk("%s" "end of fw dump\n", lvl);
755}
756
757static inline void bnx2x_fw_dump(struct bnx2x *bp)
758{
759 bnx2x_fw_dump_lvl(bp, KERN_ERR);
a2fbb9ea
ET		 760}
761
6c719d00 762void bnx2x_panic_dump(struct bnx2x *bp)
a2fbb9ea
ET		 763{
764 int i;
523224a3
DK		 765 u16 j;
766 struct hc_sp_status_block_data sp_sb_data;
767 int func = BP_FUNC(bp);
768#ifdef BNX2X_STOP_ON_ERROR
769 u16 start = 0, end = 0;
6383c0b3 770 u8 cos;
523224a3 771#endif
a2fbb9ea 772
66e855f3
YG		 773 bp->stats_state = STATS_STATE_DISABLED;
774 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
775
a2fbb9ea
ET		 776 BNX2X_ERR("begin crash dump -----------------\n");
777
8440d2b6
EG		 778 /* Indices */
779 /* Common */
523224a3 780 BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x)"
619c5cb6
VZ		 781 " spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n",
782 bp->def_idx, bp->def_att_idx, bp->attn_state,
783 bp->spq_prod_idx, bp->stats_counter);
523224a3
DK		 784 BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n",
785 bp->def_status_blk->atten_status_block.attn_bits,
786 bp->def_status_blk->atten_status_block.attn_bits_ack,
787 bp->def_status_blk->atten_status_block.status_block_id,
788 bp->def_status_blk->atten_status_block.attn_bits_index);
789 BNX2X_ERR(" def (");
790 for (i = 0; i < HC_SP_SB_MAX_INDICES; i++)
791 pr_cont("0x%x%s",
792 bp->def_status_blk->sp_sb.index_values[i],
793 (i == HC_SP_SB_MAX_INDICES - 1) ? ") " : " ");
794
795 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
796 *((u32 *)&sp_sb_data + i) = REG_RD(bp, BAR_CSTRORM_INTMEM +
797 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
798 i*sizeof(u32));
799
619c5cb6 800 pr_cont("igu_sb_id(0x%x) igu_seg_id(0x%x) "
523224a3 801 "pf_id(0x%x) vnic_id(0x%x) "
619c5cb6
VZ		 802 "vf_id(0x%x) vf_valid (0x%x) "
803 "state(0x%x)\n",
523224a3
DK		 804 sp_sb_data.igu_sb_id,
805 sp_sb_data.igu_seg_id,
806 sp_sb_data.p_func.pf_id,
807 sp_sb_data.p_func.vnic_id,
808 sp_sb_data.p_func.vf_id,
619c5cb6
VZ		 809 sp_sb_data.p_func.vf_valid,
810 sp_sb_data.state);
523224a3 811
8440d2b6 812
ec6ba945 813 for_each_eth_queue(bp, i) {
a2fbb9ea 814 struct bnx2x_fastpath *fp = &bp->fp[i];
523224a3 815 int loop;
f2e0899f 816 struct hc_status_block_data_e2 sb_data_e2;
523224a3
DK		 817 struct hc_status_block_data_e1x sb_data_e1x;
818 struct hc_status_block_sm *hc_sm_p =
619c5cb6
VZ		 819 CHIP_IS_E1x(bp) ?
820 sb_data_e1x.common.state_machine :
821 sb_data_e2.common.state_machine;
523224a3 822 struct hc_index_data *hc_index_p =
619c5cb6
VZ		 823 CHIP_IS_E1x(bp) ?
824 sb_data_e1x.index_data :
825 sb_data_e2.index_data;
6383c0b3 826 u8 data_size, cos;
523224a3 827 u32 *sb_data_p;
6383c0b3 828 struct bnx2x_fp_txdata txdata;
523224a3
DK		 829
830 /* Rx */
cdaa7cb8 831 BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x)"
523224a3 832 " rx_comp_prod(0x%x)"
cdaa7cb8 833 " rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n",
8440d2b6 834 i, fp->rx_bd_prod, fp->rx_bd_cons,
523224a3 835 fp->rx_comp_prod,
66e855f3 836 fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
cdaa7cb8 837 BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x)"
523224a3 838 " fp_hc_idx(0x%x)\n",
8440d2b6 839 fp->rx_sge_prod, fp->last_max_sge,
523224a3 840 le16_to_cpu(fp->fp_hc_idx));
a2fbb9ea 841
523224a3 842 /* Tx */
6383c0b3
AE		 843 for_each_cos_in_tx_queue(fp, cos)
844 {
845 txdata = fp->txdata[cos];
846 BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x)"
847 " tx_bd_prod(0x%x) tx_bd_cons(0x%x)"
848 " *tx_cons_sb(0x%x)\n",
849 i, txdata.tx_pkt_prod,
850 txdata.tx_pkt_cons, txdata.tx_bd_prod,
851 txdata.tx_bd_cons,
852 le16_to_cpu(*txdata.tx_cons_sb));
853 }
523224a3 854
619c5cb6
VZ		 855 loop = CHIP_IS_E1x(bp) ?
856 HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2;
523224a3
DK		 857
858 /* host sb data */
859
ec6ba945
VZ		 860#ifdef BCM_CNIC
861 if (IS_FCOE_FP(fp))
862 continue;
863#endif
523224a3
DK		 864 BNX2X_ERR(" run indexes (");
865 for (j = 0; j < HC_SB_MAX_SM; j++)
866 pr_cont("0x%x%s",
867 fp->sb_running_index[j],
868 (j == HC_SB_MAX_SM - 1) ? ")" : " ");
869
870 BNX2X_ERR(" indexes (");
871 for (j = 0; j < loop; j++)
872 pr_cont("0x%x%s",
873 fp->sb_index_values[j],
874 (j == loop - 1) ? ")" : " ");
875 /* fw sb data */
619c5cb6
VZ		 876 data_size = CHIP_IS_E1x(bp) ?
877 sizeof(struct hc_status_block_data_e1x) :
878 sizeof(struct hc_status_block_data_e2);
523224a3 879 data_size /= sizeof(u32);
619c5cb6
VZ		 880 sb_data_p = CHIP_IS_E1x(bp) ?
881 (u32 *)&sb_data_e1x :
882 (u32 *)&sb_data_e2;
523224a3
DK		 883 /* copy sb data in here */
884 for (j = 0; j < data_size; j++)
885 *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +
886 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) +
887 j * sizeof(u32));
888
619c5cb6
VZ		 889 if (!CHIP_IS_E1x(bp)) {
890 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) "
891 "vnic_id(0x%x) same_igu_sb_1b(0x%x) "
892 "state(0x%x)\n",
f2e0899f
DK		 893 sb_data_e2.common.p_func.pf_id,
894 sb_data_e2.common.p_func.vf_id,
895 sb_data_e2.common.p_func.vf_valid,
896 sb_data_e2.common.p_func.vnic_id,
619c5cb6
VZ		 897 sb_data_e2.common.same_igu_sb_1b,
898 sb_data_e2.common.state);
f2e0899f 899 } else {
619c5cb6
VZ		 900 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) "
901 "vnic_id(0x%x) same_igu_sb_1b(0x%x) "
902 "state(0x%x)\n",
f2e0899f
DK		 903 sb_data_e1x.common.p_func.pf_id,
904 sb_data_e1x.common.p_func.vf_id,
905 sb_data_e1x.common.p_func.vf_valid,
906 sb_data_e1x.common.p_func.vnic_id,
619c5cb6
VZ		 907 sb_data_e1x.common.same_igu_sb_1b,
908 sb_data_e1x.common.state);
f2e0899f 909 }
523224a3
DK		 910
911 /* SB_SMs data */
912 for (j = 0; j < HC_SB_MAX_SM; j++) {
913 pr_cont("SM[%d] __flags (0x%x) "
914 "igu_sb_id (0x%x) igu_seg_id(0x%x) "
915 "time_to_expire (0x%x) "
916 "timer_value(0x%x)\n", j,
917 hc_sm_p[j].__flags,
918 hc_sm_p[j].igu_sb_id,
919 hc_sm_p[j].igu_seg_id,
920 hc_sm_p[j].time_to_expire,
921 hc_sm_p[j].timer_value);
922 }
923
924 /* Indecies data */
925 for (j = 0; j < loop; j++) {
926 pr_cont("INDEX[%d] flags (0x%x) "
927 "timeout (0x%x)\n", j,
928 hc_index_p[j].flags,
929 hc_index_p[j].timeout);
930 }
8440d2b6 931 }
a2fbb9ea 932
523224a3 933#ifdef BNX2X_STOP_ON_ERROR
8440d2b6
EG		 934 /* Rings */
935 /* Rx */
ec6ba945 936 for_each_rx_queue(bp, i) {
8440d2b6 937 struct bnx2x_fastpath *fp = &bp->fp[i];
a2fbb9ea
ET		 938
939 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
940 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
8440d2b6 941 for (j = start; j != end; j = RX_BD(j + 1)) {
a2fbb9ea
ET		 942 u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
943 struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
944
c3eefaf6
EG		 945 BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n",
946 i, j, rx_bd[1], rx_bd[0], sw_bd->skb);
a2fbb9ea
ET		 947 }
948
3196a88a
EG		 949 start = RX_SGE(fp->rx_sge_prod);
950 end = RX_SGE(fp->last_max_sge);
8440d2b6 951 for (j = start; j != end; j = RX_SGE(j + 1)) {
7a9b2557
VZ		 952 u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
953 struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
954
c3eefaf6
EG		 955 BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n",
956 i, j, rx_sge[1], rx_sge[0], sw_page->page);
7a9b2557
VZ		 957 }
958
a2fbb9ea
ET		 959 start = RCQ_BD(fp->rx_comp_cons - 10);
960 end = RCQ_BD(fp->rx_comp_cons + 503);
8440d2b6 961 for (j = start; j != end; j = RCQ_BD(j + 1)) {
a2fbb9ea
ET		 962 u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
963
c3eefaf6
EG		 964 BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
965 i, j, cqe[0], cqe[1], cqe[2], cqe[3]);
a2fbb9ea
ET		 966 }
967 }
968
8440d2b6 969 /* Tx */
ec6ba945 970 for_each_tx_queue(bp, i) {
8440d2b6 971 struct bnx2x_fastpath *fp = &bp->fp[i];
6383c0b3
AE		 972 for_each_cos_in_tx_queue(fp, cos) {
973 struct bnx2x_fp_txdata *txdata = &fp->txdata[cos];
974
975 start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10);
976 end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245);
977 for (j = start; j != end; j = TX_BD(j + 1)) {
978 struct sw_tx_bd *sw_bd =
979 &txdata->tx_buf_ring[j];
980
981 BNX2X_ERR("fp%d: txdata %d, "
982 "packet[%x]=[%p,%x]\n",
983 i, cos, j, sw_bd->skb,
984 sw_bd->first_bd);
985 }
8440d2b6 986
6383c0b3
AE		 987 start = TX_BD(txdata->tx_bd_cons - 10);
988 end = TX_BD(txdata->tx_bd_cons + 254);
989 for (j = start; j != end; j = TX_BD(j + 1)) {
990 u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j];
8440d2b6 991
6383c0b3
AE		 992 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]="
993 "[%x:%x:%x:%x]\n",
994 i, cos, j, tx_bd[0], tx_bd[1],
995 tx_bd[2], tx_bd[3]);
996 }
8440d2b6
EG		 997 }
998 }
523224a3 999#endif
34f80b04 1000 bnx2x_fw_dump(bp);
a2fbb9ea
ET		 1001 bnx2x_mc_assert(bp);
1002 BNX2X_ERR("end crash dump -----------------\n");
a2fbb9ea
ET		 1003}
1004
619c5cb6
VZ		 1005/*
1006 * FLR Support for E2
1007 *
1008 * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW
1009 * initialization.
1010 */
1011#define FLR_WAIT_USEC 10000 /* 10 miliseconds */
1012#define FLR_WAIT_INTERAVAL 50 /* usec */
1013#define FLR_POLL_CNT (FLR_WAIT_USEC/FLR_WAIT_INTERAVAL) /* 200 */
1014
1015struct pbf_pN_buf_regs {
1016 int pN;
1017 u32 init_crd;
1018 u32 crd;
1019 u32 crd_freed;
1020};
1021
1022struct pbf_pN_cmd_regs {
1023 int pN;
1024 u32 lines_occup;
1025 u32 lines_freed;
1026};
1027
1028static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp,
1029 struct pbf_pN_buf_regs *regs,
1030 u32 poll_count)
1031{
1032 u32 init_crd, crd, crd_start, crd_freed, crd_freed_start;
1033 u32 cur_cnt = poll_count;
1034
1035 crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed);
1036 crd = crd_start = REG_RD(bp, regs->crd);
1037 init_crd = REG_RD(bp, regs->init_crd);
1038
1039 DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd);
1040 DP(BNX2X_MSG_SP, "CREDIT[%d] : s:%x\n", regs->pN, crd);
1041 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed);
1042
1043 while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) <
1044 (init_crd - crd_start))) {
1045 if (cur_cnt--) {
1046 udelay(FLR_WAIT_INTERAVAL);
1047 crd = REG_RD(bp, regs->crd);
1048 crd_freed = REG_RD(bp, regs->crd_freed);
1049 } else {
1050 DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n",
1051 regs->pN);
1052 DP(BNX2X_MSG_SP, "CREDIT[%d] : c:%x\n",
1053 regs->pN, crd);
1054 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n",
1055 regs->pN, crd_freed);
1056 break;
1057 }
1058 }
1059 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n",
1060 poll_count-cur_cnt, FLR_WAIT_INTERAVAL, regs->pN);
1061}
1062
1063static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp,
1064 struct pbf_pN_cmd_regs *regs,
1065 u32 poll_count)
1066{
1067 u32 occup, to_free, freed, freed_start;
1068 u32 cur_cnt = poll_count;
1069
1070 occup = to_free = REG_RD(bp, regs->lines_occup);
1071 freed = freed_start = REG_RD(bp, regs->lines_freed);
1072
1073 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup);
1074 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed);
1075
1076 while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) {
1077 if (cur_cnt--) {
1078 udelay(FLR_WAIT_INTERAVAL);
1079 occup = REG_RD(bp, regs->lines_occup);
1080 freed = REG_RD(bp, regs->lines_freed);
1081 } else {
1082 DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n",
1083 regs->pN);
1084 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n",
1085 regs->pN, occup);
1086 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n",
1087 regs->pN, freed);
1088 break;
1089 }
1090 }
1091 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n",
1092 poll_count-cur_cnt, FLR_WAIT_INTERAVAL, regs->pN);
1093}
1094
1095static inline u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg,
1096 u32 expected, u32 poll_count)
1097{
1098 u32 cur_cnt = poll_count;
1099 u32 val;
1100
1101 while ((val = REG_RD(bp, reg)) != expected && cur_cnt--)
1102 udelay(FLR_WAIT_INTERAVAL);
1103
1104 return val;
1105}
1106
1107static inline int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
1108 char *msg, u32 poll_cnt)
1109{
1110 u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt);
1111 if (val != 0) {
1112 BNX2X_ERR("%s usage count=%d\n", msg, val);
1113 return 1;
1114 }
1115 return 0;
1116}
1117
1118static u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp)
1119{
1120 /* adjust polling timeout */
1121 if (CHIP_REV_IS_EMUL(bp))
1122 return FLR_POLL_CNT * 2000;
1123
1124 if (CHIP_REV_IS_FPGA(bp))
1125 return FLR_POLL_CNT * 120;
1126
1127 return FLR_POLL_CNT;
1128}
1129
1130static void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count)
1131{
1132 struct pbf_pN_cmd_regs cmd_regs[] = {
1133 {0, (CHIP_IS_E3B0(bp)) ?
1134 PBF_REG_TQ_OCCUPANCY_Q0 :
1135 PBF_REG_P0_TQ_OCCUPANCY,
1136 (CHIP_IS_E3B0(bp)) ?
1137 PBF_REG_TQ_LINES_FREED_CNT_Q0 :
1138 PBF_REG_P0_TQ_LINES_FREED_CNT},
1139 {1, (CHIP_IS_E3B0(bp)) ?
1140 PBF_REG_TQ_OCCUPANCY_Q1 :
1141 PBF_REG_P1_TQ_OCCUPANCY,
1142 (CHIP_IS_E3B0(bp)) ?
1143 PBF_REG_TQ_LINES_FREED_CNT_Q1 :
1144 PBF_REG_P1_TQ_LINES_FREED_CNT},
1145 {4, (CHIP_IS_E3B0(bp)) ?
1146 PBF_REG_TQ_OCCUPANCY_LB_Q :
1147 PBF_REG_P4_TQ_OCCUPANCY,
1148 (CHIP_IS_E3B0(bp)) ?
1149 PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
1150 PBF_REG_P4_TQ_LINES_FREED_CNT}
1151 };
1152
1153 struct pbf_pN_buf_regs buf_regs[] = {
1154 {0, (CHIP_IS_E3B0(bp)) ?
1155 PBF_REG_INIT_CRD_Q0 :
1156 PBF_REG_P0_INIT_CRD ,
1157 (CHIP_IS_E3B0(bp)) ?
1158 PBF_REG_CREDIT_Q0 :
1159 PBF_REG_P0_CREDIT,
1160 (CHIP_IS_E3B0(bp)) ?
1161 PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
1162 PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
1163 {1, (CHIP_IS_E3B0(bp)) ?
1164 PBF_REG_INIT_CRD_Q1 :
1165 PBF_REG_P1_INIT_CRD,
1166 (CHIP_IS_E3B0(bp)) ?
1167 PBF_REG_CREDIT_Q1 :
1168 PBF_REG_P1_CREDIT,
1169 (CHIP_IS_E3B0(bp)) ?
1170 PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
1171 PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
1172 {4, (CHIP_IS_E3B0(bp)) ?
1173 PBF_REG_INIT_CRD_LB_Q :
1174 PBF_REG_P4_INIT_CRD,
1175 (CHIP_IS_E3B0(bp)) ?
1176 PBF_REG_CREDIT_LB_Q :
1177 PBF_REG_P4_CREDIT,
1178 (CHIP_IS_E3B0(bp)) ?
1179 PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
1180 PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
1181 };
1182
1183 int i;
1184
1185 /* Verify the command queues are flushed P0, P1, P4 */
1186 for (i = 0; i < ARRAY_SIZE(cmd_regs); i++)
1187 bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count);
1188
1189
1190 /* Verify the transmission buffers are flushed P0, P1, P4 */
1191 for (i = 0; i < ARRAY_SIZE(buf_regs); i++)
1192 bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count);
1193}
1194
1195#define OP_GEN_PARAM(param) \
1196 (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
1197
1198#define OP_GEN_TYPE(type) \
1199 (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
1200
1201#define OP_GEN_AGG_VECT(index) \
1202 (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
1203
1204
1205static inline int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func,
1206 u32 poll_cnt)
1207{
1208 struct sdm_op_gen op_gen = {0};
1209
1210 u32 comp_addr = BAR_CSTRORM_INTMEM +
1211 CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func);
1212 int ret = 0;
1213
1214 if (REG_RD(bp, comp_addr)) {
1215 BNX2X_ERR("Cleanup complete is not 0\n");
1216 return 1;
1217 }
1218
1219 op_gen.command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
1220 op_gen.command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
1221 op_gen.command |= OP_GEN_AGG_VECT(clnup_func);
1222 op_gen.command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
1223
1224 DP(BNX2X_MSG_SP, "FW Final cleanup\n");
1225 REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen.command);
1226
1227 if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) {
1228 BNX2X_ERR("FW final cleanup did not succeed\n");
1229 ret = 1;
1230 }
1231 /* Zero completion for nxt FLR */
1232 REG_WR(bp, comp_addr, 0);
1233
1234 return ret;
1235}
1236
1237static inline u8 bnx2x_is_pcie_pending(struct pci_dev *dev)
1238{
1239 int pos;
1240 u16 status;
1241
77c98e6a 1242 pos = pci_pcie_cap(dev);
619c5cb6
VZ		 1243 if (!pos)
1244 return false;
1245
1246 pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &status);
1247 return status & PCI_EXP_DEVSTA_TRPND;
1248}
1249
1250/* PF FLR specific routines
1251*/
1252static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt)
1253{
1254
1255 /* wait for CFC PF usage-counter to zero (includes all the VFs) */
1256 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1257 CFC_REG_NUM_LCIDS_INSIDE_PF,
1258 "CFC PF usage counter timed out",
1259 poll_cnt))
1260 return 1;
1261
1262
1263 /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
1264 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1265 DORQ_REG_PF_USAGE_CNT,
1266 "DQ PF usage counter timed out",
1267 poll_cnt))
1268 return 1;
1269
1270 /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
1271 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1272 QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp),
1273 "QM PF usage counter timed out",
1274 poll_cnt))
1275 return 1;
1276
1277 /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
1278 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1279 TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp),
1280 "Timers VNIC usage counter timed out",
1281 poll_cnt))
1282 return 1;
1283 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1284 TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp),
1285 "Timers NUM_SCANS usage counter timed out",
1286 poll_cnt))
1287 return 1;
1288
1289 /* Wait DMAE PF usage counter to zero */
1290 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1291 dmae_reg_go_c[INIT_DMAE_C(bp)],
1292 "DMAE dommand register timed out",
1293 poll_cnt))
1294 return 1;
1295
1296 return 0;
1297}
1298
1299static void bnx2x_hw_enable_status(struct bnx2x *bp)
1300{
1301 u32 val;
1302
1303 val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF);
1304 DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val);
1305
1306 val = REG_RD(bp, PBF_REG_DISABLE_PF);
1307 DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val);
1308
1309 val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN);
1310 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val);
1311
1312 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN);
1313 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val);
1314
1315 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
1316 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val);
1317
1318 val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
1319 DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val);
1320
1321 val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
1322 DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val);
1323
1324 val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1325 DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n",
1326 val);
1327}
1328
1329static int bnx2x_pf_flr_clnup(struct bnx2x *bp)
1330{
1331 u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp);
1332
1333 DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp));
1334
1335 /* Re-enable PF target read access */
1336 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
1337
1338 /* Poll HW usage counters */
1339 if (bnx2x_poll_hw_usage_counters(bp, poll_cnt))
1340 return -EBUSY;
1341
1342 /* Zero the igu 'trailing edge' and 'leading edge' */
1343
1344 /* Send the FW cleanup command */
1345 if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt))
1346 return -EBUSY;
1347
1348 /* ATC cleanup */
1349
1350 /* Verify TX hw is flushed */
1351 bnx2x_tx_hw_flushed(bp, poll_cnt);
1352
1353 /* Wait 100ms (not adjusted according to platform) */
1354 msleep(100);
1355
1356 /* Verify no pending pci transactions */
1357 if (bnx2x_is_pcie_pending(bp->pdev))
1358 BNX2X_ERR("PCIE Transactions still pending\n");
1359
1360 /* Debug */
1361 bnx2x_hw_enable_status(bp);
1362
1363 /*
1364 * Master enable - Due to WB DMAE writes performed before this
1365 * register is re-initialized as part of the regular function init
1366 */
1367 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
1368
1369 return 0;
1370}
1371
f2e0899f 1372static void bnx2x_hc_int_enable(struct bnx2x *bp)
a2fbb9ea 1373{
34f80b04 1374 int port = BP_PORT(bp);
a2fbb9ea
ET		 1375 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1376 u32 val = REG_RD(bp, addr);
1377 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
8badd27a 1378 int msi = (bp->flags & USING_MSI_FLAG) ? 1 : 0;
a2fbb9ea
ET		 1379
1380 if (msix) {
8badd27a
EG		 1381 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1382 HC_CONFIG_0_REG_INT_LINE_EN_0);
a2fbb9ea
ET		 1383 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1384 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
8badd27a
EG		 1385 } else if (msi) {
1386 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
1387 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1388 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1389 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
a2fbb9ea
ET		 1390 } else {
1391 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
615f8fd9 1392 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
a2fbb9ea
ET		 1393 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1394 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
615f8fd9 1395
a0fd065c
DK		 1396 if (!CHIP_IS_E1(bp)) {
1397 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n",
1398 val, port, addr);
615f8fd9 1399
a0fd065c 1400 REG_WR(bp, addr, val);
615f8fd9 1401
a0fd065c
DK		 1402 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
1403 }
a2fbb9ea
ET		 1404 }
1405
a0fd065c
DK		 1406 if (CHIP_IS_E1(bp))
1407 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF);
1408
8badd27a
EG		 1409 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x) mode %s\n",
1410 val, port, addr, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
a2fbb9ea
ET		 1411
1412 REG_WR(bp, addr, val);
37dbbf32
EG		 1413 /*
1414 * Ensure that HC_CONFIG is written before leading/trailing edge config
1415 */
1416 mmiowb();
1417 barrier();
34f80b04 1418
f2e0899f 1419 if (!CHIP_IS_E1(bp)) {
34f80b04 1420 /* init leading/trailing edge */
fb3bff17 1421 if (IS_MF(bp)) {
8badd27a 1422 val = (0xee0f | (1 << (BP_E1HVN(bp) + 4)));
34f80b04 1423 if (bp->port.pmf)
4acac6a5
EG		 1424 /* enable nig and gpio3 attention */
1425 val |= 0x1100;
34f80b04
EG		 1426 } else
1427 val = 0xffff;
1428
1429 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
1430 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
1431 }
37dbbf32
EG		 1432
1433 /* Make sure that interrupts are indeed enabled from here on */
1434 mmiowb();
a2fbb9ea
ET		 1435}
1436
f2e0899f
DK		 1437static void bnx2x_igu_int_enable(struct bnx2x *bp)
1438{
1439 u32 val;
1440 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1441 int msi = (bp->flags & USING_MSI_FLAG) ? 1 : 0;
1442
1443 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1444
1445 if (msix) {
1446 val &= ~(IGU_PF_CONF_INT_LINE_EN |
1447 IGU_PF_CONF_SINGLE_ISR_EN);
1448 val |= (IGU_PF_CONF_FUNC_EN |
1449 IGU_PF_CONF_MSI_MSIX_EN |
1450 IGU_PF_CONF_ATTN_BIT_EN);
1451 } else if (msi) {
1452 val &= ~IGU_PF_CONF_INT_LINE_EN;
1453 val |= (IGU_PF_CONF_FUNC_EN |
1454 IGU_PF_CONF_MSI_MSIX_EN |
1455 IGU_PF_CONF_ATTN_BIT_EN |
1456 IGU_PF_CONF_SINGLE_ISR_EN);
1457 } else {
1458 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
1459 val |= (IGU_PF_CONF_FUNC_EN |
1460 IGU_PF_CONF_INT_LINE_EN |
1461 IGU_PF_CONF_ATTN_BIT_EN |
1462 IGU_PF_CONF_SINGLE_ISR_EN);
1463 }
1464
1465 DP(NETIF_MSG_INTR, "write 0x%x to IGU mode %s\n",
1466 val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1467
1468 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1469
1470 barrier();
1471
1472 /* init leading/trailing edge */
1473 if (IS_MF(bp)) {
1474 val = (0xee0f | (1 << (BP_E1HVN(bp) + 4)));
1475 if (bp->port.pmf)
1476 /* enable nig and gpio3 attention */
1477 val |= 0x1100;
1478 } else
1479 val = 0xffff;
1480
1481 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
1482 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
1483
1484 /* Make sure that interrupts are indeed enabled from here on */
1485 mmiowb();
1486}
1487
1488void bnx2x_int_enable(struct bnx2x *bp)
1489{
1490 if (bp->common.int_block == INT_BLOCK_HC)
1491 bnx2x_hc_int_enable(bp);
1492 else
1493 bnx2x_igu_int_enable(bp);
1494}
1495
1496static void bnx2x_hc_int_disable(struct bnx2x *bp)
a2fbb9ea 1497{
34f80b04 1498 int port = BP_PORT(bp);
a2fbb9ea
ET		 1499 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1500 u32 val = REG_RD(bp, addr);
1501
a0fd065c
DK		 1502 /*
1503 * in E1 we must use only PCI configuration space to disable
1504 * MSI/MSIX capablility
1505 * It's forbitten to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
1506 */
1507 if (CHIP_IS_E1(bp)) {
1508 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on
1509 * Use mask register to prevent from HC sending interrupts
1510 * after we exit the function
1511 */
1512 REG_WR(bp, HC_REG_INT_MASK + port*4, 0);
1513
1514 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1515 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1516 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1517 } else
1518 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1519 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1520 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1521 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
a2fbb9ea
ET		 1522
1523 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n",
1524 val, port, addr);
1525
8badd27a
EG		 1526 /* flush all outstanding writes */
1527 mmiowb();
1528
a2fbb9ea
ET		 1529 REG_WR(bp, addr, val);
1530 if (REG_RD(bp, addr) != val)
1531 BNX2X_ERR("BUG! proper val not read from IGU!\n");
1532}
1533
f2e0899f
DK		 1534static void bnx2x_igu_int_disable(struct bnx2x *bp)
1535{
1536 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1537
1538 val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
1539 IGU_PF_CONF_INT_LINE_EN |
1540 IGU_PF_CONF_ATTN_BIT_EN);
1541
1542 DP(NETIF_MSG_INTR, "write %x to IGU\n", val);
1543
1544 /* flush all outstanding writes */
1545 mmiowb();
1546
1547 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1548 if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)
1549 BNX2X_ERR("BUG! proper val not read from IGU!\n");
1550}
1551
6383c0b3 1552void bnx2x_int_disable(struct bnx2x *bp)
f2e0899f
DK		 1553{
1554 if (bp->common.int_block == INT_BLOCK_HC)
1555 bnx2x_hc_int_disable(bp);
1556 else
1557 bnx2x_igu_int_disable(bp);
1558}
1559
9f6c9258 1560void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
a2fbb9ea 1561{
a2fbb9ea 1562 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
8badd27a 1563 int i, offset;
a2fbb9ea 1564
f8ef6e44
YG		 1565 if (disable_hw)
1566 /* prevent the HW from sending interrupts */
1567 bnx2x_int_disable(bp);
a2fbb9ea
ET		 1568
1569 /* make sure all ISRs are done */
1570 if (msix) {
8badd27a
EG		 1571 synchronize_irq(bp->msix_table[0].vector);
1572 offset = 1;
37b091ba
MC		 1573#ifdef BCM_CNIC
1574 offset++;
1575#endif
ec6ba945 1576 for_each_eth_queue(bp, i)
754a2f52 1577 synchronize_irq(bp->msix_table[offset++].vector);
a2fbb9ea
ET		 1578 } else
1579 synchronize_irq(bp->pdev->irq);
1580
1581 /* make sure sp_task is not running */
1cf167f2 1582 cancel_delayed_work(&bp->sp_task);
3deb8167 1583 cancel_delayed_work(&bp->period_task);
1cf167f2 1584 flush_workqueue(bnx2x_wq);
a2fbb9ea
ET		 1585}
1586
34f80b04 1587/* fast path */
a2fbb9ea
ET		 1588
1589/*
34f80b04 1590 * General service functions
a2fbb9ea
ET		 1591 */
1592
72fd0718
VZ		 1593/* Return true if succeeded to acquire the lock */
1594static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
1595{
1596 u32 lock_status;
1597 u32 resource_bit = (1 << resource);
1598 int func = BP_FUNC(bp);
1599 u32 hw_lock_control_reg;
1600
1601 DP(NETIF_MSG_HW, "Trying to take a lock on resource %d\n", resource);
1602
1603 /* Validating that the resource is within range */
1604 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1605 DP(NETIF_MSG_HW,
1606 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1607 resource, HW_LOCK_MAX_RESOURCE_VALUE);
0fdf4d09 1608 return false;
72fd0718
VZ		 1609 }
1610
1611 if (func <= 5)
1612 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1613 else
1614 hw_lock_control_reg =
1615 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1616
1617 /* Try to acquire the lock */
1618 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1619 lock_status = REG_RD(bp, hw_lock_control_reg);
1620 if (lock_status & resource_bit)
1621 return true;
1622
1623 DP(NETIF_MSG_HW, "Failed to get a lock on resource %d\n", resource);
1624 return false;
1625}
1626
c9ee9206
VZ		 1627/**
1628 * bnx2x_get_leader_lock_resource - get the recovery leader resource id
1629 *
1630 * @bp: driver handle
1631 *
1632 * Returns the recovery leader resource id according to the engine this function
1633 * belongs to. Currently only only 2 engines is supported.
1634 */
1635static inline int bnx2x_get_leader_lock_resource(struct bnx2x *bp)
1636{
1637 if (BP_PATH(bp))
1638 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
1639 else
1640 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
1641}
1642
1643/**
1644 * bnx2x_trylock_leader_lock- try to aquire a leader lock.
1645 *
1646 * @bp: driver handle
1647 *
1648 * Tries to aquire a leader lock for cuurent engine.
1649 */
1650static inline bool bnx2x_trylock_leader_lock(struct bnx2x *bp)
1651{
1652 return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1653}
1654
993ac7b5 1655#ifdef BCM_CNIC
619c5cb6 1656static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err);
993ac7b5 1657#endif
3196a88a 1658
619c5cb6 1659void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe)
a2fbb9ea
ET		 1660{
1661 struct bnx2x *bp = fp->bp;
1662 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1663 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
619c5cb6
VZ		 1664 enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX;
1665 struct bnx2x_queue_sp_obj *q_obj = &fp->q_obj;
a2fbb9ea 1666
34f80b04 1667 DP(BNX2X_MSG_SP,
a2fbb9ea 1668 "fp %d cid %d got ramrod #%d state is %x type is %d\n",
0626b899 1669 fp->index, cid, command, bp->state,
34f80b04 1670 rr_cqe->ramrod_cqe.ramrod_type);
a2fbb9ea 1671
619c5cb6
VZ		 1672 switch (command) {
1673 case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
1674 DP(NETIF_MSG_IFUP, "got UPDATE ramrod. CID %d\n", cid);
1675 drv_cmd = BNX2X_Q_CMD_UPDATE;
1676 break;
1677 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
523224a3 1678 DP(NETIF_MSG_IFUP, "got MULTI[%d] setup ramrod\n", cid);
619c5cb6 1679 drv_cmd = BNX2X_Q_CMD_SETUP;
a2fbb9ea
ET		 1680 break;
1681
6383c0b3
AE		 1682 case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
1683 DP(NETIF_MSG_IFUP, "got MULTI[%d] tx-only setup ramrod\n", cid);
1684 drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
1685 break;
1686
619c5cb6 1687 case (RAMROD_CMD_ID_ETH_HALT):
523224a3 1688 DP(NETIF_MSG_IFDOWN, "got MULTI[%d] halt ramrod\n", cid);
619c5cb6 1689 drv_cmd = BNX2X_Q_CMD_HALT;
a2fbb9ea
ET		 1690 break;
1691
619c5cb6 1692 case (RAMROD_CMD_ID_ETH_TERMINATE):
523224a3 1693 DP(NETIF_MSG_IFDOWN, "got MULTI[%d] teminate ramrod\n", cid);
619c5cb6 1694 drv_cmd = BNX2X_Q_CMD_TERMINATE;
a2fbb9ea
ET		 1695 break;
1696
619c5cb6
VZ		 1697 case (RAMROD_CMD_ID_ETH_EMPTY):
1698 DP(NETIF_MSG_IFDOWN, "got MULTI[%d] empty ramrod\n", cid);
1699 drv_cmd = BNX2X_Q_CMD_EMPTY;
993ac7b5 1700 break;
619c5cb6
VZ		 1701
1702 default:
1703 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n",
1704 command, fp->index);
1705 return;
523224a3 1706 }
3196a88a 1707
619c5cb6
VZ		 1708 if ((drv_cmd != BNX2X_Q_CMD_MAX) &&
1709 q_obj->complete_cmd(bp, q_obj, drv_cmd))
1710 /* q_obj->complete_cmd() failure means that this was
1711 * an unexpected completion.
1712 *
1713 * In this case we don't want to increase the bp->spq_left
1714 * because apparently we haven't sent this command the first
1715 * place.
1716 */
1717#ifdef BNX2X_STOP_ON_ERROR
1718 bnx2x_panic();
1719#else
1720 return;
1721#endif
1722
8fe23fbd 1723 smp_mb__before_atomic_inc();
6e30dd4e 1724 atomic_inc(&bp->cq_spq_left);
619c5cb6
VZ		 1725 /* push the change in bp->spq_left and towards the memory */
1726 smp_mb__after_atomic_inc();
49d66772 1727
523224a3 1728 return;
a2fbb9ea
ET		 1729}
1730
619c5cb6
VZ		 1731void bnx2x_update_rx_prod(struct bnx2x *bp, struct bnx2x_fastpath *fp,
1732 u16 bd_prod, u16 rx_comp_prod, u16 rx_sge_prod)
1733{
1734 u32 start = BAR_USTRORM_INTMEM + fp->ustorm_rx_prods_offset;
1735
1736 bnx2x_update_rx_prod_gen(bp, fp, bd_prod, rx_comp_prod, rx_sge_prod,
1737 start);
1738}
1739
9f6c9258 1740irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
a2fbb9ea 1741{
555f6c78 1742 struct bnx2x *bp = netdev_priv(dev_instance);
a2fbb9ea 1743 u16 status = bnx2x_ack_int(bp);
34f80b04 1744 u16 mask;
ca00392c 1745 int i;
6383c0b3 1746 u8 cos;
a2fbb9ea 1747
34f80b04 1748 /* Return here if interrupt is shared and it's not for us */
a2fbb9ea
ET		 1749 if (unlikely(status == 0)) {
1750 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1751 return IRQ_NONE;
1752 }
f5372251 1753 DP(NETIF_MSG_INTR, "got an interrupt status 0x%x\n", status);
a2fbb9ea 1754
3196a88a
EG		 1755#ifdef BNX2X_STOP_ON_ERROR
1756 if (unlikely(bp->panic))
1757 return IRQ_HANDLED;
1758#endif
1759
ec6ba945 1760 for_each_eth_queue(bp, i) {
ca00392c 1761 struct bnx2x_fastpath *fp = &bp->fp[i];
a2fbb9ea 1762
6383c0b3 1763 mask = 0x2 << (fp->index + CNIC_PRESENT);
ca00392c 1764 if (status & mask) {
619c5cb6 1765 /* Handle Rx or Tx according to SB id */
54b9ddaa 1766 prefetch(fp->rx_cons_sb);
6383c0b3
AE		 1767 for_each_cos_in_tx_queue(fp, cos)
1768 prefetch(fp->txdata[cos].tx_cons_sb);
523224a3 1769 prefetch(&fp->sb_running_index[SM_RX_ID]);
54b9ddaa 1770 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
ca00392c
EG		 1771 status &= ~mask;
1772 }
a2fbb9ea
ET		 1773 }
1774
993ac7b5 1775#ifdef BCM_CNIC
523224a3 1776 mask = 0x2;
993ac7b5
MC		 1777 if (status & (mask | 0x1)) {
1778 struct cnic_ops *c_ops = NULL;
1779
619c5cb6
VZ		 1780 if (likely(bp->state == BNX2X_STATE_OPEN)) {
1781 rcu_read_lock();
1782 c_ops = rcu_dereference(bp->cnic_ops);
1783 if (c_ops)
1784 c_ops->cnic_handler(bp->cnic_data, NULL);
1785 rcu_read_unlock();
1786 }
993ac7b5
MC		 1787
1788 status &= ~mask;
1789 }
1790#endif
a2fbb9ea 1791
34f80b04 1792 if (unlikely(status & 0x1)) {
1cf167f2 1793 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
a2fbb9ea
ET		 1794
1795 status &= ~0x1;
1796 if (!status)
1797 return IRQ_HANDLED;
1798 }
1799
cdaa7cb8
VZ		 1800 if (unlikely(status))
1801 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
34f80b04 1802 status);
a2fbb9ea 1803
c18487ee 1804 return IRQ_HANDLED;
a2fbb9ea
ET		 1805}
1806
c18487ee
YR		 1807/* Link */
1808
1809/*
1810 * General service functions
1811 */
a2fbb9ea 1812
9f6c9258 1813int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
c18487ee
YR		 1814{
1815 u32 lock_status;
1816 u32 resource_bit = (1 << resource);
4a37fb66
YG		 1817 int func = BP_FUNC(bp);
1818 u32 hw_lock_control_reg;
c18487ee 1819 int cnt;
a2fbb9ea 1820
c18487ee
YR		 1821 /* Validating that the resource is within range */
1822 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1823 DP(NETIF_MSG_HW,
1824 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1825 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1826 return -EINVAL;
1827 }
a2fbb9ea 1828
4a37fb66
YG		 1829 if (func <= 5) {
1830 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1831 } else {
1832 hw_lock_control_reg =
1833 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1834 }
1835
c18487ee 1836 /* Validating that the resource is not already taken */
4a37fb66 1837 lock_status = REG_RD(bp, hw_lock_control_reg);
c18487ee
YR		 1838 if (lock_status & resource_bit) {
1839 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n",
1840 lock_status, resource_bit);
1841 return -EEXIST;
1842 }
a2fbb9ea 1843
46230476
EG		 1844 /* Try for 5 second every 5ms */
1845 for (cnt = 0; cnt < 1000; cnt++) {
c18487ee 1846 /* Try to acquire the lock */
4a37fb66
YG		 1847 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1848 lock_status = REG_RD(bp, hw_lock_control_reg);
c18487ee
YR		 1849 if (lock_status & resource_bit)
1850 return 0;
a2fbb9ea 1851
c18487ee 1852 msleep(5);
a2fbb9ea 1853 }
c18487ee
YR		 1854 DP(NETIF_MSG_HW, "Timeout\n");
1855 return -EAGAIN;
1856}
a2fbb9ea 1857
c9ee9206
VZ		 1858int bnx2x_release_leader_lock(struct bnx2x *bp)
1859{
1860 return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1861}
1862
9f6c9258 1863int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
c18487ee
YR		 1864{
1865 u32 lock_status;
1866 u32 resource_bit = (1 << resource);
4a37fb66
YG		 1867 int func = BP_FUNC(bp);
1868 u32 hw_lock_control_reg;
a2fbb9ea 1869
72fd0718
VZ		 1870 DP(NETIF_MSG_HW, "Releasing a lock on resource %d\n", resource);
1871
c18487ee
YR		 1872 /* Validating that the resource is within range */
1873 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1874 DP(NETIF_MSG_HW,
1875 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1876 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1877 return -EINVAL;
1878 }
1879
4a37fb66
YG		 1880 if (func <= 5) {
1881 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1882 } else {
1883 hw_lock_control_reg =
1884 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1885 }
1886
c18487ee 1887 /* Validating that the resource is currently taken */
4a37fb66 1888 lock_status = REG_RD(bp, hw_lock_control_reg);
c18487ee
YR		 1889 if (!(lock_status & resource_bit)) {
1890 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n",
1891 lock_status, resource_bit);
1892 return -EFAULT;
a2fbb9ea
ET		 1893 }
1894
9f6c9258
DK		 1895 REG_WR(bp, hw_lock_control_reg, resource_bit);
1896 return 0;
c18487ee 1897}
a2fbb9ea 1898
9f6c9258 1899
4acac6a5
EG		 1900int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
1901{
1902 /* The GPIO should be swapped if swap register is set and active */
1903 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1904 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1905 int gpio_shift = gpio_num +
1906 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1907 u32 gpio_mask = (1 << gpio_shift);
1908 u32 gpio_reg;
1909 int value;
1910
1911 if (gpio_num > MISC_REGISTERS_GPIO_3) {
1912 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1913 return -EINVAL;
1914 }
1915
1916 /* read GPIO value */
1917 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
1918
1919 /* get the requested pin value */
1920 if ((gpio_reg & gpio_mask) == gpio_mask)
1921 value = 1;
1922 else
1923 value = 0;
1924
1925 DP(NETIF_MSG_LINK, "pin %d value 0x%x\n", gpio_num, value);
1926
1927 return value;
1928}
1929
17de50b7 1930int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
c18487ee
YR		 1931{
1932 /* The GPIO should be swapped if swap register is set and active */
1933 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
17de50b7 1934 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
c18487ee
YR		 1935 int gpio_shift = gpio_num +
1936 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1937 u32 gpio_mask = (1 << gpio_shift);
1938 u32 gpio_reg;
a2fbb9ea 1939
c18487ee
YR		 1940 if (gpio_num > MISC_REGISTERS_GPIO_3) {
1941 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1942 return -EINVAL;
1943 }
a2fbb9ea 1944
4a37fb66 1945 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
c18487ee
YR		 1946 /* read GPIO and mask except the float bits */
1947 gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
a2fbb9ea 1948
c18487ee
YR		 1949 switch (mode) {
1950 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
1951 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output low\n",
1952 gpio_num, gpio_shift);
1953 /* clear FLOAT and set CLR */
1954 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1955 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
1956 break;
a2fbb9ea 1957
c18487ee
YR		 1958 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
1959 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output high\n",
1960 gpio_num, gpio_shift);
1961 /* clear FLOAT and set SET */
1962 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1963 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
1964 break;
a2fbb9ea 1965
17de50b7 1966 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
c18487ee
YR		 1967 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> input\n",
1968 gpio_num, gpio_shift);
1969 /* set FLOAT */
1970 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1971 break;
a2fbb9ea 1972
c18487ee
YR		 1973 default:
1974 break;
a2fbb9ea
ET		 1975 }
1976
c18487ee 1977 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
4a37fb66 1978 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
f1410647 1979
c18487ee 1980 return 0;
a2fbb9ea
ET		 1981}
1982
0d40f0d4
YR		 1983int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode)
1984{
1985 u32 gpio_reg = 0;
1986 int rc = 0;
1987
1988 /* Any port swapping should be handled by caller. */
1989
1990 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1991 /* read GPIO and mask except the float bits */
1992 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
1993 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
1994 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
1995 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
1996
1997 switch (mode) {
1998 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
1999 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins);
2000 /* set CLR */
2001 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
2002 break;
2003
2004 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2005 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins);
2006 /* set SET */
2007 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
2008 break;
2009
2010 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2011 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins);
2012 /* set FLOAT */
2013 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2014 break;
2015
2016 default:
2017 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode);
2018 rc = -EINVAL;
2019 break;
2020 }
2021
2022 if (rc == 0)
2023 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2024
2025 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2026
2027 return rc;
2028}
2029
4acac6a5
EG		 2030int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2031{
2032 /* The GPIO should be swapped if swap register is set and active */
2033 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2034 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2035 int gpio_shift = gpio_num +
2036 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2037 u32 gpio_mask = (1 << gpio_shift);
2038 u32 gpio_reg;
2039
2040 if (gpio_num > MISC_REGISTERS_GPIO_3) {
2041 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2042 return -EINVAL;
2043 }
2044
2045 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2046 /* read GPIO int */
2047 gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);
2048
2049 switch (mode) {
2050 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
2051 DP(NETIF_MSG_LINK, "Clear GPIO INT %d (shift %d) -> "
2052 "output low\n", gpio_num, gpio_shift);
2053 /* clear SET and set CLR */
2054 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2055 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2056 break;
2057
2058 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
2059 DP(NETIF_MSG_LINK, "Set GPIO INT %d (shift %d) -> "
2060 "output high\n", gpio_num, gpio_shift);
2061 /* clear CLR and set SET */
2062 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2063 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2064 break;
2065
2066 default:
2067 break;
2068 }
2069
2070 REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg);
2071 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2072
2073 return 0;
2074}
2075
c18487ee 2076static int bnx2x_set_spio(struct bnx2x *bp, int spio_num, u32 mode)
a2fbb9ea 2077{
c18487ee
YR		 2078 u32 spio_mask = (1 << spio_num);
2079 u32 spio_reg;
a2fbb9ea 2080
c18487ee
YR		 2081 if ((spio_num < MISC_REGISTERS_SPIO_4) ||
2082 (spio_num > MISC_REGISTERS_SPIO_7)) {
2083 BNX2X_ERR("Invalid SPIO %d\n", spio_num);
2084 return -EINVAL;
a2fbb9ea
ET		 2085 }
2086
4a37fb66 2087 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
c18487ee
YR		 2088 /* read SPIO and mask except the float bits */
2089 spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_REGISTERS_SPIO_FLOAT);
a2fbb9ea 2090
c18487ee 2091 switch (mode) {
6378c025 2092 case MISC_REGISTERS_SPIO_OUTPUT_LOW:
c18487ee
YR		 2093 DP(NETIF_MSG_LINK, "Set SPIO %d -> output low\n", spio_num);
2094 /* clear FLOAT and set CLR */
2095 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
2096 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_CLR_POS);
2097 break;
a2fbb9ea 2098
6378c025 2099 case MISC_REGISTERS_SPIO_OUTPUT_HIGH:
c18487ee
YR		 2100 DP(NETIF_MSG_LINK, "Set SPIO %d -> output high\n", spio_num);
2101 /* clear FLOAT and set SET */
2102 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
2103 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_SET_POS);
2104 break;
a2fbb9ea 2105
c18487ee
YR		 2106 case MISC_REGISTERS_SPIO_INPUT_HI_Z:
2107 DP(NETIF_MSG_LINK, "Set SPIO %d -> input\n", spio_num);
2108 /* set FLOAT */
2109 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
2110 break;
a2fbb9ea 2111
c18487ee
YR		 2112 default:
2113 break;
a2fbb9ea
ET		 2114 }
2115
c18487ee 2116 REG_WR(bp, MISC_REG_SPIO, spio_reg);
4a37fb66 2117 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
c18487ee 2118
a2fbb9ea
ET		 2119 return 0;
2120}
2121
9f6c9258 2122void bnx2x_calc_fc_adv(struct bnx2x *bp)
a2fbb9ea 2123{
a22f0788 2124 u8 cfg_idx = bnx2x_get_link_cfg_idx(bp);
ad33ea3a
EG		 2125 switch (bp->link_vars.ieee_fc &
2126 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
c18487ee 2127 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
a22f0788 2128 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
f85582f8 2129 ADVERTISED_Pause);
c18487ee 2130 break;
356e2385 2131
c18487ee 2132 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
a22f0788 2133 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
f85582f8 2134 ADVERTISED_Pause);
c18487ee 2135 break;
356e2385 2136
c18487ee 2137 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
a22f0788 2138 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
c18487ee 2139 break;
356e2385 2140
c18487ee 2141 default:
a22f0788 2142 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
f85582f8 2143 ADVERTISED_Pause);
c18487ee
YR		 2144 break;
2145 }
2146}
f1410647 2147
9f6c9258 2148u8 bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
c18487ee 2149{
19680c48
EG		 2150 if (!BP_NOMCP(bp)) {
2151 u8 rc;
a22f0788
YR		 2152 int cfx_idx = bnx2x_get_link_cfg_idx(bp);
2153 u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx];
19680c48 2154 /* Initialize link parameters structure variables */
8c99e7b0
YR		 2155 /* It is recommended to turn off RX FC for jumbo frames
2156 for better performance */
f2e0899f 2157 if ((CHIP_IS_E1x(bp)) && (bp->dev->mtu > 5000))
c0700f90 2158 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
8c99e7b0 2159 else
c0700f90 2160 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
a2fbb9ea 2161
4a37fb66 2162 bnx2x_acquire_phy_lock(bp);
b5bf9068 2163
a22f0788 2164 if (load_mode == LOAD_DIAG) {
de6eae1f 2165 bp->link_params.loopback_mode = LOOPBACK_XGXS;
a22f0788
YR		 2166 bp->link_params.req_line_speed[cfx_idx] = SPEED_10000;
2167 }
b5bf9068 2168
19680c48 2169 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
b5bf9068 2170
4a37fb66 2171 bnx2x_release_phy_lock(bp);
a2fbb9ea 2172
3c96c68b
EG		 2173 bnx2x_calc_fc_adv(bp);
2174
b5bf9068
EG		 2175 if (CHIP_REV_IS_SLOW(bp) && bp->link_vars.link_up) {
2176 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
19680c48 2177 bnx2x_link_report(bp);
3deb8167
YR		 2178 } else
2179 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
a22f0788 2180 bp->link_params.req_line_speed[cfx_idx] = req_line_speed;
19680c48
EG		 2181 return rc;
2182 }
f5372251 2183 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
19680c48 2184 return -EINVAL;
a2fbb9ea
ET		 2185}
2186
9f6c9258 2187void bnx2x_link_set(struct bnx2x *bp)
a2fbb9ea 2188{
19680c48 2189 if (!BP_NOMCP(bp)) {
4a37fb66 2190 bnx2x_acquire_phy_lock(bp);
54c2fb78 2191 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
19680c48 2192 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
4a37fb66 2193 bnx2x_release_phy_lock(bp);
a2fbb9ea 2194
19680c48
EG		 2195 bnx2x_calc_fc_adv(bp);
2196 } else
f5372251 2197 BNX2X_ERR("Bootcode is missing - can not set link\n");
c18487ee 2198}
a2fbb9ea 2199
c18487ee
YR		 2200static void bnx2x__link_reset(struct bnx2x *bp)
2201{
19680c48 2202 if (!BP_NOMCP(bp)) {
4a37fb66 2203 bnx2x_acquire_phy_lock(bp);
589abe3a 2204 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
4a37fb66 2205 bnx2x_release_phy_lock(bp);
19680c48 2206 } else
f5372251 2207 BNX2X_ERR("Bootcode is missing - can not reset link\n");
c18487ee 2208}
a2fbb9ea 2209
a22f0788 2210u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes)
c18487ee 2211{
2145a920 2212 u8 rc = 0;
a2fbb9ea 2213
2145a920
VZ		 2214 if (!BP_NOMCP(bp)) {
2215 bnx2x_acquire_phy_lock(bp);
a22f0788
YR		 2216 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars,
2217 is_serdes);
2145a920
VZ		 2218 bnx2x_release_phy_lock(bp);
2219 } else
2220 BNX2X_ERR("Bootcode is missing - can not test link\n");
a2fbb9ea 2221
c18487ee
YR		 2222 return rc;
2223}
a2fbb9ea 2224
8a1c38d1 2225static void bnx2x_init_port_minmax(struct bnx2x *bp)
34f80b04 2226{
8a1c38d1
EG		 2227 u32 r_param = bp->link_vars.line_speed / 8;
2228 u32 fair_periodic_timeout_usec;
2229 u32 t_fair;
34f80b04 2230
8a1c38d1
EG		 2231 memset(&(bp->cmng.rs_vars), 0,
2232 sizeof(struct rate_shaping_vars_per_port));
2233 memset(&(bp->cmng.fair_vars), 0, sizeof(struct fairness_vars_per_port));
34f80b04 2234
8a1c38d1
EG		 2235 /* 100 usec in SDM ticks = 25 since each tick is 4 usec */
2236 bp->cmng.rs_vars.rs_periodic_timeout = RS_PERIODIC_TIMEOUT_USEC / 4;
34f80b04 2237
8a1c38d1
EG		 2238 /* this is the threshold below which no timer arming will occur
2239 1.25 coefficient is for the threshold to be a little bigger
2240 than the real time, to compensate for timer in-accuracy */
2241 bp->cmng.rs_vars.rs_threshold =
34f80b04
EG		 2242 (RS_PERIODIC_TIMEOUT_USEC * r_param * 5) / 4;
2243
8a1c38d1
EG		 2244 /* resolution of fairness timer */
2245 fair_periodic_timeout_usec = QM_ARB_BYTES / r_param;
2246 /* for 10G it is 1000usec. for 1G it is 10000usec. */
2247 t_fair = T_FAIR_COEF / bp->link_vars.line_speed;
34f80b04 2248
8a1c38d1
EG		 2249 /* this is the threshold below which we won't arm the timer anymore */
2250 bp->cmng.fair_vars.fair_threshold = QM_ARB_BYTES;
34f80b04 2251
8a1c38d1
EG		 2252 /* we multiply by 1e3/8 to get bytes/msec.
2253 We don't want the credits to pass a credit
2254 of the t_fair*FAIR_MEM (algorithm resolution) */
2255 bp->cmng.fair_vars.upper_bound = r_param * t_fair * FAIR_MEM;
2256 /* since each tick is 4 usec */
2257 bp->cmng.fair_vars.fairness_timeout = fair_periodic_timeout_usec / 4;
34f80b04
EG		 2258}
2259
2691d51d
EG		 2260/* Calculates the sum of vn_min_rates.
2261 It's needed for further normalizing of the min_rates.
2262 Returns:
2263 sum of vn_min_rates.
2264 or
2265 0 - if all the min_rates are 0.
2266 In the later case fainess algorithm should be deactivated.
2267 If not all min_rates are zero then those that are zeroes will be set to 1.
2268 */
2269static void bnx2x_calc_vn_weight_sum(struct bnx2x *bp)
2270{
2271 int all_zero = 1;
2691d51d
EG		 2272 int vn;
2273
2274 bp->vn_weight_sum = 0;
2275 for (vn = VN_0; vn < E1HVN_MAX; vn++) {
f2e0899f 2276 u32 vn_cfg = bp->mf_config[vn];
2691d51d
EG		 2277 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2278 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2279
2280 /* Skip hidden vns */
2281 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2282 continue;
2283
2284 /* If min rate is zero - set it to 1 */
2285 if (!vn_min_rate)
2286 vn_min_rate = DEF_MIN_RATE;
2287 else
2288 all_zero = 0;
2289
2290 bp->vn_weight_sum += vn_min_rate;
2291 }
2292
30ae438b
DK		 2293 /* if ETS or all min rates are zeros - disable fairness */
2294 if (BNX2X_IS_ETS_ENABLED(bp)) {
2295 bp->cmng.flags.cmng_enables &=
2296 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2297 DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n");
2298 } else if (all_zero) {
b015e3d1
EG		 2299 bp->cmng.flags.cmng_enables &=
2300 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2301 DP(NETIF_MSG_IFUP, "All MIN values are zeroes"
2302 " fairness will be disabled\n");
2303 } else
2304 bp->cmng.flags.cmng_enables |=
2305 CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2691d51d
EG		 2306}
2307
f2e0899f 2308static void bnx2x_init_vn_minmax(struct bnx2x *bp, int vn)
34f80b04
EG		 2309{
2310 struct rate_shaping_vars_per_vn m_rs_vn;
2311 struct fairness_vars_per_vn m_fair_vn;
f2e0899f
DK		 2312 u32 vn_cfg = bp->mf_config[vn];
2313 int func = 2*vn + BP_PORT(bp);
34f80b04
EG		 2314 u16 vn_min_rate, vn_max_rate;
2315 int i;
2316
2317 /* If function is hidden - set min and max to zeroes */
2318 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
2319 vn_min_rate = 0;
2320 vn_max_rate = 0;
2321
2322 } else {
faa6fcbb
DK		 2323 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg);
2324
34f80b04
EG		 2325 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2326 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
faa6fcbb
DK		 2327 /* If fairness is enabled (not all min rates are zeroes) and
2328 if current min rate is zero - set it to 1.
2329 This is a requirement of the algorithm. */
f2e0899f 2330 if (bp->vn_weight_sum && (vn_min_rate == 0))
34f80b04 2331 vn_min_rate = DEF_MIN_RATE;
faa6fcbb
DK		 2332
2333 if (IS_MF_SI(bp))
2334 /* maxCfg in percents of linkspeed */
2335 vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100;
2336 else
2337 /* maxCfg is absolute in 100Mb units */
2338 vn_max_rate = maxCfg * 100;
34f80b04 2339 }
f85582f8 2340
8a1c38d1 2341 DP(NETIF_MSG_IFUP,
b015e3d1 2342 "func %d: vn_min_rate %d vn_max_rate %d vn_weight_sum %d\n",
8a1c38d1 2343 func, vn_min_rate, vn_max_rate, bp->vn_weight_sum);
34f80b04
EG		 2344
2345 memset(&m_rs_vn, 0, sizeof(struct rate_shaping_vars_per_vn));
2346 memset(&m_fair_vn, 0, sizeof(struct fairness_vars_per_vn));
2347
2348 /* global vn counter - maximal Mbps for this vn */
2349 m_rs_vn.vn_counter.rate = vn_max_rate;
2350
2351 /* quota - number of bytes transmitted in this period */
2352 m_rs_vn.vn_counter.quota =
2353 (vn_max_rate * RS_PERIODIC_TIMEOUT_USEC) / 8;
2354
8a1c38d1 2355 if (bp->vn_weight_sum) {
34f80b04
EG		 2356 /* credit for each period of the fairness algorithm:
2357 number of bytes in T_FAIR (the vn share the port rate).
8a1c38d1
EG		 2358 vn_weight_sum should not be larger than 10000, thus
2359 T_FAIR_COEF / (8 * vn_weight_sum) will always be greater
2360 than zero */
34f80b04 2361 m_fair_vn.vn_credit_delta =
cdaa7cb8
VZ		 2362 max_t(u32, (vn_min_rate * (T_FAIR_COEF /
2363 (8 * bp->vn_weight_sum))),
ff80ee02
DK		 2364 (bp->cmng.fair_vars.fair_threshold +
2365 MIN_ABOVE_THRESH));
cdaa7cb8 2366 DP(NETIF_MSG_IFUP, "m_fair_vn.vn_credit_delta %d\n",
34f80b04
EG		 2367 m_fair_vn.vn_credit_delta);
2368 }
2369
34f80b04
EG		 2370 /* Store it to internal memory */
2371 for (i = 0; i < sizeof(struct rate_shaping_vars_per_vn)/4; i++)
2372 REG_WR(bp, BAR_XSTRORM_INTMEM +
2373 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func) + i * 4,
2374 ((u32 *)(&m_rs_vn))[i]);
2375
2376 for (i = 0; i < sizeof(struct fairness_vars_per_vn)/4; i++)
2377 REG_WR(bp, BAR_XSTRORM_INTMEM +
2378 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func) + i * 4,
2379 ((u32 *)(&m_fair_vn))[i]);
2380}
f85582f8 2381
523224a3
DK		 2382static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp)
2383{
2384 if (CHIP_REV_IS_SLOW(bp))
2385 return CMNG_FNS_NONE;
fb3bff17 2386 if (IS_MF(bp))
523224a3
DK		 2387 return CMNG_FNS_MINMAX;
2388
2389 return CMNG_FNS_NONE;
2390}
2391
2ae17f66 2392void bnx2x_read_mf_cfg(struct bnx2x *bp)
523224a3 2393{
0793f83f 2394 int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1);
523224a3
DK		 2395
2396 if (BP_NOMCP(bp))
2397 return; /* what should be the default bvalue in this case */
2398
0793f83f
DK		 2399 /* For 2 port configuration the absolute function number formula
2400 * is:
2401 * abs_func = 2 * vn + BP_PORT + BP_PATH
2402 *
2403 * and there are 4 functions per port
2404 *
2405 * For 4 port configuration it is
2406 * abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2407 *
2408 * and there are 2 functions per port
2409 */
523224a3 2410 for (vn = VN_0; vn < E1HVN_MAX; vn++) {
0793f83f
DK		 2411 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
2412
2413 if (func >= E1H_FUNC_MAX)
2414 break;
2415
f2e0899f 2416 bp->mf_config[vn] =
523224a3
DK		 2417 MF_CFG_RD(bp, func_mf_config[func].config);
2418 }
2419}
2420
2421static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)
2422{
2423
2424 if (cmng_type == CMNG_FNS_MINMAX) {
2425 int vn;
2426
2427 /* clear cmng_enables */
2428 bp->cmng.flags.cmng_enables = 0;
2429
2430 /* read mf conf from shmem */
2431 if (read_cfg)
2432 bnx2x_read_mf_cfg(bp);
2433
2434 /* Init rate shaping and fairness contexts */
2435 bnx2x_init_port_minmax(bp);
2436
2437 /* vn_weight_sum and enable fairness if not 0 */
2438 bnx2x_calc_vn_weight_sum(bp);
2439
2440 /* calculate and set min-max rate for each vn */
c4154f25
DK		 2441 if (bp->port.pmf)
2442 for (vn = VN_0; vn < E1HVN_MAX; vn++)
2443 bnx2x_init_vn_minmax(bp, vn);
523224a3
DK		 2444
2445 /* always enable rate shaping and fairness */
2446 bp->cmng.flags.cmng_enables |=
2447 CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
2448 if (!bp->vn_weight_sum)
2449 DP(NETIF_MSG_IFUP, "All MIN values are zeroes"
2450 " fairness will be disabled\n");
2451 return;
2452 }
2453
2454 /* rate shaping and fairness are disabled */
2455 DP(NETIF_MSG_IFUP,
2456 "rate shaping and fairness are disabled\n");
2457}
34f80b04 2458
523224a3
DK		 2459static inline void bnx2x_link_sync_notify(struct bnx2x *bp)
2460{
2461 int port = BP_PORT(bp);
2462 int func;
2463 int vn;
2464
2465 /* Set the attention towards other drivers on the same port */
2466 for (vn = VN_0; vn < E1HVN_MAX; vn++) {
2467 if (vn == BP_E1HVN(bp))
2468 continue;
2469
2470 func = ((vn << 1) | port);
2471 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_0 +
2472 (LINK_SYNC_ATTENTION_BIT_FUNC_0 + func)*4, 1);
2473 }
2474}
8a1c38d1 2475
c18487ee
YR		 2476/* This function is called upon link interrupt */
2477static void bnx2x_link_attn(struct bnx2x *bp)
2478{
bb2a0f7a
YG		 2479 /* Make sure that we are synced with the current statistics */
2480 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2481
c18487ee 2482 bnx2x_link_update(&bp->link_params, &bp->link_vars);
a2fbb9ea 2483
bb2a0f7a
YG		 2484 if (bp->link_vars.link_up) {
2485
1c06328c 2486 /* dropless flow control */
f2e0899f 2487 if (!CHIP_IS_E1(bp) && bp->dropless_fc) {
1c06328c
EG		 2488 int port = BP_PORT(bp);
2489 u32 pause_enabled = 0;
2490
2491 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
2492 pause_enabled = 1;
2493
2494 REG_WR(bp, BAR_USTRORM_INTMEM +
ca00392c 2495 USTORM_ETH_PAUSE_ENABLED_OFFSET(port),
1c06328c
EG		 2496 pause_enabled);
2497 }
2498
619c5cb6 2499 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) {
bb2a0f7a
YG		 2500 struct host_port_stats *pstats;
2501
2502 pstats = bnx2x_sp(bp, port_stats);
619c5cb6 2503 /* reset old mac stats */
bb2a0f7a
YG		 2504 memset(&(pstats->mac_stx[0]), 0,
2505 sizeof(struct mac_stx));
2506 }
f34d28ea 2507 if (bp->state == BNX2X_STATE_OPEN)
bb2a0f7a
YG		 2508 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2509 }
2510
f2e0899f
DK		 2511 if (bp->link_vars.link_up && bp->link_vars.line_speed) {
2512 int cmng_fns = bnx2x_get_cmng_fns_mode(bp);
8a1c38d1 2513
f2e0899f
DK		 2514 if (cmng_fns != CMNG_FNS_NONE) {
2515 bnx2x_cmng_fns_init(bp, false, cmng_fns);
2516 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2517 } else
2518 /* rate shaping and fairness are disabled */
2519 DP(NETIF_MSG_IFUP,
2520 "single function mode without fairness\n");
34f80b04 2521 }
9fdc3e95 2522
2ae17f66
VZ		 2523 __bnx2x_link_report(bp);
2524
9fdc3e95
DK		 2525 if (IS_MF(bp))
2526 bnx2x_link_sync_notify(bp);
c18487ee 2527}
a2fbb9ea 2528
9f6c9258 2529void bnx2x__link_status_update(struct bnx2x *bp)
c18487ee 2530{
2ae17f66 2531 if (bp->state != BNX2X_STATE_OPEN)
c18487ee 2532 return;
a2fbb9ea 2533
c18487ee 2534 bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
a2fbb9ea 2535
bb2a0f7a
YG		 2536 if (bp->link_vars.link_up)
2537 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2538 else
2539 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2540
c18487ee
YR		 2541 /* indicate link status */
2542 bnx2x_link_report(bp);
a2fbb9ea 2543}
a2fbb9ea 2544
34f80b04
EG		 2545static void bnx2x_pmf_update(struct bnx2x *bp)
2546{
2547 int port = BP_PORT(bp);
2548 u32 val;
2549
2550 bp->port.pmf = 1;
2551 DP(NETIF_MSG_LINK, "pmf %d\n", bp->port.pmf);
2552
3deb8167
YR		 2553 /*
2554 * We need the mb() to ensure the ordering between the writing to
2555 * bp->port.pmf here and reading it from the bnx2x_periodic_task().
2556 */
2557 smp_mb();
2558
2559 /* queue a periodic task */
2560 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2561
ef01854e
DK		 2562 bnx2x_dcbx_pmf_update(bp);
2563
34f80b04
EG		 2564 /* enable nig attention */
2565 val = (0xff0f | (1 << (BP_E1HVN(bp) + 4)));
f2e0899f
DK		 2566 if (bp->common.int_block == INT_BLOCK_HC) {
2567 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2568 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
619c5cb6 2569 } else if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 2570 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
2571 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
2572 }
bb2a0f7a
YG		 2573
2574 bnx2x_stats_handle(bp, STATS_EVENT_PMF);
34f80b04
EG		 2575}
2576
c18487ee 2577/* end of Link */
a2fbb9ea
ET		 2578
2579/* slow path */
2580
2581/*
2582 * General service functions
2583 */
2584
2691d51d 2585/* send the MCP a request, block until there is a reply */
a22f0788 2586u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param)
2691d51d 2587{
f2e0899f 2588 int mb_idx = BP_FW_MB_IDX(bp);
a5971d43 2589 u32 seq;
2691d51d
EG		 2590 u32 rc = 0;
2591 u32 cnt = 1;
2592 u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
2593
c4ff7cbf 2594 mutex_lock(&bp->fw_mb_mutex);
a5971d43 2595 seq = ++bp->fw_seq;
f2e0899f
DK		 2596 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param);
2597 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq));
2598
754a2f52
DK		 2599 DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n",
2600 (command | seq), param);
2691d51d
EG		 2601
2602 do {
2603 /* let the FW do it's magic ... */
2604 msleep(delay);
2605
f2e0899f 2606 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header);
2691d51d 2607
c4ff7cbf
EG		 2608 /* Give the FW up to 5 second (500*10ms) */
2609 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
2691d51d
EG		 2610
2611 DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
2612 cnt*delay, rc, seq);
2613
2614 /* is this a reply to our command? */
2615 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK))
2616 rc &= FW_MSG_CODE_MASK;
2617 else {
2618 /* FW BUG! */
2619 BNX2X_ERR("FW failed to respond!\n");
2620 bnx2x_fw_dump(bp);
2621 rc = 0;
2622 }
c4ff7cbf 2623 mutex_unlock(&bp->fw_mb_mutex);
2691d51d
EG		 2624
2625 return rc;
2626}
2627
ec6ba945
VZ		 2628static u8 stat_counter_valid(struct bnx2x *bp, struct bnx2x_fastpath *fp)
2629{
2630#ifdef BCM_CNIC
619c5cb6
VZ		 2631 /* Statistics are not supported for CNIC Clients at the moment */
2632 if (IS_FCOE_FP(fp))
ec6ba945
VZ		 2633 return false;
2634#endif
2635 return true;
2636}
2637
619c5cb6
VZ		 2638void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p)
2639{
2640 if (CHIP_IS_E1x(bp)) {
2641 struct tstorm_eth_function_common_config tcfg = {0};
2642
2643 storm_memset_func_cfg(bp, &tcfg, p->func_id);
2644 }
2645
2646 /* Enable the function in the FW */
2647 storm_memset_vf_to_pf(bp, p->func_id, p->pf_id);
2648 storm_memset_func_en(bp, p->func_id, 1);
2649
2650 /* spq */
2651 if (p->func_flgs & FUNC_FLG_SPQ) {
2652 storm_memset_spq_addr(bp, p->spq_map, p->func_id);
2653 REG_WR(bp, XSEM_REG_FAST_MEMORY +
2654 XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod);
2655 }
2656}
2657
6383c0b3
AE		 2658/**
2659 * bnx2x_get_tx_only_flags - Return common flags
2660 *
2661 * @bp device handle
2662 * @fp queue handle
2663 * @zero_stats TRUE if statistics zeroing is needed
2664 *
2665 * Return the flags that are common for the Tx-only and not normal connections.
2666 */
2667static inline unsigned long bnx2x_get_common_flags(struct bnx2x *bp,
2668 struct bnx2x_fastpath *fp,
2669 bool zero_stats)
28912902 2670{
619c5cb6
VZ		 2671 unsigned long flags = 0;
2672
2673 /* PF driver will always initialize the Queue to an ACTIVE state */
2674 __set_bit(BNX2X_Q_FLG_ACTIVE, &flags);
28912902 2675
6383c0b3
AE		 2676 /* tx only connections collect statistics (on the same index as the
2677 * parent connection). The statistics are zeroed when the parent
2678 * connection is initialized.
2679 */
2680 if (stat_counter_valid(bp, fp)) {
2681 __set_bit(BNX2X_Q_FLG_STATS, &flags);
2682 if (zero_stats)
2683 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags);
2684 }
2685
2686 return flags;
2687}
2688
2689static inline unsigned long bnx2x_get_q_flags(struct bnx2x *bp,
2690 struct bnx2x_fastpath *fp,
2691 bool leading)
2692{
2693 unsigned long flags = 0;
2694
619c5cb6
VZ		 2695 /* calculate other queue flags */
2696 if (IS_MF_SD(bp))
2697 __set_bit(BNX2X_Q_FLG_OV, &flags);
28912902 2698
619c5cb6
VZ		 2699 if (IS_FCOE_FP(fp))
2700 __set_bit(BNX2X_Q_FLG_FCOE, &flags);
523224a3
DK		 2701
2702 if (!fp->disable_tpa)
619c5cb6
VZ		 2703 __set_bit(BNX2X_Q_FLG_TPA, &flags);
2704
619c5cb6
VZ		 2705 if (leading) {
2706 __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags);
2707 __set_bit(BNX2X_Q_FLG_MCAST, &flags);
2708 }
523224a3 2709
619c5cb6
VZ		 2710 /* Always set HW VLAN stripping */
2711 __set_bit(BNX2X_Q_FLG_VLAN, &flags);
523224a3 2712
6383c0b3
AE		 2713
2714 return flags | bnx2x_get_common_flags(bp, fp, true);
523224a3
DK		 2715}
2716
619c5cb6 2717static void bnx2x_pf_q_prep_general(struct bnx2x *bp,
6383c0b3
AE		 2718 struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init,
2719 u8 cos)
619c5cb6
VZ		 2720{
2721 gen_init->stat_id = bnx2x_stats_id(fp);
2722 gen_init->spcl_id = fp->cl_id;
2723
2724 /* Always use mini-jumbo MTU for FCoE L2 ring */
2725 if (IS_FCOE_FP(fp))
2726 gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU;
2727 else
2728 gen_init->mtu = bp->dev->mtu;
6383c0b3
AE		 2729
2730 gen_init->cos = cos;
619c5cb6
VZ		 2731}
2732
2733static void bnx2x_pf_rx_q_prep(struct bnx2x *bp,
523224a3 2734 struct bnx2x_fastpath *fp, struct rxq_pause_params *pause,
619c5cb6 2735 struct bnx2x_rxq_setup_params *rxq_init)
523224a3 2736{
619c5cb6 2737 u8 max_sge = 0;
523224a3
DK		 2738 u16 sge_sz = 0;
2739 u16 tpa_agg_size = 0;
2740
523224a3
DK		 2741 if (!fp->disable_tpa) {
2742 pause->sge_th_hi = 250;
2743 pause->sge_th_lo = 150;
2744 tpa_agg_size = min_t(u32,
2745 (min_t(u32, 8, MAX_SKB_FRAGS) *
2746 SGE_PAGE_SIZE * PAGES_PER_SGE), 0xffff);
2747 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >>
2748 SGE_PAGE_SHIFT;
2749 max_sge = ((max_sge + PAGES_PER_SGE - 1) &
2750 (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT;
2751 sge_sz = (u16)min_t(u32, SGE_PAGE_SIZE * PAGES_PER_SGE,
2752 0xffff);
2753 }
2754
2755 /* pause - not for e1 */
2756 if (!CHIP_IS_E1(bp)) {
2757 pause->bd_th_hi = 350;
2758 pause->bd_th_lo = 250;
2759 pause->rcq_th_hi = 350;
2760 pause->rcq_th_lo = 250;
619c5cb6 2761
523224a3
DK		 2762 pause->pri_map = 1;
2763 }
2764
2765 /* rxq setup */
523224a3
DK		 2766 rxq_init->dscr_map = fp->rx_desc_mapping;
2767 rxq_init->sge_map = fp->rx_sge_mapping;
2768 rxq_init->rcq_map = fp->rx_comp_mapping;
2769 rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE;
a8c94b91 2770
619c5cb6
VZ		 2771 /* This should be a maximum number of data bytes that may be
2772 * placed on the BD (not including paddings).
2773 */
2774 rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN -
2775 IP_HEADER_ALIGNMENT_PADDING;
a8c94b91 2776
523224a3 2777 rxq_init->cl_qzone_id = fp->cl_qzone_id;
523224a3
DK		 2778 rxq_init->tpa_agg_sz = tpa_agg_size;
2779 rxq_init->sge_buf_sz = sge_sz;
2780 rxq_init->max_sges_pkt = max_sge;
619c5cb6
VZ		 2781 rxq_init->rss_engine_id = BP_FUNC(bp);
2782
2783 /* Maximum number or simultaneous TPA aggregation for this Queue.
2784 *
2785 * For PF Clients it should be the maximum avaliable number.
2786 * VF driver(s) may want to define it to a smaller value.
2787 */
2788 rxq_init->max_tpa_queues =
2789 (CHIP_IS_E1(bp) ? ETH_MAX_AGGREGATION_QUEUES_E1 :
2790 ETH_MAX_AGGREGATION_QUEUES_E1H_E2);
2791
523224a3
DK		 2792 rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
2793 rxq_init->fw_sb_id = fp->fw_sb_id;
2794
ec6ba945
VZ		 2795 if (IS_FCOE_FP(fp))
2796 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS;
2797 else
6383c0b3 2798 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
523224a3
DK		 2799}
2800
619c5cb6 2801static void bnx2x_pf_tx_q_prep(struct bnx2x *bp,
6383c0b3
AE		 2802 struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init,
2803 u8 cos)
523224a3 2804{
6383c0b3
AE		 2805 txq_init->dscr_map = fp->txdata[cos].tx_desc_mapping;
2806 txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
523224a3
DK		 2807 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
2808 txq_init->fw_sb_id = fp->fw_sb_id;
ec6ba945 2809
619c5cb6
VZ		 2810 /*
2811 * set the tss leading client id for TX classfication ==
2812 * leading RSS client id
2813 */
2814 txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id);
2815
ec6ba945
VZ		 2816 if (IS_FCOE_FP(fp)) {
2817 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS;
2818 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE;
2819 }
523224a3
DK		 2820}
2821
8d96286a 2822static void bnx2x_pf_init(struct bnx2x *bp)
523224a3
DK		 2823{
2824 struct bnx2x_func_init_params func_init = {0};
523224a3
DK		 2825 struct event_ring_data eq_data = { {0} };
2826 u16 flags;
2827
619c5cb6 2828 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 2829 /* reset IGU PF statistics: MSIX + ATTN */
2830 /* PF */
2831 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
2832 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
2833 (CHIP_MODE_IS_4_PORT(bp) ?
2834 BP_FUNC(bp) : BP_VN(bp))*4, 0);
2835 /* ATTN */
2836 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
2837 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
2838 BNX2X_IGU_STAS_MSG_PF_CNT*4 +
2839 (CHIP_MODE_IS_4_PORT(bp) ?
2840 BP_FUNC(bp) : BP_VN(bp))*4, 0);
2841 }
2842
523224a3
DK		 2843 /* function setup flags */
2844 flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
2845
619c5cb6
VZ		 2846 /* This flag is relevant for E1x only.
2847 * E2 doesn't have a TPA configuration in a function level.
523224a3 2848 */
619c5cb6 2849 flags |= (bp->flags & TPA_ENABLE_FLAG) ? FUNC_FLG_TPA : 0;
523224a3
DK		 2850
2851 func_init.func_flgs = flags;
2852 func_init.pf_id = BP_FUNC(bp);
2853 func_init.func_id = BP_FUNC(bp);
523224a3
DK		 2854 func_init.spq_map = bp->spq_mapping;
2855 func_init.spq_prod = bp->spq_prod_idx;
2856
2857 bnx2x_func_init(bp, &func_init);
2858
2859 memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
2860
2861 /*
619c5cb6
VZ		 2862 * Congestion management values depend on the link rate
2863 * There is no active link so initial link rate is set to 10 Gbps.
2864 * When the link comes up The congestion management values are
2865 * re-calculated according to the actual link rate.
2866 */
523224a3
DK		 2867 bp->link_vars.line_speed = SPEED_10000;
2868 bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp));
2869
2870 /* Only the PMF sets the HW */
2871 if (bp->port.pmf)
2872 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2873
523224a3
DK		 2874 /* init Event Queue */
2875 eq_data.base_addr.hi = U64_HI(bp->eq_mapping);
2876 eq_data.base_addr.lo = U64_LO(bp->eq_mapping);
2877 eq_data.producer = bp->eq_prod;
2878 eq_data.index_id = HC_SP_INDEX_EQ_CONS;
2879 eq_data.sb_id = DEF_SB_ID;
2880 storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp));
2881}
2882
2883
2884static void bnx2x_e1h_disable(struct bnx2x *bp)
2885{
2886 int port = BP_PORT(bp);
2887
619c5cb6 2888 bnx2x_tx_disable(bp);
523224a3
DK		 2889
2890 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
523224a3
DK		 2891}
2892
2893static void bnx2x_e1h_enable(struct bnx2x *bp)
2894{
2895 int port = BP_PORT(bp);
2896
2897 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
2898
2899 /* Tx queue should be only reenabled */
2900 netif_tx_wake_all_queues(bp->dev);
2901
2902 /*
2903 * Should not call netif_carrier_on since it will be called if the link
2904 * is up when checking for link state
2905 */
2906}
2907
0793f83f
DK		 2908/* called due to MCP event (on pmf):
2909 * reread new bandwidth configuration
2910 * configure FW
2911 * notify others function about the change
2912 */
2913static inline void bnx2x_config_mf_bw(struct bnx2x *bp)
2914{
2915 if (bp->link_vars.link_up) {
2916 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX);
2917 bnx2x_link_sync_notify(bp);
2918 }
2919 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2920}
2921
2922static inline void bnx2x_set_mf_bw(struct bnx2x *bp)
2923{
2924 bnx2x_config_mf_bw(bp);
2925 bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
2926}
2927
523224a3
DK		 2928static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event)
2929{
2930 DP(BNX2X_MSG_MCP, "dcc_event 0x%x\n", dcc_event);
2931
2932 if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
2933
2934 /*
2935 * This is the only place besides the function initialization
2936 * where the bp->flags can change so it is done without any
2937 * locks
2938 */
f2e0899f 2939 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
523224a3
DK		 2940 DP(NETIF_MSG_IFDOWN, "mf_cfg function disabled\n");
2941 bp->flags |= MF_FUNC_DIS;
2942
2943 bnx2x_e1h_disable(bp);
2944 } else {
2945 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n");
2946 bp->flags &= ~MF_FUNC_DIS;
2947
2948 bnx2x_e1h_enable(bp);
2949 }
2950 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
2951 }
2952 if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
0793f83f 2953 bnx2x_config_mf_bw(bp);
523224a3
DK		 2954 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
2955 }
2956
2957 /* Report results to MCP */
2958 if (dcc_event)
2959 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_FAILURE, 0);
2960 else
2961 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_OK, 0);
2962}
2963
2964/* must be called under the spq lock */
2965static inline struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp)
2966{
2967 struct eth_spe *next_spe = bp->spq_prod_bd;
2968
2969 if (bp->spq_prod_bd == bp->spq_last_bd) {
2970 bp->spq_prod_bd = bp->spq;
2971 bp->spq_prod_idx = 0;
2972 DP(NETIF_MSG_TIMER, "end of spq\n");
2973 } else {
2974 bp->spq_prod_bd++;
2975 bp->spq_prod_idx++;
2976 }
2977 return next_spe;
2978}
2979
2980/* must be called under the spq lock */
28912902
MC		 2981static inline void bnx2x_sp_prod_update(struct bnx2x *bp)
2982{
2983 int func = BP_FUNC(bp);
2984
2985 /* Make sure that BD data is updated before writing the producer */
2986 wmb();
2987
523224a3 2988 REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
f85582f8 2989 bp->spq_prod_idx);
28912902
MC		 2990 mmiowb();
2991}
2992
619c5cb6
VZ		 2993/**
2994 * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
2995 *
2996 * @cmd: command to check
2997 * @cmd_type: command type
2998 */
2999static inline bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
3000{
3001 if ((cmd_type == NONE_CONNECTION_TYPE) ||
6383c0b3 3002 (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
619c5cb6
VZ		 3003 (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
3004 (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
3005 (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
3006 (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
3007 (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE))
3008 return true;
3009 else
3010 return false;
3011
3012}
3013
3014
3015/**
3016 * bnx2x_sp_post - place a single command on an SP ring
3017 *
3018 * @bp: driver handle
3019 * @command: command to place (e.g. SETUP, FILTER_RULES, etc.)
3020 * @cid: SW CID the command is related to
3021 * @data_hi: command private data address (high 32 bits)
3022 * @data_lo: command private data address (low 32 bits)
3023 * @cmd_type: command type (e.g. NONE, ETH)
3024 *
3025 * SP data is handled as if it's always an address pair, thus data fields are
3026 * not swapped to little endian in upper functions. Instead this function swaps
3027 * data as if it's two u32 fields.
3028 */
9f6c9258 3029int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
619c5cb6 3030 u32 data_hi, u32 data_lo, int cmd_type)
a2fbb9ea 3031{
28912902 3032 struct eth_spe *spe;
523224a3 3033 u16 type;
619c5cb6 3034 bool common = bnx2x_is_contextless_ramrod(command, cmd_type);
a2fbb9ea 3035
a2fbb9ea
ET		 3036#ifdef BNX2X_STOP_ON_ERROR
3037 if (unlikely(bp->panic))
3038 return -EIO;
3039#endif
3040
34f80b04 3041 spin_lock_bh(&bp->spq_lock);
a2fbb9ea 3042
6e30dd4e
VZ		 3043 if (common) {
3044 if (!atomic_read(&bp->eq_spq_left)) {
3045 BNX2X_ERR("BUG! EQ ring full!\n");
3046 spin_unlock_bh(&bp->spq_lock);
3047 bnx2x_panic();
3048 return -EBUSY;
3049 }
3050 } else if (!atomic_read(&bp->cq_spq_left)) {
3051 BNX2X_ERR("BUG! SPQ ring full!\n");
3052 spin_unlock_bh(&bp->spq_lock);
3053 bnx2x_panic();
3054 return -EBUSY;
a2fbb9ea 3055 }
f1410647 3056
28912902
MC		 3057 spe = bnx2x_sp_get_next(bp);
3058
a2fbb9ea 3059 /* CID needs port number to be encoded int it */
28912902 3060 spe->hdr.conn_and_cmd_data =
cdaa7cb8
VZ		 3061 cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) |
3062 HW_CID(bp, cid));
523224a3 3063
619c5cb6 3064 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
a2fbb9ea 3065
523224a3
DK		 3066 type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) &
3067 SPE_HDR_FUNCTION_ID);
a2fbb9ea 3068
523224a3
DK		 3069 spe->hdr.type = cpu_to_le16(type);
3070
3071 spe->data.update_data_addr.hi = cpu_to_le32(data_hi);
3072 spe->data.update_data_addr.lo = cpu_to_le32(data_lo);
3073
3074 /* stats ramrod has it's own slot on the spq */
6e30dd4e 3075 if (command != RAMROD_CMD_ID_COMMON_STAT_QUERY) {
619c5cb6
VZ		 3076 /*
3077 * It's ok if the actual decrement is issued towards the memory
523224a3
DK		 3078 * somewhere between the spin_lock and spin_unlock. Thus no
3079 * more explict memory barrier is needed.
3080 */
6e30dd4e
VZ		 3081 if (common)
3082 atomic_dec(&bp->eq_spq_left);
3083 else
3084 atomic_dec(&bp->cq_spq_left);
3085 }
3086
a2fbb9ea 3087
cdaa7cb8 3088 DP(BNX2X_MSG_SP/*NETIF_MSG_TIMER*/,
523224a3 3089 "SPQE[%x] (%x:%x) command %d hw_cid %x data (%x:%x) "
6e30dd4e 3090 "type(0x%x) left (ETH, COMMON) (%x,%x)\n",
cdaa7cb8
VZ		 3091 bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping),
3092 (u32)(U64_LO(bp->spq_mapping) +
3093 (void *)bp->spq_prod_bd - (void *)bp->spq), command,
6e30dd4e
VZ		 3094 HW_CID(bp, cid), data_hi, data_lo, type,
3095 atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left));
cdaa7cb8 3096
28912902 3097 bnx2x_sp_prod_update(bp);
34f80b04 3098 spin_unlock_bh(&bp->spq_lock);
a2fbb9ea
ET		 3099 return 0;
3100}
3101
3102/* acquire split MCP access lock register */
4a37fb66 3103static int bnx2x_acquire_alr(struct bnx2x *bp)
a2fbb9ea 3104{
72fd0718 3105 u32 j, val;
34f80b04 3106 int rc = 0;
a2fbb9ea
ET		 3107
3108 might_sleep();
72fd0718 3109 for (j = 0; j < 1000; j++) {
a2fbb9ea
ET		 3110 val = (1UL << 31);
3111 REG_WR(bp, GRCBASE_MCP + 0x9c, val);
3112 val = REG_RD(bp, GRCBASE_MCP + 0x9c);
3113 if (val & (1L << 31))
3114 break;
3115
3116 msleep(5);
3117 }
a2fbb9ea 3118 if (!(val & (1L << 31))) {
19680c48 3119 BNX2X_ERR("Cannot acquire MCP access lock register\n");
a2fbb9ea
ET		 3120 rc = -EBUSY;
3121 }
3122
3123 return rc;
3124}
3125
4a37fb66
YG		 3126/* release split MCP access lock register */
3127static void bnx2x_release_alr(struct bnx2x *bp)
a2fbb9ea 3128{
72fd0718 3129 REG_WR(bp, GRCBASE_MCP + 0x9c, 0);
a2fbb9ea
ET		 3130}
3131
523224a3
DK		 3132#define BNX2X_DEF_SB_ATT_IDX 0x0001
3133#define BNX2X_DEF_SB_IDX 0x0002
3134
a2fbb9ea
ET		 3135static inline u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
3136{
523224a3 3137 struct host_sp_status_block *def_sb = bp->def_status_blk;
a2fbb9ea
ET		 3138 u16 rc = 0;
3139
3140 barrier(); /* status block is written to by the chip */
a2fbb9ea
ET		 3141 if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
3142 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
523224a3 3143 rc |= BNX2X_DEF_SB_ATT_IDX;
a2fbb9ea 3144 }
523224a3
DK		 3145
3146 if (bp->def_idx != def_sb->sp_sb.running_index) {
3147 bp->def_idx = def_sb->sp_sb.running_index;
3148 rc |= BNX2X_DEF_SB_IDX;
a2fbb9ea 3149 }
523224a3
DK		 3150
3151 /* Do not reorder: indecies reading should complete before handling */
3152 barrier();
a2fbb9ea
ET		 3153 return rc;
3154}
3155
3156/*
3157 * slow path service functions
3158 */
3159
3160static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
3161{
34f80b04 3162 int port = BP_PORT(bp);
a2fbb9ea
ET		 3163 u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
3164 MISC_REG_AEU_MASK_ATTN_FUNC_0;
877e9aa4
ET		 3165 u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
3166 NIG_REG_MASK_INTERRUPT_PORT0;
3fcaf2e5 3167 u32 aeu_mask;
87942b46 3168 u32 nig_mask = 0;
f2e0899f 3169 u32 reg_addr;
a2fbb9ea 3170
a2fbb9ea
ET		 3171 if (bp->attn_state & asserted)
3172 BNX2X_ERR("IGU ERROR\n");
3173
3fcaf2e5
EG		 3174 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3175 aeu_mask = REG_RD(bp, aeu_addr);
3176
a2fbb9ea 3177 DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n",
3fcaf2e5 3178 aeu_mask, asserted);
72fd0718 3179 aeu_mask &= ~(asserted & 0x3ff);
3fcaf2e5 3180 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
a2fbb9ea 3181
3fcaf2e5
EG		 3182 REG_WR(bp, aeu_addr, aeu_mask);
3183 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
a2fbb9ea 3184
3fcaf2e5 3185 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
a2fbb9ea 3186 bp->attn_state |= asserted;
3fcaf2e5 3187 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
a2fbb9ea
ET		 3188
3189 if (asserted & ATTN_HARD_WIRED_MASK) {
3190 if (asserted & ATTN_NIG_FOR_FUNC) {
a2fbb9ea 3191
a5e9a7cf
EG		 3192 bnx2x_acquire_phy_lock(bp);
3193
877e9aa4 3194 /* save nig interrupt mask */
87942b46 3195 nig_mask = REG_RD(bp, nig_int_mask_addr);
a2fbb9ea 3196
361c391e
YR		 3197 /* If nig_mask is not set, no need to call the update
3198 * function.
3199 */
3200 if (nig_mask) {
3201 REG_WR(bp, nig_int_mask_addr, 0);
3202
3203 bnx2x_link_attn(bp);
3204 }
a2fbb9ea
ET		 3205
3206 /* handle unicore attn? */
3207 }
3208 if (asserted & ATTN_SW_TIMER_4_FUNC)
3209 DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
3210
3211 if (asserted & GPIO_2_FUNC)
3212 DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
3213
3214 if (asserted & GPIO_3_FUNC)
3215 DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
3216
3217 if (asserted & GPIO_4_FUNC)
3218 DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
3219
3220 if (port == 0) {
3221 if (asserted & ATTN_GENERAL_ATTN_1) {
3222 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
3223 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
3224 }
3225 if (asserted & ATTN_GENERAL_ATTN_2) {
3226 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
3227 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
3228 }
3229 if (asserted & ATTN_GENERAL_ATTN_3) {
3230 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
3231 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
3232 }
3233 } else {
3234 if (asserted & ATTN_GENERAL_ATTN_4) {
3235 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
3236 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
3237 }
3238 if (asserted & ATTN_GENERAL_ATTN_5) {
3239 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
3240 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
3241 }
3242 if (asserted & ATTN_GENERAL_ATTN_6) {
3243 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
3244 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
3245 }
3246 }
3247
3248 } /* if hardwired */
3249
f2e0899f
DK		 3250 if (bp->common.int_block == INT_BLOCK_HC)
3251 reg_addr = (HC_REG_COMMAND_REG + port*32 +
3252 COMMAND_REG_ATTN_BITS_SET);
3253 else
3254 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
3255
3256 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted,
3257 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
3258 REG_WR(bp, reg_addr, asserted);
a2fbb9ea
ET		 3259
3260 /* now set back the mask */
a5e9a7cf 3261 if (asserted & ATTN_NIG_FOR_FUNC) {
87942b46 3262 REG_WR(bp, nig_int_mask_addr, nig_mask);
a5e9a7cf
EG		 3263 bnx2x_release_phy_lock(bp);
3264 }
a2fbb9ea
ET		 3265}
3266
fd4ef40d
EG		 3267static inline void bnx2x_fan_failure(struct bnx2x *bp)
3268{
3269 int port = BP_PORT(bp);
b7737c9b 3270 u32 ext_phy_config;
fd4ef40d 3271 /* mark the failure */
b7737c9b
YR		 3272 ext_phy_config =
3273 SHMEM_RD(bp,
3274 dev_info.port_hw_config[port].external_phy_config);
3275
3276 ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
3277 ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
fd4ef40d 3278 SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
b7737c9b 3279 ext_phy_config);
fd4ef40d
EG		 3280
3281 /* log the failure */
cdaa7cb8
VZ		 3282 netdev_err(bp->dev, "Fan Failure on Network Controller has caused"
3283 " the driver to shutdown the card to prevent permanent"
3284 " damage. Please contact OEM Support for assistance\n");
fd4ef40d 3285}
ab6ad5a4 3286
877e9aa4 3287static inline void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
a2fbb9ea 3288{
34f80b04 3289 int port = BP_PORT(bp);
877e9aa4 3290 int reg_offset;
d90d96ba 3291 u32 val;
877e9aa4 3292
34f80b04
EG		 3293 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
3294 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
877e9aa4 3295
34f80b04 3296 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
877e9aa4
ET		 3297
3298 val = REG_RD(bp, reg_offset);
3299 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
3300 REG_WR(bp, reg_offset, val);
3301
3302 BNX2X_ERR("SPIO5 hw attention\n");
3303
fd4ef40d 3304 /* Fan failure attention */
d90d96ba 3305 bnx2x_hw_reset_phy(&bp->link_params);
fd4ef40d 3306 bnx2x_fan_failure(bp);
877e9aa4 3307 }
34f80b04 3308
3deb8167 3309 if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) {
589abe3a
EG		 3310 bnx2x_acquire_phy_lock(bp);
3311 bnx2x_handle_module_detect_int(&bp->link_params);
3312 bnx2x_release_phy_lock(bp);
3313 }
3314
34f80b04
EG		 3315 if (attn & HW_INTERRUT_ASSERT_SET_0) {
3316
3317 val = REG_RD(bp, reg_offset);
3318 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
3319 REG_WR(bp, reg_offset, val);
3320
3321 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
0fc5d009 3322 (u32)(attn & HW_INTERRUT_ASSERT_SET_0));
34f80b04
EG		 3323 bnx2x_panic();
3324 }
877e9aa4
ET		 3325}
3326
3327static inline void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
3328{
3329 u32 val;
3330
0626b899 3331 if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
877e9aa4
ET		 3332
3333 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
3334 BNX2X_ERR("DB hw attention 0x%x\n", val);
3335 /* DORQ discard attention */
3336 if (val & 0x2)
3337 BNX2X_ERR("FATAL error from DORQ\n");
3338 }
34f80b04
EG		 3339
3340 if (attn & HW_INTERRUT_ASSERT_SET_1) {
3341
3342 int port = BP_PORT(bp);
3343 int reg_offset;
3344
3345 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
3346 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
3347
3348 val = REG_RD(bp, reg_offset);
3349 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
3350 REG_WR(bp, reg_offset, val);
3351
3352 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
0fc5d009 3353 (u32)(attn & HW_INTERRUT_ASSERT_SET_1));
34f80b04
EG		 3354 bnx2x_panic();
3355 }
877e9aa4
ET		 3356}
3357
3358static inline void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
3359{
3360 u32 val;
3361
3362 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
3363
3364 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
3365 BNX2X_ERR("CFC hw attention 0x%x\n", val);
3366 /* CFC error attention */
3367 if (val & 0x2)
3368 BNX2X_ERR("FATAL error from CFC\n");
3369 }
3370
3371 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
877e9aa4 3372 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
619c5cb6 3373 BNX2X_ERR("PXP hw attention-0 0x%x\n", val);
877e9aa4
ET		 3374 /* RQ_USDMDP_FIFO_OVERFLOW */
3375 if (val & 0x18000)
3376 BNX2X_ERR("FATAL error from PXP\n");
619c5cb6
VZ		 3377
3378 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 3379 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1);
3380 BNX2X_ERR("PXP hw attention-1 0x%x\n", val);
3381 }
877e9aa4 3382 }
34f80b04
EG		 3383
3384 if (attn & HW_INTERRUT_ASSERT_SET_2) {
3385
3386 int port = BP_PORT(bp);
3387 int reg_offset;
3388
3389 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
3390 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
3391
3392 val = REG_RD(bp, reg_offset);
3393 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
3394 REG_WR(bp, reg_offset, val);
3395
3396 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
0fc5d009 3397 (u32)(attn & HW_INTERRUT_ASSERT_SET_2));
34f80b04
EG		 3398 bnx2x_panic();
3399 }
877e9aa4
ET		 3400}
3401
3402static inline void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
3403{
34f80b04
EG		 3404 u32 val;
3405
877e9aa4
ET		 3406 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
3407
34f80b04
EG		 3408 if (attn & BNX2X_PMF_LINK_ASSERT) {
3409 int func = BP_FUNC(bp);
3410
3411 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
f2e0899f
DK		 3412 bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp,
3413 func_mf_config[BP_ABS_FUNC(bp)].config);
3414 val = SHMEM_RD(bp,
3415 func_mb[BP_FW_MB_IDX(bp)].drv_status);
2691d51d
EG		 3416 if (val & DRV_STATUS_DCC_EVENT_MASK)
3417 bnx2x_dcc_event(bp,
3418 (val & DRV_STATUS_DCC_EVENT_MASK));
0793f83f
DK		 3419
3420 if (val & DRV_STATUS_SET_MF_BW)
3421 bnx2x_set_mf_bw(bp);
3422
2691d51d 3423 if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
34f80b04
EG		 3424 bnx2x_pmf_update(bp);
3425
e4901dde 3426 if (bp->port.pmf &&
785b9b1a
SR		 3427 (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) &&
3428 bp->dcbx_enabled > 0)
e4901dde
VZ		 3429 /* start dcbx state machine */
3430 bnx2x_dcbx_set_params(bp,
3431 BNX2X_DCBX_STATE_NEG_RECEIVED);
3deb8167
YR		 3432 if (bp->link_vars.periodic_flags &
3433 PERIODIC_FLAGS_LINK_EVENT) {
3434 /* sync with link */
3435 bnx2x_acquire_phy_lock(bp);
3436 bp->link_vars.periodic_flags &=
3437 ~PERIODIC_FLAGS_LINK_EVENT;
3438 bnx2x_release_phy_lock(bp);
3439 if (IS_MF(bp))
3440 bnx2x_link_sync_notify(bp);
3441 bnx2x_link_report(bp);
3442 }
3443 /* Always call it here: bnx2x_link_report() will
3444 * prevent the link indication duplication.
3445 */
3446 bnx2x__link_status_update(bp);
34f80b04 3447 } else if (attn & BNX2X_MC_ASSERT_BITS) {
877e9aa4
ET		 3448
3449 BNX2X_ERR("MC assert!\n");
3450 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
3451 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
3452 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
3453 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
3454 bnx2x_panic();
3455
3456 } else if (attn & BNX2X_MCP_ASSERT) {
3457
3458 BNX2X_ERR("MCP assert!\n");
3459 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
34f80b04 3460 bnx2x_fw_dump(bp);
877e9aa4
ET		 3461
3462 } else
3463 BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
3464 }
3465
3466 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
34f80b04
EG		 3467 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
3468 if (attn & BNX2X_GRC_TIMEOUT) {
f2e0899f
DK		 3469 val = CHIP_IS_E1(bp) ? 0 :
3470 REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN);
34f80b04
EG		 3471 BNX2X_ERR("GRC time-out 0x%08x\n", val);
3472 }
3473 if (attn & BNX2X_GRC_RSV) {
f2e0899f
DK		 3474 val = CHIP_IS_E1(bp) ? 0 :
3475 REG_RD(bp, MISC_REG_GRC_RSV_ATTN);
34f80b04
EG		 3476 BNX2X_ERR("GRC reserved 0x%08x\n", val);
3477 }
877e9aa4 3478 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
877e9aa4
ET		 3479 }
3480}
3481
c9ee9206
VZ		 3482/*
3483 * Bits map:
3484 * 0-7 - Engine0 load counter.
3485 * 8-15 - Engine1 load counter.
3486 * 16 - Engine0 RESET_IN_PROGRESS bit.
3487 * 17 - Engine1 RESET_IN_PROGRESS bit.
3488 * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active function
3489 * on the engine
3490 * 19 - Engine1 ONE_IS_LOADED.
3491 * 20 - Chip reset flow bit. When set none-leader must wait for both engines
3492 * leader to complete (check for both RESET_IN_PROGRESS bits and not for
3493 * just the one belonging to its engine).
3494 *
3495 */
3496#define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1
3497
3498#define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff
3499#define BNX2X_PATH0_LOAD_CNT_SHIFT 0
3500#define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00
3501#define BNX2X_PATH1_LOAD_CNT_SHIFT 8
3502#define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000
3503#define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000
3504#define BNX2X_GLOBAL_RESET_BIT 0x00040000
3505
3506/*
3507 * Set the GLOBAL_RESET bit.
3508 *
3509 * Should be run under rtnl lock
3510 */
3511void bnx2x_set_reset_global(struct bnx2x *bp)
3512{
3513 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3514
3515 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
3516 barrier();
3517 mmiowb();
3518}
3519
3520/*
3521 * Clear the GLOBAL_RESET bit.
3522 *
3523 * Should be run under rtnl lock
3524 */
3525static inline void bnx2x_clear_reset_global(struct bnx2x *bp)
3526{
3527 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3528
3529 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
3530 barrier();
3531 mmiowb();
3532}
f85582f8 3533
72fd0718 3534/*
c9ee9206
VZ		 3535 * Checks the GLOBAL_RESET bit.
3536 *
72fd0718
VZ		 3537 * should be run under rtnl lock
3538 */
c9ee9206
VZ		 3539static inline bool bnx2x_reset_is_global(struct bnx2x *bp)
3540{
3541 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3542
3543 DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val);
3544 return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false;
3545}
3546
3547/*
3548 * Clear RESET_IN_PROGRESS bit for the current engine.
3549 *
3550 * Should be run under rtnl lock
3551 */
72fd0718
VZ		 3552static inline void bnx2x_set_reset_done(struct bnx2x *bp)
3553{
c9ee9206
VZ		 3554 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3555 u32 bit = BP_PATH(bp) ?
3556 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
3557
3558 /* Clear the bit */
3559 val &= ~bit;
3560 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
72fd0718
VZ		 3561 barrier();
3562 mmiowb();
3563}
3564
3565/*
c9ee9206
VZ		 3566 * Set RESET_IN_PROGRESS for the current engine.
3567 *
72fd0718
VZ		 3568 * should be run under rtnl lock
3569 */
c9ee9206 3570void bnx2x_set_reset_in_progress(struct bnx2x *bp)
72fd0718 3571{
c9ee9206
VZ		 3572 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3573 u32 bit = BP_PATH(bp) ?
3574 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
3575
3576 /* Set the bit */
3577 val |= bit;
3578 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
72fd0718
VZ		 3579 barrier();
3580 mmiowb();
3581}
3582
3583/*
c9ee9206 3584 * Checks the RESET_IN_PROGRESS bit for the given engine.
72fd0718
VZ		 3585 * should be run under rtnl lock
3586 */
c9ee9206 3587bool bnx2x_reset_is_done(struct bnx2x *bp, int engine)
72fd0718 3588{
c9ee9206
VZ		 3589 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3590 u32 bit = engine ?
3591 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
3592
3593 /* return false if bit is set */
3594 return (val & bit) ? false : true;
72fd0718
VZ		 3595}
3596
3597/*
c9ee9206
VZ		 3598 * Increment the load counter for the current engine.
3599 *
72fd0718
VZ		 3600 * should be run under rtnl lock
3601 */
c9ee9206 3602void bnx2x_inc_load_cnt(struct bnx2x *bp)
72fd0718 3603{
c9ee9206
VZ		 3604 u32 val1, val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3605 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
3606 BNX2X_PATH0_LOAD_CNT_MASK;
3607 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
3608 BNX2X_PATH0_LOAD_CNT_SHIFT;
72fd0718
VZ		 3609
3610 DP(NETIF_MSG_HW, "Old GEN_REG_VAL=0x%08x\n", val);
3611
c9ee9206
VZ		 3612 /* get the current counter value */
3613 val1 = (val & mask) >> shift;
3614
3615 /* increment... */
3616 val1++;
3617
3618 /* clear the old value */
3619 val &= ~mask;
3620
3621 /* set the new one */
3622 val |= ((val1 << shift) & mask);
3623
3624 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
72fd0718
VZ		 3625 barrier();
3626 mmiowb();
3627}
3628
c9ee9206
VZ		 3629/**
3630 * bnx2x_dec_load_cnt - decrement the load counter
3631 *
3632 * @bp: driver handle
3633 *
3634 * Should be run under rtnl lock.
3635 * Decrements the load counter for the current engine. Returns
3636 * the new counter value.
72fd0718 3637 */
9f6c9258 3638u32 bnx2x_dec_load_cnt(struct bnx2x *bp)
72fd0718 3639{
c9ee9206
VZ		 3640 u32 val1, val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3641 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
3642 BNX2X_PATH0_LOAD_CNT_MASK;
3643 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
3644 BNX2X_PATH0_LOAD_CNT_SHIFT;
72fd0718
VZ		 3645
3646 DP(NETIF_MSG_HW, "Old GEN_REG_VAL=0x%08x\n", val);
3647
c9ee9206
VZ		 3648 /* get the current counter value */
3649 val1 = (val & mask) >> shift;
3650
3651 /* decrement... */
3652 val1--;
3653
3654 /* clear the old value */
3655 val &= ~mask;
3656
3657 /* set the new one */
3658 val |= ((val1 << shift) & mask);
3659
3660 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
72fd0718
VZ		 3661 barrier();
3662 mmiowb();
3663
3664 return val1;
3665}
3666
3667/*
c9ee9206
VZ		 3668 * Read the load counter for the current engine.
3669 *
72fd0718
VZ		 3670 * should be run under rtnl lock
3671 */
c9ee9206 3672static inline u32 bnx2x_get_load_cnt(struct bnx2x *bp, int engine)
72fd0718 3673{
c9ee9206
VZ		 3674 u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK :
3675 BNX2X_PATH0_LOAD_CNT_MASK);
3676 u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
3677 BNX2X_PATH0_LOAD_CNT_SHIFT);
3678 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3679
3680 DP(NETIF_MSG_HW, "GLOB_REG=0x%08x\n", val);
3681
3682 val = (val & mask) >> shift;
3683
3684 DP(NETIF_MSG_HW, "load_cnt for engine %d = %d\n", engine, val);
3685
3686 return val;
72fd0718
VZ		 3687}
3688
c9ee9206
VZ		 3689/*
3690 * Reset the load counter for the current engine.
3691 *
3692 * should be run under rtnl lock
3693 */
72fd0718
VZ		 3694static inline void bnx2x_clear_load_cnt(struct bnx2x *bp)
3695{
c9ee9206
VZ		 3696 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3697 u32 mask = (BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
3698 BNX2X_PATH0_LOAD_CNT_MASK);
3699
3700 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~mask));
72fd0718
VZ		 3701}
3702
3703static inline void _print_next_block(int idx, const char *blk)
3704{
3705 if (idx)
3706 pr_cont(", ");
3707 pr_cont("%s", blk);
3708}
3709
c9ee9206
VZ		 3710static inline int bnx2x_check_blocks_with_parity0(u32 sig, int par_num,
3711 bool print)
72fd0718
VZ		 3712{
3713 int i = 0;
3714 u32 cur_bit = 0;
3715 for (i = 0; sig; i++) {
3716 cur_bit = ((u32)0x1 << i);
3717 if (sig & cur_bit) {
3718 switch (cur_bit) {
3719 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
c9ee9206
VZ		 3720 if (print)
3721 _print_next_block(par_num++, "BRB");
72fd0718
VZ		 3722 break;
3723 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
c9ee9206
VZ		 3724 if (print)
3725 _print_next_block(par_num++, "PARSER");
72fd0718
VZ		 3726 break;
3727 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
c9ee9206
VZ		 3728 if (print)
3729 _print_next_block(par_num++, "TSDM");
72fd0718
VZ		 3730 break;
3731 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
c9ee9206
VZ		 3732 if (print)
3733 _print_next_block(par_num++,
3734 "SEARCHER");
3735 break;
3736 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
3737 if (print)
3738 _print_next_block(par_num++, "TCM");
72fd0718
VZ		 3739 break;
3740 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
c9ee9206
VZ		 3741 if (print)
3742 _print_next_block(par_num++, "TSEMI");
3743 break;
3744 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
3745 if (print)
3746 _print_next_block(par_num++, "XPB");
72fd0718
VZ		 3747 break;
3748 }
3749
3750 /* Clear the bit */
3751 sig &= ~cur_bit;
3752 }
3753 }
3754
3755 return par_num;
3756}
3757
c9ee9206
VZ		 3758static inline int bnx2x_check_blocks_with_parity1(u32 sig, int par_num,
3759 bool *global, bool print)
72fd0718
VZ		 3760{
3761 int i = 0;
3762 u32 cur_bit = 0;
3763 for (i = 0; sig; i++) {
3764 cur_bit = ((u32)0x1 << i);
3765 if (sig & cur_bit) {
3766 switch (cur_bit) {
c9ee9206
VZ		 3767 case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
3768 if (print)
3769 _print_next_block(par_num++, "PBF");
72fd0718
VZ		 3770 break;
3771 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
c9ee9206
VZ		 3772 if (print)
3773 _print_next_block(par_num++, "QM");
3774 break;
3775 case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
3776 if (print)
3777 _print_next_block(par_num++, "TM");
72fd0718
VZ		 3778 break;
3779 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
c9ee9206
VZ		 3780 if (print)
3781 _print_next_block(par_num++, "XSDM");
3782 break;
3783 case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
3784 if (print)
3785 _print_next_block(par_num++, "XCM");
72fd0718
VZ		 3786 break;
3787 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
c9ee9206
VZ		 3788 if (print)
3789 _print_next_block(par_num++, "XSEMI");
72fd0718
VZ		 3790 break;
3791 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
c9ee9206
VZ		 3792 if (print)
3793 _print_next_block(par_num++,
3794 "DOORBELLQ");
3795 break;
3796 case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
3797 if (print)
3798 _print_next_block(par_num++, "NIG");
72fd0718
VZ		 3799 break;
3800 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
c9ee9206
VZ		 3801 if (print)
3802 _print_next_block(par_num++,
3803 "VAUX PCI CORE");
3804 *global = true;
72fd0718
VZ		 3805 break;
3806 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
c9ee9206
VZ		 3807 if (print)
3808 _print_next_block(par_num++, "DEBUG");
72fd0718
VZ		 3809 break;
3810 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
c9ee9206
VZ		 3811 if (print)
3812 _print_next_block(par_num++, "USDM");
72fd0718
VZ		 3813 break;
3814 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
c9ee9206
VZ		 3815 if (print)
3816 _print_next_block(par_num++, "USEMI");
72fd0718
VZ		 3817 break;
3818 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
c9ee9206
VZ		 3819 if (print)
3820 _print_next_block(par_num++, "UPB");
72fd0718
VZ		 3821 break;
3822 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
c9ee9206
VZ		 3823 if (print)
3824 _print_next_block(par_num++, "CSDM");
72fd0718
VZ		 3825 break;
3826 }
3827
3828 /* Clear the bit */
3829 sig &= ~cur_bit;
3830 }
3831 }
3832
3833 return par_num;
3834}
3835
c9ee9206
VZ		 3836static inline int bnx2x_check_blocks_with_parity2(u32 sig, int par_num,
3837 bool print)
72fd0718
VZ		 3838{
3839 int i = 0;
3840 u32 cur_bit = 0;
3841 for (i = 0; sig; i++) {
3842 cur_bit = ((u32)0x1 << i);
3843 if (sig & cur_bit) {
3844 switch (cur_bit) {
3845 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
c9ee9206
VZ		 3846 if (print)
3847 _print_next_block(par_num++, "CSEMI");
72fd0718
VZ		 3848 break;
3849 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
c9ee9206
VZ		 3850 if (print)
3851 _print_next_block(par_num++, "PXP");
72fd0718
VZ		 3852 break;
3853 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
c9ee9206
VZ		 3854 if (print)
3855 _print_next_block(par_num++,
72fd0718
VZ		 3856 "PXPPCICLOCKCLIENT");
3857 break;
3858 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
c9ee9206
VZ		 3859 if (print)
3860 _print_next_block(par_num++, "CFC");
72fd0718
VZ		 3861 break;
3862 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
c9ee9206
VZ		 3863 if (print)
3864 _print_next_block(par_num++, "CDU");
3865 break;
3866 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
3867 if (print)
3868 _print_next_block(par_num++, "DMAE");
72fd0718
VZ		 3869 break;
3870 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
c9ee9206
VZ		 3871 if (print)
3872 _print_next_block(par_num++, "IGU");
72fd0718
VZ		 3873 break;
3874 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
c9ee9206
VZ		 3875 if (print)
3876 _print_next_block(par_num++, "MISC");
72fd0718
VZ		 3877 break;
3878 }
3879
3880 /* Clear the bit */
3881 sig &= ~cur_bit;
3882 }
3883 }
3884
3885 return par_num;
3886}
3887
c9ee9206
VZ		 3888static inline int bnx2x_check_blocks_with_parity3(u32 sig, int par_num,
3889 bool *global, bool print)
72fd0718
VZ		 3890{
3891 int i = 0;
3892 u32 cur_bit = 0;
3893 for (i = 0; sig; i++) {
3894 cur_bit = ((u32)0x1 << i);
3895 if (sig & cur_bit) {
3896 switch (cur_bit) {
3897 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
c9ee9206
VZ		 3898 if (print)
3899 _print_next_block(par_num++, "MCP ROM");
3900 *global = true;
72fd0718
VZ		 3901 break;
3902 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
c9ee9206
VZ		 3903 if (print)
3904 _print_next_block(par_num++,
3905 "MCP UMP RX");
3906 *global = true;
72fd0718
VZ		 3907 break;
3908 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
c9ee9206
VZ		 3909 if (print)
3910 _print_next_block(par_num++,
3911 "MCP UMP TX");
3912 *global = true;
72fd0718
VZ		 3913 break;
3914 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
c9ee9206
VZ		 3915 if (print)
3916 _print_next_block(par_num++,
3917 "MCP SCPAD");
3918 *global = true;
72fd0718
VZ		 3919 break;
3920 }
3921
3922 /* Clear the bit */
3923 sig &= ~cur_bit;
3924 }
3925 }
3926
3927 return par_num;
3928}
3929
c9ee9206
VZ		 3930static inline bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
3931 u32 sig0, u32 sig1, u32 sig2, u32 sig3)
72fd0718
VZ		 3932{
3933 if ((sig0 & HW_PRTY_ASSERT_SET_0) || (sig1 & HW_PRTY_ASSERT_SET_1) ||
3934 (sig2 & HW_PRTY_ASSERT_SET_2) || (sig3 & HW_PRTY_ASSERT_SET_3)) {
3935 int par_num = 0;
3936 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention: "
3937 "[0]:0x%08x [1]:0x%08x "
3938 "[2]:0x%08x [3]:0x%08x\n",
3939 sig0 & HW_PRTY_ASSERT_SET_0,
3940 sig1 & HW_PRTY_ASSERT_SET_1,
3941 sig2 & HW_PRTY_ASSERT_SET_2,
3942 sig3 & HW_PRTY_ASSERT_SET_3);
c9ee9206
VZ		 3943 if (print)
3944 netdev_err(bp->dev,
3945 "Parity errors detected in blocks: ");
3946 par_num = bnx2x_check_blocks_with_parity0(
3947 sig0 & HW_PRTY_ASSERT_SET_0, par_num, print);
3948 par_num = bnx2x_check_blocks_with_parity1(
3949 sig1 & HW_PRTY_ASSERT_SET_1, par_num, global, print);
3950 par_num = bnx2x_check_blocks_with_parity2(
3951 sig2 & HW_PRTY_ASSERT_SET_2, par_num, print);
3952 par_num = bnx2x_check_blocks_with_parity3(
3953 sig3 & HW_PRTY_ASSERT_SET_3, par_num, global, print);
3954 if (print)
3955 pr_cont("\n");
72fd0718
VZ		 3956 return true;
3957 } else
3958 return false;
3959}
3960
c9ee9206
VZ		 3961/**
3962 * bnx2x_chk_parity_attn - checks for parity attentions.
3963 *
3964 * @bp: driver handle
3965 * @global: true if there was a global attention
3966 * @print: show parity attention in syslog
3967 */
3968bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print)
877e9aa4 3969{
a2fbb9ea 3970 struct attn_route attn;
72fd0718
VZ		 3971 int port = BP_PORT(bp);
3972
3973 attn.sig[0] = REG_RD(bp,
3974 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
3975 port*4);
3976 attn.sig[1] = REG_RD(bp,
3977 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 +
3978 port*4);
3979 attn.sig[2] = REG_RD(bp,
3980 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 +
3981 port*4);
3982 attn.sig[3] = REG_RD(bp,
3983 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
3984 port*4);
3985
c9ee9206
VZ		 3986 return bnx2x_parity_attn(bp, global, print, attn.sig[0], attn.sig[1],
3987 attn.sig[2], attn.sig[3]);
72fd0718
VZ		 3988}
3989
f2e0899f
DK		 3990
3991static inline void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn)
3992{
3993 u32 val;
3994 if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
3995
3996 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
3997 BNX2X_ERR("PGLUE hw attention 0x%x\n", val);
3998 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
3999 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4000 "ADDRESS_ERROR\n");
4001 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
4002 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4003 "INCORRECT_RCV_BEHAVIOR\n");
4004 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
4005 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4006 "WAS_ERROR_ATTN\n");
4007 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
4008 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4009 "VF_LENGTH_VIOLATION_ATTN\n");
4010 if (val &
4011 PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
4012 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4013 "VF_GRC_SPACE_VIOLATION_ATTN\n");
4014 if (val &
4015 PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
4016 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4017 "VF_MSIX_BAR_VIOLATION_ATTN\n");
4018 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
4019 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4020 "TCPL_ERROR_ATTN\n");
4021 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
4022 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4023 "TCPL_IN_TWO_RCBS_ATTN\n");
4024 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
4025 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4026 "CSSNOOP_FIFO_OVERFLOW\n");
4027 }
4028 if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
4029 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);
4030 BNX2X_ERR("ATC hw attention 0x%x\n", val);
4031 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
4032 BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
4033 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
4034 BNX2X_ERR("ATC_ATC_INT_STS_REG"
4035 "_ATC_TCPL_TO_NOT_PEND\n");
4036 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
4037 BNX2X_ERR("ATC_ATC_INT_STS_REG_"
4038 "ATC_GPA_MULTIPLE_HITS\n");
4039 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
4040 BNX2X_ERR("ATC_ATC_INT_STS_REG_"
4041 "ATC_RCPL_TO_EMPTY_CNT\n");
4042 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
4043 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
4044 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
4045 BNX2X_ERR("ATC_ATC_INT_STS_REG_"
4046 "ATC_IREQ_LESS_THAN_STU\n");
4047 }
4048
4049 if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4050 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
4051 BNX2X_ERR("FATAL parity attention set4 0x%x\n",
4052 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4053 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
4054 }
4055
4056}
4057
72fd0718
VZ		 4058static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
4059{
4060 struct attn_route attn, *group_mask;
34f80b04 4061 int port = BP_PORT(bp);
877e9aa4 4062 int index;
a2fbb9ea
ET		 4063 u32 reg_addr;
4064 u32 val;
3fcaf2e5 4065 u32 aeu_mask;
c9ee9206 4066 bool global = false;
a2fbb9ea
ET		 4067
4068 /* need to take HW lock because MCP or other port might also
4069 try to handle this event */
4a37fb66 4070 bnx2x_acquire_alr(bp);
a2fbb9ea 4071
c9ee9206
VZ		 4072 if (bnx2x_chk_parity_attn(bp, &global, true)) {
4073#ifndef BNX2X_STOP_ON_ERROR
72fd0718 4074 bp->recovery_state = BNX2X_RECOVERY_INIT;
7be08a72 4075 schedule_delayed_work(&bp->sp_rtnl_task, 0);
72fd0718
VZ		 4076 /* Disable HW interrupts */
4077 bnx2x_int_disable(bp);
72fd0718
VZ		 4078 /* In case of parity errors don't handle attentions so that
4079 * other function would "see" parity errors.
4080 */
c9ee9206
VZ		 4081#else
4082 bnx2x_panic();
4083#endif
4084 bnx2x_release_alr(bp);
72fd0718
VZ		 4085 return;
4086 }
4087
a2fbb9ea
ET		 4088 attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
4089 attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
4090 attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
4091 attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
619c5cb6 4092 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 4093 attn.sig[4] =
4094 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
4095 else
4096 attn.sig[4] = 0;
4097
4098 DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n",
4099 attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
a2fbb9ea
ET		 4100
4101 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4102 if (deasserted & (1 << index)) {
72fd0718 4103 group_mask = &bp->attn_group[index];
a2fbb9ea 4104
f2e0899f
DK		 4105 DP(NETIF_MSG_HW, "group[%d]: %08x %08x "
4106 "%08x %08x %08x\n",
4107 index,
4108 group_mask->sig[0], group_mask->sig[1],
4109 group_mask->sig[2], group_mask->sig[3],
4110 group_mask->sig[4]);
a2fbb9ea 4111
f2e0899f
DK		 4112 bnx2x_attn_int_deasserted4(bp,
4113 attn.sig[4] & group_mask->sig[4]);
877e9aa4 4114 bnx2x_attn_int_deasserted3(bp,
72fd0718 4115 attn.sig[3] & group_mask->sig[3]);
877e9aa4 4116 bnx2x_attn_int_deasserted1(bp,
72fd0718 4117 attn.sig[1] & group_mask->sig[1]);
877e9aa4 4118 bnx2x_attn_int_deasserted2(bp,
72fd0718 4119 attn.sig[2] & group_mask->sig[2]);
877e9aa4 4120 bnx2x_attn_int_deasserted0(bp,
72fd0718 4121 attn.sig[0] & group_mask->sig[0]);
a2fbb9ea
ET		 4122 }
4123 }
4124
4a37fb66 4125 bnx2x_release_alr(bp);
a2fbb9ea 4126
f2e0899f
DK		 4127 if (bp->common.int_block == INT_BLOCK_HC)
4128 reg_addr = (HC_REG_COMMAND_REG + port*32 +
4129 COMMAND_REG_ATTN_BITS_CLR);
4130 else
4131 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
a2fbb9ea
ET		 4132
4133 val = ~deasserted;
f2e0899f
DK		 4134 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val,
4135 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
5c862848 4136 REG_WR(bp, reg_addr, val);
a2fbb9ea 4137
a2fbb9ea 4138 if (~bp->attn_state & deasserted)
3fcaf2e5 4139 BNX2X_ERR("IGU ERROR\n");
a2fbb9ea
ET		 4140
4141 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
4142 MISC_REG_AEU_MASK_ATTN_FUNC_0;
4143
3fcaf2e5
EG		 4144 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4145 aeu_mask = REG_RD(bp, reg_addr);
4146
4147 DP(NETIF_MSG_HW, "aeu_mask %x newly deasserted %x\n",
4148 aeu_mask, deasserted);
72fd0718 4149 aeu_mask |= (deasserted & 0x3ff);
3fcaf2e5 4150 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
a2fbb9ea 4151
3fcaf2e5
EG		 4152 REG_WR(bp, reg_addr, aeu_mask);
4153 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
a2fbb9ea
ET		 4154
4155 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
4156 bp->attn_state &= ~deasserted;
4157 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
4158}
4159
4160static void bnx2x_attn_int(struct bnx2x *bp)
4161{
4162 /* read local copy of bits */
68d59484
EG		 4163 u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
4164 attn_bits);
4165 u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
4166 attn_bits_ack);
a2fbb9ea
ET		 4167 u32 attn_state = bp->attn_state;
4168
4169 /* look for changed bits */
4170 u32 asserted = attn_bits & ~attn_ack & ~attn_state;
4171 u32 deasserted = ~attn_bits & attn_ack & attn_state;
4172
4173 DP(NETIF_MSG_HW,
4174 "attn_bits %x attn_ack %x asserted %x deasserted %x\n",
4175 attn_bits, attn_ack, asserted, deasserted);
4176
4177 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
34f80b04 4178 BNX2X_ERR("BAD attention state\n");
a2fbb9ea
ET		 4179
4180 /* handle bits that were raised */
4181 if (asserted)
4182 bnx2x_attn_int_asserted(bp, asserted);
4183
4184 if (deasserted)
4185 bnx2x_attn_int_deasserted(bp, deasserted);
4186}
4187
619c5cb6
VZ		 4188void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
4189 u16 index, u8 op, u8 update)
4190{
4191 u32 igu_addr = BAR_IGU_INTMEM + (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8;
4192
4193 bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update,
4194 igu_addr);
4195}
4196
523224a3
DK		 4197static inline void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod)
4198{
4199 /* No memory barriers */
4200 storm_memset_eq_prod(bp, prod, BP_FUNC(bp));
4201 mmiowb(); /* keep prod updates ordered */
4202}
4203
4204#ifdef BCM_CNIC
4205static int bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid,
4206 union event_ring_elem *elem)
4207{
619c5cb6
VZ		 4208 u8 err = elem->message.error;
4209
523224a3 4210 if (!bp->cnic_eth_dev.starting_cid ||
c3a8ce61
VZ		 4211 (cid < bp->cnic_eth_dev.starting_cid &&
4212 cid != bp->cnic_eth_dev.iscsi_l2_cid))
523224a3
DK		 4213 return 1;
4214
4215 DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid);
4216
619c5cb6
VZ		 4217 if (unlikely(err)) {
4218
523224a3
DK		 4219 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
4220 cid);
4221 bnx2x_panic_dump(bp);
4222 }
619c5cb6 4223 bnx2x_cnic_cfc_comp(bp, cid, err);
523224a3
DK		 4224 return 0;
4225}
4226#endif
4227
619c5cb6
VZ		 4228static inline void bnx2x_handle_mcast_eqe(struct bnx2x *bp)
4229{
4230 struct bnx2x_mcast_ramrod_params rparam;
4231 int rc;
4232
4233 memset(&rparam, 0, sizeof(rparam));
4234
4235 rparam.mcast_obj = &bp->mcast_obj;
4236
4237 netif_addr_lock_bh(bp->dev);
4238
4239 /* Clear pending state for the last command */
4240 bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw);
4241
4242 /* If there are pending mcast commands - send them */
4243 if (bp->mcast_obj.check_pending(&bp->mcast_obj)) {
4244 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
4245 if (rc < 0)
4246 BNX2X_ERR("Failed to send pending mcast commands: %d\n",
4247 rc);
4248 }
4249
4250 netif_addr_unlock_bh(bp->dev);
4251}
4252
4253static inline void bnx2x_handle_classification_eqe(struct bnx2x *bp,
4254 union event_ring_elem *elem)
4255{
4256 unsigned long ramrod_flags = 0;
4257 int rc = 0;
4258 u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4259 struct bnx2x_vlan_mac_obj *vlan_mac_obj;
4260
4261 /* Always push next commands out, don't wait here */
4262 __set_bit(RAMROD_CONT, &ramrod_flags);
4263
4264 switch (elem->message.data.eth_event.echo >> BNX2X_SWCID_SHIFT) {
4265 case BNX2X_FILTER_MAC_PENDING:
4266#ifdef BCM_CNIC
4267 if (cid == BNX2X_ISCSI_ETH_CID)
4268 vlan_mac_obj = &bp->iscsi_l2_mac_obj;
4269 else
4270#endif
4271 vlan_mac_obj = &bp->fp[cid].mac_obj;
4272
4273 break;
4274 vlan_mac_obj = &bp->fp[cid].mac_obj;
4275
4276 case BNX2X_FILTER_MCAST_PENDING:
4277 /* This is only relevant for 57710 where multicast MACs are
4278 * configured as unicast MACs using the same ramrod.
4279 */
4280 bnx2x_handle_mcast_eqe(bp);
4281 return;
4282 default:
4283 BNX2X_ERR("Unsupported classification command: %d\n",
4284 elem->message.data.eth_event.echo);
4285 return;
4286 }
4287
4288 rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags);
4289
4290 if (rc < 0)
4291 BNX2X_ERR("Failed to schedule new commands: %d\n", rc);
4292 else if (rc > 0)
4293 DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n");
4294
4295}
4296
4297#ifdef BCM_CNIC
4298static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start);
4299#endif
4300
4301static inline void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp)
4302{
4303 netif_addr_lock_bh(bp->dev);
4304
4305 clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
4306
4307 /* Send rx_mode command again if was requested */
4308 if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state))
4309 bnx2x_set_storm_rx_mode(bp);
4310#ifdef BCM_CNIC
4311 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED,
4312 &bp->sp_state))
4313 bnx2x_set_iscsi_eth_rx_mode(bp, true);
4314 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED,
4315 &bp->sp_state))
4316 bnx2x_set_iscsi_eth_rx_mode(bp, false);
4317#endif
4318
4319 netif_addr_unlock_bh(bp->dev);
4320}
4321
4322static inline struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj(
4323 struct bnx2x *bp, u32 cid)
4324{
6383c0b3 4325 DP(BNX2X_MSG_SP, "retrieving fp from cid %d", cid);
619c5cb6
VZ		 4326#ifdef BCM_CNIC
4327 if (cid == BNX2X_FCOE_ETH_CID)
4328 return &bnx2x_fcoe(bp, q_obj);
4329 else
4330#endif
6383c0b3 4331 return &bnx2x_fp(bp, CID_TO_FP(cid), q_obj);
619c5cb6
VZ		 4332}
4333
523224a3
DK		 4334static void bnx2x_eq_int(struct bnx2x *bp)
4335{
4336 u16 hw_cons, sw_cons, sw_prod;
4337 union event_ring_elem *elem;
4338 u32 cid;
4339 u8 opcode;
4340 int spqe_cnt = 0;
619c5cb6
VZ		 4341 struct bnx2x_queue_sp_obj *q_obj;
4342 struct bnx2x_func_sp_obj *f_obj = &bp->func_obj;
4343 struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw;
523224a3
DK		 4344
4345 hw_cons = le16_to_cpu(*bp->eq_cons_sb);
4346
4347 /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
4348 * when we get the the next-page we nned to adjust so the loop
4349 * condition below will be met. The next element is the size of a
4350 * regular element and hence incrementing by 1
4351 */
4352 if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE)
4353 hw_cons++;
4354
25985edc 4355 /* This function may never run in parallel with itself for a
523224a3
DK		 4356 * specific bp, thus there is no need in "paired" read memory
4357 * barrier here.
4358 */
4359 sw_cons = bp->eq_cons;
4360 sw_prod = bp->eq_prod;
4361
6e30dd4e
VZ		 4362 DP(BNX2X_MSG_SP, "EQ: hw_cons %u sw_cons %u bp->cq_spq_left %u\n",
4363 hw_cons, sw_cons, atomic_read(&bp->eq_spq_left));
523224a3
DK		 4364
4365 for (; sw_cons != hw_cons;
4366 sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
4367
4368
4369 elem = &bp->eq_ring[EQ_DESC(sw_cons)];
4370
4371 cid = SW_CID(elem->message.data.cfc_del_event.cid);
4372 opcode = elem->message.opcode;
4373
4374
4375 /* handle eq element */
4376 switch (opcode) {
4377 case EVENT_RING_OPCODE_STAT_QUERY:
619c5cb6
VZ		 4378 DP(NETIF_MSG_TIMER, "got statistics comp event %d\n",
4379 bp->stats_comp++);
523224a3
DK		 4380 /* nothing to do with stats comp */
4381 continue;
4382
4383 case EVENT_RING_OPCODE_CFC_DEL:
4384 /* handle according to cid range */
4385 /*
4386 * we may want to verify here that the bp state is
4387 * HALTING
4388 */
4389 DP(NETIF_MSG_IFDOWN,
4390 "got delete ramrod for MULTI[%d]\n", cid);
4391#ifdef BCM_CNIC
4392 if (!bnx2x_cnic_handle_cfc_del(bp, cid, elem))
4393 goto next_spqe;
4394#endif
619c5cb6
VZ		 4395 q_obj = bnx2x_cid_to_q_obj(bp, cid);
4396
4397 if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL))
4398 break;
4399
4400
523224a3
DK		 4401
4402 goto next_spqe;
e4901dde
VZ		 4403
4404 case EVENT_RING_OPCODE_STOP_TRAFFIC:
4405 DP(NETIF_MSG_IFUP, "got STOP TRAFFIC\n");
4406 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED);
4407 goto next_spqe;
619c5cb6 4408
e4901dde
VZ		 4409 case EVENT_RING_OPCODE_START_TRAFFIC:
4410 DP(NETIF_MSG_IFUP, "got START TRAFFIC\n");
4411 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED);
4412 goto next_spqe;
619c5cb6
VZ		 4413 case EVENT_RING_OPCODE_FUNCTION_START:
4414 DP(NETIF_MSG_IFUP, "got FUNC_START ramrod\n");
4415 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START))
4416 break;
4417
4418 goto next_spqe;
4419
4420 case EVENT_RING_OPCODE_FUNCTION_STOP:
4421 DP(NETIF_MSG_IFDOWN, "got FUNC_STOP ramrod\n");
4422 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP))
4423 break;
4424
4425 goto next_spqe;
523224a3
DK		 4426 }
4427
4428 switch (opcode | bp->state) {
619c5cb6
VZ		 4429 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
4430 BNX2X_STATE_OPEN):
4431 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
523224a3 4432 BNX2X_STATE_OPENING_WAIT4_PORT):
619c5cb6
VZ		 4433 cid = elem->message.data.eth_event.echo &
4434 BNX2X_SWCID_MASK;
4435 DP(NETIF_MSG_IFUP, "got RSS_UPDATE ramrod. CID %d\n",
4436 cid);
4437 rss_raw->clear_pending(rss_raw);
523224a3
DK		 4438 break;
4439
619c5cb6
VZ		 4440 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
4441 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
4442 case (EVENT_RING_OPCODE_SET_MAC |
523224a3 4443 BNX2X_STATE_CLOSING_WAIT4_HALT):
619c5cb6
VZ		 4444 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
4445 BNX2X_STATE_OPEN):
4446 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
4447 BNX2X_STATE_DIAG):
4448 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
4449 BNX2X_STATE_CLOSING_WAIT4_HALT):
4450 DP(NETIF_MSG_IFUP, "got (un)set mac ramrod\n");
4451 bnx2x_handle_classification_eqe(bp, elem);
523224a3
DK		 4452 break;
4453
619c5cb6
VZ		 4454 case (EVENT_RING_OPCODE_MULTICAST_RULES |
4455 BNX2X_STATE_OPEN):
4456 case (EVENT_RING_OPCODE_MULTICAST_RULES |
4457 BNX2X_STATE_DIAG):
4458 case (EVENT_RING_OPCODE_MULTICAST_RULES |
4459 BNX2X_STATE_CLOSING_WAIT4_HALT):
4460 DP(NETIF_MSG_IFUP, "got mcast ramrod\n");
4461 bnx2x_handle_mcast_eqe(bp);
523224a3
DK		 4462 break;
4463
619c5cb6
VZ		 4464 case (EVENT_RING_OPCODE_FILTERS_RULES |
4465 BNX2X_STATE_OPEN):
4466 case (EVENT_RING_OPCODE_FILTERS_RULES |
4467 BNX2X_STATE_DIAG):
4468 case (EVENT_RING_OPCODE_FILTERS_RULES |
523224a3 4469 BNX2X_STATE_CLOSING_WAIT4_HALT):
619c5cb6
VZ		 4470 DP(NETIF_MSG_IFUP, "got rx_mode ramrod\n");
4471 bnx2x_handle_rx_mode_eqe(bp);
523224a3
DK		 4472 break;
4473 default:
4474 /* unknown event log error and continue */
619c5cb6
VZ		 4475 BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n",
4476 elem->message.opcode, bp->state);
523224a3
DK		 4477 }
4478next_spqe:
4479 spqe_cnt++;
4480 } /* for */
4481
8fe23fbd 4482 smp_mb__before_atomic_inc();
6e30dd4e 4483 atomic_add(spqe_cnt, &bp->eq_spq_left);
523224a3
DK		 4484
4485 bp->eq_cons = sw_cons;
4486 bp->eq_prod = sw_prod;
4487 /* Make sure that above mem writes were issued towards the memory */
4488 smp_wmb();
4489
4490 /* update producer */
4491 bnx2x_update_eq_prod(bp, bp->eq_prod);
4492}
4493
a2fbb9ea
ET		 4494static void bnx2x_sp_task(struct work_struct *work)
4495{
1cf167f2 4496 struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
a2fbb9ea
ET		 4497 u16 status;
4498
a2fbb9ea 4499 status = bnx2x_update_dsb_idx(bp);
34f80b04
EG		 4500/* if (status == 0) */
4501/* BNX2X_ERR("spurious slowpath interrupt!\n"); */
a2fbb9ea 4502
cdaa7cb8 4503 DP(NETIF_MSG_INTR, "got a slowpath interrupt (status 0x%x)\n", status);
a2fbb9ea 4504
877e9aa4 4505 /* HW attentions */
523224a3 4506 if (status & BNX2X_DEF_SB_ATT_IDX) {
a2fbb9ea 4507 bnx2x_attn_int(bp);
523224a3 4508 status &= ~BNX2X_DEF_SB_ATT_IDX;
cdaa7cb8
VZ		 4509 }
4510
523224a3
DK		 4511 /* SP events: STAT_QUERY and others */
4512 if (status & BNX2X_DEF_SB_IDX) {
ec6ba945
VZ		 4513#ifdef BCM_CNIC
4514 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
523224a3 4515
ec6ba945
VZ		 4516 if ((!NO_FCOE(bp)) &&
4517 (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp)))
4518 napi_schedule(&bnx2x_fcoe(bp, napi));
4519#endif
523224a3
DK		 4520 /* Handle EQ completions */
4521 bnx2x_eq_int(bp);
4522
4523 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID,
4524 le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1);
4525
4526 status &= ~BNX2X_DEF_SB_IDX;
cdaa7cb8
VZ		 4527 }
4528
4529 if (unlikely(status))
4530 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
4531 status);
a2fbb9ea 4532
523224a3
DK		 4533 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID,
4534 le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1);
a2fbb9ea
ET		 4535}
4536
9f6c9258 4537irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
a2fbb9ea
ET		 4538{
4539 struct net_device *dev = dev_instance;
4540 struct bnx2x *bp = netdev_priv(dev);
4541
523224a3
DK		 4542 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0,
4543 IGU_INT_DISABLE, 0);
a2fbb9ea
ET		 4544
4545#ifdef BNX2X_STOP_ON_ERROR
4546 if (unlikely(bp->panic))
4547 return IRQ_HANDLED;
4548#endif
4549
993ac7b5
MC		 4550#ifdef BCM_CNIC
4551 {
4552 struct cnic_ops *c_ops;
4553
4554 rcu_read_lock();
4555 c_ops = rcu_dereference(bp->cnic_ops);
4556 if (c_ops)
4557 c_ops->cnic_handler(bp->cnic_data, NULL);
4558 rcu_read_unlock();
4559 }
4560#endif
1cf167f2 4561 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
a2fbb9ea
ET		 4562
4563 return IRQ_HANDLED;
4564}
4565
4566/* end of slow path */
4567
619c5cb6
VZ		 4568
4569void bnx2x_drv_pulse(struct bnx2x *bp)
4570{
4571 SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb,
4572 bp->fw_drv_pulse_wr_seq);
4573}
4574
4575
a2fbb9ea
ET		 4576static void bnx2x_timer(unsigned long data)
4577{
6383c0b3 4578 u8 cos;
a2fbb9ea
ET		 4579 struct bnx2x *bp = (struct bnx2x *) data;
4580
4581 if (!netif_running(bp->dev))
4582 return;
4583
a2fbb9ea
ET		 4584 if (poll) {
4585 struct bnx2x_fastpath *fp = &bp->fp[0];
a2fbb9ea 4586
6383c0b3
AE		 4587 for_each_cos_in_tx_queue(fp, cos)
4588 bnx2x_tx_int(bp, &fp->txdata[cos]);
b8ee8328 4589 bnx2x_rx_int(fp, 1000);
a2fbb9ea
ET		 4590 }
4591
34f80b04 4592 if (!BP_NOMCP(bp)) {
f2e0899f 4593 int mb_idx = BP_FW_MB_IDX(bp);
a2fbb9ea
ET		 4594 u32 drv_pulse;
4595 u32 mcp_pulse;
4596
4597 ++bp->fw_drv_pulse_wr_seq;
4598 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
4599 /* TBD - add SYSTEM_TIME */
4600 drv_pulse = bp->fw_drv_pulse_wr_seq;
619c5cb6 4601 bnx2x_drv_pulse(bp);
a2fbb9ea 4602
f2e0899f 4603 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) &
a2fbb9ea
ET		 4604 MCP_PULSE_SEQ_MASK);
4605 /* The delta between driver pulse and mcp response
4606 * should be 1 (before mcp response) or 0 (after mcp response)
4607 */
4608 if ((drv_pulse != mcp_pulse) &&
4609 (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
4610 /* someone lost a heartbeat... */
4611 BNX2X_ERR("drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
4612 drv_pulse, mcp_pulse);
4613 }
4614 }
4615
f34d28ea 4616 if (bp->state == BNX2X_STATE_OPEN)
bb2a0f7a 4617 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
a2fbb9ea 4618
a2fbb9ea
ET		 4619 mod_timer(&bp->timer, jiffies + bp->current_interval);
4620}
4621
4622/* end of Statistics */
4623
4624/* nic init */
4625
4626/*
4627 * nic init service functions
4628 */
4629
523224a3 4630static inline void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
a2fbb9ea 4631{
523224a3
DK		 4632 u32 i;
4633 if (!(len%4) && !(addr%4))
4634 for (i = 0; i < len; i += 4)
4635 REG_WR(bp, addr + i, fill);
4636 else
4637 for (i = 0; i < len; i++)
4638 REG_WR8(bp, addr + i, fill);
34f80b04 4639
34f80b04
EG		 4640}
4641
523224a3
DK		 4642/* helper: writes FP SP data to FW - data_size in dwords */
4643static inline void bnx2x_wr_fp_sb_data(struct bnx2x *bp,
4644 int fw_sb_id,
4645 u32 *sb_data_p,
4646 u32 data_size)
34f80b04 4647{
a2fbb9ea 4648 int index;
523224a3
DK		 4649 for (index = 0; index < data_size; index++)
4650 REG_WR(bp, BAR_CSTRORM_INTMEM +
4651 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
4652 sizeof(u32)*index,
4653 *(sb_data_p + index));
4654}
a2fbb9ea 4655
523224a3
DK		 4656static inline void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id)
4657{
4658 u32 *sb_data_p;
4659 u32 data_size = 0;
f2e0899f 4660 struct hc_status_block_data_e2 sb_data_e2;
523224a3 4661 struct hc_status_block_data_e1x sb_data_e1x;
a2fbb9ea 4662
523224a3 4663 /* disable the function first */
619c5cb6 4664 if (!CHIP_IS_E1x(bp)) {
f2e0899f 4665 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
619c5cb6 4666 sb_data_e2.common.state = SB_DISABLED;
f2e0899f
DK		 4667 sb_data_e2.common.p_func.vf_valid = false;
4668 sb_data_p = (u32 *)&sb_data_e2;
4669 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
4670 } else {
4671 memset(&sb_data_e1x, 0,
4672 sizeof(struct hc_status_block_data_e1x));
619c5cb6 4673 sb_data_e1x.common.state = SB_DISABLED;
f2e0899f
DK		 4674 sb_data_e1x.common.p_func.vf_valid = false;
4675 sb_data_p = (u32 *)&sb_data_e1x;
4676 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
4677 }
523224a3 4678 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
a2fbb9ea 4679
523224a3
DK		 4680 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4681 CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0,
4682 CSTORM_STATUS_BLOCK_SIZE);
4683 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4684 CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0,
4685 CSTORM_SYNC_BLOCK_SIZE);
4686}
34f80b04 4687
523224a3
DK		 4688/* helper: writes SP SB data to FW */
4689static inline void bnx2x_wr_sp_sb_data(struct bnx2x *bp,
4690 struct hc_sp_status_block_data *sp_sb_data)
4691{
4692 int func = BP_FUNC(bp);
4693 int i;
4694 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
4695 REG_WR(bp, BAR_CSTRORM_INTMEM +
4696 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
4697 i*sizeof(u32),
4698 *((u32 *)sp_sb_data + i));
34f80b04
EG		 4699}
4700
523224a3 4701static inline void bnx2x_zero_sp_sb(struct bnx2x *bp)
34f80b04
EG		 4702{
4703 int func = BP_FUNC(bp);
523224a3
DK		 4704 struct hc_sp_status_block_data sp_sb_data;
4705 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
a2fbb9ea 4706
619c5cb6 4707 sp_sb_data.state = SB_DISABLED;
523224a3
DK		 4708 sp_sb_data.p_func.vf_valid = false;
4709
4710 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
4711
4712 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4713 CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0,
4714 CSTORM_SP_STATUS_BLOCK_SIZE);
4715 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4716 CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0,
4717 CSTORM_SP_SYNC_BLOCK_SIZE);
4718
4719}
4720
4721
4722static inline
4723void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
4724 int igu_sb_id, int igu_seg_id)
4725{
4726 hc_sm->igu_sb_id = igu_sb_id;
4727 hc_sm->igu_seg_id = igu_seg_id;
4728 hc_sm->timer_value = 0xFF;
4729 hc_sm->time_to_expire = 0xFFFFFFFF;
a2fbb9ea
ET		 4730}
4731
8d96286a 4732static void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
523224a3 4733 u8 vf_valid, int fw_sb_id, int igu_sb_id)
a2fbb9ea 4734{
523224a3
DK		 4735 int igu_seg_id;
4736
f2e0899f 4737 struct hc_status_block_data_e2 sb_data_e2;
523224a3
DK		 4738 struct hc_status_block_data_e1x sb_data_e1x;
4739 struct hc_status_block_sm *hc_sm_p;
523224a3
DK		 4740 int data_size;
4741 u32 *sb_data_p;
4742
f2e0899f
DK		 4743 if (CHIP_INT_MODE_IS_BC(bp))
4744 igu_seg_id = HC_SEG_ACCESS_NORM;
4745 else
4746 igu_seg_id = IGU_SEG_ACCESS_NORM;
523224a3
DK		 4747
4748 bnx2x_zero_fp_sb(bp, fw_sb_id);
4749
619c5cb6 4750 if (!CHIP_IS_E1x(bp)) {
f2e0899f 4751 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
619c5cb6 4752 sb_data_e2.common.state = SB_ENABLED;
f2e0899f
DK		 4753 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp);
4754 sb_data_e2.common.p_func.vf_id = vfid;
4755 sb_data_e2.common.p_func.vf_valid = vf_valid;
4756 sb_data_e2.common.p_func.vnic_id = BP_VN(bp);
4757 sb_data_e2.common.same_igu_sb_1b = true;
4758 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping);
4759 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping);
4760 hc_sm_p = sb_data_e2.common.state_machine;
f2e0899f
DK		 4761 sb_data_p = (u32 *)&sb_data_e2;
4762 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
4763 } else {
4764 memset(&sb_data_e1x, 0,
4765 sizeof(struct hc_status_block_data_e1x));
619c5cb6 4766 sb_data_e1x.common.state = SB_ENABLED;
f2e0899f
DK		 4767 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp);
4768 sb_data_e1x.common.p_func.vf_id = 0xff;
4769 sb_data_e1x.common.p_func.vf_valid = false;
4770 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp);
4771 sb_data_e1x.common.same_igu_sb_1b = true;
4772 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping);
4773 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping);
4774 hc_sm_p = sb_data_e1x.common.state_machine;
f2e0899f
DK		 4775 sb_data_p = (u32 *)&sb_data_e1x;
4776 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
4777 }
523224a3
DK		 4778
4779 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID],
4780 igu_sb_id, igu_seg_id);
4781 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID],
4782 igu_sb_id, igu_seg_id);
4783
4784 DP(NETIF_MSG_HW, "Init FW SB %d\n", fw_sb_id);
4785
4786 /* write indecies to HW */
4787 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
4788}
4789
619c5cb6 4790static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id,
523224a3
DK		 4791 u16 tx_usec, u16 rx_usec)
4792{
6383c0b3 4793 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS,
523224a3 4794 false, rx_usec);
6383c0b3
AE		 4795 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
4796 HC_INDEX_ETH_TX_CQ_CONS_COS0, false,
4797 tx_usec);
4798 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
4799 HC_INDEX_ETH_TX_CQ_CONS_COS1, false,
4800 tx_usec);
4801 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
4802 HC_INDEX_ETH_TX_CQ_CONS_COS2, false,
4803 tx_usec);
523224a3 4804}
f2e0899f 4805
523224a3
DK		 4806static void bnx2x_init_def_sb(struct bnx2x *bp)
4807{
4808 struct host_sp_status_block *def_sb = bp->def_status_blk;
4809 dma_addr_t mapping = bp->def_status_blk_mapping;
4810 int igu_sp_sb_index;
4811 int igu_seg_id;
34f80b04
EG		 4812 int port = BP_PORT(bp);
4813 int func = BP_FUNC(bp);
523224a3 4814 int reg_offset;
a2fbb9ea 4815 u64 section;
523224a3
DK		 4816 int index;
4817 struct hc_sp_status_block_data sp_sb_data;
4818 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
4819
f2e0899f
DK		 4820 if (CHIP_INT_MODE_IS_BC(bp)) {
4821 igu_sp_sb_index = DEF_SB_IGU_ID;
4822 igu_seg_id = HC_SEG_ACCESS_DEF;
4823 } else {
4824 igu_sp_sb_index = bp->igu_dsb_id;
4825 igu_seg_id = IGU_SEG_ACCESS_DEF;
4826 }
a2fbb9ea
ET		 4827
4828 /* ATTN */
523224a3 4829 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
a2fbb9ea 4830 atten_status_block);
523224a3 4831 def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
a2fbb9ea 4832
49d66772
ET		 4833 bp->attn_state = 0;
4834
a2fbb9ea
ET		 4835 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4836 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
34f80b04 4837 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
523224a3
DK		 4838 int sindex;
4839 /* take care of sig[0]..sig[4] */
4840 for (sindex = 0; sindex < 4; sindex++)
4841 bp->attn_group[index].sig[sindex] =
4842 REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);
f2e0899f 4843
619c5cb6 4844 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 4845 /*
4846 * enable5 is separate from the rest of the registers,
4847 * and therefore the address skip is 4
4848 * and not 16 between the different groups
4849 */
4850 bp->attn_group[index].sig[4] = REG_RD(bp,
4851 reg_offset + 0x10 + 0x4*index);
4852 else
4853 bp->attn_group[index].sig[4] = 0;
a2fbb9ea
ET		 4854 }
4855
f2e0899f
DK		 4856 if (bp->common.int_block == INT_BLOCK_HC) {
4857 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
4858 HC_REG_ATTN_MSG0_ADDR_L);
4859
4860 REG_WR(bp, reg_offset, U64_LO(section));
4861 REG_WR(bp, reg_offset + 4, U64_HI(section));
619c5cb6 4862 } else if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 4863 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
4864 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
4865 }
a2fbb9ea 4866
523224a3
DK		 4867 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
4868 sp_sb);
a2fbb9ea 4869
523224a3 4870 bnx2x_zero_sp_sb(bp);
a2fbb9ea 4871
619c5cb6 4872 sp_sb_data.state = SB_ENABLED;
523224a3
DK		 4873 sp_sb_data.host_sb_addr.lo = U64_LO(section);
4874 sp_sb_data.host_sb_addr.hi = U64_HI(section);
4875 sp_sb_data.igu_sb_id = igu_sp_sb_index;
4876 sp_sb_data.igu_seg_id = igu_seg_id;
4877 sp_sb_data.p_func.pf_id = func;
f2e0899f 4878 sp_sb_data.p_func.vnic_id = BP_VN(bp);
523224a3 4879 sp_sb_data.p_func.vf_id = 0xff;
a2fbb9ea 4880
523224a3 4881 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
49d66772 4882
523224a3 4883 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
a2fbb9ea
ET		 4884}
4885
9f6c9258 4886void bnx2x_update_coalesce(struct bnx2x *bp)
a2fbb9ea 4887{
a2fbb9ea
ET		 4888 int i;
4889
ec6ba945 4890 for_each_eth_queue(bp, i)
523224a3 4891 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id,
423cfa7e 4892 bp->tx_ticks, bp->rx_ticks);
a2fbb9ea
ET		 4893}
4894
a2fbb9ea
ET		 4895static void bnx2x_init_sp_ring(struct bnx2x *bp)
4896{
a2fbb9ea 4897 spin_lock_init(&bp->spq_lock);
6e30dd4e 4898 atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING);
a2fbb9ea 4899
a2fbb9ea 4900 bp->spq_prod_idx = 0;
a2fbb9ea
ET		 4901 bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
4902 bp->spq_prod_bd = bp->spq;
4903 bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
a2fbb9ea
ET		 4904}
4905
523224a3 4906static void bnx2x_init_eq_ring(struct bnx2x *bp)
a2fbb9ea
ET		 4907{
4908 int i;
523224a3
DK		 4909 for (i = 1; i <= NUM_EQ_PAGES; i++) {
4910 union event_ring_elem *elem =
4911 &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1];
a2fbb9ea 4912
523224a3
DK		 4913 elem->next_page.addr.hi =
4914 cpu_to_le32(U64_HI(bp->eq_mapping +
4915 BCM_PAGE_SIZE * (i % NUM_EQ_PAGES)));
4916 elem->next_page.addr.lo =
4917 cpu_to_le32(U64_LO(bp->eq_mapping +
4918 BCM_PAGE_SIZE*(i % NUM_EQ_PAGES)));
a2fbb9ea 4919 }
523224a3
DK		 4920 bp->eq_cons = 0;
4921 bp->eq_prod = NUM_EQ_DESC;
4922 bp->eq_cons_sb = BNX2X_EQ_INDEX;
6e30dd4e
VZ		 4923 /* we want a warning message before it gets rought... */
4924 atomic_set(&bp->eq_spq_left,
4925 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1);
a2fbb9ea
ET		 4926}
4927
619c5cb6
VZ		 4928
4929/* called with netif_addr_lock_bh() */
4930void bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id,
4931 unsigned long rx_mode_flags,
4932 unsigned long rx_accept_flags,
4933 unsigned long tx_accept_flags,
4934 unsigned long ramrod_flags)
ab532cf3 4935{
619c5cb6
VZ		 4936 struct bnx2x_rx_mode_ramrod_params ramrod_param;
4937 int rc;
4938
4939 memset(&ramrod_param, 0, sizeof(ramrod_param));
4940
4941 /* Prepare ramrod parameters */
4942 ramrod_param.cid = 0;
4943 ramrod_param.cl_id = cl_id;
4944 ramrod_param.rx_mode_obj = &bp->rx_mode_obj;
4945 ramrod_param.func_id = BP_FUNC(bp);
ab532cf3 4946
619c5cb6
VZ		 4947 ramrod_param.pstate = &bp->sp_state;
4948 ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING;
ab532cf3 4949
619c5cb6
VZ		 4950 ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata);
4951 ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata);
4952
4953 set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
4954
4955 ramrod_param.ramrod_flags = ramrod_flags;
4956 ramrod_param.rx_mode_flags = rx_mode_flags;
4957
4958 ramrod_param.rx_accept_flags = rx_accept_flags;
4959 ramrod_param.tx_accept_flags = tx_accept_flags;
4960
4961 rc = bnx2x_config_rx_mode(bp, &ramrod_param);
4962 if (rc < 0) {
4963 BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode);
4964 return;
4965 }
a2fbb9ea
ET		 4966}
4967
619c5cb6
VZ		 4968/* called with netif_addr_lock_bh() */
4969void bnx2x_set_storm_rx_mode(struct bnx2x *bp)
471de716 4970{
619c5cb6
VZ		 4971 unsigned long rx_mode_flags = 0, ramrod_flags = 0;
4972 unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
471de716 4973
619c5cb6
VZ		 4974#ifdef BCM_CNIC
4975 if (!NO_FCOE(bp))
4976
4977 /* Configure rx_mode of FCoE Queue */
4978 __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags);
4979#endif
4980
4981 switch (bp->rx_mode) {
4982 case BNX2X_RX_MODE_NONE:
4983 /*
4984 * 'drop all' supersedes any accept flags that may have been
4985 * passed to the function.
4986 */
4987 break;
4988 case BNX2X_RX_MODE_NORMAL:
4989 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
4990 __set_bit(BNX2X_ACCEPT_MULTICAST, &rx_accept_flags);
4991 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
4992
4993 /* internal switching mode */
4994 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
4995 __set_bit(BNX2X_ACCEPT_MULTICAST, &tx_accept_flags);
4996 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
4997
4998 break;
4999 case BNX2X_RX_MODE_ALLMULTI:
5000 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
5001 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags);
5002 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
5003
5004 /* internal switching mode */
5005 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
5006 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags);
5007 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
5008
5009 break;
5010 case BNX2X_RX_MODE_PROMISC:
5011 /* According to deffinition of SI mode, iface in promisc mode
5012 * should receive matched and unmatched (in resolution of port)
5013 * unicast packets.
5014 */
5015 __set_bit(BNX2X_ACCEPT_UNMATCHED, &rx_accept_flags);
5016 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
5017 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags);
5018 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
5019
5020 /* internal switching mode */
5021 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags);
5022 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
5023
5024 if (IS_MF_SI(bp))
5025 __set_bit(BNX2X_ACCEPT_ALL_UNICAST, &tx_accept_flags);
5026 else
5027 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
5028
5029 break;
5030 default:
5031 BNX2X_ERR("Unknown rx_mode: %d\n", bp->rx_mode);
5032 return;
5033 }
de832a55 5034
619c5cb6
VZ		 5035 if (bp->rx_mode != BNX2X_RX_MODE_NONE) {
5036 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &rx_accept_flags);
5037 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &tx_accept_flags);
34f80b04
EG		 5038 }
5039
619c5cb6
VZ		 5040 __set_bit(RAMROD_RX, &ramrod_flags);
5041 __set_bit(RAMROD_TX, &ramrod_flags);
5042
5043 bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags, rx_accept_flags,
5044 tx_accept_flags, ramrod_flags);
5045}
5046
5047static void bnx2x_init_internal_common(struct bnx2x *bp)
5048{
5049 int i;
5050
0793f83f
DK		 5051 if (IS_MF_SI(bp))
5052 /*
5053 * In switch independent mode, the TSTORM needs to accept
5054 * packets that failed classification, since approximate match
5055 * mac addresses aren't written to NIG LLH
5056 */
5057 REG_WR8(bp, BAR_TSTRORM_INTMEM +
5058 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 2);
619c5cb6
VZ		 5059 else if (!CHIP_IS_E1(bp)) /* 57710 doesn't support MF */
5060 REG_WR8(bp, BAR_TSTRORM_INTMEM +
5061 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 0);
0793f83f 5062
523224a3
DK		 5063 /* Zero this manually as its initialization is
5064 currently missing in the initTool */
5065 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
ca00392c 5066 REG_WR(bp, BAR_USTRORM_INTMEM +
523224a3 5067 USTORM_AGG_DATA_OFFSET + i * 4, 0);
619c5cb6 5068 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 5069 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET,
5070 CHIP_INT_MODE_IS_BC(bp) ?
5071 HC_IGU_BC_MODE : HC_IGU_NBC_MODE);
5072 }
523224a3 5073}
8a1c38d1 5074
471de716
EG		 5075static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
5076{
5077 switch (load_code) {
5078 case FW_MSG_CODE_DRV_LOAD_COMMON:
f2e0899f 5079 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
471de716
EG		 5080 bnx2x_init_internal_common(bp);
5081 /* no break */
5082
5083 case FW_MSG_CODE_DRV_LOAD_PORT:
619c5cb6 5084 /* nothing to do */
471de716
EG		 5085 /* no break */
5086
5087 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
523224a3
DK		 5088 /* internal memory per function is
5089 initialized inside bnx2x_pf_init */
471de716
EG		 5090 break;
5091
5092 default:
5093 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
5094 break;
5095 }
5096}
5097
619c5cb6 5098static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp)
523224a3 5099{
6383c0b3 5100 return fp->bp->igu_base_sb + fp->index + CNIC_PRESENT;
619c5cb6 5101}
523224a3 5102
619c5cb6
VZ		 5103static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp)
5104{
6383c0b3 5105 return fp->bp->base_fw_ndsb + fp->index + CNIC_PRESENT;
619c5cb6
VZ		 5106}
5107
5108static inline u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp)
5109{
5110 if (CHIP_IS_E1x(fp->bp))
5111 return BP_L_ID(fp->bp) + fp->index;
5112 else /* We want Client ID to be the same as IGU SB ID for 57712 */
5113 return bnx2x_fp_igu_sb_id(fp);
5114}
5115
6383c0b3 5116static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx)
619c5cb6
VZ		 5117{
5118 struct bnx2x_fastpath *fp = &bp->fp[fp_idx];
6383c0b3 5119 u8 cos;
619c5cb6 5120 unsigned long q_type = 0;
6383c0b3 5121 u32 cids[BNX2X_MULTI_TX_COS] = { 0 };
523224a3 5122
b3b83c3f 5123 fp->cid = fp_idx;
619c5cb6
VZ		 5124 fp->cl_id = bnx2x_fp_cl_id(fp);
5125 fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp);
5126 fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp);
523224a3 5127 /* qZone id equals to FW (per path) client id */
619c5cb6
VZ		 5128 fp->cl_qzone_id = bnx2x_fp_qzone_id(fp);
5129
523224a3 5130 /* init shortcut */
619c5cb6 5131 fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp);
523224a3
DK		 5132 /* Setup SB indicies */
5133 fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
523224a3 5134
619c5cb6
VZ		 5135 /* Configure Queue State object */
5136 __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
5137 __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
6383c0b3
AE		 5138
5139 BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS);
5140
5141 /* init tx data */
5142 for_each_cos_in_tx_queue(fp, cos) {
5143 bnx2x_init_txdata(bp, &fp->txdata[cos],
5144 CID_COS_TO_TX_ONLY_CID(fp->cid, cos),
5145 FP_COS_TO_TXQ(fp, cos),
5146 BNX2X_TX_SB_INDEX_BASE + cos);
5147 cids[cos] = fp->txdata[cos].cid;
5148 }
5149
5150 bnx2x_init_queue_obj(bp, &fp->q_obj, fp->cl_id, cids, fp->max_cos,
5151 BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
5152 bnx2x_sp_mapping(bp, q_rdata), q_type);
619c5cb6
VZ		 5153
5154 /**
5155 * Configure classification DBs: Always enable Tx switching
5156 */
5157 bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX);
5158
523224a3
DK		 5159 DP(NETIF_MSG_IFUP, "queue[%d]: bnx2x_init_sb(%p,%p) "
5160 "cl_id %d fw_sb %d igu_sb %d\n",
619c5cb6 5161 fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
523224a3
DK		 5162 fp->igu_sb_id);
5163 bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false,
5164 fp->fw_sb_id, fp->igu_sb_id);
5165
5166 bnx2x_update_fpsb_idx(fp);
5167}
5168
9f6c9258 5169void bnx2x_nic_init(struct bnx2x *bp, u32 load_code)
a2fbb9ea
ET		 5170{
5171 int i;
5172
ec6ba945 5173 for_each_eth_queue(bp, i)
6383c0b3 5174 bnx2x_init_eth_fp(bp, i);
37b091ba 5175#ifdef BCM_CNIC
ec6ba945
VZ		 5176 if (!NO_FCOE(bp))
5177 bnx2x_init_fcoe_fp(bp);
523224a3
DK		 5178
5179 bnx2x_init_sb(bp, bp->cnic_sb_mapping,
5180 BNX2X_VF_ID_INVALID, false,
619c5cb6 5181 bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp));
523224a3 5182
37b091ba 5183#endif
a2fbb9ea 5184
020c7e3f
YR		 5185 /* Initialize MOD_ABS interrupts */
5186 bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id,
5187 bp->common.shmem_base, bp->common.shmem2_base,
5188 BP_PORT(bp));
16119785
EG		 5189 /* ensure status block indices were read */
5190 rmb();
5191
523224a3 5192 bnx2x_init_def_sb(bp);
5c862848 5193 bnx2x_update_dsb_idx(bp);
a2fbb9ea 5194 bnx2x_init_rx_rings(bp);
523224a3 5195 bnx2x_init_tx_rings(bp);
a2fbb9ea 5196 bnx2x_init_sp_ring(bp);
523224a3 5197 bnx2x_init_eq_ring(bp);
471de716 5198 bnx2x_init_internal(bp, load_code);
523224a3 5199 bnx2x_pf_init(bp);
0ef00459
EG		 5200 bnx2x_stats_init(bp);
5201
0ef00459
EG		 5202 /* flush all before enabling interrupts */
5203 mb();
5204 mmiowb();
5205
615f8fd9 5206 bnx2x_int_enable(bp);
eb8da205
EG		 5207
5208 /* Check for SPIO5 */
5209 bnx2x_attn_int_deasserted0(bp,
5210 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) &
5211 AEU_INPUTS_ATTN_BITS_SPIO5);
a2fbb9ea
ET		 5212}
5213
5214/* end of nic init */
5215
5216/*
5217 * gzip service functions
5218 */
5219
5220static int bnx2x_gunzip_init(struct bnx2x *bp)
5221{
1a983142
FT		 5222 bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE,
5223 &bp->gunzip_mapping, GFP_KERNEL);
a2fbb9ea
ET		 5224 if (bp->gunzip_buf == NULL)
5225 goto gunzip_nomem1;
5226
5227 bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
5228 if (bp->strm == NULL)
5229 goto gunzip_nomem2;
5230
7ab24bfd 5231 bp->strm->workspace = vmalloc(zlib_inflate_workspacesize());
a2fbb9ea
ET		 5232 if (bp->strm->workspace == NULL)
5233 goto gunzip_nomem3;
5234
5235 return 0;
5236
5237gunzip_nomem3:
5238 kfree(bp->strm);
5239 bp->strm = NULL;
5240
5241gunzip_nomem2:
1a983142
FT		 5242 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
5243 bp->gunzip_mapping);
a2fbb9ea
ET		 5244 bp->gunzip_buf = NULL;
5245
5246gunzip_nomem1:
cdaa7cb8
VZ		 5247 netdev_err(bp->dev, "Cannot allocate firmware buffer for"
5248 " un-compression\n");
a2fbb9ea
ET		 5249 return -ENOMEM;
5250}
5251
5252static void bnx2x_gunzip_end(struct bnx2x *bp)
5253{
b3b83c3f 5254 if (bp->strm) {
7ab24bfd 5255 vfree(bp->strm->workspace);
b3b83c3f
DK		 5256 kfree(bp->strm);
5257 bp->strm = NULL;
5258 }
a2fbb9ea
ET		 5259
5260 if (bp->gunzip_buf) {
1a983142
FT		 5261 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
5262 bp->gunzip_mapping);
a2fbb9ea
ET		 5263 bp->gunzip_buf = NULL;
5264 }
5265}
5266
94a78b79 5267static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len)
a2fbb9ea
ET		 5268{
5269 int n, rc;
5270
5271 /* check gzip header */
94a78b79
VZ		 5272 if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) {
5273 BNX2X_ERR("Bad gzip header\n");
a2fbb9ea 5274 return -EINVAL;
94a78b79 5275 }
a2fbb9ea
ET		 5276
5277 n = 10;
5278
34f80b04 5279#define FNAME 0x8
a2fbb9ea
ET		 5280
5281 if (zbuf[3] & FNAME)
5282 while ((zbuf[n++] != 0) && (n < len));
5283
94a78b79 5284 bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n;
a2fbb9ea
ET		 5285 bp->strm->avail_in = len - n;
5286 bp->strm->next_out = bp->gunzip_buf;
5287 bp->strm->avail_out = FW_BUF_SIZE;
5288
5289 rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
5290 if (rc != Z_OK)
5291 return rc;
5292
5293 rc = zlib_inflate(bp->strm, Z_FINISH);
5294 if ((rc != Z_OK) && (rc != Z_STREAM_END))
7995c64e
JP		 5295 netdev_err(bp->dev, "Firmware decompression error: %s\n",
5296 bp->strm->msg);
a2fbb9ea
ET		 5297
5298 bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
5299 if (bp->gunzip_outlen & 0x3)
cdaa7cb8
VZ		 5300 netdev_err(bp->dev, "Firmware decompression error:"
5301 " gunzip_outlen (%d) not aligned\n",
5302 bp->gunzip_outlen);
a2fbb9ea
ET		 5303 bp->gunzip_outlen >>= 2;
5304
5305 zlib_inflateEnd(bp->strm);
5306
5307 if (rc == Z_STREAM_END)
5308 return 0;
5309
5310 return rc;
5311}
5312
5313/* nic load/unload */
5314
5315/*
34f80b04 5316 * General service functions
a2fbb9ea
ET		 5317 */
5318
5319/* send a NIG loopback debug packet */
5320static void bnx2x_lb_pckt(struct bnx2x *bp)
5321{
a2fbb9ea 5322 u32 wb_write[3];
a2fbb9ea
ET		 5323
5324 /* Ethernet source and destination addresses */
a2fbb9ea
ET		 5325 wb_write[0] = 0x55555555;
5326 wb_write[1] = 0x55555555;
34f80b04 5327 wb_write[2] = 0x20; /* SOP */
a2fbb9ea 5328 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
a2fbb9ea
ET		 5329
5330 /* NON-IP protocol */
a2fbb9ea
ET		 5331 wb_write[0] = 0x09000000;
5332 wb_write[1] = 0x55555555;
34f80b04 5333 wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */
a2fbb9ea 5334 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
a2fbb9ea
ET		 5335}
5336
5337/* some of the internal memories
5338 * are not directly readable from the driver
5339 * to test them we send debug packets
5340 */
5341static int bnx2x_int_mem_test(struct bnx2x *bp)
5342{
5343 int factor;
5344 int count, i;
5345 u32 val = 0;
5346
ad8d3948 5347 if (CHIP_REV_IS_FPGA(bp))
a2fbb9ea 5348 factor = 120;
ad8d3948
EG		 5349 else if (CHIP_REV_IS_EMUL(bp))
5350 factor = 200;
5351 else
a2fbb9ea 5352 factor = 1;
a2fbb9ea 5353
a2fbb9ea
ET		 5354 /* Disable inputs of parser neighbor blocks */
5355 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
5356 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
5357 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
3196a88a 5358 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
a2fbb9ea
ET		 5359
5360 /* Write 0 to parser credits for CFC search request */
5361 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
5362
5363 /* send Ethernet packet */
5364 bnx2x_lb_pckt(bp);
5365
5366 /* TODO do i reset NIG statistic? */
5367 /* Wait until NIG register shows 1 packet of size 0x10 */
5368 count = 1000 * factor;
5369 while (count) {
34f80b04 5370
a2fbb9ea
ET		 5371 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
5372 val = *bnx2x_sp(bp, wb_data[0]);
a2fbb9ea
ET		 5373 if (val == 0x10)
5374 break;
5375
5376 msleep(10);
5377 count--;
5378 }
5379 if (val != 0x10) {
5380 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
5381 return -1;
5382 }
5383
5384 /* Wait until PRS register shows 1 packet */
5385 count = 1000 * factor;
5386 while (count) {
5387 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
a2fbb9ea
ET		 5388 if (val == 1)
5389 break;
5390
5391 msleep(10);
5392 count--;
5393 }
5394 if (val != 0x1) {
5395 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
5396 return -2;
5397 }
5398
5399 /* Reset and init BRB, PRS */
34f80b04 5400 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
a2fbb9ea 5401 msleep(50);
34f80b04 5402 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
a2fbb9ea 5403 msleep(50);
619c5cb6
VZ		 5404 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
5405 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
a2fbb9ea
ET		 5406
5407 DP(NETIF_MSG_HW, "part2\n");
5408
5409 /* Disable inputs of parser neighbor blocks */
5410 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
5411 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
5412 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
3196a88a 5413 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
a2fbb9ea
ET		 5414
5415 /* Write 0 to parser credits for CFC search request */
5416 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
5417
5418 /* send 10 Ethernet packets */
5419 for (i = 0; i < 10; i++)
5420 bnx2x_lb_pckt(bp);
5421
5422 /* Wait until NIG register shows 10 + 1
5423 packets of size 11*0x10 = 0xb0 */
5424 count = 1000 * factor;
5425 while (count) {
34f80b04 5426
a2fbb9ea
ET		 5427 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
5428 val = *bnx2x_sp(bp, wb_data[0]);
a2fbb9ea
ET		 5429 if (val == 0xb0)
5430 break;
5431
5432 msleep(10);
5433 count--;
5434 }
5435 if (val != 0xb0) {
5436 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
5437 return -3;
5438 }
5439
5440 /* Wait until PRS register shows 2 packets */
5441 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
5442 if (val != 2)
5443 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
5444
5445 /* Write 1 to parser credits for CFC search request */
5446 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
5447
5448 /* Wait until PRS register shows 3 packets */
5449 msleep(10 * factor);
5450 /* Wait until NIG register shows 1 packet of size 0x10 */
5451 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
5452 if (val != 3)
5453 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
5454
5455 /* clear NIG EOP FIFO */
5456 for (i = 0; i < 11; i++)
5457 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);
5458 val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);
5459 if (val != 1) {
5460 BNX2X_ERR("clear of NIG failed\n");
5461 return -4;
5462 }
5463
5464 /* Reset and init BRB, PRS, NIG */
5465 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
5466 msleep(50);
5467 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
5468 msleep(50);
619c5cb6
VZ		 5469 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
5470 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
37b091ba 5471#ifndef BCM_CNIC
a2fbb9ea
ET		 5472 /* set NIC mode */
5473 REG_WR(bp, PRS_REG_NIC_MODE, 1);
5474#endif
5475
5476 /* Enable inputs of parser neighbor blocks */
5477 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
5478 REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
5479 REG_WR(bp, CFC_REG_DEBUG0, 0x0);
3196a88a 5480 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1);
a2fbb9ea
ET		 5481
5482 DP(NETIF_MSG_HW, "done\n");
5483
5484 return 0; /* OK */
5485}
5486
4a33bc03 5487static void bnx2x_enable_blocks_attention(struct bnx2x *bp)
a2fbb9ea
ET		 5488{
5489 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
619c5cb6 5490 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 5491 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40);
5492 else
5493 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
a2fbb9ea
ET		 5494 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
5495 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
f2e0899f
DK		 5496 /*
5497 * mask read length error interrupts in brb for parser
5498 * (parsing unit and 'checksum and crc' unit)
5499 * these errors are legal (PU reads fixed length and CAC can cause
5500 * read length error on truncated packets)
5501 */
5502 REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00);
a2fbb9ea
ET		 5503 REG_WR(bp, QM_REG_QM_INT_MASK, 0);
5504 REG_WR(bp, TM_REG_TM_INT_MASK, 0);
5505 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
5506 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0);
5507 REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
34f80b04
EG		 5508/* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
5509/* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
a2fbb9ea
ET		 5510 REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0);
5511 REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0);
5512 REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
34f80b04
EG		 5513/* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
5514/* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
a2fbb9ea
ET		 5515 REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
5516 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0);
5517 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0);
5518 REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
34f80b04
EG		 5519/* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
5520/* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
f85582f8 5521
34f80b04
EG		 5522 if (CHIP_REV_IS_FPGA(bp))
5523 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x580000);
619c5cb6 5524 else if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 5525 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0,
5526 (PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF
5527 | PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT
5528 | PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN
5529 | PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED
5530 | PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED));
34f80b04
EG		 5531 else
5532 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x480000);
a2fbb9ea
ET		 5533 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
5534 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
5535 REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
34f80b04 5536/* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
619c5cb6
VZ		 5537
5538 if (!CHIP_IS_E1x(bp))
5539 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
5540 REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
5541
a2fbb9ea
ET		 5542 REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
5543 REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
34f80b04 5544/* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
4a33bc03 5545 REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */
a2fbb9ea
ET		 5546}
5547
81f75bbf
EG		 5548static void bnx2x_reset_common(struct bnx2x *bp)
5549{
619c5cb6
VZ		 5550 u32 val = 0x1400;
5551
81f75bbf
EG		 5552 /* reset_common */
5553 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
5554 0xd3ffff7f);
619c5cb6
VZ		 5555
5556 if (CHIP_IS_E3(bp)) {
5557 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
5558 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
5559 }
5560
5561 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val);
5562}
5563
5564static void bnx2x_setup_dmae(struct bnx2x *bp)
5565{
5566 bp->dmae_ready = 0;
5567 spin_lock_init(&bp->dmae_lock);
81f75bbf
EG		 5568}
5569
573f2035
EG		 5570static void bnx2x_init_pxp(struct bnx2x *bp)
5571{
5572 u16 devctl;
5573 int r_order, w_order;
5574
5575 pci_read_config_word(bp->pdev,
77c98e6a 5576 bp->pdev->pcie_cap + PCI_EXP_DEVCTL, &devctl);
573f2035
EG		 5577 DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
5578 w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
5579 if (bp->mrrs == -1)
5580 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12);
5581 else {
5582 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs);
5583 r_order = bp->mrrs;
5584 }
5585
5586 bnx2x_init_pxp_arb(bp, r_order, w_order);
5587}
fd4ef40d
EG		 5588
5589static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp)
5590{
2145a920 5591 int is_required;
fd4ef40d 5592 u32 val;
2145a920 5593 int port;
fd4ef40d 5594
2145a920
VZ		 5595 if (BP_NOMCP(bp))
5596 return;
5597
5598 is_required = 0;
fd4ef40d
EG		 5599 val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
5600 SHARED_HW_CFG_FAN_FAILURE_MASK;
5601
5602 if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED)
5603 is_required = 1;
5604
5605 /*
5606 * The fan failure mechanism is usually related to the PHY type since
5607 * the power consumption of the board is affected by the PHY. Currently,
5608 * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
5609 */
5610 else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE)
5611 for (port = PORT_0; port < PORT_MAX; port++) {
fd4ef40d 5612 is_required |=
d90d96ba
YR		 5613 bnx2x_fan_failure_det_req(
5614 bp,
5615 bp->common.shmem_base,
a22f0788 5616 bp->common.shmem2_base,
d90d96ba 5617 port);
fd4ef40d
EG		 5618 }
5619
5620 DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required);
5621
5622 if (is_required == 0)
5623 return;
5624
5625 /* Fan failure is indicated by SPIO 5 */
5626 bnx2x_set_spio(bp, MISC_REGISTERS_SPIO_5,
5627 MISC_REGISTERS_SPIO_INPUT_HI_Z);
5628
5629 /* set to active low mode */
5630 val = REG_RD(bp, MISC_REG_SPIO_INT);
5631 val |= ((1 << MISC_REGISTERS_SPIO_5) <<
cdaa7cb8 5632 MISC_REGISTERS_SPIO_INT_OLD_SET_POS);
fd4ef40d
EG		 5633 REG_WR(bp, MISC_REG_SPIO_INT, val);
5634
5635 /* enable interrupt to signal the IGU */
5636 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
5637 val |= (1 << MISC_REGISTERS_SPIO_5);
5638 REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
5639}
5640
f2e0899f
DK		 5641static void bnx2x_pretend_func(struct bnx2x *bp, u8 pretend_func_num)
5642{
5643 u32 offset = 0;
5644
5645 if (CHIP_IS_E1(bp))
5646 return;
5647 if (CHIP_IS_E1H(bp) && (pretend_func_num >= E1H_FUNC_MAX))
5648 return;
5649
5650 switch (BP_ABS_FUNC(bp)) {
5651 case 0:
5652 offset = PXP2_REG_PGL_PRETEND_FUNC_F0;
5653 break;
5654 case 1:
5655 offset = PXP2_REG_PGL_PRETEND_FUNC_F1;
5656 break;
5657 case 2:
5658 offset = PXP2_REG_PGL_PRETEND_FUNC_F2;
5659 break;
5660 case 3:
5661 offset = PXP2_REG_PGL_PRETEND_FUNC_F3;
5662 break;
5663 case 4:
5664 offset = PXP2_REG_PGL_PRETEND_FUNC_F4;
5665 break;
5666 case 5:
5667 offset = PXP2_REG_PGL_PRETEND_FUNC_F5;
5668 break;
5669 case 6:
5670 offset = PXP2_REG_PGL_PRETEND_FUNC_F6;
5671 break;
5672 case 7:
5673 offset = PXP2_REG_PGL_PRETEND_FUNC_F7;
5674 break;
5675 default:
5676 return;
5677 }
5678
5679 REG_WR(bp, offset, pretend_func_num);
5680 REG_RD(bp, offset);
5681 DP(NETIF_MSG_HW, "Pretending to func %d\n", pretend_func_num);
5682}
5683
c9ee9206 5684void bnx2x_pf_disable(struct bnx2x *bp)
f2e0899f
DK		 5685{
5686 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
5687 val &= ~IGU_PF_CONF_FUNC_EN;
5688
5689 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
5690 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
5691 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0);
5692}
5693
619c5cb6
VZ		 5694static inline void bnx2x__common_init_phy(struct bnx2x *bp)
5695{
5696 u32 shmem_base[2], shmem2_base[2];
5697 shmem_base[0] = bp->common.shmem_base;
5698 shmem2_base[0] = bp->common.shmem2_base;
5699 if (!CHIP_IS_E1x(bp)) {
5700 shmem_base[1] =
5701 SHMEM2_RD(bp, other_shmem_base_addr);
5702 shmem2_base[1] =
5703 SHMEM2_RD(bp, other_shmem2_base_addr);
5704 }
5705 bnx2x_acquire_phy_lock(bp);
5706 bnx2x_common_init_phy(bp, shmem_base, shmem2_base,
5707 bp->common.chip_id);
5708 bnx2x_release_phy_lock(bp);
5709}
5710
5711/**
5712 * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
5713 *
5714 * @bp: driver handle
5715 */
5716static int bnx2x_init_hw_common(struct bnx2x *bp)
a2fbb9ea 5717{
619c5cb6 5718 u32 val;
a2fbb9ea 5719
f2e0899f 5720 DP(BNX2X_MSG_MCP, "starting common init func %d\n", BP_ABS_FUNC(bp));
a2fbb9ea 5721
81f75bbf 5722 bnx2x_reset_common(bp);
34f80b04 5723 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
a2fbb9ea 5724
619c5cb6
VZ		 5725 val = 0xfffc;
5726 if (CHIP_IS_E3(bp)) {
5727 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
5728 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
5729 }
5730 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val);
5731
5732 bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON);
a2fbb9ea 5733
619c5cb6
VZ		 5734 if (!CHIP_IS_E1x(bp)) {
5735 u8 abs_func_id;
f2e0899f
DK		 5736
5737 /**
5738 * 4-port mode or 2-port mode we need to turn of master-enable
5739 * for everyone, after that, turn it back on for self.
5740 * so, we disregard multi-function or not, and always disable
5741 * for all functions on the given path, this means 0,2,4,6 for
5742 * path 0 and 1,3,5,7 for path 1
5743 */
619c5cb6
VZ		 5744 for (abs_func_id = BP_PATH(bp);
5745 abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) {
5746 if (abs_func_id == BP_ABS_FUNC(bp)) {
f2e0899f
DK		 5747 REG_WR(bp,
5748 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
5749 1);
5750 continue;
5751 }
5752
619c5cb6 5753 bnx2x_pretend_func(bp, abs_func_id);
f2e0899f
DK		 5754 /* clear pf enable */
5755 bnx2x_pf_disable(bp);
5756 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
5757 }
5758 }
a2fbb9ea 5759
619c5cb6 5760 bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON);
34f80b04
EG		 5761 if (CHIP_IS_E1(bp)) {
5762 /* enable HW interrupt from PXP on USDM overflow
5763 bit 16 on INT_MASK_0 */
5764 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
5765 }
a2fbb9ea 5766
619c5cb6 5767 bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON);
34f80b04 5768 bnx2x_init_pxp(bp);
a2fbb9ea
ET		 5769
5770#ifdef __BIG_ENDIAN
34f80b04
EG		 5771 REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1);
5772 REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1);
5773 REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
5774 REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
5775 REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
8badd27a
EG		 5776 /* make sure this value is 0 */
5777 REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0);
34f80b04
EG		 5778
5779/* REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */
5780 REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1);
5781 REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1);
5782 REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1);
5783 REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
a2fbb9ea
ET		 5784#endif
5785
523224a3
DK		 5786 bnx2x_ilt_init_page_size(bp, INITOP_SET);
5787
34f80b04
EG		 5788 if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
5789 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
a2fbb9ea 5790
34f80b04
EG		 5791 /* let the HW do it's magic ... */
5792 msleep(100);
5793 /* finish PXP init */
5794 val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
5795 if (val != 1) {
5796 BNX2X_ERR("PXP2 CFG failed\n");
5797 return -EBUSY;
5798 }
5799 val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
5800 if (val != 1) {
5801 BNX2X_ERR("PXP2 RD_INIT failed\n");
5802 return -EBUSY;
5803 }
a2fbb9ea 5804
f2e0899f
DK		 5805 /* Timers bug workaround E2 only. We need to set the entire ILT to
5806 * have entries with value "0" and valid bit on.
5807 * This needs to be done by the first PF that is loaded in a path
5808 * (i.e. common phase)
5809 */
619c5cb6
VZ		 5810 if (!CHIP_IS_E1x(bp)) {
5811/* In E2 there is a bug in the timers block that can cause function 6 / 7
5812 * (i.e. vnic3) to start even if it is marked as "scan-off".
5813 * This occurs when a different function (func2,3) is being marked
5814 * as "scan-off". Real-life scenario for example: if a driver is being
5815 * load-unloaded while func6,7 are down. This will cause the timer to access
5816 * the ilt, translate to a logical address and send a request to read/write.
5817 * Since the ilt for the function that is down is not valid, this will cause
5818 * a translation error which is unrecoverable.
5819 * The Workaround is intended to make sure that when this happens nothing fatal
5820 * will occur. The workaround:
5821 * 1. First PF driver which loads on a path will:
5822 * a. After taking the chip out of reset, by using pretend,
5823 * it will write "0" to the following registers of
5824 * the other vnics.
5825 * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
5826 * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
5827 * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
5828 * And for itself it will write '1' to
5829 * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
5830 * dmae-operations (writing to pram for example.)
5831 * note: can be done for only function 6,7 but cleaner this
5832 * way.
5833 * b. Write zero+valid to the entire ILT.
5834 * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of
5835 * VNIC3 (of that port). The range allocated will be the
5836 * entire ILT. This is needed to prevent ILT range error.
5837 * 2. Any PF driver load flow:
5838 * a. ILT update with the physical addresses of the allocated
5839 * logical pages.
5840 * b. Wait 20msec. - note that this timeout is needed to make
5841 * sure there are no requests in one of the PXP internal
5842 * queues with "old" ILT addresses.
5843 * c. PF enable in the PGLC.
5844 * d. Clear the was_error of the PF in the PGLC. (could have
5845 * occured while driver was down)
5846 * e. PF enable in the CFC (WEAK + STRONG)
5847 * f. Timers scan enable
5848 * 3. PF driver unload flow:
5849 * a. Clear the Timers scan_en.
5850 * b. Polling for scan_on=0 for that PF.
5851 * c. Clear the PF enable bit in the PXP.
5852 * d. Clear the PF enable in the CFC (WEAK + STRONG)
5853 * e. Write zero+valid to all ILT entries (The valid bit must
5854 * stay set)
5855 * f. If this is VNIC 3 of a port then also init
5856 * first_timers_ilt_entry to zero and last_timers_ilt_entry
5857 * to the last enrty in the ILT.
5858 *
5859 * Notes:
5860 * Currently the PF error in the PGLC is non recoverable.
5861 * In the future the there will be a recovery routine for this error.
5862 * Currently attention is masked.
5863 * Having an MCP lock on the load/unload process does not guarantee that
5864 * there is no Timer disable during Func6/7 enable. This is because the
5865 * Timers scan is currently being cleared by the MCP on FLR.
5866 * Step 2.d can be done only for PF6/7 and the driver can also check if
5867 * there is error before clearing it. But the flow above is simpler and
5868 * more general.
5869 * All ILT entries are written by zero+valid and not just PF6/7
5870 * ILT entries since in the future the ILT entries allocation for
5871 * PF-s might be dynamic.
5872 */
f2e0899f
DK		 5873 struct ilt_client_info ilt_cli;
5874 struct bnx2x_ilt ilt;
5875 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
5876 memset(&ilt, 0, sizeof(struct bnx2x_ilt));
5877
b595076a 5878 /* initialize dummy TM client */
f2e0899f
DK		 5879 ilt_cli.start = 0;
5880 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
5881 ilt_cli.client_num = ILT_CLIENT_TM;
5882
5883 /* Step 1: set zeroes to all ilt page entries with valid bit on
5884 * Step 2: set the timers first/last ilt entry to point
5885 * to the entire range to prevent ILT range error for 3rd/4th
619c5cb6 5886 * vnic (this code assumes existance of the vnic)
f2e0899f
DK		 5887 *
5888 * both steps performed by call to bnx2x_ilt_client_init_op()
5889 * with dummy TM client
5890 *
5891 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
5892 * and his brother are split registers
5893 */
5894 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6));
5895 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR);
5896 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
5897
5898 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
5899 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
5900 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
5901 }
5902
5903
34f80b04
EG		 5904 REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
5905 REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
a2fbb9ea 5906
619c5cb6 5907 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 5908 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 :
5909 (CHIP_REV_IS_FPGA(bp) ? 400 : 0);
619c5cb6 5910 bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON);
f2e0899f 5911
619c5cb6 5912 bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON);
f2e0899f
DK		 5913
5914 /* let the HW do it's magic ... */
5915 do {
5916 msleep(200);
5917 val = REG_RD(bp, ATC_REG_ATC_INIT_DONE);
5918 } while (factor-- && (val != 1));
5919
5920 if (val != 1) {
5921 BNX2X_ERR("ATC_INIT failed\n");
5922 return -EBUSY;
5923 }
5924 }
5925
619c5cb6 5926 bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON);
a2fbb9ea 5927
34f80b04
EG		 5928 /* clean the DMAE memory */
5929 bp->dmae_ready = 1;
619c5cb6
VZ		 5930 bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1);
5931
5932 bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON);
5933
5934 bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON);
5935
5936 bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON);
a2fbb9ea 5937
619c5cb6 5938 bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON);
a2fbb9ea 5939
34f80b04
EG		 5940 bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
5941 bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
5942 bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
5943 bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
5944
619c5cb6 5945 bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON);
37b091ba 5946
f85582f8 5947
523224a3
DK		 5948 /* QM queues pointers table */
5949 bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET);
5950
34f80b04
EG		 5951 /* soft reset pulse */
5952 REG_WR(bp, QM_REG_SOFT_RESET, 1);
5953 REG_WR(bp, QM_REG_SOFT_RESET, 0);
a2fbb9ea 5954
37b091ba 5955#ifdef BCM_CNIC
619c5cb6 5956 bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON);
a2fbb9ea 5957#endif
a2fbb9ea 5958
619c5cb6 5959 bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON);
523224a3 5960 REG_WR(bp, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT);
619c5cb6 5961 if (!CHIP_REV_IS_SLOW(bp))
34f80b04
EG		 5962 /* enable hw interrupt from doorbell Q */
5963 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
a2fbb9ea 5964
619c5cb6 5965 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
f2e0899f 5966
619c5cb6 5967 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
26c8fa4d 5968 REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
619c5cb6 5969
f2e0899f 5970 if (!CHIP_IS_E1(bp))
619c5cb6 5971 REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan);
f85582f8 5972
619c5cb6
VZ		 5973 if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp))
5974 /* Bit-map indicating which L2 hdrs may appear
5975 * after the basic Ethernet header
5976 */
5977 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC,
5978 bp->path_has_ovlan ? 7 : 6);
a2fbb9ea 5979
619c5cb6
VZ		 5980 bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON);
5981 bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON);
5982 bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON);
5983 bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON);
a2fbb9ea 5984
619c5cb6
VZ		 5985 if (!CHIP_IS_E1x(bp)) {
5986 /* reset VFC memories */
5987 REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
5988 VFC_MEMORIES_RST_REG_CAM_RST |
5989 VFC_MEMORIES_RST_REG_RAM_RST);
5990 REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
5991 VFC_MEMORIES_RST_REG_CAM_RST |
5992 VFC_MEMORIES_RST_REG_RAM_RST);
a2fbb9ea 5993
619c5cb6
VZ		 5994 msleep(20);
5995 }
a2fbb9ea 5996
619c5cb6
VZ		 5997 bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON);
5998 bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON);
5999 bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON);
6000 bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON);
f2e0899f 6001
34f80b04
EG		 6002 /* sync semi rtc */
6003 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6004 0x80000000);
6005 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
6006 0x80000000);
a2fbb9ea 6007
619c5cb6
VZ		 6008 bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON);
6009 bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON);
6010 bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON);
a2fbb9ea 6011
619c5cb6
VZ		 6012 if (!CHIP_IS_E1x(bp))
6013 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC,
6014 bp->path_has_ovlan ? 7 : 6);
f2e0899f 6015
34f80b04 6016 REG_WR(bp, SRC_REG_SOFT_RST, 1);
f85582f8 6017
619c5cb6
VZ		 6018 bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON);
6019
37b091ba
MC		 6020#ifdef BCM_CNIC
6021 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672);
6022 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
6023 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b);
6024 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a);
6025 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116);
6026 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
6027 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf);
6028 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
6029 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f);
6030 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7);
6031#endif
34f80b04 6032 REG_WR(bp, SRC_REG_SOFT_RST, 0);
a2fbb9ea 6033
34f80b04
EG		 6034 if (sizeof(union cdu_context) != 1024)
6035 /* we currently assume that a context is 1024 bytes */
cdaa7cb8
VZ		 6036 dev_alert(&bp->pdev->dev, "please adjust the size "
6037 "of cdu_context(%ld)\n",
7995c64e 6038 (long)sizeof(union cdu_context));
a2fbb9ea 6039
619c5cb6 6040 bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON);
34f80b04
EG		 6041 val = (4 << 24) + (0 << 12) + 1024;
6042 REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
a2fbb9ea 6043
619c5cb6 6044 bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON);
34f80b04 6045 REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
8d9c5f34
EG		 6046 /* enable context validation interrupt from CFC */
6047 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
6048
6049 /* set the thresholds to prevent CFC/CDU race */
6050 REG_WR(bp, CFC_REG_DEBUG0, 0x20020000);
a2fbb9ea 6051
619c5cb6 6052 bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON);
f2e0899f 6053
619c5cb6 6054 if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp))
f2e0899f
DK		 6055 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36);
6056
619c5cb6
VZ		 6057 bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON);
6058 bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON);
a2fbb9ea 6059
34f80b04
EG		 6060 /* Reset PCIE errors for debug */
6061 REG_WR(bp, 0x2814, 0xffffffff);
6062 REG_WR(bp, 0x3820, 0xffffffff);
a2fbb9ea 6063
619c5cb6 6064 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 6065 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
6066 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
6067 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
6068 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
6069 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
6070 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
6071 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
6072 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
6073 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
6074 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
6075 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
6076 }
6077
619c5cb6 6078 bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON);
f2e0899f 6079 if (!CHIP_IS_E1(bp)) {
619c5cb6
VZ		 6080 /* in E3 this done in per-port section */
6081 if (!CHIP_IS_E3(bp))
6082 REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp));
f2e0899f 6083 }
619c5cb6
VZ		 6084 if (CHIP_IS_E1H(bp))
6085 /* not applicable for E2 (and above ...) */
6086 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp));
34f80b04
EG		 6087
6088 if (CHIP_REV_IS_SLOW(bp))
6089 msleep(200);
6090
6091 /* finish CFC init */
6092 val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10);
6093 if (val != 1) {
6094 BNX2X_ERR("CFC LL_INIT failed\n");
6095 return -EBUSY;
6096 }
6097 val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10);
6098 if (val != 1) {
6099 BNX2X_ERR("CFC AC_INIT failed\n");
6100 return -EBUSY;
6101 }
6102 val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
6103 if (val != 1) {
6104 BNX2X_ERR("CFC CAM_INIT failed\n");
6105 return -EBUSY;
6106 }
6107 REG_WR(bp, CFC_REG_DEBUG0, 0);
f1410647 6108
f2e0899f
DK		 6109 if (CHIP_IS_E1(bp)) {
6110 /* read NIG statistic
6111 to see if this is our first up since powerup */
6112 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6113 val = *bnx2x_sp(bp, wb_data[0]);
34f80b04 6114
f2e0899f
DK		 6115 /* do internal memory self test */
6116 if ((val == 0) && bnx2x_int_mem_test(bp)) {
6117 BNX2X_ERR("internal mem self test failed\n");
6118 return -EBUSY;
6119 }
34f80b04
EG		 6120 }
6121
fd4ef40d
EG		 6122 bnx2x_setup_fan_failure_detection(bp);
6123
34f80b04
EG		 6124 /* clear PXP2 attentions */
6125 REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
a2fbb9ea 6126
4a33bc03 6127 bnx2x_enable_blocks_attention(bp);
c9ee9206 6128 bnx2x_enable_blocks_parity(bp);
a2fbb9ea 6129
6bbca910 6130 if (!BP_NOMCP(bp)) {
619c5cb6
VZ		 6131 if (CHIP_IS_E1x(bp))
6132 bnx2x__common_init_phy(bp);
6bbca910
YR		 6133 } else
6134 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
6135
34f80b04
EG		 6136 return 0;
6137}
a2fbb9ea 6138
619c5cb6
VZ		 6139/**
6140 * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
6141 *
6142 * @bp: driver handle
6143 */
6144static int bnx2x_init_hw_common_chip(struct bnx2x *bp)
6145{
6146 int rc = bnx2x_init_hw_common(bp);
6147
6148 if (rc)
6149 return rc;
6150
6151 /* In E2 2-PORT mode, same ext phy is used for the two paths */
6152 if (!BP_NOMCP(bp))
6153 bnx2x__common_init_phy(bp);
6154
6155 return 0;
6156}
6157
523224a3 6158static int bnx2x_init_hw_port(struct bnx2x *bp)
34f80b04
EG		 6159{
6160 int port = BP_PORT(bp);
619c5cb6 6161 int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
1c06328c 6162 u32 low, high;
34f80b04 6163 u32 val;
a2fbb9ea 6164
619c5cb6
VZ		 6165 bnx2x__link_reset(bp);
6166
cdaa7cb8 6167 DP(BNX2X_MSG_MCP, "starting port init port %d\n", port);
34f80b04
EG		 6168
6169 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
a2fbb9ea 6170
619c5cb6
VZ		 6171 bnx2x_init_block(bp, BLOCK_MISC, init_phase);
6172 bnx2x_init_block(bp, BLOCK_PXP, init_phase);
6173 bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
ca00392c 6174
f2e0899f
DK		 6175 /* Timers bug workaround: disables the pf_master bit in pglue at
6176 * common phase, we need to enable it here before any dmae access are
6177 * attempted. Therefore we manually added the enable-master to the
6178 * port phase (it also happens in the function phase)
6179 */
619c5cb6 6180 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 6181 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
6182
619c5cb6
VZ		 6183 bnx2x_init_block(bp, BLOCK_ATC, init_phase);
6184 bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
6185 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
6186 bnx2x_init_block(bp, BLOCK_QM, init_phase);
6187
6188 bnx2x_init_block(bp, BLOCK_TCM, init_phase);
6189 bnx2x_init_block(bp, BLOCK_UCM, init_phase);
6190 bnx2x_init_block(bp, BLOCK_CCM, init_phase);
6191 bnx2x_init_block(bp, BLOCK_XCM, init_phase);
a2fbb9ea 6192
523224a3
DK		 6193 /* QM cid (connection) count */
6194 bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET);
a2fbb9ea 6195
523224a3 6196#ifdef BCM_CNIC
619c5cb6 6197 bnx2x_init_block(bp, BLOCK_TM, init_phase);
37b091ba
MC		 6198 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20);
6199 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31);
a2fbb9ea 6200#endif
cdaa7cb8 6201
619c5cb6 6202 bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
f2e0899f
DK		 6203
6204 if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) {
619c5cb6
VZ		 6205 bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
6206
6207 if (IS_MF(bp))
6208 low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246);
6209 else if (bp->dev->mtu > 4096) {
6210 if (bp->flags & ONE_PORT_FLAG)
6211 low = 160;
6212 else {
6213 val = bp->dev->mtu;
6214 /* (24*1024 + val*4)/256 */
6215 low = 96 + (val/64) +
6216 ((val % 64) ? 1 : 0);
6217 }
6218 } else
6219 low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160);
6220 high = low + 56; /* 14*1024/256 */
f2e0899f
DK		 6221 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
6222 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
1c06328c 6223 }
1c06328c 6224
619c5cb6
VZ		 6225 if (CHIP_MODE_IS_4_PORT(bp))
6226 REG_WR(bp, (BP_PORT(bp) ?
6227 BRB1_REG_MAC_GUARANTIED_1 :
6228 BRB1_REG_MAC_GUARANTIED_0), 40);
1c06328c 6229
ca00392c 6230
619c5cb6
VZ		 6231 bnx2x_init_block(bp, BLOCK_PRS, init_phase);
6232 if (CHIP_IS_E3B0(bp))
6233 /* Ovlan exists only if we are in multi-function +
6234 * switch-dependent mode, in switch-independent there
6235 * is no ovlan headers
6236 */
6237 REG_WR(bp, BP_PORT(bp) ?
6238 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
6239 PRS_REG_HDRS_AFTER_BASIC_PORT_0,
6240 (bp->path_has_ovlan ? 7 : 6));
356e2385 6241
619c5cb6
VZ		 6242 bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
6243 bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
6244 bnx2x_init_block(bp, BLOCK_USDM, init_phase);
6245 bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
356e2385 6246
619c5cb6
VZ		 6247 bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
6248 bnx2x_init_block(bp, BLOCK_USEM, init_phase);
6249 bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
6250 bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
34f80b04 6251
619c5cb6
VZ		 6252 bnx2x_init_block(bp, BLOCK_UPB, init_phase);
6253 bnx2x_init_block(bp, BLOCK_XPB, init_phase);
a2fbb9ea 6254
619c5cb6
VZ		 6255 bnx2x_init_block(bp, BLOCK_PBF, init_phase);
6256
6257 if (CHIP_IS_E1x(bp)) {
f2e0899f
DK		 6258 /* configure PBF to work without PAUSE mtu 9000 */
6259 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
a2fbb9ea 6260
f2e0899f
DK		 6261 /* update threshold */
6262 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
6263 /* update init credit */
6264 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
a2fbb9ea 6265
f2e0899f
DK		 6266 /* probe changes */
6267 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
6268 udelay(50);
6269 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
6270 }
a2fbb9ea 6271
37b091ba 6272#ifdef BCM_CNIC
619c5cb6 6273 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
a2fbb9ea 6274#endif
619c5cb6
VZ		 6275 bnx2x_init_block(bp, BLOCK_CDU, init_phase);
6276 bnx2x_init_block(bp, BLOCK_CFC, init_phase);
34f80b04
EG		 6277
6278 if (CHIP_IS_E1(bp)) {
6279 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
6280 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
6281 }
619c5cb6 6282 bnx2x_init_block(bp, BLOCK_HC, init_phase);
34f80b04 6283
619c5cb6 6284 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
f2e0899f 6285
619c5cb6 6286 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
34f80b04
EG		 6287 /* init aeu_mask_attn_func_0/1:
6288 * - SF mode: bits 3-7 are masked. only bits 0-2 are in use
6289 * - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
6290 * bits 4-7 are used for "per vn group attention" */
e4901dde
VZ		 6291 val = IS_MF(bp) ? 0xF7 : 0x7;
6292 /* Enable DCBX attention for all but E1 */
6293 val |= CHIP_IS_E1(bp) ? 0 : 0x10;
6294 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
34f80b04 6295
619c5cb6
VZ		 6296 bnx2x_init_block(bp, BLOCK_NIG, init_phase);
6297
6298 if (!CHIP_IS_E1x(bp)) {
6299 /* Bit-map indicating which L2 hdrs may appear after the
6300 * basic Ethernet header
6301 */
6302 REG_WR(bp, BP_PORT(bp) ?
6303 NIG_REG_P1_HDRS_AFTER_BASIC :
6304 NIG_REG_P0_HDRS_AFTER_BASIC,
6305 IS_MF_SD(bp) ? 7 : 6);
6306
6307 if (CHIP_IS_E3(bp))
6308 REG_WR(bp, BP_PORT(bp) ?
6309 NIG_REG_LLH1_MF_MODE :
6310 NIG_REG_LLH_MF_MODE, IS_MF(bp));
6311 }
6312 if (!CHIP_IS_E3(bp))
6313 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
34f80b04 6314
f2e0899f 6315 if (!CHIP_IS_E1(bp)) {
fb3bff17 6316 /* 0x2 disable mf_ov, 0x1 enable */
34f80b04 6317 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
0793f83f 6318 (IS_MF_SD(bp) ? 0x1 : 0x2));
34f80b04 6319
619c5cb6 6320 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 6321 val = 0;
6322 switch (bp->mf_mode) {
6323 case MULTI_FUNCTION_SD:
6324 val = 1;
6325 break;
6326 case MULTI_FUNCTION_SI:
6327 val = 2;
6328 break;
6329 }
6330
6331 REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE :
6332 NIG_REG_LLH0_CLS_TYPE), val);
6333 }
1c06328c
EG		 6334 {
6335 REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
6336 REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
6337 REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1);
6338 }
34f80b04
EG		 6339 }
6340
619c5cb6
VZ		 6341
6342 /* If SPIO5 is set to generate interrupts, enable it for this port */
6343 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
6344 if (val & (1 << MISC_REGISTERS_SPIO_5)) {
4d295db0
EG		 6345 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
6346 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
6347 val = REG_RD(bp, reg_addr);
f1410647 6348 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
4d295db0 6349 REG_WR(bp, reg_addr, val);
f1410647 6350 }
a2fbb9ea 6351
34f80b04
EG		 6352 return 0;
6353}
6354
34f80b04
EG		 6355static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr)
6356{
6357 int reg;
6358
f2e0899f 6359 if (CHIP_IS_E1(bp))
34f80b04 6360 reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
f2e0899f
DK		 6361 else
6362 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
34f80b04
EG		 6363
6364 bnx2x_wb_wr(bp, reg, ONCHIP_ADDR1(addr), ONCHIP_ADDR2(addr));
6365}
6366
f2e0899f
DK		 6367static inline void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id)
6368{
619c5cb6 6369 bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/);
f2e0899f
DK		 6370}
6371
6372static inline void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func)
6373{
6374 u32 i, base = FUNC_ILT_BASE(func);
6375 for (i = base; i < base + ILT_PER_FUNC; i++)
6376 bnx2x_ilt_wr(bp, i, 0);
6377}
6378
523224a3 6379static int bnx2x_init_hw_func(struct bnx2x *bp)
34f80b04
EG		 6380{
6381 int port = BP_PORT(bp);
6382 int func = BP_FUNC(bp);
619c5cb6 6383 int init_phase = PHASE_PF0 + func;
523224a3
DK		 6384 struct bnx2x_ilt *ilt = BP_ILT(bp);
6385 u16 cdu_ilt_start;
8badd27a 6386 u32 addr, val;
f4a66897
VZ		 6387 u32 main_mem_base, main_mem_size, main_mem_prty_clr;
6388 int i, main_mem_width;
34f80b04 6389
cdaa7cb8 6390 DP(BNX2X_MSG_MCP, "starting func init func %d\n", func);
34f80b04 6391
619c5cb6
VZ		 6392 /* FLR cleanup - hmmm */
6393 if (!CHIP_IS_E1x(bp))
6394 bnx2x_pf_flr_clnup(bp);
6395
8badd27a 6396 /* set MSI reconfigure capability */
f2e0899f
DK		 6397 if (bp->common.int_block == INT_BLOCK_HC) {
6398 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
6399 val = REG_RD(bp, addr);
6400 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
6401 REG_WR(bp, addr, val);
6402 }
8badd27a 6403
619c5cb6
VZ		 6404 bnx2x_init_block(bp, BLOCK_PXP, init_phase);
6405 bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
6406
523224a3
DK		 6407 ilt = BP_ILT(bp);
6408 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
37b091ba 6409
523224a3
DK		 6410 for (i = 0; i < L2_ILT_LINES(bp); i++) {
6411 ilt->lines[cdu_ilt_start + i].page =
6412 bp->context.vcxt + (ILT_PAGE_CIDS * i);
6413 ilt->lines[cdu_ilt_start + i].page_mapping =
6414 bp->context.cxt_mapping + (CDU_ILT_PAGE_SZ * i);
6415 /* cdu ilt pages are allocated manually so there's no need to
6416 set the size */
37b091ba 6417 }
523224a3 6418 bnx2x_ilt_init_op(bp, INITOP_SET);
f85582f8 6419
523224a3
DK		 6420#ifdef BCM_CNIC
6421 bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM);
37b091ba 6422
523224a3
DK		 6423 /* T1 hash bits value determines the T1 number of entries */
6424 REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS);
6425#endif
37b091ba 6426
523224a3
DK		 6427#ifndef BCM_CNIC
6428 /* set NIC mode */
6429 REG_WR(bp, PRS_REG_NIC_MODE, 1);
6430#endif /* BCM_CNIC */
37b091ba 6431
619c5cb6 6432 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 6433 u32 pf_conf = IGU_PF_CONF_FUNC_EN;
6434
6435 /* Turn on a single ISR mode in IGU if driver is going to use
6436 * INT#x or MSI
6437 */
6438 if (!(bp->flags & USING_MSIX_FLAG))
6439 pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
6440 /*
6441 * Timers workaround bug: function init part.
6442 * Need to wait 20msec after initializing ILT,
6443 * needed to make sure there are no requests in
6444 * one of the PXP internal queues with "old" ILT addresses
6445 */
6446 msleep(20);
6447 /*
6448 * Master enable - Due to WB DMAE writes performed before this
6449 * register is re-initialized as part of the regular function
6450 * init
6451 */
6452 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
6453 /* Enable the function in IGU */
6454 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf);
6455 }
6456
523224a3 6457 bp->dmae_ready = 1;
34f80b04 6458
619c5cb6 6459 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
523224a3 6460
619c5cb6 6461 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 6462 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
6463
619c5cb6
VZ		 6464 bnx2x_init_block(bp, BLOCK_ATC, init_phase);
6465 bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
6466 bnx2x_init_block(bp, BLOCK_NIG, init_phase);
6467 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
6468 bnx2x_init_block(bp, BLOCK_MISC, init_phase);
6469 bnx2x_init_block(bp, BLOCK_TCM, init_phase);
6470 bnx2x_init_block(bp, BLOCK_UCM, init_phase);
6471 bnx2x_init_block(bp, BLOCK_CCM, init_phase);
6472 bnx2x_init_block(bp, BLOCK_XCM, init_phase);
6473 bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
6474 bnx2x_init_block(bp, BLOCK_USEM, init_phase);
6475 bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
6476 bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
6477
6478 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 6479 REG_WR(bp, QM_REG_PF_EN, 1);
6480
619c5cb6
VZ		 6481 if (!CHIP_IS_E1x(bp)) {
6482 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
6483 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
6484 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
6485 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
6486 }
6487 bnx2x_init_block(bp, BLOCK_QM, init_phase);
6488
6489 bnx2x_init_block(bp, BLOCK_TM, init_phase);
6490 bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
6491 bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
6492 bnx2x_init_block(bp, BLOCK_PRS, init_phase);
6493 bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
6494 bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
6495 bnx2x_init_block(bp, BLOCK_USDM, init_phase);
6496 bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
6497 bnx2x_init_block(bp, BLOCK_UPB, init_phase);
6498 bnx2x_init_block(bp, BLOCK_XPB, init_phase);
6499 bnx2x_init_block(bp, BLOCK_PBF, init_phase);
6500 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 6501 REG_WR(bp, PBF_REG_DISABLE_PF, 0);
6502
619c5cb6 6503 bnx2x_init_block(bp, BLOCK_CDU, init_phase);
523224a3 6504
619c5cb6 6505 bnx2x_init_block(bp, BLOCK_CFC, init_phase);
34f80b04 6506
619c5cb6 6507 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 6508 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1);
6509
fb3bff17 6510 if (IS_MF(bp)) {
34f80b04 6511 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
fb3bff17 6512 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->mf_ov);
34f80b04
EG		 6513 }
6514
619c5cb6 6515 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
523224a3 6516
34f80b04 6517 /* HC init per function */
f2e0899f
DK		 6518 if (bp->common.int_block == INT_BLOCK_HC) {
6519 if (CHIP_IS_E1H(bp)) {
6520 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
6521
6522 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
6523 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
6524 }
619c5cb6 6525 bnx2x_init_block(bp, BLOCK_HC, init_phase);
f2e0899f
DK		 6526
6527 } else {
6528 int num_segs, sb_idx, prod_offset;
6529
34f80b04
EG		 6530 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
6531
619c5cb6 6532 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 6533 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
6534 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
6535 }
6536
619c5cb6 6537 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
f2e0899f 6538
619c5cb6 6539 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 6540 int dsb_idx = 0;
6541 /**
6542 * Producer memory:
6543 * E2 mode: address 0-135 match to the mapping memory;
6544 * 136 - PF0 default prod; 137 - PF1 default prod;
6545 * 138 - PF2 default prod; 139 - PF3 default prod;
6546 * 140 - PF0 attn prod; 141 - PF1 attn prod;
6547 * 142 - PF2 attn prod; 143 - PF3 attn prod;
6548 * 144-147 reserved.
6549 *
6550 * E1.5 mode - In backward compatible mode;
6551 * for non default SB; each even line in the memory
6552 * holds the U producer and each odd line hold
6553 * the C producer. The first 128 producers are for
6554 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
6555 * producers are for the DSB for each PF.
6556 * Each PF has five segments: (the order inside each
6557 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
6558 * 132-135 C prods; 136-139 X prods; 140-143 T prods;
6559 * 144-147 attn prods;
6560 */
6561 /* non-default-status-blocks */
6562 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
6563 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
6564 for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) {
6565 prod_offset = (bp->igu_base_sb + sb_idx) *
6566 num_segs;
6567
6568 for (i = 0; i < num_segs; i++) {
6569 addr = IGU_REG_PROD_CONS_MEMORY +
6570 (prod_offset + i) * 4;
6571 REG_WR(bp, addr, 0);
6572 }
6573 /* send consumer update with value 0 */
6574 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx,
6575 USTORM_ID, 0, IGU_INT_NOP, 1);
6576 bnx2x_igu_clear_sb(bp,
6577 bp->igu_base_sb + sb_idx);
6578 }
6579
6580 /* default-status-blocks */
6581 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
6582 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
6583
6584 if (CHIP_MODE_IS_4_PORT(bp))
6585 dsb_idx = BP_FUNC(bp);
6586 else
6587 dsb_idx = BP_E1HVN(bp);
6588
6589 prod_offset = (CHIP_INT_MODE_IS_BC(bp) ?
6590 IGU_BC_BASE_DSB_PROD + dsb_idx :
6591 IGU_NORM_BASE_DSB_PROD + dsb_idx);
6592
6593 for (i = 0; i < (num_segs * E1HVN_MAX);
6594 i += E1HVN_MAX) {
6595 addr = IGU_REG_PROD_CONS_MEMORY +
6596 (prod_offset + i)*4;
6597 REG_WR(bp, addr, 0);
6598 }
6599 /* send consumer update with 0 */
6600 if (CHIP_INT_MODE_IS_BC(bp)) {
6601 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6602 USTORM_ID, 0, IGU_INT_NOP, 1);
6603 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6604 CSTORM_ID, 0, IGU_INT_NOP, 1);
6605 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6606 XSTORM_ID, 0, IGU_INT_NOP, 1);
6607 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6608 TSTORM_ID, 0, IGU_INT_NOP, 1);
6609 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6610 ATTENTION_ID, 0, IGU_INT_NOP, 1);
6611 } else {
6612 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6613 USTORM_ID, 0, IGU_INT_NOP, 1);
6614 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6615 ATTENTION_ID, 0, IGU_INT_NOP, 1);
6616 }
6617 bnx2x_igu_clear_sb(bp, bp->igu_dsb_id);
6618
6619 /* !!! these should become driver const once
6620 rf-tool supports split-68 const */
6621 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
6622 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
6623 REG_WR(bp, IGU_REG_SB_MASK_LSB, 0);
6624 REG_WR(bp, IGU_REG_SB_MASK_MSB, 0);
6625 REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0);
6626 REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0);
6627 }
34f80b04 6628 }
34f80b04 6629
c14423fe 6630 /* Reset PCIE errors for debug */
a2fbb9ea
ET		 6631 REG_WR(bp, 0x2114, 0xffffffff);
6632 REG_WR(bp, 0x2120, 0xffffffff);
523224a3 6633
f4a66897
VZ		 6634 if (CHIP_IS_E1x(bp)) {
6635 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/
6636 main_mem_base = HC_REG_MAIN_MEMORY +
6637 BP_PORT(bp) * (main_mem_size * 4);
6638 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
6639 main_mem_width = 8;
6640
6641 val = REG_RD(bp, main_mem_prty_clr);
6642 if (val)
6643 DP(BNX2X_MSG_MCP, "Hmmm... Parity errors in HC "
6644 "block during "
6645 "function init (0x%x)!\n", val);
6646
6647 /* Clear "false" parity errors in MSI-X table */
6648 for (i = main_mem_base;
6649 i < main_mem_base + main_mem_size * 4;
6650 i += main_mem_width) {
6651 bnx2x_read_dmae(bp, i, main_mem_width / 4);
6652 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data),
6653 i, main_mem_width / 4);
6654 }
6655 /* Clear HC parity attention */
6656 REG_RD(bp, main_mem_prty_clr);
6657 }
6658
619c5cb6
VZ		 6659#ifdef BNX2X_STOP_ON_ERROR
6660 /* Enable STORMs SP logging */
6661 REG_WR8(bp, BAR_USTRORM_INTMEM +
6662 USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
6663 REG_WR8(bp, BAR_TSTRORM_INTMEM +
6664 TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
6665 REG_WR8(bp, BAR_CSTRORM_INTMEM +
6666 CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
6667 REG_WR8(bp, BAR_XSTRORM_INTMEM +
6668 XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
6669#endif
6670
b7737c9b 6671 bnx2x_phy_probe(&bp->link_params);
f85582f8 6672
34f80b04
EG		 6673 return 0;
6674}
6675
a2fbb9ea 6676
9f6c9258 6677void bnx2x_free_mem(struct bnx2x *bp)
a2fbb9ea 6678{
a2fbb9ea 6679 /* fastpath */
b3b83c3f 6680 bnx2x_free_fp_mem(bp);
a2fbb9ea
ET		 6681 /* end of fastpath */
6682
6683 BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping,
523224a3 6684 sizeof(struct host_sp_status_block));
a2fbb9ea 6685
619c5cb6
VZ		 6686 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
6687 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
6688
a2fbb9ea 6689 BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping,
34f80b04 6690 sizeof(struct bnx2x_slowpath));
a2fbb9ea 6691
523224a3
DK		 6692 BNX2X_PCI_FREE(bp->context.vcxt, bp->context.cxt_mapping,
6693 bp->context.size);
6694
6695 bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE);
6696
6697 BNX2X_FREE(bp->ilt->lines);
f85582f8 6698
37b091ba 6699#ifdef BCM_CNIC
619c5cb6 6700 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 6701 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping,
6702 sizeof(struct host_hc_status_block_e2));
6703 else
6704 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping,
6705 sizeof(struct host_hc_status_block_e1x));
f85582f8 6706
523224a3 6707 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
a2fbb9ea 6708#endif
f85582f8 6709
7a9b2557 6710 BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE);
a2fbb9ea 6711
523224a3
DK		 6712 BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping,
6713 BCM_PAGE_SIZE * NUM_EQ_PAGES);
619c5cb6
VZ		 6714}
6715
6716static inline int bnx2x_alloc_fw_stats_mem(struct bnx2x *bp)
6717{
6718 int num_groups;
6719
6720 /* number of eth_queues */
6721 u8 num_queue_stats = BNX2X_NUM_ETH_QUEUES(bp);
6722
6723 /* Total number of FW statistics requests =
6724 * 1 for port stats + 1 for PF stats + num_eth_queues */
6725 bp->fw_stats_num = 2 + num_queue_stats;
523224a3 6726
619c5cb6
VZ		 6727
6728 /* Request is built from stats_query_header and an array of
6729 * stats_query_cmd_group each of which contains
6730 * STATS_QUERY_CMD_COUNT rules. The real number or requests is
6731 * configured in the stats_query_header.
6732 */
6733 num_groups = (2 + num_queue_stats) / STATS_QUERY_CMD_COUNT +
6734 (((2 + num_queue_stats) % STATS_QUERY_CMD_COUNT) ? 1 : 0);
6735
6736 bp->fw_stats_req_sz = sizeof(struct stats_query_header) +
6737 num_groups * sizeof(struct stats_query_cmd_group);
6738
6739 /* Data for statistics requests + stats_conter
6740 *
6741 * stats_counter holds per-STORM counters that are incremented
6742 * when STORM has finished with the current request.
6743 */
6744 bp->fw_stats_data_sz = sizeof(struct per_port_stats) +
6745 sizeof(struct per_pf_stats) +
6746 sizeof(struct per_queue_stats) * num_queue_stats +
6747 sizeof(struct stats_counter);
6748
6749 BNX2X_PCI_ALLOC(bp->fw_stats, &bp->fw_stats_mapping,
6750 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
6751
6752 /* Set shortcuts */
6753 bp->fw_stats_req = (struct bnx2x_fw_stats_req *)bp->fw_stats;
6754 bp->fw_stats_req_mapping = bp->fw_stats_mapping;
6755
6756 bp->fw_stats_data = (struct bnx2x_fw_stats_data *)
6757 ((u8 *)bp->fw_stats + bp->fw_stats_req_sz);
6758
6759 bp->fw_stats_data_mapping = bp->fw_stats_mapping +
6760 bp->fw_stats_req_sz;
6761 return 0;
6762
6763alloc_mem_err:
6764 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
6765 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
6766 return -ENOMEM;
a2fbb9ea
ET		 6767}
6768
f2e0899f 6769
9f6c9258 6770int bnx2x_alloc_mem(struct bnx2x *bp)
a2fbb9ea 6771{
523224a3 6772#ifdef BCM_CNIC
619c5cb6
VZ		 6773 if (!CHIP_IS_E1x(bp))
6774 /* size = the status block + ramrod buffers */
f2e0899f
DK		 6775 BNX2X_PCI_ALLOC(bp->cnic_sb.e2_sb, &bp->cnic_sb_mapping,
6776 sizeof(struct host_hc_status_block_e2));
6777 else
6778 BNX2X_PCI_ALLOC(bp->cnic_sb.e1x_sb, &bp->cnic_sb_mapping,
6779 sizeof(struct host_hc_status_block_e1x));
8badd27a 6780
523224a3
DK		 6781 /* allocate searcher T2 table */
6782 BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ);
6783#endif
a2fbb9ea 6784
8badd27a 6785
523224a3
DK		 6786 BNX2X_PCI_ALLOC(bp->def_status_blk, &bp->def_status_blk_mapping,
6787 sizeof(struct host_sp_status_block));
a2fbb9ea 6788
523224a3
DK		 6789 BNX2X_PCI_ALLOC(bp->slowpath, &bp->slowpath_mapping,
6790 sizeof(struct bnx2x_slowpath));
a2fbb9ea 6791
619c5cb6
VZ		 6792 /* Allocated memory for FW statistics */
6793 if (bnx2x_alloc_fw_stats_mem(bp))
6794 goto alloc_mem_err;
6795
6383c0b3 6796 bp->context.size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp);
f85582f8 6797
523224a3
DK		 6798 BNX2X_PCI_ALLOC(bp->context.vcxt, &bp->context.cxt_mapping,
6799 bp->context.size);
65abd74d 6800
523224a3 6801 BNX2X_ALLOC(bp->ilt->lines, sizeof(struct ilt_line) * ILT_MAX_LINES);
65abd74d 6802
523224a3
DK		 6803 if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC))
6804 goto alloc_mem_err;
65abd74d 6805
9f6c9258
DK		 6806 /* Slow path ring */
6807 BNX2X_PCI_ALLOC(bp->spq, &bp->spq_mapping, BCM_PAGE_SIZE);
65abd74d 6808
523224a3
DK		 6809 /* EQ */
6810 BNX2X_PCI_ALLOC(bp->eq_ring, &bp->eq_mapping,
6811 BCM_PAGE_SIZE * NUM_EQ_PAGES);
ab532cf3 6812
b3b83c3f
DK		 6813
6814 /* fastpath */
6815 /* need to be done at the end, since it's self adjusting to amount
6816 * of memory available for RSS queues
6817 */
6818 if (bnx2x_alloc_fp_mem(bp))
6819 goto alloc_mem_err;
9f6c9258 6820 return 0;
e1510706 6821
9f6c9258
DK		 6822alloc_mem_err:
6823 bnx2x_free_mem(bp);
6824 return -ENOMEM;
65abd74d
YG		 6825}
6826
a2fbb9ea
ET		 6827/*
6828 * Init service functions
6829 */
a2fbb9ea 6830
619c5cb6
VZ		 6831int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
6832 struct bnx2x_vlan_mac_obj *obj, bool set,
6833 int mac_type, unsigned long *ramrod_flags)
a2fbb9ea 6834{
619c5cb6
VZ		 6835 int rc;
6836 struct bnx2x_vlan_mac_ramrod_params ramrod_param;
a2fbb9ea 6837
619c5cb6 6838 memset(&ramrod_param, 0, sizeof(ramrod_param));
a2fbb9ea 6839
619c5cb6
VZ		 6840 /* Fill general parameters */
6841 ramrod_param.vlan_mac_obj = obj;
6842 ramrod_param.ramrod_flags = *ramrod_flags;
a2fbb9ea 6843
619c5cb6
VZ		 6844 /* Fill a user request section if needed */
6845 if (!test_bit(RAMROD_CONT, ramrod_flags)) {
6846 memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN);
a2fbb9ea 6847
619c5cb6 6848 __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
e3553b29 6849
619c5cb6
VZ		 6850 /* Set the command: ADD or DEL */
6851 if (set)
6852 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD;
6853 else
6854 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL;
a2fbb9ea
ET		 6855 }
6856
619c5cb6
VZ		 6857 rc = bnx2x_config_vlan_mac(bp, &ramrod_param);
6858 if (rc < 0)
6859 BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del"));
6860 return rc;
a2fbb9ea
ET		 6861}
6862
619c5cb6
VZ		 6863int bnx2x_del_all_macs(struct bnx2x *bp,
6864 struct bnx2x_vlan_mac_obj *mac_obj,
6865 int mac_type, bool wait_for_comp)
e665bfda 6866{
619c5cb6
VZ		 6867 int rc;
6868 unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
0793f83f 6869
619c5cb6
VZ		 6870 /* Wait for completion of requested */
6871 if (wait_for_comp)
6872 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
0793f83f 6873
619c5cb6
VZ		 6874 /* Set the mac type of addresses we want to clear */
6875 __set_bit(mac_type, &vlan_mac_flags);
0793f83f 6876
619c5cb6
VZ		 6877 rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags);
6878 if (rc < 0)
6879 BNX2X_ERR("Failed to delete MACs: %d\n", rc);
0793f83f 6880
619c5cb6 6881 return rc;
0793f83f
DK		 6882}
6883
619c5cb6 6884int bnx2x_set_eth_mac(struct bnx2x *bp, bool set)
523224a3 6885{
619c5cb6 6886 unsigned long ramrod_flags = 0;
e665bfda 6887
619c5cb6 6888 DP(NETIF_MSG_IFUP, "Adding Eth MAC\n");
0793f83f 6889
619c5cb6
VZ		 6890 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
6891 /* Eth MAC is set on RSS leading client (fp[0]) */
6892 return bnx2x_set_mac_one(bp, bp->dev->dev_addr, &bp->fp->mac_obj, set,
6893 BNX2X_ETH_MAC, &ramrod_flags);
e665bfda 6894}
6e30dd4e 6895
619c5cb6 6896int bnx2x_setup_leading(struct bnx2x *bp)
ec6ba945 6897{
619c5cb6 6898 return bnx2x_setup_queue(bp, &bp->fp[0], 1);
993ac7b5 6899}
a2fbb9ea 6900
d6214d7a 6901/**
e8920674 6902 * bnx2x_set_int_mode - configure interrupt mode
d6214d7a 6903 *
e8920674 6904 * @bp: driver handle
d6214d7a 6905 *
e8920674 6906 * In case of MSI-X it will also try to enable MSI-X.
d6214d7a 6907 */
9ee3d37b 6908static void __devinit bnx2x_set_int_mode(struct bnx2x *bp)
ca00392c 6909{
9ee3d37b 6910 switch (int_mode) {
d6214d7a
DK		 6911 case INT_MODE_MSI:
6912 bnx2x_enable_msi(bp);
6913 /* falling through... */
6914 case INT_MODE_INTx:
6383c0b3 6915 bp->num_queues = 1 + NON_ETH_CONTEXT_USE;
d6214d7a 6916 DP(NETIF_MSG_IFUP, "set number of queues to 1\n");
ca00392c 6917 break;
d6214d7a
DK		 6918 default:
6919 /* Set number of queues according to bp->multi_mode value */
6920 bnx2x_set_num_queues(bp);
ca00392c 6921
d6214d7a
DK		 6922 DP(NETIF_MSG_IFUP, "set number of queues to %d\n",
6923 bp->num_queues);
ca00392c 6924
d6214d7a
DK		 6925 /* if we can't use MSI-X we only need one fp,
6926 * so try to enable MSI-X with the requested number of fp's
6927 * and fallback to MSI or legacy INTx with one fp
6928 */
9ee3d37b 6929 if (bnx2x_enable_msix(bp)) {
d6214d7a
DK		 6930 /* failed to enable MSI-X */
6931 if (bp->multi_mode)
6932 DP(NETIF_MSG_IFUP,
6933 "Multi requested but failed to "
6934 "enable MSI-X (%d), "
6935 "set number of queues to %d\n",
6936 bp->num_queues,
6383c0b3
AE		 6937 1 + NON_ETH_CONTEXT_USE);
6938 bp->num_queues = 1 + NON_ETH_CONTEXT_USE;
d6214d7a 6939
9ee3d37b 6940 /* Try to enable MSI */
d6214d7a
DK		 6941 if (!(bp->flags & DISABLE_MSI_FLAG))
6942 bnx2x_enable_msi(bp);
6943 }
9f6c9258
DK		 6944 break;
6945 }
a2fbb9ea
ET		 6946}
6947
c2bff63f
DK		 6948/* must be called prioir to any HW initializations */
6949static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp)
6950{
6951 return L2_ILT_LINES(bp);
6952}
6953
523224a3
DK		 6954void bnx2x_ilt_set_info(struct bnx2x *bp)
6955{
6956 struct ilt_client_info *ilt_client;
6957 struct bnx2x_ilt *ilt = BP_ILT(bp);
6958 u16 line = 0;
6959
6960 ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp));
6961 DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line);
6962
6963 /* CDU */
6964 ilt_client = &ilt->clients[ILT_CLIENT_CDU];
6965 ilt_client->client_num = ILT_CLIENT_CDU;
6966 ilt_client->page_size = CDU_ILT_PAGE_SZ;
6967 ilt_client->flags = ILT_CLIENT_SKIP_MEM;
6968 ilt_client->start = line;
619c5cb6 6969 line += bnx2x_cid_ilt_lines(bp);
523224a3
DK		 6970#ifdef BCM_CNIC
6971 line += CNIC_ILT_LINES;
6972#endif
6973 ilt_client->end = line - 1;
6974
6975 DP(BNX2X_MSG_SP, "ilt client[CDU]: start %d, end %d, psz 0x%x, "
6976 "flags 0x%x, hw psz %d\n",
6977 ilt_client->start,
6978 ilt_client->end,
6979 ilt_client->page_size,
6980 ilt_client->flags,
6981 ilog2(ilt_client->page_size >> 12));
6982
6983 /* QM */
6984 if (QM_INIT(bp->qm_cid_count)) {
6985 ilt_client = &ilt->clients[ILT_CLIENT_QM];
6986 ilt_client->client_num = ILT_CLIENT_QM;
6987 ilt_client->page_size = QM_ILT_PAGE_SZ;
6988 ilt_client->flags = 0;
6989 ilt_client->start = line;
6990
6991 /* 4 bytes for each cid */
6992 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
6993 QM_ILT_PAGE_SZ);
6994
6995 ilt_client->end = line - 1;
6996
6997 DP(BNX2X_MSG_SP, "ilt client[QM]: start %d, end %d, psz 0x%x, "
6998 "flags 0x%x, hw psz %d\n",
6999 ilt_client->start,
7000 ilt_client->end,
7001 ilt_client->page_size,
7002 ilt_client->flags,
7003 ilog2(ilt_client->page_size >> 12));
7004
7005 }
7006 /* SRC */
7007 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
7008#ifdef BCM_CNIC
7009 ilt_client->client_num = ILT_CLIENT_SRC;
7010 ilt_client->page_size = SRC_ILT_PAGE_SZ;
7011 ilt_client->flags = 0;
7012 ilt_client->start = line;
7013 line += SRC_ILT_LINES;
7014 ilt_client->end = line - 1;
7015
7016 DP(BNX2X_MSG_SP, "ilt client[SRC]: start %d, end %d, psz 0x%x, "
7017 "flags 0x%x, hw psz %d\n",
7018 ilt_client->start,
7019 ilt_client->end,
7020 ilt_client->page_size,
7021 ilt_client->flags,
7022 ilog2(ilt_client->page_size >> 12));
7023
7024#else
7025 ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM);
7026#endif
9f6c9258 7027
523224a3
DK		 7028 /* TM */
7029 ilt_client = &ilt->clients[ILT_CLIENT_TM];
7030#ifdef BCM_CNIC
7031 ilt_client->client_num = ILT_CLIENT_TM;
7032 ilt_client->page_size = TM_ILT_PAGE_SZ;
7033 ilt_client->flags = 0;
7034 ilt_client->start = line;
7035 line += TM_ILT_LINES;
7036 ilt_client->end = line - 1;
7037
7038 DP(BNX2X_MSG_SP, "ilt client[TM]: start %d, end %d, psz 0x%x, "
7039 "flags 0x%x, hw psz %d\n",
7040 ilt_client->start,
7041 ilt_client->end,
7042 ilt_client->page_size,
7043 ilt_client->flags,
7044 ilog2(ilt_client->page_size >> 12));
9f6c9258 7045
523224a3
DK		 7046#else
7047 ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM);
7048#endif
619c5cb6 7049 BUG_ON(line > ILT_MAX_LINES);
523224a3 7050}
f85582f8 7051
619c5cb6
VZ		 7052/**
7053 * bnx2x_pf_q_prep_init - prepare INIT transition parameters
7054 *
7055 * @bp: driver handle
7056 * @fp: pointer to fastpath
7057 * @init_params: pointer to parameters structure
7058 *
7059 * parameters configured:
7060 * - HC configuration
7061 * - Queue's CDU context
7062 */
7063static inline void bnx2x_pf_q_prep_init(struct bnx2x *bp,
7064 struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params)
a2fbb9ea 7065{
6383c0b3
AE		 7066
7067 u8 cos;
619c5cb6
VZ		 7068 /* FCoE Queue uses Default SB, thus has no HC capabilities */
7069 if (!IS_FCOE_FP(fp)) {
7070 __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags);
7071 __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags);
7072
7073 /* If HC is supporterd, enable host coalescing in the transition
7074 * to INIT state.
7075 */
7076 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags);
7077 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags);
7078
7079 /* HC rate */
7080 init_params->rx.hc_rate = bp->rx_ticks ?
7081 (1000000 / bp->rx_ticks) : 0;
7082 init_params->tx.hc_rate = bp->tx_ticks ?
7083 (1000000 / bp->tx_ticks) : 0;
7084
7085 /* FW SB ID */
7086 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id =
7087 fp->fw_sb_id;
7088
7089 /*
7090 * CQ index among the SB indices: FCoE clients uses the default
7091 * SB, therefore it's different.
7092 */
6383c0b3
AE		 7093 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
7094 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
619c5cb6
VZ		 7095 }
7096
6383c0b3
AE		 7097 /* set maximum number of COSs supported by this queue */
7098 init_params->max_cos = fp->max_cos;
7099
7100 DP(BNX2X_MSG_SP, "fp: %d setting queue params max cos to: %d",
7101 fp->index, init_params->max_cos);
7102
7103 /* set the context pointers queue object */
7104 for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++)
7105 init_params->cxts[cos] =
7106 &bp->context.vcxt[fp->txdata[cos].cid].eth;
619c5cb6
VZ		 7107}
7108
6383c0b3
AE		 7109int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp,
7110 struct bnx2x_queue_state_params *q_params,
7111 struct bnx2x_queue_setup_tx_only_params *tx_only_params,
7112 int tx_index, bool leading)
7113{
7114 memset(tx_only_params, 0, sizeof(*tx_only_params));
7115
7116 /* Set the command */
7117 q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
7118
7119 /* Set tx-only QUEUE flags: don't zero statistics */
7120 tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false);
7121
7122 /* choose the index of the cid to send the slow path on */
7123 tx_only_params->cid_index = tx_index;
7124
7125 /* Set general TX_ONLY_SETUP parameters */
7126 bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index);
7127
7128 /* Set Tx TX_ONLY_SETUP parameters */
7129 bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index);
7130
7131 DP(BNX2X_MSG_SP, "preparing to send tx-only ramrod for connection:"
7132 "cos %d, primary cid %d, cid %d, "
7133 "client id %d, sp-client id %d, flags %lx",
7134 tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX],
7135 q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id,
7136 tx_only_params->gen_params.spcl_id, tx_only_params->flags);
7137
7138 /* send the ramrod */
7139 return bnx2x_queue_state_change(bp, q_params);
7140}
7141
7142
619c5cb6
VZ		 7143/**
7144 * bnx2x_setup_queue - setup queue
7145 *
7146 * @bp: driver handle
7147 * @fp: pointer to fastpath
7148 * @leading: is leading
7149 *
7150 * This function performs 2 steps in a Queue state machine
7151 * actually: 1) RESET->INIT 2) INIT->SETUP
7152 */
7153
7154int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp,
7155 bool leading)
7156{
7157 struct bnx2x_queue_state_params q_params = {0};
7158 struct bnx2x_queue_setup_params *setup_params =
7159 &q_params.params.setup;
6383c0b3
AE		 7160 struct bnx2x_queue_setup_tx_only_params *tx_only_params =
7161 &q_params.params.tx_only;
a2fbb9ea 7162 int rc;
6383c0b3
AE		 7163 u8 tx_index;
7164
7165 DP(BNX2X_MSG_SP, "setting up queue %d", fp->index);
a2fbb9ea 7166
ec6ba945
VZ		 7167 /* reset IGU state skip FCoE L2 queue */
7168 if (!IS_FCOE_FP(fp))
7169 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0,
523224a3 7170 IGU_INT_ENABLE, 0);
a2fbb9ea 7171
619c5cb6
VZ		 7172 q_params.q_obj = &fp->q_obj;
7173 /* We want to wait for completion in this context */
7174 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
a2fbb9ea 7175
619c5cb6
VZ		 7176 /* Prepare the INIT parameters */
7177 bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init);
ec6ba945 7178
619c5cb6
VZ		 7179 /* Set the command */
7180 q_params.cmd = BNX2X_Q_CMD_INIT;
7181
7182 /* Change the state to INIT */
7183 rc = bnx2x_queue_state_change(bp, &q_params);
7184 if (rc) {
6383c0b3 7185 BNX2X_ERR("Queue(%d) INIT failed\n", fp->index);
619c5cb6
VZ		 7186 return rc;
7187 }
ec6ba945 7188
6383c0b3
AE		 7189 DP(BNX2X_MSG_SP, "init complete");
7190
7191
619c5cb6
VZ		 7192 /* Now move the Queue to the SETUP state... */
7193 memset(setup_params, 0, sizeof(*setup_params));
a2fbb9ea 7194
619c5cb6
VZ		 7195 /* Set QUEUE flags */
7196 setup_params->flags = bnx2x_get_q_flags(bp, fp, leading);
523224a3 7197
619c5cb6 7198 /* Set general SETUP parameters */
6383c0b3
AE		 7199 bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params,
7200 FIRST_TX_COS_INDEX);
619c5cb6 7201
6383c0b3 7202 bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params,
619c5cb6
VZ		 7203 &setup_params->rxq_params);
7204
6383c0b3
AE		 7205 bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params,
7206 FIRST_TX_COS_INDEX);
619c5cb6
VZ		 7207
7208 /* Set the command */
7209 q_params.cmd = BNX2X_Q_CMD_SETUP;
7210
7211 /* Change the state to SETUP */
7212 rc = bnx2x_queue_state_change(bp, &q_params);
6383c0b3
AE		 7213 if (rc) {
7214 BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index);
7215 return rc;
7216 }
7217
7218 /* loop through the relevant tx-only indices */
7219 for (tx_index = FIRST_TX_ONLY_COS_INDEX;
7220 tx_index < fp->max_cos;
7221 tx_index++) {
7222
7223 /* prepare and send tx-only ramrod*/
7224 rc = bnx2x_setup_tx_only(bp, fp, &q_params,
7225 tx_only_params, tx_index, leading);
7226 if (rc) {
7227 BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n",
7228 fp->index, tx_index);
7229 return rc;
7230 }
7231 }
523224a3 7232
34f80b04 7233 return rc;
a2fbb9ea
ET		 7234}
7235
619c5cb6 7236static int bnx2x_stop_queue(struct bnx2x *bp, int index)
a2fbb9ea 7237{
619c5cb6 7238 struct bnx2x_fastpath *fp = &bp->fp[index];
6383c0b3 7239 struct bnx2x_fp_txdata *txdata;
619c5cb6 7240 struct bnx2x_queue_state_params q_params = {0};
6383c0b3
AE		 7241 int rc, tx_index;
7242
7243 DP(BNX2X_MSG_SP, "stopping queue %d cid %d", index, fp->cid);
a2fbb9ea 7244
619c5cb6
VZ		 7245 q_params.q_obj = &fp->q_obj;
7246 /* We want to wait for completion in this context */
7247 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
a2fbb9ea 7248
6383c0b3
AE		 7249
7250 /* close tx-only connections */
7251 for (tx_index = FIRST_TX_ONLY_COS_INDEX;
7252 tx_index < fp->max_cos;
7253 tx_index++){
7254
7255 /* ascertain this is a normal queue*/
7256 txdata = &fp->txdata[tx_index];
7257
7258 DP(BNX2X_MSG_SP, "stopping tx-only queue %d",
7259 txdata->txq_index);
7260
7261 /* send halt terminate on tx-only connection */
7262 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
7263 memset(&q_params.params.terminate, 0,
7264 sizeof(q_params.params.terminate));
7265 q_params.params.terminate.cid_index = tx_index;
7266
7267 rc = bnx2x_queue_state_change(bp, &q_params);
7268 if (rc)
7269 return rc;
7270
7271 /* send halt terminate on tx-only connection */
7272 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
7273 memset(&q_params.params.cfc_del, 0,
7274 sizeof(q_params.params.cfc_del));
7275 q_params.params.cfc_del.cid_index = tx_index;
7276 rc = bnx2x_queue_state_change(bp, &q_params);
7277 if (rc)
7278 return rc;
7279 }
7280 /* Stop the primary connection: */
7281 /* ...halt the connection */
619c5cb6
VZ		 7282 q_params.cmd = BNX2X_Q_CMD_HALT;
7283 rc = bnx2x_queue_state_change(bp, &q_params);
7284 if (rc)
da5a662a 7285 return rc;
a2fbb9ea 7286
6383c0b3 7287 /* ...terminate the connection */
619c5cb6 7288 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
6383c0b3
AE		 7289 memset(&q_params.params.terminate, 0,
7290 sizeof(q_params.params.terminate));
7291 q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
619c5cb6
VZ		 7292 rc = bnx2x_queue_state_change(bp, &q_params);
7293 if (rc)
523224a3 7294 return rc;
6383c0b3 7295 /* ...delete cfc entry */
619c5cb6 7296 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
6383c0b3
AE		 7297 memset(&q_params.params.cfc_del, 0,
7298 sizeof(q_params.params.cfc_del));
7299 q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
619c5cb6 7300 return bnx2x_queue_state_change(bp, &q_params);
523224a3
DK		 7301}
7302
7303
34f80b04
EG		 7304static void bnx2x_reset_func(struct bnx2x *bp)
7305{
7306 int port = BP_PORT(bp);
7307 int func = BP_FUNC(bp);
f2e0899f 7308 int i;
523224a3
DK		 7309
7310 /* Disable the function in the FW */
7311 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
7312 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
7313 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
7314 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
7315
7316 /* FP SBs */
ec6ba945 7317 for_each_eth_queue(bp, i) {
523224a3 7318 struct bnx2x_fastpath *fp = &bp->fp[i];
619c5cb6 7319 REG_WR8(bp, BAR_CSTRORM_INTMEM +
6383c0b3
AE		 7320 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
7321 SB_DISABLED);
523224a3
DK		 7322 }
7323
619c5cb6
VZ		 7324#ifdef BCM_CNIC
7325 /* CNIC SB */
7326 REG_WR8(bp, BAR_CSTRORM_INTMEM +
7327 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(bnx2x_cnic_fw_sb_id(bp)),
7328 SB_DISABLED);
7329#endif
523224a3 7330 /* SP SB */
619c5cb6 7331 REG_WR8(bp, BAR_CSTRORM_INTMEM +
6383c0b3
AE		 7332 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func),
7333 SB_DISABLED);
523224a3
DK		 7334
7335 for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++)
7336 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
7337 0);
34f80b04
EG		 7338
7339 /* Configure IGU */
f2e0899f
DK		 7340 if (bp->common.int_block == INT_BLOCK_HC) {
7341 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7342 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7343 } else {
7344 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
7345 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
7346 }
34f80b04 7347
37b091ba
MC		 7348#ifdef BCM_CNIC
7349 /* Disable Timer scan */
7350 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
7351 /*
7352 * Wait for at least 10ms and up to 2 second for the timers scan to
7353 * complete
7354 */
7355 for (i = 0; i < 200; i++) {
7356 msleep(10);
7357 if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4))
7358 break;
7359 }
7360#endif
34f80b04 7361 /* Clear ILT */
f2e0899f
DK		 7362 bnx2x_clear_func_ilt(bp, func);
7363
7364 /* Timers workaround bug for E2: if this is vnic-3,
7365 * we need to set the entire ilt range for this timers.
7366 */
619c5cb6 7367 if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) {
f2e0899f
DK		 7368 struct ilt_client_info ilt_cli;
7369 /* use dummy TM client */
7370 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
7371 ilt_cli.start = 0;
7372 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
7373 ilt_cli.client_num = ILT_CLIENT_TM;
7374
7375 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR);
7376 }
7377
7378 /* this assumes that reset_port() called before reset_func()*/
619c5cb6 7379 if (!CHIP_IS_E1x(bp))
f2e0899f 7380 bnx2x_pf_disable(bp);
523224a3
DK		 7381
7382 bp->dmae_ready = 0;
34f80b04
EG		 7383}
7384
7385static void bnx2x_reset_port(struct bnx2x *bp)
7386{
7387 int port = BP_PORT(bp);
7388 u32 val;
7389
619c5cb6
VZ		 7390 /* Reset physical Link */
7391 bnx2x__link_reset(bp);
7392
34f80b04
EG		 7393 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
7394
7395 /* Do not rcv packets to BRB */
7396 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
7397 /* Do not direct rcv packets that are not for MCP to the BRB */
7398 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
7399 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
7400
7401 /* Configure AEU */
7402 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
7403
7404 msleep(100);
7405 /* Check for BRB port occupancy */
7406 val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
7407 if (val)
7408 DP(NETIF_MSG_IFDOWN,
33471629 7409 "BRB1 is not empty %d blocks are occupied\n", val);
34f80b04
EG		 7410
7411 /* TODO: Close Doorbell port? */
7412}
7413
619c5cb6 7414static inline int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code)
34f80b04 7415{
619c5cb6 7416 struct bnx2x_func_state_params func_params = {0};
34f80b04 7417
619c5cb6
VZ		 7418 /* Prepare parameters for function state transitions */
7419 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
34f80b04 7420
619c5cb6
VZ		 7421 func_params.f_obj = &bp->func_obj;
7422 func_params.cmd = BNX2X_F_CMD_HW_RESET;
34f80b04 7423
619c5cb6 7424 func_params.params.hw_init.load_phase = load_code;
49d66772 7425
619c5cb6 7426 return bnx2x_func_state_change(bp, &func_params);
34f80b04
EG		 7427}
7428
619c5cb6 7429static inline int bnx2x_func_stop(struct bnx2x *bp)
ec6ba945 7430{
619c5cb6
VZ		 7431 struct bnx2x_func_state_params func_params = {0};
7432 int rc;
228241eb 7433
619c5cb6
VZ		 7434 /* Prepare parameters for function state transitions */
7435 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
7436 func_params.f_obj = &bp->func_obj;
7437 func_params.cmd = BNX2X_F_CMD_STOP;
da5a662a 7438
619c5cb6
VZ		 7439 /*
7440 * Try to stop the function the 'good way'. If fails (in case
7441 * of a parity error during bnx2x_chip_cleanup()) and we are
7442 * not in a debug mode, perform a state transaction in order to
7443 * enable further HW_RESET transaction.
7444 */
7445 rc = bnx2x_func_state_change(bp, &func_params);
7446 if (rc) {
34f80b04 7447#ifdef BNX2X_STOP_ON_ERROR
619c5cb6 7448 return rc;
34f80b04 7449#else
619c5cb6
VZ		 7450 BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry "
7451 "transaction\n");
7452 __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
7453 return bnx2x_func_state_change(bp, &func_params);
34f80b04 7454#endif
228241eb 7455 }
a2fbb9ea 7456
619c5cb6
VZ		 7457 return 0;
7458}
523224a3 7459
619c5cb6
VZ		 7460/**
7461 * bnx2x_send_unload_req - request unload mode from the MCP.
7462 *
7463 * @bp: driver handle
7464 * @unload_mode: requested function's unload mode
7465 *
7466 * Return unload mode returned by the MCP: COMMON, PORT or FUNC.
7467 */
7468u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode)
7469{
7470 u32 reset_code = 0;
7471 int port = BP_PORT(bp);
3101c2bc 7472
619c5cb6 7473 /* Select the UNLOAD request mode */
65abd74d
YG		 7474 if (unload_mode == UNLOAD_NORMAL)
7475 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
7476
7d0446c2 7477 else if (bp->flags & NO_WOL_FLAG)
65abd74d 7478 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
65abd74d 7479
7d0446c2 7480 else if (bp->wol) {
65abd74d
YG		 7481 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
7482 u8 *mac_addr = bp->dev->dev_addr;
7483 u32 val;
7484 /* The mac address is written to entries 1-4 to
7485 preserve entry 0 which is used by the PMF */
7486 u8 entry = (BP_E1HVN(bp) + 1)*8;
7487
7488 val = (mac_addr[0] << 8) | mac_addr[1];
7489 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val);
7490
7491 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
7492 (mac_addr[4] << 8) | mac_addr[5];
7493 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
7494
7495 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
7496
7497 } else
7498 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
da5a662a 7499
619c5cb6
VZ		 7500 /* Send the request to the MCP */
7501 if (!BP_NOMCP(bp))
7502 reset_code = bnx2x_fw_command(bp, reset_code, 0);
7503 else {
7504 int path = BP_PATH(bp);
7505
7506 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d] "
7507 "%d, %d, %d\n",
7508 path, load_count[path][0], load_count[path][1],
7509 load_count[path][2]);
7510 load_count[path][0]--;
7511 load_count[path][1 + port]--;
7512 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d] "
7513 "%d, %d, %d\n",
7514 path, load_count[path][0], load_count[path][1],
7515 load_count[path][2]);
7516 if (load_count[path][0] == 0)
7517 reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
7518 else if (load_count[path][1 + port] == 0)
7519 reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT;
7520 else
7521 reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
7522 }
7523
7524 return reset_code;
7525}
7526
7527/**
7528 * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP.
7529 *
7530 * @bp: driver handle
7531 */
7532void bnx2x_send_unload_done(struct bnx2x *bp)
7533{
7534 /* Report UNLOAD_DONE to MCP */
7535 if (!BP_NOMCP(bp))
7536 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
7537}
7538
7539void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode)
7540{
7541 int port = BP_PORT(bp);
6383c0b3
AE		 7542 int i, rc = 0;
7543 u8 cos;
619c5cb6
VZ		 7544 struct bnx2x_mcast_ramrod_params rparam = {0};
7545 u32 reset_code;
7546
7547 /* Wait until tx fastpath tasks complete */
7548 for_each_tx_queue(bp, i) {
7549 struct bnx2x_fastpath *fp = &bp->fp[i];
7550
6383c0b3
AE		 7551 for_each_cos_in_tx_queue(fp, cos)
7552 rc = bnx2x_clean_tx_queue(bp, &fp->txdata[cos]);
619c5cb6
VZ		 7553#ifdef BNX2X_STOP_ON_ERROR
7554 if (rc)
7555 return;
7556#endif
7557 }
7558
7559 /* Give HW time to discard old tx messages */
7560 usleep_range(1000, 1000);
7561
7562 /* Clean all ETH MACs */
7563 rc = bnx2x_del_all_macs(bp, &bp->fp[0].mac_obj, BNX2X_ETH_MAC, false);
7564 if (rc < 0)
7565 BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc);
7566
7567 /* Clean up UC list */
7568 rc = bnx2x_del_all_macs(bp, &bp->fp[0].mac_obj, BNX2X_UC_LIST_MAC,
7569 true);
7570 if (rc < 0)
7571 BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: "
7572 "%d\n", rc);
7573
7574 /* Disable LLH */
7575 if (!CHIP_IS_E1(bp))
7576 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
7577
7578 /* Set "drop all" (stop Rx).
7579 * We need to take a netif_addr_lock() here in order to prevent
7580 * a race between the completion code and this code.
7581 */
7582 netif_addr_lock_bh(bp->dev);
7583 /* Schedule the rx_mode command */
7584 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
7585 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
7586 else
7587 bnx2x_set_storm_rx_mode(bp);
7588
7589 /* Cleanup multicast configuration */
7590 rparam.mcast_obj = &bp->mcast_obj;
7591 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
7592 if (rc < 0)
7593 BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc);
7594
7595 netif_addr_unlock_bh(bp->dev);
7596
7597
34f80b04 7598 /* Close multi and leading connections
619c5cb6
VZ		 7599 * Completions for ramrods are collected in a synchronous way
7600 */
523224a3 7601 for_each_queue(bp, i)
619c5cb6 7602 if (bnx2x_stop_queue(bp, i))
523224a3
DK		 7603#ifdef BNX2X_STOP_ON_ERROR
7604 return;
7605#else
228241eb 7606 goto unload_error;
523224a3 7607#endif
619c5cb6
VZ		 7608 /* If SP settings didn't get completed so far - something
7609 * very wrong has happen.
7610 */
7611 if (!bnx2x_wait_sp_comp(bp, ~0x0UL))
7612 BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n");
a2fbb9ea 7613
619c5cb6
VZ		 7614#ifndef BNX2X_STOP_ON_ERROR
7615unload_error:
7616#endif
523224a3 7617 rc = bnx2x_func_stop(bp);
da5a662a 7618 if (rc) {
523224a3 7619 BNX2X_ERR("Function stop failed!\n");
da5a662a 7620#ifdef BNX2X_STOP_ON_ERROR
523224a3 7621 return;
523224a3 7622#endif
34f80b04 7623 }
a2fbb9ea 7624
619c5cb6
VZ		 7625 /*
7626 * Send the UNLOAD_REQUEST to the MCP. This will return if
7627 * this function should perform FUNC, PORT or COMMON HW
7628 * reset.
7629 */
7630 reset_code = bnx2x_send_unload_req(bp, unload_mode);
a2fbb9ea 7631
523224a3
DK		 7632 /* Disable HW interrupts, NAPI */
7633 bnx2x_netif_stop(bp, 1);
7634
7635 /* Release IRQs */
d6214d7a 7636 bnx2x_free_irq(bp);
523224a3 7637
a2fbb9ea 7638 /* Reset the chip */
619c5cb6
VZ		 7639 rc = bnx2x_reset_hw(bp, reset_code);
7640 if (rc)
7641 BNX2X_ERR("HW_RESET failed\n");
a2fbb9ea 7642
356e2385 7643
619c5cb6
VZ		 7644 /* Report UNLOAD_DONE to MCP */
7645 bnx2x_send_unload_done(bp);
72fd0718
VZ		 7646}
7647
9f6c9258 7648void bnx2x_disable_close_the_gate(struct bnx2x *bp)
72fd0718
VZ		 7649{
7650 u32 val;
7651
7652 DP(NETIF_MSG_HW, "Disabling \"close the gates\"\n");
7653
7654 if (CHIP_IS_E1(bp)) {
7655 int port = BP_PORT(bp);
7656 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
7657 MISC_REG_AEU_MASK_ATTN_FUNC_0;
7658
7659 val = REG_RD(bp, addr);
7660 val &= ~(0x300);
7661 REG_WR(bp, addr, val);
619c5cb6 7662 } else {
72fd0718
VZ		 7663 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK);
7664 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
7665 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
7666 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val);
7667 }
7668}
7669
72fd0718
VZ		 7670/* Close gates #2, #3 and #4: */
7671static void bnx2x_set_234_gates(struct bnx2x *bp, bool close)
7672{
c9ee9206 7673 u32 val;
72fd0718
VZ		 7674
7675 /* Gates #2 and #4a are closed/opened for "not E1" only */
7676 if (!CHIP_IS_E1(bp)) {
7677 /* #4 */
c9ee9206 7678 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close);
72fd0718 7679 /* #2 */
c9ee9206 7680 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close);
72fd0718
VZ		 7681 }
7682
7683 /* #3 */
c9ee9206
VZ		 7684 if (CHIP_IS_E1x(bp)) {
7685 /* Prevent interrupts from HC on both ports */
7686 val = REG_RD(bp, HC_REG_CONFIG_1);
7687 REG_WR(bp, HC_REG_CONFIG_1,
7688 (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) :
7689 (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1));
7690
7691 val = REG_RD(bp, HC_REG_CONFIG_0);
7692 REG_WR(bp, HC_REG_CONFIG_0,
7693 (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) :
7694 (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0));
7695 } else {
7696 /* Prevent incomming interrupts in IGU */
7697 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
7698
7699 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION,
7700 (!close) ?
7701 (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) :
7702 (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
7703 }
72fd0718
VZ		 7704
7705 DP(NETIF_MSG_HW, "%s gates #2, #3 and #4\n",
7706 close ? "closing" : "opening");
7707 mmiowb();
7708}
7709
7710#define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */
7711
7712static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val)
7713{
7714 /* Do some magic... */
7715 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
7716 *magic_val = val & SHARED_MF_CLP_MAGIC;
7717 MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
7718}
7719
e8920674
DK		 7720/**
7721 * bnx2x_clp_reset_done - restore the value of the `magic' bit.
72fd0718 7722 *
e8920674
DK		 7723 * @bp: driver handle
7724 * @magic_val: old value of the `magic' bit.
72fd0718
VZ		 7725 */
7726static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val)
7727{
7728 /* Restore the `magic' bit value... */
72fd0718
VZ		 7729 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
7730 MF_CFG_WR(bp, shared_mf_config.clp_mb,
7731 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
7732}
7733
f85582f8 7734/**
e8920674 7735 * bnx2x_reset_mcp_prep - prepare for MCP reset.
72fd0718 7736 *
e8920674
DK		 7737 * @bp: driver handle
7738 * @magic_val: old value of 'magic' bit.
7739 *
7740 * Takes care of CLP configurations.
72fd0718
VZ		 7741 */
7742static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val)
7743{
7744 u32 shmem;
7745 u32 validity_offset;
7746
7747 DP(NETIF_MSG_HW, "Starting\n");
7748
7749 /* Set `magic' bit in order to save MF config */
7750 if (!CHIP_IS_E1(bp))
7751 bnx2x_clp_reset_prep(bp, magic_val);
7752
7753 /* Get shmem offset */
7754 shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
7755 validity_offset = offsetof(struct shmem_region, validity_map[0]);
7756
7757 /* Clear validity map flags */
7758 if (shmem > 0)
7759 REG_WR(bp, shmem + validity_offset, 0);
7760}
7761
7762#define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */
7763#define MCP_ONE_TIMEOUT 100 /* 100 ms */
7764
e8920674
DK		 7765/**
7766 * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT
72fd0718 7767 *
e8920674 7768 * @bp: driver handle
72fd0718
VZ		 7769 */
7770static inline void bnx2x_mcp_wait_one(struct bnx2x *bp)
7771{
7772 /* special handling for emulation and FPGA,
7773 wait 10 times longer */
7774 if (CHIP_REV_IS_SLOW(bp))
7775 msleep(MCP_ONE_TIMEOUT*10);
7776 else
7777 msleep(MCP_ONE_TIMEOUT);
7778}
7779
1b6e2ceb
DK		 7780/*
7781 * initializes bp->common.shmem_base and waits for validity signature to appear
7782 */
7783static int bnx2x_init_shmem(struct bnx2x *bp)
72fd0718 7784{
1b6e2ceb
DK		 7785 int cnt = 0;
7786 u32 val = 0;
72fd0718 7787
1b6e2ceb
DK		 7788 do {
7789 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
7790 if (bp->common.shmem_base) {
7791 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
7792 if (val & SHR_MEM_VALIDITY_MB)
7793 return 0;
7794 }
72fd0718 7795
1b6e2ceb 7796 bnx2x_mcp_wait_one(bp);
72fd0718 7797
1b6e2ceb 7798 } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
72fd0718 7799
1b6e2ceb 7800 BNX2X_ERR("BAD MCP validity signature\n");
72fd0718 7801
1b6e2ceb
DK		 7802 return -ENODEV;
7803}
72fd0718 7804
1b6e2ceb
DK		 7805static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val)
7806{
7807 int rc = bnx2x_init_shmem(bp);
72fd0718 7808
72fd0718
VZ		 7809 /* Restore the `magic' bit value */
7810 if (!CHIP_IS_E1(bp))
7811 bnx2x_clp_reset_done(bp, magic_val);
7812
7813 return rc;
7814}
7815
7816static void bnx2x_pxp_prep(struct bnx2x *bp)
7817{
7818 if (!CHIP_IS_E1(bp)) {
7819 REG_WR(bp, PXP2_REG_RD_START_INIT, 0);
7820 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0);
72fd0718
VZ		 7821 mmiowb();
7822 }
7823}
7824
7825/*
7826 * Reset the whole chip except for:
7827 * - PCIE core
7828 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by
7829 * one reset bit)
7830 * - IGU
7831 * - MISC (including AEU)
7832 * - GRC
7833 * - RBCN, RBCP
7834 */
c9ee9206 7835static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global)
72fd0718
VZ		 7836{
7837 u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
c9ee9206
VZ		 7838 u32 global_bits2;
7839
7840 /*
7841 * Bits that have to be set in reset_mask2 if we want to reset 'global'
7842 * (per chip) blocks.
7843 */
7844 global_bits2 =
7845 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
7846 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
72fd0718
VZ		 7847
7848 not_reset_mask1 =
7849 MISC_REGISTERS_RESET_REG_1_RST_HC |
7850 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
7851 MISC_REGISTERS_RESET_REG_1_RST_PXP;
7852
7853 not_reset_mask2 =
c9ee9206 7854 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
72fd0718
VZ		 7855 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
7856 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
7857 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
7858 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
7859 MISC_REGISTERS_RESET_REG_2_RST_GRC |
7860 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
7861 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B;
7862
7863 reset_mask1 = 0xffffffff;
7864
7865 if (CHIP_IS_E1(bp))
7866 reset_mask2 = 0xffff;
7867 else
7868 reset_mask2 = 0x1ffff;
7869
c9ee9206
VZ		 7870 if (CHIP_IS_E3(bp)) {
7871 reset_mask2 |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
7872 reset_mask2 |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
7873 }
7874
7875 /* Don't reset global blocks unless we need to */
7876 if (!global)
7877 reset_mask2 &= ~global_bits2;
7878
7879 /*
7880 * In case of attention in the QM, we need to reset PXP
7881 * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
7882 * because otherwise QM reset would release 'close the gates' shortly
7883 * before resetting the PXP, then the PSWRQ would send a write
7884 * request to PGLUE. Then when PXP is reset, PGLUE would try to
7885 * read the payload data from PSWWR, but PSWWR would not
7886 * respond. The write queue in PGLUE would stuck, dmae commands
7887 * would not return. Therefore it's important to reset the second
7888 * reset register (containing the
7889 * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
7890 * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
7891 * bit).
7892 */
72fd0718
VZ		 7893 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
7894 reset_mask2 & (~not_reset_mask2));
7895
c9ee9206
VZ		 7896 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
7897 reset_mask1 & (~not_reset_mask1));
7898
72fd0718
VZ		 7899 barrier();
7900 mmiowb();
7901
72fd0718 7902 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, reset_mask2);
c9ee9206 7903 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
72fd0718
VZ		 7904 mmiowb();
7905}
7906
c9ee9206
VZ		 7907/**
7908 * bnx2x_er_poll_igu_vq - poll for pending writes bit.
7909 * It should get cleared in no more than 1s.
7910 *
7911 * @bp: driver handle
7912 *
7913 * It should get cleared in no more than 1s. Returns 0 if
7914 * pending writes bit gets cleared.
7915 */
7916static int bnx2x_er_poll_igu_vq(struct bnx2x *bp)
7917{
7918 u32 cnt = 1000;
7919 u32 pend_bits = 0;
7920
7921 do {
7922 pend_bits = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS);
7923
7924 if (pend_bits == 0)
7925 break;
7926
7927 usleep_range(1000, 1000);
7928 } while (cnt-- > 0);
7929
7930 if (cnt <= 0) {
7931 BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n",
7932 pend_bits);
7933 return -EBUSY;
7934 }
7935
7936 return 0;
7937}
7938
7939static int bnx2x_process_kill(struct bnx2x *bp, bool global)
72fd0718
VZ		 7940{
7941 int cnt = 1000;
7942 u32 val = 0;
7943 u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
7944
7945
7946 /* Empty the Tetris buffer, wait for 1s */
7947 do {
7948 sr_cnt = REG_RD(bp, PXP2_REG_RD_SR_CNT);
7949 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT);
7950 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0);
7951 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1);
7952 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2);
7953 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
7954 ((port_is_idle_0 & 0x1) == 0x1) &&
7955 ((port_is_idle_1 & 0x1) == 0x1) &&
7956 (pgl_exp_rom2 == 0xffffffff))
7957 break;
c9ee9206 7958 usleep_range(1000, 1000);
72fd0718
VZ		 7959 } while (cnt-- > 0);
7960
7961 if (cnt <= 0) {
7962 DP(NETIF_MSG_HW, "Tetris buffer didn't get empty or there"
7963 " are still"
7964 " outstanding read requests after 1s!\n");
7965 DP(NETIF_MSG_HW, "sr_cnt=0x%08x, blk_cnt=0x%08x,"
7966 " port_is_idle_0=0x%08x,"
7967 " port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
7968 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
7969 pgl_exp_rom2);
7970 return -EAGAIN;
7971 }
7972
7973 barrier();
7974
7975 /* Close gates #2, #3 and #4 */
7976 bnx2x_set_234_gates(bp, true);
7977
c9ee9206
VZ		 7978 /* Poll for IGU VQs for 57712 and newer chips */
7979 if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp))
7980 return -EAGAIN;
7981
7982
72fd0718
VZ		 7983 /* TBD: Indicate that "process kill" is in progress to MCP */
7984
7985 /* Clear "unprepared" bit */
7986 REG_WR(bp, MISC_REG_UNPREPARED, 0);
7987 barrier();
7988
7989 /* Make sure all is written to the chip before the reset */
7990 mmiowb();
7991
7992 /* Wait for 1ms to empty GLUE and PCI-E core queues,
7993 * PSWHST, GRC and PSWRD Tetris buffer.
7994 */
c9ee9206 7995 usleep_range(1000, 1000);
72fd0718
VZ		 7996
7997 /* Prepare to chip reset: */
7998 /* MCP */
c9ee9206
VZ		 7999 if (global)
8000 bnx2x_reset_mcp_prep(bp, &val);
72fd0718
VZ		 8001
8002 /* PXP */
8003 bnx2x_pxp_prep(bp);
8004 barrier();
8005
8006 /* reset the chip */
c9ee9206 8007 bnx2x_process_kill_chip_reset(bp, global);
72fd0718
VZ		 8008 barrier();
8009
8010 /* Recover after reset: */
8011 /* MCP */
c9ee9206 8012 if (global && bnx2x_reset_mcp_comp(bp, val))
72fd0718
VZ		 8013 return -EAGAIN;
8014
c9ee9206
VZ		 8015 /* TBD: Add resetting the NO_MCP mode DB here */
8016
72fd0718
VZ		 8017 /* PXP */
8018 bnx2x_pxp_prep(bp);
8019
8020 /* Open the gates #2, #3 and #4 */
8021 bnx2x_set_234_gates(bp, false);
8022
8023 /* TBD: IGU/AEU preparation bring back the AEU/IGU to a
8024 * reset state, re-enable attentions. */
8025
a2fbb9ea
ET		 8026 return 0;
8027}
8028
c9ee9206 8029int bnx2x_leader_reset(struct bnx2x *bp)
72fd0718
VZ		 8030{
8031 int rc = 0;
c9ee9206
VZ		 8032 bool global = bnx2x_reset_is_global(bp);
8033
72fd0718 8034 /* Try to recover after the failure */
c9ee9206
VZ		 8035 if (bnx2x_process_kill(bp, global)) {
8036 netdev_err(bp->dev, "Something bad had happen on engine %d! "
8037 "Aii!\n", BP_PATH(bp));
72fd0718
VZ		 8038 rc = -EAGAIN;
8039 goto exit_leader_reset;
8040 }
8041
c9ee9206
VZ		 8042 /*
8043 * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver
8044 * state.
8045 */
72fd0718 8046 bnx2x_set_reset_done(bp);
c9ee9206
VZ		 8047 if (global)
8048 bnx2x_clear_reset_global(bp);
72fd0718
VZ		 8049
8050exit_leader_reset:
8051 bp->is_leader = 0;
c9ee9206
VZ		 8052 bnx2x_release_leader_lock(bp);
8053 smp_mb();
72fd0718
VZ		 8054 return rc;
8055}
8056
c9ee9206
VZ		 8057static inline void bnx2x_recovery_failed(struct bnx2x *bp)
8058{
8059 netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n");
8060
8061 /* Disconnect this device */
8062 netif_device_detach(bp->dev);
8063
8064 /*
8065 * Block ifup for all function on this engine until "process kill"
8066 * or power cycle.
8067 */
8068 bnx2x_set_reset_in_progress(bp);
8069
8070 /* Shut down the power */
8071 bnx2x_set_power_state(bp, PCI_D3hot);
8072
8073 bp->recovery_state = BNX2X_RECOVERY_FAILED;
8074
8075 smp_mb();
8076}
8077
8078/*
8079 * Assumption: runs under rtnl lock. This together with the fact
6383c0b3 8080 * that it's called only from bnx2x_sp_rtnl() ensure that it
72fd0718
VZ		 8081 * will never be called when netif_running(bp->dev) is false.
8082 */
8083static void bnx2x_parity_recover(struct bnx2x *bp)
8084{
c9ee9206
VZ		 8085 bool global = false;
8086
72fd0718
VZ		 8087 DP(NETIF_MSG_HW, "Handling parity\n");
8088 while (1) {
8089 switch (bp->recovery_state) {
8090 case BNX2X_RECOVERY_INIT:
8091 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n");
c9ee9206
VZ		 8092 bnx2x_chk_parity_attn(bp, &global, false);
8093
72fd0718 8094 /* Try to get a LEADER_LOCK HW lock */
c9ee9206
VZ		 8095 if (bnx2x_trylock_leader_lock(bp)) {
8096 bnx2x_set_reset_in_progress(bp);
8097 /*
8098 * Check if there is a global attention and if
8099 * there was a global attention, set the global
8100 * reset bit.
8101 */
8102
8103 if (global)
8104 bnx2x_set_reset_global(bp);
8105
72fd0718 8106 bp->is_leader = 1;
c9ee9206 8107 }
72fd0718
VZ		 8108
8109 /* Stop the driver */
8110 /* If interface has been removed - break */
8111 if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY))
8112 return;
8113
8114 bp->recovery_state = BNX2X_RECOVERY_WAIT;
c9ee9206
VZ		 8115
8116 /*
8117 * Reset MCP command sequence number and MCP mail box
8118 * sequence as we are going to reset the MCP.
8119 */
8120 if (global) {
8121 bp->fw_seq = 0;
8122 bp->fw_drv_pulse_wr_seq = 0;
8123 }
8124
8125 /* Ensure "is_leader", MCP command sequence and
8126 * "recovery_state" update values are seen on other
8127 * CPUs.
72fd0718 8128 */
c9ee9206 8129 smp_mb();
72fd0718
VZ		 8130 break;
8131
8132 case BNX2X_RECOVERY_WAIT:
8133 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n");
8134 if (bp->is_leader) {
c9ee9206
VZ		 8135 int other_engine = BP_PATH(bp) ? 0 : 1;
8136 u32 other_load_counter =
8137 bnx2x_get_load_cnt(bp, other_engine);
8138 u32 load_counter =
8139 bnx2x_get_load_cnt(bp, BP_PATH(bp));
8140 global = bnx2x_reset_is_global(bp);
8141
8142 /*
8143 * In case of a parity in a global block, let
8144 * the first leader that performs a
8145 * leader_reset() reset the global blocks in
8146 * order to clear global attentions. Otherwise
8147 * the the gates will remain closed for that
8148 * engine.
8149 */
8150 if (load_counter ||
8151 (global && other_load_counter)) {
72fd0718
VZ		 8152 /* Wait until all other functions get
8153 * down.
8154 */
7be08a72 8155 schedule_delayed_work(&bp->sp_rtnl_task,
72fd0718
VZ		 8156 HZ/10);
8157 return;
8158 } else {
8159 /* If all other functions got down -
8160 * try to bring the chip back to
8161 * normal. In any case it's an exit
8162 * point for a leader.
8163 */
c9ee9206
VZ		 8164 if (bnx2x_leader_reset(bp)) {
8165 bnx2x_recovery_failed(bp);
72fd0718
VZ		 8166 return;
8167 }
8168
c9ee9206
VZ		 8169 /* If we are here, means that the
8170 * leader has succeeded and doesn't
8171 * want to be a leader any more. Try
8172 * to continue as a none-leader.
8173 */
8174 break;
72fd0718
VZ		 8175 }
8176 } else { /* non-leader */
c9ee9206 8177 if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) {
72fd0718
VZ		 8178 /* Try to get a LEADER_LOCK HW lock as
8179 * long as a former leader may have
8180 * been unloaded by the user or
8181 * released a leadership by another
8182 * reason.
8183 */
c9ee9206 8184 if (bnx2x_trylock_leader_lock(bp)) {
72fd0718
VZ		 8185 /* I'm a leader now! Restart a
8186 * switch case.
8187 */
8188 bp->is_leader = 1;
8189 break;
8190 }
8191
7be08a72 8192 schedule_delayed_work(&bp->sp_rtnl_task,
72fd0718
VZ		 8193 HZ/10);
8194 return;
8195
c9ee9206
VZ		 8196 } else {
8197 /*
8198 * If there was a global attention, wait
8199 * for it to be cleared.
8200 */
8201 if (bnx2x_reset_is_global(bp)) {
8202 schedule_delayed_work(
7be08a72
AE		 8203 &bp->sp_rtnl_task,
8204 HZ/10);
c9ee9206
VZ		 8205 return;
8206 }
8207
8208 if (bnx2x_nic_load(bp, LOAD_NORMAL))
8209 bnx2x_recovery_failed(bp);
8210 else {
8211 bp->recovery_state =
8212 BNX2X_RECOVERY_DONE;
8213 smp_mb();
8214 }
8215
72fd0718
VZ		 8216 return;
8217 }
8218 }
8219 default:
8220 return;
8221 }
8222 }
8223}
8224
8225/* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is
8226 * scheduled on a general queue in order to prevent a dead lock.
8227 */
7be08a72 8228static void bnx2x_sp_rtnl_task(struct work_struct *work)
34f80b04 8229{
7be08a72 8230 struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work);
34f80b04
EG		 8231
8232 rtnl_lock();
8233
8234 if (!netif_running(bp->dev))
7be08a72
AE		 8235 goto sp_rtnl_exit;
8236
6383c0b3
AE		 8237 if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state))
8238 bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos);
8239
7be08a72
AE		 8240 /* if stop on error is defined no recovery flows should be executed */
8241#ifdef BNX2X_STOP_ON_ERROR
8242 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined "
8243 "so reset not done to allow debug dump,\n"
8244 "you will need to reboot when done\n");
8245 goto sp_rtnl_exit;
8246#endif
34f80b04 8247
7be08a72
AE		 8248 if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) {
8249 /*
8250 * Clear TX_TIMEOUT bit as we are going to reset the function
8251 * anyway.
8252 */
8253 smp_mb__before_clear_bit();
8254 clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state);
8255 smp_mb__after_clear_bit();
72fd0718 8256 bnx2x_parity_recover(bp);
7be08a72
AE		 8257 } else if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT,
8258 &bp->sp_rtnl_state)){
72fd0718
VZ		 8259 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
8260 bnx2x_nic_load(bp, LOAD_NORMAL);
8261 }
34f80b04 8262
7be08a72 8263sp_rtnl_exit:
34f80b04
EG		 8264 rtnl_unlock();
8265}
8266
a2fbb9ea
ET		 8267/* end of nic load/unload */
8268
3deb8167
YR		 8269static void bnx2x_period_task(struct work_struct *work)
8270{
8271 struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work);
8272
8273 if (!netif_running(bp->dev))
8274 goto period_task_exit;
8275
8276 if (CHIP_REV_IS_SLOW(bp)) {
8277 BNX2X_ERR("period task called on emulation, ignoring\n");
8278 goto period_task_exit;
8279 }
8280
8281 bnx2x_acquire_phy_lock(bp);
8282 /*
8283 * The barrier is needed to ensure the ordering between the writing to
8284 * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
8285 * the reading here.
8286 */
8287 smp_mb();
8288 if (bp->port.pmf) {
8289 bnx2x_period_func(&bp->link_params, &bp->link_vars);
8290
8291 /* Re-queue task in 1 sec */
8292 queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ);
8293 }
8294
8295 bnx2x_release_phy_lock(bp);
8296period_task_exit:
8297 return;
8298}
8299
a2fbb9ea
ET		 8300/*
8301 * Init service functions
8302 */
8303
8d96286a 8304static u32 bnx2x_get_pretend_reg(struct bnx2x *bp)
f2e0899f
DK		 8305{
8306 u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0;
8307 u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base;
8308 return base + (BP_ABS_FUNC(bp)) * stride;
f1ef27ef
EG		 8309}
8310
f2e0899f 8311static void bnx2x_undi_int_disable_e1h(struct bnx2x *bp)
f1ef27ef 8312{
f2e0899f 8313 u32 reg = bnx2x_get_pretend_reg(bp);
f1ef27ef
EG		 8314
8315 /* Flush all outstanding writes */
8316 mmiowb();
8317
8318 /* Pretend to be function 0 */
8319 REG_WR(bp, reg, 0);
f2e0899f 8320 REG_RD(bp, reg); /* Flush the GRC transaction (in the chip) */
f1ef27ef
EG		 8321
8322 /* From now we are in the "like-E1" mode */
8323 bnx2x_int_disable(bp);
8324
8325 /* Flush all outstanding writes */
8326 mmiowb();
8327
f2e0899f
DK		 8328 /* Restore the original function */
8329 REG_WR(bp, reg, BP_ABS_FUNC(bp));
8330 REG_RD(bp, reg);
f1ef27ef
EG		 8331}
8332
f2e0899f 8333static inline void bnx2x_undi_int_disable(struct bnx2x *bp)
f1ef27ef 8334{
f2e0899f 8335 if (CHIP_IS_E1(bp))
f1ef27ef 8336 bnx2x_int_disable(bp);
f2e0899f
DK		 8337 else
8338 bnx2x_undi_int_disable_e1h(bp);
f1ef27ef
EG		 8339}
8340
34f80b04
EG		 8341static void __devinit bnx2x_undi_unload(struct bnx2x *bp)
8342{
8343 u32 val;
8344
8345 /* Check if there is any driver already loaded */
8346 val = REG_RD(bp, MISC_REG_UNPREPARED);
8347 if (val == 0x1) {
8348 /* Check if it is the UNDI driver
8349 * UNDI driver initializes CID offset for normal bell to 0x7
8350 */
4a37fb66 8351 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_UNDI);
34f80b04
EG		 8352 val = REG_RD(bp, DORQ_REG_NORM_CID_OFST);
8353 if (val == 0x7) {
8354 u32 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
f2e0899f
DK		 8355 /* save our pf_num */
8356 int orig_pf_num = bp->pf_num;
619c5cb6
VZ		 8357 int port;
8358 u32 swap_en, swap_val, value;
34f80b04 8359
b4661739
EG		 8360 /* clear the UNDI indication */
8361 REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0);
8362
34f80b04
EG		 8363 BNX2X_DEV_INFO("UNDI is active! reset device\n");
8364
8365 /* try unload UNDI on port 0 */
f2e0899f 8366 bp->pf_num = 0;
da5a662a 8367 bp->fw_seq =
f2e0899f 8368 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) &
da5a662a 8369 DRV_MSG_SEQ_NUMBER_MASK);
a22f0788 8370 reset_code = bnx2x_fw_command(bp, reset_code, 0);
34f80b04
EG		 8371
8372 /* if UNDI is loaded on the other port */
8373 if (reset_code != FW_MSG_CODE_DRV_UNLOAD_COMMON) {
8374
da5a662a 8375 /* send "DONE" for previous unload */
a22f0788
YR		 8376 bnx2x_fw_command(bp,
8377 DRV_MSG_CODE_UNLOAD_DONE, 0);
da5a662a
VZ		 8378
8379 /* unload UNDI on port 1 */
f2e0899f 8380 bp->pf_num = 1;
da5a662a 8381 bp->fw_seq =
f2e0899f 8382 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) &
da5a662a
VZ		 8383 DRV_MSG_SEQ_NUMBER_MASK);
8384 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
8385
a22f0788 8386 bnx2x_fw_command(bp, reset_code, 0);
34f80b04
EG		 8387 }
8388
b4661739
EG		 8389 /* now it's safe to release the lock */
8390 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_UNDI);
8391
f2e0899f 8392 bnx2x_undi_int_disable(bp);
619c5cb6 8393 port = BP_PORT(bp);
da5a662a
VZ		 8394
8395 /* close input traffic and wait for it */
8396 /* Do not rcv packets to BRB */
619c5cb6
VZ		 8397 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_DRV_MASK :
8398 NIG_REG_LLH0_BRB1_DRV_MASK), 0x0);
da5a662a
VZ		 8399 /* Do not direct rcv packets that are not for MCP to
8400 * the BRB */
619c5cb6
VZ		 8401 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
8402 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
da5a662a 8403 /* clear AEU */
619c5cb6
VZ		 8404 REG_WR(bp, (port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
8405 MISC_REG_AEU_MASK_ATTN_FUNC_0), 0);
da5a662a
VZ		 8406 msleep(10);
8407
8408 /* save NIG port swap info */
8409 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
8410 swap_en = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
34f80b04
EG		 8411 /* reset device */
8412 REG_WR(bp,
8413 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
da5a662a 8414 0xd3ffffff);
619c5cb6
VZ		 8415
8416 value = 0x1400;
8417 if (CHIP_IS_E3(bp)) {
8418 value |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
8419 value |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
8420 }
8421
34f80b04
EG		 8422 REG_WR(bp,
8423 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
619c5cb6
VZ		 8424 value);
8425
da5a662a
VZ		 8426 /* take the NIG out of reset and restore swap values */
8427 REG_WR(bp,
8428 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
8429 MISC_REGISTERS_RESET_REG_1_RST_NIG);
8430 REG_WR(bp, NIG_REG_PORT_SWAP, swap_val);
8431 REG_WR(bp, NIG_REG_STRAP_OVERRIDE, swap_en);
8432
8433 /* send unload done to the MCP */
a22f0788 8434 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
da5a662a
VZ		 8435
8436 /* restore our func and fw_seq */
f2e0899f 8437 bp->pf_num = orig_pf_num;
da5a662a 8438 bp->fw_seq =
f2e0899f 8439 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) &
da5a662a 8440 DRV_MSG_SEQ_NUMBER_MASK);
b4661739
EG		 8441 } else
8442 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_UNDI);
34f80b04
EG		 8443 }
8444}
8445
8446static void __devinit bnx2x_get_common_hwinfo(struct bnx2x *bp)
8447{
8448 u32 val, val2, val3, val4, id;
72ce58c3 8449 u16 pmc;
34f80b04
EG		 8450
8451 /* Get the chip revision id and number. */
8452 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
8453 val = REG_RD(bp, MISC_REG_CHIP_NUM);
8454 id = ((val & 0xffff) << 16);
8455 val = REG_RD(bp, MISC_REG_CHIP_REV);
8456 id |= ((val & 0xf) << 12);
8457 val = REG_RD(bp, MISC_REG_CHIP_METAL);
8458 id |= ((val & 0xff) << 4);
5a40e08e 8459 val = REG_RD(bp, MISC_REG_BOND_ID);
34f80b04
EG		 8460 id |= (val & 0xf);
8461 bp->common.chip_id = id;
523224a3
DK		 8462
8463 /* Set doorbell size */
8464 bp->db_size = (1 << BNX2X_DB_SHIFT);
8465
619c5cb6 8466 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 8467 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
8468 if ((val & 1) == 0)
8469 val = REG_RD(bp, MISC_REG_PORT4MODE_EN);
8470 else
8471 val = (val >> 1) & 1;
8472 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" :
8473 "2_PORT_MODE");
8474 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE :
8475 CHIP_2_PORT_MODE;
8476
8477 if (CHIP_MODE_IS_4_PORT(bp))
8478 bp->pfid = (bp->pf_num >> 1); /* 0..3 */
8479 else
8480 bp->pfid = (bp->pf_num & 0x6); /* 0, 2, 4, 6 */
8481 } else {
8482 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */
8483 bp->pfid = bp->pf_num; /* 0..7 */
8484 }
8485
f2e0899f
DK		 8486 bp->link_params.chip_id = bp->common.chip_id;
8487 BNX2X_DEV_INFO("chip ID is 0x%x\n", id);
523224a3 8488
1c06328c
EG		 8489 val = (REG_RD(bp, 0x2874) & 0x55);
8490 if ((bp->common.chip_id & 0x1) ||
8491 (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) {
8492 bp->flags |= ONE_PORT_FLAG;
8493 BNX2X_DEV_INFO("single port device\n");
8494 }
8495
34f80b04 8496 val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);
754a2f52 8497 bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE <<
34f80b04
EG		 8498 (val & MCPR_NVM_CFG4_FLASH_SIZE));
8499 BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
8500 bp->common.flash_size, bp->common.flash_size);
8501
1b6e2ceb
DK		 8502 bnx2x_init_shmem(bp);
8503
619c5cb6
VZ		 8504
8505
f2e0899f
DK		 8506 bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ?
8507 MISC_REG_GENERIC_CR_1 :
8508 MISC_REG_GENERIC_CR_0));
1b6e2ceb 8509
34f80b04 8510 bp->link_params.shmem_base = bp->common.shmem_base;
a22f0788 8511 bp->link_params.shmem2_base = bp->common.shmem2_base;
2691d51d
EG		 8512 BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n",
8513 bp->common.shmem_base, bp->common.shmem2_base);
34f80b04 8514
f2e0899f 8515 if (!bp->common.shmem_base) {
34f80b04
EG		 8516 BNX2X_DEV_INFO("MCP not active\n");
8517 bp->flags |= NO_MCP_FLAG;
8518 return;
8519 }
8520
34f80b04 8521 bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
35b19ba5 8522 BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config);
34f80b04
EG		 8523
8524 bp->link_params.hw_led_mode = ((bp->common.hw_config &
8525 SHARED_HW_CFG_LED_MODE_MASK) >>
8526 SHARED_HW_CFG_LED_MODE_SHIFT);
8527
c2c8b03e
EG		 8528 bp->link_params.feature_config_flags = 0;
8529 val = SHMEM_RD(bp, dev_info.shared_feature_config.config);
8530 if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED)
8531 bp->link_params.feature_config_flags |=
8532 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
8533 else
8534 bp->link_params.feature_config_flags &=
8535 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
8536
34f80b04
EG		 8537 val = SHMEM_RD(bp, dev_info.bc_rev) >> 8;
8538 bp->common.bc_ver = val;
8539 BNX2X_DEV_INFO("bc_ver %X\n", val);
8540 if (val < BNX2X_BC_VER) {
8541 /* for now only warn
8542 * later we might need to enforce this */
f2e0899f
DK		 8543 BNX2X_ERR("This driver needs bc_ver %X but found %X, "
8544 "please upgrade BC\n", BNX2X_BC_VER, val);
34f80b04 8545 }
4d295db0 8546 bp->link_params.feature_config_flags |=
a22f0788 8547 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ?
f85582f8
DK		 8548 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0;
8549
a22f0788
YR		 8550 bp->link_params.feature_config_flags |=
8551 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ?
8552 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0;
72ce58c3 8553
85242eea
YR		 8554 bp->link_params.feature_config_flags |=
8555 (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ?
8556 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0;
8557
f9a3ebbe
DK		 8558 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_PMC, &pmc);
8559 bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG;
8560
72ce58c3 8561 BNX2X_DEV_INFO("%sWoL capable\n",
f5372251 8562 (bp->flags & NO_WOL_FLAG) ? "not " : "");
34f80b04
EG		 8563
8564 val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
8565 val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
8566 val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]);
8567 val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]);
8568
cdaa7cb8
VZ		 8569 dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n",
8570 val, val2, val3, val4);
34f80b04
EG		 8571}
8572
f2e0899f
DK		 8573#define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
8574#define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
8575
8576static void __devinit bnx2x_get_igu_cam_info(struct bnx2x *bp)
8577{
8578 int pfid = BP_FUNC(bp);
8579 int vn = BP_E1HVN(bp);
8580 int igu_sb_id;
8581 u32 val;
6383c0b3 8582 u8 fid, igu_sb_cnt = 0;
f2e0899f
DK		 8583
8584 bp->igu_base_sb = 0xff;
f2e0899f 8585 if (CHIP_INT_MODE_IS_BC(bp)) {
6383c0b3 8586 igu_sb_cnt = bp->igu_sb_cnt;
f2e0899f
DK		 8587 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) *
8588 FP_SB_MAX_E1x;
8589
8590 bp->igu_dsb_id = E1HVN_MAX * FP_SB_MAX_E1x +
8591 (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn);
8592
8593 return;
8594 }
8595
8596 /* IGU in normal mode - read CAM */
8597 for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE;
8598 igu_sb_id++) {
8599 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
8600 if (!(val & IGU_REG_MAPPING_MEMORY_VALID))
8601 continue;
8602 fid = IGU_FID(val);
8603 if ((fid & IGU_FID_ENCODE_IS_PF)) {
8604 if ((fid & IGU_FID_PF_NUM_MASK) != pfid)
8605 continue;
8606 if (IGU_VEC(val) == 0)
8607 /* default status block */
8608 bp->igu_dsb_id = igu_sb_id;
8609 else {
8610 if (bp->igu_base_sb == 0xff)
8611 bp->igu_base_sb = igu_sb_id;
6383c0b3 8612 igu_sb_cnt++;
f2e0899f
DK		 8613 }
8614 }
8615 }
619c5cb6 8616
6383c0b3
AE		 8617#ifdef CONFIG_PCI_MSI
8618 /*
8619 * It's expected that number of CAM entries for this functions is equal
8620 * to the number evaluated based on the MSI-X table size. We want a
8621 * harsh warning if these values are different!
619c5cb6 8622 */
6383c0b3
AE		 8623 WARN_ON(bp->igu_sb_cnt != igu_sb_cnt);
8624#endif
619c5cb6 8625
6383c0b3 8626 if (igu_sb_cnt == 0)
f2e0899f
DK		 8627 BNX2X_ERR("CAM configuration error\n");
8628}
8629
34f80b04
EG		 8630static void __devinit bnx2x_link_settings_supported(struct bnx2x *bp,
8631 u32 switch_cfg)
a2fbb9ea 8632{
a22f0788
YR		 8633 int cfg_size = 0, idx, port = BP_PORT(bp);
8634
8635 /* Aggregation of supported attributes of all external phys */
8636 bp->port.supported[0] = 0;
8637 bp->port.supported[1] = 0;
b7737c9b
YR		 8638 switch (bp->link_params.num_phys) {
8639 case 1:
a22f0788
YR		 8640 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported;
8641 cfg_size = 1;
8642 break;
b7737c9b 8643 case 2:
a22f0788
YR		 8644 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported;
8645 cfg_size = 1;
8646 break;
8647 case 3:
8648 if (bp->link_params.multi_phy_config &
8649 PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
8650 bp->port.supported[1] =
8651 bp->link_params.phy[EXT_PHY1].supported;
8652 bp->port.supported[0] =
8653 bp->link_params.phy[EXT_PHY2].supported;
8654 } else {
8655 bp->port.supported[0] =
8656 bp->link_params.phy[EXT_PHY1].supported;
8657 bp->port.supported[1] =
8658 bp->link_params.phy[EXT_PHY2].supported;
8659 }
8660 cfg_size = 2;
8661 break;
b7737c9b 8662 }
a2fbb9ea 8663
a22f0788 8664 if (!(bp->port.supported[0] || bp->port.supported[1])) {
b7737c9b 8665 BNX2X_ERR("NVRAM config error. BAD phy config."
a22f0788 8666 "PHY1 config 0x%x, PHY2 config 0x%x\n",
b7737c9b 8667 SHMEM_RD(bp,
a22f0788
YR		 8668 dev_info.port_hw_config[port].external_phy_config),
8669 SHMEM_RD(bp,
8670 dev_info.port_hw_config[port].external_phy_config2));
a2fbb9ea 8671 return;
f85582f8 8672 }
a2fbb9ea 8673
619c5cb6
VZ		 8674 if (CHIP_IS_E3(bp))
8675 bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR);
8676 else {
8677 switch (switch_cfg) {
8678 case SWITCH_CFG_1G:
8679 bp->port.phy_addr = REG_RD(
8680 bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10);
8681 break;
8682 case SWITCH_CFG_10G:
8683 bp->port.phy_addr = REG_RD(
8684 bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18);
8685 break;
8686 default:
8687 BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
8688 bp->port.link_config[0]);
8689 return;
8690 }
a2fbb9ea 8691 }
619c5cb6 8692 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
a22f0788
YR		 8693 /* mask what we support according to speed_cap_mask per configuration */
8694 for (idx = 0; idx < cfg_size; idx++) {
8695 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 8696 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF))
a22f0788 8697 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half;
a2fbb9ea 8698
a22f0788 8699 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 8700 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL))
a22f0788 8701 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full;
a2fbb9ea 8702
a22f0788 8703 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 8704 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))
a22f0788 8705 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half;
a2fbb9ea 8706
a22f0788 8707 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 8708 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL))
a22f0788 8709 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full;
a2fbb9ea 8710
a22f0788 8711 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 8712 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))
a22f0788 8713 bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half |
f85582f8 8714 SUPPORTED_1000baseT_Full);
a2fbb9ea 8715
a22f0788 8716 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 8717 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
a22f0788 8718 bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full;
a2fbb9ea 8719
a22f0788 8720 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 8721 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G))
a22f0788
YR		 8722 bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full;
8723
8724 }
a2fbb9ea 8725
a22f0788
YR		 8726 BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0],
8727 bp->port.supported[1]);
a2fbb9ea
ET		 8728}
8729
34f80b04 8730static void __devinit bnx2x_link_settings_requested(struct bnx2x *bp)
a2fbb9ea 8731{
a22f0788
YR		 8732 u32 link_config, idx, cfg_size = 0;
8733 bp->port.advertising[0] = 0;
8734 bp->port.advertising[1] = 0;
8735 switch (bp->link_params.num_phys) {
8736 case 1:
8737 case 2:
8738 cfg_size = 1;
8739 break;
8740 case 3:
8741 cfg_size = 2;
8742 break;
8743 }
8744 for (idx = 0; idx < cfg_size; idx++) {
8745 bp->link_params.req_duplex[idx] = DUPLEX_FULL;
8746 link_config = bp->port.link_config[idx];
8747 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
f85582f8 8748 case PORT_FEATURE_LINK_SPEED_AUTO:
a22f0788
YR		 8749 if (bp->port.supported[idx] & SUPPORTED_Autoneg) {
8750 bp->link_params.req_line_speed[idx] =
8751 SPEED_AUTO_NEG;
8752 bp->port.advertising[idx] |=
8753 bp->port.supported[idx];
f85582f8
DK		 8754 } else {
8755 /* force 10G, no AN */
a22f0788
YR		 8756 bp->link_params.req_line_speed[idx] =
8757 SPEED_10000;
8758 bp->port.advertising[idx] |=
8759 (ADVERTISED_10000baseT_Full |
f85582f8 8760 ADVERTISED_FIBRE);
a22f0788 8761 continue;
f85582f8
DK		 8762 }
8763 break;
a2fbb9ea 8764
f85582f8 8765 case PORT_FEATURE_LINK_SPEED_10M_FULL:
a22f0788
YR		 8766 if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) {
8767 bp->link_params.req_line_speed[idx] =
8768 SPEED_10;
8769 bp->port.advertising[idx] |=
8770 (ADVERTISED_10baseT_Full |
f85582f8
DK		 8771 ADVERTISED_TP);
8772 } else {
754a2f52 8773 BNX2X_ERR("NVRAM config error. "
f85582f8
DK		 8774 "Invalid link_config 0x%x"
8775 " speed_cap_mask 0x%x\n",
8776 link_config,
a22f0788 8777 bp->link_params.speed_cap_mask[idx]);
f85582f8
DK		 8778 return;
8779 }
8780 break;
a2fbb9ea 8781
f85582f8 8782 case PORT_FEATURE_LINK_SPEED_10M_HALF:
a22f0788
YR		 8783 if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) {
8784 bp->link_params.req_line_speed[idx] =
8785 SPEED_10;
8786 bp->link_params.req_duplex[idx] =
8787 DUPLEX_HALF;
8788 bp->port.advertising[idx] |=
8789 (ADVERTISED_10baseT_Half |
f85582f8
DK		 8790 ADVERTISED_TP);
8791 } else {
754a2f52 8792 BNX2X_ERR("NVRAM config error. "
f85582f8
DK		 8793 "Invalid link_config 0x%x"
8794 " speed_cap_mask 0x%x\n",
8795 link_config,
8796 bp->link_params.speed_cap_mask[idx]);
8797 return;
8798 }
8799 break;
a2fbb9ea 8800
f85582f8
DK		 8801 case PORT_FEATURE_LINK_SPEED_100M_FULL:
8802 if (bp->port.supported[idx] &
8803 SUPPORTED_100baseT_Full) {
a22f0788
YR		 8804 bp->link_params.req_line_speed[idx] =
8805 SPEED_100;
8806 bp->port.advertising[idx] |=
8807 (ADVERTISED_100baseT_Full |
f85582f8
DK		 8808 ADVERTISED_TP);
8809 } else {
754a2f52 8810 BNX2X_ERR("NVRAM config error. "
f85582f8
DK		 8811 "Invalid link_config 0x%x"
8812 " speed_cap_mask 0x%x\n",
8813 link_config,
8814 bp->link_params.speed_cap_mask[idx]);
8815 return;
8816 }
8817 break;
a2fbb9ea 8818
f85582f8
DK		 8819 case PORT_FEATURE_LINK_SPEED_100M_HALF:
8820 if (bp->port.supported[idx] &
8821 SUPPORTED_100baseT_Half) {
8822 bp->link_params.req_line_speed[idx] =
8823 SPEED_100;
8824 bp->link_params.req_duplex[idx] =
8825 DUPLEX_HALF;
a22f0788
YR		 8826 bp->port.advertising[idx] |=
8827 (ADVERTISED_100baseT_Half |
f85582f8
DK		 8828 ADVERTISED_TP);
8829 } else {
754a2f52 8830 BNX2X_ERR("NVRAM config error. "
cdaa7cb8
VZ		 8831 "Invalid link_config 0x%x"
8832 " speed_cap_mask 0x%x\n",
a22f0788
YR		 8833 link_config,
8834 bp->link_params.speed_cap_mask[idx]);
f85582f8
DK		 8835 return;
8836 }
8837 break;
a2fbb9ea 8838
f85582f8 8839 case PORT_FEATURE_LINK_SPEED_1G:
a22f0788
YR		 8840 if (bp->port.supported[idx] &
8841 SUPPORTED_1000baseT_Full) {
8842 bp->link_params.req_line_speed[idx] =
8843 SPEED_1000;
8844 bp->port.advertising[idx] |=
8845 (ADVERTISED_1000baseT_Full |
f85582f8
DK		 8846 ADVERTISED_TP);
8847 } else {
754a2f52 8848 BNX2X_ERR("NVRAM config error. "
cdaa7cb8
VZ		 8849 "Invalid link_config 0x%x"
8850 " speed_cap_mask 0x%x\n",
a22f0788
YR		 8851 link_config,
8852 bp->link_params.speed_cap_mask[idx]);
f85582f8
DK		 8853 return;
8854 }
8855 break;
a2fbb9ea 8856
f85582f8 8857 case PORT_FEATURE_LINK_SPEED_2_5G:
a22f0788
YR		 8858 if (bp->port.supported[idx] &
8859 SUPPORTED_2500baseX_Full) {
8860 bp->link_params.req_line_speed[idx] =
8861 SPEED_2500;
8862 bp->port.advertising[idx] |=
8863 (ADVERTISED_2500baseX_Full |
34f80b04 8864 ADVERTISED_TP);
f85582f8 8865 } else {
754a2f52 8866 BNX2X_ERR("NVRAM config error. "
cdaa7cb8
VZ		 8867 "Invalid link_config 0x%x"
8868 " speed_cap_mask 0x%x\n",
a22f0788 8869 link_config,
f85582f8
DK		 8870 bp->link_params.speed_cap_mask[idx]);
8871 return;
8872 }
8873 break;
a2fbb9ea 8874
f85582f8 8875 case PORT_FEATURE_LINK_SPEED_10G_CX4:
a22f0788
YR		 8876 if (bp->port.supported[idx] &
8877 SUPPORTED_10000baseT_Full) {
8878 bp->link_params.req_line_speed[idx] =
8879 SPEED_10000;
8880 bp->port.advertising[idx] |=
8881 (ADVERTISED_10000baseT_Full |
34f80b04 8882 ADVERTISED_FIBRE);
f85582f8 8883 } else {
754a2f52 8884 BNX2X_ERR("NVRAM config error. "
cdaa7cb8
VZ		 8885 "Invalid link_config 0x%x"
8886 " speed_cap_mask 0x%x\n",
a22f0788 8887 link_config,
f85582f8
DK		 8888 bp->link_params.speed_cap_mask[idx]);
8889 return;
8890 }
8891 break;
3c9ada22
YR		 8892 case PORT_FEATURE_LINK_SPEED_20G:
8893 bp->link_params.req_line_speed[idx] = SPEED_20000;
a2fbb9ea 8894
3c9ada22 8895 break;
f85582f8 8896 default:
754a2f52
DK		 8897 BNX2X_ERR("NVRAM config error. "
8898 "BAD link speed link_config 0x%x\n",
8899 link_config);
f85582f8
DK		 8900 bp->link_params.req_line_speed[idx] =
8901 SPEED_AUTO_NEG;
8902 bp->port.advertising[idx] =
8903 bp->port.supported[idx];
8904 break;
8905 }
a2fbb9ea 8906
a22f0788 8907 bp->link_params.req_flow_ctrl[idx] = (link_config &
34f80b04 8908 PORT_FEATURE_FLOW_CONTROL_MASK);
a22f0788
YR		 8909 if ((bp->link_params.req_flow_ctrl[idx] ==
8910 BNX2X_FLOW_CTRL_AUTO) &&
8911 !(bp->port.supported[idx] & SUPPORTED_Autoneg)) {
8912 bp->link_params.req_flow_ctrl[idx] =
8913 BNX2X_FLOW_CTRL_NONE;
8914 }
a2fbb9ea 8915
a22f0788
YR		 8916 BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl"
8917 " 0x%x advertising 0x%x\n",
8918 bp->link_params.req_line_speed[idx],
8919 bp->link_params.req_duplex[idx],
8920 bp->link_params.req_flow_ctrl[idx],
8921 bp->port.advertising[idx]);
8922 }
a2fbb9ea
ET		 8923}
8924
e665bfda
MC		 8925static void __devinit bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi)
8926{
8927 mac_hi = cpu_to_be16(mac_hi);
8928 mac_lo = cpu_to_be32(mac_lo);
8929 memcpy(mac_buf, &mac_hi, sizeof(mac_hi));
8930 memcpy(mac_buf + sizeof(mac_hi), &mac_lo, sizeof(mac_lo));
8931}
8932
34f80b04 8933static void __devinit bnx2x_get_port_hwinfo(struct bnx2x *bp)
a2fbb9ea 8934{
34f80b04 8935 int port = BP_PORT(bp);
589abe3a 8936 u32 config;
6f38ad93 8937 u32 ext_phy_type, ext_phy_config;
a2fbb9ea 8938
c18487ee 8939 bp->link_params.bp = bp;
34f80b04 8940 bp->link_params.port = port;
c18487ee 8941
c18487ee 8942 bp->link_params.lane_config =
a2fbb9ea 8943 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
4d295db0 8944
a22f0788 8945 bp->link_params.speed_cap_mask[0] =
a2fbb9ea
ET		 8946 SHMEM_RD(bp,
8947 dev_info.port_hw_config[port].speed_capability_mask);
a22f0788
YR		 8948 bp->link_params.speed_cap_mask[1] =
8949 SHMEM_RD(bp,
8950 dev_info.port_hw_config[port].speed_capability_mask2);
8951 bp->port.link_config[0] =
a2fbb9ea
ET		 8952 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
8953
a22f0788
YR		 8954 bp->port.link_config[1] =
8955 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2);
c2c8b03e 8956
a22f0788
YR		 8957 bp->link_params.multi_phy_config =
8958 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config);
3ce2c3f9
EG		 8959 /* If the device is capable of WoL, set the default state according
8960 * to the HW
8961 */
4d295db0 8962 config = SHMEM_RD(bp, dev_info.port_feature_config[port].config);
3ce2c3f9
EG		 8963 bp->wol = (!(bp->flags & NO_WOL_FLAG) &&
8964 (config & PORT_FEATURE_WOL_ENABLED));
8965
f85582f8 8966 BNX2X_DEV_INFO("lane_config 0x%08x "
a22f0788 8967 "speed_cap_mask0 0x%08x link_config0 0x%08x\n",
c18487ee 8968 bp->link_params.lane_config,
a22f0788
YR		 8969 bp->link_params.speed_cap_mask[0],
8970 bp->port.link_config[0]);
a2fbb9ea 8971
a22f0788 8972 bp->link_params.switch_cfg = (bp->port.link_config[0] &
f85582f8 8973 PORT_FEATURE_CONNECTED_SWITCH_MASK);
b7737c9b 8974 bnx2x_phy_probe(&bp->link_params);
c18487ee 8975 bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg);
a2fbb9ea
ET		 8976
8977 bnx2x_link_settings_requested(bp);
8978
01cd4528
EG		 8979 /*
8980 * If connected directly, work with the internal PHY, otherwise, work
8981 * with the external PHY
8982 */
b7737c9b
YR		 8983 ext_phy_config =
8984 SHMEM_RD(bp,
8985 dev_info.port_hw_config[port].external_phy_config);
8986 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
01cd4528 8987 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
b7737c9b 8988 bp->mdio.prtad = bp->port.phy_addr;
01cd4528
EG		 8989
8990 else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
8991 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
8992 bp->mdio.prtad =
b7737c9b 8993 XGXS_EXT_PHY_ADDR(ext_phy_config);
5866df6d
YR		 8994
8995 /*
8996 * Check if hw lock is required to access MDC/MDIO bus to the PHY(s)
8997 * In MF mode, it is set to cover self test cases
8998 */
8999 if (IS_MF(bp))
9000 bp->port.need_hw_lock = 1;
9001 else
9002 bp->port.need_hw_lock = bnx2x_hw_lock_required(bp,
9003 bp->common.shmem_base,
9004 bp->common.shmem2_base);
0793f83f 9005}
01cd4528 9006
2ba45142
VZ		 9007#ifdef BCM_CNIC
9008static void __devinit bnx2x_get_cnic_info(struct bnx2x *bp)
9009{
9010 u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
9011 drv_lic_key[BP_PORT(bp)].max_iscsi_conn);
9012 u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
9013 drv_lic_key[BP_PORT(bp)].max_fcoe_conn);
9014
9015 /* Get the number of maximum allowed iSCSI and FCoE connections */
9016 bp->cnic_eth_dev.max_iscsi_conn =
9017 (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >>
9018 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT;
9019
9020 bp->cnic_eth_dev.max_fcoe_conn =
9021 (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >>
9022 BNX2X_MAX_FCOE_INIT_CONN_SHIFT;
9023
9024 BNX2X_DEV_INFO("max_iscsi_conn 0x%x max_fcoe_conn 0x%x\n",
9025 bp->cnic_eth_dev.max_iscsi_conn,
9026 bp->cnic_eth_dev.max_fcoe_conn);
9027
9028 /* If mamimum allowed number of connections is zero -
9029 * disable the feature.
9030 */
9031 if (!bp->cnic_eth_dev.max_iscsi_conn)
9032 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
9033
9034 if (!bp->cnic_eth_dev.max_fcoe_conn)
9035 bp->flags |= NO_FCOE_FLAG;
9036}
9037#endif
9038
0793f83f
DK		 9039static void __devinit bnx2x_get_mac_hwinfo(struct bnx2x *bp)
9040{
9041 u32 val, val2;
9042 int func = BP_ABS_FUNC(bp);
9043 int port = BP_PORT(bp);
2ba45142
VZ		 9044#ifdef BCM_CNIC
9045 u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac;
9046 u8 *fip_mac = bp->fip_mac;
9047#endif
0793f83f 9048
619c5cb6
VZ		 9049 /* Zero primary MAC configuration */
9050 memset(bp->dev->dev_addr, 0, ETH_ALEN);
9051
0793f83f
DK		 9052 if (BP_NOMCP(bp)) {
9053 BNX2X_ERROR("warning: random MAC workaround active\n");
9054 random_ether_addr(bp->dev->dev_addr);
9055 } else if (IS_MF(bp)) {
9056 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
9057 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower);
9058 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) &&
9059 (val != FUNC_MF_CFG_LOWERMAC_DEFAULT))
9060 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
37b091ba
MC		 9061
9062#ifdef BCM_CNIC
2ba45142
VZ		 9063 /* iSCSI and FCoE NPAR MACs: if there is no either iSCSI or
9064 * FCoE MAC then the appropriate feature should be disabled.
9065 */
0793f83f
DK		 9066 if (IS_MF_SI(bp)) {
9067 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
9068 if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
9069 val2 = MF_CFG_RD(bp, func_ext_config[func].
9070 iscsi_mac_addr_upper);
9071 val = MF_CFG_RD(bp, func_ext_config[func].
9072 iscsi_mac_addr_lower);
2ba45142 9073 bnx2x_set_mac_buf(iscsi_mac, val, val2);
619c5cb6
VZ		 9074 BNX2X_DEV_INFO("Read iSCSI MAC: "
9075 BNX2X_MAC_FMT"\n",
9076 BNX2X_MAC_PRN_LIST(iscsi_mac));
2ba45142
VZ		 9077 } else
9078 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
9079
9080 if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
9081 val2 = MF_CFG_RD(bp, func_ext_config[func].
9082 fcoe_mac_addr_upper);
9083 val = MF_CFG_RD(bp, func_ext_config[func].
9084 fcoe_mac_addr_lower);
2ba45142 9085 bnx2x_set_mac_buf(fip_mac, val, val2);
619c5cb6
VZ		 9086 BNX2X_DEV_INFO("Read FCoE L2 MAC to "
9087 BNX2X_MAC_FMT"\n",
9088 BNX2X_MAC_PRN_LIST(fip_mac));
2ba45142 9089
2ba45142
VZ		 9090 } else
9091 bp->flags |= NO_FCOE_FLAG;
0793f83f 9092 }
37b091ba 9093#endif
0793f83f
DK		 9094 } else {
9095 /* in SF read MACs from port configuration */
9096 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
9097 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
9098 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
9099
9100#ifdef BCM_CNIC
9101 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
9102 iscsi_mac_upper);
9103 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
9104 iscsi_mac_lower);
2ba45142 9105 bnx2x_set_mac_buf(iscsi_mac, val, val2);
0793f83f
DK		 9106#endif
9107 }
9108
9109 memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN);
9110 memcpy(bp->dev->perm_addr, bp->dev->dev_addr, ETH_ALEN);
9111
ec6ba945 9112#ifdef BCM_CNIC
2ba45142 9113 /* Set the FCoE MAC in modes other then MF_SI */
ec6ba945
VZ		 9114 if (!CHIP_IS_E1x(bp)) {
9115 if (IS_MF_SD(bp))
2ba45142
VZ		 9116 memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN);
9117 else if (!IS_MF(bp))
9118 memcpy(fip_mac, iscsi_mac, ETH_ALEN);
ec6ba945 9119 }
426b9241
DK		 9120
9121 /* Disable iSCSI if MAC configuration is
9122 * invalid.
9123 */
9124 if (!is_valid_ether_addr(iscsi_mac)) {
9125 bp->flags |= NO_ISCSI_FLAG;
9126 memset(iscsi_mac, 0, ETH_ALEN);
9127 }
9128
9129 /* Disable FCoE if MAC configuration is
9130 * invalid.
9131 */
9132 if (!is_valid_ether_addr(fip_mac)) {
9133 bp->flags |= NO_FCOE_FLAG;
9134 memset(bp->fip_mac, 0, ETH_ALEN);
9135 }
ec6ba945 9136#endif
619c5cb6
VZ		 9137
9138 if (!is_valid_ether_addr(bp->dev->dev_addr))
9139 dev_err(&bp->pdev->dev,
9140 "bad Ethernet MAC address configuration: "
9141 BNX2X_MAC_FMT", change it manually before bringing up "
9142 "the appropriate network interface\n",
9143 BNX2X_MAC_PRN_LIST(bp->dev->dev_addr));
34f80b04
EG		 9144}
9145
9146static int __devinit bnx2x_get_hwinfo(struct bnx2x *bp)
9147{
0793f83f 9148 int /*abs*/func = BP_ABS_FUNC(bp);
b8ee8328 9149 int vn;
0793f83f 9150 u32 val = 0;
34f80b04 9151 int rc = 0;
a2fbb9ea 9152
34f80b04 9153 bnx2x_get_common_hwinfo(bp);
a2fbb9ea 9154
6383c0b3
AE		 9155 /*
9156 * initialize IGU parameters
9157 */
f2e0899f
DK		 9158 if (CHIP_IS_E1x(bp)) {
9159 bp->common.int_block = INT_BLOCK_HC;
9160
9161 bp->igu_dsb_id = DEF_SB_IGU_ID;
9162 bp->igu_base_sb = 0;
f2e0899f
DK		 9163 } else {
9164 bp->common.int_block = INT_BLOCK_IGU;
9165 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
619c5cb6
VZ		 9166
9167 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
9168 int tout = 5000;
9169
9170 BNX2X_DEV_INFO("FORCING Normal Mode\n");
9171
9172 val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
9173 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val);
9174 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f);
9175
9176 while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
9177 tout--;
9178 usleep_range(1000, 1000);
9179 }
9180
9181 if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
9182 dev_err(&bp->pdev->dev,
9183 "FORCING Normal Mode failed!!!\n");
9184 return -EPERM;
9185 }
9186 }
9187
f2e0899f 9188 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
619c5cb6 9189 BNX2X_DEV_INFO("IGU Backward Compatible Mode\n");
f2e0899f
DK		 9190 bp->common.int_block |= INT_BLOCK_MODE_BW_COMP;
9191 } else
619c5cb6 9192 BNX2X_DEV_INFO("IGU Normal Mode\n");
523224a3 9193
f2e0899f
DK		 9194 bnx2x_get_igu_cam_info(bp);
9195
9196 }
619c5cb6
VZ		 9197
9198 /*
9199 * set base FW non-default (fast path) status block id, this value is
9200 * used to initialize the fw_sb_id saved on the fp/queue structure to
9201 * determine the id used by the FW.
9202 */
9203 if (CHIP_IS_E1x(bp))
9204 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp);
9205 else /*
9206 * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of
9207 * the same queue are indicated on the same IGU SB). So we prefer
9208 * FW and IGU SBs to be the same value.
9209 */
9210 bp->base_fw_ndsb = bp->igu_base_sb;
9211
9212 BNX2X_DEV_INFO("igu_dsb_id %d igu_base_sb %d igu_sb_cnt %d\n"
9213 "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb,
9214 bp->igu_sb_cnt, bp->base_fw_ndsb);
f2e0899f
DK		 9215
9216 /*
9217 * Initialize MF configuration
9218 */
523224a3 9219
fb3bff17
DK		 9220 bp->mf_ov = 0;
9221 bp->mf_mode = 0;
f2e0899f 9222 vn = BP_E1HVN(bp);
0793f83f 9223
f2e0899f 9224 if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) {
619c5cb6
VZ		 9225 BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n",
9226 bp->common.shmem2_base, SHMEM2_RD(bp, size),
9227 (u32)offsetof(struct shmem2_region, mf_cfg_addr));
9228
f2e0899f
DK		 9229 if (SHMEM2_HAS(bp, mf_cfg_addr))
9230 bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr);
9231 else
9232 bp->common.mf_cfg_base = bp->common.shmem_base +
523224a3
DK		 9233 offsetof(struct shmem_region, func_mb) +
9234 E1H_FUNC_MAX * sizeof(struct drv_func_mb);
0793f83f
DK		 9235 /*
9236 * get mf configuration:
25985edc 9237 * 1. existence of MF configuration
0793f83f
DK		 9238 * 2. MAC address must be legal (check only upper bytes)
9239 * for Switch-Independent mode;
9240 * OVLAN must be legal for Switch-Dependent mode
9241 * 3. SF_MODE configures specific MF mode
9242 */
9243 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
9244 /* get mf configuration */
9245 val = SHMEM_RD(bp,
9246 dev_info.shared_feature_config.config);
9247 val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK;
9248
9249 switch (val) {
9250 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
9251 val = MF_CFG_RD(bp, func_mf_config[func].
9252 mac_upper);
9253 /* check for legal mac (upper bytes)*/
9254 if (val != 0xffff) {
9255 bp->mf_mode = MULTI_FUNCTION_SI;
9256 bp->mf_config[vn] = MF_CFG_RD(bp,
9257 func_mf_config[func].config);
9258 } else
619c5cb6
VZ		 9259 BNX2X_DEV_INFO("illegal MAC address "
9260 "for SI\n");
0793f83f
DK		 9261 break;
9262 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
9263 /* get OV configuration */
9264 val = MF_CFG_RD(bp,
9265 func_mf_config[FUNC_0].e1hov_tag);
9266 val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
9267
9268 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
9269 bp->mf_mode = MULTI_FUNCTION_SD;
9270 bp->mf_config[vn] = MF_CFG_RD(bp,
9271 func_mf_config[func].config);
9272 } else
754a2f52 9273 BNX2X_DEV_INFO("illegal OV for SD\n");
0793f83f
DK		 9274 break;
9275 default:
9276 /* Unknown configuration: reset mf_config */
9277 bp->mf_config[vn] = 0;
754a2f52 9278 BNX2X_DEV_INFO("unkown MF mode 0x%x\n", val);
0793f83f
DK		 9279 }
9280 }
a2fbb9ea 9281
2691d51d 9282 BNX2X_DEV_INFO("%s function mode\n",
fb3bff17 9283 IS_MF(bp) ? "multi" : "single");
2691d51d 9284
0793f83f
DK		 9285 switch (bp->mf_mode) {
9286 case MULTI_FUNCTION_SD:
9287 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
9288 FUNC_MF_CFG_E1HOV_TAG_MASK;
2691d51d 9289 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
fb3bff17 9290 bp->mf_ov = val;
619c5cb6
VZ		 9291 bp->path_has_ovlan = true;
9292
9293 BNX2X_DEV_INFO("MF OV for func %d is %d "
9294 "(0x%04x)\n", func, bp->mf_ov,
9295 bp->mf_ov);
2691d51d 9296 } else {
619c5cb6
VZ		 9297 dev_err(&bp->pdev->dev,
9298 "No valid MF OV for func %d, "
9299 "aborting\n", func);
9300 return -EPERM;
34f80b04 9301 }
0793f83f
DK		 9302 break;
9303 case MULTI_FUNCTION_SI:
9304 BNX2X_DEV_INFO("func %d is in MF "
9305 "switch-independent mode\n", func);
9306 break;
9307 default:
9308 if (vn) {
619c5cb6
VZ		 9309 dev_err(&bp->pdev->dev,
9310 "VN %d is in a single function mode, "
9311 "aborting\n", vn);
9312 return -EPERM;
2691d51d 9313 }
0793f83f 9314 break;
34f80b04 9315 }
0793f83f 9316
619c5cb6
VZ		 9317 /* check if other port on the path needs ovlan:
9318 * Since MF configuration is shared between ports
9319 * Possible mixed modes are only
9320 * {SF, SI} {SF, SD} {SD, SF} {SI, SF}
9321 */
9322 if (CHIP_MODE_IS_4_PORT(bp) &&
9323 !bp->path_has_ovlan &&
9324 !IS_MF(bp) &&
9325 bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
9326 u8 other_port = !BP_PORT(bp);
9327 u8 other_func = BP_PATH(bp) + 2*other_port;
9328 val = MF_CFG_RD(bp,
9329 func_mf_config[other_func].e1hov_tag);
9330 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT)
9331 bp->path_has_ovlan = true;
9332 }
34f80b04 9333 }
a2fbb9ea 9334
f2e0899f
DK		 9335 /* adjust igu_sb_cnt to MF for E1x */
9336 if (CHIP_IS_E1x(bp) && IS_MF(bp))
523224a3
DK		 9337 bp->igu_sb_cnt /= E1HVN_MAX;
9338
619c5cb6
VZ		 9339 /* port info */
9340 bnx2x_get_port_hwinfo(bp);
f2e0899f 9341
34f80b04 9342 if (!BP_NOMCP(bp)) {
f2e0899f
DK		 9343 bp->fw_seq =
9344 (SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
9345 DRV_MSG_SEQ_NUMBER_MASK);
34f80b04
EG		 9346 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
9347 }
9348
0793f83f
DK		 9349 /* Get MAC addresses */
9350 bnx2x_get_mac_hwinfo(bp);
a2fbb9ea 9351
2ba45142
VZ		 9352#ifdef BCM_CNIC
9353 bnx2x_get_cnic_info(bp);
9354#endif
9355
619c5cb6
VZ		 9356 /* Get current FW pulse sequence */
9357 if (!BP_NOMCP(bp)) {
9358 int mb_idx = BP_FW_MB_IDX(bp);
9359
9360 bp->fw_drv_pulse_wr_seq =
9361 (SHMEM_RD(bp, func_mb[mb_idx].drv_pulse_mb) &
9362 DRV_PULSE_SEQ_MASK);
9363 BNX2X_DEV_INFO("drv_pulse 0x%x\n", bp->fw_drv_pulse_wr_seq);
9364 }
9365
34f80b04
EG		 9366 return rc;
9367}
9368
34f24c7f
VZ		 9369static void __devinit bnx2x_read_fwinfo(struct bnx2x *bp)
9370{
9371 int cnt, i, block_end, rodi;
9372 char vpd_data[BNX2X_VPD_LEN+1];
9373 char str_id_reg[VENDOR_ID_LEN+1];
9374 char str_id_cap[VENDOR_ID_LEN+1];
9375 u8 len;
9376
9377 cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_data);
9378 memset(bp->fw_ver, 0, sizeof(bp->fw_ver));
9379
9380 if (cnt < BNX2X_VPD_LEN)
9381 goto out_not_found;
9382
9383 i = pci_vpd_find_tag(vpd_data, 0, BNX2X_VPD_LEN,
9384 PCI_VPD_LRDT_RO_DATA);
9385 if (i < 0)
9386 goto out_not_found;
9387
9388
9389 block_end = i + PCI_VPD_LRDT_TAG_SIZE +
9390 pci_vpd_lrdt_size(&vpd_data[i]);
9391
9392 i += PCI_VPD_LRDT_TAG_SIZE;
9393
9394 if (block_end > BNX2X_VPD_LEN)
9395 goto out_not_found;
9396
9397 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
9398 PCI_VPD_RO_KEYWORD_MFR_ID);
9399 if (rodi < 0)
9400 goto out_not_found;
9401
9402 len = pci_vpd_info_field_size(&vpd_data[rodi]);
9403
9404 if (len != VENDOR_ID_LEN)
9405 goto out_not_found;
9406
9407 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
9408
9409 /* vendor specific info */
9410 snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL);
9411 snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL);
9412 if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) ||
9413 !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) {
9414
9415 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
9416 PCI_VPD_RO_KEYWORD_VENDOR0);
9417 if (rodi >= 0) {
9418 len = pci_vpd_info_field_size(&vpd_data[rodi]);
9419
9420 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
9421
9422 if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) {
9423 memcpy(bp->fw_ver, &vpd_data[rodi], len);
9424 bp->fw_ver[len] = ' ';
9425 }
9426 }
9427 return;
9428 }
9429out_not_found:
9430 return;
9431}
9432
619c5cb6
VZ		 9433static void __devinit bnx2x_set_modes_bitmap(struct bnx2x *bp)
9434{
9435 u32 flags = 0;
9436
9437 if (CHIP_REV_IS_FPGA(bp))
9438 SET_FLAGS(flags, MODE_FPGA);
9439 else if (CHIP_REV_IS_EMUL(bp))
9440 SET_FLAGS(flags, MODE_EMUL);
9441 else
9442 SET_FLAGS(flags, MODE_ASIC);
9443
9444 if (CHIP_MODE_IS_4_PORT(bp))
9445 SET_FLAGS(flags, MODE_PORT4);
9446 else
9447 SET_FLAGS(flags, MODE_PORT2);
9448
9449 if (CHIP_IS_E2(bp))
9450 SET_FLAGS(flags, MODE_E2);
9451 else if (CHIP_IS_E3(bp)) {
9452 SET_FLAGS(flags, MODE_E3);
9453 if (CHIP_REV(bp) == CHIP_REV_Ax)
9454 SET_FLAGS(flags, MODE_E3_A0);
6383c0b3
AE		 9455 else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/
9456 SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3);
619c5cb6
VZ		 9457 }
9458
9459 if (IS_MF(bp)) {
9460 SET_FLAGS(flags, MODE_MF);
9461 switch (bp->mf_mode) {
9462 case MULTI_FUNCTION_SD:
9463 SET_FLAGS(flags, MODE_MF_SD);
9464 break;
9465 case MULTI_FUNCTION_SI:
9466 SET_FLAGS(flags, MODE_MF_SI);
9467 break;
9468 }
9469 } else
9470 SET_FLAGS(flags, MODE_SF);
9471
9472#if defined(__LITTLE_ENDIAN)
9473 SET_FLAGS(flags, MODE_LITTLE_ENDIAN);
9474#else /*(__BIG_ENDIAN)*/
9475 SET_FLAGS(flags, MODE_BIG_ENDIAN);
9476#endif
9477 INIT_MODE_FLAGS(bp) = flags;
9478}
9479
34f80b04
EG		 9480static int __devinit bnx2x_init_bp(struct bnx2x *bp)
9481{
f2e0899f 9482 int func;
87942b46 9483 int timer_interval;
34f80b04
EG		 9484 int rc;
9485
34f80b04 9486 mutex_init(&bp->port.phy_mutex);
c4ff7cbf 9487 mutex_init(&bp->fw_mb_mutex);
bb7e95c8 9488 spin_lock_init(&bp->stats_lock);
993ac7b5
MC		 9489#ifdef BCM_CNIC
9490 mutex_init(&bp->cnic_mutex);
9491#endif
a2fbb9ea 9492
1cf167f2 9493 INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task);
7be08a72 9494 INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task);
3deb8167 9495 INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task);
34f80b04 9496 rc = bnx2x_get_hwinfo(bp);
619c5cb6
VZ		 9497 if (rc)
9498 return rc;
34f80b04 9499
619c5cb6
VZ		 9500 bnx2x_set_modes_bitmap(bp);
9501
9502 rc = bnx2x_alloc_mem_bp(bp);
9503 if (rc)
9504 return rc;
523224a3 9505
34f24c7f 9506 bnx2x_read_fwinfo(bp);
f2e0899f
DK		 9507
9508 func = BP_FUNC(bp);
9509
34f80b04
EG		 9510 /* need to reset chip if undi was active */
9511 if (!BP_NOMCP(bp))
9512 bnx2x_undi_unload(bp);
9513
9514 if (CHIP_REV_IS_FPGA(bp))
cdaa7cb8 9515 dev_err(&bp->pdev->dev, "FPGA detected\n");
34f80b04
EG		 9516
9517 if (BP_NOMCP(bp) && (func == 0))
cdaa7cb8
VZ		 9518 dev_err(&bp->pdev->dev, "MCP disabled, "
9519 "must load devices in order!\n");
34f80b04 9520
555f6c78 9521 bp->multi_mode = multi_mode;
555f6c78 9522
7a9b2557
VZ		 9523 /* Set TPA flags */
9524 if (disable_tpa) {
9525 bp->flags &= ~TPA_ENABLE_FLAG;
9526 bp->dev->features &= ~NETIF_F_LRO;
9527 } else {
9528 bp->flags |= TPA_ENABLE_FLAG;
9529 bp->dev->features |= NETIF_F_LRO;
9530 }
5d7cd496 9531 bp->disable_tpa = disable_tpa;
7a9b2557 9532
a18f5128
EG		 9533 if (CHIP_IS_E1(bp))
9534 bp->dropless_fc = 0;
9535 else
9536 bp->dropless_fc = dropless_fc;
9537
8d5726c4 9538 bp->mrrs = mrrs;
7a9b2557 9539
34f80b04 9540 bp->tx_ring_size = MAX_TX_AVAIL;
34f80b04 9541
7d323bfd 9542 /* make sure that the numbers are in the right granularity */
523224a3
DK		 9543 bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR;
9544 bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR;
34f80b04 9545
87942b46
EG		 9546 timer_interval = (CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ);
9547 bp->current_interval = (poll ? poll : timer_interval);
34f80b04
EG		 9548
9549 init_timer(&bp->timer);
9550 bp->timer.expires = jiffies + bp->current_interval;
9551 bp->timer.data = (unsigned long) bp;
9552 bp->timer.function = bnx2x_timer;
9553
785b9b1a 9554 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON);
e4901dde
VZ		 9555 bnx2x_dcbx_init_params(bp);
9556
619c5cb6
VZ		 9557#ifdef BCM_CNIC
9558 if (CHIP_IS_E1x(bp))
9559 bp->cnic_base_cl_id = FP_SB_MAX_E1x;
9560 else
9561 bp->cnic_base_cl_id = FP_SB_MAX_E2;
9562#endif
9563
6383c0b3
AE		 9564 /* multiple tx priority */
9565 if (CHIP_IS_E1x(bp))
9566 bp->max_cos = BNX2X_MULTI_TX_COS_E1X;
9567 if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp))
9568 bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0;
9569 if (CHIP_IS_E3B0(bp))
9570 bp->max_cos = BNX2X_MULTI_TX_COS_E3B0;
9571
34f80b04 9572 return rc;
a2fbb9ea
ET		 9573}
9574
a2fbb9ea 9575
de0c62db
DK		 9576/****************************************************************************
9577* General service functions
9578****************************************************************************/
a2fbb9ea 9579
619c5cb6
VZ		 9580/*
9581 * net_device service functions
9582 */
9583
bb2a0f7a 9584/* called with rtnl_lock */
a2fbb9ea
ET		 9585static int bnx2x_open(struct net_device *dev)
9586{
9587 struct bnx2x *bp = netdev_priv(dev);
c9ee9206
VZ		 9588 bool global = false;
9589 int other_engine = BP_PATH(bp) ? 0 : 1;
9590 u32 other_load_counter, load_counter;
a2fbb9ea 9591
6eccabb3
EG		 9592 netif_carrier_off(dev);
9593
a2fbb9ea
ET		 9594 bnx2x_set_power_state(bp, PCI_D0);
9595
c9ee9206
VZ		 9596 other_load_counter = bnx2x_get_load_cnt(bp, other_engine);
9597 load_counter = bnx2x_get_load_cnt(bp, BP_PATH(bp));
9598
9599 /*
9600 * If parity had happen during the unload, then attentions
9601 * and/or RECOVERY_IN_PROGRES may still be set. In this case we
9602 * want the first function loaded on the current engine to
9603 * complete the recovery.
9604 */
9605 if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) ||
9606 bnx2x_chk_parity_attn(bp, &global, true))
72fd0718 9607 do {
c9ee9206
VZ		 9608 /*
9609 * If there are attentions and they are in a global
9610 * blocks, set the GLOBAL_RESET bit regardless whether
9611 * it will be this function that will complete the
9612 * recovery or not.
72fd0718 9613 */
c9ee9206
VZ		 9614 if (global)
9615 bnx2x_set_reset_global(bp);
72fd0718 9616
c9ee9206
VZ		 9617 /*
9618 * Only the first function on the current engine should
9619 * try to recover in open. In case of attentions in
9620 * global blocks only the first in the chip should try
9621 * to recover.
72fd0718 9622 */
c9ee9206
VZ		 9623 if ((!load_counter &&
9624 (!global || !other_load_counter)) &&
9625 bnx2x_trylock_leader_lock(bp) &&
9626 !bnx2x_leader_reset(bp)) {
9627 netdev_info(bp->dev, "Recovered in open\n");
72fd0718
VZ		 9628 break;
9629 }
9630
c9ee9206 9631 /* recovery has failed... */
72fd0718 9632 bnx2x_set_power_state(bp, PCI_D3hot);
c9ee9206 9633 bp->recovery_state = BNX2X_RECOVERY_FAILED;
72fd0718 9634
c9ee9206 9635 netdev_err(bp->dev, "Recovery flow hasn't been properly"
72fd0718
VZ		 9636 " completed yet. Try again later. If u still see this"
9637 " message after a few retries then power cycle is"
c9ee9206 9638 " required.\n");
72fd0718
VZ		 9639
9640 return -EAGAIN;
9641 } while (0);
72fd0718
VZ		 9642
9643 bp->recovery_state = BNX2X_RECOVERY_DONE;
bb2a0f7a 9644 return bnx2x_nic_load(bp, LOAD_OPEN);
a2fbb9ea
ET		 9645}
9646
bb2a0f7a 9647/* called with rtnl_lock */
a2fbb9ea
ET		 9648static int bnx2x_close(struct net_device *dev)
9649{
a2fbb9ea
ET		 9650 struct bnx2x *bp = netdev_priv(dev);
9651
9652 /* Unload the driver, release IRQs */
bb2a0f7a 9653 bnx2x_nic_unload(bp, UNLOAD_CLOSE);
c9ee9206
VZ		 9654
9655 /* Power off */
d3dbfee0 9656 bnx2x_set_power_state(bp, PCI_D3hot);
a2fbb9ea
ET		 9657
9658 return 0;
9659}
9660
619c5cb6
VZ		 9661static inline int bnx2x_init_mcast_macs_list(struct bnx2x *bp,
9662 struct bnx2x_mcast_ramrod_params *p)
6e30dd4e 9663{
619c5cb6
VZ		 9664 int mc_count = netdev_mc_count(bp->dev);
9665 struct bnx2x_mcast_list_elem *mc_mac =
9666 kzalloc(sizeof(*mc_mac) * mc_count, GFP_ATOMIC);
9667 struct netdev_hw_addr *ha;
6e30dd4e 9668
619c5cb6
VZ		 9669 if (!mc_mac)
9670 return -ENOMEM;
6e30dd4e 9671
619c5cb6 9672 INIT_LIST_HEAD(&p->mcast_list);
6e30dd4e 9673
619c5cb6
VZ		 9674 netdev_for_each_mc_addr(ha, bp->dev) {
9675 mc_mac->mac = bnx2x_mc_addr(ha);
9676 list_add_tail(&mc_mac->link, &p->mcast_list);
9677 mc_mac++;
6e30dd4e 9678 }
619c5cb6
VZ		 9679
9680 p->mcast_list_len = mc_count;
9681
9682 return 0;
6e30dd4e
VZ		 9683}
9684
619c5cb6
VZ		 9685static inline void bnx2x_free_mcast_macs_list(
9686 struct bnx2x_mcast_ramrod_params *p)
9687{
9688 struct bnx2x_mcast_list_elem *mc_mac =
9689 list_first_entry(&p->mcast_list, struct bnx2x_mcast_list_elem,
9690 link);
9691
9692 WARN_ON(!mc_mac);
9693 kfree(mc_mac);
9694}
9695
9696/**
9697 * bnx2x_set_uc_list - configure a new unicast MACs list.
9698 *
9699 * @bp: driver handle
6e30dd4e 9700 *
619c5cb6 9701 * We will use zero (0) as a MAC type for these MACs.
6e30dd4e 9702 */
619c5cb6 9703static inline int bnx2x_set_uc_list(struct bnx2x *bp)
6e30dd4e 9704{
619c5cb6 9705 int rc;
6e30dd4e 9706 struct net_device *dev = bp->dev;
6e30dd4e 9707 struct netdev_hw_addr *ha;
619c5cb6
VZ		 9708 struct bnx2x_vlan_mac_obj *mac_obj = &bp->fp->mac_obj;
9709 unsigned long ramrod_flags = 0;
6e30dd4e 9710
619c5cb6
VZ		 9711 /* First schedule a cleanup up of old configuration */
9712 rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false);
9713 if (rc < 0) {
9714 BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc);
9715 return rc;
9716 }
6e30dd4e
VZ		 9717
9718 netdev_for_each_uc_addr(ha, dev) {
619c5cb6
VZ		 9719 rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true,
9720 BNX2X_UC_LIST_MAC, &ramrod_flags);
9721 if (rc < 0) {
9722 BNX2X_ERR("Failed to schedule ADD operations: %d\n",
9723 rc);
9724 return rc;
6e30dd4e
VZ		 9725 }
9726 }
9727
619c5cb6
VZ		 9728 /* Execute the pending commands */
9729 __set_bit(RAMROD_CONT, &ramrod_flags);
9730 return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */,
9731 BNX2X_UC_LIST_MAC, &ramrod_flags);
6e30dd4e
VZ		 9732}
9733
619c5cb6 9734static inline int bnx2x_set_mc_list(struct bnx2x *bp)
6e30dd4e 9735{
619c5cb6
VZ		 9736 struct net_device *dev = bp->dev;
9737 struct bnx2x_mcast_ramrod_params rparam = {0};
9738 int rc = 0;
6e30dd4e 9739
619c5cb6 9740 rparam.mcast_obj = &bp->mcast_obj;
6e30dd4e 9741
619c5cb6
VZ		 9742 /* first, clear all configured multicast MACs */
9743 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
9744 if (rc < 0) {
9745 BNX2X_ERR("Failed to clear multicast "
9746 "configuration: %d\n", rc);
9747 return rc;
9748 }
6e30dd4e 9749
619c5cb6
VZ		 9750 /* then, configure a new MACs list */
9751 if (netdev_mc_count(dev)) {
9752 rc = bnx2x_init_mcast_macs_list(bp, &rparam);
9753 if (rc) {
9754 BNX2X_ERR("Failed to create multicast MACs "
9755 "list: %d\n", rc);
9756 return rc;
9757 }
6e30dd4e 9758
619c5cb6
VZ		 9759 /* Now add the new MACs */
9760 rc = bnx2x_config_mcast(bp, &rparam,
9761 BNX2X_MCAST_CMD_ADD);
9762 if (rc < 0)
9763 BNX2X_ERR("Failed to set a new multicast "
9764 "configuration: %d\n", rc);
6e30dd4e 9765
619c5cb6
VZ		 9766 bnx2x_free_mcast_macs_list(&rparam);
9767 }
6e30dd4e 9768
619c5cb6 9769 return rc;
6e30dd4e
VZ		 9770}
9771
6e30dd4e 9772
619c5cb6 9773/* If bp->state is OPEN, should be called with netif_addr_lock_bh() */
9f6c9258 9774void bnx2x_set_rx_mode(struct net_device *dev)
34f80b04
EG		 9775{
9776 struct bnx2x *bp = netdev_priv(dev);
9777 u32 rx_mode = BNX2X_RX_MODE_NORMAL;
34f80b04
EG		 9778
9779 if (bp->state != BNX2X_STATE_OPEN) {
9780 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
9781 return;
9782 }
9783
619c5cb6 9784 DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags);
34f80b04
EG		 9785
9786 if (dev->flags & IFF_PROMISC)
9787 rx_mode = BNX2X_RX_MODE_PROMISC;
619c5cb6
VZ		 9788 else if ((dev->flags & IFF_ALLMULTI) ||
9789 ((netdev_mc_count(dev) > BNX2X_MAX_MULTICAST) &&
9790 CHIP_IS_E1(bp)))
34f80b04 9791 rx_mode = BNX2X_RX_MODE_ALLMULTI;
6e30dd4e
VZ		 9792 else {
9793 /* some multicasts */
619c5cb6 9794 if (bnx2x_set_mc_list(bp) < 0)
6e30dd4e 9795 rx_mode = BNX2X_RX_MODE_ALLMULTI;
34f80b04 9796
619c5cb6 9797 if (bnx2x_set_uc_list(bp) < 0)
6e30dd4e 9798 rx_mode = BNX2X_RX_MODE_PROMISC;
34f80b04
EG		 9799 }
9800
9801 bp->rx_mode = rx_mode;
619c5cb6
VZ		 9802
9803 /* Schedule the rx_mode command */
9804 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) {
9805 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
9806 return;
9807 }
9808
34f80b04
EG		 9809 bnx2x_set_storm_rx_mode(bp);
9810}
9811
c18487ee 9812/* called with rtnl_lock */
01cd4528
EG		 9813static int bnx2x_mdio_read(struct net_device *netdev, int prtad,
9814 int devad, u16 addr)
a2fbb9ea 9815{
01cd4528
EG		 9816 struct bnx2x *bp = netdev_priv(netdev);
9817 u16 value;
9818 int rc;
a2fbb9ea 9819
01cd4528
EG		 9820 DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n",
9821 prtad, devad, addr);
a2fbb9ea 9822
01cd4528
EG		 9823 /* The HW expects different devad if CL22 is used */
9824 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
c18487ee 9825
01cd4528 9826 bnx2x_acquire_phy_lock(bp);
e10bc84d 9827 rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value);
01cd4528
EG		 9828 bnx2x_release_phy_lock(bp);
9829 DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc);
a2fbb9ea 9830
01cd4528
EG		 9831 if (!rc)
9832 rc = value;
9833 return rc;
9834}
a2fbb9ea 9835
01cd4528
EG		 9836/* called with rtnl_lock */
9837static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad,
9838 u16 addr, u16 value)
9839{
9840 struct bnx2x *bp = netdev_priv(netdev);
01cd4528
EG		 9841 int rc;
9842
9843 DP(NETIF_MSG_LINK, "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x,"
9844 " value 0x%x\n", prtad, devad, addr, value);
9845
01cd4528
EG		 9846 /* The HW expects different devad if CL22 is used */
9847 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
a2fbb9ea 9848
01cd4528 9849 bnx2x_acquire_phy_lock(bp);
e10bc84d 9850 rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value);
01cd4528
EG		 9851 bnx2x_release_phy_lock(bp);
9852 return rc;
9853}
c18487ee 9854
01cd4528
EG		 9855/* called with rtnl_lock */
9856static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
9857{
9858 struct bnx2x *bp = netdev_priv(dev);
9859 struct mii_ioctl_data *mdio = if_mii(ifr);
a2fbb9ea 9860
01cd4528
EG		 9861 DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
9862 mdio->phy_id, mdio->reg_num, mdio->val_in);
a2fbb9ea 9863
01cd4528
EG		 9864 if (!netif_running(dev))
9865 return -EAGAIN;
9866
9867 return mdio_mii_ioctl(&bp->mdio, mdio, cmd);
a2fbb9ea
ET		 9868}
9869
257ddbda 9870#ifdef CONFIG_NET_POLL_CONTROLLER
a2fbb9ea
ET		 9871static void poll_bnx2x(struct net_device *dev)
9872{
9873 struct bnx2x *bp = netdev_priv(dev);
9874
9875 disable_irq(bp->pdev->irq);
9876 bnx2x_interrupt(bp->pdev->irq, dev);
9877 enable_irq(bp->pdev->irq);
9878}
9879#endif
9880
c64213cd
SH		 9881static const struct net_device_ops bnx2x_netdev_ops = {
9882 .ndo_open = bnx2x_open,
9883 .ndo_stop = bnx2x_close,
9884 .ndo_start_xmit = bnx2x_start_xmit,
8307fa3e 9885 .ndo_select_queue = bnx2x_select_queue,
6e30dd4e 9886 .ndo_set_rx_mode = bnx2x_set_rx_mode,
c64213cd
SH		 9887 .ndo_set_mac_address = bnx2x_change_mac_addr,
9888 .ndo_validate_addr = eth_validate_addr,
9889 .ndo_do_ioctl = bnx2x_ioctl,
9890 .ndo_change_mtu = bnx2x_change_mtu,
66371c44
MM		 9891 .ndo_fix_features = bnx2x_fix_features,
9892 .ndo_set_features = bnx2x_set_features,
c64213cd 9893 .ndo_tx_timeout = bnx2x_tx_timeout,
257ddbda 9894#ifdef CONFIG_NET_POLL_CONTROLLER
c64213cd
SH		 9895 .ndo_poll_controller = poll_bnx2x,
9896#endif
6383c0b3
AE		 9897 .ndo_setup_tc = bnx2x_setup_tc,
9898
c64213cd
SH		 9899};
9900
619c5cb6
VZ		 9901static inline int bnx2x_set_coherency_mask(struct bnx2x *bp)
9902{
9903 struct device *dev = &bp->pdev->dev;
9904
9905 if (dma_set_mask(dev, DMA_BIT_MASK(64)) == 0) {
9906 bp->flags |= USING_DAC_FLAG;
9907 if (dma_set_coherent_mask(dev, DMA_BIT_MASK(64)) != 0) {
9908 dev_err(dev, "dma_set_coherent_mask failed, "
9909 "aborting\n");
9910 return -EIO;
9911 }
9912 } else if (dma_set_mask(dev, DMA_BIT_MASK(32)) != 0) {
9913 dev_err(dev, "System does not support DMA, aborting\n");
9914 return -EIO;
9915 }
9916
9917 return 0;
9918}
9919
34f80b04 9920static int __devinit bnx2x_init_dev(struct pci_dev *pdev,
619c5cb6
VZ		 9921 struct net_device *dev,
9922 unsigned long board_type)
a2fbb9ea
ET		 9923{
9924 struct bnx2x *bp;
9925 int rc;
9926
9927 SET_NETDEV_DEV(dev, &pdev->dev);
9928 bp = netdev_priv(dev);
9929
34f80b04
EG		 9930 bp->dev = dev;
9931 bp->pdev = pdev;
a2fbb9ea 9932 bp->flags = 0;
f2e0899f 9933 bp->pf_num = PCI_FUNC(pdev->devfn);
a2fbb9ea
ET		 9934
9935 rc = pci_enable_device(pdev);
9936 if (rc) {
cdaa7cb8
VZ		 9937 dev_err(&bp->pdev->dev,
9938 "Cannot enable PCI device, aborting\n");
a2fbb9ea
ET		 9939 goto err_out;
9940 }
9941
9942 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
cdaa7cb8
VZ		 9943 dev_err(&bp->pdev->dev,
9944 "Cannot find PCI device base address, aborting\n");
a2fbb9ea
ET		 9945 rc = -ENODEV;
9946 goto err_out_disable;
9947 }
9948
9949 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
cdaa7cb8
VZ		 9950 dev_err(&bp->pdev->dev, "Cannot find second PCI device"
9951 " base address, aborting\n");
a2fbb9ea
ET		 9952 rc = -ENODEV;
9953 goto err_out_disable;
9954 }
9955
34f80b04
EG		 9956 if (atomic_read(&pdev->enable_cnt) == 1) {
9957 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
9958 if (rc) {
cdaa7cb8
VZ		 9959 dev_err(&bp->pdev->dev,
9960 "Cannot obtain PCI resources, aborting\n");
34f80b04
EG		 9961 goto err_out_disable;
9962 }
a2fbb9ea 9963
34f80b04
EG		 9964 pci_set_master(pdev);
9965 pci_save_state(pdev);
9966 }
a2fbb9ea
ET		 9967
9968 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
9969 if (bp->pm_cap == 0) {
cdaa7cb8
VZ		 9970 dev_err(&bp->pdev->dev,
9971 "Cannot find power management capability, aborting\n");
a2fbb9ea
ET		 9972 rc = -EIO;
9973 goto err_out_release;
9974 }
9975
77c98e6a
JM		 9976 if (!pci_is_pcie(pdev)) {
9977 dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n");
a2fbb9ea
ET		 9978 rc = -EIO;
9979 goto err_out_release;
9980 }
9981
619c5cb6
VZ		 9982 rc = bnx2x_set_coherency_mask(bp);
9983 if (rc)
a2fbb9ea 9984 goto err_out_release;
a2fbb9ea 9985
34f80b04
EG		 9986 dev->mem_start = pci_resource_start(pdev, 0);
9987 dev->base_addr = dev->mem_start;
9988 dev->mem_end = pci_resource_end(pdev, 0);
a2fbb9ea
ET		 9989
9990 dev->irq = pdev->irq;
9991
275f165f 9992 bp->regview = pci_ioremap_bar(pdev, 0);
a2fbb9ea 9993 if (!bp->regview) {
cdaa7cb8
VZ		 9994 dev_err(&bp->pdev->dev,
9995 "Cannot map register space, aborting\n");
a2fbb9ea
ET		 9996 rc = -ENOMEM;
9997 goto err_out_release;
9998 }
9999
a2fbb9ea
ET		 10000 bnx2x_set_power_state(bp, PCI_D0);
10001
34f80b04
EG		 10002 /* clean indirect addresses */
10003 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
10004 PCICFG_VENDOR_ID_OFFSET);
10005 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0 + BP_PORT(bp)*16, 0);
10006 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0 + BP_PORT(bp)*16, 0);
10007 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0 + BP_PORT(bp)*16, 0);
10008 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0 + BP_PORT(bp)*16, 0);
a2fbb9ea 10009
619c5cb6
VZ		 10010 /**
10011 * Enable internal target-read (in case we are probed after PF FLR).
10012 * Must be done prior to any BAR read access
10013 */
10014 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
10015
72fd0718
VZ		 10016 /* Reset the load counter */
10017 bnx2x_clear_load_cnt(bp);
10018
34f80b04 10019 dev->watchdog_timeo = TX_TIMEOUT;
a2fbb9ea 10020
c64213cd 10021 dev->netdev_ops = &bnx2x_netdev_ops;
de0c62db 10022 bnx2x_set_ethtool_ops(dev);
5316bc0b 10023
66371c44
MM		 10024 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
10025 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
10026 NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_HW_VLAN_TX;
10027
10028 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
10029 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA;
10030
10031 dev->features |= dev->hw_features | NETIF_F_HW_VLAN_RX;
5316bc0b 10032 if (bp->flags & USING_DAC_FLAG)
66371c44 10033 dev->features |= NETIF_F_HIGHDMA;
a2fbb9ea 10034
538dd2e3
MB		 10035 /* Add Loopback capability to the device */
10036 dev->hw_features |= NETIF_F_LOOPBACK;
10037
98507672 10038#ifdef BCM_DCBNL
785b9b1a
SR		 10039 dev->dcbnl_ops = &bnx2x_dcbnl_ops;
10040#endif
10041
01cd4528
EG		 10042 /* get_port_hwinfo() will set prtad and mmds properly */
10043 bp->mdio.prtad = MDIO_PRTAD_NONE;
10044 bp->mdio.mmds = 0;
10045 bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
10046 bp->mdio.dev = dev;
10047 bp->mdio.mdio_read = bnx2x_mdio_read;
10048 bp->mdio.mdio_write = bnx2x_mdio_write;
10049
a2fbb9ea
ET		 10050 return 0;
10051
a2fbb9ea 10052err_out_release:
34f80b04
EG		 10053 if (atomic_read(&pdev->enable_cnt) == 1)
10054 pci_release_regions(pdev);
a2fbb9ea
ET		 10055
10056err_out_disable:
10057 pci_disable_device(pdev);
10058 pci_set_drvdata(pdev, NULL);
10059
10060err_out:
10061 return rc;
10062}
10063
37f9ce62
EG		 10064static void __devinit bnx2x_get_pcie_width_speed(struct bnx2x *bp,
10065 int *width, int *speed)
25047950
ET		 10066{
10067 u32 val = REG_RD(bp, PCICFG_OFFSET + PCICFG_LINK_CONTROL);
10068
37f9ce62 10069 *width = (val & PCICFG_LINK_WIDTH) >> PCICFG_LINK_WIDTH_SHIFT;
25047950 10070
37f9ce62
EG		 10071 /* return value of 1=2.5GHz 2=5GHz */
10072 *speed = (val & PCICFG_LINK_SPEED) >> PCICFG_LINK_SPEED_SHIFT;
25047950 10073}
37f9ce62 10074
6891dd25 10075static int bnx2x_check_firmware(struct bnx2x *bp)
94a78b79 10076{
37f9ce62 10077 const struct firmware *firmware = bp->firmware;
94a78b79
VZ		 10078 struct bnx2x_fw_file_hdr *fw_hdr;
10079 struct bnx2x_fw_file_section *sections;
94a78b79 10080 u32 offset, len, num_ops;
37f9ce62 10081 u16 *ops_offsets;
94a78b79 10082 int i;
37f9ce62 10083 const u8 *fw_ver;
94a78b79
VZ		 10084
10085 if (firmware->size < sizeof(struct bnx2x_fw_file_hdr))
10086 return -EINVAL;
10087
10088 fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data;
10089 sections = (struct bnx2x_fw_file_section *)fw_hdr;
10090
10091 /* Make sure none of the offsets and sizes make us read beyond
10092 * the end of the firmware data */
10093 for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) {
10094 offset = be32_to_cpu(sections[i].offset);
10095 len = be32_to_cpu(sections[i].len);
10096 if (offset + len > firmware->size) {
cdaa7cb8
VZ		 10097 dev_err(&bp->pdev->dev,
10098 "Section %d length is out of bounds\n", i);
94a78b79
VZ		 10099 return -EINVAL;
10100 }
10101 }
10102
10103 /* Likewise for the init_ops offsets */
10104 offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset);
10105 ops_offsets = (u16 *)(firmware->data + offset);
10106 num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op);
10107
10108 for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) {
10109 if (be16_to_cpu(ops_offsets[i]) > num_ops) {
cdaa7cb8
VZ		 10110 dev_err(&bp->pdev->dev,
10111 "Section offset %d is out of bounds\n", i);
94a78b79
VZ		 10112 return -EINVAL;
10113 }
10114 }
10115
10116 /* Check FW version */
10117 offset = be32_to_cpu(fw_hdr->fw_version.offset);
10118 fw_ver = firmware->data + offset;
10119 if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) ||
10120 (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) ||
10121 (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) ||
10122 (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) {
cdaa7cb8
VZ		 10123 dev_err(&bp->pdev->dev,
10124 "Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n",
94a78b79
VZ		 10125 fw_ver[0], fw_ver[1], fw_ver[2],
10126 fw_ver[3], BCM_5710_FW_MAJOR_VERSION,
10127 BCM_5710_FW_MINOR_VERSION,
10128 BCM_5710_FW_REVISION_VERSION,
10129 BCM_5710_FW_ENGINEERING_VERSION);
ab6ad5a4 10130 return -EINVAL;
94a78b79
VZ		 10131 }
10132
10133 return 0;
10134}
10135
ab6ad5a4 10136static inline void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
94a78b79 10137{
ab6ad5a4
EG		 10138 const __be32 *source = (const __be32 *)_source;
10139 u32 *target = (u32 *)_target;
94a78b79 10140 u32 i;
94a78b79
VZ		 10141
10142 for (i = 0; i < n/4; i++)
10143 target[i] = be32_to_cpu(source[i]);
10144}
10145
10146/*
10147 Ops array is stored in the following format:
10148 {op(8bit), offset(24bit, big endian), data(32bit, big endian)}
10149 */
ab6ad5a4 10150static inline void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n)
94a78b79 10151{
ab6ad5a4
EG		 10152 const __be32 *source = (const __be32 *)_source;
10153 struct raw_op *target = (struct raw_op *)_target;
94a78b79 10154 u32 i, j, tmp;
94a78b79 10155
ab6ad5a4 10156 for (i = 0, j = 0; i < n/8; i++, j += 2) {
94a78b79
VZ		 10157 tmp = be32_to_cpu(source[j]);
10158 target[i].op = (tmp >> 24) & 0xff;
cdaa7cb8
VZ		 10159 target[i].offset = tmp & 0xffffff;
10160 target[i].raw_data = be32_to_cpu(source[j + 1]);
94a78b79
VZ		 10161 }
10162}
ab6ad5a4 10163
523224a3
DK		 10164/**
10165 * IRO array is stored in the following format:
10166 * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) }
10167 */
10168static inline void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n)
10169{
10170 const __be32 *source = (const __be32 *)_source;
10171 struct iro *target = (struct iro *)_target;
10172 u32 i, j, tmp;
10173
10174 for (i = 0, j = 0; i < n/sizeof(struct iro); i++) {
10175 target[i].base = be32_to_cpu(source[j]);
10176 j++;
10177 tmp = be32_to_cpu(source[j]);
10178 target[i].m1 = (tmp >> 16) & 0xffff;
10179 target[i].m2 = tmp & 0xffff;
10180 j++;
10181 tmp = be32_to_cpu(source[j]);
10182 target[i].m3 = (tmp >> 16) & 0xffff;
10183 target[i].size = tmp & 0xffff;
10184 j++;
10185 }
10186}
10187
ab6ad5a4 10188static inline void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
94a78b79 10189{
ab6ad5a4
EG		 10190 const __be16 *source = (const __be16 *)_source;
10191 u16 *target = (u16 *)_target;
94a78b79 10192 u32 i;
94a78b79
VZ		 10193
10194 for (i = 0; i < n/2; i++)
10195 target[i] = be16_to_cpu(source[i]);
10196}
10197
7995c64e
JP		 10198#define BNX2X_ALLOC_AND_SET(arr, lbl, func) \
10199do { \
10200 u32 len = be32_to_cpu(fw_hdr->arr.len); \
10201 bp->arr = kmalloc(len, GFP_KERNEL); \
10202 if (!bp->arr) { \
10203 pr_err("Failed to allocate %d bytes for "#arr"\n", len); \
10204 goto lbl; \
10205 } \
10206 func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \
10207 (u8 *)bp->arr, len); \
10208} while (0)
94a78b79 10209
6891dd25 10210int bnx2x_init_firmware(struct bnx2x *bp)
94a78b79 10211{
45229b42 10212 const char *fw_file_name;
94a78b79 10213 struct bnx2x_fw_file_hdr *fw_hdr;
45229b42 10214 int rc;
94a78b79 10215
94a78b79 10216 if (CHIP_IS_E1(bp))
45229b42 10217 fw_file_name = FW_FILE_NAME_E1;
cdaa7cb8 10218 else if (CHIP_IS_E1H(bp))
45229b42 10219 fw_file_name = FW_FILE_NAME_E1H;
619c5cb6 10220 else if (!CHIP_IS_E1x(bp))
f2e0899f 10221 fw_file_name = FW_FILE_NAME_E2;
cdaa7cb8 10222 else {
6891dd25 10223 BNX2X_ERR("Unsupported chip revision\n");
cdaa7cb8
VZ		 10224 return -EINVAL;
10225 }
94a78b79 10226
6891dd25 10227 BNX2X_DEV_INFO("Loading %s\n", fw_file_name);
94a78b79 10228
6891dd25 10229 rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev);
94a78b79 10230 if (rc) {
6891dd25 10231 BNX2X_ERR("Can't load firmware file %s\n", fw_file_name);
94a78b79
VZ		 10232 goto request_firmware_exit;
10233 }
10234
10235 rc = bnx2x_check_firmware(bp);
10236 if (rc) {
6891dd25 10237 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name);
94a78b79
VZ		 10238 goto request_firmware_exit;
10239 }
10240
10241 fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data;
10242
10243 /* Initialize the pointers to the init arrays */
10244 /* Blob */
10245 BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n);
10246
10247 /* Opcodes */
10248 BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops);
10249
10250 /* Offsets */
ab6ad5a4
EG		 10251 BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err,
10252 be16_to_cpu_n);
94a78b79
VZ		 10253
10254 /* STORMs firmware */
573f2035
EG		 10255 INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
10256 be32_to_cpu(fw_hdr->tsem_int_table_data.offset);
10257 INIT_TSEM_PRAM_DATA(bp) = bp->firmware->data +
10258 be32_to_cpu(fw_hdr->tsem_pram_data.offset);
10259 INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data +
10260 be32_to_cpu(fw_hdr->usem_int_table_data.offset);
10261 INIT_USEM_PRAM_DATA(bp) = bp->firmware->data +
10262 be32_to_cpu(fw_hdr->usem_pram_data.offset);
10263 INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
10264 be32_to_cpu(fw_hdr->xsem_int_table_data.offset);
10265 INIT_XSEM_PRAM_DATA(bp) = bp->firmware->data +
10266 be32_to_cpu(fw_hdr->xsem_pram_data.offset);
10267 INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
10268 be32_to_cpu(fw_hdr->csem_int_table_data.offset);
10269 INIT_CSEM_PRAM_DATA(bp) = bp->firmware->data +
10270 be32_to_cpu(fw_hdr->csem_pram_data.offset);
523224a3
DK		 10271 /* IRO */
10272 BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro);
94a78b79
VZ		 10273
10274 return 0;
ab6ad5a4 10275
523224a3
DK		 10276iro_alloc_err:
10277 kfree(bp->init_ops_offsets);
94a78b79
VZ		 10278init_offsets_alloc_err:
10279 kfree(bp->init_ops);
10280init_ops_alloc_err:
10281 kfree(bp->init_data);
10282request_firmware_exit:
10283 release_firmware(bp->firmware);
10284
10285 return rc;
10286}
10287
619c5cb6
VZ		 10288static void bnx2x_release_firmware(struct bnx2x *bp)
10289{
10290 kfree(bp->init_ops_offsets);
10291 kfree(bp->init_ops);
10292 kfree(bp->init_data);
10293 release_firmware(bp->firmware);
10294}
10295
10296
10297static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = {
10298 .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
10299 .init_hw_cmn = bnx2x_init_hw_common,
10300 .init_hw_port = bnx2x_init_hw_port,
10301 .init_hw_func = bnx2x_init_hw_func,
10302
10303 .reset_hw_cmn = bnx2x_reset_common,
10304 .reset_hw_port = bnx2x_reset_port,
10305 .reset_hw_func = bnx2x_reset_func,
10306
10307 .gunzip_init = bnx2x_gunzip_init,
10308 .gunzip_end = bnx2x_gunzip_end,
10309
10310 .init_fw = bnx2x_init_firmware,
10311 .release_fw = bnx2x_release_firmware,
10312};
10313
10314void bnx2x__init_func_obj(struct bnx2x *bp)
10315{
10316 /* Prepare DMAE related driver resources */
10317 bnx2x_setup_dmae(bp);
10318
10319 bnx2x_init_func_obj(bp, &bp->func_obj,
10320 bnx2x_sp(bp, func_rdata),
10321 bnx2x_sp_mapping(bp, func_rdata),
10322 &bnx2x_func_sp_drv);
10323}
10324
10325/* must be called after sriov-enable */
6383c0b3 10326static inline int bnx2x_set_qm_cid_count(struct bnx2x *bp)
523224a3 10327{
6383c0b3 10328 int cid_count = BNX2X_L2_CID_COUNT(bp);
94a78b79 10329
523224a3
DK		 10330#ifdef BCM_CNIC
10331 cid_count += CNIC_CID_MAX;
10332#endif
10333 return roundup(cid_count, QM_CID_ROUND);
10334}
f85582f8 10335
619c5cb6 10336/**
6383c0b3 10337 * bnx2x_get_num_none_def_sbs - return the number of none default SBs
619c5cb6
VZ		 10338 *
10339 * @dev: pci device
10340 *
10341 */
6383c0b3 10342static inline int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev)
619c5cb6
VZ		 10343{
10344 int pos;
10345 u16 control;
10346
10347 pos = pci_find_capability(pdev, PCI_CAP_ID_MSIX);
6383c0b3
AE		 10348
10349 /*
10350 * If MSI-X is not supported - return number of SBs needed to support
10351 * one fast path queue: one FP queue + SB for CNIC
10352 */
619c5cb6 10353 if (!pos)
6383c0b3 10354 return 1 + CNIC_PRESENT;
619c5cb6 10355
6383c0b3
AE		 10356 /*
10357 * The value in the PCI configuration space is the index of the last
10358 * entry, namely one less than the actual size of the table, which is
10359 * exactly what we want to return from this function: number of all SBs
10360 * without the default SB.
10361 */
619c5cb6 10362 pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &control);
6383c0b3 10363 return control & PCI_MSIX_FLAGS_QSIZE;
619c5cb6
VZ		 10364}
10365
a2fbb9ea
ET		 10366static int __devinit bnx2x_init_one(struct pci_dev *pdev,
10367 const struct pci_device_id *ent)
10368{
a2fbb9ea
ET		 10369 struct net_device *dev = NULL;
10370 struct bnx2x *bp;
37f9ce62 10371 int pcie_width, pcie_speed;
6383c0b3
AE		 10372 int rc, max_non_def_sbs;
10373 int rx_count, tx_count, rss_count;
10374 /*
10375 * An estimated maximum supported CoS number according to the chip
10376 * version.
10377 * We will try to roughly estimate the maximum number of CoSes this chip
10378 * may support in order to minimize the memory allocated for Tx
10379 * netdev_queue's. This number will be accurately calculated during the
10380 * initialization of bp->max_cos based on the chip versions AND chip
10381 * revision in the bnx2x_init_bp().
10382 */
10383 u8 max_cos_est = 0;
523224a3 10384
f2e0899f
DK		 10385 switch (ent->driver_data) {
10386 case BCM57710:
10387 case BCM57711:
10388 case BCM57711E:
6383c0b3
AE		 10389 max_cos_est = BNX2X_MULTI_TX_COS_E1X;
10390 break;
10391
f2e0899f 10392 case BCM57712:
619c5cb6 10393 case BCM57712_MF:
6383c0b3
AE		 10394 max_cos_est = BNX2X_MULTI_TX_COS_E2_E3A0;
10395 break;
10396
619c5cb6
VZ		 10397 case BCM57800:
10398 case BCM57800_MF:
10399 case BCM57810:
10400 case BCM57810_MF:
10401 case BCM57840:
10402 case BCM57840_MF:
6383c0b3 10403 max_cos_est = BNX2X_MULTI_TX_COS_E3B0;
f2e0899f 10404 break;
a2fbb9ea 10405
f2e0899f
DK		 10406 default:
10407 pr_err("Unknown board_type (%ld), aborting\n",
10408 ent->driver_data);
870634b0 10409 return -ENODEV;
f2e0899f
DK		 10410 }
10411
6383c0b3
AE		 10412 max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev);
10413
10414 /* !!! FIXME !!!
10415 * Do not allow the maximum SB count to grow above 16
10416 * since Special CIDs starts from 16*BNX2X_MULTI_TX_COS=48.
10417 * We will use the FP_SB_MAX_E1x macro for this matter.
10418 */
10419 max_non_def_sbs = min_t(int, FP_SB_MAX_E1x, max_non_def_sbs);
10420
10421 WARN_ON(!max_non_def_sbs);
10422
10423 /* Maximum number of RSS queues: one IGU SB goes to CNIC */
10424 rss_count = max_non_def_sbs - CNIC_PRESENT;
10425
10426 /* Maximum number of netdev Rx queues: RSS + FCoE L2 */
10427 rx_count = rss_count + FCOE_PRESENT;
10428
10429 /*
10430 * Maximum number of netdev Tx queues:
10431 * Maximum TSS queues * Maximum supported number of CoS + FCoE L2
10432 */
10433 tx_count = MAX_TXQS_PER_COS * max_cos_est + FCOE_PRESENT;
f85582f8 10434
a2fbb9ea 10435 /* dev zeroed in init_etherdev */
6383c0b3 10436 dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count);
34f80b04 10437 if (!dev) {
cdaa7cb8 10438 dev_err(&pdev->dev, "Cannot allocate net device\n");
a2fbb9ea 10439 return -ENOMEM;
34f80b04 10440 }
a2fbb9ea 10441
a2fbb9ea 10442 bp = netdev_priv(dev);
a2fbb9ea 10443
6383c0b3
AE		 10444 DP(NETIF_MSG_DRV, "Allocated netdev with %d tx and %d rx queues\n",
10445 tx_count, rx_count);
df4770de 10446
6383c0b3
AE		 10447 bp->igu_sb_cnt = max_non_def_sbs;
10448 bp->msg_enable = debug;
10449 pci_set_drvdata(pdev, dev);
523224a3 10450
619c5cb6 10451 rc = bnx2x_init_dev(pdev, dev, ent->driver_data);
a2fbb9ea
ET		 10452 if (rc < 0) {
10453 free_netdev(dev);
10454 return rc;
10455 }
10456
6383c0b3 10457 DP(NETIF_MSG_DRV, "max_non_def_sbs %d", max_non_def_sbs);
619c5cb6 10458
34f80b04 10459 rc = bnx2x_init_bp(bp);
693fc0d1
EG		 10460 if (rc)
10461 goto init_one_exit;
10462
6383c0b3
AE		 10463 /*
10464 * Map doorbels here as we need the real value of bp->max_cos which
10465 * is initialized in bnx2x_init_bp().
10466 */
10467 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2),
10468 min_t(u64, BNX2X_DB_SIZE(bp),
10469 pci_resource_len(pdev, 2)));
10470 if (!bp->doorbells) {
10471 dev_err(&bp->pdev->dev,
10472 "Cannot map doorbell space, aborting\n");
10473 rc = -ENOMEM;
10474 goto init_one_exit;
10475 }
10476
523224a3 10477 /* calc qm_cid_count */
6383c0b3 10478 bp->qm_cid_count = bnx2x_set_qm_cid_count(bp);
523224a3 10479
ec6ba945
VZ		 10480#ifdef BCM_CNIC
10481 /* disable FCOE L2 queue for E1x*/
10482 if (CHIP_IS_E1x(bp))
10483 bp->flags |= NO_FCOE_FLAG;
10484
10485#endif
10486
25985edc 10487 /* Configure interrupt mode: try to enable MSI-X/MSI if
d6214d7a
DK		 10488 * needed, set bp->num_queues appropriately.
10489 */
10490 bnx2x_set_int_mode(bp);
10491
10492 /* Add all NAPI objects */
10493 bnx2x_add_all_napi(bp);
10494
b340007f
VZ		 10495 rc = register_netdev(dev);
10496 if (rc) {
10497 dev_err(&pdev->dev, "Cannot register net device\n");
10498 goto init_one_exit;
10499 }
10500
ec6ba945
VZ		 10501#ifdef BCM_CNIC
10502 if (!NO_FCOE(bp)) {
10503 /* Add storage MAC address */
10504 rtnl_lock();
10505 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
10506 rtnl_unlock();
10507 }
10508#endif
10509
37f9ce62 10510 bnx2x_get_pcie_width_speed(bp, &pcie_width, &pcie_speed);
d6214d7a 10511
cdaa7cb8
VZ		 10512 netdev_info(dev, "%s (%c%d) PCI-E x%d %s found at mem %lx,"
10513 " IRQ %d, ", board_info[ent->driver_data].name,
10514 (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),
f2e0899f
DK		 10515 pcie_width,
10516 ((!CHIP_IS_E2(bp) && pcie_speed == 2) ||
10517 (CHIP_IS_E2(bp) && pcie_speed == 1)) ?
10518 "5GHz (Gen2)" : "2.5GHz",
cdaa7cb8
VZ		 10519 dev->base_addr, bp->pdev->irq);
10520 pr_cont("node addr %pM\n", dev->dev_addr);
c016201c 10521
a2fbb9ea 10522 return 0;
34f80b04
EG		 10523
10524init_one_exit:
10525 if (bp->regview)
10526 iounmap(bp->regview);
10527
10528 if (bp->doorbells)
10529 iounmap(bp->doorbells);
10530
10531 free_netdev(dev);
10532
10533 if (atomic_read(&pdev->enable_cnt) == 1)
10534 pci_release_regions(pdev);
10535
10536 pci_disable_device(pdev);
10537 pci_set_drvdata(pdev, NULL);
10538
10539 return rc;
a2fbb9ea
ET		 10540}
10541
10542static void __devexit bnx2x_remove_one(struct pci_dev *pdev)
10543{
10544 struct net_device *dev = pci_get_drvdata(pdev);
228241eb
ET		 10545 struct bnx2x *bp;
10546
10547 if (!dev) {
cdaa7cb8 10548 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n");
228241eb
ET		 10549 return;
10550 }
228241eb 10551 bp = netdev_priv(dev);
a2fbb9ea 10552
ec6ba945
VZ		 10553#ifdef BCM_CNIC
10554 /* Delete storage MAC address */
10555 if (!NO_FCOE(bp)) {
10556 rtnl_lock();
10557 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
10558 rtnl_unlock();
10559 }
10560#endif
10561
98507672
SR		 10562#ifdef BCM_DCBNL
10563 /* Delete app tlvs from dcbnl */
10564 bnx2x_dcbnl_update_applist(bp, true);
10565#endif
10566
a2fbb9ea
ET		 10567 unregister_netdev(dev);
10568
d6214d7a
DK		 10569 /* Delete all NAPI objects */
10570 bnx2x_del_all_napi(bp);
10571
084d6cbb
VZ		 10572 /* Power on: we can't let PCI layer write to us while we are in D3 */
10573 bnx2x_set_power_state(bp, PCI_D0);
10574
d6214d7a
DK		 10575 /* Disable MSI/MSI-X */
10576 bnx2x_disable_msi(bp);
f85582f8 10577
084d6cbb
VZ		 10578 /* Power off */
10579 bnx2x_set_power_state(bp, PCI_D3hot);
10580
72fd0718 10581 /* Make sure RESET task is not scheduled before continuing */
7be08a72 10582 cancel_delayed_work_sync(&bp->sp_rtnl_task);
72fd0718 10583
a2fbb9ea
ET		 10584 if (bp->regview)
10585 iounmap(bp->regview);
10586
10587 if (bp->doorbells)
10588 iounmap(bp->doorbells);
10589
523224a3
DK		 10590 bnx2x_free_mem_bp(bp);
10591
a2fbb9ea 10592 free_netdev(dev);
34f80b04
EG		 10593
10594 if (atomic_read(&pdev->enable_cnt) == 1)
10595 pci_release_regions(pdev);
10596
a2fbb9ea
ET		 10597 pci_disable_device(pdev);
10598 pci_set_drvdata(pdev, NULL);
10599}
10600
f8ef6e44
YG		 10601static int bnx2x_eeh_nic_unload(struct bnx2x *bp)
10602{
10603 int i;
10604
10605 bp->state = BNX2X_STATE_ERROR;
10606
10607 bp->rx_mode = BNX2X_RX_MODE_NONE;
10608
619c5cb6
VZ		 10609#ifdef BCM_CNIC
10610 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD);
10611#endif
10612 /* Stop Tx */
10613 bnx2x_tx_disable(bp);
10614
f8ef6e44
YG		 10615 bnx2x_netif_stop(bp, 0);
10616
10617 del_timer_sync(&bp->timer);
619c5cb6
VZ		 10618
10619 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
f8ef6e44
YG		 10620
10621 /* Release IRQs */
d6214d7a 10622 bnx2x_free_irq(bp);
f8ef6e44 10623
f8ef6e44
YG		 10624 /* Free SKBs, SGEs, TPA pool and driver internals */
10625 bnx2x_free_skbs(bp);
523224a3 10626
ec6ba945 10627 for_each_rx_queue(bp, i)
f8ef6e44 10628 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
d6214d7a 10629
f8ef6e44
YG		 10630 bnx2x_free_mem(bp);
10631
10632 bp->state = BNX2X_STATE_CLOSED;
10633
619c5cb6
VZ		 10634 netif_carrier_off(bp->dev);
10635
f8ef6e44
YG		 10636 return 0;
10637}
10638
10639static void bnx2x_eeh_recover(struct bnx2x *bp)
10640{
10641 u32 val;
10642
10643 mutex_init(&bp->port.phy_mutex);
10644
10645 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
10646 bp->link_params.shmem_base = bp->common.shmem_base;
10647 BNX2X_DEV_INFO("shmem offset is 0x%x\n", bp->common.shmem_base);
10648
10649 if (!bp->common.shmem_base ||
10650 (bp->common.shmem_base < 0xA0000) ||
10651 (bp->common.shmem_base >= 0xC0000)) {
10652 BNX2X_DEV_INFO("MCP not active\n");
10653 bp->flags |= NO_MCP_FLAG;
10654 return;
10655 }
10656
10657 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
10658 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
10659 != (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
10660 BNX2X_ERR("BAD MCP validity signature\n");
10661
10662 if (!BP_NOMCP(bp)) {
f2e0899f
DK		 10663 bp->fw_seq =
10664 (SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
10665 DRV_MSG_SEQ_NUMBER_MASK);
f8ef6e44
YG		 10666 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
10667 }
10668}
10669
493adb1f
WX		 10670/**
10671 * bnx2x_io_error_detected - called when PCI error is detected
10672 * @pdev: Pointer to PCI device
10673 * @state: The current pci connection state
10674 *
10675 * This function is called after a PCI bus error affecting
10676 * this device has been detected.
10677 */
10678static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev,
10679 pci_channel_state_t state)
10680{
10681 struct net_device *dev = pci_get_drvdata(pdev);
10682 struct bnx2x *bp = netdev_priv(dev);
10683
10684 rtnl_lock();
10685
10686 netif_device_detach(dev);
10687
07ce50e4
DN		 10688 if (state == pci_channel_io_perm_failure) {
10689 rtnl_unlock();
10690 return PCI_ERS_RESULT_DISCONNECT;
10691 }
10692
493adb1f 10693 if (netif_running(dev))
f8ef6e44 10694 bnx2x_eeh_nic_unload(bp);
493adb1f
WX		 10695
10696 pci_disable_device(pdev);
10697
10698 rtnl_unlock();
10699
10700 /* Request a slot reset */
10701 return PCI_ERS_RESULT_NEED_RESET;
10702}
10703
10704/**
10705 * bnx2x_io_slot_reset - called after the PCI bus has been reset
10706 * @pdev: Pointer to PCI device
10707 *
10708 * Restart the card from scratch, as if from a cold-boot.
10709 */
10710static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev)
10711{
10712 struct net_device *dev = pci_get_drvdata(pdev);
10713 struct bnx2x *bp = netdev_priv(dev);
10714
10715 rtnl_lock();
10716
10717 if (pci_enable_device(pdev)) {
10718 dev_err(&pdev->dev,
10719 "Cannot re-enable PCI device after reset\n");
10720 rtnl_unlock();
10721 return PCI_ERS_RESULT_DISCONNECT;
10722 }
10723
10724 pci_set_master(pdev);
10725 pci_restore_state(pdev);
10726
10727 if (netif_running(dev))
10728 bnx2x_set_power_state(bp, PCI_D0);
10729
10730 rtnl_unlock();
10731
10732 return PCI_ERS_RESULT_RECOVERED;
10733}
10734
10735/**
10736 * bnx2x_io_resume - called when traffic can start flowing again
10737 * @pdev: Pointer to PCI device
10738 *
10739 * This callback is called when the error recovery driver tells us that
10740 * its OK to resume normal operation.
10741 */
10742static void bnx2x_io_resume(struct pci_dev *pdev)
10743{
10744 struct net_device *dev = pci_get_drvdata(pdev);
10745 struct bnx2x *bp = netdev_priv(dev);
10746
72fd0718 10747 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
754a2f52
DK		 10748 netdev_err(bp->dev, "Handling parity error recovery. "
10749 "Try again later\n");
72fd0718
VZ		 10750 return;
10751 }
10752
493adb1f
WX		 10753 rtnl_lock();
10754
f8ef6e44
YG		 10755 bnx2x_eeh_recover(bp);
10756
493adb1f 10757 if (netif_running(dev))
f8ef6e44 10758 bnx2x_nic_load(bp, LOAD_NORMAL);
493adb1f
WX		 10759
10760 netif_device_attach(dev);
10761
10762 rtnl_unlock();
10763}
10764
10765static struct pci_error_handlers bnx2x_err_handler = {
10766 .error_detected = bnx2x_io_error_detected,
356e2385
EG		 10767 .slot_reset = bnx2x_io_slot_reset,
10768 .resume = bnx2x_io_resume,
493adb1f
WX		 10769};
10770
a2fbb9ea 10771static struct pci_driver bnx2x_pci_driver = {
493adb1f
WX		 10772 .name = DRV_MODULE_NAME,
10773 .id_table = bnx2x_pci_tbl,
10774 .probe = bnx2x_init_one,
10775 .remove = __devexit_p(bnx2x_remove_one),
10776 .suspend = bnx2x_suspend,
10777 .resume = bnx2x_resume,
10778 .err_handler = &bnx2x_err_handler,
a2fbb9ea
ET		 10779};
10780
10781static int __init bnx2x_init(void)
10782{
dd21ca6d
SG		 10783 int ret;
10784
7995c64e 10785 pr_info("%s", version);
938cf541 10786
1cf167f2
EG		 10787 bnx2x_wq = create_singlethread_workqueue("bnx2x");
10788 if (bnx2x_wq == NULL) {
7995c64e 10789 pr_err("Cannot create workqueue\n");
1cf167f2
EG		 10790 return -ENOMEM;
10791 }
10792
dd21ca6d
SG		 10793 ret = pci_register_driver(&bnx2x_pci_driver);
10794 if (ret) {
7995c64e 10795 pr_err("Cannot register driver\n");
dd21ca6d
SG		 10796 destroy_workqueue(bnx2x_wq);
10797 }
10798 return ret;
a2fbb9ea
ET		 10799}
10800
10801static void __exit bnx2x_cleanup(void)
10802{
10803 pci_unregister_driver(&bnx2x_pci_driver);
1cf167f2
EG		 10804
10805 destroy_workqueue(bnx2x_wq);
a2fbb9ea
ET		 10806}
10807
3deb8167
YR		 10808void bnx2x_notify_link_changed(struct bnx2x *bp)
10809{
10810 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1);
10811}
10812
a2fbb9ea
ET		 10813module_init(bnx2x_init);
10814module_exit(bnx2x_cleanup);
10815
993ac7b5 10816#ifdef BCM_CNIC
619c5cb6
VZ		 10817/**
10818 * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s).
10819 *
10820 * @bp: driver handle
10821 * @set: set or clear the CAM entry
10822 *
10823 * This function will wait until the ramdord completion returns.
10824 * Return 0 if success, -ENODEV if ramrod doesn't return.
10825 */
10826static inline int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp)
10827{
10828 unsigned long ramrod_flags = 0;
10829
10830 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
10831 return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac,
10832 &bp->iscsi_l2_mac_obj, true,
10833 BNX2X_ISCSI_ETH_MAC, &ramrod_flags);
10834}
993ac7b5
MC		 10835
10836/* count denotes the number of new completions we have seen */
10837static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count)
10838{
10839 struct eth_spe *spe;
10840
10841#ifdef BNX2X_STOP_ON_ERROR
10842 if (unlikely(bp->panic))
10843 return;
10844#endif
10845
10846 spin_lock_bh(&bp->spq_lock);
c2bff63f 10847 BUG_ON(bp->cnic_spq_pending < count);
993ac7b5
MC		 10848 bp->cnic_spq_pending -= count;
10849
993ac7b5 10850
c2bff63f
DK		 10851 for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) {
10852 u16 type = (le16_to_cpu(bp->cnic_kwq_cons->hdr.type)
10853 & SPE_HDR_CONN_TYPE) >>
10854 SPE_HDR_CONN_TYPE_SHIFT;
619c5cb6
VZ		 10855 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data)
10856 >> SPE_HDR_CMD_ID_SHIFT) & 0xff;
c2bff63f
DK		 10857
10858 /* Set validation for iSCSI L2 client before sending SETUP
10859 * ramrod
10860 */
10861 if (type == ETH_CONNECTION_TYPE) {
c2bff63f 10862 if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP)
619c5cb6
VZ		 10863 bnx2x_set_ctx_validation(bp, &bp->context.
10864 vcxt[BNX2X_ISCSI_ETH_CID].eth,
10865 BNX2X_ISCSI_ETH_CID);
c2bff63f
DK		 10866 }
10867
619c5cb6
VZ		 10868 /*
10869 * There may be not more than 8 L2, not more than 8 L5 SPEs
10870 * and in the air. We also check that number of outstanding
6e30dd4e
VZ		 10871 * COMMON ramrods is not more than the EQ and SPQ can
10872 * accommodate.
c2bff63f 10873 */
6e30dd4e
VZ		 10874 if (type == ETH_CONNECTION_TYPE) {
10875 if (!atomic_read(&bp->cq_spq_left))
10876 break;
10877 else
10878 atomic_dec(&bp->cq_spq_left);
10879 } else if (type == NONE_CONNECTION_TYPE) {
10880 if (!atomic_read(&bp->eq_spq_left))
c2bff63f
DK		 10881 break;
10882 else
6e30dd4e 10883 atomic_dec(&bp->eq_spq_left);
ec6ba945
VZ		 10884 } else if ((type == ISCSI_CONNECTION_TYPE) ||
10885 (type == FCOE_CONNECTION_TYPE)) {
c2bff63f
DK		 10886 if (bp->cnic_spq_pending >=
10887 bp->cnic_eth_dev.max_kwqe_pending)
10888 break;
10889 else
10890 bp->cnic_spq_pending++;
10891 } else {
10892 BNX2X_ERR("Unknown SPE type: %d\n", type);
10893 bnx2x_panic();
993ac7b5 10894 break;
c2bff63f 10895 }
993ac7b5
MC		 10896
10897 spe = bnx2x_sp_get_next(bp);
10898 *spe = *bp->cnic_kwq_cons;
10899
993ac7b5
MC		 10900 DP(NETIF_MSG_TIMER, "pending on SPQ %d, on KWQ %d count %d\n",
10901 bp->cnic_spq_pending, bp->cnic_kwq_pending, count);
10902
10903 if (bp->cnic_kwq_cons == bp->cnic_kwq_last)
10904 bp->cnic_kwq_cons = bp->cnic_kwq;
10905 else
10906 bp->cnic_kwq_cons++;
10907 }
10908 bnx2x_sp_prod_update(bp);
10909 spin_unlock_bh(&bp->spq_lock);
10910}
10911
10912static int bnx2x_cnic_sp_queue(struct net_device *dev,
10913 struct kwqe_16 *kwqes[], u32 count)
10914{
10915 struct bnx2x *bp = netdev_priv(dev);
10916 int i;
10917
10918#ifdef BNX2X_STOP_ON_ERROR
10919 if (unlikely(bp->panic))
10920 return -EIO;
10921#endif
10922
10923 spin_lock_bh(&bp->spq_lock);
10924
10925 for (i = 0; i < count; i++) {
10926 struct eth_spe *spe = (struct eth_spe *)kwqes[i];
10927
10928 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT)
10929 break;
10930
10931 *bp->cnic_kwq_prod = *spe;
10932
10933 bp->cnic_kwq_pending++;
10934
10935 DP(NETIF_MSG_TIMER, "L5 SPQE %x %x %x:%x pos %d\n",
10936 spe->hdr.conn_and_cmd_data, spe->hdr.type,
523224a3
DK		 10937 spe->data.update_data_addr.hi,
10938 spe->data.update_data_addr.lo,
993ac7b5
MC		 10939 bp->cnic_kwq_pending);
10940
10941 if (bp->cnic_kwq_prod == bp->cnic_kwq_last)
10942 bp->cnic_kwq_prod = bp->cnic_kwq;
10943 else
10944 bp->cnic_kwq_prod++;
10945 }
10946
10947 spin_unlock_bh(&bp->spq_lock);
10948
10949 if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending)
10950 bnx2x_cnic_sp_post(bp, 0);
10951
10952 return i;
10953}
10954
10955static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl)
10956{
10957 struct cnic_ops *c_ops;
10958 int rc = 0;
10959
10960 mutex_lock(&bp->cnic_mutex);
13707f9e
ED		 10961 c_ops = rcu_dereference_protected(bp->cnic_ops,
10962 lockdep_is_held(&bp->cnic_mutex));
993ac7b5
MC		 10963 if (c_ops)
10964 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
10965 mutex_unlock(&bp->cnic_mutex);
10966
10967 return rc;
10968}
10969
10970static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl)
10971{
10972 struct cnic_ops *c_ops;
10973 int rc = 0;
10974
10975 rcu_read_lock();
10976 c_ops = rcu_dereference(bp->cnic_ops);
10977 if (c_ops)
10978 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
10979 rcu_read_unlock();
10980
10981 return rc;
10982}
10983
10984/*
10985 * for commands that have no data
10986 */
9f6c9258 10987int bnx2x_cnic_notify(struct bnx2x *bp, int cmd)
993ac7b5
MC		 10988{
10989 struct cnic_ctl_info ctl = {0};
10990
10991 ctl.cmd = cmd;
10992
10993 return bnx2x_cnic_ctl_send(bp, &ctl);
10994}
10995
619c5cb6 10996static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err)
993ac7b5 10997{
619c5cb6 10998 struct cnic_ctl_info ctl = {0};
993ac7b5
MC		 10999
11000 /* first we tell CNIC and only then we count this as a completion */
11001 ctl.cmd = CNIC_CTL_COMPLETION_CMD;
11002 ctl.data.comp.cid = cid;
619c5cb6 11003 ctl.data.comp.error = err;
993ac7b5
MC		 11004
11005 bnx2x_cnic_ctl_send_bh(bp, &ctl);
c2bff63f 11006 bnx2x_cnic_sp_post(bp, 0);
993ac7b5
MC		 11007}
11008
619c5cb6
VZ		 11009
11010/* Called with netif_addr_lock_bh() taken.
11011 * Sets an rx_mode config for an iSCSI ETH client.
11012 * Doesn't block.
11013 * Completion should be checked outside.
11014 */
11015static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start)
11016{
11017 unsigned long accept_flags = 0, ramrod_flags = 0;
11018 u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
11019 int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED;
11020
11021 if (start) {
11022 /* Start accepting on iSCSI L2 ring. Accept all multicasts
11023 * because it's the only way for UIO Queue to accept
11024 * multicasts (in non-promiscuous mode only one Queue per
11025 * function will receive multicast packets (leading in our
11026 * case).
11027 */
11028 __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags);
11029 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags);
11030 __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags);
11031 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags);
11032
11033 /* Clear STOP_PENDING bit if START is requested */
11034 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state);
11035
11036 sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED;
11037 } else
11038 /* Clear START_PENDING bit if STOP is requested */
11039 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state);
11040
11041 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
11042 set_bit(sched_state, &bp->sp_state);
11043 else {
11044 __set_bit(RAMROD_RX, &ramrod_flags);
11045 bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0,
11046 ramrod_flags);
11047 }
11048}
11049
11050
993ac7b5
MC		 11051static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl)
11052{
11053 struct bnx2x *bp = netdev_priv(dev);
11054 int rc = 0;
11055
11056 switch (ctl->cmd) {
11057 case DRV_CTL_CTXTBL_WR_CMD: {
11058 u32 index = ctl->data.io.offset;
11059 dma_addr_t addr = ctl->data.io.dma_addr;
11060
11061 bnx2x_ilt_wr(bp, index, addr);
11062 break;
11063 }
11064
c2bff63f
DK		 11065 case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: {
11066 int count = ctl->data.credit.credit_count;
993ac7b5
MC		 11067
11068 bnx2x_cnic_sp_post(bp, count);
11069 break;
11070 }
11071
11072 /* rtnl_lock is held. */
11073 case DRV_CTL_START_L2_CMD: {
619c5cb6
VZ		 11074 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
11075 unsigned long sp_bits = 0;
11076
11077 /* Configure the iSCSI classification object */
11078 bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj,
11079 cp->iscsi_l2_client_id,
11080 cp->iscsi_l2_cid, BP_FUNC(bp),
11081 bnx2x_sp(bp, mac_rdata),
11082 bnx2x_sp_mapping(bp, mac_rdata),
11083 BNX2X_FILTER_MAC_PENDING,
11084 &bp->sp_state, BNX2X_OBJ_TYPE_RX,
11085 &bp->macs_pool);
ec6ba945 11086
523224a3 11087 /* Set iSCSI MAC address */
619c5cb6
VZ		 11088 rc = bnx2x_set_iscsi_eth_mac_addr(bp);
11089 if (rc)
11090 break;
523224a3
DK		 11091
11092 mmiowb();
11093 barrier();
11094
619c5cb6
VZ		 11095 /* Start accepting on iSCSI L2 ring */
11096
11097 netif_addr_lock_bh(dev);
11098 bnx2x_set_iscsi_eth_rx_mode(bp, true);
11099 netif_addr_unlock_bh(dev);
11100
11101 /* bits to wait on */
11102 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
11103 __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits);
11104
11105 if (!bnx2x_wait_sp_comp(bp, sp_bits))
11106 BNX2X_ERR("rx_mode completion timed out!\n");
523224a3 11107
993ac7b5
MC		 11108 break;
11109 }
11110
11111 /* rtnl_lock is held. */
11112 case DRV_CTL_STOP_L2_CMD: {
619c5cb6 11113 unsigned long sp_bits = 0;
993ac7b5 11114
523224a3 11115 /* Stop accepting on iSCSI L2 ring */
619c5cb6
VZ		 11116 netif_addr_lock_bh(dev);
11117 bnx2x_set_iscsi_eth_rx_mode(bp, false);
11118 netif_addr_unlock_bh(dev);
11119
11120 /* bits to wait on */
11121 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
11122 __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits);
11123
11124 if (!bnx2x_wait_sp_comp(bp, sp_bits))
11125 BNX2X_ERR("rx_mode completion timed out!\n");
523224a3
DK		 11126
11127 mmiowb();
11128 barrier();
11129
11130 /* Unset iSCSI L2 MAC */
619c5cb6
VZ		 11131 rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj,
11132 BNX2X_ISCSI_ETH_MAC, true);
993ac7b5
MC		 11133 break;
11134 }
c2bff63f
DK		 11135 case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: {
11136 int count = ctl->data.credit.credit_count;
11137
11138 smp_mb__before_atomic_inc();
6e30dd4e 11139 atomic_add(count, &bp->cq_spq_left);
c2bff63f
DK		 11140 smp_mb__after_atomic_inc();
11141 break;
11142 }
993ac7b5
MC		 11143
11144 default:
11145 BNX2X_ERR("unknown command %x\n", ctl->cmd);
11146 rc = -EINVAL;
11147 }
11148
11149 return rc;
11150}
11151
9f6c9258 11152void bnx2x_setup_cnic_irq_info(struct bnx2x *bp)
993ac7b5
MC		 11153{
11154 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
11155
11156 if (bp->flags & USING_MSIX_FLAG) {
11157 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
11158 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
11159 cp->irq_arr[0].vector = bp->msix_table[1].vector;
11160 } else {
11161 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
11162 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
11163 }
619c5cb6 11164 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 11165 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb;
11166 else
11167 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb;
11168
619c5cb6
VZ		 11169 cp->irq_arr[0].status_blk_num = bnx2x_cnic_fw_sb_id(bp);
11170 cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp);
993ac7b5
MC		 11171 cp->irq_arr[1].status_blk = bp->def_status_blk;
11172 cp->irq_arr[1].status_blk_num = DEF_SB_ID;
523224a3 11173 cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID;
993ac7b5
MC		 11174
11175 cp->num_irq = 2;
11176}
11177
11178static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops,
11179 void *data)
11180{
11181 struct bnx2x *bp = netdev_priv(dev);
11182 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
11183
11184 if (ops == NULL)
11185 return -EINVAL;
11186
993ac7b5
MC		 11187 bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL);
11188 if (!bp->cnic_kwq)
11189 return -ENOMEM;
11190
11191 bp->cnic_kwq_cons = bp->cnic_kwq;
11192 bp->cnic_kwq_prod = bp->cnic_kwq;
11193 bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT;
11194
11195 bp->cnic_spq_pending = 0;
11196 bp->cnic_kwq_pending = 0;
11197
11198 bp->cnic_data = data;
11199
11200 cp->num_irq = 0;
619c5cb6 11201 cp->drv_state |= CNIC_DRV_STATE_REGD;
523224a3 11202 cp->iro_arr = bp->iro_arr;
993ac7b5 11203
993ac7b5 11204 bnx2x_setup_cnic_irq_info(bp);
c2bff63f 11205
993ac7b5
MC		 11206 rcu_assign_pointer(bp->cnic_ops, ops);
11207
11208 return 0;
11209}
11210
11211static int bnx2x_unregister_cnic(struct net_device *dev)
11212{
11213 struct bnx2x *bp = netdev_priv(dev);
11214 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
11215
11216 mutex_lock(&bp->cnic_mutex);
993ac7b5
MC		 11217 cp->drv_state = 0;
11218 rcu_assign_pointer(bp->cnic_ops, NULL);
11219 mutex_unlock(&bp->cnic_mutex);
11220 synchronize_rcu();
11221 kfree(bp->cnic_kwq);
11222 bp->cnic_kwq = NULL;
11223
11224 return 0;
11225}
11226
11227struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev)
11228{
11229 struct bnx2x *bp = netdev_priv(dev);
11230 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
11231
2ba45142
VZ		 11232 /* If both iSCSI and FCoE are disabled - return NULL in
11233 * order to indicate CNIC that it should not try to work
11234 * with this device.
11235 */
11236 if (NO_ISCSI(bp) && NO_FCOE(bp))
11237 return NULL;
11238
993ac7b5
MC		 11239 cp->drv_owner = THIS_MODULE;
11240 cp->chip_id = CHIP_ID(bp);
11241 cp->pdev = bp->pdev;
11242 cp->io_base = bp->regview;
11243 cp->io_base2 = bp->doorbells;
11244 cp->max_kwqe_pending = 8;
523224a3 11245 cp->ctx_blk_size = CDU_ILT_PAGE_SZ;
c2bff63f
DK		 11246 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
11247 bnx2x_cid_ilt_lines(bp);
993ac7b5 11248 cp->ctx_tbl_len = CNIC_ILT_LINES;
c2bff63f 11249 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
993ac7b5
MC		 11250 cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue;
11251 cp->drv_ctl = bnx2x_drv_ctl;
11252 cp->drv_register_cnic = bnx2x_register_cnic;
11253 cp->drv_unregister_cnic = bnx2x_unregister_cnic;
ec6ba945 11254 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID;
619c5cb6
VZ		 11255 cp->iscsi_l2_client_id =
11256 bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
c2bff63f
DK		 11257 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID;
11258
2ba45142
VZ		 11259 if (NO_ISCSI_OOO(bp))
11260 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
11261
11262 if (NO_ISCSI(bp))
11263 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI;
11264
11265 if (NO_FCOE(bp))
11266 cp->drv_state |= CNIC_DRV_STATE_NO_FCOE;
11267
c2bff63f
DK		 11268 DP(BNX2X_MSG_SP, "page_size %d, tbl_offset %d, tbl_lines %d, "
11269 "starting cid %d\n",
11270 cp->ctx_blk_size,
11271 cp->ctx_tbl_offset,
11272 cp->ctx_tbl_len,
11273 cp->starting_cid);
993ac7b5
MC		 11274 return cp;
11275}
11276EXPORT_SYMBOL(bnx2x_cnic_probe);
11277
11278#endif /* BCM_CNIC */
94a78b79 11279
Linux kernel - Deliverables
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