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bnx2x: function descriptions format fixed
[deliverable/linux.git] / drivers / net / bnx2x / bnx2x_main.c
CommitLineData
34f80b04 1/* bnx2x_main.c: Broadcom Everest network driver.
a2fbb9ea 2 *
5de92408 3 * Copyright (c) 2007-2011 Broadcom Corporation
a2fbb9ea
ET		 4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
24e3fcef
EG		 9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
a2fbb9ea
ET		 11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
ca00392c 13 * Slowpath and fastpath rework by Vladislav Zolotarov
c14423fe 14 * Statistics and Link management by Yitchak Gertner
a2fbb9ea
ET		 15 *
16 */
17
a2fbb9ea
ET		 18#include <linux/module.h>
19#include <linux/moduleparam.h>
20#include <linux/kernel.h>
21#include <linux/device.h> /* for dev_info() */
22#include <linux/timer.h>
23#include <linux/errno.h>
24#include <linux/ioport.h>
25#include <linux/slab.h>
a2fbb9ea
ET		 26#include <linux/interrupt.h>
27#include <linux/pci.h>
28#include <linux/init.h>
29#include <linux/netdevice.h>
30#include <linux/etherdevice.h>
31#include <linux/skbuff.h>
32#include <linux/dma-mapping.h>
33#include <linux/bitops.h>
34#include <linux/irq.h>
35#include <linux/delay.h>
36#include <asm/byteorder.h>
37#include <linux/time.h>
38#include <linux/ethtool.h>
39#include <linux/mii.h>
0c6671b0 40#include <linux/if_vlan.h>
a2fbb9ea
ET		 41#include <net/ip.h>
42#include <net/tcp.h>
43#include <net/checksum.h>
34f80b04 44#include <net/ip6_checksum.h>
a2fbb9ea
ET		 45#include <linux/workqueue.h>
46#include <linux/crc32.h>
34f80b04 47#include <linux/crc32c.h>
a2fbb9ea
ET		 48#include <linux/prefetch.h>
49#include <linux/zlib.h>
a2fbb9ea 50#include <linux/io.h>
45229b42 51#include <linux/stringify.h>
a2fbb9ea 52
b0efbb99 53#define BNX2X_MAIN
a2fbb9ea
ET		 54#include "bnx2x.h"
55#include "bnx2x_init.h"
94a78b79 56#include "bnx2x_init_ops.h"
9f6c9258 57#include "bnx2x_cmn.h"
e4901dde 58#include "bnx2x_dcb.h"
a2fbb9ea 59
94a78b79
VZ		 60#include <linux/firmware.h>
61#include "bnx2x_fw_file_hdr.h"
62/* FW files */
45229b42
BH		 63#define FW_FILE_VERSION \
64 __stringify(BCM_5710_FW_MAJOR_VERSION) "." \
65 __stringify(BCM_5710_FW_MINOR_VERSION) "." \
66 __stringify(BCM_5710_FW_REVISION_VERSION) "." \
67 __stringify(BCM_5710_FW_ENGINEERING_VERSION)
560131f3
DK		 68#define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
69#define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
f2e0899f 70#define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
94a78b79 71
34f80b04
EG		 72/* Time in jiffies before concluding the transmitter is hung */
73#define TX_TIMEOUT (5*HZ)
a2fbb9ea 74
53a10565 75static char version[] __devinitdata =
34f80b04 76 "Broadcom NetXtreme II 5771x 10Gigabit Ethernet Driver "
a2fbb9ea
ET		 77 DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
78
24e3fcef 79MODULE_AUTHOR("Eliezer Tamir");
f2e0899f
DK		 80MODULE_DESCRIPTION("Broadcom NetXtreme II "
81 "BCM57710/57711/57711E/57712/57712E Driver");
a2fbb9ea
ET		 82MODULE_LICENSE("GPL");
83MODULE_VERSION(DRV_MODULE_VERSION);
45229b42
BH		 84MODULE_FIRMWARE(FW_FILE_NAME_E1);
85MODULE_FIRMWARE(FW_FILE_NAME_E1H);
f2e0899f 86MODULE_FIRMWARE(FW_FILE_NAME_E2);
a2fbb9ea 87
555f6c78
EG		 88static int multi_mode = 1;
89module_param(multi_mode, int, 0);
ca00392c
EG		 90MODULE_PARM_DESC(multi_mode, " Multi queue mode "
91 "(0 Disable; 1 Enable (default))");
92
d6214d7a 93int num_queues;
54b9ddaa
VZ		 94module_param(num_queues, int, 0);
95MODULE_PARM_DESC(num_queues, " Number of queues for multi_mode=1"
96 " (default is as a number of CPUs)");
555f6c78 97
19680c48 98static int disable_tpa;
19680c48 99module_param(disable_tpa, int, 0);
9898f86d 100MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
8badd27a
EG		 101
102static int int_mode;
103module_param(int_mode, int, 0);
cdaa7cb8
VZ		 104MODULE_PARM_DESC(int_mode, " Force interrupt mode other then MSI-X "
105 "(1 INT#x; 2 MSI)");
8badd27a 106
a18f5128
EG		 107static int dropless_fc;
108module_param(dropless_fc, int, 0);
109MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring");
110
9898f86d 111static int poll;
a2fbb9ea 112module_param(poll, int, 0);
9898f86d 113MODULE_PARM_DESC(poll, " Use polling (for debug)");
8d5726c4
EG		 114
115static int mrrs = -1;
116module_param(mrrs, int, 0);
117MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
118
9898f86d 119static int debug;
a2fbb9ea 120module_param(debug, int, 0);
9898f86d
EG		 121MODULE_PARM_DESC(debug, " Default debug msglevel");
122
1cf167f2 123static struct workqueue_struct *bnx2x_wq;
a2fbb9ea 124
ec6ba945
VZ		 125#ifdef BCM_CNIC
126static u8 ALL_ENODE_MACS[] = {0x01, 0x10, 0x18, 0x01, 0x00, 0x01};
127#endif
128
a2fbb9ea
ET		 129enum bnx2x_board_type {
130 BCM57710 = 0,
34f80b04
EG		 131 BCM57711 = 1,
132 BCM57711E = 2,
f2e0899f
DK		 133 BCM57712 = 3,
134 BCM57712E = 4
a2fbb9ea
ET		 135};
136
34f80b04 137/* indexed by board_type, above */
53a10565 138static struct {
a2fbb9ea
ET		 139 char *name;
140} board_info[] __devinitdata = {
34f80b04
EG		 141 { "Broadcom NetXtreme II BCM57710 XGb" },
142 { "Broadcom NetXtreme II BCM57711 XGb" },
f2e0899f
DK		 143 { "Broadcom NetXtreme II BCM57711E XGb" },
144 { "Broadcom NetXtreme II BCM57712 XGb" },
145 { "Broadcom NetXtreme II BCM57712E XGb" }
a2fbb9ea
ET		 146};
147
a3aa1884 148static DEFINE_PCI_DEVICE_TABLE(bnx2x_pci_tbl) = {
e4ed7113
EG		 149 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 },
150 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 },
151 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E },
f2e0899f
DK		 152 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 },
153 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712E), BCM57712E },
a2fbb9ea
ET		 154 { 0 }
155};
156
157MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
158
159/****************************************************************************
160* General service functions
161****************************************************************************/
162
523224a3
DK		 163static inline void __storm_memset_dma_mapping(struct bnx2x *bp,
164 u32 addr, dma_addr_t mapping)
165{
166 REG_WR(bp, addr, U64_LO(mapping));
167 REG_WR(bp, addr + 4, U64_HI(mapping));
168}
169
170static inline void __storm_memset_fill(struct bnx2x *bp,
171 u32 addr, size_t size, u32 val)
172{
173 int i;
174 for (i = 0; i < size/4; i++)
175 REG_WR(bp, addr + (i * 4), val);
176}
177
178static inline void storm_memset_ustats_zero(struct bnx2x *bp,
179 u8 port, u16 stat_id)
180{
181 size_t size = sizeof(struct ustorm_per_client_stats);
182
183 u32 addr = BAR_USTRORM_INTMEM +
184 USTORM_PER_COUNTER_ID_STATS_OFFSET(port, stat_id);
185
186 __storm_memset_fill(bp, addr, size, 0);
187}
188
189static inline void storm_memset_tstats_zero(struct bnx2x *bp,
190 u8 port, u16 stat_id)
191{
192 size_t size = sizeof(struct tstorm_per_client_stats);
193
194 u32 addr = BAR_TSTRORM_INTMEM +
195 TSTORM_PER_COUNTER_ID_STATS_OFFSET(port, stat_id);
196
197 __storm_memset_fill(bp, addr, size, 0);
198}
199
200static inline void storm_memset_xstats_zero(struct bnx2x *bp,
201 u8 port, u16 stat_id)
202{
203 size_t size = sizeof(struct xstorm_per_client_stats);
204
205 u32 addr = BAR_XSTRORM_INTMEM +
206 XSTORM_PER_COUNTER_ID_STATS_OFFSET(port, stat_id);
207
208 __storm_memset_fill(bp, addr, size, 0);
209}
210
211
212static inline void storm_memset_spq_addr(struct bnx2x *bp,
213 dma_addr_t mapping, u16 abs_fid)
214{
215 u32 addr = XSEM_REG_FAST_MEMORY +
216 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid);
217
218 __storm_memset_dma_mapping(bp, addr, mapping);
219}
220
221static inline void storm_memset_ov(struct bnx2x *bp, u16 ov, u16 abs_fid)
222{
223 REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_E1HOV_OFFSET(abs_fid), ov);
224}
225
226static inline void storm_memset_func_cfg(struct bnx2x *bp,
227 struct tstorm_eth_function_common_config *tcfg,
228 u16 abs_fid)
229{
230 size_t size = sizeof(struct tstorm_eth_function_common_config);
231
232 u32 addr = BAR_TSTRORM_INTMEM +
233 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid);
234
235 __storm_memset_struct(bp, addr, size, (u32 *)tcfg);
236}
237
238static inline void storm_memset_xstats_flags(struct bnx2x *bp,
239 struct stats_indication_flags *flags,
240 u16 abs_fid)
241{
242 size_t size = sizeof(struct stats_indication_flags);
243
244 u32 addr = BAR_XSTRORM_INTMEM + XSTORM_STATS_FLAGS_OFFSET(abs_fid);
245
246 __storm_memset_struct(bp, addr, size, (u32 *)flags);
247}
248
249static inline void storm_memset_tstats_flags(struct bnx2x *bp,
250 struct stats_indication_flags *flags,
251 u16 abs_fid)
252{
253 size_t size = sizeof(struct stats_indication_flags);
254
255 u32 addr = BAR_TSTRORM_INTMEM + TSTORM_STATS_FLAGS_OFFSET(abs_fid);
256
257 __storm_memset_struct(bp, addr, size, (u32 *)flags);
258}
259
260static inline void storm_memset_ustats_flags(struct bnx2x *bp,
261 struct stats_indication_flags *flags,
262 u16 abs_fid)
263{
264 size_t size = sizeof(struct stats_indication_flags);
265
266 u32 addr = BAR_USTRORM_INTMEM + USTORM_STATS_FLAGS_OFFSET(abs_fid);
267
268 __storm_memset_struct(bp, addr, size, (u32 *)flags);
269}
270
271static inline void storm_memset_cstats_flags(struct bnx2x *bp,
272 struct stats_indication_flags *flags,
273 u16 abs_fid)
274{
275 size_t size = sizeof(struct stats_indication_flags);
276
277 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_STATS_FLAGS_OFFSET(abs_fid);
278
279 __storm_memset_struct(bp, addr, size, (u32 *)flags);
280}
281
282static inline void storm_memset_xstats_addr(struct bnx2x *bp,
283 dma_addr_t mapping, u16 abs_fid)
284{
285 u32 addr = BAR_XSTRORM_INTMEM +
286 XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(abs_fid);
287
288 __storm_memset_dma_mapping(bp, addr, mapping);
289}
290
291static inline void storm_memset_tstats_addr(struct bnx2x *bp,
292 dma_addr_t mapping, u16 abs_fid)
293{
294 u32 addr = BAR_TSTRORM_INTMEM +
295 TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(abs_fid);
296
297 __storm_memset_dma_mapping(bp, addr, mapping);
298}
299
300static inline void storm_memset_ustats_addr(struct bnx2x *bp,
301 dma_addr_t mapping, u16 abs_fid)
302{
303 u32 addr = BAR_USTRORM_INTMEM +
304 USTORM_ETH_STATS_QUERY_ADDR_OFFSET(abs_fid);
305
306 __storm_memset_dma_mapping(bp, addr, mapping);
307}
308
309static inline void storm_memset_cstats_addr(struct bnx2x *bp,
310 dma_addr_t mapping, u16 abs_fid)
311{
312 u32 addr = BAR_CSTRORM_INTMEM +
313 CSTORM_ETH_STATS_QUERY_ADDR_OFFSET(abs_fid);
314
315 __storm_memset_dma_mapping(bp, addr, mapping);
316}
317
318static inline void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
319 u16 pf_id)
320{
321 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
322 pf_id);
323 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
324 pf_id);
325 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
326 pf_id);
327 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
328 pf_id);
329}
330
331static inline void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
332 u8 enable)
333{
334 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
335 enable);
336 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
337 enable);
338 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
339 enable);
340 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
341 enable);
342}
343
344static inline void storm_memset_eq_data(struct bnx2x *bp,
345 struct event_ring_data *eq_data,
346 u16 pfid)
347{
348 size_t size = sizeof(struct event_ring_data);
349
350 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid);
351
352 __storm_memset_struct(bp, addr, size, (u32 *)eq_data);
353}
354
355static inline void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod,
356 u16 pfid)
357{
358 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid);
359 REG_WR16(bp, addr, eq_prod);
360}
361
362static inline void storm_memset_hc_timeout(struct bnx2x *bp, u8 port,
363 u16 fw_sb_id, u8 sb_index,
364 u8 ticks)
365{
366
f2e0899f
DK		 367 int index_offset = CHIP_IS_E2(bp) ?
368 offsetof(struct hc_status_block_data_e2, index_data) :
523224a3
DK		 369 offsetof(struct hc_status_block_data_e1x, index_data);
370 u32 addr = BAR_CSTRORM_INTMEM +
371 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
372 index_offset +
373 sizeof(struct hc_index_data)*sb_index +
374 offsetof(struct hc_index_data, timeout);
375 REG_WR8(bp, addr, ticks);
376 DP(NETIF_MSG_HW, "port %x fw_sb_id %d sb_index %d ticks %d\n",
377 port, fw_sb_id, sb_index, ticks);
378}
379static inline void storm_memset_hc_disable(struct bnx2x *bp, u8 port,
380 u16 fw_sb_id, u8 sb_index,
381 u8 disable)
382{
383 u32 enable_flag = disable ? 0 : (1 << HC_INDEX_DATA_HC_ENABLED_SHIFT);
f2e0899f
DK		 384 int index_offset = CHIP_IS_E2(bp) ?
385 offsetof(struct hc_status_block_data_e2, index_data) :
523224a3
DK		 386 offsetof(struct hc_status_block_data_e1x, index_data);
387 u32 addr = BAR_CSTRORM_INTMEM +
388 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
389 index_offset +
390 sizeof(struct hc_index_data)*sb_index +
391 offsetof(struct hc_index_data, flags);
392 u16 flags = REG_RD16(bp, addr);
393 /* clear and set */
394 flags &= ~HC_INDEX_DATA_HC_ENABLED;
395 flags |= enable_flag;
396 REG_WR16(bp, addr, flags);
397 DP(NETIF_MSG_HW, "port %x fw_sb_id %d sb_index %d disable %d\n",
398 port, fw_sb_id, sb_index, disable);
399}
400
a2fbb9ea
ET		 401/* used only at init
402 * locking is done by mcp
403 */
8d96286a 404static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
a2fbb9ea
ET		 405{
406 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
407 pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
408 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
409 PCICFG_VENDOR_ID_OFFSET);
410}
411
a2fbb9ea
ET		 412static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
413{
414 u32 val;
415
416 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
417 pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
418 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
419 PCICFG_VENDOR_ID_OFFSET);
420
421 return val;
422}
a2fbb9ea 423
f2e0899f
DK		 424#define DMAE_DP_SRC_GRC "grc src_addr [%08x]"
425#define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]"
426#define DMAE_DP_DST_GRC "grc dst_addr [%08x]"
427#define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]"
428#define DMAE_DP_DST_NONE "dst_addr [none]"
429
8d96286a 430static void bnx2x_dp_dmae(struct bnx2x *bp, struct dmae_command *dmae,
431 int msglvl)
f2e0899f
DK		 432{
433 u32 src_type = dmae->opcode & DMAE_COMMAND_SRC;
434
435 switch (dmae->opcode & DMAE_COMMAND_DST) {
436 case DMAE_CMD_DST_PCI:
437 if (src_type == DMAE_CMD_SRC_PCI)
438 DP(msglvl, "DMAE: opcode 0x%08x\n"
439 "src [%x:%08x], len [%d*4], dst [%x:%08x]\n"
440 "comp_addr [%x:%08x], comp_val 0x%08x\n",
441 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
442 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
443 dmae->comp_addr_hi, dmae->comp_addr_lo,
444 dmae->comp_val);
445 else
446 DP(msglvl, "DMAE: opcode 0x%08x\n"
447 "src [%08x], len [%d*4], dst [%x:%08x]\n"
448 "comp_addr [%x:%08x], comp_val 0x%08x\n",
449 dmae->opcode, dmae->src_addr_lo >> 2,
450 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
451 dmae->comp_addr_hi, dmae->comp_addr_lo,
452 dmae->comp_val);
453 break;
454 case DMAE_CMD_DST_GRC:
455 if (src_type == DMAE_CMD_SRC_PCI)
456 DP(msglvl, "DMAE: opcode 0x%08x\n"
457 "src [%x:%08x], len [%d*4], dst_addr [%08x]\n"
458 "comp_addr [%x:%08x], comp_val 0x%08x\n",
459 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
460 dmae->len, dmae->dst_addr_lo >> 2,
461 dmae->comp_addr_hi, dmae->comp_addr_lo,
462 dmae->comp_val);
463 else
464 DP(msglvl, "DMAE: opcode 0x%08x\n"
465 "src [%08x], len [%d*4], dst [%08x]\n"
466 "comp_addr [%x:%08x], comp_val 0x%08x\n",
467 dmae->opcode, dmae->src_addr_lo >> 2,
468 dmae->len, dmae->dst_addr_lo >> 2,
469 dmae->comp_addr_hi, dmae->comp_addr_lo,
470 dmae->comp_val);
471 break;
472 default:
473 if (src_type == DMAE_CMD_SRC_PCI)
474 DP(msglvl, "DMAE: opcode 0x%08x\n"
475 DP_LEVEL "src_addr [%x:%08x] len [%d * 4] "
476 "dst_addr [none]\n"
477 DP_LEVEL "comp_addr [%x:%08x] comp_val 0x%08x\n",
478 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
479 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
480 dmae->comp_val);
481 else
482 DP(msglvl, "DMAE: opcode 0x%08x\n"
483 DP_LEVEL "src_addr [%08x] len [%d * 4] "
484 "dst_addr [none]\n"
485 DP_LEVEL "comp_addr [%x:%08x] comp_val 0x%08x\n",
486 dmae->opcode, dmae->src_addr_lo >> 2,
487 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
488 dmae->comp_val);
489 break;
490 }
491
492}
493
6c719d00 494const u32 dmae_reg_go_c[] = {
a2fbb9ea
ET		 495 DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3,
496 DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7,
497 DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11,
498 DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15
499};
500
501/* copy command into DMAE command memory and set DMAE command go */
6c719d00 502void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx)
a2fbb9ea
ET		 503{
504 u32 cmd_offset;
505 int i;
506
507 cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
508 for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
509 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
510
ad8d3948
EG		 511 DP(BNX2X_MSG_OFF, "DMAE cmd[%d].%d (0x%08x) : 0x%08x\n",
512 idx, i, cmd_offset + i*4, *(((u32 *)dmae) + i));
a2fbb9ea
ET		 513 }
514 REG_WR(bp, dmae_reg_go_c[idx], 1);
515}
516
f2e0899f 517u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type)
a2fbb9ea 518{
f2e0899f
DK		 519 return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
520 DMAE_CMD_C_ENABLE);
521}
ad8d3948 522
f2e0899f
DK		 523u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode)
524{
525 return opcode & ~DMAE_CMD_SRC_RESET;
526}
ad8d3948 527
f2e0899f
DK		 528u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
529 bool with_comp, u8 comp_type)
530{
531 u32 opcode = 0;
532
533 opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
534 (dst_type << DMAE_COMMAND_DST_SHIFT));
ad8d3948 535
f2e0899f
DK		 536 opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET);
537
538 opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
539 opcode |= ((BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT) |
540 (BP_E1HVN(bp) << DMAE_COMMAND_DST_VN_SHIFT));
541 opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
a2fbb9ea 542
a2fbb9ea 543#ifdef __BIG_ENDIAN
f2e0899f 544 opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
a2fbb9ea 545#else
f2e0899f 546 opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
a2fbb9ea 547#endif
f2e0899f
DK		 548 if (with_comp)
549 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
550 return opcode;
551}
552
8d96286a 553static void bnx2x_prep_dmae_with_comp(struct bnx2x *bp,
554 struct dmae_command *dmae,
555 u8 src_type, u8 dst_type)
f2e0899f
DK		 556{
557 memset(dmae, 0, sizeof(struct dmae_command));
558
559 /* set the opcode */
560 dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type,
561 true, DMAE_COMP_PCI);
562
563 /* fill in the completion parameters */
564 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
565 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
566 dmae->comp_val = DMAE_COMP_VAL;
567}
568
569/* issue a dmae command over the init-channel and wailt for completion */
8d96286a 570static int bnx2x_issue_dmae_with_comp(struct bnx2x *bp,
571 struct dmae_command *dmae)
f2e0899f
DK		 572{
573 u32 *wb_comp = bnx2x_sp(bp, wb_comp);
574 int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 40;
575 int rc = 0;
576
577 DP(BNX2X_MSG_OFF, "data before [0x%08x 0x%08x 0x%08x 0x%08x]\n",
a2fbb9ea
ET		 578 bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
579 bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
a2fbb9ea 580
f2e0899f 581 /* lock the dmae channel */
6e30dd4e 582 spin_lock_bh(&bp->dmae_lock);
5ff7b6d4 583
f2e0899f 584 /* reset completion */
a2fbb9ea
ET		 585 *wb_comp = 0;
586
f2e0899f
DK		 587 /* post the command on the channel used for initializations */
588 bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
a2fbb9ea 589
f2e0899f 590 /* wait for completion */
a2fbb9ea 591 udelay(5);
f2e0899f 592 while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
ad8d3948
EG		 593 DP(BNX2X_MSG_OFF, "wb_comp 0x%08x\n", *wb_comp);
594
ad8d3948 595 if (!cnt) {
c3eefaf6 596 BNX2X_ERR("DMAE timeout!\n");
f2e0899f
DK		 597 rc = DMAE_TIMEOUT;
598 goto unlock;
a2fbb9ea 599 }
ad8d3948 600 cnt--;
f2e0899f 601 udelay(50);
a2fbb9ea 602 }
f2e0899f
DK		 603 if (*wb_comp & DMAE_PCI_ERR_FLAG) {
604 BNX2X_ERR("DMAE PCI error!\n");
605 rc = DMAE_PCI_ERROR;
606 }
607
608 DP(BNX2X_MSG_OFF, "data after [0x%08x 0x%08x 0x%08x 0x%08x]\n",
609 bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
610 bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
ad8d3948 611
f2e0899f 612unlock:
6e30dd4e 613 spin_unlock_bh(&bp->dmae_lock);
f2e0899f
DK		 614 return rc;
615}
616
617void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
618 u32 len32)
619{
620 struct dmae_command dmae;
621
622 if (!bp->dmae_ready) {
623 u32 *data = bnx2x_sp(bp, wb_data[0]);
624
625 DP(BNX2X_MSG_OFF, "DMAE is not ready (dst_addr %08x len32 %d)"
626 " using indirect\n", dst_addr, len32);
627 bnx2x_init_ind_wr(bp, dst_addr, data, len32);
628 return;
629 }
630
631 /* set opcode and fixed command fields */
632 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
633
634 /* fill in addresses and len */
635 dmae.src_addr_lo = U64_LO(dma_addr);
636 dmae.src_addr_hi = U64_HI(dma_addr);
637 dmae.dst_addr_lo = dst_addr >> 2;
638 dmae.dst_addr_hi = 0;
639 dmae.len = len32;
640
641 bnx2x_dp_dmae(bp, &dmae, BNX2X_MSG_OFF);
642
643 /* issue the command and wait for completion */
644 bnx2x_issue_dmae_with_comp(bp, &dmae);
a2fbb9ea
ET		 645}
646
c18487ee 647void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
a2fbb9ea 648{
5ff7b6d4 649 struct dmae_command dmae;
ad8d3948
EG		 650
651 if (!bp->dmae_ready) {
652 u32 *data = bnx2x_sp(bp, wb_data[0]);
653 int i;
654
655 DP(BNX2X_MSG_OFF, "DMAE is not ready (src_addr %08x len32 %d)"
656 " using indirect\n", src_addr, len32);
657 for (i = 0; i < len32; i++)
658 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
659 return;
660 }
661
f2e0899f
DK		 662 /* set opcode and fixed command fields */
663 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
a2fbb9ea 664
f2e0899f 665 /* fill in addresses and len */
5ff7b6d4
EG		 666 dmae.src_addr_lo = src_addr >> 2;
667 dmae.src_addr_hi = 0;
668 dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
669 dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
670 dmae.len = len32;
ad8d3948 671
f2e0899f 672 bnx2x_dp_dmae(bp, &dmae, BNX2X_MSG_OFF);
ad8d3948 673
f2e0899f
DK		 674 /* issue the command and wait for completion */
675 bnx2x_issue_dmae_with_comp(bp, &dmae);
ad8d3948
EG		 676}
677
8d96286a 678static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
679 u32 addr, u32 len)
573f2035 680{
02e3c6cb 681 int dmae_wr_max = DMAE_LEN32_WR_MAX(bp);
573f2035
EG		 682 int offset = 0;
683
02e3c6cb 684 while (len > dmae_wr_max) {
573f2035 685 bnx2x_write_dmae(bp, phys_addr + offset,
02e3c6cb
VZ		 686 addr + offset, dmae_wr_max);
687 offset += dmae_wr_max * 4;
688 len -= dmae_wr_max;
573f2035
EG		 689 }
690
691 bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
692}
693
ad8d3948
EG		 694/* used only for slowpath so not inlined */
695static void bnx2x_wb_wr(struct bnx2x *bp, int reg, u32 val_hi, u32 val_lo)
696{
697 u32 wb_write[2];
698
699 wb_write[0] = val_hi;
700 wb_write[1] = val_lo;
701 REG_WR_DMAE(bp, reg, wb_write, 2);
a2fbb9ea 702}
a2fbb9ea 703
ad8d3948
EG		 704#ifdef USE_WB_RD
705static u64 bnx2x_wb_rd(struct bnx2x *bp, int reg)
706{
707 u32 wb_data[2];
708
709 REG_RD_DMAE(bp, reg, wb_data, 2);
710
711 return HILO_U64(wb_data[0], wb_data[1]);
712}
713#endif
714
a2fbb9ea
ET		 715static int bnx2x_mc_assert(struct bnx2x *bp)
716{
a2fbb9ea 717 char last_idx;
34f80b04
EG		 718 int i, rc = 0;
719 u32 row0, row1, row2, row3;
720
721 /* XSTORM */
722 last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM +
723 XSTORM_ASSERT_LIST_INDEX_OFFSET);
724 if (last_idx)
725 BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
726
727 /* print the asserts */
728 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
729
730 row0 = REG_RD(bp, BAR_XSTRORM_INTMEM +
731 XSTORM_ASSERT_LIST_OFFSET(i));
732 row1 = REG_RD(bp, BAR_XSTRORM_INTMEM +
733 XSTORM_ASSERT_LIST_OFFSET(i) + 4);
734 row2 = REG_RD(bp, BAR_XSTRORM_INTMEM +
735 XSTORM_ASSERT_LIST_OFFSET(i) + 8);
736 row3 = REG_RD(bp, BAR_XSTRORM_INTMEM +
737 XSTORM_ASSERT_LIST_OFFSET(i) + 12);
738
739 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
740 BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x"
741 " 0x%08x 0x%08x 0x%08x\n",
742 i, row3, row2, row1, row0);
743 rc++;
744 } else {
745 break;
746 }
747 }
748
749 /* TSTORM */
750 last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM +
751 TSTORM_ASSERT_LIST_INDEX_OFFSET);
752 if (last_idx)
753 BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
754
755 /* print the asserts */
756 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
757
758 row0 = REG_RD(bp, BAR_TSTRORM_INTMEM +
759 TSTORM_ASSERT_LIST_OFFSET(i));
760 row1 = REG_RD(bp, BAR_TSTRORM_INTMEM +
761 TSTORM_ASSERT_LIST_OFFSET(i) + 4);
762 row2 = REG_RD(bp, BAR_TSTRORM_INTMEM +
763 TSTORM_ASSERT_LIST_OFFSET(i) + 8);
764 row3 = REG_RD(bp, BAR_TSTRORM_INTMEM +
765 TSTORM_ASSERT_LIST_OFFSET(i) + 12);
766
767 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
768 BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x"
769 " 0x%08x 0x%08x 0x%08x\n",
770 i, row3, row2, row1, row0);
771 rc++;
772 } else {
773 break;
774 }
775 }
776
777 /* CSTORM */
778 last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM +
779 CSTORM_ASSERT_LIST_INDEX_OFFSET);
780 if (last_idx)
781 BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
782
783 /* print the asserts */
784 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
785
786 row0 = REG_RD(bp, BAR_CSTRORM_INTMEM +
787 CSTORM_ASSERT_LIST_OFFSET(i));
788 row1 = REG_RD(bp, BAR_CSTRORM_INTMEM +
789 CSTORM_ASSERT_LIST_OFFSET(i) + 4);
790 row2 = REG_RD(bp, BAR_CSTRORM_INTMEM +
791 CSTORM_ASSERT_LIST_OFFSET(i) + 8);
792 row3 = REG_RD(bp, BAR_CSTRORM_INTMEM +
793 CSTORM_ASSERT_LIST_OFFSET(i) + 12);
794
795 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
796 BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x"
797 " 0x%08x 0x%08x 0x%08x\n",
798 i, row3, row2, row1, row0);
799 rc++;
800 } else {
801 break;
802 }
803 }
804
805 /* USTORM */
806 last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM +
807 USTORM_ASSERT_LIST_INDEX_OFFSET);
808 if (last_idx)
809 BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
810
811 /* print the asserts */
812 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
813
814 row0 = REG_RD(bp, BAR_USTRORM_INTMEM +
815 USTORM_ASSERT_LIST_OFFSET(i));
816 row1 = REG_RD(bp, BAR_USTRORM_INTMEM +
817 USTORM_ASSERT_LIST_OFFSET(i) + 4);
818 row2 = REG_RD(bp, BAR_USTRORM_INTMEM +
819 USTORM_ASSERT_LIST_OFFSET(i) + 8);
820 row3 = REG_RD(bp, BAR_USTRORM_INTMEM +
821 USTORM_ASSERT_LIST_OFFSET(i) + 12);
822
823 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
824 BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x"
825 " 0x%08x 0x%08x 0x%08x\n",
826 i, row3, row2, row1, row0);
827 rc++;
828 } else {
829 break;
a2fbb9ea
ET		 830 }
831 }
34f80b04 832
a2fbb9ea
ET		 833 return rc;
834}
c14423fe 835
a2fbb9ea
ET		 836static void bnx2x_fw_dump(struct bnx2x *bp)
837{
cdaa7cb8 838 u32 addr;
a2fbb9ea 839 u32 mark, offset;
4781bfad 840 __be32 data[9];
a2fbb9ea 841 int word;
f2e0899f 842 u32 trace_shmem_base;
2145a920
VZ		 843 if (BP_NOMCP(bp)) {
844 BNX2X_ERR("NO MCP - can not dump\n");
845 return;
846 }
cdaa7cb8 847
f2e0899f
DK		 848 if (BP_PATH(bp) == 0)
849 trace_shmem_base = bp->common.shmem_base;
850 else
851 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr);
852 addr = trace_shmem_base - 0x0800 + 4;
cdaa7cb8 853 mark = REG_RD(bp, addr);
f2e0899f
DK		 854 mark = (CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH)
855 + ((mark + 0x3) & ~0x3) - 0x08000000;
7995c64e 856 pr_err("begin fw dump (mark 0x%x)\n", mark);
a2fbb9ea 857
7995c64e 858 pr_err("");
f2e0899f 859 for (offset = mark; offset <= trace_shmem_base; offset += 0x8*4) {
a2fbb9ea 860 for (word = 0; word < 8; word++)
cdaa7cb8 861 data[word] = htonl(REG_RD(bp, offset + 4*word));
a2fbb9ea 862 data[8] = 0x0;
7995c64e 863 pr_cont("%s", (char *)data);
a2fbb9ea 864 }
cdaa7cb8 865 for (offset = addr + 4; offset <= mark; offset += 0x8*4) {
a2fbb9ea 866 for (word = 0; word < 8; word++)
cdaa7cb8 867 data[word] = htonl(REG_RD(bp, offset + 4*word));
a2fbb9ea 868 data[8] = 0x0;
7995c64e 869 pr_cont("%s", (char *)data);
a2fbb9ea 870 }
7995c64e 871 pr_err("end of fw dump\n");
a2fbb9ea
ET		 872}
873
6c719d00 874void bnx2x_panic_dump(struct bnx2x *bp)
a2fbb9ea
ET		 875{
876 int i;
523224a3
DK		 877 u16 j;
878 struct hc_sp_status_block_data sp_sb_data;
879 int func = BP_FUNC(bp);
880#ifdef BNX2X_STOP_ON_ERROR
881 u16 start = 0, end = 0;
882#endif
a2fbb9ea 883
66e855f3
YG		 884 bp->stats_state = STATS_STATE_DISABLED;
885 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
886
a2fbb9ea
ET		 887 BNX2X_ERR("begin crash dump -----------------\n");
888
8440d2b6
EG		 889 /* Indices */
890 /* Common */
523224a3 891 BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x)"
cdaa7cb8 892 " spq_prod_idx(0x%x)\n",
523224a3
DK		 893 bp->def_idx, bp->def_att_idx,
894 bp->attn_state, bp->spq_prod_idx);
895 BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n",
896 bp->def_status_blk->atten_status_block.attn_bits,
897 bp->def_status_blk->atten_status_block.attn_bits_ack,
898 bp->def_status_blk->atten_status_block.status_block_id,
899 bp->def_status_blk->atten_status_block.attn_bits_index);
900 BNX2X_ERR(" def (");
901 for (i = 0; i < HC_SP_SB_MAX_INDICES; i++)
902 pr_cont("0x%x%s",
903 bp->def_status_blk->sp_sb.index_values[i],
904 (i == HC_SP_SB_MAX_INDICES - 1) ? ") " : " ");
905
906 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
907 *((u32 *)&sp_sb_data + i) = REG_RD(bp, BAR_CSTRORM_INTMEM +
908 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
909 i*sizeof(u32));
910
911 pr_cont("igu_sb_id(0x%x) igu_seg_id (0x%x) "
912 "pf_id(0x%x) vnic_id(0x%x) "
913 "vf_id(0x%x) vf_valid (0x%x)\n",
914 sp_sb_data.igu_sb_id,
915 sp_sb_data.igu_seg_id,
916 sp_sb_data.p_func.pf_id,
917 sp_sb_data.p_func.vnic_id,
918 sp_sb_data.p_func.vf_id,
919 sp_sb_data.p_func.vf_valid);
920
8440d2b6 921
ec6ba945 922 for_each_eth_queue(bp, i) {
a2fbb9ea 923 struct bnx2x_fastpath *fp = &bp->fp[i];
523224a3 924 int loop;
f2e0899f 925 struct hc_status_block_data_e2 sb_data_e2;
523224a3
DK		 926 struct hc_status_block_data_e1x sb_data_e1x;
927 struct hc_status_block_sm *hc_sm_p =
f2e0899f
DK		 928 CHIP_IS_E2(bp) ?
929 sb_data_e2.common.state_machine :
523224a3
DK		 930 sb_data_e1x.common.state_machine;
931 struct hc_index_data *hc_index_p =
f2e0899f
DK		 932 CHIP_IS_E2(bp) ?
933 sb_data_e2.index_data :
523224a3
DK		 934 sb_data_e1x.index_data;
935 int data_size;
936 u32 *sb_data_p;
937
938 /* Rx */
cdaa7cb8 939 BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x)"
523224a3 940 " rx_comp_prod(0x%x)"
cdaa7cb8 941 " rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n",
8440d2b6 942 i, fp->rx_bd_prod, fp->rx_bd_cons,
523224a3 943 fp->rx_comp_prod,
66e855f3 944 fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
cdaa7cb8 945 BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x)"
523224a3 946 " fp_hc_idx(0x%x)\n",
8440d2b6 947 fp->rx_sge_prod, fp->last_max_sge,
523224a3 948 le16_to_cpu(fp->fp_hc_idx));
a2fbb9ea 949
523224a3 950 /* Tx */
cdaa7cb8
VZ		 951 BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x)"
952 " tx_bd_prod(0x%x) tx_bd_cons(0x%x)"
953 " *tx_cons_sb(0x%x)\n",
8440d2b6
EG		 954 i, fp->tx_pkt_prod, fp->tx_pkt_cons, fp->tx_bd_prod,
955 fp->tx_bd_cons, le16_to_cpu(*fp->tx_cons_sb));
523224a3 956
f2e0899f
DK		 957 loop = CHIP_IS_E2(bp) ?
958 HC_SB_MAX_INDICES_E2 : HC_SB_MAX_INDICES_E1X;
523224a3
DK		 959
960 /* host sb data */
961
ec6ba945
VZ		 962#ifdef BCM_CNIC
963 if (IS_FCOE_FP(fp))
964 continue;
965#endif
523224a3
DK		 966 BNX2X_ERR(" run indexes (");
967 for (j = 0; j < HC_SB_MAX_SM; j++)
968 pr_cont("0x%x%s",
969 fp->sb_running_index[j],
970 (j == HC_SB_MAX_SM - 1) ? ")" : " ");
971
972 BNX2X_ERR(" indexes (");
973 for (j = 0; j < loop; j++)
974 pr_cont("0x%x%s",
975 fp->sb_index_values[j],
976 (j == loop - 1) ? ")" : " ");
977 /* fw sb data */
f2e0899f
DK		 978 data_size = CHIP_IS_E2(bp) ?
979 sizeof(struct hc_status_block_data_e2) :
523224a3
DK		 980 sizeof(struct hc_status_block_data_e1x);
981 data_size /= sizeof(u32);
f2e0899f
DK		 982 sb_data_p = CHIP_IS_E2(bp) ?
983 (u32 *)&sb_data_e2 :
984 (u32 *)&sb_data_e1x;
523224a3
DK		 985 /* copy sb data in here */
986 for (j = 0; j < data_size; j++)
987 *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +
988 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) +
989 j * sizeof(u32));
990
f2e0899f
DK		 991 if (CHIP_IS_E2(bp)) {
992 pr_cont("pf_id(0x%x) vf_id (0x%x) vf_valid(0x%x) "
993 "vnic_id(0x%x) same_igu_sb_1b(0x%x)\n",
994 sb_data_e2.common.p_func.pf_id,
995 sb_data_e2.common.p_func.vf_id,
996 sb_data_e2.common.p_func.vf_valid,
997 sb_data_e2.common.p_func.vnic_id,
998 sb_data_e2.common.same_igu_sb_1b);
999 } else {
1000 pr_cont("pf_id(0x%x) vf_id (0x%x) vf_valid(0x%x) "
1001 "vnic_id(0x%x) same_igu_sb_1b(0x%x)\n",
1002 sb_data_e1x.common.p_func.pf_id,
1003 sb_data_e1x.common.p_func.vf_id,
1004 sb_data_e1x.common.p_func.vf_valid,
1005 sb_data_e1x.common.p_func.vnic_id,
1006 sb_data_e1x.common.same_igu_sb_1b);
1007 }
523224a3
DK		 1008
1009 /* SB_SMs data */
1010 for (j = 0; j < HC_SB_MAX_SM; j++) {
1011 pr_cont("SM[%d] __flags (0x%x) "
1012 "igu_sb_id (0x%x) igu_seg_id(0x%x) "
1013 "time_to_expire (0x%x) "
1014 "timer_value(0x%x)\n", j,
1015 hc_sm_p[j].__flags,
1016 hc_sm_p[j].igu_sb_id,
1017 hc_sm_p[j].igu_seg_id,
1018 hc_sm_p[j].time_to_expire,
1019 hc_sm_p[j].timer_value);
1020 }
1021
1022 /* Indecies data */
1023 for (j = 0; j < loop; j++) {
1024 pr_cont("INDEX[%d] flags (0x%x) "
1025 "timeout (0x%x)\n", j,
1026 hc_index_p[j].flags,
1027 hc_index_p[j].timeout);
1028 }
8440d2b6 1029 }
a2fbb9ea 1030
523224a3 1031#ifdef BNX2X_STOP_ON_ERROR
8440d2b6
EG		 1032 /* Rings */
1033 /* Rx */
ec6ba945 1034 for_each_rx_queue(bp, i) {
8440d2b6 1035 struct bnx2x_fastpath *fp = &bp->fp[i];
a2fbb9ea
ET		 1036
1037 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
1038 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
8440d2b6 1039 for (j = start; j != end; j = RX_BD(j + 1)) {
a2fbb9ea
ET		 1040 u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
1041 struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
1042
c3eefaf6
EG		 1043 BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n",
1044 i, j, rx_bd[1], rx_bd[0], sw_bd->skb);
a2fbb9ea
ET		 1045 }
1046
3196a88a
EG		 1047 start = RX_SGE(fp->rx_sge_prod);
1048 end = RX_SGE(fp->last_max_sge);
8440d2b6 1049 for (j = start; j != end; j = RX_SGE(j + 1)) {
7a9b2557
VZ		 1050 u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
1051 struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
1052
c3eefaf6
EG		 1053 BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n",
1054 i, j, rx_sge[1], rx_sge[0], sw_page->page);
7a9b2557
VZ		 1055 }
1056
a2fbb9ea
ET		 1057 start = RCQ_BD(fp->rx_comp_cons - 10);
1058 end = RCQ_BD(fp->rx_comp_cons + 503);
8440d2b6 1059 for (j = start; j != end; j = RCQ_BD(j + 1)) {
a2fbb9ea
ET		 1060 u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
1061
c3eefaf6
EG		 1062 BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
1063 i, j, cqe[0], cqe[1], cqe[2], cqe[3]);
a2fbb9ea
ET		 1064 }
1065 }
1066
8440d2b6 1067 /* Tx */
ec6ba945 1068 for_each_tx_queue(bp, i) {
8440d2b6
EG		 1069 struct bnx2x_fastpath *fp = &bp->fp[i];
1070
1071 start = TX_BD(le16_to_cpu(*fp->tx_cons_sb) - 10);
1072 end = TX_BD(le16_to_cpu(*fp->tx_cons_sb) + 245);
1073 for (j = start; j != end; j = TX_BD(j + 1)) {
1074 struct sw_tx_bd *sw_bd = &fp->tx_buf_ring[j];
1075
c3eefaf6
EG		 1076 BNX2X_ERR("fp%d: packet[%x]=[%p,%x]\n",
1077 i, j, sw_bd->skb, sw_bd->first_bd);
8440d2b6
EG		 1078 }
1079
1080 start = TX_BD(fp->tx_bd_cons - 10);
1081 end = TX_BD(fp->tx_bd_cons + 254);
1082 for (j = start; j != end; j = TX_BD(j + 1)) {
1083 u32 *tx_bd = (u32 *)&fp->tx_desc_ring[j];
1084
c3eefaf6
EG		 1085 BNX2X_ERR("fp%d: tx_bd[%x]=[%x:%x:%x:%x]\n",
1086 i, j, tx_bd[0], tx_bd[1], tx_bd[2], tx_bd[3]);
8440d2b6
EG		 1087 }
1088 }
523224a3 1089#endif
34f80b04 1090 bnx2x_fw_dump(bp);
a2fbb9ea
ET		 1091 bnx2x_mc_assert(bp);
1092 BNX2X_ERR("end crash dump -----------------\n");
a2fbb9ea
ET		 1093}
1094
f2e0899f 1095static void bnx2x_hc_int_enable(struct bnx2x *bp)
a2fbb9ea 1096{
34f80b04 1097 int port = BP_PORT(bp);
a2fbb9ea
ET		 1098 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1099 u32 val = REG_RD(bp, addr);
1100 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
8badd27a 1101 int msi = (bp->flags & USING_MSI_FLAG) ? 1 : 0;
a2fbb9ea
ET		 1102
1103 if (msix) {
8badd27a
EG		 1104 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1105 HC_CONFIG_0_REG_INT_LINE_EN_0);
a2fbb9ea
ET		 1106 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1107 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
8badd27a
EG		 1108 } else if (msi) {
1109 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
1110 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1111 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1112 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
a2fbb9ea
ET		 1113 } else {
1114 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
615f8fd9 1115 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
a2fbb9ea
ET		 1116 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1117 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
615f8fd9 1118
a0fd065c
DK		 1119 if (!CHIP_IS_E1(bp)) {
1120 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n",
1121 val, port, addr);
615f8fd9 1122
a0fd065c 1123 REG_WR(bp, addr, val);
615f8fd9 1124
a0fd065c
DK		 1125 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
1126 }
a2fbb9ea
ET		 1127 }
1128
a0fd065c
DK		 1129 if (CHIP_IS_E1(bp))
1130 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF);
1131
8badd27a
EG		 1132 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x) mode %s\n",
1133 val, port, addr, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
a2fbb9ea
ET		 1134
1135 REG_WR(bp, addr, val);
37dbbf32
EG		 1136 /*
1137 * Ensure that HC_CONFIG is written before leading/trailing edge config
1138 */
1139 mmiowb();
1140 barrier();
34f80b04 1141
f2e0899f 1142 if (!CHIP_IS_E1(bp)) {
34f80b04 1143 /* init leading/trailing edge */
fb3bff17 1144 if (IS_MF(bp)) {
8badd27a 1145 val = (0xee0f | (1 << (BP_E1HVN(bp) + 4)));
34f80b04 1146 if (bp->port.pmf)
4acac6a5
EG		 1147 /* enable nig and gpio3 attention */
1148 val |= 0x1100;
34f80b04
EG		 1149 } else
1150 val = 0xffff;
1151
1152 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
1153 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
1154 }
37dbbf32
EG		 1155
1156 /* Make sure that interrupts are indeed enabled from here on */
1157 mmiowb();
a2fbb9ea
ET		 1158}
1159
f2e0899f
DK		 1160static void bnx2x_igu_int_enable(struct bnx2x *bp)
1161{
1162 u32 val;
1163 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1164 int msi = (bp->flags & USING_MSI_FLAG) ? 1 : 0;
1165
1166 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1167
1168 if (msix) {
1169 val &= ~(IGU_PF_CONF_INT_LINE_EN |
1170 IGU_PF_CONF_SINGLE_ISR_EN);
1171 val |= (IGU_PF_CONF_FUNC_EN |
1172 IGU_PF_CONF_MSI_MSIX_EN |
1173 IGU_PF_CONF_ATTN_BIT_EN);
1174 } else if (msi) {
1175 val &= ~IGU_PF_CONF_INT_LINE_EN;
1176 val |= (IGU_PF_CONF_FUNC_EN |
1177 IGU_PF_CONF_MSI_MSIX_EN |
1178 IGU_PF_CONF_ATTN_BIT_EN |
1179 IGU_PF_CONF_SINGLE_ISR_EN);
1180 } else {
1181 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
1182 val |= (IGU_PF_CONF_FUNC_EN |
1183 IGU_PF_CONF_INT_LINE_EN |
1184 IGU_PF_CONF_ATTN_BIT_EN |
1185 IGU_PF_CONF_SINGLE_ISR_EN);
1186 }
1187
1188 DP(NETIF_MSG_INTR, "write 0x%x to IGU mode %s\n",
1189 val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1190
1191 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1192
1193 barrier();
1194
1195 /* init leading/trailing edge */
1196 if (IS_MF(bp)) {
1197 val = (0xee0f | (1 << (BP_E1HVN(bp) + 4)));
1198 if (bp->port.pmf)
1199 /* enable nig and gpio3 attention */
1200 val |= 0x1100;
1201 } else
1202 val = 0xffff;
1203
1204 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
1205 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
1206
1207 /* Make sure that interrupts are indeed enabled from here on */
1208 mmiowb();
1209}
1210
1211void bnx2x_int_enable(struct bnx2x *bp)
1212{
1213 if (bp->common.int_block == INT_BLOCK_HC)
1214 bnx2x_hc_int_enable(bp);
1215 else
1216 bnx2x_igu_int_enable(bp);
1217}
1218
1219static void bnx2x_hc_int_disable(struct bnx2x *bp)
a2fbb9ea 1220{
34f80b04 1221 int port = BP_PORT(bp);
a2fbb9ea
ET		 1222 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1223 u32 val = REG_RD(bp, addr);
1224
a0fd065c
DK		 1225 /*
1226 * in E1 we must use only PCI configuration space to disable
1227 * MSI/MSIX capablility
1228 * It's forbitten to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
1229 */
1230 if (CHIP_IS_E1(bp)) {
1231 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on
1232 * Use mask register to prevent from HC sending interrupts
1233 * after we exit the function
1234 */
1235 REG_WR(bp, HC_REG_INT_MASK + port*4, 0);
1236
1237 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1238 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1239 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1240 } else
1241 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1242 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1243 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1244 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
a2fbb9ea
ET		 1245
1246 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n",
1247 val, port, addr);
1248
8badd27a
EG		 1249 /* flush all outstanding writes */
1250 mmiowb();
1251
a2fbb9ea
ET		 1252 REG_WR(bp, addr, val);
1253 if (REG_RD(bp, addr) != val)
1254 BNX2X_ERR("BUG! proper val not read from IGU!\n");
1255}
1256
f2e0899f
DK		 1257static void bnx2x_igu_int_disable(struct bnx2x *bp)
1258{
1259 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1260
1261 val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
1262 IGU_PF_CONF_INT_LINE_EN |
1263 IGU_PF_CONF_ATTN_BIT_EN);
1264
1265 DP(NETIF_MSG_INTR, "write %x to IGU\n", val);
1266
1267 /* flush all outstanding writes */
1268 mmiowb();
1269
1270 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1271 if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)
1272 BNX2X_ERR("BUG! proper val not read from IGU!\n");
1273}
1274
8d96286a 1275static void bnx2x_int_disable(struct bnx2x *bp)
f2e0899f
DK		 1276{
1277 if (bp->common.int_block == INT_BLOCK_HC)
1278 bnx2x_hc_int_disable(bp);
1279 else
1280 bnx2x_igu_int_disable(bp);
1281}
1282
9f6c9258 1283void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
a2fbb9ea 1284{
a2fbb9ea 1285 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
8badd27a 1286 int i, offset;
a2fbb9ea 1287
34f80b04 1288 /* disable interrupt handling */
a2fbb9ea 1289 atomic_inc(&bp->intr_sem);
e1510706
EG		 1290 smp_wmb(); /* Ensure that bp->intr_sem update is SMP-safe */
1291
f8ef6e44
YG		 1292 if (disable_hw)
1293 /* prevent the HW from sending interrupts */
1294 bnx2x_int_disable(bp);
a2fbb9ea
ET		 1295
1296 /* make sure all ISRs are done */
1297 if (msix) {
8badd27a
EG		 1298 synchronize_irq(bp->msix_table[0].vector);
1299 offset = 1;
37b091ba
MC		 1300#ifdef BCM_CNIC
1301 offset++;
1302#endif
ec6ba945 1303 for_each_eth_queue(bp, i)
8badd27a 1304 synchronize_irq(bp->msix_table[i + offset].vector);
a2fbb9ea
ET		 1305 } else
1306 synchronize_irq(bp->pdev->irq);
1307
1308 /* make sure sp_task is not running */
1cf167f2
EG		 1309 cancel_delayed_work(&bp->sp_task);
1310 flush_workqueue(bnx2x_wq);
a2fbb9ea
ET		 1311}
1312
34f80b04 1313/* fast path */
a2fbb9ea
ET		 1314
1315/*
34f80b04 1316 * General service functions
a2fbb9ea
ET		 1317 */
1318
72fd0718
VZ		 1319/* Return true if succeeded to acquire the lock */
1320static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
1321{
1322 u32 lock_status;
1323 u32 resource_bit = (1 << resource);
1324 int func = BP_FUNC(bp);
1325 u32 hw_lock_control_reg;
1326
1327 DP(NETIF_MSG_HW, "Trying to take a lock on resource %d\n", resource);
1328
1329 /* Validating that the resource is within range */
1330 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1331 DP(NETIF_MSG_HW,
1332 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1333 resource, HW_LOCK_MAX_RESOURCE_VALUE);
0fdf4d09 1334 return false;
72fd0718
VZ		 1335 }
1336
1337 if (func <= 5)
1338 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1339 else
1340 hw_lock_control_reg =
1341 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1342
1343 /* Try to acquire the lock */
1344 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1345 lock_status = REG_RD(bp, hw_lock_control_reg);
1346 if (lock_status & resource_bit)
1347 return true;
1348
1349 DP(NETIF_MSG_HW, "Failed to get a lock on resource %d\n", resource);
1350 return false;
1351}
1352
993ac7b5
MC		 1353#ifdef BCM_CNIC
1354static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid);
1355#endif
3196a88a 1356
9f6c9258 1357void bnx2x_sp_event(struct bnx2x_fastpath *fp,
a2fbb9ea
ET		 1358 union eth_rx_cqe *rr_cqe)
1359{
1360 struct bnx2x *bp = fp->bp;
1361 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1362 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1363
34f80b04 1364 DP(BNX2X_MSG_SP,
a2fbb9ea 1365 "fp %d cid %d got ramrod #%d state is %x type is %d\n",
0626b899 1366 fp->index, cid, command, bp->state,
34f80b04 1367 rr_cqe->ramrod_cqe.ramrod_type);
a2fbb9ea 1368
523224a3
DK		 1369 switch (command | fp->state) {
1370 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP | BNX2X_FP_STATE_OPENING):
1371 DP(NETIF_MSG_IFUP, "got MULTI[%d] setup ramrod\n", cid);
1372 fp->state = BNX2X_FP_STATE_OPEN;
a2fbb9ea
ET		 1373 break;
1374
523224a3
DK		 1375 case (RAMROD_CMD_ID_ETH_HALT | BNX2X_FP_STATE_HALTING):
1376 DP(NETIF_MSG_IFDOWN, "got MULTI[%d] halt ramrod\n", cid);
a2fbb9ea
ET		 1377 fp->state = BNX2X_FP_STATE_HALTED;
1378 break;
1379
523224a3
DK		 1380 case (RAMROD_CMD_ID_ETH_TERMINATE | BNX2X_FP_STATE_TERMINATING):
1381 DP(NETIF_MSG_IFDOWN, "got MULTI[%d] teminate ramrod\n", cid);
1382 fp->state = BNX2X_FP_STATE_TERMINATED;
a2fbb9ea
ET		 1383 break;
1384
523224a3
DK		 1385 default:
1386 BNX2X_ERR("unexpected MC reply (%d) "
1387 "fp[%d] state is %x\n",
1388 command, fp->index, fp->state);
993ac7b5 1389 break;
523224a3 1390 }
3196a88a 1391
8fe23fbd 1392 smp_mb__before_atomic_inc();
6e30dd4e 1393 atomic_inc(&bp->cq_spq_left);
523224a3
DK		 1394 /* push the change in fp->state and towards the memory */
1395 smp_wmb();
49d66772 1396
523224a3 1397 return;
a2fbb9ea
ET		 1398}
1399
9f6c9258 1400irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
a2fbb9ea 1401{
555f6c78 1402 struct bnx2x *bp = netdev_priv(dev_instance);
a2fbb9ea 1403 u16 status = bnx2x_ack_int(bp);
34f80b04 1404 u16 mask;
ca00392c 1405 int i;
a2fbb9ea 1406
34f80b04 1407 /* Return here if interrupt is shared and it's not for us */
a2fbb9ea
ET		 1408 if (unlikely(status == 0)) {
1409 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1410 return IRQ_NONE;
1411 }
f5372251 1412 DP(NETIF_MSG_INTR, "got an interrupt status 0x%x\n", status);
a2fbb9ea 1413
34f80b04 1414 /* Return here if interrupt is disabled */
a2fbb9ea
ET		 1415 if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
1416 DP(NETIF_MSG_INTR, "called but intr_sem not 0, returning\n");
1417 return IRQ_HANDLED;
1418 }
1419
3196a88a
EG		 1420#ifdef BNX2X_STOP_ON_ERROR
1421 if (unlikely(bp->panic))
1422 return IRQ_HANDLED;
1423#endif
1424
ec6ba945 1425 for_each_eth_queue(bp, i) {
ca00392c 1426 struct bnx2x_fastpath *fp = &bp->fp[i];
a2fbb9ea 1427
523224a3 1428 mask = 0x2 << (fp->index + CNIC_CONTEXT_USE);
ca00392c 1429 if (status & mask) {
54b9ddaa
VZ		 1430 /* Handle Rx and Tx according to SB id */
1431 prefetch(fp->rx_cons_sb);
54b9ddaa 1432 prefetch(fp->tx_cons_sb);
523224a3 1433 prefetch(&fp->sb_running_index[SM_RX_ID]);
54b9ddaa 1434 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
ca00392c
EG		 1435 status &= ~mask;
1436 }
a2fbb9ea
ET		 1437 }
1438
993ac7b5 1439#ifdef BCM_CNIC
523224a3 1440 mask = 0x2;
993ac7b5
MC		 1441 if (status & (mask | 0x1)) {
1442 struct cnic_ops *c_ops = NULL;
1443
1444 rcu_read_lock();
1445 c_ops = rcu_dereference(bp->cnic_ops);
1446 if (c_ops)
1447 c_ops->cnic_handler(bp->cnic_data, NULL);
1448 rcu_read_unlock();
1449
1450 status &= ~mask;
1451 }
1452#endif
a2fbb9ea 1453
34f80b04 1454 if (unlikely(status & 0x1)) {
1cf167f2 1455 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
a2fbb9ea
ET		 1456
1457 status &= ~0x1;
1458 if (!status)
1459 return IRQ_HANDLED;
1460 }
1461
cdaa7cb8
VZ		 1462 if (unlikely(status))
1463 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
34f80b04 1464 status);
a2fbb9ea 1465
c18487ee 1466 return IRQ_HANDLED;
a2fbb9ea
ET		 1467}
1468
c18487ee 1469/* end of fast path */
a2fbb9ea 1470
a2fbb9ea 1471
c18487ee
YR		 1472/* Link */
1473
1474/*
1475 * General service functions
1476 */
a2fbb9ea 1477
9f6c9258 1478int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
c18487ee
YR		 1479{
1480 u32 lock_status;
1481 u32 resource_bit = (1 << resource);
4a37fb66
YG		 1482 int func = BP_FUNC(bp);
1483 u32 hw_lock_control_reg;
c18487ee 1484 int cnt;
a2fbb9ea 1485
c18487ee
YR		 1486 /* Validating that the resource is within range */
1487 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1488 DP(NETIF_MSG_HW,
1489 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1490 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1491 return -EINVAL;
1492 }
a2fbb9ea 1493
4a37fb66
YG		 1494 if (func <= 5) {
1495 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1496 } else {
1497 hw_lock_control_reg =
1498 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1499 }
1500
c18487ee 1501 /* Validating that the resource is not already taken */
4a37fb66 1502 lock_status = REG_RD(bp, hw_lock_control_reg);
c18487ee
YR		 1503 if (lock_status & resource_bit) {
1504 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n",
1505 lock_status, resource_bit);
1506 return -EEXIST;
1507 }
a2fbb9ea 1508
46230476
EG		 1509 /* Try for 5 second every 5ms */
1510 for (cnt = 0; cnt < 1000; cnt++) {
c18487ee 1511 /* Try to acquire the lock */
4a37fb66
YG		 1512 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1513 lock_status = REG_RD(bp, hw_lock_control_reg);
c18487ee
YR		 1514 if (lock_status & resource_bit)
1515 return 0;
a2fbb9ea 1516
c18487ee 1517 msleep(5);
a2fbb9ea 1518 }
c18487ee
YR		 1519 DP(NETIF_MSG_HW, "Timeout\n");
1520 return -EAGAIN;
1521}
a2fbb9ea 1522
9f6c9258 1523int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
c18487ee
YR		 1524{
1525 u32 lock_status;
1526 u32 resource_bit = (1 << resource);
4a37fb66
YG		 1527 int func = BP_FUNC(bp);
1528 u32 hw_lock_control_reg;
a2fbb9ea 1529
72fd0718
VZ		 1530 DP(NETIF_MSG_HW, "Releasing a lock on resource %d\n", resource);
1531
c18487ee
YR		 1532 /* Validating that the resource is within range */
1533 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1534 DP(NETIF_MSG_HW,
1535 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1536 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1537 return -EINVAL;
1538 }
1539
4a37fb66
YG		 1540 if (func <= 5) {
1541 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1542 } else {
1543 hw_lock_control_reg =
1544 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1545 }
1546
c18487ee 1547 /* Validating that the resource is currently taken */
4a37fb66 1548 lock_status = REG_RD(bp, hw_lock_control_reg);
c18487ee
YR		 1549 if (!(lock_status & resource_bit)) {
1550 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n",
1551 lock_status, resource_bit);
1552 return -EFAULT;
a2fbb9ea
ET		 1553 }
1554
9f6c9258
DK		 1555 REG_WR(bp, hw_lock_control_reg, resource_bit);
1556 return 0;
c18487ee 1557}
a2fbb9ea 1558
9f6c9258 1559
4acac6a5
EG		 1560int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
1561{
1562 /* The GPIO should be swapped if swap register is set and active */
1563 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1564 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1565 int gpio_shift = gpio_num +
1566 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1567 u32 gpio_mask = (1 << gpio_shift);
1568 u32 gpio_reg;
1569 int value;
1570
1571 if (gpio_num > MISC_REGISTERS_GPIO_3) {
1572 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1573 return -EINVAL;
1574 }
1575
1576 /* read GPIO value */
1577 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
1578
1579 /* get the requested pin value */
1580 if ((gpio_reg & gpio_mask) == gpio_mask)
1581 value = 1;
1582 else
1583 value = 0;
1584
1585 DP(NETIF_MSG_LINK, "pin %d value 0x%x\n", gpio_num, value);
1586
1587 return value;
1588}
1589
17de50b7 1590int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
c18487ee
YR		 1591{
1592 /* The GPIO should be swapped if swap register is set and active */
1593 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
17de50b7 1594 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
c18487ee
YR		 1595 int gpio_shift = gpio_num +
1596 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1597 u32 gpio_mask = (1 << gpio_shift);
1598 u32 gpio_reg;
a2fbb9ea 1599
c18487ee
YR		 1600 if (gpio_num > MISC_REGISTERS_GPIO_3) {
1601 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1602 return -EINVAL;
1603 }
a2fbb9ea 1604
4a37fb66 1605 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
c18487ee
YR		 1606 /* read GPIO and mask except the float bits */
1607 gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
a2fbb9ea 1608
c18487ee
YR		 1609 switch (mode) {
1610 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
1611 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output low\n",
1612 gpio_num, gpio_shift);
1613 /* clear FLOAT and set CLR */
1614 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1615 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
1616 break;
a2fbb9ea 1617
c18487ee
YR		 1618 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
1619 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output high\n",
1620 gpio_num, gpio_shift);
1621 /* clear FLOAT and set SET */
1622 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1623 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
1624 break;
a2fbb9ea 1625
17de50b7 1626 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
c18487ee
YR		 1627 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> input\n",
1628 gpio_num, gpio_shift);
1629 /* set FLOAT */
1630 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1631 break;
a2fbb9ea 1632
c18487ee
YR		 1633 default:
1634 break;
a2fbb9ea
ET		 1635 }
1636
c18487ee 1637 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
4a37fb66 1638 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
f1410647 1639
c18487ee 1640 return 0;
a2fbb9ea
ET		 1641}
1642
4acac6a5
EG		 1643int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
1644{
1645 /* The GPIO should be swapped if swap register is set and active */
1646 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1647 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1648 int gpio_shift = gpio_num +
1649 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1650 u32 gpio_mask = (1 << gpio_shift);
1651 u32 gpio_reg;
1652
1653 if (gpio_num > MISC_REGISTERS_GPIO_3) {
1654 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1655 return -EINVAL;
1656 }
1657
1658 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1659 /* read GPIO int */
1660 gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);
1661
1662 switch (mode) {
1663 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
1664 DP(NETIF_MSG_LINK, "Clear GPIO INT %d (shift %d) -> "
1665 "output low\n", gpio_num, gpio_shift);
1666 /* clear SET and set CLR */
1667 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
1668 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
1669 break;
1670
1671 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
1672 DP(NETIF_MSG_LINK, "Set GPIO INT %d (shift %d) -> "
1673 "output high\n", gpio_num, gpio_shift);
1674 /* clear CLR and set SET */
1675 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
1676 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
1677 break;
1678
1679 default:
1680 break;
1681 }
1682
1683 REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg);
1684 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1685
1686 return 0;
1687}
1688
c18487ee 1689static int bnx2x_set_spio(struct bnx2x *bp, int spio_num, u32 mode)
a2fbb9ea 1690{
c18487ee
YR		 1691 u32 spio_mask = (1 << spio_num);
1692 u32 spio_reg;
a2fbb9ea 1693
c18487ee
YR		 1694 if ((spio_num < MISC_REGISTERS_SPIO_4) ||
1695 (spio_num > MISC_REGISTERS_SPIO_7)) {
1696 BNX2X_ERR("Invalid SPIO %d\n", spio_num);
1697 return -EINVAL;
a2fbb9ea
ET		 1698 }
1699
4a37fb66 1700 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
c18487ee
YR		 1701 /* read SPIO and mask except the float bits */
1702 spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_REGISTERS_SPIO_FLOAT);
a2fbb9ea 1703
c18487ee 1704 switch (mode) {
6378c025 1705 case MISC_REGISTERS_SPIO_OUTPUT_LOW:
c18487ee
YR		 1706 DP(NETIF_MSG_LINK, "Set SPIO %d -> output low\n", spio_num);
1707 /* clear FLOAT and set CLR */
1708 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
1709 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_CLR_POS);
1710 break;
a2fbb9ea 1711
6378c025 1712 case MISC_REGISTERS_SPIO_OUTPUT_HIGH:
c18487ee
YR		 1713 DP(NETIF_MSG_LINK, "Set SPIO %d -> output high\n", spio_num);
1714 /* clear FLOAT and set SET */
1715 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
1716 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_SET_POS);
1717 break;
a2fbb9ea 1718
c18487ee
YR		 1719 case MISC_REGISTERS_SPIO_INPUT_HI_Z:
1720 DP(NETIF_MSG_LINK, "Set SPIO %d -> input\n", spio_num);
1721 /* set FLOAT */
1722 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
1723 break;
a2fbb9ea 1724
c18487ee
YR		 1725 default:
1726 break;
a2fbb9ea
ET		 1727 }
1728
c18487ee 1729 REG_WR(bp, MISC_REG_SPIO, spio_reg);
4a37fb66 1730 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
c18487ee 1731
a2fbb9ea
ET		 1732 return 0;
1733}
1734
a22f0788
YR		 1735int bnx2x_get_link_cfg_idx(struct bnx2x *bp)
1736{
1737 u32 sel_phy_idx = 0;
1738 if (bp->link_vars.link_up) {
1739 sel_phy_idx = EXT_PHY1;
1740 /* In case link is SERDES, check if the EXT_PHY2 is the one */
1741 if ((bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) &&
1742 (bp->link_params.phy[EXT_PHY2].supported & SUPPORTED_FIBRE))
1743 sel_phy_idx = EXT_PHY2;
1744 } else {
1745
1746 switch (bnx2x_phy_selection(&bp->link_params)) {
1747 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
1748 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
1749 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
1750 sel_phy_idx = EXT_PHY1;
1751 break;
1752 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
1753 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
1754 sel_phy_idx = EXT_PHY2;
1755 break;
1756 }
1757 }
1758 /*
1759 * The selected actived PHY is always after swapping (in case PHY
1760 * swapping is enabled). So when swapping is enabled, we need to reverse
1761 * the configuration
1762 */
1763
1764 if (bp->link_params.multi_phy_config &
1765 PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
1766 if (sel_phy_idx == EXT_PHY1)
1767 sel_phy_idx = EXT_PHY2;
1768 else if (sel_phy_idx == EXT_PHY2)
1769 sel_phy_idx = EXT_PHY1;
1770 }
1771 return LINK_CONFIG_IDX(sel_phy_idx);
1772}
1773
9f6c9258 1774void bnx2x_calc_fc_adv(struct bnx2x *bp)
a2fbb9ea 1775{
a22f0788 1776 u8 cfg_idx = bnx2x_get_link_cfg_idx(bp);
ad33ea3a
EG		 1777 switch (bp->link_vars.ieee_fc &
1778 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
c18487ee 1779 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
a22f0788 1780 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
f85582f8 1781 ADVERTISED_Pause);
c18487ee 1782 break;
356e2385 1783
c18487ee 1784 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
a22f0788 1785 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
f85582f8 1786 ADVERTISED_Pause);
c18487ee 1787 break;
356e2385 1788
c18487ee 1789 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
a22f0788 1790 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
c18487ee 1791 break;
356e2385 1792
c18487ee 1793 default:
a22f0788 1794 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
f85582f8 1795 ADVERTISED_Pause);
c18487ee
YR		 1796 break;
1797 }
1798}
f1410647 1799
9f6c9258 1800u8 bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
c18487ee 1801{
19680c48
EG		 1802 if (!BP_NOMCP(bp)) {
1803 u8 rc;
a22f0788
YR		 1804 int cfx_idx = bnx2x_get_link_cfg_idx(bp);
1805 u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx];
19680c48 1806 /* Initialize link parameters structure variables */
8c99e7b0
YR		 1807 /* It is recommended to turn off RX FC for jumbo frames
1808 for better performance */
f2e0899f 1809 if ((CHIP_IS_E1x(bp)) && (bp->dev->mtu > 5000))
c0700f90 1810 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
8c99e7b0 1811 else
c0700f90 1812 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
a2fbb9ea 1813
4a37fb66 1814 bnx2x_acquire_phy_lock(bp);
b5bf9068 1815
a22f0788 1816 if (load_mode == LOAD_DIAG) {
de6eae1f 1817 bp->link_params.loopback_mode = LOOPBACK_XGXS;
a22f0788
YR		 1818 bp->link_params.req_line_speed[cfx_idx] = SPEED_10000;
1819 }
b5bf9068 1820
19680c48 1821 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
b5bf9068 1822
4a37fb66 1823 bnx2x_release_phy_lock(bp);
a2fbb9ea 1824
3c96c68b
EG		 1825 bnx2x_calc_fc_adv(bp);
1826
b5bf9068
EG		 1827 if (CHIP_REV_IS_SLOW(bp) && bp->link_vars.link_up) {
1828 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
19680c48 1829 bnx2x_link_report(bp);
b5bf9068 1830 }
a22f0788 1831 bp->link_params.req_line_speed[cfx_idx] = req_line_speed;
19680c48
EG		 1832 return rc;
1833 }
f5372251 1834 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
19680c48 1835 return -EINVAL;
a2fbb9ea
ET		 1836}
1837
9f6c9258 1838void bnx2x_link_set(struct bnx2x *bp)
a2fbb9ea 1839{
19680c48 1840 if (!BP_NOMCP(bp)) {
4a37fb66 1841 bnx2x_acquire_phy_lock(bp);
54c2fb78 1842 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
19680c48 1843 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
4a37fb66 1844 bnx2x_release_phy_lock(bp);
a2fbb9ea 1845
19680c48
EG		 1846 bnx2x_calc_fc_adv(bp);
1847 } else
f5372251 1848 BNX2X_ERR("Bootcode is missing - can not set link\n");
c18487ee 1849}
a2fbb9ea 1850
c18487ee
YR		 1851static void bnx2x__link_reset(struct bnx2x *bp)
1852{
19680c48 1853 if (!BP_NOMCP(bp)) {
4a37fb66 1854 bnx2x_acquire_phy_lock(bp);
589abe3a 1855 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
4a37fb66 1856 bnx2x_release_phy_lock(bp);
19680c48 1857 } else
f5372251 1858 BNX2X_ERR("Bootcode is missing - can not reset link\n");
c18487ee 1859}
a2fbb9ea 1860
a22f0788 1861u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes)
c18487ee 1862{
2145a920 1863 u8 rc = 0;
a2fbb9ea 1864
2145a920
VZ		 1865 if (!BP_NOMCP(bp)) {
1866 bnx2x_acquire_phy_lock(bp);
a22f0788
YR		 1867 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars,
1868 is_serdes);
2145a920
VZ		 1869 bnx2x_release_phy_lock(bp);
1870 } else
1871 BNX2X_ERR("Bootcode is missing - can not test link\n");
a2fbb9ea 1872
c18487ee
YR		 1873 return rc;
1874}
a2fbb9ea 1875
8a1c38d1 1876static void bnx2x_init_port_minmax(struct bnx2x *bp)
34f80b04 1877{
8a1c38d1
EG		 1878 u32 r_param = bp->link_vars.line_speed / 8;
1879 u32 fair_periodic_timeout_usec;
1880 u32 t_fair;
34f80b04 1881
8a1c38d1
EG		 1882 memset(&(bp->cmng.rs_vars), 0,
1883 sizeof(struct rate_shaping_vars_per_port));
1884 memset(&(bp->cmng.fair_vars), 0, sizeof(struct fairness_vars_per_port));
34f80b04 1885
8a1c38d1
EG		 1886 /* 100 usec in SDM ticks = 25 since each tick is 4 usec */
1887 bp->cmng.rs_vars.rs_periodic_timeout = RS_PERIODIC_TIMEOUT_USEC / 4;
34f80b04 1888
8a1c38d1
EG		 1889 /* this is the threshold below which no timer arming will occur
1890 1.25 coefficient is for the threshold to be a little bigger
1891 than the real time, to compensate for timer in-accuracy */
1892 bp->cmng.rs_vars.rs_threshold =
34f80b04
EG		 1893 (RS_PERIODIC_TIMEOUT_USEC * r_param * 5) / 4;
1894
8a1c38d1
EG		 1895 /* resolution of fairness timer */
1896 fair_periodic_timeout_usec = QM_ARB_BYTES / r_param;
1897 /* for 10G it is 1000usec. for 1G it is 10000usec. */
1898 t_fair = T_FAIR_COEF / bp->link_vars.line_speed;
34f80b04 1899
8a1c38d1
EG		 1900 /* this is the threshold below which we won't arm the timer anymore */
1901 bp->cmng.fair_vars.fair_threshold = QM_ARB_BYTES;
34f80b04 1902
8a1c38d1
EG		 1903 /* we multiply by 1e3/8 to get bytes/msec.
1904 We don't want the credits to pass a credit
1905 of the t_fair*FAIR_MEM (algorithm resolution) */
1906 bp->cmng.fair_vars.upper_bound = r_param * t_fair * FAIR_MEM;
1907 /* since each tick is 4 usec */
1908 bp->cmng.fair_vars.fairness_timeout = fair_periodic_timeout_usec / 4;
34f80b04
EG		 1909}
1910
2691d51d
EG		 1911/* Calculates the sum of vn_min_rates.
1912 It's needed for further normalizing of the min_rates.
1913 Returns:
1914 sum of vn_min_rates.
1915 or
1916 0 - if all the min_rates are 0.
1917 In the later case fainess algorithm should be deactivated.
1918 If not all min_rates are zero then those that are zeroes will be set to 1.
1919 */
1920static void bnx2x_calc_vn_weight_sum(struct bnx2x *bp)
1921{
1922 int all_zero = 1;
2691d51d
EG		 1923 int vn;
1924
1925 bp->vn_weight_sum = 0;
1926 for (vn = VN_0; vn < E1HVN_MAX; vn++) {
f2e0899f 1927 u32 vn_cfg = bp->mf_config[vn];
2691d51d
EG		 1928 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
1929 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
1930
1931 /* Skip hidden vns */
1932 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
1933 continue;
1934
1935 /* If min rate is zero - set it to 1 */
1936 if (!vn_min_rate)
1937 vn_min_rate = DEF_MIN_RATE;
1938 else
1939 all_zero = 0;
1940
1941 bp->vn_weight_sum += vn_min_rate;
1942 }
1943
1944 /* ... only if all min rates are zeros - disable fairness */
b015e3d1
EG		 1945 if (all_zero) {
1946 bp->cmng.flags.cmng_enables &=
1947 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
1948 DP(NETIF_MSG_IFUP, "All MIN values are zeroes"
1949 " fairness will be disabled\n");
1950 } else
1951 bp->cmng.flags.cmng_enables |=
1952 CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2691d51d
EG		 1953}
1954
f2e0899f 1955static void bnx2x_init_vn_minmax(struct bnx2x *bp, int vn)
34f80b04
EG		 1956{
1957 struct rate_shaping_vars_per_vn m_rs_vn;
1958 struct fairness_vars_per_vn m_fair_vn;
f2e0899f
DK		 1959 u32 vn_cfg = bp->mf_config[vn];
1960 int func = 2*vn + BP_PORT(bp);
34f80b04
EG		 1961 u16 vn_min_rate, vn_max_rate;
1962 int i;
1963
1964 /* If function is hidden - set min and max to zeroes */
1965 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
1966 vn_min_rate = 0;
1967 vn_max_rate = 0;
1968
1969 } else {
faa6fcbb
DK		 1970 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg);
1971
34f80b04
EG		 1972 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
1973 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
faa6fcbb
DK		 1974 /* If fairness is enabled (not all min rates are zeroes) and
1975 if current min rate is zero - set it to 1.
1976 This is a requirement of the algorithm. */
f2e0899f 1977 if (bp->vn_weight_sum && (vn_min_rate == 0))
34f80b04 1978 vn_min_rate = DEF_MIN_RATE;
faa6fcbb
DK		 1979
1980 if (IS_MF_SI(bp))
1981 /* maxCfg in percents of linkspeed */
1982 vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100;
1983 else
1984 /* maxCfg is absolute in 100Mb units */
1985 vn_max_rate = maxCfg * 100;
34f80b04 1986 }
f85582f8 1987
8a1c38d1 1988 DP(NETIF_MSG_IFUP,
b015e3d1 1989 "func %d: vn_min_rate %d vn_max_rate %d vn_weight_sum %d\n",
8a1c38d1 1990 func, vn_min_rate, vn_max_rate, bp->vn_weight_sum);
34f80b04
EG		 1991
1992 memset(&m_rs_vn, 0, sizeof(struct rate_shaping_vars_per_vn));
1993 memset(&m_fair_vn, 0, sizeof(struct fairness_vars_per_vn));
1994
1995 /* global vn counter - maximal Mbps for this vn */
1996 m_rs_vn.vn_counter.rate = vn_max_rate;
1997
1998 /* quota - number of bytes transmitted in this period */
1999 m_rs_vn.vn_counter.quota =
2000 (vn_max_rate * RS_PERIODIC_TIMEOUT_USEC) / 8;
2001
8a1c38d1 2002 if (bp->vn_weight_sum) {
34f80b04
EG		 2003 /* credit for each period of the fairness algorithm:
2004 number of bytes in T_FAIR (the vn share the port rate).
8a1c38d1
EG		 2005 vn_weight_sum should not be larger than 10000, thus
2006 T_FAIR_COEF / (8 * vn_weight_sum) will always be greater
2007 than zero */
34f80b04 2008 m_fair_vn.vn_credit_delta =
cdaa7cb8
VZ		 2009 max_t(u32, (vn_min_rate * (T_FAIR_COEF /
2010 (8 * bp->vn_weight_sum))),
ff80ee02
DK		 2011 (bp->cmng.fair_vars.fair_threshold +
2012 MIN_ABOVE_THRESH));
cdaa7cb8 2013 DP(NETIF_MSG_IFUP, "m_fair_vn.vn_credit_delta %d\n",
34f80b04
EG		 2014 m_fair_vn.vn_credit_delta);
2015 }
2016
34f80b04
EG		 2017 /* Store it to internal memory */
2018 for (i = 0; i < sizeof(struct rate_shaping_vars_per_vn)/4; i++)
2019 REG_WR(bp, BAR_XSTRORM_INTMEM +
2020 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func) + i * 4,
2021 ((u32 *)(&m_rs_vn))[i]);
2022
2023 for (i = 0; i < sizeof(struct fairness_vars_per_vn)/4; i++)
2024 REG_WR(bp, BAR_XSTRORM_INTMEM +
2025 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func) + i * 4,
2026 ((u32 *)(&m_fair_vn))[i]);
2027}
f85582f8 2028
523224a3
DK		 2029static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp)
2030{
2031 if (CHIP_REV_IS_SLOW(bp))
2032 return CMNG_FNS_NONE;
fb3bff17 2033 if (IS_MF(bp))
523224a3
DK		 2034 return CMNG_FNS_MINMAX;
2035
2036 return CMNG_FNS_NONE;
2037}
2038
2ae17f66 2039void bnx2x_read_mf_cfg(struct bnx2x *bp)
523224a3 2040{
0793f83f 2041 int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1);
523224a3
DK		 2042
2043 if (BP_NOMCP(bp))
2044 return; /* what should be the default bvalue in this case */
2045
0793f83f
DK		 2046 /* For 2 port configuration the absolute function number formula
2047 * is:
2048 * abs_func = 2 * vn + BP_PORT + BP_PATH
2049 *
2050 * and there are 4 functions per port
2051 *
2052 * For 4 port configuration it is
2053 * abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2054 *
2055 * and there are 2 functions per port
2056 */
523224a3 2057 for (vn = VN_0; vn < E1HVN_MAX; vn++) {
0793f83f
DK		 2058 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
2059
2060 if (func >= E1H_FUNC_MAX)
2061 break;
2062
f2e0899f 2063 bp->mf_config[vn] =
523224a3
DK		 2064 MF_CFG_RD(bp, func_mf_config[func].config);
2065 }
2066}
2067
2068static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)
2069{
2070
2071 if (cmng_type == CMNG_FNS_MINMAX) {
2072 int vn;
2073
2074 /* clear cmng_enables */
2075 bp->cmng.flags.cmng_enables = 0;
2076
2077 /* read mf conf from shmem */
2078 if (read_cfg)
2079 bnx2x_read_mf_cfg(bp);
2080
2081 /* Init rate shaping and fairness contexts */
2082 bnx2x_init_port_minmax(bp);
2083
2084 /* vn_weight_sum and enable fairness if not 0 */
2085 bnx2x_calc_vn_weight_sum(bp);
2086
2087 /* calculate and set min-max rate for each vn */
c4154f25
DK		 2088 if (bp->port.pmf)
2089 for (vn = VN_0; vn < E1HVN_MAX; vn++)
2090 bnx2x_init_vn_minmax(bp, vn);
523224a3
DK		 2091
2092 /* always enable rate shaping and fairness */
2093 bp->cmng.flags.cmng_enables |=
2094 CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
2095 if (!bp->vn_weight_sum)
2096 DP(NETIF_MSG_IFUP, "All MIN values are zeroes"
2097 " fairness will be disabled\n");
2098 return;
2099 }
2100
2101 /* rate shaping and fairness are disabled */
2102 DP(NETIF_MSG_IFUP,
2103 "rate shaping and fairness are disabled\n");
2104}
34f80b04 2105
523224a3
DK		 2106static inline void bnx2x_link_sync_notify(struct bnx2x *bp)
2107{
2108 int port = BP_PORT(bp);
2109 int func;
2110 int vn;
2111
2112 /* Set the attention towards other drivers on the same port */
2113 for (vn = VN_0; vn < E1HVN_MAX; vn++) {
2114 if (vn == BP_E1HVN(bp))
2115 continue;
2116
2117 func = ((vn << 1) | port);
2118 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_0 +
2119 (LINK_SYNC_ATTENTION_BIT_FUNC_0 + func)*4, 1);
2120 }
2121}
8a1c38d1 2122
c18487ee
YR		 2123/* This function is called upon link interrupt */
2124static void bnx2x_link_attn(struct bnx2x *bp)
2125{
bb2a0f7a
YG		 2126 /* Make sure that we are synced with the current statistics */
2127 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2128
c18487ee 2129 bnx2x_link_update(&bp->link_params, &bp->link_vars);
a2fbb9ea 2130
bb2a0f7a
YG		 2131 if (bp->link_vars.link_up) {
2132
1c06328c 2133 /* dropless flow control */
f2e0899f 2134 if (!CHIP_IS_E1(bp) && bp->dropless_fc) {
1c06328c
EG		 2135 int port = BP_PORT(bp);
2136 u32 pause_enabled = 0;
2137
2138 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
2139 pause_enabled = 1;
2140
2141 REG_WR(bp, BAR_USTRORM_INTMEM +
ca00392c 2142 USTORM_ETH_PAUSE_ENABLED_OFFSET(port),
1c06328c
EG		 2143 pause_enabled);
2144 }
2145
bb2a0f7a
YG		 2146 if (bp->link_vars.mac_type == MAC_TYPE_BMAC) {
2147 struct host_port_stats *pstats;
2148
2149 pstats = bnx2x_sp(bp, port_stats);
2150 /* reset old bmac stats */
2151 memset(&(pstats->mac_stx[0]), 0,
2152 sizeof(struct mac_stx));
2153 }
f34d28ea 2154 if (bp->state == BNX2X_STATE_OPEN)
bb2a0f7a
YG		 2155 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2156 }
2157
f2e0899f
DK		 2158 if (bp->link_vars.link_up && bp->link_vars.line_speed) {
2159 int cmng_fns = bnx2x_get_cmng_fns_mode(bp);
8a1c38d1 2160
f2e0899f
DK		 2161 if (cmng_fns != CMNG_FNS_NONE) {
2162 bnx2x_cmng_fns_init(bp, false, cmng_fns);
2163 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2164 } else
2165 /* rate shaping and fairness are disabled */
2166 DP(NETIF_MSG_IFUP,
2167 "single function mode without fairness\n");
34f80b04 2168 }
9fdc3e95 2169
2ae17f66
VZ		 2170 __bnx2x_link_report(bp);
2171
9fdc3e95
DK		 2172 if (IS_MF(bp))
2173 bnx2x_link_sync_notify(bp);
c18487ee 2174}
a2fbb9ea 2175
9f6c9258 2176void bnx2x__link_status_update(struct bnx2x *bp)
c18487ee 2177{
2ae17f66 2178 if (bp->state != BNX2X_STATE_OPEN)
c18487ee 2179 return;
a2fbb9ea 2180
c18487ee 2181 bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
a2fbb9ea 2182
bb2a0f7a
YG		 2183 if (bp->link_vars.link_up)
2184 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2185 else
2186 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2187
c18487ee
YR		 2188 /* indicate link status */
2189 bnx2x_link_report(bp);
a2fbb9ea 2190}
a2fbb9ea 2191
34f80b04
EG		 2192static void bnx2x_pmf_update(struct bnx2x *bp)
2193{
2194 int port = BP_PORT(bp);
2195 u32 val;
2196
2197 bp->port.pmf = 1;
2198 DP(NETIF_MSG_LINK, "pmf %d\n", bp->port.pmf);
2199
2200 /* enable nig attention */
2201 val = (0xff0f | (1 << (BP_E1HVN(bp) + 4)));
f2e0899f
DK		 2202 if (bp->common.int_block == INT_BLOCK_HC) {
2203 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2204 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
2205 } else if (CHIP_IS_E2(bp)) {
2206 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
2207 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
2208 }
bb2a0f7a
YG		 2209
2210 bnx2x_stats_handle(bp, STATS_EVENT_PMF);
34f80b04
EG		 2211}
2212
c18487ee 2213/* end of Link */
a2fbb9ea
ET		 2214
2215/* slow path */
2216
2217/*
2218 * General service functions
2219 */
2220
2691d51d 2221/* send the MCP a request, block until there is a reply */
a22f0788 2222u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param)
2691d51d 2223{
f2e0899f 2224 int mb_idx = BP_FW_MB_IDX(bp);
2691d51d
EG		 2225 u32 seq = ++bp->fw_seq;
2226 u32 rc = 0;
2227 u32 cnt = 1;
2228 u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
2229
c4ff7cbf 2230 mutex_lock(&bp->fw_mb_mutex);
f2e0899f
DK		 2231 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param);
2232 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq));
2233
2691d51d
EG		 2234 DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB\n", (command | seq));
2235
2236 do {
2237 /* let the FW do it's magic ... */
2238 msleep(delay);
2239
f2e0899f 2240 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header);
2691d51d 2241
c4ff7cbf
EG		 2242 /* Give the FW up to 5 second (500*10ms) */
2243 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
2691d51d
EG		 2244
2245 DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
2246 cnt*delay, rc, seq);
2247
2248 /* is this a reply to our command? */
2249 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK))
2250 rc &= FW_MSG_CODE_MASK;
2251 else {
2252 /* FW BUG! */
2253 BNX2X_ERR("FW failed to respond!\n");
2254 bnx2x_fw_dump(bp);
2255 rc = 0;
2256 }
c4ff7cbf 2257 mutex_unlock(&bp->fw_mb_mutex);
2691d51d
EG		 2258
2259 return rc;
2260}
2261
ec6ba945
VZ		 2262static u8 stat_counter_valid(struct bnx2x *bp, struct bnx2x_fastpath *fp)
2263{
2264#ifdef BCM_CNIC
2265 if (IS_FCOE_FP(fp) && IS_MF(bp))
2266 return false;
2267#endif
2268 return true;
2269}
2270
523224a3 2271/* must be called under rtnl_lock */
8d96286a 2272static void bnx2x_rxq_set_mac_filters(struct bnx2x *bp, u16 cl_id, u32 filters)
2691d51d 2273{
523224a3 2274 u32 mask = (1 << cl_id);
2691d51d 2275
523224a3
DK		 2276 /* initial seeting is BNX2X_ACCEPT_NONE */
2277 u8 drop_all_ucast = 1, drop_all_bcast = 1, drop_all_mcast = 1;
2278 u8 accp_all_ucast = 0, accp_all_bcast = 0, accp_all_mcast = 0;
2279 u8 unmatched_unicast = 0;
2691d51d 2280
0793f83f
DK		 2281 if (filters & BNX2X_ACCEPT_UNMATCHED_UCAST)
2282 unmatched_unicast = 1;
2283
523224a3
DK		 2284 if (filters & BNX2X_PROMISCUOUS_MODE) {
2285 /* promiscious - accept all, drop none */
2286 drop_all_ucast = drop_all_bcast = drop_all_mcast = 0;
2287 accp_all_ucast = accp_all_bcast = accp_all_mcast = 1;
0793f83f
DK		 2288 if (IS_MF_SI(bp)) {
2289 /*
2290 * SI mode defines to accept in promiscuos mode
2291 * only unmatched packets
2292 */
2293 unmatched_unicast = 1;
2294 accp_all_ucast = 0;
2295 }
523224a3
DK		 2296 }
2297 if (filters & BNX2X_ACCEPT_UNICAST) {
2298 /* accept matched ucast */
2299 drop_all_ucast = 0;
2300 }
d9c8f498 2301 if (filters & BNX2X_ACCEPT_MULTICAST)
523224a3
DK		 2302 /* accept matched mcast */
2303 drop_all_mcast = 0;
d9c8f498 2304
523224a3
DK		 2305 if (filters & BNX2X_ACCEPT_ALL_UNICAST) {
2306 /* accept all mcast */
2307 drop_all_ucast = 0;
2308 accp_all_ucast = 1;
2309 }
2310 if (filters & BNX2X_ACCEPT_ALL_MULTICAST) {
2311 /* accept all mcast */
2312 drop_all_mcast = 0;
2313 accp_all_mcast = 1;
2314 }
2315 if (filters & BNX2X_ACCEPT_BROADCAST) {
2316 /* accept (all) bcast */
2317 drop_all_bcast = 0;
2318 accp_all_bcast = 1;
2319 }
2691d51d 2320
523224a3
DK		 2321 bp->mac_filters.ucast_drop_all = drop_all_ucast ?
2322 bp->mac_filters.ucast_drop_all | mask :
2323 bp->mac_filters.ucast_drop_all & ~mask;
2691d51d 2324
523224a3
DK		 2325 bp->mac_filters.mcast_drop_all = drop_all_mcast ?
2326 bp->mac_filters.mcast_drop_all | mask :
2327 bp->mac_filters.mcast_drop_all & ~mask;
2691d51d 2328
523224a3
DK		 2329 bp->mac_filters.bcast_drop_all = drop_all_bcast ?
2330 bp->mac_filters.bcast_drop_all | mask :
2331 bp->mac_filters.bcast_drop_all & ~mask;
2691d51d 2332
523224a3
DK		 2333 bp->mac_filters.ucast_accept_all = accp_all_ucast ?
2334 bp->mac_filters.ucast_accept_all | mask :
2335 bp->mac_filters.ucast_accept_all & ~mask;
2691d51d 2336
523224a3
DK		 2337 bp->mac_filters.mcast_accept_all = accp_all_mcast ?
2338 bp->mac_filters.mcast_accept_all | mask :
2339 bp->mac_filters.mcast_accept_all & ~mask;
2340
2341 bp->mac_filters.bcast_accept_all = accp_all_bcast ?
2342 bp->mac_filters.bcast_accept_all | mask :
2343 bp->mac_filters.bcast_accept_all & ~mask;
2344
2345 bp->mac_filters.unmatched_unicast = unmatched_unicast ?
2346 bp->mac_filters.unmatched_unicast | mask :
2347 bp->mac_filters.unmatched_unicast & ~mask;
2691d51d
EG		 2348}
2349
8d96286a 2350static void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p)
2691d51d 2351{
030f3356
DK		 2352 struct tstorm_eth_function_common_config tcfg = {0};
2353 u16 rss_flgs;
2691d51d 2354
030f3356
DK		 2355 /* tpa */
2356 if (p->func_flgs & FUNC_FLG_TPA)
2357 tcfg.config_flags |=
2358 TSTORM_ETH_FUNCTION_COMMON_CONFIG_ENABLE_TPA;
2691d51d 2359
030f3356
DK		 2360 /* set rss flags */
2361 rss_flgs = (p->rss->mode <<
2362 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT);
2363
2364 if (p->rss->cap & RSS_IPV4_CAP)
2365 rss_flgs |= RSS_IPV4_CAP_MASK;
2366 if (p->rss->cap & RSS_IPV4_TCP_CAP)
2367 rss_flgs |= RSS_IPV4_TCP_CAP_MASK;
2368 if (p->rss->cap & RSS_IPV6_CAP)
2369 rss_flgs |= RSS_IPV6_CAP_MASK;
2370 if (p->rss->cap & RSS_IPV6_TCP_CAP)
2371 rss_flgs |= RSS_IPV6_TCP_CAP_MASK;
2372
2373 tcfg.config_flags |= rss_flgs;
2374 tcfg.rss_result_mask = p->rss->result_mask;
2375
2376 storm_memset_func_cfg(bp, &tcfg, p->func_id);
2691d51d 2377
523224a3
DK		 2378 /* Enable the function in the FW */
2379 storm_memset_vf_to_pf(bp, p->func_id, p->pf_id);
2380 storm_memset_func_en(bp, p->func_id, 1);
2691d51d 2381
523224a3
DK		 2382 /* statistics */
2383 if (p->func_flgs & FUNC_FLG_STATS) {
2384 struct stats_indication_flags stats_flags = {0};
2385 stats_flags.collect_eth = 1;
2691d51d 2386
523224a3
DK		 2387 storm_memset_xstats_flags(bp, &stats_flags, p->func_id);
2388 storm_memset_xstats_addr(bp, p->fw_stat_map, p->func_id);
2691d51d 2389
523224a3
DK		 2390 storm_memset_tstats_flags(bp, &stats_flags, p->func_id);
2391 storm_memset_tstats_addr(bp, p->fw_stat_map, p->func_id);
2691d51d 2392
523224a3
DK		 2393 storm_memset_ustats_flags(bp, &stats_flags, p->func_id);
2394 storm_memset_ustats_addr(bp, p->fw_stat_map, p->func_id);
2691d51d 2395
523224a3
DK		 2396 storm_memset_cstats_flags(bp, &stats_flags, p->func_id);
2397 storm_memset_cstats_addr(bp, p->fw_stat_map, p->func_id);
2691d51d
EG		 2398 }
2399
523224a3
DK		 2400 /* spq */
2401 if (p->func_flgs & FUNC_FLG_SPQ) {
2402 storm_memset_spq_addr(bp, p->spq_map, p->func_id);
2403 REG_WR(bp, XSEM_REG_FAST_MEMORY +
2404 XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod);
2405 }
2691d51d
EG		 2406}
2407
523224a3
DK		 2408static inline u16 bnx2x_get_cl_flags(struct bnx2x *bp,
2409 struct bnx2x_fastpath *fp)
28912902 2410{
523224a3 2411 u16 flags = 0;
28912902 2412
523224a3
DK		 2413 /* calculate queue flags */
2414 flags |= QUEUE_FLG_CACHE_ALIGN;
2415 flags |= QUEUE_FLG_HC;
0793f83f 2416 flags |= IS_MF_SD(bp) ? QUEUE_FLG_OV : 0;
28912902 2417
523224a3
DK		 2418 flags |= QUEUE_FLG_VLAN;
2419 DP(NETIF_MSG_IFUP, "vlan removal enabled\n");
523224a3
DK		 2420
2421 if (!fp->disable_tpa)
2422 flags |= QUEUE_FLG_TPA;
2423
ec6ba945
VZ		 2424 flags = stat_counter_valid(bp, fp) ?
2425 (flags | QUEUE_FLG_STATS) : (flags & ~QUEUE_FLG_STATS);
523224a3
DK		 2426
2427 return flags;
2428}
2429
2430static void bnx2x_pf_rx_cl_prep(struct bnx2x *bp,
2431 struct bnx2x_fastpath *fp, struct rxq_pause_params *pause,
2432 struct bnx2x_rxq_init_params *rxq_init)
2433{
2434 u16 max_sge = 0;
2435 u16 sge_sz = 0;
2436 u16 tpa_agg_size = 0;
2437
2438 /* calculate queue flags */
2439 u16 flags = bnx2x_get_cl_flags(bp, fp);
2440
2441 if (!fp->disable_tpa) {
2442 pause->sge_th_hi = 250;
2443 pause->sge_th_lo = 150;
2444 tpa_agg_size = min_t(u32,
2445 (min_t(u32, 8, MAX_SKB_FRAGS) *
2446 SGE_PAGE_SIZE * PAGES_PER_SGE), 0xffff);
2447 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >>
2448 SGE_PAGE_SHIFT;
2449 max_sge = ((max_sge + PAGES_PER_SGE - 1) &
2450 (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT;
2451 sge_sz = (u16)min_t(u32, SGE_PAGE_SIZE * PAGES_PER_SGE,
2452 0xffff);
2453 }
2454
2455 /* pause - not for e1 */
2456 if (!CHIP_IS_E1(bp)) {
2457 pause->bd_th_hi = 350;
2458 pause->bd_th_lo = 250;
2459 pause->rcq_th_hi = 350;
2460 pause->rcq_th_lo = 250;
2461 pause->sge_th_hi = 0;
2462 pause->sge_th_lo = 0;
2463 pause->pri_map = 1;
2464 }
2465
2466 /* rxq setup */
2467 rxq_init->flags = flags;
2468 rxq_init->cxt = &bp->context.vcxt[fp->cid].eth;
2469 rxq_init->dscr_map = fp->rx_desc_mapping;
2470 rxq_init->sge_map = fp->rx_sge_mapping;
2471 rxq_init->rcq_map = fp->rx_comp_mapping;
2472 rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE;
a8c94b91
VZ		 2473
2474 /* Always use mini-jumbo MTU for FCoE L2 ring */
2475 if (IS_FCOE_FP(fp))
2476 rxq_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU;
2477 else
2478 rxq_init->mtu = bp->dev->mtu;
2479
2480 rxq_init->buf_sz = fp->rx_buf_size;
523224a3
DK		 2481 rxq_init->cl_qzone_id = fp->cl_qzone_id;
2482 rxq_init->cl_id = fp->cl_id;
2483 rxq_init->spcl_id = fp->cl_id;
2484 rxq_init->stat_id = fp->cl_id;
2485 rxq_init->tpa_agg_sz = tpa_agg_size;
2486 rxq_init->sge_buf_sz = sge_sz;
2487 rxq_init->max_sges_pkt = max_sge;
2488 rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
2489 rxq_init->fw_sb_id = fp->fw_sb_id;
2490
ec6ba945
VZ		 2491 if (IS_FCOE_FP(fp))
2492 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS;
2493 else
2494 rxq_init->sb_cq_index = U_SB_ETH_RX_CQ_INDEX;
523224a3
DK		 2495
2496 rxq_init->cid = HW_CID(bp, fp->cid);
2497
2498 rxq_init->hc_rate = bp->rx_ticks ? (1000000 / bp->rx_ticks) : 0;
2499}
2500
2501static void bnx2x_pf_tx_cl_prep(struct bnx2x *bp,
2502 struct bnx2x_fastpath *fp, struct bnx2x_txq_init_params *txq_init)
2503{
2504 u16 flags = bnx2x_get_cl_flags(bp, fp);
2505
2506 txq_init->flags = flags;
2507 txq_init->cxt = &bp->context.vcxt[fp->cid].eth;
2508 txq_init->dscr_map = fp->tx_desc_mapping;
2509 txq_init->stat_id = fp->cl_id;
2510 txq_init->cid = HW_CID(bp, fp->cid);
2511 txq_init->sb_cq_index = C_SB_ETH_TX_CQ_INDEX;
2512 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
2513 txq_init->fw_sb_id = fp->fw_sb_id;
ec6ba945
VZ		 2514
2515 if (IS_FCOE_FP(fp)) {
2516 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS;
2517 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE;
2518 }
2519
523224a3
DK		 2520 txq_init->hc_rate = bp->tx_ticks ? (1000000 / bp->tx_ticks) : 0;
2521}
2522
8d96286a 2523static void bnx2x_pf_init(struct bnx2x *bp)
523224a3
DK		 2524{
2525 struct bnx2x_func_init_params func_init = {0};
2526 struct bnx2x_rss_params rss = {0};
2527 struct event_ring_data eq_data = { {0} };
2528 u16 flags;
2529
2530 /* pf specific setups */
2531 if (!CHIP_IS_E1(bp))
fb3bff17 2532 storm_memset_ov(bp, bp->mf_ov, BP_FUNC(bp));
523224a3 2533
f2e0899f
DK		 2534 if (CHIP_IS_E2(bp)) {
2535 /* reset IGU PF statistics: MSIX + ATTN */
2536 /* PF */
2537 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
2538 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
2539 (CHIP_MODE_IS_4_PORT(bp) ?
2540 BP_FUNC(bp) : BP_VN(bp))*4, 0);
2541 /* ATTN */
2542 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
2543 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
2544 BNX2X_IGU_STAS_MSG_PF_CNT*4 +
2545 (CHIP_MODE_IS_4_PORT(bp) ?
2546 BP_FUNC(bp) : BP_VN(bp))*4, 0);
2547 }
2548
523224a3
DK		 2549 /* function setup flags */
2550 flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
2551
f2e0899f
DK		 2552 if (CHIP_IS_E1x(bp))
2553 flags |= (bp->flags & TPA_ENABLE_FLAG) ? FUNC_FLG_TPA : 0;
2554 else
2555 flags |= FUNC_FLG_TPA;
523224a3 2556
030f3356
DK		 2557 /* function setup */
2558
523224a3
DK		 2559 /**
2560 * Although RSS is meaningless when there is a single HW queue we
2561 * still need it enabled in order to have HW Rx hash generated.
523224a3 2562 */
030f3356
DK		 2563 rss.cap = (RSS_IPV4_CAP | RSS_IPV4_TCP_CAP |
2564 RSS_IPV6_CAP | RSS_IPV6_TCP_CAP);
2565 rss.mode = bp->multi_mode;
2566 rss.result_mask = MULTI_MASK;
2567 func_init.rss = &rss;
523224a3
DK		 2568
2569 func_init.func_flgs = flags;
2570 func_init.pf_id = BP_FUNC(bp);
2571 func_init.func_id = BP_FUNC(bp);
2572 func_init.fw_stat_map = bnx2x_sp_mapping(bp, fw_stats);
2573 func_init.spq_map = bp->spq_mapping;
2574 func_init.spq_prod = bp->spq_prod_idx;
2575
2576 bnx2x_func_init(bp, &func_init);
2577
2578 memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
2579
2580 /*
2581 Congestion management values depend on the link rate
2582 There is no active link so initial link rate is set to 10 Gbps.
2583 When the link comes up The congestion management values are
2584 re-calculated according to the actual link rate.
2585 */
2586 bp->link_vars.line_speed = SPEED_10000;
2587 bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp));
2588
2589 /* Only the PMF sets the HW */
2590 if (bp->port.pmf)
2591 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2592
2593 /* no rx until link is up */
2594 bp->rx_mode = BNX2X_RX_MODE_NONE;
2595 bnx2x_set_storm_rx_mode(bp);
2596
2597 /* init Event Queue */
2598 eq_data.base_addr.hi = U64_HI(bp->eq_mapping);
2599 eq_data.base_addr.lo = U64_LO(bp->eq_mapping);
2600 eq_data.producer = bp->eq_prod;
2601 eq_data.index_id = HC_SP_INDEX_EQ_CONS;
2602 eq_data.sb_id = DEF_SB_ID;
2603 storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp));
2604}
2605
2606
2607static void bnx2x_e1h_disable(struct bnx2x *bp)
2608{
2609 int port = BP_PORT(bp);
2610
2611 netif_tx_disable(bp->dev);
2612
2613 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
2614
2615 netif_carrier_off(bp->dev);
2616}
2617
2618static void bnx2x_e1h_enable(struct bnx2x *bp)
2619{
2620 int port = BP_PORT(bp);
2621
2622 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
2623
2624 /* Tx queue should be only reenabled */
2625 netif_tx_wake_all_queues(bp->dev);
2626
2627 /*
2628 * Should not call netif_carrier_on since it will be called if the link
2629 * is up when checking for link state
2630 */
2631}
2632
0793f83f
DK		 2633/* called due to MCP event (on pmf):
2634 * reread new bandwidth configuration
2635 * configure FW
2636 * notify others function about the change
2637 */
2638static inline void bnx2x_config_mf_bw(struct bnx2x *bp)
2639{
2640 if (bp->link_vars.link_up) {
2641 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX);
2642 bnx2x_link_sync_notify(bp);
2643 }
2644 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2645}
2646
2647static inline void bnx2x_set_mf_bw(struct bnx2x *bp)
2648{
2649 bnx2x_config_mf_bw(bp);
2650 bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
2651}
2652
523224a3
DK		 2653static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event)
2654{
2655 DP(BNX2X_MSG_MCP, "dcc_event 0x%x\n", dcc_event);
2656
2657 if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
2658
2659 /*
2660 * This is the only place besides the function initialization
2661 * where the bp->flags can change so it is done without any
2662 * locks
2663 */
f2e0899f 2664 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
523224a3
DK		 2665 DP(NETIF_MSG_IFDOWN, "mf_cfg function disabled\n");
2666 bp->flags |= MF_FUNC_DIS;
2667
2668 bnx2x_e1h_disable(bp);
2669 } else {
2670 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n");
2671 bp->flags &= ~MF_FUNC_DIS;
2672
2673 bnx2x_e1h_enable(bp);
2674 }
2675 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
2676 }
2677 if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
0793f83f 2678 bnx2x_config_mf_bw(bp);
523224a3
DK		 2679 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
2680 }
2681
2682 /* Report results to MCP */
2683 if (dcc_event)
2684 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_FAILURE, 0);
2685 else
2686 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_OK, 0);
2687}
2688
2689/* must be called under the spq lock */
2690static inline struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp)
2691{
2692 struct eth_spe *next_spe = bp->spq_prod_bd;
2693
2694 if (bp->spq_prod_bd == bp->spq_last_bd) {
2695 bp->spq_prod_bd = bp->spq;
2696 bp->spq_prod_idx = 0;
2697 DP(NETIF_MSG_TIMER, "end of spq\n");
2698 } else {
2699 bp->spq_prod_bd++;
2700 bp->spq_prod_idx++;
2701 }
2702 return next_spe;
2703}
2704
2705/* must be called under the spq lock */
28912902
MC		 2706static inline void bnx2x_sp_prod_update(struct bnx2x *bp)
2707{
2708 int func = BP_FUNC(bp);
2709
2710 /* Make sure that BD data is updated before writing the producer */
2711 wmb();
2712
523224a3 2713 REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
f85582f8 2714 bp->spq_prod_idx);
28912902
MC		 2715 mmiowb();
2716}
2717
a2fbb9ea 2718/* the slow path queue is odd since completions arrive on the fastpath ring */
9f6c9258 2719int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
f85582f8 2720 u32 data_hi, u32 data_lo, int common)
a2fbb9ea 2721{
28912902 2722 struct eth_spe *spe;
523224a3 2723 u16 type;
a2fbb9ea 2724
a2fbb9ea
ET		 2725#ifdef BNX2X_STOP_ON_ERROR
2726 if (unlikely(bp->panic))
2727 return -EIO;
2728#endif
2729
34f80b04 2730 spin_lock_bh(&bp->spq_lock);
a2fbb9ea 2731
6e30dd4e
VZ		 2732 if (common) {
2733 if (!atomic_read(&bp->eq_spq_left)) {
2734 BNX2X_ERR("BUG! EQ ring full!\n");
2735 spin_unlock_bh(&bp->spq_lock);
2736 bnx2x_panic();
2737 return -EBUSY;
2738 }
2739 } else if (!atomic_read(&bp->cq_spq_left)) {
2740 BNX2X_ERR("BUG! SPQ ring full!\n");
2741 spin_unlock_bh(&bp->spq_lock);
2742 bnx2x_panic();
2743 return -EBUSY;
a2fbb9ea 2744 }
f1410647 2745
28912902
MC		 2746 spe = bnx2x_sp_get_next(bp);
2747
a2fbb9ea 2748 /* CID needs port number to be encoded int it */
28912902 2749 spe->hdr.conn_and_cmd_data =
cdaa7cb8
VZ		 2750 cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) |
2751 HW_CID(bp, cid));
523224a3 2752
a2fbb9ea 2753 if (common)
523224a3
DK		 2754 /* Common ramrods:
2755 * FUNC_START, FUNC_STOP, CFC_DEL, STATS, SET_MAC
2756 * TRAFFIC_STOP, TRAFFIC_START
2757 */
2758 type = (NONE_CONNECTION_TYPE << SPE_HDR_CONN_TYPE_SHIFT)
2759 & SPE_HDR_CONN_TYPE;
2760 else
2761 /* ETH ramrods: SETUP, HALT */
2762 type = (ETH_CONNECTION_TYPE << SPE_HDR_CONN_TYPE_SHIFT)
2763 & SPE_HDR_CONN_TYPE;
a2fbb9ea 2764
523224a3
DK		 2765 type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) &
2766 SPE_HDR_FUNCTION_ID);
a2fbb9ea 2767
523224a3
DK		 2768 spe->hdr.type = cpu_to_le16(type);
2769
2770 spe->data.update_data_addr.hi = cpu_to_le32(data_hi);
2771 spe->data.update_data_addr.lo = cpu_to_le32(data_lo);
2772
2773 /* stats ramrod has it's own slot on the spq */
6e30dd4e 2774 if (command != RAMROD_CMD_ID_COMMON_STAT_QUERY) {
523224a3
DK		 2775 /* It's ok if the actual decrement is issued towards the memory
2776 * somewhere between the spin_lock and spin_unlock. Thus no
2777 * more explict memory barrier is needed.
2778 */
6e30dd4e
VZ		 2779 if (common)
2780 atomic_dec(&bp->eq_spq_left);
2781 else
2782 atomic_dec(&bp->cq_spq_left);
2783 }
2784
a2fbb9ea 2785
cdaa7cb8 2786 DP(BNX2X_MSG_SP/*NETIF_MSG_TIMER*/,
523224a3 2787 "SPQE[%x] (%x:%x) command %d hw_cid %x data (%x:%x) "
6e30dd4e 2788 "type(0x%x) left (ETH, COMMON) (%x,%x)\n",
cdaa7cb8
VZ		 2789 bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping),
2790 (u32)(U64_LO(bp->spq_mapping) +
2791 (void *)bp->spq_prod_bd - (void *)bp->spq), command,
6e30dd4e
VZ		 2792 HW_CID(bp, cid), data_hi, data_lo, type,
2793 atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left));
cdaa7cb8 2794
28912902 2795 bnx2x_sp_prod_update(bp);
34f80b04 2796 spin_unlock_bh(&bp->spq_lock);
a2fbb9ea
ET		 2797 return 0;
2798}
2799
2800/* acquire split MCP access lock register */
4a37fb66 2801static int bnx2x_acquire_alr(struct bnx2x *bp)
a2fbb9ea 2802{
72fd0718 2803 u32 j, val;
34f80b04 2804 int rc = 0;
a2fbb9ea
ET		 2805
2806 might_sleep();
72fd0718 2807 for (j = 0; j < 1000; j++) {
a2fbb9ea
ET		 2808 val = (1UL << 31);
2809 REG_WR(bp, GRCBASE_MCP + 0x9c, val);
2810 val = REG_RD(bp, GRCBASE_MCP + 0x9c);
2811 if (val & (1L << 31))
2812 break;
2813
2814 msleep(5);
2815 }
a2fbb9ea 2816 if (!(val & (1L << 31))) {
19680c48 2817 BNX2X_ERR("Cannot acquire MCP access lock register\n");
a2fbb9ea
ET		 2818 rc = -EBUSY;
2819 }
2820
2821 return rc;
2822}
2823
4a37fb66
YG		 2824/* release split MCP access lock register */
2825static void bnx2x_release_alr(struct bnx2x *bp)
a2fbb9ea 2826{
72fd0718 2827 REG_WR(bp, GRCBASE_MCP + 0x9c, 0);
a2fbb9ea
ET		 2828}
2829
523224a3
DK		 2830#define BNX2X_DEF_SB_ATT_IDX 0x0001
2831#define BNX2X_DEF_SB_IDX 0x0002
2832
a2fbb9ea
ET		 2833static inline u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
2834{
523224a3 2835 struct host_sp_status_block *def_sb = bp->def_status_blk;
a2fbb9ea
ET		 2836 u16 rc = 0;
2837
2838 barrier(); /* status block is written to by the chip */
a2fbb9ea
ET		 2839 if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
2840 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
523224a3 2841 rc |= BNX2X_DEF_SB_ATT_IDX;
a2fbb9ea 2842 }
523224a3
DK		 2843
2844 if (bp->def_idx != def_sb->sp_sb.running_index) {
2845 bp->def_idx = def_sb->sp_sb.running_index;
2846 rc |= BNX2X_DEF_SB_IDX;
a2fbb9ea 2847 }
523224a3
DK		 2848
2849 /* Do not reorder: indecies reading should complete before handling */
2850 barrier();
a2fbb9ea
ET		 2851 return rc;
2852}
2853
2854/*
2855 * slow path service functions
2856 */
2857
2858static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
2859{
34f80b04 2860 int port = BP_PORT(bp);
a2fbb9ea
ET		 2861 u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
2862 MISC_REG_AEU_MASK_ATTN_FUNC_0;
877e9aa4
ET		 2863 u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
2864 NIG_REG_MASK_INTERRUPT_PORT0;
3fcaf2e5 2865 u32 aeu_mask;
87942b46 2866 u32 nig_mask = 0;
f2e0899f 2867 u32 reg_addr;
a2fbb9ea 2868
a2fbb9ea
ET		 2869 if (bp->attn_state & asserted)
2870 BNX2X_ERR("IGU ERROR\n");
2871
3fcaf2e5
EG		 2872 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2873 aeu_mask = REG_RD(bp, aeu_addr);
2874
a2fbb9ea 2875 DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n",
3fcaf2e5 2876 aeu_mask, asserted);
72fd0718 2877 aeu_mask &= ~(asserted & 0x3ff);
3fcaf2e5 2878 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
a2fbb9ea 2879
3fcaf2e5
EG		 2880 REG_WR(bp, aeu_addr, aeu_mask);
2881 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
a2fbb9ea 2882
3fcaf2e5 2883 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
a2fbb9ea 2884 bp->attn_state |= asserted;
3fcaf2e5 2885 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
a2fbb9ea
ET		 2886
2887 if (asserted & ATTN_HARD_WIRED_MASK) {
2888 if (asserted & ATTN_NIG_FOR_FUNC) {
a2fbb9ea 2889
a5e9a7cf
EG		 2890 bnx2x_acquire_phy_lock(bp);
2891
877e9aa4 2892 /* save nig interrupt mask */
87942b46 2893 nig_mask = REG_RD(bp, nig_int_mask_addr);
877e9aa4 2894 REG_WR(bp, nig_int_mask_addr, 0);
a2fbb9ea 2895
c18487ee 2896 bnx2x_link_attn(bp);
a2fbb9ea
ET		 2897
2898 /* handle unicore attn? */
2899 }
2900 if (asserted & ATTN_SW_TIMER_4_FUNC)
2901 DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
2902
2903 if (asserted & GPIO_2_FUNC)
2904 DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
2905
2906 if (asserted & GPIO_3_FUNC)
2907 DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
2908
2909 if (asserted & GPIO_4_FUNC)
2910 DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
2911
2912 if (port == 0) {
2913 if (asserted & ATTN_GENERAL_ATTN_1) {
2914 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
2915 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
2916 }
2917 if (asserted & ATTN_GENERAL_ATTN_2) {
2918 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
2919 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
2920 }
2921 if (asserted & ATTN_GENERAL_ATTN_3) {
2922 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
2923 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
2924 }
2925 } else {
2926 if (asserted & ATTN_GENERAL_ATTN_4) {
2927 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
2928 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
2929 }
2930 if (asserted & ATTN_GENERAL_ATTN_5) {
2931 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
2932 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
2933 }
2934 if (asserted & ATTN_GENERAL_ATTN_6) {
2935 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
2936 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
2937 }
2938 }
2939
2940 } /* if hardwired */
2941
f2e0899f
DK		 2942 if (bp->common.int_block == INT_BLOCK_HC)
2943 reg_addr = (HC_REG_COMMAND_REG + port*32 +
2944 COMMAND_REG_ATTN_BITS_SET);
2945 else
2946 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
2947
2948 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted,
2949 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
2950 REG_WR(bp, reg_addr, asserted);
a2fbb9ea
ET		 2951
2952 /* now set back the mask */
a5e9a7cf 2953 if (asserted & ATTN_NIG_FOR_FUNC) {
87942b46 2954 REG_WR(bp, nig_int_mask_addr, nig_mask);
a5e9a7cf
EG		 2955 bnx2x_release_phy_lock(bp);
2956 }
a2fbb9ea
ET		 2957}
2958
fd4ef40d
EG		 2959static inline void bnx2x_fan_failure(struct bnx2x *bp)
2960{
2961 int port = BP_PORT(bp);
b7737c9b 2962 u32 ext_phy_config;
fd4ef40d 2963 /* mark the failure */
b7737c9b
YR		 2964 ext_phy_config =
2965 SHMEM_RD(bp,
2966 dev_info.port_hw_config[port].external_phy_config);
2967
2968 ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
2969 ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
fd4ef40d 2970 SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
b7737c9b 2971 ext_phy_config);
fd4ef40d
EG		 2972
2973 /* log the failure */
cdaa7cb8
VZ		 2974 netdev_err(bp->dev, "Fan Failure on Network Controller has caused"
2975 " the driver to shutdown the card to prevent permanent"
2976 " damage. Please contact OEM Support for assistance\n");
fd4ef40d 2977}
ab6ad5a4 2978
877e9aa4 2979static inline void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
a2fbb9ea 2980{
34f80b04 2981 int port = BP_PORT(bp);
877e9aa4 2982 int reg_offset;
d90d96ba 2983 u32 val;
877e9aa4 2984
34f80b04
EG		 2985 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
2986 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
877e9aa4 2987
34f80b04 2988 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
877e9aa4
ET		 2989
2990 val = REG_RD(bp, reg_offset);
2991 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
2992 REG_WR(bp, reg_offset, val);
2993
2994 BNX2X_ERR("SPIO5 hw attention\n");
2995
fd4ef40d 2996 /* Fan failure attention */
d90d96ba 2997 bnx2x_hw_reset_phy(&bp->link_params);
fd4ef40d 2998 bnx2x_fan_failure(bp);
877e9aa4 2999 }
34f80b04 3000
589abe3a
EG		 3001 if (attn & (AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0 |
3002 AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1)) {
3003 bnx2x_acquire_phy_lock(bp);
3004 bnx2x_handle_module_detect_int(&bp->link_params);
3005 bnx2x_release_phy_lock(bp);
3006 }
3007
34f80b04
EG		 3008 if (attn & HW_INTERRUT_ASSERT_SET_0) {
3009
3010 val = REG_RD(bp, reg_offset);
3011 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
3012 REG_WR(bp, reg_offset, val);
3013
3014 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
0fc5d009 3015 (u32)(attn & HW_INTERRUT_ASSERT_SET_0));
34f80b04
EG		 3016 bnx2x_panic();
3017 }
877e9aa4
ET		 3018}
3019
3020static inline void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
3021{
3022 u32 val;
3023
0626b899 3024 if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
877e9aa4
ET		 3025
3026 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
3027 BNX2X_ERR("DB hw attention 0x%x\n", val);
3028 /* DORQ discard attention */
3029 if (val & 0x2)
3030 BNX2X_ERR("FATAL error from DORQ\n");
3031 }
34f80b04
EG		 3032
3033 if (attn & HW_INTERRUT_ASSERT_SET_1) {
3034
3035 int port = BP_PORT(bp);
3036 int reg_offset;
3037
3038 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
3039 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
3040
3041 val = REG_RD(bp, reg_offset);
3042 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
3043 REG_WR(bp, reg_offset, val);
3044
3045 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
0fc5d009 3046 (u32)(attn & HW_INTERRUT_ASSERT_SET_1));
34f80b04
EG		 3047 bnx2x_panic();
3048 }
877e9aa4
ET		 3049}
3050
3051static inline void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
3052{
3053 u32 val;
3054
3055 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
3056
3057 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
3058 BNX2X_ERR("CFC hw attention 0x%x\n", val);
3059 /* CFC error attention */
3060 if (val & 0x2)
3061 BNX2X_ERR("FATAL error from CFC\n");
3062 }
3063
3064 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
3065
3066 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
3067 BNX2X_ERR("PXP hw attention 0x%x\n", val);
3068 /* RQ_USDMDP_FIFO_OVERFLOW */
3069 if (val & 0x18000)
3070 BNX2X_ERR("FATAL error from PXP\n");
f2e0899f
DK		 3071 if (CHIP_IS_E2(bp)) {
3072 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1);
3073 BNX2X_ERR("PXP hw attention-1 0x%x\n", val);
3074 }
877e9aa4 3075 }
34f80b04
EG		 3076
3077 if (attn & HW_INTERRUT_ASSERT_SET_2) {
3078
3079 int port = BP_PORT(bp);
3080 int reg_offset;
3081
3082 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
3083 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
3084
3085 val = REG_RD(bp, reg_offset);
3086 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
3087 REG_WR(bp, reg_offset, val);
3088
3089 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
0fc5d009 3090 (u32)(attn & HW_INTERRUT_ASSERT_SET_2));
34f80b04
EG		 3091 bnx2x_panic();
3092 }
877e9aa4
ET		 3093}
3094
3095static inline void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
3096{
34f80b04
EG		 3097 u32 val;
3098
877e9aa4
ET		 3099 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
3100
34f80b04
EG		 3101 if (attn & BNX2X_PMF_LINK_ASSERT) {
3102 int func = BP_FUNC(bp);
3103
3104 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
f2e0899f
DK		 3105 bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp,
3106 func_mf_config[BP_ABS_FUNC(bp)].config);
3107 val = SHMEM_RD(bp,
3108 func_mb[BP_FW_MB_IDX(bp)].drv_status);
2691d51d
EG		 3109 if (val & DRV_STATUS_DCC_EVENT_MASK)
3110 bnx2x_dcc_event(bp,
3111 (val & DRV_STATUS_DCC_EVENT_MASK));
0793f83f
DK		 3112
3113 if (val & DRV_STATUS_SET_MF_BW)
3114 bnx2x_set_mf_bw(bp);
3115
2691d51d 3116 if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
34f80b04
EG		 3117 bnx2x_pmf_update(bp);
3118
2ae17f66
VZ		 3119 /* Always call it here: bnx2x_link_report() will
3120 * prevent the link indication duplication.
3121 */
3122 bnx2x__link_status_update(bp);
3123
e4901dde 3124 if (bp->port.pmf &&
785b9b1a
SR		 3125 (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) &&
3126 bp->dcbx_enabled > 0)
e4901dde
VZ		 3127 /* start dcbx state machine */
3128 bnx2x_dcbx_set_params(bp,
3129 BNX2X_DCBX_STATE_NEG_RECEIVED);
34f80b04 3130 } else if (attn & BNX2X_MC_ASSERT_BITS) {
877e9aa4
ET		 3131
3132 BNX2X_ERR("MC assert!\n");
3133 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
3134 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
3135 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
3136 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
3137 bnx2x_panic();
3138
3139 } else if (attn & BNX2X_MCP_ASSERT) {
3140
3141 BNX2X_ERR("MCP assert!\n");
3142 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
34f80b04 3143 bnx2x_fw_dump(bp);
877e9aa4
ET		 3144
3145 } else
3146 BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
3147 }
3148
3149 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
34f80b04
EG		 3150 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
3151 if (attn & BNX2X_GRC_TIMEOUT) {
f2e0899f
DK		 3152 val = CHIP_IS_E1(bp) ? 0 :
3153 REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN);
34f80b04
EG		 3154 BNX2X_ERR("GRC time-out 0x%08x\n", val);
3155 }
3156 if (attn & BNX2X_GRC_RSV) {
f2e0899f
DK		 3157 val = CHIP_IS_E1(bp) ? 0 :
3158 REG_RD(bp, MISC_REG_GRC_RSV_ATTN);
34f80b04
EG		 3159 BNX2X_ERR("GRC reserved 0x%08x\n", val);
3160 }
877e9aa4 3161 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
877e9aa4
ET		 3162 }
3163}
3164
72fd0718
VZ		 3165#define BNX2X_MISC_GEN_REG MISC_REG_GENERIC_POR_1
3166#define LOAD_COUNTER_BITS 16 /* Number of bits for load counter */
3167#define LOAD_COUNTER_MASK (((u32)0x1 << LOAD_COUNTER_BITS) - 1)
3168#define RESET_DONE_FLAG_MASK (~LOAD_COUNTER_MASK)
3169#define RESET_DONE_FLAG_SHIFT LOAD_COUNTER_BITS
f85582f8 3170
72fd0718
VZ		 3171/*
3172 * should be run under rtnl lock
3173 */
3174static inline void bnx2x_set_reset_done(struct bnx2x *bp)
3175{
3176 u32 val = REG_RD(bp, BNX2X_MISC_GEN_REG);
3177 val &= ~(1 << RESET_DONE_FLAG_SHIFT);
3178 REG_WR(bp, BNX2X_MISC_GEN_REG, val);
3179 barrier();
3180 mmiowb();
3181}
3182
3183/*
3184 * should be run under rtnl lock
3185 */
3186static inline void bnx2x_set_reset_in_progress(struct bnx2x *bp)
3187{
3188 u32 val = REG_RD(bp, BNX2X_MISC_GEN_REG);
3189 val |= (1 << 16);
3190 REG_WR(bp, BNX2X_MISC_GEN_REG, val);
3191 barrier();
3192 mmiowb();
3193}
3194
3195/*
3196 * should be run under rtnl lock
3197 */
9f6c9258 3198bool bnx2x_reset_is_done(struct bnx2x *bp)
72fd0718
VZ		 3199{
3200 u32 val = REG_RD(bp, BNX2X_MISC_GEN_REG);
3201 DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val);
3202 return (val & RESET_DONE_FLAG_MASK) ? false : true;
3203}
3204
3205/*
3206 * should be run under rtnl lock
3207 */
9f6c9258 3208inline void bnx2x_inc_load_cnt(struct bnx2x *bp)
72fd0718
VZ		 3209{
3210 u32 val1, val = REG_RD(bp, BNX2X_MISC_GEN_REG);
3211
3212 DP(NETIF_MSG_HW, "Old GEN_REG_VAL=0x%08x\n", val);
3213
3214 val1 = ((val & LOAD_COUNTER_MASK) + 1) & LOAD_COUNTER_MASK;
3215 REG_WR(bp, BNX2X_MISC_GEN_REG, (val & RESET_DONE_FLAG_MASK) | val1);
3216 barrier();
3217 mmiowb();
3218}
3219
3220/*
3221 * should be run under rtnl lock
3222 */
9f6c9258 3223u32 bnx2x_dec_load_cnt(struct bnx2x *bp)
72fd0718
VZ		 3224{
3225 u32 val1, val = REG_RD(bp, BNX2X_MISC_GEN_REG);
3226
3227 DP(NETIF_MSG_HW, "Old GEN_REG_VAL=0x%08x\n", val);
3228
3229 val1 = ((val & LOAD_COUNTER_MASK) - 1) & LOAD_COUNTER_MASK;
3230 REG_WR(bp, BNX2X_MISC_GEN_REG, (val & RESET_DONE_FLAG_MASK) | val1);
3231 barrier();
3232 mmiowb();
3233
3234 return val1;
3235}
3236
3237/*
3238 * should be run under rtnl lock
3239 */
3240static inline u32 bnx2x_get_load_cnt(struct bnx2x *bp)
3241{
3242 return REG_RD(bp, BNX2X_MISC_GEN_REG) & LOAD_COUNTER_MASK;
3243}
3244
3245static inline void bnx2x_clear_load_cnt(struct bnx2x *bp)
3246{
3247 u32 val = REG_RD(bp, BNX2X_MISC_GEN_REG);
3248 REG_WR(bp, BNX2X_MISC_GEN_REG, val & (~LOAD_COUNTER_MASK));
3249}
3250
3251static inline void _print_next_block(int idx, const char *blk)
3252{
3253 if (idx)
3254 pr_cont(", ");
3255 pr_cont("%s", blk);
3256}
3257
3258static inline int bnx2x_print_blocks_with_parity0(u32 sig, int par_num)
3259{
3260 int i = 0;
3261 u32 cur_bit = 0;
3262 for (i = 0; sig; i++) {
3263 cur_bit = ((u32)0x1 << i);
3264 if (sig & cur_bit) {
3265 switch (cur_bit) {
3266 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
3267 _print_next_block(par_num++, "BRB");
3268 break;
3269 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
3270 _print_next_block(par_num++, "PARSER");
3271 break;
3272 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
3273 _print_next_block(par_num++, "TSDM");
3274 break;
3275 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
3276 _print_next_block(par_num++, "SEARCHER");
3277 break;
3278 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
3279 _print_next_block(par_num++, "TSEMI");
3280 break;
3281 }
3282
3283 /* Clear the bit */
3284 sig &= ~cur_bit;
3285 }
3286 }
3287
3288 return par_num;
3289}
3290
3291static inline int bnx2x_print_blocks_with_parity1(u32 sig, int par_num)
3292{
3293 int i = 0;
3294 u32 cur_bit = 0;
3295 for (i = 0; sig; i++) {
3296 cur_bit = ((u32)0x1 << i);
3297 if (sig & cur_bit) {
3298 switch (cur_bit) {
3299 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
3300 _print_next_block(par_num++, "PBCLIENT");
3301 break;
3302 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
3303 _print_next_block(par_num++, "QM");
3304 break;
3305 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
3306 _print_next_block(par_num++, "XSDM");
3307 break;
3308 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
3309 _print_next_block(par_num++, "XSEMI");
3310 break;
3311 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
3312 _print_next_block(par_num++, "DOORBELLQ");
3313 break;
3314 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
3315 _print_next_block(par_num++, "VAUX PCI CORE");
3316 break;
3317 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
3318 _print_next_block(par_num++, "DEBUG");
3319 break;
3320 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
3321 _print_next_block(par_num++, "USDM");
3322 break;
3323 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
3324 _print_next_block(par_num++, "USEMI");
3325 break;
3326 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
3327 _print_next_block(par_num++, "UPB");
3328 break;
3329 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
3330 _print_next_block(par_num++, "CSDM");
3331 break;
3332 }
3333
3334 /* Clear the bit */
3335 sig &= ~cur_bit;
3336 }
3337 }
3338
3339 return par_num;
3340}
3341
3342static inline int bnx2x_print_blocks_with_parity2(u32 sig, int par_num)
3343{
3344 int i = 0;
3345 u32 cur_bit = 0;
3346 for (i = 0; sig; i++) {
3347 cur_bit = ((u32)0x1 << i);
3348 if (sig & cur_bit) {
3349 switch (cur_bit) {
3350 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
3351 _print_next_block(par_num++, "CSEMI");
3352 break;
3353 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
3354 _print_next_block(par_num++, "PXP");
3355 break;
3356 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
3357 _print_next_block(par_num++,
3358 "PXPPCICLOCKCLIENT");
3359 break;
3360 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
3361 _print_next_block(par_num++, "CFC");
3362 break;
3363 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
3364 _print_next_block(par_num++, "CDU");
3365 break;
3366 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
3367 _print_next_block(par_num++, "IGU");
3368 break;
3369 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
3370 _print_next_block(par_num++, "MISC");
3371 break;
3372 }
3373
3374 /* Clear the bit */
3375 sig &= ~cur_bit;
3376 }
3377 }
3378
3379 return par_num;
3380}
3381
3382static inline int bnx2x_print_blocks_with_parity3(u32 sig, int par_num)
3383{
3384 int i = 0;
3385 u32 cur_bit = 0;
3386 for (i = 0; sig; i++) {
3387 cur_bit = ((u32)0x1 << i);
3388 if (sig & cur_bit) {
3389 switch (cur_bit) {
3390 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
3391 _print_next_block(par_num++, "MCP ROM");
3392 break;
3393 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
3394 _print_next_block(par_num++, "MCP UMP RX");
3395 break;
3396 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
3397 _print_next_block(par_num++, "MCP UMP TX");
3398 break;
3399 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
3400 _print_next_block(par_num++, "MCP SCPAD");
3401 break;
3402 }
3403
3404 /* Clear the bit */
3405 sig &= ~cur_bit;
3406 }
3407 }
3408
3409 return par_num;
3410}
3411
3412static inline bool bnx2x_parity_attn(struct bnx2x *bp, u32 sig0, u32 sig1,
3413 u32 sig2, u32 sig3)
3414{
3415 if ((sig0 & HW_PRTY_ASSERT_SET_0) || (sig1 & HW_PRTY_ASSERT_SET_1) ||
3416 (sig2 & HW_PRTY_ASSERT_SET_2) || (sig3 & HW_PRTY_ASSERT_SET_3)) {
3417 int par_num = 0;
3418 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention: "
3419 "[0]:0x%08x [1]:0x%08x "
3420 "[2]:0x%08x [3]:0x%08x\n",
3421 sig0 & HW_PRTY_ASSERT_SET_0,
3422 sig1 & HW_PRTY_ASSERT_SET_1,
3423 sig2 & HW_PRTY_ASSERT_SET_2,
3424 sig3 & HW_PRTY_ASSERT_SET_3);
3425 printk(KERN_ERR"%s: Parity errors detected in blocks: ",
3426 bp->dev->name);
3427 par_num = bnx2x_print_blocks_with_parity0(
3428 sig0 & HW_PRTY_ASSERT_SET_0, par_num);
3429 par_num = bnx2x_print_blocks_with_parity1(
3430 sig1 & HW_PRTY_ASSERT_SET_1, par_num);
3431 par_num = bnx2x_print_blocks_with_parity2(
3432 sig2 & HW_PRTY_ASSERT_SET_2, par_num);
3433 par_num = bnx2x_print_blocks_with_parity3(
3434 sig3 & HW_PRTY_ASSERT_SET_3, par_num);
3435 printk("\n");
3436 return true;
3437 } else
3438 return false;
3439}
3440
9f6c9258 3441bool bnx2x_chk_parity_attn(struct bnx2x *bp)
877e9aa4 3442{
a2fbb9ea 3443 struct attn_route attn;
72fd0718
VZ		 3444 int port = BP_PORT(bp);
3445
3446 attn.sig[0] = REG_RD(bp,
3447 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
3448 port*4);
3449 attn.sig[1] = REG_RD(bp,
3450 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 +
3451 port*4);
3452 attn.sig[2] = REG_RD(bp,
3453 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 +
3454 port*4);
3455 attn.sig[3] = REG_RD(bp,
3456 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
3457 port*4);
3458
3459 return bnx2x_parity_attn(bp, attn.sig[0], attn.sig[1], attn.sig[2],
3460 attn.sig[3]);
3461}
3462
f2e0899f
DK		 3463
3464static inline void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn)
3465{
3466 u32 val;
3467 if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
3468
3469 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
3470 BNX2X_ERR("PGLUE hw attention 0x%x\n", val);
3471 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
3472 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3473 "ADDRESS_ERROR\n");
3474 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
3475 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3476 "INCORRECT_RCV_BEHAVIOR\n");
3477 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
3478 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3479 "WAS_ERROR_ATTN\n");
3480 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
3481 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3482 "VF_LENGTH_VIOLATION_ATTN\n");
3483 if (val &
3484 PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
3485 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3486 "VF_GRC_SPACE_VIOLATION_ATTN\n");
3487 if (val &
3488 PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
3489 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3490 "VF_MSIX_BAR_VIOLATION_ATTN\n");
3491 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
3492 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3493 "TCPL_ERROR_ATTN\n");
3494 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
3495 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3496 "TCPL_IN_TWO_RCBS_ATTN\n");
3497 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
3498 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3499 "CSSNOOP_FIFO_OVERFLOW\n");
3500 }
3501 if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
3502 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);
3503 BNX2X_ERR("ATC hw attention 0x%x\n", val);
3504 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
3505 BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
3506 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
3507 BNX2X_ERR("ATC_ATC_INT_STS_REG"
3508 "_ATC_TCPL_TO_NOT_PEND\n");
3509 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
3510 BNX2X_ERR("ATC_ATC_INT_STS_REG_"
3511 "ATC_GPA_MULTIPLE_HITS\n");
3512 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
3513 BNX2X_ERR("ATC_ATC_INT_STS_REG_"
3514 "ATC_RCPL_TO_EMPTY_CNT\n");
3515 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
3516 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
3517 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
3518 BNX2X_ERR("ATC_ATC_INT_STS_REG_"
3519 "ATC_IREQ_LESS_THAN_STU\n");
3520 }
3521
3522 if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
3523 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
3524 BNX2X_ERR("FATAL parity attention set4 0x%x\n",
3525 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
3526 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
3527 }
3528
3529}
3530
72fd0718
VZ		 3531static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
3532{
3533 struct attn_route attn, *group_mask;
34f80b04 3534 int port = BP_PORT(bp);
877e9aa4 3535 int index;
a2fbb9ea
ET		 3536 u32 reg_addr;
3537 u32 val;
3fcaf2e5 3538 u32 aeu_mask;
a2fbb9ea
ET		 3539
3540 /* need to take HW lock because MCP or other port might also
3541 try to handle this event */
4a37fb66 3542 bnx2x_acquire_alr(bp);
a2fbb9ea 3543
4a33bc03 3544 if (CHIP_PARITY_ENABLED(bp) && bnx2x_chk_parity_attn(bp)) {
72fd0718
VZ		 3545 bp->recovery_state = BNX2X_RECOVERY_INIT;
3546 bnx2x_set_reset_in_progress(bp);
3547 schedule_delayed_work(&bp->reset_task, 0);
3548 /* Disable HW interrupts */
3549 bnx2x_int_disable(bp);
3550 bnx2x_release_alr(bp);
3551 /* In case of parity errors don't handle attentions so that
3552 * other function would "see" parity errors.
3553 */
3554 return;
3555 }
3556
a2fbb9ea
ET		 3557 attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
3558 attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
3559 attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
3560 attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
f2e0899f
DK		 3561 if (CHIP_IS_E2(bp))
3562 attn.sig[4] =
3563 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
3564 else
3565 attn.sig[4] = 0;
3566
3567 DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n",
3568 attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
a2fbb9ea
ET		 3569
3570 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
3571 if (deasserted & (1 << index)) {
72fd0718 3572 group_mask = &bp->attn_group[index];
a2fbb9ea 3573
f2e0899f
DK		 3574 DP(NETIF_MSG_HW, "group[%d]: %08x %08x "
3575 "%08x %08x %08x\n",
3576 index,
3577 group_mask->sig[0], group_mask->sig[1],
3578 group_mask->sig[2], group_mask->sig[3],
3579 group_mask->sig[4]);
a2fbb9ea 3580
f2e0899f
DK		 3581 bnx2x_attn_int_deasserted4(bp,
3582 attn.sig[4] & group_mask->sig[4]);
877e9aa4 3583 bnx2x_attn_int_deasserted3(bp,
72fd0718 3584 attn.sig[3] & group_mask->sig[3]);
877e9aa4 3585 bnx2x_attn_int_deasserted1(bp,
72fd0718 3586 attn.sig[1] & group_mask->sig[1]);
877e9aa4 3587 bnx2x_attn_int_deasserted2(bp,
72fd0718 3588 attn.sig[2] & group_mask->sig[2]);
877e9aa4 3589 bnx2x_attn_int_deasserted0(bp,
72fd0718 3590 attn.sig[0] & group_mask->sig[0]);
a2fbb9ea
ET		 3591 }
3592 }
3593
4a37fb66 3594 bnx2x_release_alr(bp);
a2fbb9ea 3595
f2e0899f
DK		 3596 if (bp->common.int_block == INT_BLOCK_HC)
3597 reg_addr = (HC_REG_COMMAND_REG + port*32 +
3598 COMMAND_REG_ATTN_BITS_CLR);
3599 else
3600 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
a2fbb9ea
ET		 3601
3602 val = ~deasserted;
f2e0899f
DK		 3603 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val,
3604 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
5c862848 3605 REG_WR(bp, reg_addr, val);
a2fbb9ea 3606
a2fbb9ea 3607 if (~bp->attn_state & deasserted)
3fcaf2e5 3608 BNX2X_ERR("IGU ERROR\n");
a2fbb9ea
ET		 3609
3610 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
3611 MISC_REG_AEU_MASK_ATTN_FUNC_0;
3612
3fcaf2e5
EG		 3613 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3614 aeu_mask = REG_RD(bp, reg_addr);
3615
3616 DP(NETIF_MSG_HW, "aeu_mask %x newly deasserted %x\n",
3617 aeu_mask, deasserted);
72fd0718 3618 aeu_mask |= (deasserted & 0x3ff);
3fcaf2e5 3619 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
a2fbb9ea 3620
3fcaf2e5
EG		 3621 REG_WR(bp, reg_addr, aeu_mask);
3622 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
a2fbb9ea
ET		 3623
3624 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
3625 bp->attn_state &= ~deasserted;
3626 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
3627}
3628
3629static void bnx2x_attn_int(struct bnx2x *bp)
3630{
3631 /* read local copy of bits */
68d59484
EG		 3632 u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
3633 attn_bits);
3634 u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
3635 attn_bits_ack);
a2fbb9ea
ET		 3636 u32 attn_state = bp->attn_state;
3637
3638 /* look for changed bits */
3639 u32 asserted = attn_bits & ~attn_ack & ~attn_state;
3640 u32 deasserted = ~attn_bits & attn_ack & attn_state;
3641
3642 DP(NETIF_MSG_HW,
3643 "attn_bits %x attn_ack %x asserted %x deasserted %x\n",
3644 attn_bits, attn_ack, asserted, deasserted);
3645
3646 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
34f80b04 3647 BNX2X_ERR("BAD attention state\n");
a2fbb9ea
ET		 3648
3649 /* handle bits that were raised */
3650 if (asserted)
3651 bnx2x_attn_int_asserted(bp, asserted);
3652
3653 if (deasserted)
3654 bnx2x_attn_int_deasserted(bp, deasserted);
3655}
3656
523224a3
DK		 3657static inline void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod)
3658{
3659 /* No memory barriers */
3660 storm_memset_eq_prod(bp, prod, BP_FUNC(bp));
3661 mmiowb(); /* keep prod updates ordered */
3662}
3663
3664#ifdef BCM_CNIC
3665static int bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid,
3666 union event_ring_elem *elem)
3667{
3668 if (!bp->cnic_eth_dev.starting_cid ||
3669 cid < bp->cnic_eth_dev.starting_cid)
3670 return 1;
3671
3672 DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid);
3673
3674 if (unlikely(elem->message.data.cfc_del_event.error)) {
3675 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
3676 cid);
3677 bnx2x_panic_dump(bp);
3678 }
3679 bnx2x_cnic_cfc_comp(bp, cid);
3680 return 0;
3681}
3682#endif
3683
3684static void bnx2x_eq_int(struct bnx2x *bp)
3685{
3686 u16 hw_cons, sw_cons, sw_prod;
3687 union event_ring_elem *elem;
3688 u32 cid;
3689 u8 opcode;
3690 int spqe_cnt = 0;
3691
3692 hw_cons = le16_to_cpu(*bp->eq_cons_sb);
3693
3694 /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
3695 * when we get the the next-page we nned to adjust so the loop
3696 * condition below will be met. The next element is the size of a
3697 * regular element and hence incrementing by 1
3698 */
3699 if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE)
3700 hw_cons++;
3701
25985edc 3702 /* This function may never run in parallel with itself for a
523224a3
DK		 3703 * specific bp, thus there is no need in "paired" read memory
3704 * barrier here.
3705 */
3706 sw_cons = bp->eq_cons;
3707 sw_prod = bp->eq_prod;
3708
6e30dd4e
VZ		 3709 DP(BNX2X_MSG_SP, "EQ: hw_cons %u sw_cons %u bp->cq_spq_left %u\n",
3710 hw_cons, sw_cons, atomic_read(&bp->eq_spq_left));
523224a3
DK		 3711
3712 for (; sw_cons != hw_cons;
3713 sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
3714
3715
3716 elem = &bp->eq_ring[EQ_DESC(sw_cons)];
3717
3718 cid = SW_CID(elem->message.data.cfc_del_event.cid);
3719 opcode = elem->message.opcode;
3720
3721
3722 /* handle eq element */
3723 switch (opcode) {
3724 case EVENT_RING_OPCODE_STAT_QUERY:
3725 DP(NETIF_MSG_TIMER, "got statistics comp event\n");
3726 /* nothing to do with stats comp */
3727 continue;
3728
3729 case EVENT_RING_OPCODE_CFC_DEL:
3730 /* handle according to cid range */
3731 /*
3732 * we may want to verify here that the bp state is
3733 * HALTING
3734 */
3735 DP(NETIF_MSG_IFDOWN,
3736 "got delete ramrod for MULTI[%d]\n", cid);
3737#ifdef BCM_CNIC
3738 if (!bnx2x_cnic_handle_cfc_del(bp, cid, elem))
3739 goto next_spqe;
ec6ba945
VZ		 3740 if (cid == BNX2X_FCOE_ETH_CID)
3741 bnx2x_fcoe(bp, state) = BNX2X_FP_STATE_CLOSED;
3742 else
523224a3 3743#endif
ec6ba945 3744 bnx2x_fp(bp, cid, state) =
523224a3
DK		 3745 BNX2X_FP_STATE_CLOSED;
3746
3747 goto next_spqe;
e4901dde
VZ		 3748
3749 case EVENT_RING_OPCODE_STOP_TRAFFIC:
3750 DP(NETIF_MSG_IFUP, "got STOP TRAFFIC\n");
3751 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED);
3752 goto next_spqe;
3753 case EVENT_RING_OPCODE_START_TRAFFIC:
3754 DP(NETIF_MSG_IFUP, "got START TRAFFIC\n");
3755 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED);
3756 goto next_spqe;
523224a3
DK		 3757 }
3758
3759 switch (opcode | bp->state) {
3760 case (EVENT_RING_OPCODE_FUNCTION_START |
3761 BNX2X_STATE_OPENING_WAIT4_PORT):
3762 DP(NETIF_MSG_IFUP, "got setup ramrod\n");
3763 bp->state = BNX2X_STATE_FUNC_STARTED;
3764 break;
3765
3766 case (EVENT_RING_OPCODE_FUNCTION_STOP |
3767 BNX2X_STATE_CLOSING_WAIT4_HALT):
3768 DP(NETIF_MSG_IFDOWN, "got halt ramrod\n");
3769 bp->state = BNX2X_STATE_CLOSING_WAIT4_UNLOAD;
3770 break;
3771
3772 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
3773 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
3774 DP(NETIF_MSG_IFUP, "got set mac ramrod\n");
6e30dd4e
VZ		 3775 if (elem->message.data.set_mac_event.echo)
3776 bp->set_mac_pending = 0;
523224a3
DK		 3777 break;
3778
3779 case (EVENT_RING_OPCODE_SET_MAC |
3780 BNX2X_STATE_CLOSING_WAIT4_HALT):
3781 DP(NETIF_MSG_IFDOWN, "got (un)set mac ramrod\n");
6e30dd4e
VZ		 3782 if (elem->message.data.set_mac_event.echo)
3783 bp->set_mac_pending = 0;
523224a3
DK		 3784 break;
3785 default:
3786 /* unknown event log error and continue */
3787 BNX2X_ERR("Unknown EQ event %d\n",
3788 elem->message.opcode);
3789 }
3790next_spqe:
3791 spqe_cnt++;
3792 } /* for */
3793
8fe23fbd 3794 smp_mb__before_atomic_inc();
6e30dd4e 3795 atomic_add(spqe_cnt, &bp->eq_spq_left);
523224a3
DK		 3796
3797 bp->eq_cons = sw_cons;
3798 bp->eq_prod = sw_prod;
3799 /* Make sure that above mem writes were issued towards the memory */
3800 smp_wmb();
3801
3802 /* update producer */
3803 bnx2x_update_eq_prod(bp, bp->eq_prod);
3804}
3805
a2fbb9ea
ET		 3806static void bnx2x_sp_task(struct work_struct *work)
3807{
1cf167f2 3808 struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
a2fbb9ea
ET		 3809 u16 status;
3810
3811 /* Return here if interrupt is disabled */
3812 if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
3196a88a 3813 DP(NETIF_MSG_INTR, "called but intr_sem not 0, returning\n");
a2fbb9ea
ET		 3814 return;
3815 }
3816
3817 status = bnx2x_update_dsb_idx(bp);
34f80b04
EG		 3818/* if (status == 0) */
3819/* BNX2X_ERR("spurious slowpath interrupt!\n"); */
a2fbb9ea 3820
cdaa7cb8 3821 DP(NETIF_MSG_INTR, "got a slowpath interrupt (status 0x%x)\n", status);
a2fbb9ea 3822
877e9aa4 3823 /* HW attentions */
523224a3 3824 if (status & BNX2X_DEF_SB_ATT_IDX) {
a2fbb9ea 3825 bnx2x_attn_int(bp);
523224a3 3826 status &= ~BNX2X_DEF_SB_ATT_IDX;
cdaa7cb8
VZ		 3827 }
3828
523224a3
DK		 3829 /* SP events: STAT_QUERY and others */
3830 if (status & BNX2X_DEF_SB_IDX) {
ec6ba945
VZ		 3831#ifdef BCM_CNIC
3832 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
523224a3 3833
ec6ba945
VZ		 3834 if ((!NO_FCOE(bp)) &&
3835 (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp)))
3836 napi_schedule(&bnx2x_fcoe(bp, napi));
3837#endif
523224a3
DK		 3838 /* Handle EQ completions */
3839 bnx2x_eq_int(bp);
3840
3841 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID,
3842 le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1);
3843
3844 status &= ~BNX2X_DEF_SB_IDX;
cdaa7cb8
VZ		 3845 }
3846
3847 if (unlikely(status))
3848 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
3849 status);
a2fbb9ea 3850
523224a3
DK		 3851 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID,
3852 le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1);
a2fbb9ea
ET		 3853}
3854
9f6c9258 3855irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
a2fbb9ea
ET		 3856{
3857 struct net_device *dev = dev_instance;
3858 struct bnx2x *bp = netdev_priv(dev);
3859
3860 /* Return here if interrupt is disabled */
3861 if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
3196a88a 3862 DP(NETIF_MSG_INTR, "called but intr_sem not 0, returning\n");
a2fbb9ea
ET		 3863 return IRQ_HANDLED;
3864 }
3865
523224a3
DK		 3866 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0,
3867 IGU_INT_DISABLE, 0);
a2fbb9ea
ET		 3868
3869#ifdef BNX2X_STOP_ON_ERROR
3870 if (unlikely(bp->panic))
3871 return IRQ_HANDLED;
3872#endif
3873
993ac7b5
MC		 3874#ifdef BCM_CNIC
3875 {
3876 struct cnic_ops *c_ops;
3877
3878 rcu_read_lock();
3879 c_ops = rcu_dereference(bp->cnic_ops);
3880 if (c_ops)
3881 c_ops->cnic_handler(bp->cnic_data, NULL);
3882 rcu_read_unlock();
3883 }
3884#endif
1cf167f2 3885 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
a2fbb9ea
ET		 3886
3887 return IRQ_HANDLED;
3888}
3889
3890/* end of slow path */
3891
a2fbb9ea
ET		 3892static void bnx2x_timer(unsigned long data)
3893{
3894 struct bnx2x *bp = (struct bnx2x *) data;
3895
3896 if (!netif_running(bp->dev))
3897 return;
3898
3899 if (atomic_read(&bp->intr_sem) != 0)
f1410647 3900 goto timer_restart;
a2fbb9ea
ET		 3901
3902 if (poll) {
3903 struct bnx2x_fastpath *fp = &bp->fp[0];
a2fbb9ea 3904
7961f791 3905 bnx2x_tx_int(fp);
b8ee8328 3906 bnx2x_rx_int(fp, 1000);
a2fbb9ea
ET		 3907 }
3908
34f80b04 3909 if (!BP_NOMCP(bp)) {
f2e0899f 3910 int mb_idx = BP_FW_MB_IDX(bp);
a2fbb9ea
ET		 3911 u32 drv_pulse;
3912 u32 mcp_pulse;
3913
3914 ++bp->fw_drv_pulse_wr_seq;
3915 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
3916 /* TBD - add SYSTEM_TIME */
3917 drv_pulse = bp->fw_drv_pulse_wr_seq;
f2e0899f 3918 SHMEM_WR(bp, func_mb[mb_idx].drv_pulse_mb, drv_pulse);
a2fbb9ea 3919
f2e0899f 3920 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) &
a2fbb9ea
ET		 3921 MCP_PULSE_SEQ_MASK);
3922 /* The delta between driver pulse and mcp response
3923 * should be 1 (before mcp response) or 0 (after mcp response)
3924 */
3925 if ((drv_pulse != mcp_pulse) &&
3926 (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
3927 /* someone lost a heartbeat... */
3928 BNX2X_ERR("drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
3929 drv_pulse, mcp_pulse);
3930 }
3931 }
3932
f34d28ea 3933 if (bp->state == BNX2X_STATE_OPEN)
bb2a0f7a 3934 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
a2fbb9ea 3935
f1410647 3936timer_restart:
a2fbb9ea
ET		 3937 mod_timer(&bp->timer, jiffies + bp->current_interval);
3938}
3939
3940/* end of Statistics */
3941
3942/* nic init */
3943
3944/*
3945 * nic init service functions
3946 */
3947
523224a3 3948static inline void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
a2fbb9ea 3949{
523224a3
DK		 3950 u32 i;
3951 if (!(len%4) && !(addr%4))
3952 for (i = 0; i < len; i += 4)
3953 REG_WR(bp, addr + i, fill);
3954 else
3955 for (i = 0; i < len; i++)
3956 REG_WR8(bp, addr + i, fill);
34f80b04 3957
34f80b04
EG		 3958}
3959
523224a3
DK		 3960/* helper: writes FP SP data to FW - data_size in dwords */
3961static inline void bnx2x_wr_fp_sb_data(struct bnx2x *bp,
3962 int fw_sb_id,
3963 u32 *sb_data_p,
3964 u32 data_size)
34f80b04 3965{
a2fbb9ea 3966 int index;
523224a3
DK		 3967 for (index = 0; index < data_size; index++)
3968 REG_WR(bp, BAR_CSTRORM_INTMEM +
3969 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
3970 sizeof(u32)*index,
3971 *(sb_data_p + index));
3972}
a2fbb9ea 3973
523224a3
DK		 3974static inline void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id)
3975{
3976 u32 *sb_data_p;
3977 u32 data_size = 0;
f2e0899f 3978 struct hc_status_block_data_e2 sb_data_e2;
523224a3 3979 struct hc_status_block_data_e1x sb_data_e1x;
a2fbb9ea 3980
523224a3 3981 /* disable the function first */
f2e0899f
DK		 3982 if (CHIP_IS_E2(bp)) {
3983 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
3984 sb_data_e2.common.p_func.pf_id = HC_FUNCTION_DISABLED;
3985 sb_data_e2.common.p_func.vf_id = HC_FUNCTION_DISABLED;
3986 sb_data_e2.common.p_func.vf_valid = false;
3987 sb_data_p = (u32 *)&sb_data_e2;
3988 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
3989 } else {
3990 memset(&sb_data_e1x, 0,
3991 sizeof(struct hc_status_block_data_e1x));
3992 sb_data_e1x.common.p_func.pf_id = HC_FUNCTION_DISABLED;
3993 sb_data_e1x.common.p_func.vf_id = HC_FUNCTION_DISABLED;
3994 sb_data_e1x.common.p_func.vf_valid = false;
3995 sb_data_p = (u32 *)&sb_data_e1x;
3996 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
3997 }
523224a3 3998 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
a2fbb9ea 3999
523224a3
DK		 4000 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4001 CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0,
4002 CSTORM_STATUS_BLOCK_SIZE);
4003 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4004 CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0,
4005 CSTORM_SYNC_BLOCK_SIZE);
4006}
34f80b04 4007
523224a3
DK		 4008/* helper: writes SP SB data to FW */
4009static inline void bnx2x_wr_sp_sb_data(struct bnx2x *bp,
4010 struct hc_sp_status_block_data *sp_sb_data)
4011{
4012 int func = BP_FUNC(bp);
4013 int i;
4014 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
4015 REG_WR(bp, BAR_CSTRORM_INTMEM +
4016 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
4017 i*sizeof(u32),
4018 *((u32 *)sp_sb_data + i));
34f80b04
EG		 4019}
4020
523224a3 4021static inline void bnx2x_zero_sp_sb(struct bnx2x *bp)
34f80b04
EG		 4022{
4023 int func = BP_FUNC(bp);
523224a3
DK		 4024 struct hc_sp_status_block_data sp_sb_data;
4025 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
a2fbb9ea 4026
523224a3
DK		 4027 sp_sb_data.p_func.pf_id = HC_FUNCTION_DISABLED;
4028 sp_sb_data.p_func.vf_id = HC_FUNCTION_DISABLED;
4029 sp_sb_data.p_func.vf_valid = false;
4030
4031 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
4032
4033 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4034 CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0,
4035 CSTORM_SP_STATUS_BLOCK_SIZE);
4036 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4037 CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0,
4038 CSTORM_SP_SYNC_BLOCK_SIZE);
4039
4040}
4041
4042
4043static inline
4044void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
4045 int igu_sb_id, int igu_seg_id)
4046{
4047 hc_sm->igu_sb_id = igu_sb_id;
4048 hc_sm->igu_seg_id = igu_seg_id;
4049 hc_sm->timer_value = 0xFF;
4050 hc_sm->time_to_expire = 0xFFFFFFFF;
a2fbb9ea
ET		 4051}
4052
8d96286a 4053static void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
523224a3 4054 u8 vf_valid, int fw_sb_id, int igu_sb_id)
a2fbb9ea 4055{
523224a3
DK		 4056 int igu_seg_id;
4057
f2e0899f 4058 struct hc_status_block_data_e2 sb_data_e2;
523224a3
DK		 4059 struct hc_status_block_data_e1x sb_data_e1x;
4060 struct hc_status_block_sm *hc_sm_p;
523224a3
DK		 4061 int data_size;
4062 u32 *sb_data_p;
4063
f2e0899f
DK		 4064 if (CHIP_INT_MODE_IS_BC(bp))
4065 igu_seg_id = HC_SEG_ACCESS_NORM;
4066 else
4067 igu_seg_id = IGU_SEG_ACCESS_NORM;
523224a3
DK		 4068
4069 bnx2x_zero_fp_sb(bp, fw_sb_id);
4070
f2e0899f
DK		 4071 if (CHIP_IS_E2(bp)) {
4072 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
4073 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp);
4074 sb_data_e2.common.p_func.vf_id = vfid;
4075 sb_data_e2.common.p_func.vf_valid = vf_valid;
4076 sb_data_e2.common.p_func.vnic_id = BP_VN(bp);
4077 sb_data_e2.common.same_igu_sb_1b = true;
4078 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping);
4079 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping);
4080 hc_sm_p = sb_data_e2.common.state_machine;
f2e0899f
DK		 4081 sb_data_p = (u32 *)&sb_data_e2;
4082 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
4083 } else {
4084 memset(&sb_data_e1x, 0,
4085 sizeof(struct hc_status_block_data_e1x));
4086 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp);
4087 sb_data_e1x.common.p_func.vf_id = 0xff;
4088 sb_data_e1x.common.p_func.vf_valid = false;
4089 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp);
4090 sb_data_e1x.common.same_igu_sb_1b = true;
4091 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping);
4092 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping);
4093 hc_sm_p = sb_data_e1x.common.state_machine;
f2e0899f
DK		 4094 sb_data_p = (u32 *)&sb_data_e1x;
4095 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
4096 }
523224a3
DK		 4097
4098 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID],
4099 igu_sb_id, igu_seg_id);
4100 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID],
4101 igu_sb_id, igu_seg_id);
4102
4103 DP(NETIF_MSG_HW, "Init FW SB %d\n", fw_sb_id);
4104
4105 /* write indecies to HW */
4106 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
4107}
4108
4109static void bnx2x_update_coalesce_sb_index(struct bnx2x *bp, u16 fw_sb_id,
4110 u8 sb_index, u8 disable, u16 usec)
4111{
4112 int port = BP_PORT(bp);
4113 u8 ticks = usec / BNX2X_BTR;
4114
4115 storm_memset_hc_timeout(bp, port, fw_sb_id, sb_index, ticks);
4116
4117 disable = disable ? 1 : (usec ? 0 : 1);
4118 storm_memset_hc_disable(bp, port, fw_sb_id, sb_index, disable);
4119}
4120
4121static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u16 fw_sb_id,
4122 u16 tx_usec, u16 rx_usec)
4123{
4124 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, U_SB_ETH_RX_CQ_INDEX,
4125 false, rx_usec);
4126 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, C_SB_ETH_TX_CQ_INDEX,
4127 false, tx_usec);
4128}
f2e0899f 4129
523224a3
DK		 4130static void bnx2x_init_def_sb(struct bnx2x *bp)
4131{
4132 struct host_sp_status_block *def_sb = bp->def_status_blk;
4133 dma_addr_t mapping = bp->def_status_blk_mapping;
4134 int igu_sp_sb_index;
4135 int igu_seg_id;
34f80b04
EG		 4136 int port = BP_PORT(bp);
4137 int func = BP_FUNC(bp);
523224a3 4138 int reg_offset;
a2fbb9ea 4139 u64 section;
523224a3
DK		 4140 int index;
4141 struct hc_sp_status_block_data sp_sb_data;
4142 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
4143
f2e0899f
DK		 4144 if (CHIP_INT_MODE_IS_BC(bp)) {
4145 igu_sp_sb_index = DEF_SB_IGU_ID;
4146 igu_seg_id = HC_SEG_ACCESS_DEF;
4147 } else {
4148 igu_sp_sb_index = bp->igu_dsb_id;
4149 igu_seg_id = IGU_SEG_ACCESS_DEF;
4150 }
a2fbb9ea
ET		 4151
4152 /* ATTN */
523224a3 4153 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
a2fbb9ea 4154 atten_status_block);
523224a3 4155 def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
a2fbb9ea 4156
49d66772
ET		 4157 bp->attn_state = 0;
4158
a2fbb9ea
ET		 4159 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4160 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
34f80b04 4161 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
523224a3
DK		 4162 int sindex;
4163 /* take care of sig[0]..sig[4] */
4164 for (sindex = 0; sindex < 4; sindex++)
4165 bp->attn_group[index].sig[sindex] =
4166 REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);
f2e0899f
DK		 4167
4168 if (CHIP_IS_E2(bp))
4169 /*
4170 * enable5 is separate from the rest of the registers,
4171 * and therefore the address skip is 4
4172 * and not 16 between the different groups
4173 */
4174 bp->attn_group[index].sig[4] = REG_RD(bp,
4175 reg_offset + 0x10 + 0x4*index);
4176 else
4177 bp->attn_group[index].sig[4] = 0;
a2fbb9ea
ET		 4178 }
4179
f2e0899f
DK		 4180 if (bp->common.int_block == INT_BLOCK_HC) {
4181 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
4182 HC_REG_ATTN_MSG0_ADDR_L);
4183
4184 REG_WR(bp, reg_offset, U64_LO(section));
4185 REG_WR(bp, reg_offset + 4, U64_HI(section));
4186 } else if (CHIP_IS_E2(bp)) {
4187 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
4188 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
4189 }
a2fbb9ea 4190
523224a3
DK		 4191 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
4192 sp_sb);
a2fbb9ea 4193
523224a3 4194 bnx2x_zero_sp_sb(bp);
a2fbb9ea 4195
523224a3
DK		 4196 sp_sb_data.host_sb_addr.lo = U64_LO(section);
4197 sp_sb_data.host_sb_addr.hi = U64_HI(section);
4198 sp_sb_data.igu_sb_id = igu_sp_sb_index;
4199 sp_sb_data.igu_seg_id = igu_seg_id;
4200 sp_sb_data.p_func.pf_id = func;
f2e0899f 4201 sp_sb_data.p_func.vnic_id = BP_VN(bp);
523224a3 4202 sp_sb_data.p_func.vf_id = 0xff;
a2fbb9ea 4203
523224a3 4204 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
49d66772 4205
bb2a0f7a 4206 bp->stats_pending = 0;
66e855f3 4207 bp->set_mac_pending = 0;
bb2a0f7a 4208
523224a3 4209 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
a2fbb9ea
ET		 4210}
4211
9f6c9258 4212void bnx2x_update_coalesce(struct bnx2x *bp)
a2fbb9ea 4213{
a2fbb9ea
ET		 4214 int i;
4215
ec6ba945 4216 for_each_eth_queue(bp, i)
523224a3 4217 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id,
423cfa7e 4218 bp->tx_ticks, bp->rx_ticks);
a2fbb9ea
ET		 4219}
4220
a2fbb9ea
ET		 4221static void bnx2x_init_sp_ring(struct bnx2x *bp)
4222{
a2fbb9ea 4223 spin_lock_init(&bp->spq_lock);
6e30dd4e 4224 atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING);
a2fbb9ea 4225
a2fbb9ea 4226 bp->spq_prod_idx = 0;
a2fbb9ea
ET		 4227 bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
4228 bp->spq_prod_bd = bp->spq;
4229 bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
a2fbb9ea
ET		 4230}
4231
523224a3 4232static void bnx2x_init_eq_ring(struct bnx2x *bp)
a2fbb9ea
ET		 4233{
4234 int i;
523224a3
DK		 4235 for (i = 1; i <= NUM_EQ_PAGES; i++) {
4236 union event_ring_elem *elem =
4237 &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1];
a2fbb9ea 4238
523224a3
DK		 4239 elem->next_page.addr.hi =
4240 cpu_to_le32(U64_HI(bp->eq_mapping +
4241 BCM_PAGE_SIZE * (i % NUM_EQ_PAGES)));
4242 elem->next_page.addr.lo =
4243 cpu_to_le32(U64_LO(bp->eq_mapping +
4244 BCM_PAGE_SIZE*(i % NUM_EQ_PAGES)));
a2fbb9ea 4245 }
523224a3
DK		 4246 bp->eq_cons = 0;
4247 bp->eq_prod = NUM_EQ_DESC;
4248 bp->eq_cons_sb = BNX2X_EQ_INDEX;
6e30dd4e
VZ		 4249 /* we want a warning message before it gets rought... */
4250 atomic_set(&bp->eq_spq_left,
4251 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1);
a2fbb9ea
ET		 4252}
4253
ab532cf3 4254void bnx2x_push_indir_table(struct bnx2x *bp)
a2fbb9ea 4255{
26c8fa4d 4256 int func = BP_FUNC(bp);
a2fbb9ea
ET		 4257 int i;
4258
555f6c78 4259 if (bp->multi_mode == ETH_RSS_MODE_DISABLED)
a2fbb9ea
ET		 4260 return;
4261
4262 for (i = 0; i < TSTORM_INDIRECTION_TABLE_SIZE; i++)
34f80b04 4263 REG_WR8(bp, BAR_TSTRORM_INTMEM +
26c8fa4d 4264 TSTORM_INDIRECTION_TABLE_OFFSET(func) + i,
ab532cf3
TH		 4265 bp->fp->cl_id + bp->rx_indir_table[i]);
4266}
4267
4268static void bnx2x_init_ind_table(struct bnx2x *bp)
4269{
4270 int i;
4271
4272 for (i = 0; i < TSTORM_INDIRECTION_TABLE_SIZE; i++)
4273 bp->rx_indir_table[i] = i % BNX2X_NUM_ETH_QUEUES(bp);
4274
4275 bnx2x_push_indir_table(bp);
a2fbb9ea
ET		 4276}
4277
9f6c9258 4278void bnx2x_set_storm_rx_mode(struct bnx2x *bp)
a2fbb9ea 4279{
34f80b04 4280 int mode = bp->rx_mode;
ec6ba945 4281 int port = BP_PORT(bp);
523224a3 4282 u16 cl_id;
ec6ba945 4283 u32 def_q_filters = 0;
523224a3 4284
581ce43d
EG		 4285 /* All but management unicast packets should pass to the host as well */
4286 u32 llh_mask =
4287 NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_BRCST |
4288 NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_MLCST |
4289 NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_VLAN |
4290 NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_NO_VLAN;
a2fbb9ea 4291
a2fbb9ea
ET		 4292 switch (mode) {
4293 case BNX2X_RX_MODE_NONE: /* no Rx */
ec6ba945
VZ		 4294 def_q_filters = BNX2X_ACCEPT_NONE;
4295#ifdef BCM_CNIC
4296 if (!NO_FCOE(bp)) {
4297 cl_id = bnx2x_fcoe(bp, cl_id);
4298 bnx2x_rxq_set_mac_filters(bp, cl_id, BNX2X_ACCEPT_NONE);
4299 }
4300#endif
a2fbb9ea 4301 break;
356e2385 4302
a2fbb9ea 4303 case BNX2X_RX_MODE_NORMAL:
ec6ba945
VZ		 4304 def_q_filters |= BNX2X_ACCEPT_UNICAST | BNX2X_ACCEPT_BROADCAST |
4305 BNX2X_ACCEPT_MULTICAST;
4306#ifdef BCM_CNIC
711c9146
VZ		 4307 if (!NO_FCOE(bp)) {
4308 cl_id = bnx2x_fcoe(bp, cl_id);
4309 bnx2x_rxq_set_mac_filters(bp, cl_id,
4310 BNX2X_ACCEPT_UNICAST |
4311 BNX2X_ACCEPT_MULTICAST);
4312 }
ec6ba945 4313#endif
a2fbb9ea 4314 break;
356e2385 4315
a2fbb9ea 4316 case BNX2X_RX_MODE_ALLMULTI:
ec6ba945
VZ		 4317 def_q_filters |= BNX2X_ACCEPT_UNICAST | BNX2X_ACCEPT_BROADCAST |
4318 BNX2X_ACCEPT_ALL_MULTICAST;
4319#ifdef BCM_CNIC
711c9146
VZ		 4320 /*
4321 * Prevent duplication of multicast packets by configuring FCoE
4322 * L2 Client to receive only matched unicast frames.
4323 */
4324 if (!NO_FCOE(bp)) {
4325 cl_id = bnx2x_fcoe(bp, cl_id);
4326 bnx2x_rxq_set_mac_filters(bp, cl_id,
4327 BNX2X_ACCEPT_UNICAST);
4328 }
ec6ba945 4329#endif
a2fbb9ea 4330 break;
356e2385 4331
a2fbb9ea 4332 case BNX2X_RX_MODE_PROMISC:
ec6ba945
VZ		 4333 def_q_filters |= BNX2X_PROMISCUOUS_MODE;
4334#ifdef BCM_CNIC
711c9146
VZ		 4335 /*
4336 * Prevent packets duplication by configuring DROP_ALL for FCoE
4337 * L2 Client.
4338 */
4339 if (!NO_FCOE(bp)) {
4340 cl_id = bnx2x_fcoe(bp, cl_id);
4341 bnx2x_rxq_set_mac_filters(bp, cl_id, BNX2X_ACCEPT_NONE);
4342 }
ec6ba945 4343#endif
581ce43d
EG		 4344 /* pass management unicast packets as well */
4345 llh_mask |= NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_UNCST;
a2fbb9ea 4346 break;
356e2385 4347
a2fbb9ea 4348 default:
34f80b04
EG		 4349 BNX2X_ERR("BAD rx mode (%d)\n", mode);
4350 break;
a2fbb9ea
ET		 4351 }
4352
ec6ba945
VZ		 4353 cl_id = BP_L_ID(bp);
4354 bnx2x_rxq_set_mac_filters(bp, cl_id, def_q_filters);
4355
581ce43d 4356 REG_WR(bp,
ec6ba945
VZ		 4357 (port ? NIG_REG_LLH1_BRB1_DRV_MASK :
4358 NIG_REG_LLH0_BRB1_DRV_MASK), llh_mask);
581ce43d 4359
523224a3
DK		 4360 DP(NETIF_MSG_IFUP, "rx mode %d\n"
4361 "drop_ucast 0x%x\ndrop_mcast 0x%x\ndrop_bcast 0x%x\n"
ec6ba945
VZ		 4362 "accp_ucast 0x%x\naccp_mcast 0x%x\naccp_bcast 0x%x\n"
4363 "unmatched_ucast 0x%x\n", mode,
523224a3
DK		 4364 bp->mac_filters.ucast_drop_all,
4365 bp->mac_filters.mcast_drop_all,
4366 bp->mac_filters.bcast_drop_all,
4367 bp->mac_filters.ucast_accept_all,
4368 bp->mac_filters.mcast_accept_all,
ec6ba945
VZ		 4369 bp->mac_filters.bcast_accept_all,
4370 bp->mac_filters.unmatched_unicast
523224a3 4371 );
a2fbb9ea 4372
523224a3 4373 storm_memset_mac_filters(bp, &bp->mac_filters, BP_FUNC(bp));
a2fbb9ea
ET		 4374}
4375
471de716
EG		 4376static void bnx2x_init_internal_common(struct bnx2x *bp)
4377{
4378 int i;
4379
523224a3 4380 if (!CHIP_IS_E1(bp)) {
de832a55 4381
523224a3
DK		 4382 /* xstorm needs to know whether to add ovlan to packets or not,
4383 * in switch-independent we'll write 0 to here... */
34f80b04 4384 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNCTION_MODE_OFFSET,
fb3bff17 4385 bp->mf_mode);
34f80b04 4386 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNCTION_MODE_OFFSET,
fb3bff17 4387 bp->mf_mode);
34f80b04 4388 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNCTION_MODE_OFFSET,
fb3bff17 4389 bp->mf_mode);
34f80b04 4390 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNCTION_MODE_OFFSET,
fb3bff17 4391 bp->mf_mode);
34f80b04
EG		 4392 }
4393
0793f83f
DK		 4394 if (IS_MF_SI(bp))
4395 /*
4396 * In switch independent mode, the TSTORM needs to accept
4397 * packets that failed classification, since approximate match
4398 * mac addresses aren't written to NIG LLH
4399 */
4400 REG_WR8(bp, BAR_TSTRORM_INTMEM +
4401 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 2);
4402
523224a3
DK		 4403 /* Zero this manually as its initialization is
4404 currently missing in the initTool */
4405 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
ca00392c 4406 REG_WR(bp, BAR_USTRORM_INTMEM +
523224a3 4407 USTORM_AGG_DATA_OFFSET + i * 4, 0);
f2e0899f
DK		 4408 if (CHIP_IS_E2(bp)) {
4409 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET,
4410 CHIP_INT_MODE_IS_BC(bp) ?
4411 HC_IGU_BC_MODE : HC_IGU_NBC_MODE);
4412 }
523224a3 4413}
8a1c38d1 4414
523224a3
DK		 4415static void bnx2x_init_internal_port(struct bnx2x *bp)
4416{
4417 /* port */
e4901dde 4418 bnx2x_dcb_init_intmem_pfc(bp);
a2fbb9ea
ET		 4419}
4420
471de716
EG		 4421static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
4422{
4423 switch (load_code) {
4424 case FW_MSG_CODE_DRV_LOAD_COMMON:
f2e0899f 4425 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
471de716
EG		 4426 bnx2x_init_internal_common(bp);
4427 /* no break */
4428
4429 case FW_MSG_CODE_DRV_LOAD_PORT:
4430 bnx2x_init_internal_port(bp);
4431 /* no break */
4432
4433 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
523224a3
DK		 4434 /* internal memory per function is
4435 initialized inside bnx2x_pf_init */
471de716
EG		 4436 break;
4437
4438 default:
4439 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
4440 break;
4441 }
4442}
4443
523224a3
DK		 4444static void bnx2x_init_fp_sb(struct bnx2x *bp, int fp_idx)
4445{
4446 struct bnx2x_fastpath *fp = &bp->fp[fp_idx];
4447
4448 fp->state = BNX2X_FP_STATE_CLOSED;
4449
b3b83c3f 4450 fp->cid = fp_idx;
523224a3
DK		 4451 fp->cl_id = BP_L_ID(bp) + fp_idx;
4452 fp->fw_sb_id = bp->base_fw_ndsb + fp->cl_id + CNIC_CONTEXT_USE;
4453 fp->igu_sb_id = bp->igu_base_sb + fp_idx + CNIC_CONTEXT_USE;
4454 /* qZone id equals to FW (per path) client id */
4455 fp->cl_qzone_id = fp->cl_id +
f2e0899f
DK		 4456 BP_PORT(bp)*(CHIP_IS_E2(bp) ? ETH_MAX_RX_CLIENTS_E2 :
4457 ETH_MAX_RX_CLIENTS_E1H);
523224a3 4458 /* init shortcut */
f2e0899f
DK		 4459 fp->ustorm_rx_prods_offset = CHIP_IS_E2(bp) ?
4460 USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id) :
523224a3
DK		 4461 USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp), fp->cl_id);
4462 /* Setup SB indicies */
4463 fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
4464 fp->tx_cons_sb = BNX2X_TX_SB_INDEX;
4465
4466 DP(NETIF_MSG_IFUP, "queue[%d]: bnx2x_init_sb(%p,%p) "
4467 "cl_id %d fw_sb %d igu_sb %d\n",
4468 fp_idx, bp, fp->status_blk.e1x_sb, fp->cl_id, fp->fw_sb_id,
4469 fp->igu_sb_id);
4470 bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false,
4471 fp->fw_sb_id, fp->igu_sb_id);
4472
4473 bnx2x_update_fpsb_idx(fp);
4474}
4475
9f6c9258 4476void bnx2x_nic_init(struct bnx2x *bp, u32 load_code)
a2fbb9ea
ET		 4477{
4478 int i;
4479
ec6ba945 4480 for_each_eth_queue(bp, i)
523224a3 4481 bnx2x_init_fp_sb(bp, i);
37b091ba 4482#ifdef BCM_CNIC
ec6ba945
VZ		 4483 if (!NO_FCOE(bp))
4484 bnx2x_init_fcoe_fp(bp);
523224a3
DK		 4485
4486 bnx2x_init_sb(bp, bp->cnic_sb_mapping,
4487 BNX2X_VF_ID_INVALID, false,
4488 CNIC_SB_ID(bp), CNIC_IGU_SB_ID(bp));
4489
37b091ba 4490#endif
a2fbb9ea 4491
16119785
EG		 4492 /* ensure status block indices were read */
4493 rmb();
4494
523224a3 4495 bnx2x_init_def_sb(bp);
5c862848 4496 bnx2x_update_dsb_idx(bp);
a2fbb9ea 4497 bnx2x_init_rx_rings(bp);
523224a3 4498 bnx2x_init_tx_rings(bp);
a2fbb9ea 4499 bnx2x_init_sp_ring(bp);
523224a3 4500 bnx2x_init_eq_ring(bp);
471de716 4501 bnx2x_init_internal(bp, load_code);
523224a3 4502 bnx2x_pf_init(bp);
a2fbb9ea 4503 bnx2x_init_ind_table(bp);
0ef00459
EG		 4504 bnx2x_stats_init(bp);
4505
4506 /* At this point, we are ready for interrupts */
4507 atomic_set(&bp->intr_sem, 0);
4508
4509 /* flush all before enabling interrupts */
4510 mb();
4511 mmiowb();
4512
615f8fd9 4513 bnx2x_int_enable(bp);
eb8da205
EG		 4514
4515 /* Check for SPIO5 */
4516 bnx2x_attn_int_deasserted0(bp,
4517 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) &
4518 AEU_INPUTS_ATTN_BITS_SPIO5);
a2fbb9ea
ET		 4519}
4520
4521/* end of nic init */
4522
4523/*
4524 * gzip service functions
4525 */
4526
4527static int bnx2x_gunzip_init(struct bnx2x *bp)
4528{
1a983142
FT		 4529 bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE,
4530 &bp->gunzip_mapping, GFP_KERNEL);
a2fbb9ea
ET		 4531 if (bp->gunzip_buf == NULL)
4532 goto gunzip_nomem1;
4533
4534 bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
4535 if (bp->strm == NULL)
4536 goto gunzip_nomem2;
4537
4538 bp->strm->workspace = kmalloc(zlib_inflate_workspacesize(),
4539 GFP_KERNEL);
4540 if (bp->strm->workspace == NULL)
4541 goto gunzip_nomem3;
4542
4543 return 0;
4544
4545gunzip_nomem3:
4546 kfree(bp->strm);
4547 bp->strm = NULL;
4548
4549gunzip_nomem2:
1a983142
FT		 4550 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
4551 bp->gunzip_mapping);
a2fbb9ea
ET		 4552 bp->gunzip_buf = NULL;
4553
4554gunzip_nomem1:
cdaa7cb8
VZ		 4555 netdev_err(bp->dev, "Cannot allocate firmware buffer for"
4556 " un-compression\n");
a2fbb9ea
ET		 4557 return -ENOMEM;
4558}
4559
4560static void bnx2x_gunzip_end(struct bnx2x *bp)
4561{
b3b83c3f
DK		 4562 if (bp->strm) {
4563 kfree(bp->strm->workspace);
4564 kfree(bp->strm);
4565 bp->strm = NULL;
4566 }
a2fbb9ea
ET		 4567
4568 if (bp->gunzip_buf) {
1a983142
FT		 4569 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
4570 bp->gunzip_mapping);
a2fbb9ea
ET		 4571 bp->gunzip_buf = NULL;
4572 }
4573}
4574
94a78b79 4575static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len)
a2fbb9ea
ET		 4576{
4577 int n, rc;
4578
4579 /* check gzip header */
94a78b79
VZ		 4580 if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) {
4581 BNX2X_ERR("Bad gzip header\n");
a2fbb9ea 4582 return -EINVAL;
94a78b79 4583 }
a2fbb9ea
ET		 4584
4585 n = 10;
4586
34f80b04 4587#define FNAME 0x8
a2fbb9ea
ET		 4588
4589 if (zbuf[3] & FNAME)
4590 while ((zbuf[n++] != 0) && (n < len));
4591
94a78b79 4592 bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n;
a2fbb9ea
ET		 4593 bp->strm->avail_in = len - n;
4594 bp->strm->next_out = bp->gunzip_buf;
4595 bp->strm->avail_out = FW_BUF_SIZE;
4596
4597 rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
4598 if (rc != Z_OK)
4599 return rc;
4600
4601 rc = zlib_inflate(bp->strm, Z_FINISH);
4602 if ((rc != Z_OK) && (rc != Z_STREAM_END))
7995c64e
JP		 4603 netdev_err(bp->dev, "Firmware decompression error: %s\n",
4604 bp->strm->msg);
a2fbb9ea
ET		 4605
4606 bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
4607 if (bp->gunzip_outlen & 0x3)
cdaa7cb8
VZ		 4608 netdev_err(bp->dev, "Firmware decompression error:"
4609 " gunzip_outlen (%d) not aligned\n",
4610 bp->gunzip_outlen);
a2fbb9ea
ET		 4611 bp->gunzip_outlen >>= 2;
4612
4613 zlib_inflateEnd(bp->strm);
4614
4615 if (rc == Z_STREAM_END)
4616 return 0;
4617
4618 return rc;
4619}
4620
4621/* nic load/unload */
4622
4623/*
34f80b04 4624 * General service functions
a2fbb9ea
ET		 4625 */
4626
4627/* send a NIG loopback debug packet */
4628static void bnx2x_lb_pckt(struct bnx2x *bp)
4629{
a2fbb9ea 4630 u32 wb_write[3];
a2fbb9ea
ET		 4631
4632 /* Ethernet source and destination addresses */
a2fbb9ea
ET		 4633 wb_write[0] = 0x55555555;
4634 wb_write[1] = 0x55555555;
34f80b04 4635 wb_write[2] = 0x20; /* SOP */
a2fbb9ea 4636 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
a2fbb9ea
ET		 4637
4638 /* NON-IP protocol */
a2fbb9ea
ET		 4639 wb_write[0] = 0x09000000;
4640 wb_write[1] = 0x55555555;
34f80b04 4641 wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */
a2fbb9ea 4642 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
a2fbb9ea
ET		 4643}
4644
4645/* some of the internal memories
4646 * are not directly readable from the driver
4647 * to test them we send debug packets
4648 */
4649static int bnx2x_int_mem_test(struct bnx2x *bp)
4650{
4651 int factor;
4652 int count, i;
4653 u32 val = 0;
4654
ad8d3948 4655 if (CHIP_REV_IS_FPGA(bp))
a2fbb9ea 4656 factor = 120;
ad8d3948
EG		 4657 else if (CHIP_REV_IS_EMUL(bp))
4658 factor = 200;
4659 else
a2fbb9ea 4660 factor = 1;
a2fbb9ea 4661
a2fbb9ea
ET		 4662 /* Disable inputs of parser neighbor blocks */
4663 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
4664 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
4665 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
3196a88a 4666 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
a2fbb9ea
ET		 4667
4668 /* Write 0 to parser credits for CFC search request */
4669 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
4670
4671 /* send Ethernet packet */
4672 bnx2x_lb_pckt(bp);
4673
4674 /* TODO do i reset NIG statistic? */
4675 /* Wait until NIG register shows 1 packet of size 0x10 */
4676 count = 1000 * factor;
4677 while (count) {
34f80b04 4678
a2fbb9ea
ET		 4679 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
4680 val = *bnx2x_sp(bp, wb_data[0]);
a2fbb9ea
ET		 4681 if (val == 0x10)
4682 break;
4683
4684 msleep(10);
4685 count--;
4686 }
4687 if (val != 0x10) {
4688 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
4689 return -1;
4690 }
4691
4692 /* Wait until PRS register shows 1 packet */
4693 count = 1000 * factor;
4694 while (count) {
4695 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
a2fbb9ea
ET		 4696 if (val == 1)
4697 break;
4698
4699 msleep(10);
4700 count--;
4701 }
4702 if (val != 0x1) {
4703 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
4704 return -2;
4705 }
4706
4707 /* Reset and init BRB, PRS */
34f80b04 4708 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
a2fbb9ea 4709 msleep(50);
34f80b04 4710 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
a2fbb9ea 4711 msleep(50);
94a78b79
VZ		 4712 bnx2x_init_block(bp, BRB1_BLOCK, COMMON_STAGE);
4713 bnx2x_init_block(bp, PRS_BLOCK, COMMON_STAGE);
a2fbb9ea
ET		 4714
4715 DP(NETIF_MSG_HW, "part2\n");
4716
4717 /* Disable inputs of parser neighbor blocks */
4718 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
4719 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
4720 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
3196a88a 4721 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
a2fbb9ea
ET		 4722
4723 /* Write 0 to parser credits for CFC search request */
4724 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
4725
4726 /* send 10 Ethernet packets */
4727 for (i = 0; i < 10; i++)
4728 bnx2x_lb_pckt(bp);
4729
4730 /* Wait until NIG register shows 10 + 1
4731 packets of size 11*0x10 = 0xb0 */
4732 count = 1000 * factor;
4733 while (count) {
34f80b04 4734
a2fbb9ea
ET		 4735 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
4736 val = *bnx2x_sp(bp, wb_data[0]);
a2fbb9ea
ET		 4737 if (val == 0xb0)
4738 break;
4739
4740 msleep(10);
4741 count--;
4742 }
4743 if (val != 0xb0) {
4744 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
4745 return -3;
4746 }
4747
4748 /* Wait until PRS register shows 2 packets */
4749 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
4750 if (val != 2)
4751 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
4752
4753 /* Write 1 to parser credits for CFC search request */
4754 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
4755
4756 /* Wait until PRS register shows 3 packets */
4757 msleep(10 * factor);
4758 /* Wait until NIG register shows 1 packet of size 0x10 */
4759 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
4760 if (val != 3)
4761 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
4762
4763 /* clear NIG EOP FIFO */
4764 for (i = 0; i < 11; i++)
4765 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);
4766 val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);
4767 if (val != 1) {
4768 BNX2X_ERR("clear of NIG failed\n");
4769 return -4;
4770 }
4771
4772 /* Reset and init BRB, PRS, NIG */
4773 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
4774 msleep(50);
4775 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
4776 msleep(50);
94a78b79
VZ		 4777 bnx2x_init_block(bp, BRB1_BLOCK, COMMON_STAGE);
4778 bnx2x_init_block(bp, PRS_BLOCK, COMMON_STAGE);
37b091ba 4779#ifndef BCM_CNIC
a2fbb9ea
ET		 4780 /* set NIC mode */
4781 REG_WR(bp, PRS_REG_NIC_MODE, 1);
4782#endif
4783
4784 /* Enable inputs of parser neighbor blocks */
4785 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
4786 REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
4787 REG_WR(bp, CFC_REG_DEBUG0, 0x0);
3196a88a 4788 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1);
a2fbb9ea
ET		 4789
4790 DP(NETIF_MSG_HW, "done\n");
4791
4792 return 0; /* OK */
4793}
4794
4a33bc03 4795static void bnx2x_enable_blocks_attention(struct bnx2x *bp)
a2fbb9ea
ET		 4796{
4797 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
f2e0899f
DK		 4798 if (CHIP_IS_E2(bp))
4799 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40);
4800 else
4801 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
a2fbb9ea
ET		 4802 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
4803 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
f2e0899f
DK		 4804 /*
4805 * mask read length error interrupts in brb for parser
4806 * (parsing unit and 'checksum and crc' unit)
4807 * these errors are legal (PU reads fixed length and CAC can cause
4808 * read length error on truncated packets)
4809 */
4810 REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00);
a2fbb9ea
ET		 4811 REG_WR(bp, QM_REG_QM_INT_MASK, 0);
4812 REG_WR(bp, TM_REG_TM_INT_MASK, 0);
4813 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
4814 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0);
4815 REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
34f80b04
EG		 4816/* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
4817/* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
a2fbb9ea
ET		 4818 REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0);
4819 REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0);
4820 REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
34f80b04
EG		 4821/* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
4822/* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
a2fbb9ea
ET		 4823 REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
4824 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0);
4825 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0);
4826 REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
34f80b04
EG		 4827/* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
4828/* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
f85582f8 4829
34f80b04
EG		 4830 if (CHIP_REV_IS_FPGA(bp))
4831 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x580000);
f2e0899f
DK		 4832 else if (CHIP_IS_E2(bp))
4833 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0,
4834 (PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF
4835 | PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT
4836 | PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN
4837 | PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED
4838 | PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED));
34f80b04
EG		 4839 else
4840 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x480000);
a2fbb9ea
ET		 4841 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
4842 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
4843 REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
34f80b04
EG		 4844/* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
4845/* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0); */
a2fbb9ea
ET		 4846 REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
4847 REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
34f80b04 4848/* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
4a33bc03 4849 REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */
a2fbb9ea
ET		 4850}
4851
81f75bbf
EG		 4852static void bnx2x_reset_common(struct bnx2x *bp)
4853{
4854 /* reset_common */
4855 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
4856 0xd3ffff7f);
4857 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 0x1403);
4858}
4859
573f2035
EG		 4860static void bnx2x_init_pxp(struct bnx2x *bp)
4861{
4862 u16 devctl;
4863 int r_order, w_order;
4864
4865 pci_read_config_word(bp->pdev,
4866 bp->pcie_cap + PCI_EXP_DEVCTL, &devctl);
4867 DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
4868 w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
4869 if (bp->mrrs == -1)
4870 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12);
4871 else {
4872 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs);
4873 r_order = bp->mrrs;
4874 }
4875
4876 bnx2x_init_pxp_arb(bp, r_order, w_order);
4877}
fd4ef40d
EG		 4878
4879static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp)
4880{
2145a920 4881 int is_required;
fd4ef40d 4882 u32 val;
2145a920 4883 int port;
fd4ef40d 4884
2145a920
VZ		 4885 if (BP_NOMCP(bp))
4886 return;
4887
4888 is_required = 0;
fd4ef40d
EG		 4889 val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
4890 SHARED_HW_CFG_FAN_FAILURE_MASK;
4891
4892 if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED)
4893 is_required = 1;
4894
4895 /*
4896 * The fan failure mechanism is usually related to the PHY type since
4897 * the power consumption of the board is affected by the PHY. Currently,
4898 * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
4899 */
4900 else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE)
4901 for (port = PORT_0; port < PORT_MAX; port++) {
fd4ef40d 4902 is_required |=
d90d96ba
YR		 4903 bnx2x_fan_failure_det_req(
4904 bp,
4905 bp->common.shmem_base,
a22f0788 4906 bp->common.shmem2_base,
d90d96ba 4907 port);
fd4ef40d
EG		 4908 }
4909
4910 DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required);
4911
4912 if (is_required == 0)
4913 return;
4914
4915 /* Fan failure is indicated by SPIO 5 */
4916 bnx2x_set_spio(bp, MISC_REGISTERS_SPIO_5,
4917 MISC_REGISTERS_SPIO_INPUT_HI_Z);
4918
4919 /* set to active low mode */
4920 val = REG_RD(bp, MISC_REG_SPIO_INT);
4921 val |= ((1 << MISC_REGISTERS_SPIO_5) <<
cdaa7cb8 4922 MISC_REGISTERS_SPIO_INT_OLD_SET_POS);
fd4ef40d
EG		 4923 REG_WR(bp, MISC_REG_SPIO_INT, val);
4924
4925 /* enable interrupt to signal the IGU */
4926 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
4927 val |= (1 << MISC_REGISTERS_SPIO_5);
4928 REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
4929}
4930
f2e0899f
DK		 4931static void bnx2x_pretend_func(struct bnx2x *bp, u8 pretend_func_num)
4932{
4933 u32 offset = 0;
4934
4935 if (CHIP_IS_E1(bp))
4936 return;
4937 if (CHIP_IS_E1H(bp) && (pretend_func_num >= E1H_FUNC_MAX))
4938 return;
4939
4940 switch (BP_ABS_FUNC(bp)) {
4941 case 0:
4942 offset = PXP2_REG_PGL_PRETEND_FUNC_F0;
4943 break;
4944 case 1:
4945 offset = PXP2_REG_PGL_PRETEND_FUNC_F1;
4946 break;
4947 case 2:
4948 offset = PXP2_REG_PGL_PRETEND_FUNC_F2;
4949 break;
4950 case 3:
4951 offset = PXP2_REG_PGL_PRETEND_FUNC_F3;
4952 break;
4953 case 4:
4954 offset = PXP2_REG_PGL_PRETEND_FUNC_F4;
4955 break;
4956 case 5:
4957 offset = PXP2_REG_PGL_PRETEND_FUNC_F5;
4958 break;
4959 case 6:
4960 offset = PXP2_REG_PGL_PRETEND_FUNC_F6;
4961 break;
4962 case 7:
4963 offset = PXP2_REG_PGL_PRETEND_FUNC_F7;
4964 break;
4965 default:
4966 return;
4967 }
4968
4969 REG_WR(bp, offset, pretend_func_num);
4970 REG_RD(bp, offset);
4971 DP(NETIF_MSG_HW, "Pretending to func %d\n", pretend_func_num);
4972}
4973
4974static void bnx2x_pf_disable(struct bnx2x *bp)
4975{
4976 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
4977 val &= ~IGU_PF_CONF_FUNC_EN;
4978
4979 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
4980 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
4981 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0);
4982}
4983
523224a3 4984static int bnx2x_init_hw_common(struct bnx2x *bp, u32 load_code)
a2fbb9ea 4985{
a2fbb9ea 4986 u32 val, i;
a2fbb9ea 4987
f2e0899f 4988 DP(BNX2X_MSG_MCP, "starting common init func %d\n", BP_ABS_FUNC(bp));
a2fbb9ea 4989
81f75bbf 4990 bnx2x_reset_common(bp);
34f80b04
EG		 4991 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
4992 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 0xfffc);
a2fbb9ea 4993
94a78b79 4994 bnx2x_init_block(bp, MISC_BLOCK, COMMON_STAGE);
f2e0899f 4995 if (!CHIP_IS_E1(bp))
fb3bff17 4996 REG_WR(bp, MISC_REG_E1HMF_MODE, IS_MF(bp));
a2fbb9ea 4997
f2e0899f
DK		 4998 if (CHIP_IS_E2(bp)) {
4999 u8 fid;
5000
5001 /**
5002 * 4-port mode or 2-port mode we need to turn of master-enable
5003 * for everyone, after that, turn it back on for self.
5004 * so, we disregard multi-function or not, and always disable
5005 * for all functions on the given path, this means 0,2,4,6 for
5006 * path 0 and 1,3,5,7 for path 1
5007 */
5008 for (fid = BP_PATH(bp); fid < E2_FUNC_MAX*2; fid += 2) {
5009 if (fid == BP_ABS_FUNC(bp)) {
5010 REG_WR(bp,
5011 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
5012 1);
5013 continue;
5014 }
5015
5016 bnx2x_pretend_func(bp, fid);
5017 /* clear pf enable */
5018 bnx2x_pf_disable(bp);
5019 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
5020 }
5021 }
a2fbb9ea 5022
94a78b79 5023 bnx2x_init_block(bp, PXP_BLOCK, COMMON_STAGE);
34f80b04
EG		 5024 if (CHIP_IS_E1(bp)) {
5025 /* enable HW interrupt from PXP on USDM overflow
5026 bit 16 on INT_MASK_0 */
5027 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
5028 }
a2fbb9ea 5029
94a78b79 5030 bnx2x_init_block(bp, PXP2_BLOCK, COMMON_STAGE);
34f80b04 5031 bnx2x_init_pxp(bp);
a2fbb9ea
ET		 5032
5033#ifdef __BIG_ENDIAN
34f80b04
EG		 5034 REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1);
5035 REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1);
5036 REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
5037 REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
5038 REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
8badd27a
EG		 5039 /* make sure this value is 0 */
5040 REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0);
34f80b04
EG		 5041
5042/* REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */
5043 REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1);
5044 REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1);
5045 REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1);
5046 REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
a2fbb9ea
ET		 5047#endif
5048
523224a3
DK		 5049 bnx2x_ilt_init_page_size(bp, INITOP_SET);
5050
34f80b04
EG		 5051 if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
5052 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
a2fbb9ea 5053
34f80b04
EG		 5054 /* let the HW do it's magic ... */
5055 msleep(100);
5056 /* finish PXP init */
5057 val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
5058 if (val != 1) {
5059 BNX2X_ERR("PXP2 CFG failed\n");
5060 return -EBUSY;
5061 }
5062 val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
5063 if (val != 1) {
5064 BNX2X_ERR("PXP2 RD_INIT failed\n");
5065 return -EBUSY;
5066 }
a2fbb9ea 5067
f2e0899f
DK		 5068 /* Timers bug workaround E2 only. We need to set the entire ILT to
5069 * have entries with value "0" and valid bit on.
5070 * This needs to be done by the first PF that is loaded in a path
5071 * (i.e. common phase)
5072 */
5073 if (CHIP_IS_E2(bp)) {
5074 struct ilt_client_info ilt_cli;
5075 struct bnx2x_ilt ilt;
5076 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
5077 memset(&ilt, 0, sizeof(struct bnx2x_ilt));
5078
b595076a 5079 /* initialize dummy TM client */
f2e0899f
DK		 5080 ilt_cli.start = 0;
5081 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
5082 ilt_cli.client_num = ILT_CLIENT_TM;
5083
5084 /* Step 1: set zeroes to all ilt page entries with valid bit on
5085 * Step 2: set the timers first/last ilt entry to point
5086 * to the entire range to prevent ILT range error for 3rd/4th
25985edc 5087 * vnic (this code assumes existence of the vnic)
f2e0899f
DK		 5088 *
5089 * both steps performed by call to bnx2x_ilt_client_init_op()
5090 * with dummy TM client
5091 *
5092 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
5093 * and his brother are split registers
5094 */
5095 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6));
5096 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR);
5097 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
5098
5099 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
5100 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
5101 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
5102 }
5103
5104
34f80b04
EG		 5105 REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
5106 REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
a2fbb9ea 5107
f2e0899f
DK		 5108 if (CHIP_IS_E2(bp)) {
5109 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 :
5110 (CHIP_REV_IS_FPGA(bp) ? 400 : 0);
5111 bnx2x_init_block(bp, PGLUE_B_BLOCK, COMMON_STAGE);
5112
5113 bnx2x_init_block(bp, ATC_BLOCK, COMMON_STAGE);
5114
5115 /* let the HW do it's magic ... */
5116 do {
5117 msleep(200);
5118 val = REG_RD(bp, ATC_REG_ATC_INIT_DONE);
5119 } while (factor-- && (val != 1));
5120
5121 if (val != 1) {
5122 BNX2X_ERR("ATC_INIT failed\n");
5123 return -EBUSY;
5124 }
5125 }
5126
94a78b79 5127 bnx2x_init_block(bp, DMAE_BLOCK, COMMON_STAGE);
a2fbb9ea 5128
34f80b04
EG		 5129 /* clean the DMAE memory */
5130 bp->dmae_ready = 1;
5131 bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8);
a2fbb9ea 5132
94a78b79
VZ		 5133 bnx2x_init_block(bp, TCM_BLOCK, COMMON_STAGE);
5134 bnx2x_init_block(bp, UCM_BLOCK, COMMON_STAGE);
5135 bnx2x_init_block(bp, CCM_BLOCK, COMMON_STAGE);
5136 bnx2x_init_block(bp, XCM_BLOCK, COMMON_STAGE);
a2fbb9ea 5137
34f80b04
EG		 5138 bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
5139 bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
5140 bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
5141 bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
5142
94a78b79 5143 bnx2x_init_block(bp, QM_BLOCK, COMMON_STAGE);
37b091ba 5144
f2e0899f
DK		 5145 if (CHIP_MODE_IS_4_PORT(bp))
5146 bnx2x_init_block(bp, QM_4PORT_BLOCK, COMMON_STAGE);
f85582f8 5147
523224a3
DK		 5148 /* QM queues pointers table */
5149 bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET);
5150
34f80b04
EG		 5151 /* soft reset pulse */
5152 REG_WR(bp, QM_REG_SOFT_RESET, 1);
5153 REG_WR(bp, QM_REG_SOFT_RESET, 0);
a2fbb9ea 5154
37b091ba 5155#ifdef BCM_CNIC
94a78b79 5156 bnx2x_init_block(bp, TIMERS_BLOCK, COMMON_STAGE);
a2fbb9ea 5157#endif
a2fbb9ea 5158
94a78b79 5159 bnx2x_init_block(bp, DQ_BLOCK, COMMON_STAGE);
523224a3
DK		 5160 REG_WR(bp, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT);
5161
34f80b04
EG		 5162 if (!CHIP_REV_IS_SLOW(bp)) {
5163 /* enable hw interrupt from doorbell Q */
5164 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
5165 }
a2fbb9ea 5166
94a78b79 5167 bnx2x_init_block(bp, BRB1_BLOCK, COMMON_STAGE);
f2e0899f
DK		 5168 if (CHIP_MODE_IS_4_PORT(bp)) {
5169 REG_WR(bp, BRB1_REG_FULL_LB_XOFF_THRESHOLD, 248);
5170 REG_WR(bp, BRB1_REG_FULL_LB_XON_THRESHOLD, 328);
5171 }
5172
94a78b79 5173 bnx2x_init_block(bp, PRS_BLOCK, COMMON_STAGE);
26c8fa4d 5174 REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
37b091ba 5175#ifndef BCM_CNIC
3196a88a
EG		 5176 /* set NIC mode */
5177 REG_WR(bp, PRS_REG_NIC_MODE, 1);
37b091ba 5178#endif
f2e0899f 5179 if (!CHIP_IS_E1(bp))
0793f83f 5180 REG_WR(bp, PRS_REG_E1HOV_MODE, IS_MF_SD(bp));
f85582f8 5181
f2e0899f
DK		 5182 if (CHIP_IS_E2(bp)) {
5183 /* Bit-map indicating which L2 hdrs may appear after the
5184 basic Ethernet header */
0793f83f 5185 int has_ovlan = IS_MF_SD(bp);
f2e0899f
DK		 5186 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, (has_ovlan ? 7 : 6));
5187 REG_WR(bp, PRS_REG_MUST_HAVE_HDRS, (has_ovlan ? 1 : 0));
5188 }
a2fbb9ea 5189
94a78b79
VZ		 5190 bnx2x_init_block(bp, TSDM_BLOCK, COMMON_STAGE);
5191 bnx2x_init_block(bp, CSDM_BLOCK, COMMON_STAGE);
5192 bnx2x_init_block(bp, USDM_BLOCK, COMMON_STAGE);
5193 bnx2x_init_block(bp, XSDM_BLOCK, COMMON_STAGE);
a2fbb9ea 5194
ca00392c
EG		 5195 bnx2x_init_fill(bp, TSEM_REG_FAST_MEMORY, 0, STORM_INTMEM_SIZE(bp));
5196 bnx2x_init_fill(bp, USEM_REG_FAST_MEMORY, 0, STORM_INTMEM_SIZE(bp));
5197 bnx2x_init_fill(bp, CSEM_REG_FAST_MEMORY, 0, STORM_INTMEM_SIZE(bp));
5198 bnx2x_init_fill(bp, XSEM_REG_FAST_MEMORY, 0, STORM_INTMEM_SIZE(bp));
a2fbb9ea 5199
94a78b79
VZ		 5200 bnx2x_init_block(bp, TSEM_BLOCK, COMMON_STAGE);
5201 bnx2x_init_block(bp, USEM_BLOCK, COMMON_STAGE);
5202 bnx2x_init_block(bp, CSEM_BLOCK, COMMON_STAGE);
5203 bnx2x_init_block(bp, XSEM_BLOCK, COMMON_STAGE);
a2fbb9ea 5204
f2e0899f
DK		 5205 if (CHIP_MODE_IS_4_PORT(bp))
5206 bnx2x_init_block(bp, XSEM_4PORT_BLOCK, COMMON_STAGE);
5207
34f80b04
EG		 5208 /* sync semi rtc */
5209 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
5210 0x80000000);
5211 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
5212 0x80000000);
a2fbb9ea 5213
94a78b79
VZ		 5214 bnx2x_init_block(bp, UPB_BLOCK, COMMON_STAGE);
5215 bnx2x_init_block(bp, XPB_BLOCK, COMMON_STAGE);
5216 bnx2x_init_block(bp, PBF_BLOCK, COMMON_STAGE);
a2fbb9ea 5217
f2e0899f 5218 if (CHIP_IS_E2(bp)) {
0793f83f 5219 int has_ovlan = IS_MF_SD(bp);
f2e0899f
DK		 5220 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, (has_ovlan ? 7 : 6));
5221 REG_WR(bp, PBF_REG_MUST_HAVE_HDRS, (has_ovlan ? 1 : 0));
5222 }
5223
34f80b04 5224 REG_WR(bp, SRC_REG_SOFT_RST, 1);
c68ed255
TH		 5225 for (i = SRC_REG_KEYRSS0_0; i <= SRC_REG_KEYRSS1_9; i += 4)
5226 REG_WR(bp, i, random32());
f85582f8 5227
94a78b79 5228 bnx2x_init_block(bp, SRCH_BLOCK, COMMON_STAGE);
37b091ba
MC		 5229#ifdef BCM_CNIC
5230 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672);
5231 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
5232 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b);
5233 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a);
5234 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116);
5235 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
5236 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf);
5237 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
5238 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f);
5239 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7);
5240#endif
34f80b04 5241 REG_WR(bp, SRC_REG_SOFT_RST, 0);
a2fbb9ea 5242
34f80b04
EG		 5243 if (sizeof(union cdu_context) != 1024)
5244 /* we currently assume that a context is 1024 bytes */
cdaa7cb8
VZ		 5245 dev_alert(&bp->pdev->dev, "please adjust the size "
5246 "of cdu_context(%ld)\n",
7995c64e 5247 (long)sizeof(union cdu_context));
a2fbb9ea 5248
94a78b79 5249 bnx2x_init_block(bp, CDU_BLOCK, COMMON_STAGE);
34f80b04
EG		 5250 val = (4 << 24) + (0 << 12) + 1024;
5251 REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
a2fbb9ea 5252
94a78b79 5253 bnx2x_init_block(bp, CFC_BLOCK, COMMON_STAGE);
34f80b04 5254 REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
8d9c5f34
EG		 5255 /* enable context validation interrupt from CFC */
5256 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
5257
5258 /* set the thresholds to prevent CFC/CDU race */
5259 REG_WR(bp, CFC_REG_DEBUG0, 0x20020000);
a2fbb9ea 5260
94a78b79 5261 bnx2x_init_block(bp, HC_BLOCK, COMMON_STAGE);
f2e0899f
DK		 5262
5263 if (CHIP_IS_E2(bp) && BP_NOMCP(bp))
5264 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36);
5265
5266 bnx2x_init_block(bp, IGU_BLOCK, COMMON_STAGE);
94a78b79 5267 bnx2x_init_block(bp, MISC_AEU_BLOCK, COMMON_STAGE);
a2fbb9ea 5268
94a78b79 5269 bnx2x_init_block(bp, PXPCS_BLOCK, COMMON_STAGE);
34f80b04
EG		 5270 /* Reset PCIE errors for debug */
5271 REG_WR(bp, 0x2814, 0xffffffff);
5272 REG_WR(bp, 0x3820, 0xffffffff);
a2fbb9ea 5273
f2e0899f
DK		 5274 if (CHIP_IS_E2(bp)) {
5275 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
5276 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
5277 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
5278 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
5279 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
5280 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
5281 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
5282 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
5283 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
5284 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
5285 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
5286 }
5287
94a78b79 5288 bnx2x_init_block(bp, EMAC0_BLOCK, COMMON_STAGE);
94a78b79 5289 bnx2x_init_block(bp, EMAC1_BLOCK, COMMON_STAGE);
94a78b79 5290 bnx2x_init_block(bp, DBU_BLOCK, COMMON_STAGE);
94a78b79 5291 bnx2x_init_block(bp, DBG_BLOCK, COMMON_STAGE);
34f80b04 5292
94a78b79 5293 bnx2x_init_block(bp, NIG_BLOCK, COMMON_STAGE);
f2e0899f 5294 if (!CHIP_IS_E1(bp)) {
fb3bff17 5295 REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp));
0793f83f 5296 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp));
34f80b04 5297 }
f2e0899f
DK		 5298 if (CHIP_IS_E2(bp)) {
5299 /* Bit-map indicating which L2 hdrs may appear after the
5300 basic Ethernet header */
0793f83f 5301 REG_WR(bp, NIG_REG_P0_HDRS_AFTER_BASIC, (IS_MF_SD(bp) ? 7 : 6));
f2e0899f 5302 }
34f80b04
EG		 5303
5304 if (CHIP_REV_IS_SLOW(bp))
5305 msleep(200);
5306
5307 /* finish CFC init */
5308 val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10);
5309 if (val != 1) {
5310 BNX2X_ERR("CFC LL_INIT failed\n");
5311 return -EBUSY;
5312 }
5313 val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10);
5314 if (val != 1) {
5315 BNX2X_ERR("CFC AC_INIT failed\n");
5316 return -EBUSY;
5317 }
5318 val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
5319 if (val != 1) {
5320 BNX2X_ERR("CFC CAM_INIT failed\n");
5321 return -EBUSY;
5322 }
5323 REG_WR(bp, CFC_REG_DEBUG0, 0);
f1410647 5324
f2e0899f
DK		 5325 if (CHIP_IS_E1(bp)) {
5326 /* read NIG statistic
5327 to see if this is our first up since powerup */
5328 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
5329 val = *bnx2x_sp(bp, wb_data[0]);
34f80b04 5330
f2e0899f
DK		 5331 /* do internal memory self test */
5332 if ((val == 0) && bnx2x_int_mem_test(bp)) {
5333 BNX2X_ERR("internal mem self test failed\n");
5334 return -EBUSY;
5335 }
34f80b04
EG		 5336 }
5337
fd4ef40d
EG		 5338 bnx2x_setup_fan_failure_detection(bp);
5339
34f80b04
EG		 5340 /* clear PXP2 attentions */
5341 REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
a2fbb9ea 5342
4a33bc03
VZ		 5343 bnx2x_enable_blocks_attention(bp);
5344 if (CHIP_PARITY_ENABLED(bp))
5345 bnx2x_enable_blocks_parity(bp);
a2fbb9ea 5346
6bbca910 5347 if (!BP_NOMCP(bp)) {
f2e0899f
DK		 5348 /* In E2 2-PORT mode, same ext phy is used for the two paths */
5349 if ((load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) ||
5350 CHIP_IS_E1x(bp)) {
5351 u32 shmem_base[2], shmem2_base[2];
5352 shmem_base[0] = bp->common.shmem_base;
5353 shmem2_base[0] = bp->common.shmem2_base;
5354 if (CHIP_IS_E2(bp)) {
5355 shmem_base[1] =
5356 SHMEM2_RD(bp, other_shmem_base_addr);
5357 shmem2_base[1] =
5358 SHMEM2_RD(bp, other_shmem2_base_addr);
5359 }
5360 bnx2x_acquire_phy_lock(bp);
5361 bnx2x_common_init_phy(bp, shmem_base, shmem2_base,
5362 bp->common.chip_id);
5363 bnx2x_release_phy_lock(bp);
5364 }
6bbca910
YR		 5365 } else
5366 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
5367
34f80b04
EG		 5368 return 0;
5369}
a2fbb9ea 5370
523224a3 5371static int bnx2x_init_hw_port(struct bnx2x *bp)
34f80b04
EG		 5372{
5373 int port = BP_PORT(bp);
94a78b79 5374 int init_stage = port ? PORT1_STAGE : PORT0_STAGE;
1c06328c 5375 u32 low, high;
34f80b04 5376 u32 val;
a2fbb9ea 5377
cdaa7cb8 5378 DP(BNX2X_MSG_MCP, "starting port init port %d\n", port);
34f80b04
EG		 5379
5380 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
a2fbb9ea 5381
94a78b79 5382 bnx2x_init_block(bp, PXP_BLOCK, init_stage);
94a78b79 5383 bnx2x_init_block(bp, PXP2_BLOCK, init_stage);
ca00392c 5384
f2e0899f
DK		 5385 /* Timers bug workaround: disables the pf_master bit in pglue at
5386 * common phase, we need to enable it here before any dmae access are
5387 * attempted. Therefore we manually added the enable-master to the
5388 * port phase (it also happens in the function phase)
5389 */
5390 if (CHIP_IS_E2(bp))
5391 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
5392
ca00392c
EG		 5393 bnx2x_init_block(bp, TCM_BLOCK, init_stage);
5394 bnx2x_init_block(bp, UCM_BLOCK, init_stage);
5395 bnx2x_init_block(bp, CCM_BLOCK, init_stage);
94a78b79 5396 bnx2x_init_block(bp, XCM_BLOCK, init_stage);
a2fbb9ea 5397
523224a3
DK		 5398 /* QM cid (connection) count */
5399 bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET);
a2fbb9ea 5400
523224a3 5401#ifdef BCM_CNIC
94a78b79 5402 bnx2x_init_block(bp, TIMERS_BLOCK, init_stage);
37b091ba
MC		 5403 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20);
5404 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31);
a2fbb9ea 5405#endif
cdaa7cb8 5406
94a78b79 5407 bnx2x_init_block(bp, DQ_BLOCK, init_stage);
1c06328c 5408
f2e0899f
DK		 5409 if (CHIP_MODE_IS_4_PORT(bp))
5410 bnx2x_init_block(bp, QM_4PORT_BLOCK, init_stage);
5411
5412 if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) {
5413 bnx2x_init_block(bp, BRB1_BLOCK, init_stage);
5414 if (CHIP_REV_IS_SLOW(bp) && CHIP_IS_E1(bp)) {
5415 /* no pause for emulation and FPGA */
5416 low = 0;
5417 high = 513;
5418 } else {
5419 if (IS_MF(bp))
5420 low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246);
5421 else if (bp->dev->mtu > 4096) {
5422 if (bp->flags & ONE_PORT_FLAG)
5423 low = 160;
5424 else {
5425 val = bp->dev->mtu;
5426 /* (24*1024 + val*4)/256 */
5427 low = 96 + (val/64) +
5428 ((val % 64) ? 1 : 0);
5429 }
5430 } else
5431 low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160);
5432 high = low + 56; /* 14*1024/256 */
5433 }
5434 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
5435 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
1c06328c 5436 }
1c06328c 5437
f2e0899f
DK		 5438 if (CHIP_MODE_IS_4_PORT(bp)) {
5439 REG_WR(bp, BRB1_REG_PAUSE_0_XOFF_THRESHOLD_0 + port*8, 248);
5440 REG_WR(bp, BRB1_REG_PAUSE_0_XON_THRESHOLD_0 + port*8, 328);
5441 REG_WR(bp, (BP_PORT(bp) ? BRB1_REG_MAC_GUARANTIED_1 :
5442 BRB1_REG_MAC_GUARANTIED_0), 40);
5443 }
1c06328c 5444
94a78b79 5445 bnx2x_init_block(bp, PRS_BLOCK, init_stage);
ca00392c 5446
94a78b79 5447 bnx2x_init_block(bp, TSDM_BLOCK, init_stage);
94a78b79 5448 bnx2x_init_block(bp, CSDM_BLOCK, init_stage);
94a78b79 5449 bnx2x_init_block(bp, USDM_BLOCK, init_stage);
94a78b79 5450 bnx2x_init_block(bp, XSDM_BLOCK, init_stage);
356e2385 5451
94a78b79
VZ		 5452 bnx2x_init_block(bp, TSEM_BLOCK, init_stage);
5453 bnx2x_init_block(bp, USEM_BLOCK, init_stage);
5454 bnx2x_init_block(bp, CSEM_BLOCK, init_stage);
5455 bnx2x_init_block(bp, XSEM_BLOCK, init_stage);
f2e0899f
DK		 5456 if (CHIP_MODE_IS_4_PORT(bp))
5457 bnx2x_init_block(bp, XSEM_4PORT_BLOCK, init_stage);
356e2385 5458
94a78b79 5459 bnx2x_init_block(bp, UPB_BLOCK, init_stage);
94a78b79 5460 bnx2x_init_block(bp, XPB_BLOCK, init_stage);
34f80b04 5461
94a78b79 5462 bnx2x_init_block(bp, PBF_BLOCK, init_stage);
a2fbb9ea 5463
f2e0899f
DK		 5464 if (!CHIP_IS_E2(bp)) {
5465 /* configure PBF to work without PAUSE mtu 9000 */
5466 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
a2fbb9ea 5467
f2e0899f
DK		 5468 /* update threshold */
5469 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
5470 /* update init credit */
5471 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
a2fbb9ea 5472
f2e0899f
DK		 5473 /* probe changes */
5474 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
5475 udelay(50);
5476 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
5477 }
a2fbb9ea 5478
37b091ba
MC		 5479#ifdef BCM_CNIC
5480 bnx2x_init_block(bp, SRCH_BLOCK, init_stage);
a2fbb9ea 5481#endif
94a78b79 5482 bnx2x_init_block(bp, CDU_BLOCK, init_stage);
94a78b79 5483 bnx2x_init_block(bp, CFC_BLOCK, init_stage);
34f80b04
EG		 5484
5485 if (CHIP_IS_E1(bp)) {
5486 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
5487 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
5488 }
94a78b79 5489 bnx2x_init_block(bp, HC_BLOCK, init_stage);
34f80b04 5490
f2e0899f
DK		 5491 bnx2x_init_block(bp, IGU_BLOCK, init_stage);
5492
94a78b79 5493 bnx2x_init_block(bp, MISC_AEU_BLOCK, init_stage);
34f80b04
EG		 5494 /* init aeu_mask_attn_func_0/1:
5495 * - SF mode: bits 3-7 are masked. only bits 0-2 are in use
5496 * - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
5497 * bits 4-7 are used for "per vn group attention" */
e4901dde
VZ		 5498 val = IS_MF(bp) ? 0xF7 : 0x7;
5499 /* Enable DCBX attention for all but E1 */
5500 val |= CHIP_IS_E1(bp) ? 0 : 0x10;
5501 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
34f80b04 5502
94a78b79 5503 bnx2x_init_block(bp, PXPCS_BLOCK, init_stage);
94a78b79 5504 bnx2x_init_block(bp, EMAC0_BLOCK, init_stage);
94a78b79 5505 bnx2x_init_block(bp, EMAC1_BLOCK, init_stage);
94a78b79 5506 bnx2x_init_block(bp, DBU_BLOCK, init_stage);
94a78b79 5507 bnx2x_init_block(bp, DBG_BLOCK, init_stage);
356e2385 5508
94a78b79 5509 bnx2x_init_block(bp, NIG_BLOCK, init_stage);
34f80b04
EG		 5510
5511 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
5512
f2e0899f 5513 if (!CHIP_IS_E1(bp)) {
fb3bff17 5514 /* 0x2 disable mf_ov, 0x1 enable */
34f80b04 5515 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
0793f83f 5516 (IS_MF_SD(bp) ? 0x1 : 0x2));
34f80b04 5517
f2e0899f
DK		 5518 if (CHIP_IS_E2(bp)) {
5519 val = 0;
5520 switch (bp->mf_mode) {
5521 case MULTI_FUNCTION_SD:
5522 val = 1;
5523 break;
5524 case MULTI_FUNCTION_SI:
5525 val = 2;
5526 break;
5527 }
5528
5529 REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE :
5530 NIG_REG_LLH0_CLS_TYPE), val);
5531 }
1c06328c
EG		 5532 {
5533 REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
5534 REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
5535 REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1);
5536 }
34f80b04
EG		 5537 }
5538
94a78b79 5539 bnx2x_init_block(bp, MCP_BLOCK, init_stage);
94a78b79 5540 bnx2x_init_block(bp, DMAE_BLOCK, init_stage);
d90d96ba 5541 if (bnx2x_fan_failure_det_req(bp, bp->common.shmem_base,
a22f0788 5542 bp->common.shmem2_base, port)) {
4d295db0
EG		 5543 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
5544 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
5545 val = REG_RD(bp, reg_addr);
f1410647 5546 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
4d295db0 5547 REG_WR(bp, reg_addr, val);
f1410647 5548 }
c18487ee 5549 bnx2x__link_reset(bp);
a2fbb9ea 5550
34f80b04
EG		 5551 return 0;
5552}
5553
34f80b04
EG		 5554static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr)
5555{
5556 int reg;
5557
f2e0899f 5558 if (CHIP_IS_E1(bp))
34f80b04 5559 reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
f2e0899f
DK		 5560 else
5561 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
34f80b04
EG		 5562
5563 bnx2x_wb_wr(bp, reg, ONCHIP_ADDR1(addr), ONCHIP_ADDR2(addr));
5564}
5565
f2e0899f
DK		 5566static inline void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id)
5567{
5568 bnx2x_igu_clear_sb_gen(bp, idu_sb_id, true /*PF*/);
5569}
5570
5571static inline void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func)
5572{
5573 u32 i, base = FUNC_ILT_BASE(func);
5574 for (i = base; i < base + ILT_PER_FUNC; i++)
5575 bnx2x_ilt_wr(bp, i, 0);
5576}
5577
523224a3 5578static int bnx2x_init_hw_func(struct bnx2x *bp)
34f80b04
EG		 5579{
5580 int port = BP_PORT(bp);
5581 int func = BP_FUNC(bp);
523224a3
DK		 5582 struct bnx2x_ilt *ilt = BP_ILT(bp);
5583 u16 cdu_ilt_start;
8badd27a 5584 u32 addr, val;
f4a66897
VZ		 5585 u32 main_mem_base, main_mem_size, main_mem_prty_clr;
5586 int i, main_mem_width;
34f80b04 5587
cdaa7cb8 5588 DP(BNX2X_MSG_MCP, "starting func init func %d\n", func);
34f80b04 5589
8badd27a 5590 /* set MSI reconfigure capability */
f2e0899f
DK		 5591 if (bp->common.int_block == INT_BLOCK_HC) {
5592 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
5593 val = REG_RD(bp, addr);
5594 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
5595 REG_WR(bp, addr, val);
5596 }
8badd27a 5597
523224a3
DK		 5598 ilt = BP_ILT(bp);
5599 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
37b091ba 5600
523224a3
DK		 5601 for (i = 0; i < L2_ILT_LINES(bp); i++) {
5602 ilt->lines[cdu_ilt_start + i].page =
5603 bp->context.vcxt + (ILT_PAGE_CIDS * i);
5604 ilt->lines[cdu_ilt_start + i].page_mapping =
5605 bp->context.cxt_mapping + (CDU_ILT_PAGE_SZ * i);
5606 /* cdu ilt pages are allocated manually so there's no need to
5607 set the size */
37b091ba 5608 }
523224a3 5609 bnx2x_ilt_init_op(bp, INITOP_SET);
f85582f8 5610
523224a3
DK		 5611#ifdef BCM_CNIC
5612 bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM);
37b091ba 5613
523224a3
DK		 5614 /* T1 hash bits value determines the T1 number of entries */
5615 REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS);
5616#endif
37b091ba 5617
523224a3
DK		 5618#ifndef BCM_CNIC
5619 /* set NIC mode */
5620 REG_WR(bp, PRS_REG_NIC_MODE, 1);
5621#endif /* BCM_CNIC */
37b091ba 5622
f2e0899f
DK		 5623 if (CHIP_IS_E2(bp)) {
5624 u32 pf_conf = IGU_PF_CONF_FUNC_EN;
5625
5626 /* Turn on a single ISR mode in IGU if driver is going to use
5627 * INT#x or MSI
5628 */
5629 if (!(bp->flags & USING_MSIX_FLAG))
5630 pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
5631 /*
5632 * Timers workaround bug: function init part.
5633 * Need to wait 20msec after initializing ILT,
5634 * needed to make sure there are no requests in
5635 * one of the PXP internal queues with "old" ILT addresses
5636 */
5637 msleep(20);
5638 /*
5639 * Master enable - Due to WB DMAE writes performed before this
5640 * register is re-initialized as part of the regular function
5641 * init
5642 */
5643 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
5644 /* Enable the function in IGU */
5645 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf);
5646 }
5647
523224a3 5648 bp->dmae_ready = 1;
34f80b04 5649
523224a3
DK		 5650 bnx2x_init_block(bp, PGLUE_B_BLOCK, FUNC0_STAGE + func);
5651
f2e0899f
DK		 5652 if (CHIP_IS_E2(bp))
5653 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
5654
523224a3
DK		 5655 bnx2x_init_block(bp, MISC_BLOCK, FUNC0_STAGE + func);
5656 bnx2x_init_block(bp, TCM_BLOCK, FUNC0_STAGE + func);
5657 bnx2x_init_block(bp, UCM_BLOCK, FUNC0_STAGE + func);
5658 bnx2x_init_block(bp, CCM_BLOCK, FUNC0_STAGE + func);
5659 bnx2x_init_block(bp, XCM_BLOCK, FUNC0_STAGE + func);
5660 bnx2x_init_block(bp, TSEM_BLOCK, FUNC0_STAGE + func);
5661 bnx2x_init_block(bp, USEM_BLOCK, FUNC0_STAGE + func);
5662 bnx2x_init_block(bp, CSEM_BLOCK, FUNC0_STAGE + func);
5663 bnx2x_init_block(bp, XSEM_BLOCK, FUNC0_STAGE + func);
5664
f2e0899f
DK		 5665 if (CHIP_IS_E2(bp)) {
5666 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_PATH_ID_OFFSET,
5667 BP_PATH(bp));
5668 REG_WR(bp, BAR_CSTRORM_INTMEM + CSTORM_PATH_ID_OFFSET,
5669 BP_PATH(bp));
5670 }
5671
5672 if (CHIP_MODE_IS_4_PORT(bp))
5673 bnx2x_init_block(bp, XSEM_4PORT_BLOCK, FUNC0_STAGE + func);
5674
5675 if (CHIP_IS_E2(bp))
5676 REG_WR(bp, QM_REG_PF_EN, 1);
5677
523224a3 5678 bnx2x_init_block(bp, QM_BLOCK, FUNC0_STAGE + func);
f2e0899f
DK		 5679
5680 if (CHIP_MODE_IS_4_PORT(bp))
5681 bnx2x_init_block(bp, QM_4PORT_BLOCK, FUNC0_STAGE + func);
5682
523224a3
DK		 5683 bnx2x_init_block(bp, TIMERS_BLOCK, FUNC0_STAGE + func);
5684 bnx2x_init_block(bp, DQ_BLOCK, FUNC0_STAGE + func);
5685 bnx2x_init_block(bp, BRB1_BLOCK, FUNC0_STAGE + func);
5686 bnx2x_init_block(bp, PRS_BLOCK, FUNC0_STAGE + func);
5687 bnx2x_init_block(bp, TSDM_BLOCK, FUNC0_STAGE + func);
5688 bnx2x_init_block(bp, CSDM_BLOCK, FUNC0_STAGE + func);
5689 bnx2x_init_block(bp, USDM_BLOCK, FUNC0_STAGE + func);
5690 bnx2x_init_block(bp, XSDM_BLOCK, FUNC0_STAGE + func);
5691 bnx2x_init_block(bp, UPB_BLOCK, FUNC0_STAGE + func);
5692 bnx2x_init_block(bp, XPB_BLOCK, FUNC0_STAGE + func);
5693 bnx2x_init_block(bp, PBF_BLOCK, FUNC0_STAGE + func);
f2e0899f
DK		 5694 if (CHIP_IS_E2(bp))
5695 REG_WR(bp, PBF_REG_DISABLE_PF, 0);
5696
523224a3
DK		 5697 bnx2x_init_block(bp, CDU_BLOCK, FUNC0_STAGE + func);
5698
5699 bnx2x_init_block(bp, CFC_BLOCK, FUNC0_STAGE + func);
34f80b04 5700
f2e0899f
DK		 5701 if (CHIP_IS_E2(bp))
5702 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1);
5703
fb3bff17 5704 if (IS_MF(bp)) {
34f80b04 5705 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
fb3bff17 5706 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->mf_ov);
34f80b04
EG		 5707 }
5708
523224a3
DK		 5709 bnx2x_init_block(bp, MISC_AEU_BLOCK, FUNC0_STAGE + func);
5710
34f80b04 5711 /* HC init per function */
f2e0899f
DK		 5712 if (bp->common.int_block == INT_BLOCK_HC) {
5713 if (CHIP_IS_E1H(bp)) {
5714 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
5715
5716 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
5717 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
5718 }
5719 bnx2x_init_block(bp, HC_BLOCK, FUNC0_STAGE + func);
5720
5721 } else {
5722 int num_segs, sb_idx, prod_offset;
5723
34f80b04
EG		 5724 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
5725
f2e0899f
DK		 5726 if (CHIP_IS_E2(bp)) {
5727 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
5728 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
5729 }
5730
5731 bnx2x_init_block(bp, IGU_BLOCK, FUNC0_STAGE + func);
5732
5733 if (CHIP_IS_E2(bp)) {
5734 int dsb_idx = 0;
5735 /**
5736 * Producer memory:
5737 * E2 mode: address 0-135 match to the mapping memory;
5738 * 136 - PF0 default prod; 137 - PF1 default prod;
5739 * 138 - PF2 default prod; 139 - PF3 default prod;
5740 * 140 - PF0 attn prod; 141 - PF1 attn prod;
5741 * 142 - PF2 attn prod; 143 - PF3 attn prod;
5742 * 144-147 reserved.
5743 *
5744 * E1.5 mode - In backward compatible mode;
5745 * for non default SB; each even line in the memory
5746 * holds the U producer and each odd line hold
5747 * the C producer. The first 128 producers are for
5748 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
5749 * producers are for the DSB for each PF.
5750 * Each PF has five segments: (the order inside each
5751 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
5752 * 132-135 C prods; 136-139 X prods; 140-143 T prods;
5753 * 144-147 attn prods;
5754 */
5755 /* non-default-status-blocks */
5756 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
5757 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
5758 for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) {
5759 prod_offset = (bp->igu_base_sb + sb_idx) *
5760 num_segs;
5761
5762 for (i = 0; i < num_segs; i++) {
5763 addr = IGU_REG_PROD_CONS_MEMORY +
5764 (prod_offset + i) * 4;
5765 REG_WR(bp, addr, 0);
5766 }
5767 /* send consumer update with value 0 */
5768 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx,
5769 USTORM_ID, 0, IGU_INT_NOP, 1);
5770 bnx2x_igu_clear_sb(bp,
5771 bp->igu_base_sb + sb_idx);
5772 }
5773
5774 /* default-status-blocks */
5775 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
5776 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
5777
5778 if (CHIP_MODE_IS_4_PORT(bp))
5779 dsb_idx = BP_FUNC(bp);
5780 else
5781 dsb_idx = BP_E1HVN(bp);
5782
5783 prod_offset = (CHIP_INT_MODE_IS_BC(bp) ?
5784 IGU_BC_BASE_DSB_PROD + dsb_idx :
5785 IGU_NORM_BASE_DSB_PROD + dsb_idx);
5786
5787 for (i = 0; i < (num_segs * E1HVN_MAX);
5788 i += E1HVN_MAX) {
5789 addr = IGU_REG_PROD_CONS_MEMORY +
5790 (prod_offset + i)*4;
5791 REG_WR(bp, addr, 0);
5792 }
5793 /* send consumer update with 0 */
5794 if (CHIP_INT_MODE_IS_BC(bp)) {
5795 bnx2x_ack_sb(bp, bp->igu_dsb_id,
5796 USTORM_ID, 0, IGU_INT_NOP, 1);
5797 bnx2x_ack_sb(bp, bp->igu_dsb_id,
5798 CSTORM_ID, 0, IGU_INT_NOP, 1);
5799 bnx2x_ack_sb(bp, bp->igu_dsb_id,
5800 XSTORM_ID, 0, IGU_INT_NOP, 1);
5801 bnx2x_ack_sb(bp, bp->igu_dsb_id,
5802 TSTORM_ID, 0, IGU_INT_NOP, 1);
5803 bnx2x_ack_sb(bp, bp->igu_dsb_id,
5804 ATTENTION_ID, 0, IGU_INT_NOP, 1);
5805 } else {
5806 bnx2x_ack_sb(bp, bp->igu_dsb_id,
5807 USTORM_ID, 0, IGU_INT_NOP, 1);
5808 bnx2x_ack_sb(bp, bp->igu_dsb_id,
5809 ATTENTION_ID, 0, IGU_INT_NOP, 1);
5810 }
5811 bnx2x_igu_clear_sb(bp, bp->igu_dsb_id);
5812
5813 /* !!! these should become driver const once
5814 rf-tool supports split-68 const */
5815 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
5816 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
5817 REG_WR(bp, IGU_REG_SB_MASK_LSB, 0);
5818 REG_WR(bp, IGU_REG_SB_MASK_MSB, 0);
5819 REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0);
5820 REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0);
5821 }
34f80b04 5822 }
34f80b04 5823
c14423fe 5824 /* Reset PCIE errors for debug */
a2fbb9ea
ET		 5825 REG_WR(bp, 0x2114, 0xffffffff);
5826 REG_WR(bp, 0x2120, 0xffffffff);
523224a3
DK		 5827
5828 bnx2x_init_block(bp, EMAC0_BLOCK, FUNC0_STAGE + func);
5829 bnx2x_init_block(bp, EMAC1_BLOCK, FUNC0_STAGE + func);
5830 bnx2x_init_block(bp, DBU_BLOCK, FUNC0_STAGE + func);
5831 bnx2x_init_block(bp, DBG_BLOCK, FUNC0_STAGE + func);
5832 bnx2x_init_block(bp, MCP_BLOCK, FUNC0_STAGE + func);
5833 bnx2x_init_block(bp, DMAE_BLOCK, FUNC0_STAGE + func);
5834
f4a66897
VZ		 5835 if (CHIP_IS_E1x(bp)) {
5836 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/
5837 main_mem_base = HC_REG_MAIN_MEMORY +
5838 BP_PORT(bp) * (main_mem_size * 4);
5839 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
5840 main_mem_width = 8;
5841
5842 val = REG_RD(bp, main_mem_prty_clr);
5843 if (val)
5844 DP(BNX2X_MSG_MCP, "Hmmm... Parity errors in HC "
5845 "block during "
5846 "function init (0x%x)!\n", val);
5847
5848 /* Clear "false" parity errors in MSI-X table */
5849 for (i = main_mem_base;
5850 i < main_mem_base + main_mem_size * 4;
5851 i += main_mem_width) {
5852 bnx2x_read_dmae(bp, i, main_mem_width / 4);
5853 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data),
5854 i, main_mem_width / 4);
5855 }
5856 /* Clear HC parity attention */
5857 REG_RD(bp, main_mem_prty_clr);
5858 }
5859
b7737c9b 5860 bnx2x_phy_probe(&bp->link_params);
f85582f8 5861
34f80b04
EG		 5862 return 0;
5863}
5864
9f6c9258 5865int bnx2x_init_hw(struct bnx2x *bp, u32 load_code)
34f80b04 5866{
523224a3 5867 int rc = 0;
a2fbb9ea 5868
34f80b04 5869 DP(BNX2X_MSG_MCP, "function %d load_code %x\n",
f2e0899f 5870 BP_ABS_FUNC(bp), load_code);
a2fbb9ea 5871
34f80b04 5872 bp->dmae_ready = 0;
6e30dd4e 5873 spin_lock_init(&bp->dmae_lock);
a2fbb9ea 5874
34f80b04
EG		 5875 switch (load_code) {
5876 case FW_MSG_CODE_DRV_LOAD_COMMON:
f2e0899f 5877 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
523224a3 5878 rc = bnx2x_init_hw_common(bp, load_code);
34f80b04
EG		 5879 if (rc)
5880 goto init_hw_err;
5881 /* no break */
5882
5883 case FW_MSG_CODE_DRV_LOAD_PORT:
523224a3 5884 rc = bnx2x_init_hw_port(bp);
34f80b04
EG		 5885 if (rc)
5886 goto init_hw_err;
5887 /* no break */
5888
5889 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
523224a3 5890 rc = bnx2x_init_hw_func(bp);
34f80b04
EG		 5891 if (rc)
5892 goto init_hw_err;
5893 break;
5894
5895 default:
5896 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
5897 break;
5898 }
5899
5900 if (!BP_NOMCP(bp)) {
f2e0899f 5901 int mb_idx = BP_FW_MB_IDX(bp);
a2fbb9ea
ET		 5902
5903 bp->fw_drv_pulse_wr_seq =
f2e0899f 5904 (SHMEM_RD(bp, func_mb[mb_idx].drv_pulse_mb) &
a2fbb9ea 5905 DRV_PULSE_SEQ_MASK);
6fe49bb9
EG		 5906 DP(BNX2X_MSG_MCP, "drv_pulse 0x%x\n", bp->fw_drv_pulse_wr_seq);
5907 }
a2fbb9ea 5908
34f80b04
EG		 5909init_hw_err:
5910 bnx2x_gunzip_end(bp);
5911
5912 return rc;
a2fbb9ea
ET		 5913}
5914
9f6c9258 5915void bnx2x_free_mem(struct bnx2x *bp)
a2fbb9ea 5916{
b3b83c3f 5917 bnx2x_gunzip_end(bp);
a2fbb9ea
ET		 5918
5919 /* fastpath */
b3b83c3f 5920 bnx2x_free_fp_mem(bp);
a2fbb9ea
ET		 5921 /* end of fastpath */
5922
5923 BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping,
523224a3 5924 sizeof(struct host_sp_status_block));
a2fbb9ea
ET		 5925
5926 BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping,
34f80b04 5927 sizeof(struct bnx2x_slowpath));
a2fbb9ea 5928
523224a3
DK		 5929 BNX2X_PCI_FREE(bp->context.vcxt, bp->context.cxt_mapping,
5930 bp->context.size);
5931
5932 bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE);
5933
5934 BNX2X_FREE(bp->ilt->lines);
f85582f8 5935
37b091ba 5936#ifdef BCM_CNIC
f2e0899f
DK		 5937 if (CHIP_IS_E2(bp))
5938 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping,
5939 sizeof(struct host_hc_status_block_e2));
5940 else
5941 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping,
5942 sizeof(struct host_hc_status_block_e1x));
f85582f8 5943
523224a3 5944 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
a2fbb9ea 5945#endif
f85582f8 5946
7a9b2557 5947 BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE);
a2fbb9ea 5948
523224a3
DK		 5949 BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping,
5950 BCM_PAGE_SIZE * NUM_EQ_PAGES);
5951
ab532cf3 5952 BNX2X_FREE(bp->rx_indir_table);
a2fbb9ea
ET		 5953}
5954
f2e0899f 5955
9f6c9258 5956int bnx2x_alloc_mem(struct bnx2x *bp)
a2fbb9ea 5957{
b3b83c3f
DK		 5958 if (bnx2x_gunzip_init(bp))
5959 return -ENOMEM;
8badd27a 5960
523224a3 5961#ifdef BCM_CNIC
f2e0899f
DK		 5962 if (CHIP_IS_E2(bp))
5963 BNX2X_PCI_ALLOC(bp->cnic_sb.e2_sb, &bp->cnic_sb_mapping,
5964 sizeof(struct host_hc_status_block_e2));
5965 else
5966 BNX2X_PCI_ALLOC(bp->cnic_sb.e1x_sb, &bp->cnic_sb_mapping,
5967 sizeof(struct host_hc_status_block_e1x));
8badd27a 5968
523224a3
DK		 5969 /* allocate searcher T2 table */
5970 BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ);
5971#endif
a2fbb9ea 5972
8badd27a 5973
523224a3
DK		 5974 BNX2X_PCI_ALLOC(bp->def_status_blk, &bp->def_status_blk_mapping,
5975 sizeof(struct host_sp_status_block));
a2fbb9ea 5976
523224a3
DK		 5977 BNX2X_PCI_ALLOC(bp->slowpath, &bp->slowpath_mapping,
5978 sizeof(struct bnx2x_slowpath));
a2fbb9ea 5979
523224a3 5980 bp->context.size = sizeof(union cdu_context) * bp->l2_cid_count;
f85582f8 5981
523224a3
DK		 5982 BNX2X_PCI_ALLOC(bp->context.vcxt, &bp->context.cxt_mapping,
5983 bp->context.size);
65abd74d 5984
523224a3 5985 BNX2X_ALLOC(bp->ilt->lines, sizeof(struct ilt_line) * ILT_MAX_LINES);
65abd74d 5986
523224a3
DK		 5987 if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC))
5988 goto alloc_mem_err;
65abd74d 5989
9f6c9258
DK		 5990 /* Slow path ring */
5991 BNX2X_PCI_ALLOC(bp->spq, &bp->spq_mapping, BCM_PAGE_SIZE);
65abd74d 5992
523224a3
DK		 5993 /* EQ */
5994 BNX2X_PCI_ALLOC(bp->eq_ring, &bp->eq_mapping,
5995 BCM_PAGE_SIZE * NUM_EQ_PAGES);
ab532cf3
TH		 5996
5997 BNX2X_ALLOC(bp->rx_indir_table, sizeof(bp->rx_indir_table[0]) *
5998 TSTORM_INDIRECTION_TABLE_SIZE);
b3b83c3f
DK		 5999
6000 /* fastpath */
6001 /* need to be done at the end, since it's self adjusting to amount
6002 * of memory available for RSS queues
6003 */
6004 if (bnx2x_alloc_fp_mem(bp))
6005 goto alloc_mem_err;
9f6c9258 6006 return 0;
e1510706 6007
9f6c9258
DK		 6008alloc_mem_err:
6009 bnx2x_free_mem(bp);
6010 return -ENOMEM;
65abd74d
YG		 6011}
6012
a2fbb9ea
ET		 6013/*
6014 * Init service functions
6015 */
8d96286a 6016static int bnx2x_wait_ramrod(struct bnx2x *bp, int state, int idx,
6017 int *state_p, int flags);
6018
523224a3 6019int bnx2x_func_start(struct bnx2x *bp)
a2fbb9ea 6020{
523224a3 6021 bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_FUNCTION_START, 0, 0, 0, 1);
a2fbb9ea 6022
523224a3
DK		 6023 /* Wait for completion */
6024 return bnx2x_wait_ramrod(bp, BNX2X_STATE_FUNC_STARTED, 0, &(bp->state),
6025 WAIT_RAMROD_COMMON);
6026}
a2fbb9ea 6027
8d96286a 6028static int bnx2x_func_stop(struct bnx2x *bp)
523224a3
DK		 6029{
6030 bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_FUNCTION_STOP, 0, 0, 0, 1);
a2fbb9ea 6031
523224a3
DK		 6032 /* Wait for completion */
6033 return bnx2x_wait_ramrod(bp, BNX2X_STATE_CLOSING_WAIT4_UNLOAD,
6034 0, &(bp->state), WAIT_RAMROD_COMMON);
a2fbb9ea
ET		 6035}
6036
e665bfda 6037/**
e8920674 6038 * bnx2x_set_mac_addr_gen - set a MAC in a CAM for a few L2 Clients for E1x chips
e665bfda 6039 *
e8920674
DK		 6040 * @bp: driver handle
6041 * @set: set or clear an entry (1 or 0)
6042 * @mac: pointer to a buffer containing a MAC
6043 * @cl_bit_vec: bit vector of clients to register a MAC for
6044 * @cam_offset: offset in a CAM to use
6045 * @is_bcast: is the set MAC a broadcast address (for E1 only)
e665bfda 6046 */
215faf9c 6047static void bnx2x_set_mac_addr_gen(struct bnx2x *bp, int set, const u8 *mac,
f85582f8
DK		 6048 u32 cl_bit_vec, u8 cam_offset,
6049 u8 is_bcast)
34f80b04 6050{
523224a3
DK		 6051 struct mac_configuration_cmd *config =
6052 (struct mac_configuration_cmd *)bnx2x_sp(bp, mac_config);
6053 int ramrod_flags = WAIT_RAMROD_COMMON;
6054
6055 bp->set_mac_pending = 1;
523224a3 6056
8d9c5f34 6057 config->hdr.length = 1;
e665bfda
MC		 6058 config->hdr.offset = cam_offset;
6059 config->hdr.client_id = 0xff;
6e30dd4e
VZ		 6060 /* Mark the single MAC configuration ramrod as opposed to a
6061 * UC/MC list configuration).
6062 */
6063 config->hdr.echo = 1;
34f80b04
EG		 6064
6065 /* primary MAC */
6066 config->config_table[0].msb_mac_addr =
e665bfda 6067 swab16(*(u16 *)&mac[0]);
34f80b04 6068 config->config_table[0].middle_mac_addr =
e665bfda 6069 swab16(*(u16 *)&mac[2]);
34f80b04 6070 config->config_table[0].lsb_mac_addr =
e665bfda 6071 swab16(*(u16 *)&mac[4]);
ca00392c 6072 config->config_table[0].clients_bit_vector =
e665bfda 6073 cpu_to_le32(cl_bit_vec);
34f80b04 6074 config->config_table[0].vlan_id = 0;
523224a3 6075 config->config_table[0].pf_id = BP_FUNC(bp);
3101c2bc 6076 if (set)
523224a3
DK		 6077 SET_FLAG(config->config_table[0].flags,
6078 MAC_CONFIGURATION_ENTRY_ACTION_TYPE,
6079 T_ETH_MAC_COMMAND_SET);
3101c2bc 6080 else
523224a3
DK		 6081 SET_FLAG(config->config_table[0].flags,
6082 MAC_CONFIGURATION_ENTRY_ACTION_TYPE,
6083 T_ETH_MAC_COMMAND_INVALIDATE);
34f80b04 6084
523224a3
DK		 6085 if (is_bcast)
6086 SET_FLAG(config->config_table[0].flags,
6087 MAC_CONFIGURATION_ENTRY_BROADCAST, 1);
6088
6089 DP(NETIF_MSG_IFUP, "%s MAC (%04x:%04x:%04x) PF_ID %d CLID mask %d\n",
3101c2bc 6090 (set ? "setting" : "clearing"),
34f80b04
EG		 6091 config->config_table[0].msb_mac_addr,
6092 config->config_table[0].middle_mac_addr,
523224a3 6093 config->config_table[0].lsb_mac_addr, BP_FUNC(bp), cl_bit_vec);
34f80b04 6094
6e30dd4e
VZ		 6095 mb();
6096
523224a3 6097 bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_SET_MAC, 0,
34f80b04 6098 U64_HI(bnx2x_sp_mapping(bp, mac_config)),
523224a3
DK		 6099 U64_LO(bnx2x_sp_mapping(bp, mac_config)), 1);
6100
6101 /* Wait for a completion */
6102 bnx2x_wait_ramrod(bp, 0, 0, &bp->set_mac_pending, ramrod_flags);
34f80b04
EG		 6103}
6104
8d96286a 6105static int bnx2x_wait_ramrod(struct bnx2x *bp, int state, int idx,
6106 int *state_p, int flags)
a2fbb9ea
ET		 6107{
6108 /* can take a while if any port is running */
8b3a0f0b 6109 int cnt = 5000;
523224a3
DK		 6110 u8 poll = flags & WAIT_RAMROD_POLL;
6111 u8 common = flags & WAIT_RAMROD_COMMON;
a2fbb9ea 6112
c14423fe
ET		 6113 DP(NETIF_MSG_IFUP, "%s for state to become %x on IDX [%d]\n",
6114 poll ? "polling" : "waiting", state, idx);
a2fbb9ea
ET		 6115
6116 might_sleep();
34f80b04 6117 while (cnt--) {
a2fbb9ea 6118 if (poll) {
523224a3
DK		 6119 if (common)
6120 bnx2x_eq_int(bp);
6121 else {
6122 bnx2x_rx_int(bp->fp, 10);
6123 /* if index is different from 0
6124 * the reply for some commands will
6125 * be on the non default queue
6126 */
6127 if (idx)
6128 bnx2x_rx_int(&bp->fp[idx], 10);
6129 }
a2fbb9ea 6130 }
a2fbb9ea 6131
3101c2bc 6132 mb(); /* state is changed by bnx2x_sp_event() */
8b3a0f0b
EG		 6133 if (*state_p == state) {
6134#ifdef BNX2X_STOP_ON_ERROR
6135 DP(NETIF_MSG_IFUP, "exit (cnt %d)\n", 5000 - cnt);
6136#endif
a2fbb9ea 6137 return 0;
8b3a0f0b 6138 }
a2fbb9ea 6139
a2fbb9ea 6140 msleep(1);
e3553b29
EG		 6141
6142 if (bp->panic)
6143 return -EIO;
a2fbb9ea
ET		 6144 }
6145
a2fbb9ea 6146 /* timeout! */
49d66772
ET		 6147 BNX2X_ERR("timeout %s for state %x on IDX [%d]\n",
6148 poll ? "polling" : "waiting", state, idx);
34f80b04
EG		 6149#ifdef BNX2X_STOP_ON_ERROR
6150 bnx2x_panic();
6151#endif
a2fbb9ea 6152
49d66772 6153 return -EBUSY;
a2fbb9ea
ET		 6154}
6155
8d96286a 6156static u8 bnx2x_e1h_cam_offset(struct bnx2x *bp, u8 rel_offset)
e665bfda 6157{
f2e0899f
DK		 6158 if (CHIP_IS_E1H(bp))
6159 return E1H_FUNC_MAX * rel_offset + BP_FUNC(bp);
6160 else if (CHIP_MODE_IS_4_PORT(bp))
6e30dd4e 6161 return E2_FUNC_MAX * rel_offset + BP_FUNC(bp);
f2e0899f 6162 else
6e30dd4e 6163 return E2_FUNC_MAX * rel_offset + BP_VN(bp);
523224a3
DK		 6164}
6165
0793f83f
DK		 6166/**
6167 * LLH CAM line allocations: currently only iSCSI and ETH macs are
6168 * relevant. In addition, current implementation is tuned for a
6169 * single ETH MAC.
0793f83f
DK		 6170 */
6171enum {
6172 LLH_CAM_ISCSI_ETH_LINE = 0,
6173 LLH_CAM_ETH_LINE,
6174 LLH_CAM_MAX_PF_LINE = NIG_REG_LLH1_FUNC_MEM_SIZE
6175};
6176
6177static void bnx2x_set_mac_in_nig(struct bnx2x *bp,
6178 int set,
6179 unsigned char *dev_addr,
6180 int index)
6181{
6182 u32 wb_data[2];
6183 u32 mem_offset, ena_offset, mem_index;
6184 /**
6185 * indexes mapping:
6186 * 0..7 - goes to MEM
6187 * 8..15 - goes to MEM2
6188 */
6189
6190 if (!IS_MF_SI(bp) || index > LLH_CAM_MAX_PF_LINE)
6191 return;
6192
6193 /* calculate memory start offset according to the mapping
6194 * and index in the memory */
6195 if (index < NIG_LLH_FUNC_MEM_MAX_OFFSET) {
6196 mem_offset = BP_PORT(bp) ? NIG_REG_LLH1_FUNC_MEM :
6197 NIG_REG_LLH0_FUNC_MEM;
6198 ena_offset = BP_PORT(bp) ? NIG_REG_LLH1_FUNC_MEM_ENABLE :
6199 NIG_REG_LLH0_FUNC_MEM_ENABLE;
6200 mem_index = index;
6201 } else {
6202 mem_offset = BP_PORT(bp) ? NIG_REG_P1_LLH_FUNC_MEM2 :
6203 NIG_REG_P0_LLH_FUNC_MEM2;
6204 ena_offset = BP_PORT(bp) ? NIG_REG_P1_LLH_FUNC_MEM2_ENABLE :
6205 NIG_REG_P0_LLH_FUNC_MEM2_ENABLE;
6206 mem_index = index - NIG_LLH_FUNC_MEM_MAX_OFFSET;
6207 }
6208
6209 if (set) {
6210 /* LLH_FUNC_MEM is a u64 WB register */
6211 mem_offset += 8*mem_index;
6212
6213 wb_data[0] = ((dev_addr[2] << 24) | (dev_addr[3] << 16) |
6214 (dev_addr[4] << 8) | dev_addr[5]);
6215 wb_data[1] = ((dev_addr[0] << 8) | dev_addr[1]);
6216
6217 REG_WR_DMAE(bp, mem_offset, wb_data, 2);
6218 }
6219
6220 /* enable/disable the entry */
6221 REG_WR(bp, ena_offset + 4*mem_index, set);
6222
6223}
6224
523224a3
DK		 6225void bnx2x_set_eth_mac(struct bnx2x *bp, int set)
6226{
6227 u8 cam_offset = (CHIP_IS_E1(bp) ? (BP_PORT(bp) ? 32 : 0) :
6228 bnx2x_e1h_cam_offset(bp, CAM_ETH_LINE));
e665bfda 6229
523224a3
DK		 6230 /* networking MAC */
6231 bnx2x_set_mac_addr_gen(bp, set, bp->dev->dev_addr,
6232 (1 << bp->fp->cl_id), cam_offset , 0);
e665bfda 6233
0793f83f
DK		 6234 bnx2x_set_mac_in_nig(bp, set, bp->dev->dev_addr, LLH_CAM_ETH_LINE);
6235
523224a3
DK		 6236 if (CHIP_IS_E1(bp)) {
6237 /* broadcast MAC */
215faf9c
JP		 6238 static const u8 bcast[ETH_ALEN] = {
6239 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
6240 };
523224a3
DK		 6241 bnx2x_set_mac_addr_gen(bp, set, bcast, 0, cam_offset + 1, 1);
6242 }
e665bfda 6243}
6e30dd4e
VZ		 6244
6245static inline u8 bnx2x_e1_cam_mc_offset(struct bnx2x *bp)
6246{
6247 return CHIP_REV_IS_SLOW(bp) ?
6248 (BNX2X_MAX_EMUL_MULTI * (1 + BP_PORT(bp))) :
6249 (BNX2X_MAX_MULTICAST * (1 + BP_PORT(bp)));
6250}
6251
6252/* set mc list, do not wait as wait implies sleep and
6253 * set_rx_mode can be invoked from non-sleepable context.
6254 *
6255 * Instead we use the same ramrod data buffer each time we need
6256 * to configure a list of addresses, and use the fact that the
6257 * list of MACs is changed in an incremental way and that the
6258 * function is called under the netif_addr_lock. A temporary
6259 * inconsistent CAM configuration (possible in case of a very fast
6260 * sequence of add/del/add on the host side) will shortly be
6261 * restored by the handler of the last ramrod.
6262 */
6263static int bnx2x_set_e1_mc_list(struct bnx2x *bp)
523224a3
DK		 6264{
6265 int i = 0, old;
6266 struct net_device *dev = bp->dev;
6e30dd4e 6267 u8 offset = bnx2x_e1_cam_mc_offset(bp);
523224a3
DK		 6268 struct netdev_hw_addr *ha;
6269 struct mac_configuration_cmd *config_cmd = bnx2x_sp(bp, mcast_config);
6270 dma_addr_t config_cmd_map = bnx2x_sp_mapping(bp, mcast_config);
6271
6e30dd4e
VZ		 6272 if (netdev_mc_count(dev) > BNX2X_MAX_MULTICAST)
6273 return -EINVAL;
6274
523224a3
DK		 6275 netdev_for_each_mc_addr(ha, dev) {
6276 /* copy mac */
6277 config_cmd->config_table[i].msb_mac_addr =
6278 swab16(*(u16 *)&bnx2x_mc_addr(ha)[0]);
6279 config_cmd->config_table[i].middle_mac_addr =
6280 swab16(*(u16 *)&bnx2x_mc_addr(ha)[2]);
6281 config_cmd->config_table[i].lsb_mac_addr =
6282 swab16(*(u16 *)&bnx2x_mc_addr(ha)[4]);
e665bfda 6283
523224a3
DK		 6284 config_cmd->config_table[i].vlan_id = 0;
6285 config_cmd->config_table[i].pf_id = BP_FUNC(bp);
6286 config_cmd->config_table[i].clients_bit_vector =
6287 cpu_to_le32(1 << BP_L_ID(bp));
6288
6289 SET_FLAG(config_cmd->config_table[i].flags,
6290 MAC_CONFIGURATION_ENTRY_ACTION_TYPE,
6291 T_ETH_MAC_COMMAND_SET);
6292
6293 DP(NETIF_MSG_IFUP,
6294 "setting MCAST[%d] (%04x:%04x:%04x)\n", i,
6295 config_cmd->config_table[i].msb_mac_addr,
6296 config_cmd->config_table[i].middle_mac_addr,
6297 config_cmd->config_table[i].lsb_mac_addr);
6298 i++;
6299 }
6300 old = config_cmd->hdr.length;
6301 if (old > i) {
6302 for (; i < old; i++) {
6303 if (CAM_IS_INVALID(config_cmd->
6304 config_table[i])) {
6305 /* already invalidated */
6306 break;
6307 }
6308 /* invalidate */
6309 SET_FLAG(config_cmd->config_table[i].flags,
6310 MAC_CONFIGURATION_ENTRY_ACTION_TYPE,
6311 T_ETH_MAC_COMMAND_INVALIDATE);
6312 }
6313 }
6314
6e30dd4e
VZ		 6315 wmb();
6316
523224a3
DK		 6317 config_cmd->hdr.length = i;
6318 config_cmd->hdr.offset = offset;
6319 config_cmd->hdr.client_id = 0xff;
6e30dd4e
VZ		 6320 /* Mark that this ramrod doesn't use bp->set_mac_pending for
6321 * synchronization.
6322 */
6323 config_cmd->hdr.echo = 0;
523224a3 6324
6e30dd4e 6325 mb();
523224a3 6326
6e30dd4e 6327 return bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_SET_MAC, 0,
523224a3
DK		 6328 U64_HI(config_cmd_map), U64_LO(config_cmd_map), 1);
6329}
6e30dd4e
VZ		 6330
6331void bnx2x_invalidate_e1_mc_list(struct bnx2x *bp)
e665bfda 6332{
523224a3
DK		 6333 int i;
6334 struct mac_configuration_cmd *config_cmd = bnx2x_sp(bp, mcast_config);
6335 dma_addr_t config_cmd_map = bnx2x_sp_mapping(bp, mcast_config);
6336 int ramrod_flags = WAIT_RAMROD_COMMON;
6e30dd4e 6337 u8 offset = bnx2x_e1_cam_mc_offset(bp);
523224a3 6338
6e30dd4e 6339 for (i = 0; i < BNX2X_MAX_MULTICAST; i++)
523224a3
DK		 6340 SET_FLAG(config_cmd->config_table[i].flags,
6341 MAC_CONFIGURATION_ENTRY_ACTION_TYPE,
6342 T_ETH_MAC_COMMAND_INVALIDATE);
6343
6e30dd4e
VZ		 6344 wmb();
6345
6346 config_cmd->hdr.length = BNX2X_MAX_MULTICAST;
6347 config_cmd->hdr.offset = offset;
6348 config_cmd->hdr.client_id = 0xff;
6349 /* We'll wait for a completion this time... */
6350 config_cmd->hdr.echo = 1;
6351
6352 bp->set_mac_pending = 1;
6353
6354 mb();
6355
523224a3
DK		 6356 bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_SET_MAC, 0,
6357 U64_HI(config_cmd_map), U64_LO(config_cmd_map), 1);
e665bfda
MC		 6358
6359 /* Wait for a completion */
523224a3
DK		 6360 bnx2x_wait_ramrod(bp, 0, 0, &bp->set_mac_pending,
6361 ramrod_flags);
6362
e665bfda
MC		 6363}
6364
6e30dd4e
VZ		 6365/* Accept one or more multicasts */
6366static int bnx2x_set_e1h_mc_list(struct bnx2x *bp)
6367{
6368 struct net_device *dev = bp->dev;
6369 struct netdev_hw_addr *ha;
6370 u32 mc_filter[MC_HASH_SIZE];
6371 u32 crc, bit, regidx;
6372 int i;
6373
6374 memset(mc_filter, 0, 4 * MC_HASH_SIZE);
6375
6376 netdev_for_each_mc_addr(ha, dev) {
6377 DP(NETIF_MSG_IFUP, "Adding mcast MAC: %pM\n",
6378 bnx2x_mc_addr(ha));
6379
6380 crc = crc32c_le(0, bnx2x_mc_addr(ha),
6381 ETH_ALEN);
6382 bit = (crc >> 24) & 0xff;
6383 regidx = bit >> 5;
6384 bit &= 0x1f;
6385 mc_filter[regidx] |= (1 << bit);
6386 }
6387
6388 for (i = 0; i < MC_HASH_SIZE; i++)
6389 REG_WR(bp, MC_HASH_OFFSET(bp, i),
6390 mc_filter[i]);
6391
6392 return 0;
6393}
6394
6395void bnx2x_invalidate_e1h_mc_list(struct bnx2x *bp)
6396{
6397 int i;
6398
6399 for (i = 0; i < MC_HASH_SIZE; i++)
6400 REG_WR(bp, MC_HASH_OFFSET(bp, i), 0);
6401}
6402
993ac7b5
MC		 6403#ifdef BCM_CNIC
6404/**
e8920674 6405 * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s).
993ac7b5 6406 *
e8920674
DK		 6407 * @bp: driver handle
6408 * @set: set or clear the CAM entry
993ac7b5 6409 *
e8920674
DK		 6410 * This function will wait until the ramdord completion returns.
6411 * Return 0 if success, -ENODEV if ramrod doesn't return.
993ac7b5 6412 */
8d96286a 6413static int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp, int set)
993ac7b5 6414{
523224a3
DK		 6415 u8 cam_offset = (CHIP_IS_E1(bp) ? ((BP_PORT(bp) ? 32 : 0) + 2) :
6416 bnx2x_e1h_cam_offset(bp, CAM_ISCSI_ETH_LINE));
ec6ba945
VZ		 6417 u32 iscsi_l2_cl_id = BNX2X_ISCSI_ETH_CL_ID +
6418 BP_E1HVN(bp) * NONE_ETH_CONTEXT_USE;
523224a3 6419 u32 cl_bit_vec = (1 << iscsi_l2_cl_id);
2ba45142 6420 u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac;
993ac7b5
MC		 6421
6422 /* Send a SET_MAC ramrod */
2ba45142 6423 bnx2x_set_mac_addr_gen(bp, set, iscsi_mac, cl_bit_vec,
523224a3 6424 cam_offset, 0);
0793f83f 6425
2ba45142 6426 bnx2x_set_mac_in_nig(bp, set, iscsi_mac, LLH_CAM_ISCSI_ETH_LINE);
ec6ba945
VZ		 6427
6428 return 0;
6429}
6430
6431/**
e8920674 6432 * bnx2x_set_fip_eth_mac_addr - set FCoE L2 MAC(s)
ec6ba945 6433 *
e8920674
DK		 6434 * @bp: driver handle
6435 * @set: set or clear the CAM entry
ec6ba945 6436 *
e8920674
DK		 6437 * This function will wait until the ramrod completion returns.
6438 * Returns 0 if success, -ENODEV if ramrod doesn't return.
ec6ba945
VZ		 6439 */
6440int bnx2x_set_fip_eth_mac_addr(struct bnx2x *bp, int set)
6441{
6442 u32 cl_bit_vec = (1 << bnx2x_fcoe(bp, cl_id));
6443 /**
6444 * CAM allocation for E1H
6445 * eth unicasts: by func number
6446 * iscsi: by func number
6447 * fip unicast: by func number
6448 * fip multicast: by func number
6449 */
6450 bnx2x_set_mac_addr_gen(bp, set, bp->fip_mac,
6451 cl_bit_vec, bnx2x_e1h_cam_offset(bp, CAM_FIP_ETH_LINE), 0);
6452
6453 return 0;
6454}
6455
6456int bnx2x_set_all_enode_macs(struct bnx2x *bp, int set)
6457{
6458 u32 cl_bit_vec = (1 << bnx2x_fcoe(bp, cl_id));
6459
6460 /**
6461 * CAM allocation for E1H
6462 * eth unicasts: by func number
6463 * iscsi: by func number
6464 * fip unicast: by func number
6465 * fip multicast: by func number
6466 */
6467 bnx2x_set_mac_addr_gen(bp, set, ALL_ENODE_MACS, cl_bit_vec,
6468 bnx2x_e1h_cam_offset(bp, CAM_FIP_MCAST_LINE), 0);
6469
993ac7b5
MC		 6470 return 0;
6471}
6472#endif
6473
523224a3
DK		 6474static void bnx2x_fill_cl_init_data(struct bnx2x *bp,
6475 struct bnx2x_client_init_params *params,
6476 u8 activate,
6477 struct client_init_ramrod_data *data)
6478{
6479 /* Clear the buffer */
6480 memset(data, 0, sizeof(*data));
6481
6482 /* general */
6483 data->general.client_id = params->rxq_params.cl_id;
6484 data->general.statistics_counter_id = params->rxq_params.stat_id;
6485 data->general.statistics_en_flg =
6486 (params->rxq_params.flags & QUEUE_FLG_STATS) ? 1 : 0;
ec6ba945
VZ		 6487 data->general.is_fcoe_flg =
6488 (params->ramrod_params.flags & CLIENT_IS_FCOE) ? 1 : 0;
523224a3
DK		 6489 data->general.activate_flg = activate;
6490 data->general.sp_client_id = params->rxq_params.spcl_id;
6491
6492 /* Rx data */
6493 data->rx.tpa_en_flg =
6494 (params->rxq_params.flags & QUEUE_FLG_TPA) ? 1 : 0;
6495 data->rx.vmqueue_mode_en_flg = 0;
6496 data->rx.cache_line_alignment_log_size =
6497 params->rxq_params.cache_line_log;
6498 data->rx.enable_dynamic_hc =
6499 (params->rxq_params.flags & QUEUE_FLG_DHC) ? 1 : 0;
6500 data->rx.max_sges_for_packet = params->rxq_params.max_sges_pkt;
6501 data->rx.client_qzone_id = params->rxq_params.cl_qzone_id;
6502 data->rx.max_agg_size = params->rxq_params.tpa_agg_sz;
6503
6504 /* We don't set drop flags */
6505 data->rx.drop_ip_cs_err_flg = 0;
6506 data->rx.drop_tcp_cs_err_flg = 0;
6507 data->rx.drop_ttl0_flg = 0;
6508 data->rx.drop_udp_cs_err_flg = 0;
6509
6510 data->rx.inner_vlan_removal_enable_flg =
6511 (params->rxq_params.flags & QUEUE_FLG_VLAN) ? 1 : 0;
6512 data->rx.outer_vlan_removal_enable_flg =
6513 (params->rxq_params.flags & QUEUE_FLG_OV) ? 1 : 0;
6514 data->rx.status_block_id = params->rxq_params.fw_sb_id;
6515 data->rx.rx_sb_index_number = params->rxq_params.sb_cq_index;
6516 data->rx.bd_buff_size = cpu_to_le16(params->rxq_params.buf_sz);
6517 data->rx.sge_buff_size = cpu_to_le16(params->rxq_params.sge_buf_sz);
6518 data->rx.mtu = cpu_to_le16(params->rxq_params.mtu);
6519 data->rx.bd_page_base.lo =
6520 cpu_to_le32(U64_LO(params->rxq_params.dscr_map));
6521 data->rx.bd_page_base.hi =
6522 cpu_to_le32(U64_HI(params->rxq_params.dscr_map));
6523 data->rx.sge_page_base.lo =
6524 cpu_to_le32(U64_LO(params->rxq_params.sge_map));
6525 data->rx.sge_page_base.hi =
6526 cpu_to_le32(U64_HI(params->rxq_params.sge_map));
6527 data->rx.cqe_page_base.lo =
6528 cpu_to_le32(U64_LO(params->rxq_params.rcq_map));
6529 data->rx.cqe_page_base.hi =
6530 cpu_to_le32(U64_HI(params->rxq_params.rcq_map));
6531 data->rx.is_leading_rss =
6532 (params->ramrod_params.flags & CLIENT_IS_LEADING_RSS) ? 1 : 0;
6533 data->rx.is_approx_mcast = data->rx.is_leading_rss;
6534
6535 /* Tx data */
6536 data->tx.enforce_security_flg = 0; /* VF specific */
6537 data->tx.tx_status_block_id = params->txq_params.fw_sb_id;
6538 data->tx.tx_sb_index_number = params->txq_params.sb_cq_index;
6539 data->tx.mtu = 0; /* VF specific */
6540 data->tx.tx_bd_page_base.lo =
6541 cpu_to_le32(U64_LO(params->txq_params.dscr_map));
6542 data->tx.tx_bd_page_base.hi =
6543 cpu_to_le32(U64_HI(params->txq_params.dscr_map));
6544
6545 /* flow control data */
6546 data->fc.cqe_pause_thr_low = cpu_to_le16(params->pause.rcq_th_lo);
6547 data->fc.cqe_pause_thr_high = cpu_to_le16(params->pause.rcq_th_hi);
6548 data->fc.bd_pause_thr_low = cpu_to_le16(params->pause.bd_th_lo);
6549 data->fc.bd_pause_thr_high = cpu_to_le16(params->pause.bd_th_hi);
6550 data->fc.sge_pause_thr_low = cpu_to_le16(params->pause.sge_th_lo);
6551 data->fc.sge_pause_thr_high = cpu_to_le16(params->pause.sge_th_hi);
6552 data->fc.rx_cos_mask = cpu_to_le16(params->pause.pri_map);
6553
6554 data->fc.safc_group_num = params->txq_params.cos;
6555 data->fc.safc_group_en_flg =
6556 (params->txq_params.flags & QUEUE_FLG_COS) ? 1 : 0;
ec6ba945
VZ		 6557 data->fc.traffic_type =
6558 (params->ramrod_params.flags & CLIENT_IS_FCOE) ?
6559 LLFC_TRAFFIC_TYPE_FCOE : LLFC_TRAFFIC_TYPE_NW;
523224a3
DK		 6560}
6561
6562static inline void bnx2x_set_ctx_validation(struct eth_context *cxt, u32 cid)
6563{
6564 /* ustorm cxt validation */
6565 cxt->ustorm_ag_context.cdu_usage =
6566 CDU_RSRVD_VALUE_TYPE_A(cid, CDU_REGION_NUMBER_UCM_AG,
6567 ETH_CONNECTION_TYPE);
6568 /* xcontext validation */
6569 cxt->xstorm_ag_context.cdu_reserved =
6570 CDU_RSRVD_VALUE_TYPE_A(cid, CDU_REGION_NUMBER_XCM_AG,
6571 ETH_CONNECTION_TYPE);
6572}
6573
8d96286a 6574static int bnx2x_setup_fw_client(struct bnx2x *bp,
6575 struct bnx2x_client_init_params *params,
6576 u8 activate,
6577 struct client_init_ramrod_data *data,
6578 dma_addr_t data_mapping)
523224a3
DK		 6579{
6580 u16 hc_usec;
6581 int ramrod = RAMROD_CMD_ID_ETH_CLIENT_SETUP;
6582 int ramrod_flags = 0, rc;
6583
6584 /* HC and context validation values */
6585 hc_usec = params->txq_params.hc_rate ?
6586 1000000 / params->txq_params.hc_rate : 0;
6587 bnx2x_update_coalesce_sb_index(bp,
6588 params->txq_params.fw_sb_id,
6589 params->txq_params.sb_cq_index,
6590 !(params->txq_params.flags & QUEUE_FLG_HC),
6591 hc_usec);
6592
6593 *(params->ramrod_params.pstate) = BNX2X_FP_STATE_OPENING;
6594
6595 hc_usec = params->rxq_params.hc_rate ?
6596 1000000 / params->rxq_params.hc_rate : 0;
6597 bnx2x_update_coalesce_sb_index(bp,
6598 params->rxq_params.fw_sb_id,
6599 params->rxq_params.sb_cq_index,
6600 !(params->rxq_params.flags & QUEUE_FLG_HC),
6601 hc_usec);
6602
6603 bnx2x_set_ctx_validation(params->rxq_params.cxt,
6604 params->rxq_params.cid);
6605
6606 /* zero stats */
6607 if (params->txq_params.flags & QUEUE_FLG_STATS)
6608 storm_memset_xstats_zero(bp, BP_PORT(bp),
6609 params->txq_params.stat_id);
6610
6611 if (params->rxq_params.flags & QUEUE_FLG_STATS) {
6612 storm_memset_ustats_zero(bp, BP_PORT(bp),
6613 params->rxq_params.stat_id);
6614 storm_memset_tstats_zero(bp, BP_PORT(bp),
6615 params->rxq_params.stat_id);
6616 }
6617
6618 /* Fill the ramrod data */
6619 bnx2x_fill_cl_init_data(bp, params, activate, data);
6620
6621 /* SETUP ramrod.
6622 *
6623 * bnx2x_sp_post() takes a spin_lock thus no other explict memory
6624 * barrier except from mmiowb() is needed to impose a
6625 * proper ordering of memory operations.
6626 */
6627 mmiowb();
a2fbb9ea 6628
a2fbb9ea 6629
523224a3
DK		 6630 bnx2x_sp_post(bp, ramrod, params->ramrod_params.cid,
6631 U64_HI(data_mapping), U64_LO(data_mapping), 0);
a2fbb9ea 6632
34f80b04 6633 /* Wait for completion */
523224a3
DK		 6634 rc = bnx2x_wait_ramrod(bp, params->ramrod_params.state,
6635 params->ramrod_params.index,
6636 params->ramrod_params.pstate,
6637 ramrod_flags);
34f80b04 6638 return rc;
a2fbb9ea
ET		 6639}
6640
d6214d7a 6641/**
e8920674 6642 * bnx2x_set_int_mode - configure interrupt mode
d6214d7a 6643 *
e8920674 6644 * @bp: driver handle
d6214d7a 6645 *
e8920674 6646 * In case of MSI-X it will also try to enable MSI-X.
d6214d7a
DK		 6647 */
6648static int __devinit bnx2x_set_int_mode(struct bnx2x *bp)
ca00392c 6649{
d6214d7a 6650 int rc = 0;
ca00392c 6651
d6214d7a
DK		 6652 switch (bp->int_mode) {
6653 case INT_MODE_MSI:
6654 bnx2x_enable_msi(bp);
6655 /* falling through... */
6656 case INT_MODE_INTx:
ec6ba945 6657 bp->num_queues = 1 + NONE_ETH_CONTEXT_USE;
d6214d7a 6658 DP(NETIF_MSG_IFUP, "set number of queues to 1\n");
ca00392c 6659 break;
d6214d7a
DK		 6660 default:
6661 /* Set number of queues according to bp->multi_mode value */
6662 bnx2x_set_num_queues(bp);
ca00392c 6663
d6214d7a
DK		 6664 DP(NETIF_MSG_IFUP, "set number of queues to %d\n",
6665 bp->num_queues);
ca00392c 6666
d6214d7a
DK		 6667 /* if we can't use MSI-X we only need one fp,
6668 * so try to enable MSI-X with the requested number of fp's
6669 * and fallback to MSI or legacy INTx with one fp
6670 */
6671 rc = bnx2x_enable_msix(bp);
6672 if (rc) {
6673 /* failed to enable MSI-X */
6674 if (bp->multi_mode)
6675 DP(NETIF_MSG_IFUP,
6676 "Multi requested but failed to "
6677 "enable MSI-X (%d), "
6678 "set number of queues to %d\n",
6679 bp->num_queues,
ec6ba945
VZ		 6680 1 + NONE_ETH_CONTEXT_USE);
6681 bp->num_queues = 1 + NONE_ETH_CONTEXT_USE;
d6214d7a
DK		 6682
6683 if (!(bp->flags & DISABLE_MSI_FLAG))
6684 bnx2x_enable_msi(bp);
6685 }
ca00392c 6686
9f6c9258
DK		 6687 break;
6688 }
d6214d7a
DK		 6689
6690 return rc;
a2fbb9ea
ET		 6691}
6692
c2bff63f
DK		 6693/* must be called prioir to any HW initializations */
6694static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp)
6695{
6696 return L2_ILT_LINES(bp);
6697}
6698
523224a3
DK		 6699void bnx2x_ilt_set_info(struct bnx2x *bp)
6700{
6701 struct ilt_client_info *ilt_client;
6702 struct bnx2x_ilt *ilt = BP_ILT(bp);
6703 u16 line = 0;
6704
6705 ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp));
6706 DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line);
6707
6708 /* CDU */
6709 ilt_client = &ilt->clients[ILT_CLIENT_CDU];
6710 ilt_client->client_num = ILT_CLIENT_CDU;
6711 ilt_client->page_size = CDU_ILT_PAGE_SZ;
6712 ilt_client->flags = ILT_CLIENT_SKIP_MEM;
6713 ilt_client->start = line;
6714 line += L2_ILT_LINES(bp);
6715#ifdef BCM_CNIC
6716 line += CNIC_ILT_LINES;
6717#endif
6718 ilt_client->end = line - 1;
6719
6720 DP(BNX2X_MSG_SP, "ilt client[CDU]: start %d, end %d, psz 0x%x, "
6721 "flags 0x%x, hw psz %d\n",
6722 ilt_client->start,
6723 ilt_client->end,
6724 ilt_client->page_size,
6725 ilt_client->flags,
6726 ilog2(ilt_client->page_size >> 12));
6727
6728 /* QM */
6729 if (QM_INIT(bp->qm_cid_count)) {
6730 ilt_client = &ilt->clients[ILT_CLIENT_QM];
6731 ilt_client->client_num = ILT_CLIENT_QM;
6732 ilt_client->page_size = QM_ILT_PAGE_SZ;
6733 ilt_client->flags = 0;
6734 ilt_client->start = line;
6735
6736 /* 4 bytes for each cid */
6737 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
6738 QM_ILT_PAGE_SZ);
6739
6740 ilt_client->end = line - 1;
6741
6742 DP(BNX2X_MSG_SP, "ilt client[QM]: start %d, end %d, psz 0x%x, "
6743 "flags 0x%x, hw psz %d\n",
6744 ilt_client->start,
6745 ilt_client->end,
6746 ilt_client->page_size,
6747 ilt_client->flags,
6748 ilog2(ilt_client->page_size >> 12));
6749
6750 }
6751 /* SRC */
6752 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
6753#ifdef BCM_CNIC
6754 ilt_client->client_num = ILT_CLIENT_SRC;
6755 ilt_client->page_size = SRC_ILT_PAGE_SZ;
6756 ilt_client->flags = 0;
6757 ilt_client->start = line;
6758 line += SRC_ILT_LINES;
6759 ilt_client->end = line - 1;
6760
6761 DP(BNX2X_MSG_SP, "ilt client[SRC]: start %d, end %d, psz 0x%x, "
6762 "flags 0x%x, hw psz %d\n",
6763 ilt_client->start,
6764 ilt_client->end,
6765 ilt_client->page_size,
6766 ilt_client->flags,
6767 ilog2(ilt_client->page_size >> 12));
6768
6769#else
6770 ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM);
6771#endif
9f6c9258 6772
523224a3
DK		 6773 /* TM */
6774 ilt_client = &ilt->clients[ILT_CLIENT_TM];
6775#ifdef BCM_CNIC
6776 ilt_client->client_num = ILT_CLIENT_TM;
6777 ilt_client->page_size = TM_ILT_PAGE_SZ;
6778 ilt_client->flags = 0;
6779 ilt_client->start = line;
6780 line += TM_ILT_LINES;
6781 ilt_client->end = line - 1;
6782
6783 DP(BNX2X_MSG_SP, "ilt client[TM]: start %d, end %d, psz 0x%x, "
6784 "flags 0x%x, hw psz %d\n",
6785 ilt_client->start,
6786 ilt_client->end,
6787 ilt_client->page_size,
6788 ilt_client->flags,
6789 ilog2(ilt_client->page_size >> 12));
9f6c9258 6790
523224a3
DK		 6791#else
6792 ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM);
6793#endif
6794}
f85582f8 6795
523224a3
DK		 6796int bnx2x_setup_client(struct bnx2x *bp, struct bnx2x_fastpath *fp,
6797 int is_leading)
a2fbb9ea 6798{
523224a3 6799 struct bnx2x_client_init_params params = { {0} };
a2fbb9ea
ET		 6800 int rc;
6801
ec6ba945
VZ		 6802 /* reset IGU state skip FCoE L2 queue */
6803 if (!IS_FCOE_FP(fp))
6804 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0,
523224a3 6805 IGU_INT_ENABLE, 0);
a2fbb9ea 6806
523224a3
DK		 6807 params.ramrod_params.pstate = &fp->state;
6808 params.ramrod_params.state = BNX2X_FP_STATE_OPEN;
6809 params.ramrod_params.index = fp->index;
6810 params.ramrod_params.cid = fp->cid;
a2fbb9ea 6811
ec6ba945
VZ		 6812#ifdef BCM_CNIC
6813 if (IS_FCOE_FP(fp))
6814 params.ramrod_params.flags |= CLIENT_IS_FCOE;
6815
6816#endif
6817
523224a3
DK		 6818 if (is_leading)
6819 params.ramrod_params.flags |= CLIENT_IS_LEADING_RSS;
a2fbb9ea 6820
523224a3
DK		 6821 bnx2x_pf_rx_cl_prep(bp, fp, &params.pause, &params.rxq_params);
6822
6823 bnx2x_pf_tx_cl_prep(bp, fp, &params.txq_params);
6824
6825 rc = bnx2x_setup_fw_client(bp, &params, 1,
6826 bnx2x_sp(bp, client_init_data),
6827 bnx2x_sp_mapping(bp, client_init_data));
34f80b04 6828 return rc;
a2fbb9ea
ET		 6829}
6830
8d96286a 6831static int bnx2x_stop_fw_client(struct bnx2x *bp,
6832 struct bnx2x_client_ramrod_params *p)
a2fbb9ea 6833{
34f80b04 6834 int rc;
a2fbb9ea 6835
523224a3 6836 int poll_flag = p->poll ? WAIT_RAMROD_POLL : 0;
a2fbb9ea 6837
523224a3
DK		 6838 /* halt the connection */
6839 *p->pstate = BNX2X_FP_STATE_HALTING;
6840 bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_HALT, p->cid, 0,
6841 p->cl_id, 0);
a2fbb9ea 6842
34f80b04 6843 /* Wait for completion */
523224a3
DK		 6844 rc = bnx2x_wait_ramrod(bp, BNX2X_FP_STATE_HALTED, p->index,
6845 p->pstate, poll_flag);
34f80b04 6846 if (rc) /* timeout */
da5a662a 6847 return rc;
a2fbb9ea 6848
523224a3
DK		 6849 *p->pstate = BNX2X_FP_STATE_TERMINATING;
6850 bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_TERMINATE, p->cid, 0,
6851 p->cl_id, 0);
6852 /* Wait for completion */
6853 rc = bnx2x_wait_ramrod(bp, BNX2X_FP_STATE_TERMINATED, p->index,
6854 p->pstate, poll_flag);
6855 if (rc) /* timeout */
6856 return rc;
a2fbb9ea 6857
a2fbb9ea 6858
523224a3
DK		 6859 /* delete cfc entry */
6860 bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_CFC_DEL, p->cid, 0, 0, 1);
da5a662a 6861
523224a3
DK		 6862 /* Wait for completion */
6863 rc = bnx2x_wait_ramrod(bp, BNX2X_FP_STATE_CLOSED, p->index,
6864 p->pstate, WAIT_RAMROD_COMMON);
da5a662a 6865 return rc;
a2fbb9ea
ET		 6866}
6867
523224a3
DK		 6868static int bnx2x_stop_client(struct bnx2x *bp, int index)
6869{
6870 struct bnx2x_client_ramrod_params client_stop = {0};
6871 struct bnx2x_fastpath *fp = &bp->fp[index];
6872
6873 client_stop.index = index;
6874 client_stop.cid = fp->cid;
6875 client_stop.cl_id = fp->cl_id;
6876 client_stop.pstate = &(fp->state);
6877 client_stop.poll = 0;
6878
6879 return bnx2x_stop_fw_client(bp, &client_stop);
6880}
6881
6882
34f80b04
EG		 6883static void bnx2x_reset_func(struct bnx2x *bp)
6884{
6885 int port = BP_PORT(bp);
6886 int func = BP_FUNC(bp);
f2e0899f 6887 int i;
523224a3 6888 int pfunc_offset_fp = offsetof(struct hc_sb_data, p_func) +
f2e0899f
DK		 6889 (CHIP_IS_E2(bp) ?
6890 offsetof(struct hc_status_block_data_e2, common) :
6891 offsetof(struct hc_status_block_data_e1x, common));
523224a3
DK		 6892 int pfunc_offset_sp = offsetof(struct hc_sp_status_block_data, p_func);
6893 int pfid_offset = offsetof(struct pci_entity, pf_id);
6894
6895 /* Disable the function in the FW */
6896 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
6897 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
6898 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
6899 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
6900
6901 /* FP SBs */
ec6ba945 6902 for_each_eth_queue(bp, i) {
523224a3
DK		 6903 struct bnx2x_fastpath *fp = &bp->fp[i];
6904 REG_WR8(bp,
6905 BAR_CSTRORM_INTMEM +
6906 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id)
6907 + pfunc_offset_fp + pfid_offset,
6908 HC_FUNCTION_DISABLED);
6909 }
6910
6911 /* SP SB */
6912 REG_WR8(bp,
6913 BAR_CSTRORM_INTMEM +
6914 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
6915 pfunc_offset_sp + pfid_offset,
6916 HC_FUNCTION_DISABLED);
6917
6918
6919 for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++)
6920 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
6921 0);
34f80b04
EG		 6922
6923 /* Configure IGU */
f2e0899f
DK		 6924 if (bp->common.int_block == INT_BLOCK_HC) {
6925 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
6926 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
6927 } else {
6928 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
6929 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
6930 }
34f80b04 6931
37b091ba
MC		 6932#ifdef BCM_CNIC
6933 /* Disable Timer scan */
6934 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
6935 /*
6936 * Wait for at least 10ms and up to 2 second for the timers scan to
6937 * complete
6938 */
6939 for (i = 0; i < 200; i++) {
6940 msleep(10);
6941 if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4))
6942 break;
6943 }
6944#endif
34f80b04 6945 /* Clear ILT */
f2e0899f
DK		 6946 bnx2x_clear_func_ilt(bp, func);
6947
6948 /* Timers workaround bug for E2: if this is vnic-3,
6949 * we need to set the entire ilt range for this timers.
6950 */
6951 if (CHIP_IS_E2(bp) && BP_VN(bp) == 3) {
6952 struct ilt_client_info ilt_cli;
6953 /* use dummy TM client */
6954 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
6955 ilt_cli.start = 0;
6956 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
6957 ilt_cli.client_num = ILT_CLIENT_TM;
6958
6959 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR);
6960 }
6961
6962 /* this assumes that reset_port() called before reset_func()*/
6963 if (CHIP_IS_E2(bp))
6964 bnx2x_pf_disable(bp);
523224a3
DK		 6965
6966 bp->dmae_ready = 0;
34f80b04
EG		 6967}
6968
6969static void bnx2x_reset_port(struct bnx2x *bp)
6970{
6971 int port = BP_PORT(bp);
6972 u32 val;
6973
6974 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
6975
6976 /* Do not rcv packets to BRB */
6977 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
6978 /* Do not direct rcv packets that are not for MCP to the BRB */
6979 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
6980 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
6981
6982 /* Configure AEU */
6983 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
6984
6985 msleep(100);
6986 /* Check for BRB port occupancy */
6987 val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
6988 if (val)
6989 DP(NETIF_MSG_IFDOWN,
33471629 6990 "BRB1 is not empty %d blocks are occupied\n", val);
34f80b04
EG		 6991
6992 /* TODO: Close Doorbell port? */
6993}
6994
34f80b04
EG		 6995static void bnx2x_reset_chip(struct bnx2x *bp, u32 reset_code)
6996{
6997 DP(BNX2X_MSG_MCP, "function %d reset_code %x\n",
f2e0899f 6998 BP_ABS_FUNC(bp), reset_code);
34f80b04
EG		 6999
7000 switch (reset_code) {
7001 case FW_MSG_CODE_DRV_UNLOAD_COMMON:
7002 bnx2x_reset_port(bp);
7003 bnx2x_reset_func(bp);
7004 bnx2x_reset_common(bp);
7005 break;
7006
7007 case FW_MSG_CODE_DRV_UNLOAD_PORT:
7008 bnx2x_reset_port(bp);
7009 bnx2x_reset_func(bp);
7010 break;
7011
7012 case FW_MSG_CODE_DRV_UNLOAD_FUNCTION:
7013 bnx2x_reset_func(bp);
7014 break;
49d66772 7015
34f80b04
EG		 7016 default:
7017 BNX2X_ERR("Unknown reset_code (0x%x) from MCP\n", reset_code);
7018 break;
7019 }
7020}
7021
ec6ba945
VZ		 7022#ifdef BCM_CNIC
7023static inline void bnx2x_del_fcoe_eth_macs(struct bnx2x *bp)
7024{
7025 if (bp->flags & FCOE_MACS_SET) {
7026 if (!IS_MF_SD(bp))
7027 bnx2x_set_fip_eth_mac_addr(bp, 0);
7028
7029 bnx2x_set_all_enode_macs(bp, 0);
7030
7031 bp->flags &= ~FCOE_MACS_SET;
7032 }
7033}
7034#endif
7035
9f6c9258 7036void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode)
a2fbb9ea 7037{
da5a662a 7038 int port = BP_PORT(bp);
a2fbb9ea 7039 u32 reset_code = 0;
da5a662a 7040 int i, cnt, rc;
a2fbb9ea 7041
555f6c78 7042 /* Wait until tx fastpath tasks complete */
ec6ba945 7043 for_each_tx_queue(bp, i) {
228241eb
ET		 7044 struct bnx2x_fastpath *fp = &bp->fp[i];
7045
34f80b04 7046 cnt = 1000;
e8b5fc51 7047 while (bnx2x_has_tx_work_unload(fp)) {
da5a662a 7048
34f80b04
EG		 7049 if (!cnt) {
7050 BNX2X_ERR("timeout waiting for queue[%d]\n",
7051 i);
7052#ifdef BNX2X_STOP_ON_ERROR
7053 bnx2x_panic();
7054 return -EBUSY;
7055#else
7056 break;
7057#endif
7058 }
7059 cnt--;
da5a662a 7060 msleep(1);
34f80b04 7061 }
228241eb 7062 }
da5a662a
VZ		 7063 /* Give HW time to discard old tx messages */
7064 msleep(1);
a2fbb9ea 7065
6e30dd4e 7066 bnx2x_set_eth_mac(bp, 0);
65abd74d 7067
6e30dd4e 7068 bnx2x_invalidate_uc_list(bp);
3101c2bc 7069
6e30dd4e
VZ		 7070 if (CHIP_IS_E1(bp))
7071 bnx2x_invalidate_e1_mc_list(bp);
7072 else {
7073 bnx2x_invalidate_e1h_mc_list(bp);
7074 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
3101c2bc 7075 }
523224a3 7076
993ac7b5 7077#ifdef BCM_CNIC
ec6ba945 7078 bnx2x_del_fcoe_eth_macs(bp);
993ac7b5 7079#endif
3101c2bc 7080
65abd74d
YG		 7081 if (unload_mode == UNLOAD_NORMAL)
7082 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
7083
7d0446c2 7084 else if (bp->flags & NO_WOL_FLAG)
65abd74d 7085 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
65abd74d 7086
7d0446c2 7087 else if (bp->wol) {
65abd74d
YG		 7088 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
7089 u8 *mac_addr = bp->dev->dev_addr;
7090 u32 val;
7091 /* The mac address is written to entries 1-4 to
7092 preserve entry 0 which is used by the PMF */
7093 u8 entry = (BP_E1HVN(bp) + 1)*8;
7094
7095 val = (mac_addr[0] << 8) | mac_addr[1];
7096 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val);
7097
7098 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
7099 (mac_addr[4] << 8) | mac_addr[5];
7100 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
7101
7102 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
7103
7104 } else
7105 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
da5a662a 7106
34f80b04
EG		 7107 /* Close multi and leading connections
7108 Completions for ramrods are collected in a synchronous way */
523224a3
DK		 7109 for_each_queue(bp, i)
7110
7111 if (bnx2x_stop_client(bp, i))
7112#ifdef BNX2X_STOP_ON_ERROR
7113 return;
7114#else
228241eb 7115 goto unload_error;
523224a3 7116#endif
a2fbb9ea 7117
523224a3 7118 rc = bnx2x_func_stop(bp);
da5a662a 7119 if (rc) {
523224a3 7120 BNX2X_ERR("Function stop failed!\n");
da5a662a 7121#ifdef BNX2X_STOP_ON_ERROR
523224a3 7122 return;
da5a662a
VZ		 7123#else
7124 goto unload_error;
34f80b04 7125#endif
228241eb 7126 }
523224a3 7127#ifndef BNX2X_STOP_ON_ERROR
228241eb 7128unload_error:
523224a3 7129#endif
34f80b04 7130 if (!BP_NOMCP(bp))
a22f0788 7131 reset_code = bnx2x_fw_command(bp, reset_code, 0);
34f80b04 7132 else {
f2e0899f
DK		 7133 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d] "
7134 "%d, %d, %d\n", BP_PATH(bp),
7135 load_count[BP_PATH(bp)][0],
7136 load_count[BP_PATH(bp)][1],
7137 load_count[BP_PATH(bp)][2]);
7138 load_count[BP_PATH(bp)][0]--;
7139 load_count[BP_PATH(bp)][1 + port]--;
7140 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d] "
7141 "%d, %d, %d\n", BP_PATH(bp),
7142 load_count[BP_PATH(bp)][0], load_count[BP_PATH(bp)][1],
7143 load_count[BP_PATH(bp)][2]);
7144 if (load_count[BP_PATH(bp)][0] == 0)
34f80b04 7145 reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
f2e0899f 7146 else if (load_count[BP_PATH(bp)][1 + port] == 0)
34f80b04
EG		 7147 reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT;
7148 else
7149 reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
7150 }
a2fbb9ea 7151
34f80b04
EG		 7152 if ((reset_code == FW_MSG_CODE_DRV_UNLOAD_COMMON) ||
7153 (reset_code == FW_MSG_CODE_DRV_UNLOAD_PORT))
7154 bnx2x__link_reset(bp);
a2fbb9ea 7155
523224a3
DK		 7156 /* Disable HW interrupts, NAPI */
7157 bnx2x_netif_stop(bp, 1);
7158
7159 /* Release IRQs */
d6214d7a 7160 bnx2x_free_irq(bp);
523224a3 7161
a2fbb9ea 7162 /* Reset the chip */
228241eb 7163 bnx2x_reset_chip(bp, reset_code);
a2fbb9ea
ET		 7164
7165 /* Report UNLOAD_DONE to MCP */
34f80b04 7166 if (!BP_NOMCP(bp))
a22f0788 7167 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
356e2385 7168
72fd0718
VZ		 7169}
7170
9f6c9258 7171void bnx2x_disable_close_the_gate(struct bnx2x *bp)
72fd0718
VZ		 7172{
7173 u32 val;
7174
7175 DP(NETIF_MSG_HW, "Disabling \"close the gates\"\n");
7176
7177 if (CHIP_IS_E1(bp)) {
7178 int port = BP_PORT(bp);
7179 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
7180 MISC_REG_AEU_MASK_ATTN_FUNC_0;
7181
7182 val = REG_RD(bp, addr);
7183 val &= ~(0x300);
7184 REG_WR(bp, addr, val);
7185 } else if (CHIP_IS_E1H(bp)) {
7186 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK);
7187 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
7188 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
7189 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val);
7190 }
7191}
7192
72fd0718
VZ		 7193/* Close gates #2, #3 and #4: */
7194static void bnx2x_set_234_gates(struct bnx2x *bp, bool close)
7195{
7196 u32 val, addr;
7197
7198 /* Gates #2 and #4a are closed/opened for "not E1" only */
7199 if (!CHIP_IS_E1(bp)) {
7200 /* #4 */
7201 val = REG_RD(bp, PXP_REG_HST_DISCARD_DOORBELLS);
7202 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS,
7203 close ? (val | 0x1) : (val & (~(u32)1)));
7204 /* #2 */
7205 val = REG_RD(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES);
7206 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES,
7207 close ? (val | 0x1) : (val & (~(u32)1)));
7208 }
7209
7210 /* #3 */
7211 addr = BP_PORT(bp) ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
7212 val = REG_RD(bp, addr);
7213 REG_WR(bp, addr, (!close) ? (val | 0x1) : (val & (~(u32)1)));
7214
7215 DP(NETIF_MSG_HW, "%s gates #2, #3 and #4\n",
7216 close ? "closing" : "opening");
7217 mmiowb();
7218}
7219
7220#define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */
7221
7222static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val)
7223{
7224 /* Do some magic... */
7225 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
7226 *magic_val = val & SHARED_MF_CLP_MAGIC;
7227 MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
7228}
7229
e8920674
DK		 7230/**
7231 * bnx2x_clp_reset_done - restore the value of the `magic' bit.
72fd0718 7232 *
e8920674
DK		 7233 * @bp: driver handle
7234 * @magic_val: old value of the `magic' bit.
72fd0718
VZ		 7235 */
7236static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val)
7237{
7238 /* Restore the `magic' bit value... */
72fd0718
VZ		 7239 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
7240 MF_CFG_WR(bp, shared_mf_config.clp_mb,
7241 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
7242}
7243
f85582f8 7244/**
e8920674 7245 * bnx2x_reset_mcp_prep - prepare for MCP reset.
72fd0718 7246 *
e8920674
DK		 7247 * @bp: driver handle
7248 * @magic_val: old value of 'magic' bit.
7249 *
7250 * Takes care of CLP configurations.
72fd0718
VZ		 7251 */
7252static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val)
7253{
7254 u32 shmem;
7255 u32 validity_offset;
7256
7257 DP(NETIF_MSG_HW, "Starting\n");
7258
7259 /* Set `magic' bit in order to save MF config */
7260 if (!CHIP_IS_E1(bp))
7261 bnx2x_clp_reset_prep(bp, magic_val);
7262
7263 /* Get shmem offset */
7264 shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
7265 validity_offset = offsetof(struct shmem_region, validity_map[0]);
7266
7267 /* Clear validity map flags */
7268 if (shmem > 0)
7269 REG_WR(bp, shmem + validity_offset, 0);
7270}
7271
7272#define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */
7273#define MCP_ONE_TIMEOUT 100 /* 100 ms */
7274
e8920674
DK		 7275/**
7276 * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT
72fd0718 7277 *
e8920674 7278 * @bp: driver handle
72fd0718
VZ		 7279 */
7280static inline void bnx2x_mcp_wait_one(struct bnx2x *bp)
7281{
7282 /* special handling for emulation and FPGA,
7283 wait 10 times longer */
7284 if (CHIP_REV_IS_SLOW(bp))
7285 msleep(MCP_ONE_TIMEOUT*10);
7286 else
7287 msleep(MCP_ONE_TIMEOUT);
7288}
7289
7290static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val)
7291{
7292 u32 shmem, cnt, validity_offset, val;
7293 int rc = 0;
7294
7295 msleep(100);
7296
7297 /* Get shmem offset */
7298 shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
7299 if (shmem == 0) {
7300 BNX2X_ERR("Shmem 0 return failure\n");
7301 rc = -ENOTTY;
7302 goto exit_lbl;
7303 }
7304
7305 validity_offset = offsetof(struct shmem_region, validity_map[0]);
7306
7307 /* Wait for MCP to come up */
7308 for (cnt = 0; cnt < (MCP_TIMEOUT / MCP_ONE_TIMEOUT); cnt++) {
7309 /* TBD: its best to check validity map of last port.
7310 * currently checks on port 0.
7311 */
7312 val = REG_RD(bp, shmem + validity_offset);
7313 DP(NETIF_MSG_HW, "shmem 0x%x validity map(0x%x)=0x%x\n", shmem,
7314 shmem + validity_offset, val);
7315
7316 /* check that shared memory is valid. */
7317 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
7318 == (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
7319 break;
7320
7321 bnx2x_mcp_wait_one(bp);
7322 }
7323
7324 DP(NETIF_MSG_HW, "Cnt=%d Shmem validity map 0x%x\n", cnt, val);
7325
7326 /* Check that shared memory is valid. This indicates that MCP is up. */
7327 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) !=
7328 (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) {
7329 BNX2X_ERR("Shmem signature not present. MCP is not up !!\n");
7330 rc = -ENOTTY;
7331 goto exit_lbl;
7332 }
7333
7334exit_lbl:
7335 /* Restore the `magic' bit value */
7336 if (!CHIP_IS_E1(bp))
7337 bnx2x_clp_reset_done(bp, magic_val);
7338
7339 return rc;
7340}
7341
7342static void bnx2x_pxp_prep(struct bnx2x *bp)
7343{
7344 if (!CHIP_IS_E1(bp)) {
7345 REG_WR(bp, PXP2_REG_RD_START_INIT, 0);
7346 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0);
7347 REG_WR(bp, PXP2_REG_RQ_CFG_DONE, 0);
7348 mmiowb();
7349 }
7350}
7351
7352/*
7353 * Reset the whole chip except for:
7354 * - PCIE core
7355 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by
7356 * one reset bit)
7357 * - IGU
7358 * - MISC (including AEU)
7359 * - GRC
7360 * - RBCN, RBCP
7361 */
7362static void bnx2x_process_kill_chip_reset(struct bnx2x *bp)
7363{
7364 u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
7365
7366 not_reset_mask1 =
7367 MISC_REGISTERS_RESET_REG_1_RST_HC |
7368 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
7369 MISC_REGISTERS_RESET_REG_1_RST_PXP;
7370
7371 not_reset_mask2 =
7372 MISC_REGISTERS_RESET_REG_2_RST_MDIO |
7373 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
7374 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
7375 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
7376 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
7377 MISC_REGISTERS_RESET_REG_2_RST_GRC |
7378 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
7379 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B;
7380
7381 reset_mask1 = 0xffffffff;
7382
7383 if (CHIP_IS_E1(bp))
7384 reset_mask2 = 0xffff;
7385 else
7386 reset_mask2 = 0x1ffff;
7387
7388 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
7389 reset_mask1 & (~not_reset_mask1));
7390 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
7391 reset_mask2 & (~not_reset_mask2));
7392
7393 barrier();
7394 mmiowb();
7395
7396 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
7397 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, reset_mask2);
7398 mmiowb();
7399}
7400
7401static int bnx2x_process_kill(struct bnx2x *bp)
7402{
7403 int cnt = 1000;
7404 u32 val = 0;
7405 u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
7406
7407
7408 /* Empty the Tetris buffer, wait for 1s */
7409 do {
7410 sr_cnt = REG_RD(bp, PXP2_REG_RD_SR_CNT);
7411 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT);
7412 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0);
7413 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1);
7414 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2);
7415 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
7416 ((port_is_idle_0 & 0x1) == 0x1) &&
7417 ((port_is_idle_1 & 0x1) == 0x1) &&
7418 (pgl_exp_rom2 == 0xffffffff))
7419 break;
7420 msleep(1);
7421 } while (cnt-- > 0);
7422
7423 if (cnt <= 0) {
7424 DP(NETIF_MSG_HW, "Tetris buffer didn't get empty or there"
7425 " are still"
7426 " outstanding read requests after 1s!\n");
7427 DP(NETIF_MSG_HW, "sr_cnt=0x%08x, blk_cnt=0x%08x,"
7428 " port_is_idle_0=0x%08x,"
7429 " port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
7430 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
7431 pgl_exp_rom2);
7432 return -EAGAIN;
7433 }
7434
7435 barrier();
7436
7437 /* Close gates #2, #3 and #4 */
7438 bnx2x_set_234_gates(bp, true);
7439
7440 /* TBD: Indicate that "process kill" is in progress to MCP */
7441
7442 /* Clear "unprepared" bit */
7443 REG_WR(bp, MISC_REG_UNPREPARED, 0);
7444 barrier();
7445
7446 /* Make sure all is written to the chip before the reset */
7447 mmiowb();
7448
7449 /* Wait for 1ms to empty GLUE and PCI-E core queues,
7450 * PSWHST, GRC and PSWRD Tetris buffer.
7451 */
7452 msleep(1);
7453
7454 /* Prepare to chip reset: */
7455 /* MCP */
7456 bnx2x_reset_mcp_prep(bp, &val);
7457
7458 /* PXP */
7459 bnx2x_pxp_prep(bp);
7460 barrier();
7461
7462 /* reset the chip */
7463 bnx2x_process_kill_chip_reset(bp);
7464 barrier();
7465
7466 /* Recover after reset: */
7467 /* MCP */
7468 if (bnx2x_reset_mcp_comp(bp, val))
7469 return -EAGAIN;
7470
7471 /* PXP */
7472 bnx2x_pxp_prep(bp);
7473
7474 /* Open the gates #2, #3 and #4 */
7475 bnx2x_set_234_gates(bp, false);
7476
7477 /* TBD: IGU/AEU preparation bring back the AEU/IGU to a
7478 * reset state, re-enable attentions. */
7479
a2fbb9ea
ET		 7480 return 0;
7481}
7482
72fd0718
VZ		 7483static int bnx2x_leader_reset(struct bnx2x *bp)
7484{
7485 int rc = 0;
7486 /* Try to recover after the failure */
7487 if (bnx2x_process_kill(bp)) {
7488 printk(KERN_ERR "%s: Something bad had happen! Aii!\n",
7489 bp->dev->name);
7490 rc = -EAGAIN;
7491 goto exit_leader_reset;
7492 }
7493
7494 /* Clear "reset is in progress" bit and update the driver state */
7495 bnx2x_set_reset_done(bp);
7496 bp->recovery_state = BNX2X_RECOVERY_DONE;
7497
7498exit_leader_reset:
7499 bp->is_leader = 0;
7500 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESERVED_08);
7501 smp_wmb();
7502 return rc;
7503}
7504
72fd0718
VZ		 7505/* Assumption: runs under rtnl lock. This together with the fact
7506 * that it's called only from bnx2x_reset_task() ensure that it
7507 * will never be called when netif_running(bp->dev) is false.
7508 */
7509static void bnx2x_parity_recover(struct bnx2x *bp)
7510{
7511 DP(NETIF_MSG_HW, "Handling parity\n");
7512 while (1) {
7513 switch (bp->recovery_state) {
7514 case BNX2X_RECOVERY_INIT:
7515 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n");
7516 /* Try to get a LEADER_LOCK HW lock */
7517 if (bnx2x_trylock_hw_lock(bp,
7518 HW_LOCK_RESOURCE_RESERVED_08))
7519 bp->is_leader = 1;
7520
7521 /* Stop the driver */
7522 /* If interface has been removed - break */
7523 if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY))
7524 return;
7525
7526 bp->recovery_state = BNX2X_RECOVERY_WAIT;
7527 /* Ensure "is_leader" and "recovery_state"
7528 * update values are seen on other CPUs
7529 */
7530 smp_wmb();
7531 break;
7532
7533 case BNX2X_RECOVERY_WAIT:
7534 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n");
7535 if (bp->is_leader) {
7536 u32 load_counter = bnx2x_get_load_cnt(bp);
7537 if (load_counter) {
7538 /* Wait until all other functions get
7539 * down.
7540 */
7541 schedule_delayed_work(&bp->reset_task,
7542 HZ/10);
7543 return;
7544 } else {
7545 /* If all other functions got down -
7546 * try to bring the chip back to
7547 * normal. In any case it's an exit
7548 * point for a leader.
7549 */
7550 if (bnx2x_leader_reset(bp) ||
7551 bnx2x_nic_load(bp, LOAD_NORMAL)) {
7552 printk(KERN_ERR"%s: Recovery "
7553 "has failed. Power cycle is "
7554 "needed.\n", bp->dev->name);
7555 /* Disconnect this device */
7556 netif_device_detach(bp->dev);
7557 /* Block ifup for all function
7558 * of this ASIC until
7559 * "process kill" or power
7560 * cycle.
7561 */
7562 bnx2x_set_reset_in_progress(bp);
7563 /* Shut down the power */
7564 bnx2x_set_power_state(bp,
7565 PCI_D3hot);
7566 return;
7567 }
7568
7569 return;
7570 }
7571 } else { /* non-leader */
7572 if (!bnx2x_reset_is_done(bp)) {
7573 /* Try to get a LEADER_LOCK HW lock as
7574 * long as a former leader may have
7575 * been unloaded by the user or
7576 * released a leadership by another
7577 * reason.
7578 */
7579 if (bnx2x_trylock_hw_lock(bp,
7580 HW_LOCK_RESOURCE_RESERVED_08)) {
7581 /* I'm a leader now! Restart a
7582 * switch case.
7583 */
7584 bp->is_leader = 1;
7585 break;
7586 }
7587
7588 schedule_delayed_work(&bp->reset_task,
7589 HZ/10);
7590 return;
7591
7592 } else { /* A leader has completed
7593 * the "process kill". It's an exit
7594 * point for a non-leader.
7595 */
7596 bnx2x_nic_load(bp, LOAD_NORMAL);
7597 bp->recovery_state =
7598 BNX2X_RECOVERY_DONE;
7599 smp_wmb();
7600 return;
7601 }
7602 }
7603 default:
7604 return;
7605 }
7606 }
7607}
7608
7609/* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is
7610 * scheduled on a general queue in order to prevent a dead lock.
7611 */
34f80b04
EG		 7612static void bnx2x_reset_task(struct work_struct *work)
7613{
72fd0718 7614 struct bnx2x *bp = container_of(work, struct bnx2x, reset_task.work);
34f80b04
EG		 7615
7616#ifdef BNX2X_STOP_ON_ERROR
7617 BNX2X_ERR("reset task called but STOP_ON_ERROR defined"
7618 " so reset not done to allow debug dump,\n"
72fd0718 7619 KERN_ERR " you will need to reboot when done\n");
34f80b04
EG		 7620 return;
7621#endif
7622
7623 rtnl_lock();
7624
7625 if (!netif_running(bp->dev))
7626 goto reset_task_exit;
7627
72fd0718
VZ		 7628 if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE))
7629 bnx2x_parity_recover(bp);
7630 else {
7631 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
7632 bnx2x_nic_load(bp, LOAD_NORMAL);
7633 }
34f80b04
EG		 7634
7635reset_task_exit:
7636 rtnl_unlock();
7637}
7638
a2fbb9ea
ET		 7639/* end of nic load/unload */
7640
a2fbb9ea
ET		 7641/*
7642 * Init service functions
7643 */
7644
8d96286a 7645static u32 bnx2x_get_pretend_reg(struct bnx2x *bp)
f2e0899f
DK		 7646{
7647 u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0;
7648 u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base;
7649 return base + (BP_ABS_FUNC(bp)) * stride;
f1ef27ef
EG		 7650}
7651
f2e0899f 7652static void bnx2x_undi_int_disable_e1h(struct bnx2x *bp)
f1ef27ef 7653{
f2e0899f 7654 u32 reg = bnx2x_get_pretend_reg(bp);
f1ef27ef
EG		 7655
7656 /* Flush all outstanding writes */
7657 mmiowb();
7658
7659 /* Pretend to be function 0 */
7660 REG_WR(bp, reg, 0);
f2e0899f 7661 REG_RD(bp, reg); /* Flush the GRC transaction (in the chip) */
f1ef27ef
EG		 7662
7663 /* From now we are in the "like-E1" mode */
7664 bnx2x_int_disable(bp);
7665
7666 /* Flush all outstanding writes */
7667 mmiowb();
7668
f2e0899f
DK		 7669 /* Restore the original function */
7670 REG_WR(bp, reg, BP_ABS_FUNC(bp));
7671 REG_RD(bp, reg);
f1ef27ef
EG		 7672}
7673
f2e0899f 7674static inline void bnx2x_undi_int_disable(struct bnx2x *bp)
f1ef27ef 7675{
f2e0899f 7676 if (CHIP_IS_E1(bp))
f1ef27ef 7677 bnx2x_int_disable(bp);
f2e0899f
DK		 7678 else
7679 bnx2x_undi_int_disable_e1h(bp);
f1ef27ef
EG		 7680}
7681
34f80b04
EG		 7682static void __devinit bnx2x_undi_unload(struct bnx2x *bp)
7683{
7684 u32 val;
7685
7686 /* Check if there is any driver already loaded */
7687 val = REG_RD(bp, MISC_REG_UNPREPARED);
7688 if (val == 0x1) {
7689 /* Check if it is the UNDI driver
7690 * UNDI driver initializes CID offset for normal bell to 0x7
7691 */
4a37fb66 7692 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_UNDI);
34f80b04
EG		 7693 val = REG_RD(bp, DORQ_REG_NORM_CID_OFST);
7694 if (val == 0x7) {
7695 u32 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
f2e0899f
DK		 7696 /* save our pf_num */
7697 int orig_pf_num = bp->pf_num;
da5a662a
VZ		 7698 u32 swap_en;
7699 u32 swap_val;
34f80b04 7700
b4661739
EG		 7701 /* clear the UNDI indication */
7702 REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0);
7703
34f80b04
EG		 7704 BNX2X_DEV_INFO("UNDI is active! reset device\n");
7705
7706 /* try unload UNDI on port 0 */
f2e0899f 7707 bp->pf_num = 0;
da5a662a 7708 bp->fw_seq =
f2e0899f 7709 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) &
da5a662a 7710 DRV_MSG_SEQ_NUMBER_MASK);
a22f0788 7711 reset_code = bnx2x_fw_command(bp, reset_code, 0);
34f80b04
EG		 7712
7713 /* if UNDI is loaded on the other port */
7714 if (reset_code != FW_MSG_CODE_DRV_UNLOAD_COMMON) {
7715
da5a662a 7716 /* send "DONE" for previous unload */
a22f0788
YR		 7717 bnx2x_fw_command(bp,
7718 DRV_MSG_CODE_UNLOAD_DONE, 0);
da5a662a
VZ		 7719
7720 /* unload UNDI on port 1 */
f2e0899f 7721 bp->pf_num = 1;
da5a662a 7722 bp->fw_seq =
f2e0899f 7723 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) &
da5a662a
VZ		 7724 DRV_MSG_SEQ_NUMBER_MASK);
7725 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
7726
a22f0788 7727 bnx2x_fw_command(bp, reset_code, 0);
34f80b04
EG		 7728 }
7729
b4661739
EG		 7730 /* now it's safe to release the lock */
7731 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_UNDI);
7732
f2e0899f 7733 bnx2x_undi_int_disable(bp);
da5a662a
VZ		 7734
7735 /* close input traffic and wait for it */
7736 /* Do not rcv packets to BRB */
7737 REG_WR(bp,
7738 (BP_PORT(bp) ? NIG_REG_LLH1_BRB1_DRV_MASK :
7739 NIG_REG_LLH0_BRB1_DRV_MASK), 0x0);
7740 /* Do not direct rcv packets that are not for MCP to
7741 * the BRB */
7742 REG_WR(bp,
7743 (BP_PORT(bp) ? NIG_REG_LLH1_BRB1_NOT_MCP :
7744 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
7745 /* clear AEU */
7746 REG_WR(bp,
7747 (BP_PORT(bp) ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
7748 MISC_REG_AEU_MASK_ATTN_FUNC_0), 0);
7749 msleep(10);
7750
7751 /* save NIG port swap info */
7752 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
7753 swap_en = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
34f80b04
EG		 7754 /* reset device */
7755 REG_WR(bp,
7756 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
da5a662a 7757 0xd3ffffff);
34f80b04
EG		 7758 REG_WR(bp,
7759 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
7760 0x1403);
da5a662a
VZ		 7761 /* take the NIG out of reset and restore swap values */
7762 REG_WR(bp,
7763 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
7764 MISC_REGISTERS_RESET_REG_1_RST_NIG);
7765 REG_WR(bp, NIG_REG_PORT_SWAP, swap_val);
7766 REG_WR(bp, NIG_REG_STRAP_OVERRIDE, swap_en);
7767
7768 /* send unload done to the MCP */
a22f0788 7769 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
da5a662a
VZ		 7770
7771 /* restore our func and fw_seq */
f2e0899f 7772 bp->pf_num = orig_pf_num;
da5a662a 7773 bp->fw_seq =
f2e0899f 7774 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) &
da5a662a 7775 DRV_MSG_SEQ_NUMBER_MASK);
b4661739
EG		 7776 } else
7777 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_UNDI);
34f80b04
EG		 7778 }
7779}
7780
7781static void __devinit bnx2x_get_common_hwinfo(struct bnx2x *bp)
7782{
7783 u32 val, val2, val3, val4, id;
72ce58c3 7784 u16 pmc;
34f80b04
EG		 7785
7786 /* Get the chip revision id and number. */
7787 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
7788 val = REG_RD(bp, MISC_REG_CHIP_NUM);
7789 id = ((val & 0xffff) << 16);
7790 val = REG_RD(bp, MISC_REG_CHIP_REV);
7791 id |= ((val & 0xf) << 12);
7792 val = REG_RD(bp, MISC_REG_CHIP_METAL);
7793 id |= ((val & 0xff) << 4);
5a40e08e 7794 val = REG_RD(bp, MISC_REG_BOND_ID);
34f80b04
EG		 7795 id |= (val & 0xf);
7796 bp->common.chip_id = id;
523224a3
DK		 7797
7798 /* Set doorbell size */
7799 bp->db_size = (1 << BNX2X_DB_SHIFT);
7800
f2e0899f
DK		 7801 if (CHIP_IS_E2(bp)) {
7802 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
7803 if ((val & 1) == 0)
7804 val = REG_RD(bp, MISC_REG_PORT4MODE_EN);
7805 else
7806 val = (val >> 1) & 1;
7807 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" :
7808 "2_PORT_MODE");
7809 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE :
7810 CHIP_2_PORT_MODE;
7811
7812 if (CHIP_MODE_IS_4_PORT(bp))
7813 bp->pfid = (bp->pf_num >> 1); /* 0..3 */
7814 else
7815 bp->pfid = (bp->pf_num & 0x6); /* 0, 2, 4, 6 */
7816 } else {
7817 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */
7818 bp->pfid = bp->pf_num; /* 0..7 */
7819 }
7820
523224a3
DK		 7821 /*
7822 * set base FW non-default (fast path) status block id, this value is
7823 * used to initialize the fw_sb_id saved on the fp/queue structure to
7824 * determine the id used by the FW.
7825 */
f2e0899f
DK		 7826 if (CHIP_IS_E1x(bp))
7827 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x;
7828 else /* E2 */
7829 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E2;
7830
7831 bp->link_params.chip_id = bp->common.chip_id;
7832 BNX2X_DEV_INFO("chip ID is 0x%x\n", id);
523224a3 7833
1c06328c
EG		 7834 val = (REG_RD(bp, 0x2874) & 0x55);
7835 if ((bp->common.chip_id & 0x1) ||
7836 (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) {
7837 bp->flags |= ONE_PORT_FLAG;
7838 BNX2X_DEV_INFO("single port device\n");
7839 }
7840
34f80b04
EG		 7841 val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);
7842 bp->common.flash_size = (NVRAM_1MB_SIZE <<
7843 (val & MCPR_NVM_CFG4_FLASH_SIZE));
7844 BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
7845 bp->common.flash_size, bp->common.flash_size);
7846
7847 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
f2e0899f
DK		 7848 bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ?
7849 MISC_REG_GENERIC_CR_1 :
7850 MISC_REG_GENERIC_CR_0));
34f80b04 7851 bp->link_params.shmem_base = bp->common.shmem_base;
a22f0788 7852 bp->link_params.shmem2_base = bp->common.shmem2_base;
2691d51d
EG		 7853 BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n",
7854 bp->common.shmem_base, bp->common.shmem2_base);
34f80b04 7855
f2e0899f 7856 if (!bp->common.shmem_base) {
34f80b04
EG		 7857 BNX2X_DEV_INFO("MCP not active\n");
7858 bp->flags |= NO_MCP_FLAG;
7859 return;
7860 }
7861
7862 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
7863 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
7864 != (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
f2e0899f 7865 BNX2X_ERR("BAD MCP validity signature\n");
34f80b04
EG		 7866
7867 bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
35b19ba5 7868 BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config);
34f80b04
EG		 7869
7870 bp->link_params.hw_led_mode = ((bp->common.hw_config &
7871 SHARED_HW_CFG_LED_MODE_MASK) >>
7872 SHARED_HW_CFG_LED_MODE_SHIFT);
7873
c2c8b03e
EG		 7874 bp->link_params.feature_config_flags = 0;
7875 val = SHMEM_RD(bp, dev_info.shared_feature_config.config);
7876 if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED)
7877 bp->link_params.feature_config_flags |=
7878 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
7879 else
7880 bp->link_params.feature_config_flags &=
7881 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
7882
34f80b04
EG		 7883 val = SHMEM_RD(bp, dev_info.bc_rev) >> 8;
7884 bp->common.bc_ver = val;
7885 BNX2X_DEV_INFO("bc_ver %X\n", val);
7886 if (val < BNX2X_BC_VER) {
7887 /* for now only warn
7888 * later we might need to enforce this */
f2e0899f
DK		 7889 BNX2X_ERR("This driver needs bc_ver %X but found %X, "
7890 "please upgrade BC\n", BNX2X_BC_VER, val);
34f80b04 7891 }
4d295db0 7892 bp->link_params.feature_config_flags |=
a22f0788 7893 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ?
f85582f8
DK		 7894 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0;
7895
a22f0788
YR		 7896 bp->link_params.feature_config_flags |=
7897 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ?
7898 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0;
72ce58c3 7899
f9a3ebbe
DK		 7900 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_PMC, &pmc);
7901 bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG;
7902
72ce58c3 7903 BNX2X_DEV_INFO("%sWoL capable\n",
f5372251 7904 (bp->flags & NO_WOL_FLAG) ? "not " : "");
34f80b04
EG		 7905
7906 val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
7907 val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
7908 val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]);
7909 val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]);
7910
cdaa7cb8
VZ		 7911 dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n",
7912 val, val2, val3, val4);
34f80b04
EG		 7913}
7914
f2e0899f
DK		 7915#define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
7916#define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
7917
7918static void __devinit bnx2x_get_igu_cam_info(struct bnx2x *bp)
7919{
7920 int pfid = BP_FUNC(bp);
7921 int vn = BP_E1HVN(bp);
7922 int igu_sb_id;
7923 u32 val;
7924 u8 fid;
7925
7926 bp->igu_base_sb = 0xff;
7927 bp->igu_sb_cnt = 0;
7928 if (CHIP_INT_MODE_IS_BC(bp)) {
7929 bp->igu_sb_cnt = min_t(u8, FP_SB_MAX_E1x,
ec6ba945 7930 NUM_IGU_SB_REQUIRED(bp->l2_cid_count));
f2e0899f
DK		 7931
7932 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) *
7933 FP_SB_MAX_E1x;
7934
7935 bp->igu_dsb_id = E1HVN_MAX * FP_SB_MAX_E1x +
7936 (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn);
7937
7938 return;
7939 }
7940
7941 /* IGU in normal mode - read CAM */
7942 for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE;
7943 igu_sb_id++) {
7944 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
7945 if (!(val & IGU_REG_MAPPING_MEMORY_VALID))
7946 continue;
7947 fid = IGU_FID(val);
7948 if ((fid & IGU_FID_ENCODE_IS_PF)) {
7949 if ((fid & IGU_FID_PF_NUM_MASK) != pfid)
7950 continue;
7951 if (IGU_VEC(val) == 0)
7952 /* default status block */
7953 bp->igu_dsb_id = igu_sb_id;
7954 else {
7955 if (bp->igu_base_sb == 0xff)
7956 bp->igu_base_sb = igu_sb_id;
7957 bp->igu_sb_cnt++;
7958 }
7959 }
7960 }
ec6ba945
VZ		 7961 bp->igu_sb_cnt = min_t(u8, bp->igu_sb_cnt,
7962 NUM_IGU_SB_REQUIRED(bp->l2_cid_count));
f2e0899f
DK		 7963 if (bp->igu_sb_cnt == 0)
7964 BNX2X_ERR("CAM configuration error\n");
7965}
7966
34f80b04
EG		 7967static void __devinit bnx2x_link_settings_supported(struct bnx2x *bp,
7968 u32 switch_cfg)
a2fbb9ea 7969{
a22f0788
YR		 7970 int cfg_size = 0, idx, port = BP_PORT(bp);
7971
7972 /* Aggregation of supported attributes of all external phys */
7973 bp->port.supported[0] = 0;
7974 bp->port.supported[1] = 0;
b7737c9b
YR		 7975 switch (bp->link_params.num_phys) {
7976 case 1:
a22f0788
YR		 7977 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported;
7978 cfg_size = 1;
7979 break;
b7737c9b 7980 case 2:
a22f0788
YR		 7981 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported;
7982 cfg_size = 1;
7983 break;
7984 case 3:
7985 if (bp->link_params.multi_phy_config &
7986 PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
7987 bp->port.supported[1] =
7988 bp->link_params.phy[EXT_PHY1].supported;
7989 bp->port.supported[0] =
7990 bp->link_params.phy[EXT_PHY2].supported;
7991 } else {
7992 bp->port.supported[0] =
7993 bp->link_params.phy[EXT_PHY1].supported;
7994 bp->port.supported[1] =
7995 bp->link_params.phy[EXT_PHY2].supported;
7996 }
7997 cfg_size = 2;
7998 break;
b7737c9b 7999 }
a2fbb9ea 8000
a22f0788 8001 if (!(bp->port.supported[0] || bp->port.supported[1])) {
b7737c9b 8002 BNX2X_ERR("NVRAM config error. BAD phy config."
a22f0788 8003 "PHY1 config 0x%x, PHY2 config 0x%x\n",
b7737c9b 8004 SHMEM_RD(bp,
a22f0788
YR		 8005 dev_info.port_hw_config[port].external_phy_config),
8006 SHMEM_RD(bp,
8007 dev_info.port_hw_config[port].external_phy_config2));
a2fbb9ea 8008 return;
f85582f8 8009 }
a2fbb9ea 8010
b7737c9b
YR		 8011 switch (switch_cfg) {
8012 case SWITCH_CFG_1G:
34f80b04
EG		 8013 bp->port.phy_addr = REG_RD(bp, NIG_REG_SERDES0_CTRL_PHY_ADDR +
8014 port*0x10);
8015 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
a2fbb9ea
ET		 8016 break;
8017
8018 case SWITCH_CFG_10G:
34f80b04
EG		 8019 bp->port.phy_addr = REG_RD(bp, NIG_REG_XGXS0_CTRL_PHY_ADDR +
8020 port*0x18);
8021 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
a2fbb9ea
ET		 8022 break;
8023
8024 default:
8025 BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
a22f0788 8026 bp->port.link_config[0]);
a2fbb9ea
ET		 8027 return;
8028 }
a22f0788
YR		 8029 /* mask what we support according to speed_cap_mask per configuration */
8030 for (idx = 0; idx < cfg_size; idx++) {
8031 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 8032 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF))
a22f0788 8033 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half;
a2fbb9ea 8034
a22f0788 8035 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 8036 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL))
a22f0788 8037 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full;
a2fbb9ea 8038
a22f0788 8039 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 8040 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))
a22f0788 8041 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half;
a2fbb9ea 8042
a22f0788 8043 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 8044 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL))
a22f0788 8045 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full;
a2fbb9ea 8046
a22f0788 8047 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 8048 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))
a22f0788 8049 bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half |
f85582f8 8050 SUPPORTED_1000baseT_Full);
a2fbb9ea 8051
a22f0788 8052 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 8053 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
a22f0788 8054 bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full;
a2fbb9ea 8055
a22f0788 8056 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 8057 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G))
a22f0788
YR		 8058 bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full;
8059
8060 }
a2fbb9ea 8061
a22f0788
YR		 8062 BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0],
8063 bp->port.supported[1]);
a2fbb9ea
ET		 8064}
8065
34f80b04 8066static void __devinit bnx2x_link_settings_requested(struct bnx2x *bp)
a2fbb9ea 8067{
a22f0788
YR		 8068 u32 link_config, idx, cfg_size = 0;
8069 bp->port.advertising[0] = 0;
8070 bp->port.advertising[1] = 0;
8071 switch (bp->link_params.num_phys) {
8072 case 1:
8073 case 2:
8074 cfg_size = 1;
8075 break;
8076 case 3:
8077 cfg_size = 2;
8078 break;
8079 }
8080 for (idx = 0; idx < cfg_size; idx++) {
8081 bp->link_params.req_duplex[idx] = DUPLEX_FULL;
8082 link_config = bp->port.link_config[idx];
8083 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
f85582f8 8084 case PORT_FEATURE_LINK_SPEED_AUTO:
a22f0788
YR		 8085 if (bp->port.supported[idx] & SUPPORTED_Autoneg) {
8086 bp->link_params.req_line_speed[idx] =
8087 SPEED_AUTO_NEG;
8088 bp->port.advertising[idx] |=
8089 bp->port.supported[idx];
f85582f8
DK		 8090 } else {
8091 /* force 10G, no AN */
a22f0788
YR		 8092 bp->link_params.req_line_speed[idx] =
8093 SPEED_10000;
8094 bp->port.advertising[idx] |=
8095 (ADVERTISED_10000baseT_Full |
f85582f8 8096 ADVERTISED_FIBRE);
a22f0788 8097 continue;
f85582f8
DK		 8098 }
8099 break;
a2fbb9ea 8100
f85582f8 8101 case PORT_FEATURE_LINK_SPEED_10M_FULL:
a22f0788
YR		 8102 if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) {
8103 bp->link_params.req_line_speed[idx] =
8104 SPEED_10;
8105 bp->port.advertising[idx] |=
8106 (ADVERTISED_10baseT_Full |
f85582f8
DK		 8107 ADVERTISED_TP);
8108 } else {
8109 BNX2X_ERROR("NVRAM config error. "
8110 "Invalid link_config 0x%x"
8111 " speed_cap_mask 0x%x\n",
8112 link_config,
a22f0788 8113 bp->link_params.speed_cap_mask[idx]);
f85582f8
DK		 8114 return;
8115 }
8116 break;
a2fbb9ea 8117
f85582f8 8118 case PORT_FEATURE_LINK_SPEED_10M_HALF:
a22f0788
YR		 8119 if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) {
8120 bp->link_params.req_line_speed[idx] =
8121 SPEED_10;
8122 bp->link_params.req_duplex[idx] =
8123 DUPLEX_HALF;
8124 bp->port.advertising[idx] |=
8125 (ADVERTISED_10baseT_Half |
f85582f8
DK		 8126 ADVERTISED_TP);
8127 } else {
8128 BNX2X_ERROR("NVRAM config error. "
8129 "Invalid link_config 0x%x"
8130 " speed_cap_mask 0x%x\n",
8131 link_config,
8132 bp->link_params.speed_cap_mask[idx]);
8133 return;
8134 }
8135 break;
a2fbb9ea 8136
f85582f8
DK		 8137 case PORT_FEATURE_LINK_SPEED_100M_FULL:
8138 if (bp->port.supported[idx] &
8139 SUPPORTED_100baseT_Full) {
a22f0788
YR		 8140 bp->link_params.req_line_speed[idx] =
8141 SPEED_100;
8142 bp->port.advertising[idx] |=
8143 (ADVERTISED_100baseT_Full |
f85582f8
DK		 8144 ADVERTISED_TP);
8145 } else {
8146 BNX2X_ERROR("NVRAM config error. "
8147 "Invalid link_config 0x%x"
8148 " speed_cap_mask 0x%x\n",
8149 link_config,
8150 bp->link_params.speed_cap_mask[idx]);
8151 return;
8152 }
8153 break;
a2fbb9ea 8154
f85582f8
DK		 8155 case PORT_FEATURE_LINK_SPEED_100M_HALF:
8156 if (bp->port.supported[idx] &
8157 SUPPORTED_100baseT_Half) {
8158 bp->link_params.req_line_speed[idx] =
8159 SPEED_100;
8160 bp->link_params.req_duplex[idx] =
8161 DUPLEX_HALF;
a22f0788
YR		 8162 bp->port.advertising[idx] |=
8163 (ADVERTISED_100baseT_Half |
f85582f8
DK		 8164 ADVERTISED_TP);
8165 } else {
8166 BNX2X_ERROR("NVRAM config error. "
cdaa7cb8
VZ		 8167 "Invalid link_config 0x%x"
8168 " speed_cap_mask 0x%x\n",
a22f0788
YR		 8169 link_config,
8170 bp->link_params.speed_cap_mask[idx]);
f85582f8
DK		 8171 return;
8172 }
8173 break;
a2fbb9ea 8174
f85582f8 8175 case PORT_FEATURE_LINK_SPEED_1G:
a22f0788
YR		 8176 if (bp->port.supported[idx] &
8177 SUPPORTED_1000baseT_Full) {
8178 bp->link_params.req_line_speed[idx] =
8179 SPEED_1000;
8180 bp->port.advertising[idx] |=
8181 (ADVERTISED_1000baseT_Full |
f85582f8
DK		 8182 ADVERTISED_TP);
8183 } else {
8184 BNX2X_ERROR("NVRAM config error. "
cdaa7cb8
VZ		 8185 "Invalid link_config 0x%x"
8186 " speed_cap_mask 0x%x\n",
a22f0788
YR		 8187 link_config,
8188 bp->link_params.speed_cap_mask[idx]);
f85582f8
DK		 8189 return;
8190 }
8191 break;
a2fbb9ea 8192
f85582f8 8193 case PORT_FEATURE_LINK_SPEED_2_5G:
a22f0788
YR		 8194 if (bp->port.supported[idx] &
8195 SUPPORTED_2500baseX_Full) {
8196 bp->link_params.req_line_speed[idx] =
8197 SPEED_2500;
8198 bp->port.advertising[idx] |=
8199 (ADVERTISED_2500baseX_Full |
34f80b04 8200 ADVERTISED_TP);
f85582f8
DK		 8201 } else {
8202 BNX2X_ERROR("NVRAM config error. "
cdaa7cb8
VZ		 8203 "Invalid link_config 0x%x"
8204 " speed_cap_mask 0x%x\n",
a22f0788 8205 link_config,
f85582f8
DK		 8206 bp->link_params.speed_cap_mask[idx]);
8207 return;
8208 }
8209 break;
a2fbb9ea 8210
f85582f8
DK		 8211 case PORT_FEATURE_LINK_SPEED_10G_CX4:
8212 case PORT_FEATURE_LINK_SPEED_10G_KX4:
8213 case PORT_FEATURE_LINK_SPEED_10G_KR:
a22f0788
YR		 8214 if (bp->port.supported[idx] &
8215 SUPPORTED_10000baseT_Full) {
8216 bp->link_params.req_line_speed[idx] =
8217 SPEED_10000;
8218 bp->port.advertising[idx] |=
8219 (ADVERTISED_10000baseT_Full |
34f80b04 8220 ADVERTISED_FIBRE);
f85582f8
DK		 8221 } else {
8222 BNX2X_ERROR("NVRAM config error. "
cdaa7cb8
VZ		 8223 "Invalid link_config 0x%x"
8224 " speed_cap_mask 0x%x\n",
a22f0788 8225 link_config,
f85582f8
DK		 8226 bp->link_params.speed_cap_mask[idx]);
8227 return;
8228 }
8229 break;
a2fbb9ea 8230
f85582f8
DK		 8231 default:
8232 BNX2X_ERROR("NVRAM config error. "
8233 "BAD link speed link_config 0x%x\n",
8234 link_config);
8235 bp->link_params.req_line_speed[idx] =
8236 SPEED_AUTO_NEG;
8237 bp->port.advertising[idx] =
8238 bp->port.supported[idx];
8239 break;
8240 }
a2fbb9ea 8241
a22f0788 8242 bp->link_params.req_flow_ctrl[idx] = (link_config &
34f80b04 8243 PORT_FEATURE_FLOW_CONTROL_MASK);
a22f0788
YR		 8244 if ((bp->link_params.req_flow_ctrl[idx] ==
8245 BNX2X_FLOW_CTRL_AUTO) &&
8246 !(bp->port.supported[idx] & SUPPORTED_Autoneg)) {
8247 bp->link_params.req_flow_ctrl[idx] =
8248 BNX2X_FLOW_CTRL_NONE;
8249 }
a2fbb9ea 8250
a22f0788
YR		 8251 BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl"
8252 " 0x%x advertising 0x%x\n",
8253 bp->link_params.req_line_speed[idx],
8254 bp->link_params.req_duplex[idx],
8255 bp->link_params.req_flow_ctrl[idx],
8256 bp->port.advertising[idx]);
8257 }
a2fbb9ea
ET		 8258}
8259
e665bfda
MC		 8260static void __devinit bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi)
8261{
8262 mac_hi = cpu_to_be16(mac_hi);
8263 mac_lo = cpu_to_be32(mac_lo);
8264 memcpy(mac_buf, &mac_hi, sizeof(mac_hi));
8265 memcpy(mac_buf + sizeof(mac_hi), &mac_lo, sizeof(mac_lo));
8266}
8267
34f80b04 8268static void __devinit bnx2x_get_port_hwinfo(struct bnx2x *bp)
a2fbb9ea 8269{
34f80b04 8270 int port = BP_PORT(bp);
589abe3a 8271 u32 config;
6f38ad93 8272 u32 ext_phy_type, ext_phy_config;
a2fbb9ea 8273
c18487ee 8274 bp->link_params.bp = bp;
34f80b04 8275 bp->link_params.port = port;
c18487ee 8276
c18487ee 8277 bp->link_params.lane_config =
a2fbb9ea 8278 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
4d295db0 8279
a22f0788 8280 bp->link_params.speed_cap_mask[0] =
a2fbb9ea
ET		 8281 SHMEM_RD(bp,
8282 dev_info.port_hw_config[port].speed_capability_mask);
a22f0788
YR		 8283 bp->link_params.speed_cap_mask[1] =
8284 SHMEM_RD(bp,
8285 dev_info.port_hw_config[port].speed_capability_mask2);
8286 bp->port.link_config[0] =
a2fbb9ea
ET		 8287 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
8288
a22f0788
YR		 8289 bp->port.link_config[1] =
8290 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2);
c2c8b03e 8291
a22f0788
YR		 8292 bp->link_params.multi_phy_config =
8293 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config);
3ce2c3f9
EG		 8294 /* If the device is capable of WoL, set the default state according
8295 * to the HW
8296 */
4d295db0 8297 config = SHMEM_RD(bp, dev_info.port_feature_config[port].config);
3ce2c3f9
EG		 8298 bp->wol = (!(bp->flags & NO_WOL_FLAG) &&
8299 (config & PORT_FEATURE_WOL_ENABLED));
8300
f85582f8 8301 BNX2X_DEV_INFO("lane_config 0x%08x "
a22f0788 8302 "speed_cap_mask0 0x%08x link_config0 0x%08x\n",
c18487ee 8303 bp->link_params.lane_config,
a22f0788
YR		 8304 bp->link_params.speed_cap_mask[0],
8305 bp->port.link_config[0]);
a2fbb9ea 8306
a22f0788 8307 bp->link_params.switch_cfg = (bp->port.link_config[0] &
f85582f8 8308 PORT_FEATURE_CONNECTED_SWITCH_MASK);
b7737c9b 8309 bnx2x_phy_probe(&bp->link_params);
c18487ee 8310 bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg);
a2fbb9ea
ET		 8311
8312 bnx2x_link_settings_requested(bp);
8313
01cd4528
EG		 8314 /*
8315 * If connected directly, work with the internal PHY, otherwise, work
8316 * with the external PHY
8317 */
b7737c9b
YR		 8318 ext_phy_config =
8319 SHMEM_RD(bp,
8320 dev_info.port_hw_config[port].external_phy_config);
8321 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
01cd4528 8322 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
b7737c9b 8323 bp->mdio.prtad = bp->port.phy_addr;
01cd4528
EG		 8324
8325 else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
8326 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
8327 bp->mdio.prtad =
b7737c9b 8328 XGXS_EXT_PHY_ADDR(ext_phy_config);
5866df6d
YR		 8329
8330 /*
8331 * Check if hw lock is required to access MDC/MDIO bus to the PHY(s)
8332 * In MF mode, it is set to cover self test cases
8333 */
8334 if (IS_MF(bp))
8335 bp->port.need_hw_lock = 1;
8336 else
8337 bp->port.need_hw_lock = bnx2x_hw_lock_required(bp,
8338 bp->common.shmem_base,
8339 bp->common.shmem2_base);
0793f83f 8340}
01cd4528 8341
2ba45142
VZ		 8342#ifdef BCM_CNIC
8343static void __devinit bnx2x_get_cnic_info(struct bnx2x *bp)
8344{
8345 u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
8346 drv_lic_key[BP_PORT(bp)].max_iscsi_conn);
8347 u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
8348 drv_lic_key[BP_PORT(bp)].max_fcoe_conn);
8349
8350 /* Get the number of maximum allowed iSCSI and FCoE connections */
8351 bp->cnic_eth_dev.max_iscsi_conn =
8352 (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >>
8353 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT;
8354
8355 bp->cnic_eth_dev.max_fcoe_conn =
8356 (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >>
8357 BNX2X_MAX_FCOE_INIT_CONN_SHIFT;
8358
8359 BNX2X_DEV_INFO("max_iscsi_conn 0x%x max_fcoe_conn 0x%x\n",
8360 bp->cnic_eth_dev.max_iscsi_conn,
8361 bp->cnic_eth_dev.max_fcoe_conn);
8362
8363 /* If mamimum allowed number of connections is zero -
8364 * disable the feature.
8365 */
8366 if (!bp->cnic_eth_dev.max_iscsi_conn)
8367 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
8368
8369 if (!bp->cnic_eth_dev.max_fcoe_conn)
8370 bp->flags |= NO_FCOE_FLAG;
8371}
8372#endif
8373
0793f83f
DK		 8374static void __devinit bnx2x_get_mac_hwinfo(struct bnx2x *bp)
8375{
8376 u32 val, val2;
8377 int func = BP_ABS_FUNC(bp);
8378 int port = BP_PORT(bp);
2ba45142
VZ		 8379#ifdef BCM_CNIC
8380 u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac;
8381 u8 *fip_mac = bp->fip_mac;
8382#endif
0793f83f
DK		 8383
8384 if (BP_NOMCP(bp)) {
8385 BNX2X_ERROR("warning: random MAC workaround active\n");
8386 random_ether_addr(bp->dev->dev_addr);
8387 } else if (IS_MF(bp)) {
8388 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
8389 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower);
8390 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) &&
8391 (val != FUNC_MF_CFG_LOWERMAC_DEFAULT))
8392 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
37b091ba
MC		 8393
8394#ifdef BCM_CNIC
2ba45142
VZ		 8395 /* iSCSI and FCoE NPAR MACs: if there is no either iSCSI or
8396 * FCoE MAC then the appropriate feature should be disabled.
8397 */
0793f83f
DK		 8398 if (IS_MF_SI(bp)) {
8399 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
8400 if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
8401 val2 = MF_CFG_RD(bp, func_ext_config[func].
8402 iscsi_mac_addr_upper);
8403 val = MF_CFG_RD(bp, func_ext_config[func].
8404 iscsi_mac_addr_lower);
2ba45142
VZ		 8405 BNX2X_DEV_INFO("Read iSCSI MAC: "
8406 "0x%x:0x%04x\n", val2, val);
8407 bnx2x_set_mac_buf(iscsi_mac, val, val2);
2ba45142
VZ		 8408 } else
8409 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
8410
8411 if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
8412 val2 = MF_CFG_RD(bp, func_ext_config[func].
8413 fcoe_mac_addr_upper);
8414 val = MF_CFG_RD(bp, func_ext_config[func].
8415 fcoe_mac_addr_lower);
8416 BNX2X_DEV_INFO("Read FCoE MAC to "
8417 "0x%x:0x%04x\n", val2, val);
8418 bnx2x_set_mac_buf(fip_mac, val, val2);
8419
2ba45142
VZ		 8420 } else
8421 bp->flags |= NO_FCOE_FLAG;
0793f83f 8422 }
37b091ba 8423#endif
0793f83f
DK		 8424 } else {
8425 /* in SF read MACs from port configuration */
8426 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
8427 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
8428 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
8429
8430#ifdef BCM_CNIC
8431 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
8432 iscsi_mac_upper);
8433 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
8434 iscsi_mac_lower);
2ba45142 8435 bnx2x_set_mac_buf(iscsi_mac, val, val2);
0793f83f
DK		 8436#endif
8437 }
8438
8439 memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN);
8440 memcpy(bp->dev->perm_addr, bp->dev->dev_addr, ETH_ALEN);
8441
ec6ba945 8442#ifdef BCM_CNIC
2ba45142 8443 /* Set the FCoE MAC in modes other then MF_SI */
ec6ba945
VZ		 8444 if (!CHIP_IS_E1x(bp)) {
8445 if (IS_MF_SD(bp))
2ba45142
VZ		 8446 memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN);
8447 else if (!IS_MF(bp))
8448 memcpy(fip_mac, iscsi_mac, ETH_ALEN);
ec6ba945 8449 }
426b9241
DK		 8450
8451 /* Disable iSCSI if MAC configuration is
8452 * invalid.
8453 */
8454 if (!is_valid_ether_addr(iscsi_mac)) {
8455 bp->flags |= NO_ISCSI_FLAG;
8456 memset(iscsi_mac, 0, ETH_ALEN);
8457 }
8458
8459 /* Disable FCoE if MAC configuration is
8460 * invalid.
8461 */
8462 if (!is_valid_ether_addr(fip_mac)) {
8463 bp->flags |= NO_FCOE_FLAG;
8464 memset(bp->fip_mac, 0, ETH_ALEN);
8465 }
ec6ba945 8466#endif
34f80b04
EG		 8467}
8468
8469static int __devinit bnx2x_get_hwinfo(struct bnx2x *bp)
8470{
0793f83f 8471 int /*abs*/func = BP_ABS_FUNC(bp);
b8ee8328 8472 int vn;
0793f83f 8473 u32 val = 0;
34f80b04 8474 int rc = 0;
a2fbb9ea 8475
34f80b04 8476 bnx2x_get_common_hwinfo(bp);
a2fbb9ea 8477
f2e0899f
DK		 8478 if (CHIP_IS_E1x(bp)) {
8479 bp->common.int_block = INT_BLOCK_HC;
8480
8481 bp->igu_dsb_id = DEF_SB_IGU_ID;
8482 bp->igu_base_sb = 0;
ec6ba945
VZ		 8483 bp->igu_sb_cnt = min_t(u8, FP_SB_MAX_E1x,
8484 NUM_IGU_SB_REQUIRED(bp->l2_cid_count));
f2e0899f
DK		 8485 } else {
8486 bp->common.int_block = INT_BLOCK_IGU;
8487 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
8488 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
8489 DP(NETIF_MSG_PROBE, "IGU Backward Compatible Mode\n");
8490 bp->common.int_block |= INT_BLOCK_MODE_BW_COMP;
8491 } else
8492 DP(NETIF_MSG_PROBE, "IGU Normal Mode\n");
523224a3 8493
f2e0899f
DK		 8494 bnx2x_get_igu_cam_info(bp);
8495
8496 }
8497 DP(NETIF_MSG_PROBE, "igu_dsb_id %d igu_base_sb %d igu_sb_cnt %d\n",
8498 bp->igu_dsb_id, bp->igu_base_sb, bp->igu_sb_cnt);
8499
8500 /*
8501 * Initialize MF configuration
8502 */
523224a3 8503
fb3bff17
DK		 8504 bp->mf_ov = 0;
8505 bp->mf_mode = 0;
f2e0899f 8506 vn = BP_E1HVN(bp);
0793f83f 8507
f2e0899f 8508 if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) {
0793f83f
DK		 8509 DP(NETIF_MSG_PROBE,
8510 "shmem2base 0x%x, size %d, mfcfg offset %d\n",
8511 bp->common.shmem2_base, SHMEM2_RD(bp, size),
8512 (u32)offsetof(struct shmem2_region, mf_cfg_addr));
f2e0899f
DK		 8513 if (SHMEM2_HAS(bp, mf_cfg_addr))
8514 bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr);
8515 else
8516 bp->common.mf_cfg_base = bp->common.shmem_base +
523224a3
DK		 8517 offsetof(struct shmem_region, func_mb) +
8518 E1H_FUNC_MAX * sizeof(struct drv_func_mb);
0793f83f
DK		 8519 /*
8520 * get mf configuration:
25985edc 8521 * 1. existence of MF configuration
0793f83f
DK		 8522 * 2. MAC address must be legal (check only upper bytes)
8523 * for Switch-Independent mode;
8524 * OVLAN must be legal for Switch-Dependent mode
8525 * 3. SF_MODE configures specific MF mode
8526 */
8527 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
8528 /* get mf configuration */
8529 val = SHMEM_RD(bp,
8530 dev_info.shared_feature_config.config);
8531 val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK;
8532
8533 switch (val) {
8534 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
8535 val = MF_CFG_RD(bp, func_mf_config[func].
8536 mac_upper);
8537 /* check for legal mac (upper bytes)*/
8538 if (val != 0xffff) {
8539 bp->mf_mode = MULTI_FUNCTION_SI;
8540 bp->mf_config[vn] = MF_CFG_RD(bp,
8541 func_mf_config[func].config);
8542 } else
8543 DP(NETIF_MSG_PROBE, "illegal MAC "
8544 "address for SI\n");
8545 break;
8546 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
8547 /* get OV configuration */
8548 val = MF_CFG_RD(bp,
8549 func_mf_config[FUNC_0].e1hov_tag);
8550 val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
8551
8552 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
8553 bp->mf_mode = MULTI_FUNCTION_SD;
8554 bp->mf_config[vn] = MF_CFG_RD(bp,
8555 func_mf_config[func].config);
8556 } else
8557 DP(NETIF_MSG_PROBE, "illegal OV for "
8558 "SD\n");
8559 break;
8560 default:
8561 /* Unknown configuration: reset mf_config */
8562 bp->mf_config[vn] = 0;
25985edc 8563 DP(NETIF_MSG_PROBE, "Unknown MF mode 0x%x\n",
0793f83f
DK		 8564 val);
8565 }
8566 }
a2fbb9ea 8567
2691d51d 8568 BNX2X_DEV_INFO("%s function mode\n",
fb3bff17 8569 IS_MF(bp) ? "multi" : "single");
2691d51d 8570
0793f83f
DK		 8571 switch (bp->mf_mode) {
8572 case MULTI_FUNCTION_SD:
8573 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
8574 FUNC_MF_CFG_E1HOV_TAG_MASK;
2691d51d 8575 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
fb3bff17 8576 bp->mf_ov = val;
0793f83f
DK		 8577 BNX2X_DEV_INFO("MF OV for func %d is %d"
8578 " (0x%04x)\n", func,
8579 bp->mf_ov, bp->mf_ov);
2691d51d 8580 } else {
0793f83f
DK		 8581 BNX2X_ERR("No valid MF OV for func %d,"
8582 " aborting\n", func);
34f80b04
EG		 8583 rc = -EPERM;
8584 }
0793f83f
DK		 8585 break;
8586 case MULTI_FUNCTION_SI:
8587 BNX2X_DEV_INFO("func %d is in MF "
8588 "switch-independent mode\n", func);
8589 break;
8590 default:
8591 if (vn) {
8592 BNX2X_ERR("VN %d in single function mode,"
8593 " aborting\n", vn);
2691d51d
EG		 8594 rc = -EPERM;
8595 }
0793f83f 8596 break;
34f80b04 8597 }
0793f83f 8598
34f80b04 8599 }
a2fbb9ea 8600
f2e0899f
DK		 8601 /* adjust igu_sb_cnt to MF for E1x */
8602 if (CHIP_IS_E1x(bp) && IS_MF(bp))
523224a3
DK		 8603 bp->igu_sb_cnt /= E1HVN_MAX;
8604
f2e0899f
DK		 8605 /*
8606 * adjust E2 sb count: to be removed when FW will support
8607 * more then 16 L2 clients
8608 */
8609#define MAX_L2_CLIENTS 16
8610 if (CHIP_IS_E2(bp))
8611 bp->igu_sb_cnt = min_t(u8, bp->igu_sb_cnt,
8612 MAX_L2_CLIENTS / (IS_MF(bp) ? 4 : 1));
8613
34f80b04
EG		 8614 if (!BP_NOMCP(bp)) {
8615 bnx2x_get_port_hwinfo(bp);
8616
f2e0899f
DK		 8617 bp->fw_seq =
8618 (SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
8619 DRV_MSG_SEQ_NUMBER_MASK);
34f80b04
EG		 8620 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
8621 }
8622
0793f83f
DK		 8623 /* Get MAC addresses */
8624 bnx2x_get_mac_hwinfo(bp);
a2fbb9ea 8625
2ba45142
VZ		 8626#ifdef BCM_CNIC
8627 bnx2x_get_cnic_info(bp);
8628#endif
8629
34f80b04
EG		 8630 return rc;
8631}
8632
34f24c7f
VZ		 8633static void __devinit bnx2x_read_fwinfo(struct bnx2x *bp)
8634{
8635 int cnt, i, block_end, rodi;
8636 char vpd_data[BNX2X_VPD_LEN+1];
8637 char str_id_reg[VENDOR_ID_LEN+1];
8638 char str_id_cap[VENDOR_ID_LEN+1];
8639 u8 len;
8640
8641 cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_data);
8642 memset(bp->fw_ver, 0, sizeof(bp->fw_ver));
8643
8644 if (cnt < BNX2X_VPD_LEN)
8645 goto out_not_found;
8646
8647 i = pci_vpd_find_tag(vpd_data, 0, BNX2X_VPD_LEN,
8648 PCI_VPD_LRDT_RO_DATA);
8649 if (i < 0)
8650 goto out_not_found;
8651
8652
8653 block_end = i + PCI_VPD_LRDT_TAG_SIZE +
8654 pci_vpd_lrdt_size(&vpd_data[i]);
8655
8656 i += PCI_VPD_LRDT_TAG_SIZE;
8657
8658 if (block_end > BNX2X_VPD_LEN)
8659 goto out_not_found;
8660
8661 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
8662 PCI_VPD_RO_KEYWORD_MFR_ID);
8663 if (rodi < 0)
8664 goto out_not_found;
8665
8666 len = pci_vpd_info_field_size(&vpd_data[rodi]);
8667
8668 if (len != VENDOR_ID_LEN)
8669 goto out_not_found;
8670
8671 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
8672
8673 /* vendor specific info */
8674 snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL);
8675 snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL);
8676 if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) ||
8677 !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) {
8678
8679 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
8680 PCI_VPD_RO_KEYWORD_VENDOR0);
8681 if (rodi >= 0) {
8682 len = pci_vpd_info_field_size(&vpd_data[rodi]);
8683
8684 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
8685
8686 if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) {
8687 memcpy(bp->fw_ver, &vpd_data[rodi], len);
8688 bp->fw_ver[len] = ' ';
8689 }
8690 }
8691 return;
8692 }
8693out_not_found:
8694 return;
8695}
8696
34f80b04
EG		 8697static int __devinit bnx2x_init_bp(struct bnx2x *bp)
8698{
f2e0899f 8699 int func;
87942b46 8700 int timer_interval;
34f80b04
EG		 8701 int rc;
8702
da5a662a
VZ		 8703 /* Disable interrupt handling until HW is initialized */
8704 atomic_set(&bp->intr_sem, 1);
e1510706 8705 smp_wmb(); /* Ensure that bp->intr_sem update is SMP-safe */
da5a662a 8706
34f80b04 8707 mutex_init(&bp->port.phy_mutex);
c4ff7cbf 8708 mutex_init(&bp->fw_mb_mutex);
bb7e95c8 8709 spin_lock_init(&bp->stats_lock);
993ac7b5
MC		 8710#ifdef BCM_CNIC
8711 mutex_init(&bp->cnic_mutex);
8712#endif
a2fbb9ea 8713
1cf167f2 8714 INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task);
72fd0718 8715 INIT_DELAYED_WORK(&bp->reset_task, bnx2x_reset_task);
34f80b04
EG		 8716
8717 rc = bnx2x_get_hwinfo(bp);
8718
523224a3
DK		 8719 if (!rc)
8720 rc = bnx2x_alloc_mem_bp(bp);
8721
34f24c7f 8722 bnx2x_read_fwinfo(bp);
f2e0899f
DK		 8723
8724 func = BP_FUNC(bp);
8725
34f80b04
EG		 8726 /* need to reset chip if undi was active */
8727 if (!BP_NOMCP(bp))
8728 bnx2x_undi_unload(bp);
8729
8730 if (CHIP_REV_IS_FPGA(bp))
cdaa7cb8 8731 dev_err(&bp->pdev->dev, "FPGA detected\n");
34f80b04
EG		 8732
8733 if (BP_NOMCP(bp) && (func == 0))
cdaa7cb8
VZ		 8734 dev_err(&bp->pdev->dev, "MCP disabled, "
8735 "must load devices in order!\n");
34f80b04 8736
555f6c78 8737 bp->multi_mode = multi_mode;
5d7cd496 8738 bp->int_mode = int_mode;
555f6c78 8739
7a9b2557
VZ		 8740 /* Set TPA flags */
8741 if (disable_tpa) {
8742 bp->flags &= ~TPA_ENABLE_FLAG;
8743 bp->dev->features &= ~NETIF_F_LRO;
8744 } else {
8745 bp->flags |= TPA_ENABLE_FLAG;
8746 bp->dev->features |= NETIF_F_LRO;
8747 }
5d7cd496 8748 bp->disable_tpa = disable_tpa;
7a9b2557 8749
a18f5128
EG		 8750 if (CHIP_IS_E1(bp))
8751 bp->dropless_fc = 0;
8752 else
8753 bp->dropless_fc = dropless_fc;
8754
8d5726c4 8755 bp->mrrs = mrrs;
7a9b2557 8756
34f80b04 8757 bp->tx_ring_size = MAX_TX_AVAIL;
34f80b04 8758
7d323bfd 8759 /* make sure that the numbers are in the right granularity */
523224a3
DK		 8760 bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR;
8761 bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR;
34f80b04 8762
87942b46
EG		 8763 timer_interval = (CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ);
8764 bp->current_interval = (poll ? poll : timer_interval);
34f80b04
EG		 8765
8766 init_timer(&bp->timer);
8767 bp->timer.expires = jiffies + bp->current_interval;
8768 bp->timer.data = (unsigned long) bp;
8769 bp->timer.function = bnx2x_timer;
8770
785b9b1a 8771 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON);
e4901dde
VZ		 8772 bnx2x_dcbx_init_params(bp);
8773
34f80b04 8774 return rc;
a2fbb9ea
ET		 8775}
8776
a2fbb9ea 8777
de0c62db
DK		 8778/****************************************************************************
8779* General service functions
8780****************************************************************************/
a2fbb9ea 8781
bb2a0f7a 8782/* called with rtnl_lock */
a2fbb9ea
ET		 8783static int bnx2x_open(struct net_device *dev)
8784{
8785 struct bnx2x *bp = netdev_priv(dev);
8786
6eccabb3
EG		 8787 netif_carrier_off(dev);
8788
a2fbb9ea
ET		 8789 bnx2x_set_power_state(bp, PCI_D0);
8790
72fd0718
VZ		 8791 if (!bnx2x_reset_is_done(bp)) {
8792 do {
8793 /* Reset MCP mail box sequence if there is on going
8794 * recovery
8795 */
8796 bp->fw_seq = 0;
8797
8798 /* If it's the first function to load and reset done
8799 * is still not cleared it may mean that. We don't
8800 * check the attention state here because it may have
8801 * already been cleared by a "common" reset but we
8802 * shell proceed with "process kill" anyway.
8803 */
8804 if ((bnx2x_get_load_cnt(bp) == 0) &&
8805 bnx2x_trylock_hw_lock(bp,
8806 HW_LOCK_RESOURCE_RESERVED_08) &&
8807 (!bnx2x_leader_reset(bp))) {
8808 DP(NETIF_MSG_HW, "Recovered in open\n");
8809 break;
8810 }
8811
8812 bnx2x_set_power_state(bp, PCI_D3hot);
8813
8814 printk(KERN_ERR"%s: Recovery flow hasn't been properly"
8815 " completed yet. Try again later. If u still see this"
8816 " message after a few retries then power cycle is"
8817 " required.\n", bp->dev->name);
8818
8819 return -EAGAIN;
8820 } while (0);
8821 }
8822
8823 bp->recovery_state = BNX2X_RECOVERY_DONE;
8824
bb2a0f7a 8825 return bnx2x_nic_load(bp, LOAD_OPEN);
a2fbb9ea
ET		 8826}
8827
bb2a0f7a 8828/* called with rtnl_lock */
a2fbb9ea
ET		 8829static int bnx2x_close(struct net_device *dev)
8830{
a2fbb9ea
ET		 8831 struct bnx2x *bp = netdev_priv(dev);
8832
8833 /* Unload the driver, release IRQs */
bb2a0f7a 8834 bnx2x_nic_unload(bp, UNLOAD_CLOSE);
d3dbfee0 8835 bnx2x_set_power_state(bp, PCI_D3hot);
a2fbb9ea
ET		 8836
8837 return 0;
8838}
8839
6e30dd4e
VZ		 8840#define E1_MAX_UC_LIST 29
8841#define E1H_MAX_UC_LIST 30
8842#define E2_MAX_UC_LIST 14
8843static inline u8 bnx2x_max_uc_list(struct bnx2x *bp)
8844{
8845 if (CHIP_IS_E1(bp))
8846 return E1_MAX_UC_LIST;
8847 else if (CHIP_IS_E1H(bp))
8848 return E1H_MAX_UC_LIST;
8849 else
8850 return E2_MAX_UC_LIST;
8851}
8852
8853
8854static inline u8 bnx2x_uc_list_cam_offset(struct bnx2x *bp)
8855{
8856 if (CHIP_IS_E1(bp))
8857 /* CAM Entries for Port0:
8858 * 0 - prim ETH MAC
8859 * 1 - BCAST MAC
8860 * 2 - iSCSI L2 ring ETH MAC
8861 * 3-31 - UC MACs
8862 *
8863 * Port1 entries are allocated the same way starting from
8864 * entry 32.
8865 */
8866 return 3 + 32 * BP_PORT(bp);
8867 else if (CHIP_IS_E1H(bp)) {
8868 /* CAM Entries:
8869 * 0-7 - prim ETH MAC for each function
8870 * 8-15 - iSCSI L2 ring ETH MAC for each function
8871 * 16 till 255 UC MAC lists for each function
8872 *
8873 * Remark: There is no FCoE support for E1H, thus FCoE related
8874 * MACs are not considered.
8875 */
8876 return E1H_FUNC_MAX * (CAM_ISCSI_ETH_LINE + 1) +
8877 bnx2x_max_uc_list(bp) * BP_FUNC(bp);
8878 } else {
8879 /* CAM Entries (there is a separate CAM per engine):
8880 * 0-4 - prim ETH MAC for each function
8881 * 4-7 - iSCSI L2 ring ETH MAC for each function
8882 * 8-11 - FIP ucast L2 MAC for each function
8883 * 12-15 - ALL_ENODE_MACS mcast MAC for each function
8884 * 16 till 71 UC MAC lists for each function
8885 */
8886 u8 func_idx =
8887 (CHIP_MODE_IS_4_PORT(bp) ? BP_FUNC(bp) : BP_VN(bp));
8888
8889 return E2_FUNC_MAX * (CAM_MAX_PF_LINE + 1) +
8890 bnx2x_max_uc_list(bp) * func_idx;
8891 }
8892}
8893
8894/* set uc list, do not wait as wait implies sleep and
8895 * set_rx_mode can be invoked from non-sleepable context.
8896 *
8897 * Instead we use the same ramrod data buffer each time we need
8898 * to configure a list of addresses, and use the fact that the
8899 * list of MACs is changed in an incremental way and that the
8900 * function is called under the netif_addr_lock. A temporary
8901 * inconsistent CAM configuration (possible in case of very fast
8902 * sequence of add/del/add on the host side) will shortly be
8903 * restored by the handler of the last ramrod.
8904 */
8905static int bnx2x_set_uc_list(struct bnx2x *bp)
8906{
8907 int i = 0, old;
8908 struct net_device *dev = bp->dev;
8909 u8 offset = bnx2x_uc_list_cam_offset(bp);
8910 struct netdev_hw_addr *ha;
8911 struct mac_configuration_cmd *config_cmd = bnx2x_sp(bp, uc_mac_config);
8912 dma_addr_t config_cmd_map = bnx2x_sp_mapping(bp, uc_mac_config);
8913
8914 if (netdev_uc_count(dev) > bnx2x_max_uc_list(bp))
8915 return -EINVAL;
8916
8917 netdev_for_each_uc_addr(ha, dev) {
8918 /* copy mac */
8919 config_cmd->config_table[i].msb_mac_addr =
8920 swab16(*(u16 *)&bnx2x_uc_addr(ha)[0]);
8921 config_cmd->config_table[i].middle_mac_addr =
8922 swab16(*(u16 *)&bnx2x_uc_addr(ha)[2]);
8923 config_cmd->config_table[i].lsb_mac_addr =
8924 swab16(*(u16 *)&bnx2x_uc_addr(ha)[4]);
8925
8926 config_cmd->config_table[i].vlan_id = 0;
8927 config_cmd->config_table[i].pf_id = BP_FUNC(bp);
8928 config_cmd->config_table[i].clients_bit_vector =
8929 cpu_to_le32(1 << BP_L_ID(bp));
8930
8931 SET_FLAG(config_cmd->config_table[i].flags,
8932 MAC_CONFIGURATION_ENTRY_ACTION_TYPE,
8933 T_ETH_MAC_COMMAND_SET);
8934
8935 DP(NETIF_MSG_IFUP,
8936 "setting UCAST[%d] (%04x:%04x:%04x)\n", i,
8937 config_cmd->config_table[i].msb_mac_addr,
8938 config_cmd->config_table[i].middle_mac_addr,
8939 config_cmd->config_table[i].lsb_mac_addr);
8940
8941 i++;
8942
8943 /* Set uc MAC in NIG */
8944 bnx2x_set_mac_in_nig(bp, 1, bnx2x_uc_addr(ha),
8945 LLH_CAM_ETH_LINE + i);
8946 }
8947 old = config_cmd->hdr.length;
8948 if (old > i) {
8949 for (; i < old; i++) {
8950 if (CAM_IS_INVALID(config_cmd->
8951 config_table[i])) {
8952 /* already invalidated */
8953 break;
8954 }
8955 /* invalidate */
8956 SET_FLAG(config_cmd->config_table[i].flags,
8957 MAC_CONFIGURATION_ENTRY_ACTION_TYPE,
8958 T_ETH_MAC_COMMAND_INVALIDATE);
8959 }
8960 }
8961
8962 wmb();
8963
8964 config_cmd->hdr.length = i;
8965 config_cmd->hdr.offset = offset;
8966 config_cmd->hdr.client_id = 0xff;
8967 /* Mark that this ramrod doesn't use bp->set_mac_pending for
8968 * synchronization.
8969 */
8970 config_cmd->hdr.echo = 0;
8971
8972 mb();
8973
8974 return bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_SET_MAC, 0,
8975 U64_HI(config_cmd_map), U64_LO(config_cmd_map), 1);
8976
8977}
8978
8979void bnx2x_invalidate_uc_list(struct bnx2x *bp)
8980{
8981 int i;
8982 struct mac_configuration_cmd *config_cmd = bnx2x_sp(bp, uc_mac_config);
8983 dma_addr_t config_cmd_map = bnx2x_sp_mapping(bp, uc_mac_config);
8984 int ramrod_flags = WAIT_RAMROD_COMMON;
8985 u8 offset = bnx2x_uc_list_cam_offset(bp);
8986 u8 max_list_size = bnx2x_max_uc_list(bp);
8987
8988 for (i = 0; i < max_list_size; i++) {
8989 SET_FLAG(config_cmd->config_table[i].flags,
8990 MAC_CONFIGURATION_ENTRY_ACTION_TYPE,
8991 T_ETH_MAC_COMMAND_INVALIDATE);
8992 bnx2x_set_mac_in_nig(bp, 0, NULL, LLH_CAM_ETH_LINE + 1 + i);
8993 }
8994
8995 wmb();
8996
8997 config_cmd->hdr.length = max_list_size;
8998 config_cmd->hdr.offset = offset;
8999 config_cmd->hdr.client_id = 0xff;
9000 /* We'll wait for a completion this time... */
9001 config_cmd->hdr.echo = 1;
9002
9003 bp->set_mac_pending = 1;
9004
9005 mb();
9006
9007 bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_SET_MAC, 0,
9008 U64_HI(config_cmd_map), U64_LO(config_cmd_map), 1);
9009
9010 /* Wait for a completion */
9011 bnx2x_wait_ramrod(bp, 0, 0, &bp->set_mac_pending,
9012 ramrod_flags);
9013
9014}
9015
9016static inline int bnx2x_set_mc_list(struct bnx2x *bp)
9017{
9018 /* some multicasts */
9019 if (CHIP_IS_E1(bp)) {
9020 return bnx2x_set_e1_mc_list(bp);
9021 } else { /* E1H and newer */
9022 return bnx2x_set_e1h_mc_list(bp);
9023 }
9024}
9025
f5372251 9026/* called with netif_tx_lock from dev_mcast.c */
9f6c9258 9027void bnx2x_set_rx_mode(struct net_device *dev)
34f80b04
EG		 9028{
9029 struct bnx2x *bp = netdev_priv(dev);
9030 u32 rx_mode = BNX2X_RX_MODE_NORMAL;
34f80b04
EG		 9031
9032 if (bp->state != BNX2X_STATE_OPEN) {
9033 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
9034 return;
9035 }
9036
9037 DP(NETIF_MSG_IFUP, "dev->flags = %x\n", dev->flags);
9038
9039 if (dev->flags & IFF_PROMISC)
9040 rx_mode = BNX2X_RX_MODE_PROMISC;
6e30dd4e 9041 else if (dev->flags & IFF_ALLMULTI)
34f80b04 9042 rx_mode = BNX2X_RX_MODE_ALLMULTI;
6e30dd4e
VZ		 9043 else {
9044 /* some multicasts */
9045 if (bnx2x_set_mc_list(bp))
9046 rx_mode = BNX2X_RX_MODE_ALLMULTI;
34f80b04 9047
6e30dd4e
VZ		 9048 /* some unicasts */
9049 if (bnx2x_set_uc_list(bp))
9050 rx_mode = BNX2X_RX_MODE_PROMISC;
34f80b04
EG		 9051 }
9052
9053 bp->rx_mode = rx_mode;
9054 bnx2x_set_storm_rx_mode(bp);
9055}
9056
c18487ee 9057/* called with rtnl_lock */
01cd4528
EG		 9058static int bnx2x_mdio_read(struct net_device *netdev, int prtad,
9059 int devad, u16 addr)
a2fbb9ea 9060{
01cd4528
EG		 9061 struct bnx2x *bp = netdev_priv(netdev);
9062 u16 value;
9063 int rc;
a2fbb9ea 9064
01cd4528
EG		 9065 DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n",
9066 prtad, devad, addr);
a2fbb9ea 9067
01cd4528
EG		 9068 /* The HW expects different devad if CL22 is used */
9069 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
c18487ee 9070
01cd4528 9071 bnx2x_acquire_phy_lock(bp);
e10bc84d 9072 rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value);
01cd4528
EG		 9073 bnx2x_release_phy_lock(bp);
9074 DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc);
a2fbb9ea 9075
01cd4528
EG		 9076 if (!rc)
9077 rc = value;
9078 return rc;
9079}
a2fbb9ea 9080
01cd4528
EG		 9081/* called with rtnl_lock */
9082static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad,
9083 u16 addr, u16 value)
9084{
9085 struct bnx2x *bp = netdev_priv(netdev);
01cd4528
EG		 9086 int rc;
9087
9088 DP(NETIF_MSG_LINK, "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x,"
9089 " value 0x%x\n", prtad, devad, addr, value);
9090
01cd4528
EG		 9091 /* The HW expects different devad if CL22 is used */
9092 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
a2fbb9ea 9093
01cd4528 9094 bnx2x_acquire_phy_lock(bp);
e10bc84d 9095 rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value);
01cd4528
EG		 9096 bnx2x_release_phy_lock(bp);
9097 return rc;
9098}
c18487ee 9099
01cd4528
EG		 9100/* called with rtnl_lock */
9101static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
9102{
9103 struct bnx2x *bp = netdev_priv(dev);
9104 struct mii_ioctl_data *mdio = if_mii(ifr);
a2fbb9ea 9105
01cd4528
EG		 9106 DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
9107 mdio->phy_id, mdio->reg_num, mdio->val_in);
a2fbb9ea 9108
01cd4528
EG		 9109 if (!netif_running(dev))
9110 return -EAGAIN;
9111
9112 return mdio_mii_ioctl(&bp->mdio, mdio, cmd);
a2fbb9ea
ET		 9113}
9114
257ddbda 9115#ifdef CONFIG_NET_POLL_CONTROLLER
a2fbb9ea
ET		 9116static void poll_bnx2x(struct net_device *dev)
9117{
9118 struct bnx2x *bp = netdev_priv(dev);
9119
9120 disable_irq(bp->pdev->irq);
9121 bnx2x_interrupt(bp->pdev->irq, dev);
9122 enable_irq(bp->pdev->irq);
9123}
9124#endif
9125
c64213cd
SH		 9126static const struct net_device_ops bnx2x_netdev_ops = {
9127 .ndo_open = bnx2x_open,
9128 .ndo_stop = bnx2x_close,
9129 .ndo_start_xmit = bnx2x_start_xmit,
8307fa3e 9130 .ndo_select_queue = bnx2x_select_queue,
6e30dd4e 9131 .ndo_set_rx_mode = bnx2x_set_rx_mode,
c64213cd
SH		 9132 .ndo_set_mac_address = bnx2x_change_mac_addr,
9133 .ndo_validate_addr = eth_validate_addr,
9134 .ndo_do_ioctl = bnx2x_ioctl,
9135 .ndo_change_mtu = bnx2x_change_mtu,
66371c44
MM		 9136 .ndo_fix_features = bnx2x_fix_features,
9137 .ndo_set_features = bnx2x_set_features,
c64213cd 9138 .ndo_tx_timeout = bnx2x_tx_timeout,
257ddbda 9139#ifdef CONFIG_NET_POLL_CONTROLLER
c64213cd
SH		 9140 .ndo_poll_controller = poll_bnx2x,
9141#endif
9142};
9143
34f80b04
EG		 9144static int __devinit bnx2x_init_dev(struct pci_dev *pdev,
9145 struct net_device *dev)
a2fbb9ea
ET		 9146{
9147 struct bnx2x *bp;
9148 int rc;
9149
9150 SET_NETDEV_DEV(dev, &pdev->dev);
9151 bp = netdev_priv(dev);
9152
34f80b04
EG		 9153 bp->dev = dev;
9154 bp->pdev = pdev;
a2fbb9ea 9155 bp->flags = 0;
f2e0899f 9156 bp->pf_num = PCI_FUNC(pdev->devfn);
a2fbb9ea
ET		 9157
9158 rc = pci_enable_device(pdev);
9159 if (rc) {
cdaa7cb8
VZ		 9160 dev_err(&bp->pdev->dev,
9161 "Cannot enable PCI device, aborting\n");
a2fbb9ea
ET		 9162 goto err_out;
9163 }
9164
9165 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
cdaa7cb8
VZ		 9166 dev_err(&bp->pdev->dev,
9167 "Cannot find PCI device base address, aborting\n");
a2fbb9ea
ET		 9168 rc = -ENODEV;
9169 goto err_out_disable;
9170 }
9171
9172 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
cdaa7cb8
VZ		 9173 dev_err(&bp->pdev->dev, "Cannot find second PCI device"
9174 " base address, aborting\n");
a2fbb9ea
ET		 9175 rc = -ENODEV;
9176 goto err_out_disable;
9177 }
9178
34f80b04
EG		 9179 if (atomic_read(&pdev->enable_cnt) == 1) {
9180 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
9181 if (rc) {
cdaa7cb8
VZ		 9182 dev_err(&bp->pdev->dev,
9183 "Cannot obtain PCI resources, aborting\n");
34f80b04
EG		 9184 goto err_out_disable;
9185 }
a2fbb9ea 9186
34f80b04
EG		 9187 pci_set_master(pdev);
9188 pci_save_state(pdev);
9189 }
a2fbb9ea
ET		 9190
9191 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
9192 if (bp->pm_cap == 0) {
cdaa7cb8
VZ		 9193 dev_err(&bp->pdev->dev,
9194 "Cannot find power management capability, aborting\n");
a2fbb9ea
ET		 9195 rc = -EIO;
9196 goto err_out_release;
9197 }
9198
9199 bp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
9200 if (bp->pcie_cap == 0) {
cdaa7cb8
VZ		 9201 dev_err(&bp->pdev->dev,
9202 "Cannot find PCI Express capability, aborting\n");
a2fbb9ea
ET		 9203 rc = -EIO;
9204 goto err_out_release;
9205 }
9206
1a983142 9207 if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) == 0) {
a2fbb9ea 9208 bp->flags |= USING_DAC_FLAG;
1a983142 9209 if (dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64)) != 0) {
cdaa7cb8
VZ		 9210 dev_err(&bp->pdev->dev, "dma_set_coherent_mask"
9211 " failed, aborting\n");
a2fbb9ea
ET		 9212 rc = -EIO;
9213 goto err_out_release;
9214 }
9215
1a983142 9216 } else if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)) != 0) {
cdaa7cb8
VZ		 9217 dev_err(&bp->pdev->dev,
9218 "System does not support DMA, aborting\n");
a2fbb9ea
ET		 9219 rc = -EIO;
9220 goto err_out_release;
9221 }
9222
34f80b04
EG		 9223 dev->mem_start = pci_resource_start(pdev, 0);
9224 dev->base_addr = dev->mem_start;
9225 dev->mem_end = pci_resource_end(pdev, 0);
a2fbb9ea
ET		 9226
9227 dev->irq = pdev->irq;
9228
275f165f 9229 bp->regview = pci_ioremap_bar(pdev, 0);
a2fbb9ea 9230 if (!bp->regview) {
cdaa7cb8
VZ		 9231 dev_err(&bp->pdev->dev,
9232 "Cannot map register space, aborting\n");
a2fbb9ea
ET		 9233 rc = -ENOMEM;
9234 goto err_out_release;
9235 }
9236
34f80b04 9237 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2),
523224a3 9238 min_t(u64, BNX2X_DB_SIZE(bp),
34f80b04 9239 pci_resource_len(pdev, 2)));
a2fbb9ea 9240 if (!bp->doorbells) {
cdaa7cb8
VZ		 9241 dev_err(&bp->pdev->dev,
9242 "Cannot map doorbell space, aborting\n");
a2fbb9ea
ET		 9243 rc = -ENOMEM;
9244 goto err_out_unmap;
9245 }
9246
9247 bnx2x_set_power_state(bp, PCI_D0);
9248
34f80b04
EG		 9249 /* clean indirect addresses */
9250 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
9251 PCICFG_VENDOR_ID_OFFSET);
9252 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0 + BP_PORT(bp)*16, 0);
9253 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0 + BP_PORT(bp)*16, 0);
9254 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0 + BP_PORT(bp)*16, 0);
9255 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0 + BP_PORT(bp)*16, 0);
a2fbb9ea 9256
72fd0718
VZ		 9257 /* Reset the load counter */
9258 bnx2x_clear_load_cnt(bp);
9259
34f80b04 9260 dev->watchdog_timeo = TX_TIMEOUT;
a2fbb9ea 9261
c64213cd 9262 dev->netdev_ops = &bnx2x_netdev_ops;
de0c62db 9263 bnx2x_set_ethtool_ops(dev);
5316bc0b 9264
66371c44
MM		 9265 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
9266 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
9267 NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_HW_VLAN_TX;
9268
9269 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
9270 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA;
9271
9272 dev->features |= dev->hw_features | NETIF_F_HW_VLAN_RX;
5316bc0b 9273 if (bp->flags & USING_DAC_FLAG)
66371c44 9274 dev->features |= NETIF_F_HIGHDMA;
a2fbb9ea 9275
98507672 9276#ifdef BCM_DCBNL
785b9b1a
SR		 9277 dev->dcbnl_ops = &bnx2x_dcbnl_ops;
9278#endif
9279
01cd4528
EG		 9280 /* get_port_hwinfo() will set prtad and mmds properly */
9281 bp->mdio.prtad = MDIO_PRTAD_NONE;
9282 bp->mdio.mmds = 0;
9283 bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
9284 bp->mdio.dev = dev;
9285 bp->mdio.mdio_read = bnx2x_mdio_read;
9286 bp->mdio.mdio_write = bnx2x_mdio_write;
9287
a2fbb9ea
ET		 9288 return 0;
9289
9290err_out_unmap:
9291 if (bp->regview) {
9292 iounmap(bp->regview);
9293 bp->regview = NULL;
9294 }
a2fbb9ea
ET		 9295 if (bp->doorbells) {
9296 iounmap(bp->doorbells);
9297 bp->doorbells = NULL;
9298 }
9299
9300err_out_release:
34f80b04
EG		 9301 if (atomic_read(&pdev->enable_cnt) == 1)
9302 pci_release_regions(pdev);
a2fbb9ea
ET		 9303
9304err_out_disable:
9305 pci_disable_device(pdev);
9306 pci_set_drvdata(pdev, NULL);
9307
9308err_out:
9309 return rc;
9310}
9311
37f9ce62
EG		 9312static void __devinit bnx2x_get_pcie_width_speed(struct bnx2x *bp,
9313 int *width, int *speed)
25047950
ET		 9314{
9315 u32 val = REG_RD(bp, PCICFG_OFFSET + PCICFG_LINK_CONTROL);
9316
37f9ce62 9317 *width = (val & PCICFG_LINK_WIDTH) >> PCICFG_LINK_WIDTH_SHIFT;
25047950 9318
37f9ce62
EG		 9319 /* return value of 1=2.5GHz 2=5GHz */
9320 *speed = (val & PCICFG_LINK_SPEED) >> PCICFG_LINK_SPEED_SHIFT;
25047950 9321}
37f9ce62 9322
6891dd25 9323static int bnx2x_check_firmware(struct bnx2x *bp)
94a78b79 9324{
37f9ce62 9325 const struct firmware *firmware = bp->firmware;
94a78b79
VZ		 9326 struct bnx2x_fw_file_hdr *fw_hdr;
9327 struct bnx2x_fw_file_section *sections;
94a78b79 9328 u32 offset, len, num_ops;
37f9ce62 9329 u16 *ops_offsets;
94a78b79 9330 int i;
37f9ce62 9331 const u8 *fw_ver;
94a78b79
VZ		 9332
9333 if (firmware->size < sizeof(struct bnx2x_fw_file_hdr))
9334 return -EINVAL;
9335
9336 fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data;
9337 sections = (struct bnx2x_fw_file_section *)fw_hdr;
9338
9339 /* Make sure none of the offsets and sizes make us read beyond
9340 * the end of the firmware data */
9341 for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) {
9342 offset = be32_to_cpu(sections[i].offset);
9343 len = be32_to_cpu(sections[i].len);
9344 if (offset + len > firmware->size) {
cdaa7cb8
VZ		 9345 dev_err(&bp->pdev->dev,
9346 "Section %d length is out of bounds\n", i);
94a78b79
VZ		 9347 return -EINVAL;
9348 }
9349 }
9350
9351 /* Likewise for the init_ops offsets */
9352 offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset);
9353 ops_offsets = (u16 *)(firmware->data + offset);
9354 num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op);
9355
9356 for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) {
9357 if (be16_to_cpu(ops_offsets[i]) > num_ops) {
cdaa7cb8
VZ		 9358 dev_err(&bp->pdev->dev,
9359 "Section offset %d is out of bounds\n", i);
94a78b79
VZ		 9360 return -EINVAL;
9361 }
9362 }
9363
9364 /* Check FW version */
9365 offset = be32_to_cpu(fw_hdr->fw_version.offset);
9366 fw_ver = firmware->data + offset;
9367 if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) ||
9368 (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) ||
9369 (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) ||
9370 (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) {
cdaa7cb8
VZ		 9371 dev_err(&bp->pdev->dev,
9372 "Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n",
94a78b79
VZ		 9373 fw_ver[0], fw_ver[1], fw_ver[2],
9374 fw_ver[3], BCM_5710_FW_MAJOR_VERSION,
9375 BCM_5710_FW_MINOR_VERSION,
9376 BCM_5710_FW_REVISION_VERSION,
9377 BCM_5710_FW_ENGINEERING_VERSION);
ab6ad5a4 9378 return -EINVAL;
94a78b79
VZ		 9379 }
9380
9381 return 0;
9382}
9383
ab6ad5a4 9384static inline void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
94a78b79 9385{
ab6ad5a4
EG		 9386 const __be32 *source = (const __be32 *)_source;
9387 u32 *target = (u32 *)_target;
94a78b79 9388 u32 i;
94a78b79
VZ		 9389
9390 for (i = 0; i < n/4; i++)
9391 target[i] = be32_to_cpu(source[i]);
9392}
9393
9394/*
9395 Ops array is stored in the following format:
9396 {op(8bit), offset(24bit, big endian), data(32bit, big endian)}
9397 */
ab6ad5a4 9398static inline void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n)
94a78b79 9399{
ab6ad5a4
EG		 9400 const __be32 *source = (const __be32 *)_source;
9401 struct raw_op *target = (struct raw_op *)_target;
94a78b79 9402 u32 i, j, tmp;
94a78b79 9403
ab6ad5a4 9404 for (i = 0, j = 0; i < n/8; i++, j += 2) {
94a78b79
VZ		 9405 tmp = be32_to_cpu(source[j]);
9406 target[i].op = (tmp >> 24) & 0xff;
cdaa7cb8
VZ		 9407 target[i].offset = tmp & 0xffffff;
9408 target[i].raw_data = be32_to_cpu(source[j + 1]);
94a78b79
VZ		 9409 }
9410}
ab6ad5a4 9411
523224a3
DK		 9412/**
9413 * IRO array is stored in the following format:
9414 * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) }
9415 */
9416static inline void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n)
9417{
9418 const __be32 *source = (const __be32 *)_source;
9419 struct iro *target = (struct iro *)_target;
9420 u32 i, j, tmp;
9421
9422 for (i = 0, j = 0; i < n/sizeof(struct iro); i++) {
9423 target[i].base = be32_to_cpu(source[j]);
9424 j++;
9425 tmp = be32_to_cpu(source[j]);
9426 target[i].m1 = (tmp >> 16) & 0xffff;
9427 target[i].m2 = tmp & 0xffff;
9428 j++;
9429 tmp = be32_to_cpu(source[j]);
9430 target[i].m3 = (tmp >> 16) & 0xffff;
9431 target[i].size = tmp & 0xffff;
9432 j++;
9433 }
9434}
9435
ab6ad5a4 9436static inline void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
94a78b79 9437{
ab6ad5a4
EG		 9438 const __be16 *source = (const __be16 *)_source;
9439 u16 *target = (u16 *)_target;
94a78b79 9440 u32 i;
94a78b79
VZ		 9441
9442 for (i = 0; i < n/2; i++)
9443 target[i] = be16_to_cpu(source[i]);
9444}
9445
7995c64e
JP		 9446#define BNX2X_ALLOC_AND_SET(arr, lbl, func) \
9447do { \
9448 u32 len = be32_to_cpu(fw_hdr->arr.len); \
9449 bp->arr = kmalloc(len, GFP_KERNEL); \
9450 if (!bp->arr) { \
9451 pr_err("Failed to allocate %d bytes for "#arr"\n", len); \
9452 goto lbl; \
9453 } \
9454 func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \
9455 (u8 *)bp->arr, len); \
9456} while (0)
94a78b79 9457
6891dd25 9458int bnx2x_init_firmware(struct bnx2x *bp)
94a78b79 9459{
45229b42 9460 const char *fw_file_name;
94a78b79 9461 struct bnx2x_fw_file_hdr *fw_hdr;
45229b42 9462 int rc;
94a78b79 9463
94a78b79 9464 if (CHIP_IS_E1(bp))
45229b42 9465 fw_file_name = FW_FILE_NAME_E1;
cdaa7cb8 9466 else if (CHIP_IS_E1H(bp))
45229b42 9467 fw_file_name = FW_FILE_NAME_E1H;
f2e0899f
DK		 9468 else if (CHIP_IS_E2(bp))
9469 fw_file_name = FW_FILE_NAME_E2;
cdaa7cb8 9470 else {
6891dd25 9471 BNX2X_ERR("Unsupported chip revision\n");
cdaa7cb8
VZ		 9472 return -EINVAL;
9473 }
94a78b79 9474
6891dd25 9475 BNX2X_DEV_INFO("Loading %s\n", fw_file_name);
94a78b79 9476
6891dd25 9477 rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev);
94a78b79 9478 if (rc) {
6891dd25 9479 BNX2X_ERR("Can't load firmware file %s\n", fw_file_name);
94a78b79
VZ		 9480 goto request_firmware_exit;
9481 }
9482
9483 rc = bnx2x_check_firmware(bp);
9484 if (rc) {
6891dd25 9485 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name);
94a78b79
VZ		 9486 goto request_firmware_exit;
9487 }
9488
9489 fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data;
9490
9491 /* Initialize the pointers to the init arrays */
9492 /* Blob */
9493 BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n);
9494
9495 /* Opcodes */
9496 BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops);
9497
9498 /* Offsets */
ab6ad5a4
EG		 9499 BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err,
9500 be16_to_cpu_n);
94a78b79
VZ		 9501
9502 /* STORMs firmware */
573f2035
EG		 9503 INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
9504 be32_to_cpu(fw_hdr->tsem_int_table_data.offset);
9505 INIT_TSEM_PRAM_DATA(bp) = bp->firmware->data +
9506 be32_to_cpu(fw_hdr->tsem_pram_data.offset);
9507 INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data +
9508 be32_to_cpu(fw_hdr->usem_int_table_data.offset);
9509 INIT_USEM_PRAM_DATA(bp) = bp->firmware->data +
9510 be32_to_cpu(fw_hdr->usem_pram_data.offset);
9511 INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
9512 be32_to_cpu(fw_hdr->xsem_int_table_data.offset);
9513 INIT_XSEM_PRAM_DATA(bp) = bp->firmware->data +
9514 be32_to_cpu(fw_hdr->xsem_pram_data.offset);
9515 INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
9516 be32_to_cpu(fw_hdr->csem_int_table_data.offset);
9517 INIT_CSEM_PRAM_DATA(bp) = bp->firmware->data +
9518 be32_to_cpu(fw_hdr->csem_pram_data.offset);
523224a3
DK		 9519 /* IRO */
9520 BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro);
94a78b79
VZ		 9521
9522 return 0;
ab6ad5a4 9523
523224a3
DK		 9524iro_alloc_err:
9525 kfree(bp->init_ops_offsets);
94a78b79
VZ		 9526init_offsets_alloc_err:
9527 kfree(bp->init_ops);
9528init_ops_alloc_err:
9529 kfree(bp->init_data);
9530request_firmware_exit:
9531 release_firmware(bp->firmware);
9532
9533 return rc;
9534}
9535
523224a3
DK		 9536static inline int bnx2x_set_qm_cid_count(struct bnx2x *bp, int l2_cid_count)
9537{
9538 int cid_count = L2_FP_COUNT(l2_cid_count);
94a78b79 9539
523224a3
DK		 9540#ifdef BCM_CNIC
9541 cid_count += CNIC_CID_MAX;
9542#endif
9543 return roundup(cid_count, QM_CID_ROUND);
9544}
f85582f8 9545
a2fbb9ea
ET		 9546static int __devinit bnx2x_init_one(struct pci_dev *pdev,
9547 const struct pci_device_id *ent)
9548{
a2fbb9ea
ET		 9549 struct net_device *dev = NULL;
9550 struct bnx2x *bp;
37f9ce62 9551 int pcie_width, pcie_speed;
523224a3
DK		 9552 int rc, cid_count;
9553
f2e0899f
DK		 9554 switch (ent->driver_data) {
9555 case BCM57710:
9556 case BCM57711:
9557 case BCM57711E:
9558 cid_count = FP_SB_MAX_E1x;
9559 break;
9560
9561 case BCM57712:
9562 case BCM57712E:
9563 cid_count = FP_SB_MAX_E2;
9564 break;
a2fbb9ea 9565
f2e0899f
DK		 9566 default:
9567 pr_err("Unknown board_type (%ld), aborting\n",
9568 ent->driver_data);
870634b0 9569 return -ENODEV;
f2e0899f
DK		 9570 }
9571
ec6ba945 9572 cid_count += NONE_ETH_CONTEXT_USE + CNIC_CONTEXT_USE;
f85582f8 9573
a2fbb9ea 9574 /* dev zeroed in init_etherdev */
523224a3 9575 dev = alloc_etherdev_mq(sizeof(*bp), cid_count);
34f80b04 9576 if (!dev) {
cdaa7cb8 9577 dev_err(&pdev->dev, "Cannot allocate net device\n");
a2fbb9ea 9578 return -ENOMEM;
34f80b04 9579 }
a2fbb9ea 9580
a2fbb9ea 9581 bp = netdev_priv(dev);
7995c64e 9582 bp->msg_enable = debug;
a2fbb9ea 9583
df4770de
EG		 9584 pci_set_drvdata(pdev, dev);
9585
523224a3
DK		 9586 bp->l2_cid_count = cid_count;
9587
34f80b04 9588 rc = bnx2x_init_dev(pdev, dev);
a2fbb9ea
ET		 9589 if (rc < 0) {
9590 free_netdev(dev);
9591 return rc;
9592 }
9593
34f80b04 9594 rc = bnx2x_init_bp(bp);
693fc0d1
EG		 9595 if (rc)
9596 goto init_one_exit;
9597
523224a3
DK		 9598 /* calc qm_cid_count */
9599 bp->qm_cid_count = bnx2x_set_qm_cid_count(bp, cid_count);
9600
ec6ba945
VZ		 9601#ifdef BCM_CNIC
9602 /* disable FCOE L2 queue for E1x*/
9603 if (CHIP_IS_E1x(bp))
9604 bp->flags |= NO_FCOE_FLAG;
9605
9606#endif
9607
25985edc 9608 /* Configure interrupt mode: try to enable MSI-X/MSI if
d6214d7a
DK		 9609 * needed, set bp->num_queues appropriately.
9610 */
9611 bnx2x_set_int_mode(bp);
9612
9613 /* Add all NAPI objects */
9614 bnx2x_add_all_napi(bp);
9615
b340007f
VZ		 9616 rc = register_netdev(dev);
9617 if (rc) {
9618 dev_err(&pdev->dev, "Cannot register net device\n");
9619 goto init_one_exit;
9620 }
9621
ec6ba945
VZ		 9622#ifdef BCM_CNIC
9623 if (!NO_FCOE(bp)) {
9624 /* Add storage MAC address */
9625 rtnl_lock();
9626 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
9627 rtnl_unlock();
9628 }
9629#endif
9630
37f9ce62 9631 bnx2x_get_pcie_width_speed(bp, &pcie_width, &pcie_speed);
d6214d7a 9632
cdaa7cb8
VZ		 9633 netdev_info(dev, "%s (%c%d) PCI-E x%d %s found at mem %lx,"
9634 " IRQ %d, ", board_info[ent->driver_data].name,
9635 (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),
f2e0899f
DK		 9636 pcie_width,
9637 ((!CHIP_IS_E2(bp) && pcie_speed == 2) ||
9638 (CHIP_IS_E2(bp) && pcie_speed == 1)) ?
9639 "5GHz (Gen2)" : "2.5GHz",
cdaa7cb8
VZ		 9640 dev->base_addr, bp->pdev->irq);
9641 pr_cont("node addr %pM\n", dev->dev_addr);
c016201c 9642
a2fbb9ea 9643 return 0;
34f80b04
EG		 9644
9645init_one_exit:
9646 if (bp->regview)
9647 iounmap(bp->regview);
9648
9649 if (bp->doorbells)
9650 iounmap(bp->doorbells);
9651
9652 free_netdev(dev);
9653
9654 if (atomic_read(&pdev->enable_cnt) == 1)
9655 pci_release_regions(pdev);
9656
9657 pci_disable_device(pdev);
9658 pci_set_drvdata(pdev, NULL);
9659
9660 return rc;
a2fbb9ea
ET		 9661}
9662
9663static void __devexit bnx2x_remove_one(struct pci_dev *pdev)
9664{
9665 struct net_device *dev = pci_get_drvdata(pdev);
228241eb
ET		 9666 struct bnx2x *bp;
9667
9668 if (!dev) {
cdaa7cb8 9669 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n");
228241eb
ET		 9670 return;
9671 }
228241eb 9672 bp = netdev_priv(dev);
a2fbb9ea 9673
ec6ba945
VZ		 9674#ifdef BCM_CNIC
9675 /* Delete storage MAC address */
9676 if (!NO_FCOE(bp)) {
9677 rtnl_lock();
9678 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
9679 rtnl_unlock();
9680 }
9681#endif
9682
98507672
SR		 9683#ifdef BCM_DCBNL
9684 /* Delete app tlvs from dcbnl */
9685 bnx2x_dcbnl_update_applist(bp, true);
9686#endif
9687
a2fbb9ea
ET		 9688 unregister_netdev(dev);
9689
d6214d7a
DK		 9690 /* Delete all NAPI objects */
9691 bnx2x_del_all_napi(bp);
9692
084d6cbb
VZ		 9693 /* Power on: we can't let PCI layer write to us while we are in D3 */
9694 bnx2x_set_power_state(bp, PCI_D0);
9695
d6214d7a
DK		 9696 /* Disable MSI/MSI-X */
9697 bnx2x_disable_msi(bp);
f85582f8 9698
084d6cbb
VZ		 9699 /* Power off */
9700 bnx2x_set_power_state(bp, PCI_D3hot);
9701
72fd0718
VZ		 9702 /* Make sure RESET task is not scheduled before continuing */
9703 cancel_delayed_work_sync(&bp->reset_task);
9704
a2fbb9ea
ET		 9705 if (bp->regview)
9706 iounmap(bp->regview);
9707
9708 if (bp->doorbells)
9709 iounmap(bp->doorbells);
9710
523224a3
DK		 9711 bnx2x_free_mem_bp(bp);
9712
a2fbb9ea 9713 free_netdev(dev);
34f80b04
EG		 9714
9715 if (atomic_read(&pdev->enable_cnt) == 1)
9716 pci_release_regions(pdev);
9717
a2fbb9ea
ET		 9718 pci_disable_device(pdev);
9719 pci_set_drvdata(pdev, NULL);
9720}
9721
f8ef6e44
YG		 9722static int bnx2x_eeh_nic_unload(struct bnx2x *bp)
9723{
9724 int i;
9725
9726 bp->state = BNX2X_STATE_ERROR;
9727
9728 bp->rx_mode = BNX2X_RX_MODE_NONE;
9729
9730 bnx2x_netif_stop(bp, 0);
c89af1a3 9731 netif_carrier_off(bp->dev);
f8ef6e44
YG		 9732
9733 del_timer_sync(&bp->timer);
9734 bp->stats_state = STATS_STATE_DISABLED;
9735 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
9736
9737 /* Release IRQs */
d6214d7a 9738 bnx2x_free_irq(bp);
f8ef6e44 9739
f8ef6e44
YG		 9740 /* Free SKBs, SGEs, TPA pool and driver internals */
9741 bnx2x_free_skbs(bp);
523224a3 9742
ec6ba945 9743 for_each_rx_queue(bp, i)
f8ef6e44 9744 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
d6214d7a 9745
f8ef6e44
YG		 9746 bnx2x_free_mem(bp);
9747
9748 bp->state = BNX2X_STATE_CLOSED;
9749
f8ef6e44
YG		 9750 return 0;
9751}
9752
9753static void bnx2x_eeh_recover(struct bnx2x *bp)
9754{
9755 u32 val;
9756
9757 mutex_init(&bp->port.phy_mutex);
9758
9759 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
9760 bp->link_params.shmem_base = bp->common.shmem_base;
9761 BNX2X_DEV_INFO("shmem offset is 0x%x\n", bp->common.shmem_base);
9762
9763 if (!bp->common.shmem_base ||
9764 (bp->common.shmem_base < 0xA0000) ||
9765 (bp->common.shmem_base >= 0xC0000)) {
9766 BNX2X_DEV_INFO("MCP not active\n");
9767 bp->flags |= NO_MCP_FLAG;
9768 return;
9769 }
9770
9771 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
9772 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
9773 != (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
9774 BNX2X_ERR("BAD MCP validity signature\n");
9775
9776 if (!BP_NOMCP(bp)) {
f2e0899f
DK		 9777 bp->fw_seq =
9778 (SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
9779 DRV_MSG_SEQ_NUMBER_MASK);
f8ef6e44
YG		 9780 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
9781 }
9782}
9783
493adb1f
WX		 9784/**
9785 * bnx2x_io_error_detected - called when PCI error is detected
9786 * @pdev: Pointer to PCI device
9787 * @state: The current pci connection state
9788 *
9789 * This function is called after a PCI bus error affecting
9790 * this device has been detected.
9791 */
9792static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev,
9793 pci_channel_state_t state)
9794{
9795 struct net_device *dev = pci_get_drvdata(pdev);
9796 struct bnx2x *bp = netdev_priv(dev);
9797
9798 rtnl_lock();
9799
9800 netif_device_detach(dev);
9801
07ce50e4
DN		 9802 if (state == pci_channel_io_perm_failure) {
9803 rtnl_unlock();
9804 return PCI_ERS_RESULT_DISCONNECT;
9805 }
9806
493adb1f 9807 if (netif_running(dev))
f8ef6e44 9808 bnx2x_eeh_nic_unload(bp);
493adb1f
WX		 9809
9810 pci_disable_device(pdev);
9811
9812 rtnl_unlock();
9813
9814 /* Request a slot reset */
9815 return PCI_ERS_RESULT_NEED_RESET;
9816}
9817
9818/**
9819 * bnx2x_io_slot_reset - called after the PCI bus has been reset
9820 * @pdev: Pointer to PCI device
9821 *
9822 * Restart the card from scratch, as if from a cold-boot.
9823 */
9824static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev)
9825{
9826 struct net_device *dev = pci_get_drvdata(pdev);
9827 struct bnx2x *bp = netdev_priv(dev);
9828
9829 rtnl_lock();
9830
9831 if (pci_enable_device(pdev)) {
9832 dev_err(&pdev->dev,
9833 "Cannot re-enable PCI device after reset\n");
9834 rtnl_unlock();
9835 return PCI_ERS_RESULT_DISCONNECT;
9836 }
9837
9838 pci_set_master(pdev);
9839 pci_restore_state(pdev);
9840
9841 if (netif_running(dev))
9842 bnx2x_set_power_state(bp, PCI_D0);
9843
9844 rtnl_unlock();
9845
9846 return PCI_ERS_RESULT_RECOVERED;
9847}
9848
9849/**
9850 * bnx2x_io_resume - called when traffic can start flowing again
9851 * @pdev: Pointer to PCI device
9852 *
9853 * This callback is called when the error recovery driver tells us that
9854 * its OK to resume normal operation.
9855 */
9856static void bnx2x_io_resume(struct pci_dev *pdev)
9857{
9858 struct net_device *dev = pci_get_drvdata(pdev);
9859 struct bnx2x *bp = netdev_priv(dev);
9860
72fd0718 9861 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
f2e0899f
DK		 9862 printk(KERN_ERR "Handling parity error recovery. "
9863 "Try again later\n");
72fd0718
VZ		 9864 return;
9865 }
9866
493adb1f
WX		 9867 rtnl_lock();
9868
f8ef6e44
YG		 9869 bnx2x_eeh_recover(bp);
9870
493adb1f 9871 if (netif_running(dev))
f8ef6e44 9872 bnx2x_nic_load(bp, LOAD_NORMAL);
493adb1f
WX		 9873
9874 netif_device_attach(dev);
9875
9876 rtnl_unlock();
9877}
9878
9879static struct pci_error_handlers bnx2x_err_handler = {
9880 .error_detected = bnx2x_io_error_detected,
356e2385
EG		 9881 .slot_reset = bnx2x_io_slot_reset,
9882 .resume = bnx2x_io_resume,
493adb1f
WX		 9883};
9884
a2fbb9ea 9885static struct pci_driver bnx2x_pci_driver = {
493adb1f
WX		 9886 .name = DRV_MODULE_NAME,
9887 .id_table = bnx2x_pci_tbl,
9888 .probe = bnx2x_init_one,
9889 .remove = __devexit_p(bnx2x_remove_one),
9890 .suspend = bnx2x_suspend,
9891 .resume = bnx2x_resume,
9892 .err_handler = &bnx2x_err_handler,
a2fbb9ea
ET		 9893};
9894
9895static int __init bnx2x_init(void)
9896{
dd21ca6d
SG		 9897 int ret;
9898
7995c64e 9899 pr_info("%s", version);
938cf541 9900
1cf167f2
EG		 9901 bnx2x_wq = create_singlethread_workqueue("bnx2x");
9902 if (bnx2x_wq == NULL) {
7995c64e 9903 pr_err("Cannot create workqueue\n");
1cf167f2
EG		 9904 return -ENOMEM;
9905 }
9906
dd21ca6d
SG		 9907 ret = pci_register_driver(&bnx2x_pci_driver);
9908 if (ret) {
7995c64e 9909 pr_err("Cannot register driver\n");
dd21ca6d
SG		 9910 destroy_workqueue(bnx2x_wq);
9911 }
9912 return ret;
a2fbb9ea
ET		 9913}
9914
9915static void __exit bnx2x_cleanup(void)
9916{
9917 pci_unregister_driver(&bnx2x_pci_driver);
1cf167f2
EG		 9918
9919 destroy_workqueue(bnx2x_wq);
a2fbb9ea
ET		 9920}
9921
9922module_init(bnx2x_init);
9923module_exit(bnx2x_cleanup);
9924
993ac7b5
MC		 9925#ifdef BCM_CNIC
9926
9927/* count denotes the number of new completions we have seen */
9928static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count)
9929{
9930 struct eth_spe *spe;
9931
9932#ifdef BNX2X_STOP_ON_ERROR
9933 if (unlikely(bp->panic))
9934 return;
9935#endif
9936
9937 spin_lock_bh(&bp->spq_lock);
c2bff63f 9938 BUG_ON(bp->cnic_spq_pending < count);
993ac7b5
MC		 9939 bp->cnic_spq_pending -= count;
9940
993ac7b5 9941
c2bff63f
DK		 9942 for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) {
9943 u16 type = (le16_to_cpu(bp->cnic_kwq_cons->hdr.type)
9944 & SPE_HDR_CONN_TYPE) >>
9945 SPE_HDR_CONN_TYPE_SHIFT;
9946
9947 /* Set validation for iSCSI L2 client before sending SETUP
9948 * ramrod
9949 */
9950 if (type == ETH_CONNECTION_TYPE) {
9951 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->
9952 hdr.conn_and_cmd_data) >>
9953 SPE_HDR_CMD_ID_SHIFT) & 0xff;
9954
9955 if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP)
9956 bnx2x_set_ctx_validation(&bp->context.
9957 vcxt[BNX2X_ISCSI_ETH_CID].eth,
9958 HW_CID(bp, BNX2X_ISCSI_ETH_CID));
9959 }
9960
6e30dd4e
VZ		 9961 /* There may be not more than 8 L2 and not more than 8 L5 SPEs
9962 * We also check that the number of outstanding
9963 * COMMON ramrods is not more than the EQ and SPQ can
9964 * accommodate.
c2bff63f 9965 */
6e30dd4e
VZ		 9966 if (type == ETH_CONNECTION_TYPE) {
9967 if (!atomic_read(&bp->cq_spq_left))
9968 break;
9969 else
9970 atomic_dec(&bp->cq_spq_left);
9971 } else if (type == NONE_CONNECTION_TYPE) {
9972 if (!atomic_read(&bp->eq_spq_left))
c2bff63f
DK		 9973 break;
9974 else
6e30dd4e 9975 atomic_dec(&bp->eq_spq_left);
ec6ba945
VZ		 9976 } else if ((type == ISCSI_CONNECTION_TYPE) ||
9977 (type == FCOE_CONNECTION_TYPE)) {
c2bff63f
DK		 9978 if (bp->cnic_spq_pending >=
9979 bp->cnic_eth_dev.max_kwqe_pending)
9980 break;
9981 else
9982 bp->cnic_spq_pending++;
9983 } else {
9984 BNX2X_ERR("Unknown SPE type: %d\n", type);
9985 bnx2x_panic();
993ac7b5 9986 break;
c2bff63f 9987 }
993ac7b5
MC		 9988
9989 spe = bnx2x_sp_get_next(bp);
9990 *spe = *bp->cnic_kwq_cons;
9991
993ac7b5
MC		 9992 DP(NETIF_MSG_TIMER, "pending on SPQ %d, on KWQ %d count %d\n",
9993 bp->cnic_spq_pending, bp->cnic_kwq_pending, count);
9994
9995 if (bp->cnic_kwq_cons == bp->cnic_kwq_last)
9996 bp->cnic_kwq_cons = bp->cnic_kwq;
9997 else
9998 bp->cnic_kwq_cons++;
9999 }
10000 bnx2x_sp_prod_update(bp);
10001 spin_unlock_bh(&bp->spq_lock);
10002}
10003
10004static int bnx2x_cnic_sp_queue(struct net_device *dev,
10005 struct kwqe_16 *kwqes[], u32 count)
10006{
10007 struct bnx2x *bp = netdev_priv(dev);
10008 int i;
10009
10010#ifdef BNX2X_STOP_ON_ERROR
10011 if (unlikely(bp->panic))
10012 return -EIO;
10013#endif
10014
10015 spin_lock_bh(&bp->spq_lock);
10016
10017 for (i = 0; i < count; i++) {
10018 struct eth_spe *spe = (struct eth_spe *)kwqes[i];
10019
10020 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT)
10021 break;
10022
10023 *bp->cnic_kwq_prod = *spe;
10024
10025 bp->cnic_kwq_pending++;
10026
10027 DP(NETIF_MSG_TIMER, "L5 SPQE %x %x %x:%x pos %d\n",
10028 spe->hdr.conn_and_cmd_data, spe->hdr.type,
523224a3
DK		 10029 spe->data.update_data_addr.hi,
10030 spe->data.update_data_addr.lo,
993ac7b5
MC		 10031 bp->cnic_kwq_pending);
10032
10033 if (bp->cnic_kwq_prod == bp->cnic_kwq_last)
10034 bp->cnic_kwq_prod = bp->cnic_kwq;
10035 else
10036 bp->cnic_kwq_prod++;
10037 }
10038
10039 spin_unlock_bh(&bp->spq_lock);
10040
10041 if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending)
10042 bnx2x_cnic_sp_post(bp, 0);
10043
10044 return i;
10045}
10046
10047static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl)
10048{
10049 struct cnic_ops *c_ops;
10050 int rc = 0;
10051
10052 mutex_lock(&bp->cnic_mutex);
13707f9e
ED		 10053 c_ops = rcu_dereference_protected(bp->cnic_ops,
10054 lockdep_is_held(&bp->cnic_mutex));
993ac7b5
MC		 10055 if (c_ops)
10056 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
10057 mutex_unlock(&bp->cnic_mutex);
10058
10059 return rc;
10060}
10061
10062static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl)
10063{
10064 struct cnic_ops *c_ops;
10065 int rc = 0;
10066
10067 rcu_read_lock();
10068 c_ops = rcu_dereference(bp->cnic_ops);
10069 if (c_ops)
10070 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
10071 rcu_read_unlock();
10072
10073 return rc;
10074}
10075
10076/*
10077 * for commands that have no data
10078 */
9f6c9258 10079int bnx2x_cnic_notify(struct bnx2x *bp, int cmd)
993ac7b5
MC		 10080{
10081 struct cnic_ctl_info ctl = {0};
10082
10083 ctl.cmd = cmd;
10084
10085 return bnx2x_cnic_ctl_send(bp, &ctl);
10086}
10087
10088static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid)
10089{
10090 struct cnic_ctl_info ctl;
10091
10092 /* first we tell CNIC and only then we count this as a completion */
10093 ctl.cmd = CNIC_CTL_COMPLETION_CMD;
10094 ctl.data.comp.cid = cid;
10095
10096 bnx2x_cnic_ctl_send_bh(bp, &ctl);
c2bff63f 10097 bnx2x_cnic_sp_post(bp, 0);
993ac7b5
MC		 10098}
10099
10100static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl)
10101{
10102 struct bnx2x *bp = netdev_priv(dev);
10103 int rc = 0;
10104
10105 switch (ctl->cmd) {
10106 case DRV_CTL_CTXTBL_WR_CMD: {
10107 u32 index = ctl->data.io.offset;
10108 dma_addr_t addr = ctl->data.io.dma_addr;
10109
10110 bnx2x_ilt_wr(bp, index, addr);
10111 break;
10112 }
10113
c2bff63f
DK		 10114 case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: {
10115 int count = ctl->data.credit.credit_count;
993ac7b5
MC		 10116
10117 bnx2x_cnic_sp_post(bp, count);
10118 break;
10119 }
10120
10121 /* rtnl_lock is held. */
10122 case DRV_CTL_START_L2_CMD: {
10123 u32 cli = ctl->data.ring.client_id;
10124
ec6ba945
VZ		 10125 /* Clear FCoE FIP and ALL ENODE MACs addresses first */
10126 bnx2x_del_fcoe_eth_macs(bp);
10127
523224a3
DK		 10128 /* Set iSCSI MAC address */
10129 bnx2x_set_iscsi_eth_mac_addr(bp, 1);
10130
10131 mmiowb();
10132 barrier();
10133
10134 /* Start accepting on iSCSI L2 ring. Accept all multicasts
10135 * because it's the only way for UIO Client to accept
10136 * multicasts (in non-promiscuous mode only one Client per
10137 * function will receive multicast packets (leading in our
10138 * case).
10139 */
10140 bnx2x_rxq_set_mac_filters(bp, cli,
10141 BNX2X_ACCEPT_UNICAST |
10142 BNX2X_ACCEPT_BROADCAST |
10143 BNX2X_ACCEPT_ALL_MULTICAST);
10144 storm_memset_mac_filters(bp, &bp->mac_filters, BP_FUNC(bp));
10145
993ac7b5
MC		 10146 break;
10147 }
10148
10149 /* rtnl_lock is held. */
10150 case DRV_CTL_STOP_L2_CMD: {
10151 u32 cli = ctl->data.ring.client_id;
10152
523224a3
DK		 10153 /* Stop accepting on iSCSI L2 ring */
10154 bnx2x_rxq_set_mac_filters(bp, cli, BNX2X_ACCEPT_NONE);
10155 storm_memset_mac_filters(bp, &bp->mac_filters, BP_FUNC(bp));
10156
10157 mmiowb();
10158 barrier();
10159
10160 /* Unset iSCSI L2 MAC */
10161 bnx2x_set_iscsi_eth_mac_addr(bp, 0);
993ac7b5
MC		 10162 break;
10163 }
c2bff63f
DK		 10164 case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: {
10165 int count = ctl->data.credit.credit_count;
10166
10167 smp_mb__before_atomic_inc();
6e30dd4e 10168 atomic_add(count, &bp->cq_spq_left);
c2bff63f
DK		 10169 smp_mb__after_atomic_inc();
10170 break;
10171 }
993ac7b5 10172
fab0dc89
DK		 10173 case DRV_CTL_ISCSI_STOPPED_CMD: {
10174 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_ISCSI_STOPPED);
10175 break;
10176 }
10177
993ac7b5
MC		 10178 default:
10179 BNX2X_ERR("unknown command %x\n", ctl->cmd);
10180 rc = -EINVAL;
10181 }
10182
10183 return rc;
10184}
10185
9f6c9258 10186void bnx2x_setup_cnic_irq_info(struct bnx2x *bp)
993ac7b5
MC		 10187{
10188 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
10189
10190 if (bp->flags & USING_MSIX_FLAG) {
10191 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
10192 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
10193 cp->irq_arr[0].vector = bp->msix_table[1].vector;
10194 } else {
10195 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
10196 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
10197 }
f2e0899f
DK		 10198 if (CHIP_IS_E2(bp))
10199 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb;
10200 else
10201 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb;
10202
993ac7b5 10203 cp->irq_arr[0].status_blk_num = CNIC_SB_ID(bp);
523224a3 10204 cp->irq_arr[0].status_blk_num2 = CNIC_IGU_SB_ID(bp);
993ac7b5
MC		 10205 cp->irq_arr[1].status_blk = bp->def_status_blk;
10206 cp->irq_arr[1].status_blk_num = DEF_SB_ID;
523224a3 10207 cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID;
993ac7b5
MC		 10208
10209 cp->num_irq = 2;
10210}
10211
10212static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops,
10213 void *data)
10214{
10215 struct bnx2x *bp = netdev_priv(dev);
10216 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
10217
10218 if (ops == NULL)
10219 return -EINVAL;
10220
10221 if (atomic_read(&bp->intr_sem) != 0)
10222 return -EBUSY;
10223
10224 bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL);
10225 if (!bp->cnic_kwq)
10226 return -ENOMEM;
10227
10228 bp->cnic_kwq_cons = bp->cnic_kwq;
10229 bp->cnic_kwq_prod = bp->cnic_kwq;
10230 bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT;
10231
10232 bp->cnic_spq_pending = 0;
10233 bp->cnic_kwq_pending = 0;
10234
10235 bp->cnic_data = data;
10236
10237 cp->num_irq = 0;
10238 cp->drv_state = CNIC_DRV_STATE_REGD;
523224a3 10239 cp->iro_arr = bp->iro_arr;
993ac7b5 10240
993ac7b5 10241 bnx2x_setup_cnic_irq_info(bp);
c2bff63f 10242
993ac7b5
MC		 10243 rcu_assign_pointer(bp->cnic_ops, ops);
10244
10245 return 0;
10246}
10247
10248static int bnx2x_unregister_cnic(struct net_device *dev)
10249{
10250 struct bnx2x *bp = netdev_priv(dev);
10251 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
10252
10253 mutex_lock(&bp->cnic_mutex);
993ac7b5
MC		 10254 cp->drv_state = 0;
10255 rcu_assign_pointer(bp->cnic_ops, NULL);
10256 mutex_unlock(&bp->cnic_mutex);
10257 synchronize_rcu();
10258 kfree(bp->cnic_kwq);
10259 bp->cnic_kwq = NULL;
10260
10261 return 0;
10262}
10263
10264struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev)
10265{
10266 struct bnx2x *bp = netdev_priv(dev);
10267 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
10268
2ba45142
VZ		 10269 /* If both iSCSI and FCoE are disabled - return NULL in
10270 * order to indicate CNIC that it should not try to work
10271 * with this device.
10272 */
10273 if (NO_ISCSI(bp) && NO_FCOE(bp))
10274 return NULL;
10275
993ac7b5
MC		 10276 cp->drv_owner = THIS_MODULE;
10277 cp->chip_id = CHIP_ID(bp);
10278 cp->pdev = bp->pdev;
10279 cp->io_base = bp->regview;
10280 cp->io_base2 = bp->doorbells;
10281 cp->max_kwqe_pending = 8;
523224a3 10282 cp->ctx_blk_size = CDU_ILT_PAGE_SZ;
c2bff63f
DK		 10283 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
10284 bnx2x_cid_ilt_lines(bp);
993ac7b5 10285 cp->ctx_tbl_len = CNIC_ILT_LINES;
c2bff63f 10286 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
993ac7b5
MC		 10287 cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue;
10288 cp->drv_ctl = bnx2x_drv_ctl;
10289 cp->drv_register_cnic = bnx2x_register_cnic;
10290 cp->drv_unregister_cnic = bnx2x_unregister_cnic;
ec6ba945
VZ		 10291 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID;
10292 cp->iscsi_l2_client_id = BNX2X_ISCSI_ETH_CL_ID +
10293 BP_E1HVN(bp) * NONE_ETH_CONTEXT_USE;
c2bff63f
DK		 10294 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID;
10295
2ba45142
VZ		 10296 if (NO_ISCSI_OOO(bp))
10297 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
10298
10299 if (NO_ISCSI(bp))
10300 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI;
10301
10302 if (NO_FCOE(bp))
10303 cp->drv_state |= CNIC_DRV_STATE_NO_FCOE;
10304
c2bff63f
DK		 10305 DP(BNX2X_MSG_SP, "page_size %d, tbl_offset %d, tbl_lines %d, "
10306 "starting cid %d\n",
10307 cp->ctx_blk_size,
10308 cp->ctx_tbl_offset,
10309 cp->ctx_tbl_len,
10310 cp->starting_cid);
993ac7b5
MC		 10311 return cp;
10312}
10313EXPORT_SYMBOL(bnx2x_cnic_probe);
10314
10315#endif /* BCM_CNIC */
94a78b79 10316
Linux kernel - Deliverables
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