projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| a2fbb9ea ET |
1 | /* bnx2x_init.h: Broadcom Everest network driver. |
| 2 | * | |
| e8717a47 | 3 | * Copyright (c) 2007-2008 Broadcom Corporation |
| a2fbb9ea ET |
4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify | |
| 6 | * it under the terms of the GNU General Public License as published by | |
| 7 | * the Free Software Foundation. | |
| 8 | * | |
| 24e3fcef EG |
9 | * Maintained by: Eilon Greenstein <eilong@broadcom.com> |
| 10 | * Written by: Eliezer Tamir | |
| a2fbb9ea ET |
11 | */ |
| 12 | ||
| 13 | #ifndef BNX2X_INIT_H | |
| 14 | #define BNX2X_INIT_H | |
| 15 | ||
| 16 | #define COMMON 0x1 | |
| 17 | #define PORT0 0x2 | |
| 18 | #define PORT1 0x4 | |
| 19 | ||
| 20 | #define INIT_EMULATION 0x1 | |
| 21 | #define INIT_FPGA 0x2 | |
| 22 | #define INIT_ASIC 0x4 | |
| 23 | #define INIT_HARDWARE 0x7 | |
| 24 | ||
| ad8d3948 EG |
25 | #define STORM_INTMEM_SIZE_E1 (0x5800 / 4) |
| 26 | #define STORM_INTMEM_SIZE_E1H (0x10000 / 4) | |
| a2fbb9ea ET |
27 | #define TSTORM_INTMEM_ADDR 0x1a0000 |
| 28 | #define CSTORM_INTMEM_ADDR 0x220000 | |
| 29 | #define XSTORM_INTMEM_ADDR 0x2a0000 | |
| 30 | #define USTORM_INTMEM_ADDR 0x320000 | |
| 31 | ||
| 32 | ||
| 33 | /* Init operation types and structures */ | |
| ad8d3948 | 34 | /* Common for both E1 and E1H */ |
| a2fbb9ea ET |
35 | #define OP_RD 0x1 /* read single register */ |
| 36 | #define OP_WR 0x2 /* write single register */ | |
| 37 | #define OP_IW 0x3 /* write single register using mailbox */ | |
| 38 | #define OP_SW 0x4 /* copy a string to the device */ | |
| 39 | #define OP_SI 0x5 /* copy a string using mailbox */ | |
| 40 | #define OP_ZR 0x6 /* clear memory */ | |
| 41 | #define OP_ZP 0x7 /* unzip then copy with DMAE */ | |
| ad8d3948 EG |
42 | #define OP_WR_64 0x8 /* write 64 bit pattern */ |
| 43 | #define OP_WB 0x9 /* copy a string using DMAE */ | |
| 44 | ||
| 45 | /* Operation specific for E1 */ | |
| 46 | #define OP_RD_E1 0xa /* read single register */ | |
| 47 | #define OP_WR_E1 0xb /* write single register */ | |
| 48 | #define OP_IW_E1 0xc /* write single register using mailbox */ | |
| 49 | #define OP_SW_E1 0xd /* copy a string to the device */ | |
| 50 | #define OP_SI_E1 0xe /* copy a string using mailbox */ | |
| 51 | #define OP_ZR_E1 0xf /* clear memory */ | |
| 52 | #define OP_ZP_E1 0x10 /* unzip then copy with DMAE */ | |
| 53 | #define OP_WR_64_E1 0x11 /* write 64 bit pattern on E1 */ | |
| 54 | #define OP_WB_E1 0x12 /* copy a string using DMAE */ | |
| 55 | ||
| 56 | /* Operation specific for E1H */ | |
| 57 | #define OP_RD_E1H 0x13 /* read single register */ | |
| 58 | #define OP_WR_E1H 0x14 /* write single register */ | |
| 59 | #define OP_IW_E1H 0x15 /* write single register using mailbox */ | |
| 60 | #define OP_SW_E1H 0x16 /* copy a string to the device */ | |
| 61 | #define OP_SI_E1H 0x17 /* copy a string using mailbox */ | |
| 62 | #define OP_ZR_E1H 0x18 /* clear memory */ | |
| 63 | #define OP_ZP_E1H 0x19 /* unzip then copy with DMAE */ | |
| 64 | #define OP_WR_64_E1H 0x1a /* write 64 bit pattern on E1H */ | |
| 65 | #define OP_WB_E1H 0x1b /* copy a string using DMAE */ | |
| 66 | ||
| 67 | /* FPGA and EMUL specific operations */ | |
| 68 | #define OP_WR_EMUL_E1H 0x1c /* write single register on E1H Emul */ | |
| 69 | #define OP_WR_EMUL 0x1d /* write single register on Emulation */ | |
| 70 | #define OP_WR_FPGA 0x1e /* write single register on FPGA */ | |
| 71 | #define OP_WR_ASIC 0x1f /* write single register on ASIC */ | |
| 72 | ||
| a2fbb9ea ET |
73 | |
| 74 | struct raw_op { | |
| 6378c025 EG |
75 | u32 op:8; |
| 76 | u32 offset:24; | |
| a2fbb9ea ET |
77 | u32 raw_data; |
| 78 | }; | |
| 79 | ||
| 80 | struct op_read { | |
| 6378c025 EG |
81 | u32 op:8; |
| 82 | u32 offset:24; | |
| a2fbb9ea ET |
83 | u32 pad; |
| 84 | }; | |
| 85 | ||
| 86 | struct op_write { | |
| 6378c025 EG |
87 | u32 op:8; |
| 88 | u32 offset:24; | |
| a2fbb9ea ET |
89 | u32 val; |
| 90 | }; | |
| 91 | ||
| 92 | struct op_string_write { | |
| 6378c025 EG |
93 | u32 op:8; |
| 94 | u32 offset:24; | |
| a2fbb9ea ET |
95 | #ifdef __LITTLE_ENDIAN |
| 96 | u16 data_off; | |
| 97 | u16 data_len; | |
| 98 | #else /* __BIG_ENDIAN */ | |
| 99 | u16 data_len; | |
| 100 | u16 data_off; | |
| 101 | #endif | |
| 102 | }; | |
| 103 | ||
| 104 | struct op_zero { | |
| 6378c025 EG |
105 | u32 op:8; |
| 106 | u32 offset:24; | |
| a2fbb9ea ET |
107 | u32 len; |
| 108 | }; | |
| 109 | ||
| 110 | union init_op { | |
| 111 | struct op_read read; | |
| 112 | struct op_write write; | |
| 113 | struct op_string_write str_wr; | |
| 114 | struct op_zero zero; | |
| 115 | struct raw_op raw; | |
| 116 | }; | |
| 117 | ||
| 118 | #include "bnx2x_init_values.h" | |
| 119 | ||
| 120 | static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val); | |
| a2fbb9ea ET |
121 | static int bnx2x_gunzip(struct bnx2x *bp, u8 *zbuf, int len); |
| 122 | ||
| 123 | static void bnx2x_init_str_wr(struct bnx2x *bp, u32 addr, const u32 *data, | |
| 124 | u32 len) | |
| 125 | { | |
| 126 | int i; | |
| 127 | ||
| 128 | for (i = 0; i < len; i++) { | |
| 129 | REG_WR(bp, addr + i*4, data[i]); | |
| 130 | if (!(i % 10000)) { | |
| 131 | touch_softlockup_watchdog(); | |
| 132 | cpu_relax(); | |
| 133 | } | |
| 134 | } | |
| 135 | } | |
| 136 | ||
| a2fbb9ea ET |
137 | static void bnx2x_init_ind_wr(struct bnx2x *bp, u32 addr, const u32 *data, |
| 138 | u16 len) | |
| 139 | { | |
| 140 | int i; | |
| 141 | ||
| 142 | for (i = 0; i < len; i++) { | |
| 143 | REG_WR_IND(bp, addr + i*4, data[i]); | |
| 144 | if (!(i % 10000)) { | |
| 145 | touch_softlockup_watchdog(); | |
| 146 | cpu_relax(); | |
| 147 | } | |
| 148 | } | |
| 149 | } | |
| 150 | ||
| ad8d3948 EG |
151 | static void bnx2x_write_big_buf(struct bnx2x *bp, u32 addr, u32 len) |
| 152 | { | |
| 153 | #ifdef USE_DMAE | |
| 154 | int offset = 0; | |
| 155 | ||
| 156 | if (bp->dmae_ready) { | |
| 157 | while (len > DMAE_LEN32_WR_MAX) { | |
| 158 | bnx2x_write_dmae(bp, bp->gunzip_mapping + offset, | |
| 159 | addr + offset, DMAE_LEN32_WR_MAX); | |
| 160 | offset += DMAE_LEN32_WR_MAX * 4; | |
| 161 | len -= DMAE_LEN32_WR_MAX; | |
| 162 | } | |
| 163 | bnx2x_write_dmae(bp, bp->gunzip_mapping + offset, | |
| 164 | addr + offset, len); | |
| 165 | } else | |
| 166 | bnx2x_init_str_wr(bp, addr, bp->gunzip_buf, len); | |
| 167 | #else | |
| 168 | bnx2x_init_str_wr(bp, addr, bp->gunzip_buf, len); | |
| 169 | #endif | |
| 170 | } | |
| 171 | ||
| 172 | static void bnx2x_init_fill(struct bnx2x *bp, u32 addr, int fill, u32 len) | |
| 173 | { | |
| 174 | if ((len * 4) > FW_BUF_SIZE) { | |
| 175 | BNX2X_ERR("LARGE DMAE OPERATION ! addr 0x%x len 0x%x\n", | |
| 176 | addr, len*4); | |
| 177 | return; | |
| 178 | } | |
| 179 | memset(bp->gunzip_buf, fill, len * 4); | |
| 180 | ||
| 181 | bnx2x_write_big_buf(bp, addr, len); | |
| 182 | } | |
| 183 | ||
| 184 | static void bnx2x_init_wr_64(struct bnx2x *bp, u32 addr, const u32 *data, | |
| 185 | u32 len64) | |
| 186 | { | |
| 187 | u32 buf_len32 = FW_BUF_SIZE/4; | |
| 188 | u32 len = len64*2; | |
| 189 | u64 data64 = 0; | |
| 190 | int i; | |
| 191 | ||
| 192 | /* 64 bit value is in a blob: first low DWORD, then high DWORD */ | |
| 193 | data64 = HILO_U64((*(data + 1)), (*data)); | |
| 194 | len64 = min((u32)(FW_BUF_SIZE/8), len64); | |
| 195 | for (i = 0; i < len64; i++) { | |
| 196 | u64 *pdata = ((u64 *)(bp->gunzip_buf)) + i; | |
| 197 | ||
| 198 | *pdata = data64; | |
| 199 | } | |
| 200 | ||
| 201 | for (i = 0; i < len; i += buf_len32) { | |
| 202 | u32 cur_len = min(buf_len32, len - i); | |
| 203 | ||
| 204 | bnx2x_write_big_buf(bp, addr + i * 4, cur_len); | |
| 205 | } | |
| 206 | } | |
| 207 | ||
| 208 | /********************************************************* | |
| 209 | There are different blobs for each PRAM section. | |
| 210 | In addition, each blob write operation is divided into a few operations | |
| 33471629 | 211 | in order to decrease the amount of phys. contiguous buffer needed. |
| ad8d3948 EG |
212 | Thus, when we select a blob the address may be with some offset |
| 213 | from the beginning of PRAM section. | |
| 214 | The same holds for the INT_TABLE sections. | |
| 215 | **********************************************************/ | |
| 216 | #define IF_IS_INT_TABLE_ADDR(base, addr) \ | |
| 217 | if (((base) <= (addr)) && ((base) + 0x400 >= (addr))) | |
| 218 | ||
| 219 | #define IF_IS_PRAM_ADDR(base, addr) \ | |
| 220 | if (((base) <= (addr)) && ((base) + 0x40000 >= (addr))) | |
| 221 | ||
| 222 | static const u32 *bnx2x_sel_blob(u32 addr, const u32 *data, int is_e1) | |
| 223 | { | |
| 224 | IF_IS_INT_TABLE_ADDR(TSEM_REG_INT_TABLE, addr) | |
| 225 | data = is_e1 ? tsem_int_table_data_e1 : | |
| 226 | tsem_int_table_data_e1h; | |
| 227 | else | |
| 228 | IF_IS_INT_TABLE_ADDR(CSEM_REG_INT_TABLE, addr) | |
| 34f80b04 EG |
229 | data = is_e1 ? csem_int_table_data_e1 : |
| 230 | csem_int_table_data_e1h; | |
| ad8d3948 EG |
231 | else |
| 232 | IF_IS_INT_TABLE_ADDR(USEM_REG_INT_TABLE, addr) | |
| 34f80b04 EG |
233 | data = is_e1 ? usem_int_table_data_e1 : |
| 234 | usem_int_table_data_e1h; | |
| ad8d3948 EG |
235 | else |
| 236 | IF_IS_INT_TABLE_ADDR(XSEM_REG_INT_TABLE, addr) | |
| 34f80b04 EG |
237 | data = is_e1 ? xsem_int_table_data_e1 : |
| 238 | xsem_int_table_data_e1h; | |
| ad8d3948 EG |
239 | else |
| 240 | IF_IS_PRAM_ADDR(TSEM_REG_PRAM, addr) | |
| 34f80b04 | 241 | data = is_e1 ? tsem_pram_data_e1 : tsem_pram_data_e1h; |
| ad8d3948 EG |
242 | else |
| 243 | IF_IS_PRAM_ADDR(CSEM_REG_PRAM, addr) | |
| 34f80b04 | 244 | data = is_e1 ? csem_pram_data_e1 : csem_pram_data_e1h; |
| ad8d3948 EG |
245 | else |
| 246 | IF_IS_PRAM_ADDR(USEM_REG_PRAM, addr) | |
| 34f80b04 | 247 | data = is_e1 ? usem_pram_data_e1 : usem_pram_data_e1h; |
| ad8d3948 EG |
248 | else |
| 249 | IF_IS_PRAM_ADDR(XSEM_REG_PRAM, addr) | |
| 34f80b04 | 250 | data = is_e1 ? xsem_pram_data_e1 : xsem_pram_data_e1h; |
| ad8d3948 EG |
251 | |
| 252 | return data; | |
| 253 | } | |
| 254 | ||
| a2fbb9ea | 255 | static void bnx2x_init_wr_wb(struct bnx2x *bp, u32 addr, const u32 *data, |
| ad8d3948 | 256 | u32 len, int gunzip, int is_e1, u32 blob_off) |
| a2fbb9ea ET |
257 | { |
| 258 | int offset = 0; | |
| 259 | ||
| ad8d3948 EG |
260 | data = bnx2x_sel_blob(addr, data, is_e1) + blob_off; |
| 261 | ||
| a2fbb9ea ET |
262 | if (gunzip) { |
| 263 | int rc; | |
| 264 | #ifdef __BIG_ENDIAN | |
| 265 | int i, size; | |
| 266 | u32 *temp; | |
| 267 | ||
| 268 | temp = kmalloc(len, GFP_KERNEL); | |
| 269 | size = (len / 4) + ((len % 4) ? 1 : 0); | |
| 270 | for (i = 0; i < size; i++) | |
| 271 | temp[i] = swab32(data[i]); | |
| 272 | data = temp; | |
| 273 | #endif | |
| 274 | rc = bnx2x_gunzip(bp, (u8 *)data, len); | |
| 275 | if (rc) { | |
| ad8d3948 | 276 | BNX2X_ERR("gunzip failed ! rc %d\n", rc); |
| a2fbb9ea ET |
277 | return; |
| 278 | } | |
| 279 | len = bp->gunzip_outlen; | |
| 280 | #ifdef __BIG_ENDIAN | |
| 281 | kfree(temp); | |
| 282 | for (i = 0; i < len; i++) | |
| ad8d3948 | 283 | ((u32 *)bp->gunzip_buf)[i] = |
| a2fbb9ea ET |
284 | swab32(((u32 *)bp->gunzip_buf)[i]); |
| 285 | #endif | |
| 286 | } else { | |
| 287 | if ((len * 4) > FW_BUF_SIZE) { | |
| ad8d3948 EG |
288 | BNX2X_ERR("LARGE DMAE OPERATION ! " |
| 289 | "addr 0x%x len 0x%x\n", addr, len*4); | |
| a2fbb9ea ET |
290 | return; |
| 291 | } | |
| 292 | memcpy(bp->gunzip_buf, data, len * 4); | |
| 293 | } | |
| 294 | ||
| ad8d3948 EG |
295 | if (bp->dmae_ready) { |
| 296 | while (len > DMAE_LEN32_WR_MAX) { | |
| 297 | bnx2x_write_dmae(bp, bp->gunzip_mapping + offset, | |
| 298 | addr + offset, DMAE_LEN32_WR_MAX); | |
| 299 | offset += DMAE_LEN32_WR_MAX * 4; | |
| 300 | len -= DMAE_LEN32_WR_MAX; | |
| 301 | } | |
| a2fbb9ea | 302 | bnx2x_write_dmae(bp, bp->gunzip_mapping + offset, |
| ad8d3948 EG |
303 | addr + offset, len); |
| 304 | } else | |
| 305 | bnx2x_init_ind_wr(bp, addr, bp->gunzip_buf, len); | |
| a2fbb9ea ET |
306 | } |
| 307 | ||
| 308 | static void bnx2x_init_block(struct bnx2x *bp, u32 op_start, u32 op_end) | |
| 309 | { | |
| ad8d3948 EG |
310 | int is_e1 = CHIP_IS_E1(bp); |
| 311 | int is_e1h = CHIP_IS_E1H(bp); | |
| 312 | int is_emul_e1h = (CHIP_REV_IS_EMUL(bp) && is_e1h); | |
| 313 | int hw_wr, i; | |
| a2fbb9ea ET |
314 | union init_op *op; |
| 315 | u32 op_type, addr, len; | |
| ad8d3948 EG |
316 | const u32 *data, *data_base; |
| 317 | ||
| 318 | if (CHIP_REV_IS_FPGA(bp)) | |
| 319 | hw_wr = OP_WR_FPGA; | |
| 320 | else if (CHIP_REV_IS_EMUL(bp)) | |
| 321 | hw_wr = OP_WR_EMUL; | |
| 322 | else | |
| 323 | hw_wr = OP_WR_ASIC; | |
| 324 | ||
| 325 | if (is_e1) | |
| 326 | data_base = init_data_e1; | |
| 327 | else /* CHIP_IS_E1H(bp) */ | |
| 328 | data_base = init_data_e1h; | |
| a2fbb9ea ET |
329 | |
| 330 | for (i = op_start; i < op_end; i++) { | |
| 331 | ||
| 332 | op = (union init_op *)&(init_ops[i]); | |
| 333 | ||
| 334 | op_type = op->str_wr.op; | |
| 335 | addr = op->str_wr.offset; | |
| 336 | len = op->str_wr.data_len; | |
| ad8d3948 EG |
337 | data = data_base + op->str_wr.data_off; |
| 338 | ||
| 33471629 | 339 | /* careful! it must be in order */ |
| ad8d3948 EG |
340 | if (unlikely(op_type > OP_WB)) { |
| 341 | ||
| 342 | /* If E1 only */ | |
| 343 | if (op_type <= OP_WB_E1) { | |
| 344 | if (is_e1) | |
| 345 | op_type -= (OP_RD_E1 - OP_RD); | |
| 346 | ||
| 347 | /* If E1H only */ | |
| 348 | } else if (op_type <= OP_WB_E1H) { | |
| 349 | if (is_e1h) | |
| 350 | op_type -= (OP_RD_E1H - OP_RD); | |
| 351 | } | |
| 352 | ||
| 353 | /* HW/EMUL specific */ | |
| 354 | if (op_type == hw_wr) | |
| 355 | op_type = OP_WR; | |
| 356 | ||
| 357 | /* EMUL on E1H is special */ | |
| 358 | if ((op_type == OP_WR_EMUL_E1H) && is_emul_e1h) | |
| 359 | op_type = OP_WR; | |
| 360 | } | |
| a2fbb9ea ET |
361 | |
| 362 | switch (op_type) { | |
| 363 | case OP_RD: | |
| 364 | REG_RD(bp, addr); | |
| 365 | break; | |
| 366 | case OP_WR: | |
| 367 | REG_WR(bp, addr, op->write.val); | |
| 368 | break; | |
| 369 | case OP_SW: | |
| 370 | bnx2x_init_str_wr(bp, addr, data, len); | |
| 371 | break; | |
| 372 | case OP_WB: | |
| ad8d3948 | 373 | bnx2x_init_wr_wb(bp, addr, data, len, 0, is_e1, 0); |
| a2fbb9ea ET |
374 | break; |
| 375 | case OP_SI: | |
| 376 | bnx2x_init_ind_wr(bp, addr, data, len); | |
| 377 | break; | |
| 378 | case OP_ZR: | |
| 379 | bnx2x_init_fill(bp, addr, 0, op->zero.len); | |
| 380 | break; | |
| 381 | case OP_ZP: | |
| ad8d3948 EG |
382 | bnx2x_init_wr_wb(bp, addr, data, len, 1, is_e1, |
| 383 | op->str_wr.data_off); | |
| 384 | break; | |
| 385 | case OP_WR_64: | |
| 386 | bnx2x_init_wr_64(bp, addr, data, len); | |
| a2fbb9ea ET |
387 | break; |
| 388 | default: | |
| ad8d3948 EG |
389 | /* happens whenever an op is of a diff HW */ |
| 390 | #if 0 | |
| 391 | DP(NETIF_MSG_HW, "skipping init operation " | |
| 392 | "index %d[%d:%d]: type %d addr 0x%x " | |
| 393 | "len %d(0x%x)\n", | |
| 394 | i, op_start, op_end, op_type, addr, len, len); | |
| 395 | #endif | |
| 396 | break; | |
| a2fbb9ea ET |
397 | } |
| 398 | } | |
| 399 | } | |
| 400 | ||
| 401 | ||
| 402 | /**************************************************************************** | |
| 403 | * PXP | |
| 404 | ****************************************************************************/ | |
| 405 | /* | |
| 406 | * This code configures the PCI read/write arbiter | |
| ad8d3948 | 407 | * which implements a weighted round robin |
| a2fbb9ea ET |
408 | * between the virtual queues in the chip. |
| 409 | * | |
| 410 | * The values were derived for each PCI max payload and max request size. | |
| 411 | * since max payload and max request size are only known at run time, | |
| 412 | * this is done as a separate init stage. | |
| 413 | */ | |
| 414 | ||
| 415 | #define NUM_WR_Q 13 | |
| 416 | #define NUM_RD_Q 29 | |
| 417 | #define MAX_RD_ORD 3 | |
| 418 | #define MAX_WR_ORD 2 | |
| 419 | ||
| 420 | /* configuration for one arbiter queue */ | |
| 421 | struct arb_line { | |
| 422 | int l; | |
| 423 | int add; | |
| 424 | int ubound; | |
| 425 | }; | |
| 426 | ||
| 427 | /* derived configuration for each read queue for each max request size */ | |
| 428 | static const struct arb_line read_arb_data[NUM_RD_Q][MAX_RD_ORD + 1] = { | |
| 429 | {{8 , 64 , 25}, {16 , 64 , 25}, {32 , 64 , 25}, {64 , 64 , 41} }, | |
| 430 | {{4 , 8 , 4}, {4 , 8 , 4}, {4 , 8 , 4}, {4 , 8 , 4} }, | |
| 431 | {{4 , 3 , 3}, {4 , 3 , 3}, {4 , 3 , 3}, {4 , 3 , 3} }, | |
| 432 | {{8 , 3 , 6}, {16 , 3 , 11}, {16 , 3 , 11}, {16 , 3 , 11} }, | |
| 433 | {{8 , 64 , 25}, {16 , 64 , 25}, {32 , 64 , 25}, {64 , 64 , 41} }, | |
| 434 | {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {64 , 3 , 41} }, | |
| 435 | {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {64 , 3 , 41} }, | |
| 436 | {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {64 , 3 , 41} }, | |
| 437 | {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {64 , 3 , 41} }, | |
| 438 | {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} }, | |
| 439 | {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} }, | |
| 440 | {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} }, | |
| 441 | {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} }, | |
| 442 | {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} }, | |
| 443 | {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} }, | |
| 444 | {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} }, | |
| 445 | {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} }, | |
| 446 | {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} }, | |
| 447 | {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} }, | |
| 448 | {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} }, | |
| 449 | {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} }, | |
| 450 | {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} }, | |
| 451 | {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} }, | |
| 452 | {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} }, | |
| 453 | {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} }, | |
| 454 | {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} }, | |
| 455 | {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} }, | |
| 456 | {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} }, | |
| 457 | {{8 , 64 , 25}, {16 , 64 , 41}, {32 , 64 , 81}, {64 , 64 , 120} } | |
| 458 | }; | |
| 459 | ||
| 460 | /* derived configuration for each write queue for each max request size */ | |
| 461 | static const struct arb_line write_arb_data[NUM_WR_Q][MAX_WR_ORD + 1] = { | |
| 462 | {{4 , 6 , 3}, {4 , 6 , 3}, {4 , 6 , 3} }, | |
| 463 | {{4 , 2 , 3}, {4 , 2 , 3}, {4 , 2 , 3} }, | |
| 464 | {{8 , 2 , 6}, {16 , 2 , 11}, {16 , 2 , 11} }, | |
| 465 | {{8 , 2 , 6}, {16 , 2 , 11}, {32 , 2 , 21} }, | |
| 466 | {{8 , 2 , 6}, {16 , 2 , 11}, {32 , 2 , 21} }, | |
| 467 | {{8 , 2 , 6}, {16 , 2 , 11}, {32 , 2 , 21} }, | |
| 468 | {{8 , 64 , 25}, {16 , 64 , 25}, {32 , 64 , 25} }, | |
| 469 | {{8 , 2 , 6}, {16 , 2 , 11}, {16 , 2 , 11} }, | |
| 470 | {{8 , 2 , 6}, {16 , 2 , 11}, {16 , 2 , 11} }, | |
| 471 | {{8 , 9 , 6}, {16 , 9 , 11}, {32 , 9 , 21} }, | |
| 472 | {{8 , 47 , 19}, {16 , 47 , 19}, {32 , 47 , 21} }, | |
| 473 | {{8 , 9 , 6}, {16 , 9 , 11}, {16 , 9 , 11} }, | |
| 474 | {{8 , 64 , 25}, {16 , 64 , 41}, {32 , 64 , 81} } | |
| 475 | }; | |
| 476 | ||
| ad8d3948 | 477 | /* register addresses for read queues */ |
| a2fbb9ea ET |
478 | static const struct arb_line read_arb_addr[NUM_RD_Q-1] = { |
| 479 | {PXP2_REG_RQ_BW_RD_L0, PXP2_REG_RQ_BW_RD_ADD0, | |
| 480 | PXP2_REG_RQ_BW_RD_UBOUND0}, | |
| 481 | {PXP2_REG_PSWRQ_BW_L1, PXP2_REG_PSWRQ_BW_ADD1, | |
| 482 | PXP2_REG_PSWRQ_BW_UB1}, | |
| 483 | {PXP2_REG_PSWRQ_BW_L2, PXP2_REG_PSWRQ_BW_ADD2, | |
| 484 | PXP2_REG_PSWRQ_BW_UB2}, | |
| 485 | {PXP2_REG_PSWRQ_BW_L3, PXP2_REG_PSWRQ_BW_ADD3, | |
| 486 | PXP2_REG_PSWRQ_BW_UB3}, | |
| 487 | {PXP2_REG_RQ_BW_RD_L4, PXP2_REG_RQ_BW_RD_ADD4, | |
| 488 | PXP2_REG_RQ_BW_RD_UBOUND4}, | |
| 489 | {PXP2_REG_RQ_BW_RD_L5, PXP2_REG_RQ_BW_RD_ADD5, | |
| 490 | PXP2_REG_RQ_BW_RD_UBOUND5}, | |
| 491 | {PXP2_REG_PSWRQ_BW_L6, PXP2_REG_PSWRQ_BW_ADD6, | |
| 492 | PXP2_REG_PSWRQ_BW_UB6}, | |
| 493 | {PXP2_REG_PSWRQ_BW_L7, PXP2_REG_PSWRQ_BW_ADD7, | |
| 494 | PXP2_REG_PSWRQ_BW_UB7}, | |
| 495 | {PXP2_REG_PSWRQ_BW_L8, PXP2_REG_PSWRQ_BW_ADD8, | |
| 496 | PXP2_REG_PSWRQ_BW_UB8}, | |
| 497 | {PXP2_REG_PSWRQ_BW_L9, PXP2_REG_PSWRQ_BW_ADD9, | |
| 498 | PXP2_REG_PSWRQ_BW_UB9}, | |
| 499 | {PXP2_REG_PSWRQ_BW_L10, PXP2_REG_PSWRQ_BW_ADD10, | |
| 500 | PXP2_REG_PSWRQ_BW_UB10}, | |
| 501 | {PXP2_REG_PSWRQ_BW_L11, PXP2_REG_PSWRQ_BW_ADD11, | |
| 502 | PXP2_REG_PSWRQ_BW_UB11}, | |
| 503 | {PXP2_REG_RQ_BW_RD_L12, PXP2_REG_RQ_BW_RD_ADD12, | |
| 504 | PXP2_REG_RQ_BW_RD_UBOUND12}, | |
| 505 | {PXP2_REG_RQ_BW_RD_L13, PXP2_REG_RQ_BW_RD_ADD13, | |
| 506 | PXP2_REG_RQ_BW_RD_UBOUND13}, | |
| 507 | {PXP2_REG_RQ_BW_RD_L14, PXP2_REG_RQ_BW_RD_ADD14, | |
| 508 | PXP2_REG_RQ_BW_RD_UBOUND14}, | |
| 509 | {PXP2_REG_RQ_BW_RD_L15, PXP2_REG_RQ_BW_RD_ADD15, | |
| 510 | PXP2_REG_RQ_BW_RD_UBOUND15}, | |
| 511 | {PXP2_REG_RQ_BW_RD_L16, PXP2_REG_RQ_BW_RD_ADD16, | |
| 512 | PXP2_REG_RQ_BW_RD_UBOUND16}, | |
| 513 | {PXP2_REG_RQ_BW_RD_L17, PXP2_REG_RQ_BW_RD_ADD17, | |
| 514 | PXP2_REG_RQ_BW_RD_UBOUND17}, | |
| 515 | {PXP2_REG_RQ_BW_RD_L18, PXP2_REG_RQ_BW_RD_ADD18, | |
| 516 | PXP2_REG_RQ_BW_RD_UBOUND18}, | |
| 517 | {PXP2_REG_RQ_BW_RD_L19, PXP2_REG_RQ_BW_RD_ADD19, | |
| 518 | PXP2_REG_RQ_BW_RD_UBOUND19}, | |
| 519 | {PXP2_REG_RQ_BW_RD_L20, PXP2_REG_RQ_BW_RD_ADD20, | |
| 520 | PXP2_REG_RQ_BW_RD_UBOUND20}, | |
| 521 | {PXP2_REG_RQ_BW_RD_L22, PXP2_REG_RQ_BW_RD_ADD22, | |
| 522 | PXP2_REG_RQ_BW_RD_UBOUND22}, | |
| 523 | {PXP2_REG_RQ_BW_RD_L23, PXP2_REG_RQ_BW_RD_ADD23, | |
| 524 | PXP2_REG_RQ_BW_RD_UBOUND23}, | |
| 525 | {PXP2_REG_RQ_BW_RD_L24, PXP2_REG_RQ_BW_RD_ADD24, | |
| 526 | PXP2_REG_RQ_BW_RD_UBOUND24}, | |
| 527 | {PXP2_REG_RQ_BW_RD_L25, PXP2_REG_RQ_BW_RD_ADD25, | |
| 528 | PXP2_REG_RQ_BW_RD_UBOUND25}, | |
| 529 | {PXP2_REG_RQ_BW_RD_L26, PXP2_REG_RQ_BW_RD_ADD26, | |
| 530 | PXP2_REG_RQ_BW_RD_UBOUND26}, | |
| 531 | {PXP2_REG_RQ_BW_RD_L27, PXP2_REG_RQ_BW_RD_ADD27, | |
| 532 | PXP2_REG_RQ_BW_RD_UBOUND27}, | |
| 533 | {PXP2_REG_PSWRQ_BW_L28, PXP2_REG_PSWRQ_BW_ADD28, | |
| 534 | PXP2_REG_PSWRQ_BW_UB28} | |
| 535 | }; | |
| 536 | ||
| ad8d3948 | 537 | /* register addresses for write queues */ |
| a2fbb9ea ET |
538 | static const struct arb_line write_arb_addr[NUM_WR_Q-1] = { |
| 539 | {PXP2_REG_PSWRQ_BW_L1, PXP2_REG_PSWRQ_BW_ADD1, | |
| 540 | PXP2_REG_PSWRQ_BW_UB1}, | |
| 541 | {PXP2_REG_PSWRQ_BW_L2, PXP2_REG_PSWRQ_BW_ADD2, | |
| 542 | PXP2_REG_PSWRQ_BW_UB2}, | |
| 543 | {PXP2_REG_PSWRQ_BW_L3, PXP2_REG_PSWRQ_BW_ADD3, | |
| 544 | PXP2_REG_PSWRQ_BW_UB3}, | |
| 545 | {PXP2_REG_PSWRQ_BW_L6, PXP2_REG_PSWRQ_BW_ADD6, | |
| 546 | PXP2_REG_PSWRQ_BW_UB6}, | |
| 547 | {PXP2_REG_PSWRQ_BW_L7, PXP2_REG_PSWRQ_BW_ADD7, | |
| 548 | PXP2_REG_PSWRQ_BW_UB7}, | |
| 549 | {PXP2_REG_PSWRQ_BW_L8, PXP2_REG_PSWRQ_BW_ADD8, | |
| 550 | PXP2_REG_PSWRQ_BW_UB8}, | |
| 551 | {PXP2_REG_PSWRQ_BW_L9, PXP2_REG_PSWRQ_BW_ADD9, | |
| 552 | PXP2_REG_PSWRQ_BW_UB9}, | |
| 553 | {PXP2_REG_PSWRQ_BW_L10, PXP2_REG_PSWRQ_BW_ADD10, | |
| 554 | PXP2_REG_PSWRQ_BW_UB10}, | |
| 555 | {PXP2_REG_PSWRQ_BW_L11, PXP2_REG_PSWRQ_BW_ADD11, | |
| 556 | PXP2_REG_PSWRQ_BW_UB11}, | |
| 557 | {PXP2_REG_PSWRQ_BW_L28, PXP2_REG_PSWRQ_BW_ADD28, | |
| 558 | PXP2_REG_PSWRQ_BW_UB28}, | |
| 559 | {PXP2_REG_RQ_BW_WR_L29, PXP2_REG_RQ_BW_WR_ADD29, | |
| 560 | PXP2_REG_RQ_BW_WR_UBOUND29}, | |
| 561 | {PXP2_REG_RQ_BW_WR_L30, PXP2_REG_RQ_BW_WR_ADD30, | |
| 562 | PXP2_REG_RQ_BW_WR_UBOUND30} | |
| 563 | }; | |
| 564 | ||
| 565 | static void bnx2x_init_pxp(struct bnx2x *bp) | |
| 566 | { | |
| 7d96567a | 567 | u16 devctl; |
| a2fbb9ea ET |
568 | int r_order, w_order; |
| 569 | u32 val, i; | |
| 570 | ||
| 571 | pci_read_config_word(bp->pdev, | |
| 7d96567a EG |
572 | bp->pcie_cap + PCI_EXP_DEVCTL, &devctl); |
| 573 | DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl); | |
| 574 | w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5); | |
| 575 | r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12); | |
| a2fbb9ea ET |
576 | |
| 577 | if (r_order > MAX_RD_ORD) { | |
| 578 | DP(NETIF_MSG_HW, "read order of %d order adjusted to %d\n", | |
| 579 | r_order, MAX_RD_ORD); | |
| 580 | r_order = MAX_RD_ORD; | |
| 581 | } | |
| 582 | if (w_order > MAX_WR_ORD) { | |
| 583 | DP(NETIF_MSG_HW, "write order of %d order adjusted to %d\n", | |
| 584 | w_order, MAX_WR_ORD); | |
| 585 | w_order = MAX_WR_ORD; | |
| 586 | } | |
| ad8d3948 EG |
587 | if (CHIP_REV_IS_FPGA(bp)) { |
| 588 | DP(NETIF_MSG_HW, "write order adjusted to 1 for FPGA\n"); | |
| 589 | w_order = 0; | |
| 590 | } | |
| a2fbb9ea ET |
591 | DP(NETIF_MSG_HW, "read order %d write order %d\n", r_order, w_order); |
| 592 | ||
| 593 | for (i = 0; i < NUM_RD_Q-1; i++) { | |
| 594 | REG_WR(bp, read_arb_addr[i].l, read_arb_data[i][r_order].l); | |
| 595 | REG_WR(bp, read_arb_addr[i].add, | |
| 596 | read_arb_data[i][r_order].add); | |
| 597 | REG_WR(bp, read_arb_addr[i].ubound, | |
| 598 | read_arb_data[i][r_order].ubound); | |
| 599 | } | |
| 600 | ||
| 601 | for (i = 0; i < NUM_WR_Q-1; i++) { | |
| 602 | if ((write_arb_addr[i].l == PXP2_REG_RQ_BW_WR_L29) || | |
| 603 | (write_arb_addr[i].l == PXP2_REG_RQ_BW_WR_L30)) { | |
| 604 | ||
| 605 | REG_WR(bp, write_arb_addr[i].l, | |
| 606 | write_arb_data[i][w_order].l); | |
| 607 | ||
| 608 | REG_WR(bp, write_arb_addr[i].add, | |
| 609 | write_arb_data[i][w_order].add); | |
| 610 | ||
| 611 | REG_WR(bp, write_arb_addr[i].ubound, | |
| 612 | write_arb_data[i][w_order].ubound); | |
| 613 | } else { | |
| 614 | ||
| 615 | val = REG_RD(bp, write_arb_addr[i].l); | |
| 616 | REG_WR(bp, write_arb_addr[i].l, | |
| 617 | val | (write_arb_data[i][w_order].l << 10)); | |
| 618 | ||
| 619 | val = REG_RD(bp, write_arb_addr[i].add); | |
| 620 | REG_WR(bp, write_arb_addr[i].add, | |
| 621 | val | (write_arb_data[i][w_order].add << 10)); | |
| 622 | ||
| 623 | val = REG_RD(bp, write_arb_addr[i].ubound); | |
| 624 | REG_WR(bp, write_arb_addr[i].ubound, | |
| 625 | val | (write_arb_data[i][w_order].ubound << 7)); | |
| 626 | } | |
| 627 | } | |
| 628 | ||
| 629 | val = write_arb_data[NUM_WR_Q-1][w_order].add; | |
| 630 | val += write_arb_data[NUM_WR_Q-1][w_order].ubound << 10; | |
| 631 | val += write_arb_data[NUM_WR_Q-1][w_order].l << 17; | |
| 632 | REG_WR(bp, PXP2_REG_PSWRQ_BW_RD, val); | |
| 633 | ||
| 634 | val = read_arb_data[NUM_RD_Q-1][r_order].add; | |
| 635 | val += read_arb_data[NUM_RD_Q-1][r_order].ubound << 10; | |
| 636 | val += read_arb_data[NUM_RD_Q-1][r_order].l << 17; | |
| 637 | REG_WR(bp, PXP2_REG_PSWRQ_BW_WR, val); | |
| 638 | ||
| 639 | REG_WR(bp, PXP2_REG_RQ_WR_MBS0, w_order); | |
| e8717a47 | 640 | REG_WR(bp, PXP2_REG_RQ_WR_MBS1, w_order); |
| a2fbb9ea | 641 | REG_WR(bp, PXP2_REG_RQ_RD_MBS0, r_order); |
| e8717a47 | 642 | REG_WR(bp, PXP2_REG_RQ_RD_MBS1, r_order); |
| a2fbb9ea | 643 | |
| e8717a47 ET |
644 | if (r_order == MAX_RD_ORD) |
| 645 | REG_WR(bp, PXP2_REG_RQ_PDR_LIMIT, 0xe00); | |
| 646 | ||
| 647 | REG_WR(bp, PXP2_REG_WR_USDMDP_TH, (0x18 << w_order)); | |
| ad8d3948 EG |
648 | |
| 649 | if (CHIP_IS_E1H(bp)) { | |
| 650 | REG_WR(bp, PXP2_REG_WR_HC_MPS, w_order+1); | |
| 651 | REG_WR(bp, PXP2_REG_WR_USDM_MPS, w_order+1); | |
| 652 | REG_WR(bp, PXP2_REG_WR_CSDM_MPS, w_order+1); | |
| 653 | REG_WR(bp, PXP2_REG_WR_TSDM_MPS, w_order+1); | |
| 654 | REG_WR(bp, PXP2_REG_WR_XSDM_MPS, w_order+1); | |
| 655 | REG_WR(bp, PXP2_REG_WR_QM_MPS, w_order+1); | |
| 656 | REG_WR(bp, PXP2_REG_WR_TM_MPS, w_order+1); | |
| 657 | REG_WR(bp, PXP2_REG_WR_SRC_MPS, w_order+1); | |
| 658 | REG_WR(bp, PXP2_REG_WR_DBG_MPS, w_order+1); | |
| 659 | REG_WR(bp, PXP2_REG_WR_DMAE_MPS, 2); /* DMAE is special */ | |
| 660 | REG_WR(bp, PXP2_REG_WR_CDU_MPS, w_order+1); | |
| 661 | } | |
| a2fbb9ea ET |
662 | } |
| 663 | ||
| 664 | ||
| 665 | /**************************************************************************** | |
| 666 | * CDU | |
| 667 | ****************************************************************************/ | |
| 668 | ||
| 669 | #define CDU_REGION_NUMBER_XCM_AG 2 | |
| 670 | #define CDU_REGION_NUMBER_UCM_AG 4 | |
| 671 | ||
| 672 | /** | |
| 673 | * String-to-compress [31:8] = CID (all 24 bits) | |
| 674 | * String-to-compress [7:4] = Region | |
| 675 | * String-to-compress [3:0] = Type | |
| 676 | */ | |
| 677 | #define CDU_VALID_DATA(_cid, _region, _type) \ | |
| 678 | (((_cid) << 8) | (((_region) & 0xf) << 4) | (((_type) & 0xf))) | |
| 679 | #define CDU_CRC8(_cid, _region, _type) \ | |
| 680 | calc_crc8(CDU_VALID_DATA(_cid, _region, _type), 0xff) | |
| 681 | #define CDU_RSRVD_VALUE_TYPE_A(_cid, _region, _type) \ | |
| 682 | (0x80 | (CDU_CRC8(_cid, _region, _type) & 0x7f)) | |
| 683 | #define CDU_RSRVD_VALUE_TYPE_B(_crc, _type) \ | |
| 684 | (0x80 | ((_type) & 0xf << 3) | (CDU_CRC8(_cid, _region, _type) & 0x7)) | |
| 685 | #define CDU_RSRVD_INVALIDATE_CONTEXT_VALUE(_val) ((_val) & ~0x80) | |
| 686 | ||
| 687 | /***************************************************************************** | |
| 688 | * Description: | |
| 689 | * Calculates crc 8 on a word value: polynomial 0-1-2-8 | |
| 690 | * Code was translated from Verilog. | |
| 691 | ****************************************************************************/ | |
| 692 | static u8 calc_crc8(u32 data, u8 crc) | |
| 693 | { | |
| 694 | u8 D[32]; | |
| 695 | u8 NewCRC[8]; | |
| 696 | u8 C[8]; | |
| 697 | u8 crc_res; | |
| 698 | u8 i; | |
| 699 | ||
| 700 | /* split the data into 31 bits */ | |
| 701 | for (i = 0; i < 32; i++) { | |
| 702 | D[i] = data & 1; | |
| 703 | data = data >> 1; | |
| 704 | } | |
| 705 | ||
| 706 | /* split the crc into 8 bits */ | |
| 707 | for (i = 0; i < 8; i++) { | |
| 708 | C[i] = crc & 1; | |
| 709 | crc = crc >> 1; | |
| 710 | } | |
| 711 | ||
| 712 | NewCRC[0] = D[31] ^ D[30] ^ D[28] ^ D[23] ^ D[21] ^ D[19] ^ D[18] ^ | |
| 713 | D[16] ^ D[14] ^ D[12] ^ D[8] ^ D[7] ^ D[6] ^ D[0] ^ C[4] ^ | |
| 714 | C[6] ^ C[7]; | |
| 715 | NewCRC[1] = D[30] ^ D[29] ^ D[28] ^ D[24] ^ D[23] ^ D[22] ^ D[21] ^ | |
| 716 | D[20] ^ D[18] ^ D[17] ^ D[16] ^ D[15] ^ D[14] ^ D[13] ^ | |
| 717 | D[12] ^ D[9] ^ D[6] ^ D[1] ^ D[0] ^ C[0] ^ C[4] ^ C[5] ^ C[6]; | |
| 718 | NewCRC[2] = D[29] ^ D[28] ^ D[25] ^ D[24] ^ D[22] ^ D[17] ^ D[15] ^ | |
| 719 | D[13] ^ D[12] ^ D[10] ^ D[8] ^ D[6] ^ D[2] ^ D[1] ^ D[0] ^ | |
| 720 | C[0] ^ C[1] ^ C[4] ^ C[5]; | |
| 721 | NewCRC[3] = D[30] ^ D[29] ^ D[26] ^ D[25] ^ D[23] ^ D[18] ^ D[16] ^ | |
| 722 | D[14] ^ D[13] ^ D[11] ^ D[9] ^ D[7] ^ D[3] ^ D[2] ^ D[1] ^ | |
| 723 | C[1] ^ C[2] ^ C[5] ^ C[6]; | |
| 724 | NewCRC[4] = D[31] ^ D[30] ^ D[27] ^ D[26] ^ D[24] ^ D[19] ^ D[17] ^ | |
| 725 | D[15] ^ D[14] ^ D[12] ^ D[10] ^ D[8] ^ D[4] ^ D[3] ^ D[2] ^ | |
| 726 | C[0] ^ C[2] ^ C[3] ^ C[6] ^ C[7]; | |
| 727 | NewCRC[5] = D[31] ^ D[28] ^ D[27] ^ D[25] ^ D[20] ^ D[18] ^ D[16] ^ | |
| 728 | D[15] ^ D[13] ^ D[11] ^ D[9] ^ D[5] ^ D[4] ^ D[3] ^ C[1] ^ | |
| 729 | C[3] ^ C[4] ^ C[7]; | |
| 730 | NewCRC[6] = D[29] ^ D[28] ^ D[26] ^ D[21] ^ D[19] ^ D[17] ^ D[16] ^ | |
| 731 | D[14] ^ D[12] ^ D[10] ^ D[6] ^ D[5] ^ D[4] ^ C[2] ^ C[4] ^ | |
| 732 | C[5]; | |
| 733 | NewCRC[7] = D[30] ^ D[29] ^ D[27] ^ D[22] ^ D[20] ^ D[18] ^ D[17] ^ | |
| 734 | D[15] ^ D[13] ^ D[11] ^ D[7] ^ D[6] ^ D[5] ^ C[3] ^ C[5] ^ | |
| 735 | C[6]; | |
| 736 | ||
| 737 | crc_res = 0; | |
| 738 | for (i = 0; i < 8; i++) | |
| 739 | crc_res |= (NewCRC[i] << i); | |
| 740 | ||
| 741 | return crc_res; | |
| 742 | } | |
| 743 | ||
| 33471629 | 744 | /* registers addresses are not in order |
| ad8d3948 EG |
745 | so these arrays help simplify the code */ |
| 746 | static const int cm_start[E1H_FUNC_MAX][9] = { | |
| 747 | {MISC_FUNC0_START, TCM_FUNC0_START, UCM_FUNC0_START, CCM_FUNC0_START, | |
| 748 | XCM_FUNC0_START, TSEM_FUNC0_START, USEM_FUNC0_START, CSEM_FUNC0_START, | |
| 749 | XSEM_FUNC0_START}, | |
| 750 | {MISC_FUNC1_START, TCM_FUNC1_START, UCM_FUNC1_START, CCM_FUNC1_START, | |
| 751 | XCM_FUNC1_START, TSEM_FUNC1_START, USEM_FUNC1_START, CSEM_FUNC1_START, | |
| 752 | XSEM_FUNC1_START}, | |
| 753 | {MISC_FUNC2_START, TCM_FUNC2_START, UCM_FUNC2_START, CCM_FUNC2_START, | |
| 754 | XCM_FUNC2_START, TSEM_FUNC2_START, USEM_FUNC2_START, CSEM_FUNC2_START, | |
| 755 | XSEM_FUNC2_START}, | |
| 756 | {MISC_FUNC3_START, TCM_FUNC3_START, UCM_FUNC3_START, CCM_FUNC3_START, | |
| 757 | XCM_FUNC3_START, TSEM_FUNC3_START, USEM_FUNC3_START, CSEM_FUNC3_START, | |
| 758 | XSEM_FUNC3_START}, | |
| 759 | {MISC_FUNC4_START, TCM_FUNC4_START, UCM_FUNC4_START, CCM_FUNC4_START, | |
| 760 | XCM_FUNC4_START, TSEM_FUNC4_START, USEM_FUNC4_START, CSEM_FUNC4_START, | |
| 761 | XSEM_FUNC4_START}, | |
| 762 | {MISC_FUNC5_START, TCM_FUNC5_START, UCM_FUNC5_START, CCM_FUNC5_START, | |
| 763 | XCM_FUNC5_START, TSEM_FUNC5_START, USEM_FUNC5_START, CSEM_FUNC5_START, | |
| 764 | XSEM_FUNC5_START}, | |
| 765 | {MISC_FUNC6_START, TCM_FUNC6_START, UCM_FUNC6_START, CCM_FUNC6_START, | |
| 766 | XCM_FUNC6_START, TSEM_FUNC6_START, USEM_FUNC6_START, CSEM_FUNC6_START, | |
| 767 | XSEM_FUNC6_START}, | |
| 768 | {MISC_FUNC7_START, TCM_FUNC7_START, UCM_FUNC7_START, CCM_FUNC7_START, | |
| 769 | XCM_FUNC7_START, TSEM_FUNC7_START, USEM_FUNC7_START, CSEM_FUNC7_START, | |
| 770 | XSEM_FUNC7_START} | |
| 771 | }; | |
| 772 | ||
| 773 | static const int cm_end[E1H_FUNC_MAX][9] = { | |
| 774 | {MISC_FUNC0_END, TCM_FUNC0_END, UCM_FUNC0_END, CCM_FUNC0_END, | |
| 775 | XCM_FUNC0_END, TSEM_FUNC0_END, USEM_FUNC0_END, CSEM_FUNC0_END, | |
| 776 | XSEM_FUNC0_END}, | |
| 777 | {MISC_FUNC1_END, TCM_FUNC1_END, UCM_FUNC1_END, CCM_FUNC1_END, | |
| 778 | XCM_FUNC1_END, TSEM_FUNC1_END, USEM_FUNC1_END, CSEM_FUNC1_END, | |
| 779 | XSEM_FUNC1_END}, | |
| 780 | {MISC_FUNC2_END, TCM_FUNC2_END, UCM_FUNC2_END, CCM_FUNC2_END, | |
| 781 | XCM_FUNC2_END, TSEM_FUNC2_END, USEM_FUNC2_END, CSEM_FUNC2_END, | |
| 782 | XSEM_FUNC2_END}, | |
| 783 | {MISC_FUNC3_END, TCM_FUNC3_END, UCM_FUNC3_END, CCM_FUNC3_END, | |
| 784 | XCM_FUNC3_END, TSEM_FUNC3_END, USEM_FUNC3_END, CSEM_FUNC3_END, | |
| 785 | XSEM_FUNC3_END}, | |
| 786 | {MISC_FUNC4_END, TCM_FUNC4_END, UCM_FUNC4_END, CCM_FUNC4_END, | |
| 787 | XCM_FUNC4_END, TSEM_FUNC4_END, USEM_FUNC4_END, CSEM_FUNC4_END, | |
| 788 | XSEM_FUNC4_END}, | |
| 789 | {MISC_FUNC5_END, TCM_FUNC5_END, UCM_FUNC5_END, CCM_FUNC5_END, | |
| 790 | XCM_FUNC5_END, TSEM_FUNC5_END, USEM_FUNC5_END, CSEM_FUNC5_END, | |
| 791 | XSEM_FUNC5_END}, | |
| 792 | {MISC_FUNC6_END, TCM_FUNC6_END, UCM_FUNC6_END, CCM_FUNC6_END, | |
| 793 | XCM_FUNC6_END, TSEM_FUNC6_END, USEM_FUNC6_END, CSEM_FUNC6_END, | |
| 794 | XSEM_FUNC6_END}, | |
| 795 | {MISC_FUNC7_END, TCM_FUNC7_END, UCM_FUNC7_END, CCM_FUNC7_END, | |
| 796 | XCM_FUNC7_END, TSEM_FUNC7_END, USEM_FUNC7_END, CSEM_FUNC7_END, | |
| 797 | XSEM_FUNC7_END}, | |
| 798 | }; | |
| 799 | ||
| 800 | static const int hc_limits[E1H_FUNC_MAX][2] = { | |
| 801 | {HC_FUNC0_START, HC_FUNC0_END}, | |
| 802 | {HC_FUNC1_START, HC_FUNC1_END}, | |
| 803 | {HC_FUNC2_START, HC_FUNC2_END}, | |
| 804 | {HC_FUNC3_START, HC_FUNC3_END}, | |
| 805 | {HC_FUNC4_START, HC_FUNC4_END}, | |
| 806 | {HC_FUNC5_START, HC_FUNC5_END}, | |
| 807 | {HC_FUNC6_START, HC_FUNC6_END}, | |
| 808 | {HC_FUNC7_START, HC_FUNC7_END} | |
| 809 | }; | |
| a2fbb9ea ET |
810 | |
| 811 | #endif /* BNX2X_INIT_H */ | |
| 812 |