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bnx2x: Enable FC when parallel-detect is used
[deliverable/linux.git] / drivers / net / bnx2x_link.c
CommitLineData
d05c26ce 1/* Copyright 2008-2009 Broadcom Corporation
ea4e040a
YR		 2 *
3 * Unless you and Broadcom execute a separate written software license
4 * agreement governing use of this software, this software is licensed to you
5 * under the terms of the GNU General Public License version 2, available
6 * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
7 *
8 * Notwithstanding the above, under no circumstances may you combine this
9 * software in any way with any other Broadcom software provided under a
10 * license other than the GPL, without Broadcom's express prior written
11 * consent.
12 *
13 * Written by Yaniv Rosner
14 *
15 */
16
17#include <linux/kernel.h>
18#include <linux/errno.h>
19#include <linux/pci.h>
20#include <linux/netdevice.h>
21#include <linux/delay.h>
22#include <linux/ethtool.h>
23#include <linux/mutex.h>
ea4e040a 24
ea4e040a
YR		 25#include "bnx2x.h"
26
27/********************************************************/
3196a88a 28#define ETH_HLEN 14
ea4e040a
YR		 29#define ETH_OVREHEAD (ETH_HLEN + 8)/* 8 for CRC + VLAN*/
30#define ETH_MIN_PACKET_SIZE 60
31#define ETH_MAX_PACKET_SIZE 1500
32#define ETH_MAX_JUMBO_PACKET_SIZE 9600
33#define MDIO_ACCESS_TIMEOUT 1000
34#define BMAC_CONTROL_RX_ENABLE 2
ea4e040a
YR		 35
36/***********************************************************/
3196a88a 37/* Shortcut definitions */
ea4e040a
YR		 38/***********************************************************/
39
2f904460
EG		 40#define NIG_LATCH_BC_ENABLE_MI_INT 0
41
42#define NIG_STATUS_EMAC0_MI_INT \
43 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT
ea4e040a
YR		 44#define NIG_STATUS_XGXS0_LINK10G \
45 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G
46#define NIG_STATUS_XGXS0_LINK_STATUS \
47 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS
48#define NIG_STATUS_XGXS0_LINK_STATUS_SIZE \
49 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE
50#define NIG_STATUS_SERDES0_LINK_STATUS \
51 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS
52#define NIG_MASK_MI_INT \
53 NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT
54#define NIG_MASK_XGXS0_LINK10G \
55 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G
56#define NIG_MASK_XGXS0_LINK_STATUS \
57 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS
58#define NIG_MASK_SERDES0_LINK_STATUS \
59 NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS
60
61#define MDIO_AN_CL73_OR_37_COMPLETE \
62 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \
63 MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE)
64
65#define XGXS_RESET_BITS \
66 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW | \
67 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ | \
68 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN | \
69 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \
70 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB)
71
72#define SERDES_RESET_BITS \
73 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \
74 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ | \
75 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN | \
76 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD)
77
78#define AUTONEG_CL37 SHARED_HW_CFG_AN_ENABLE_CL37
79#define AUTONEG_CL73 SHARED_HW_CFG_AN_ENABLE_CL73
3196a88a
EG		 80#define AUTONEG_BAM SHARED_HW_CFG_AN_ENABLE_BAM
81#define AUTONEG_PARALLEL \
ea4e040a 82 SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION
3196a88a 83#define AUTONEG_SGMII_FIBER_AUTODET \
ea4e040a 84 SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT
3196a88a 85#define AUTONEG_REMOTE_PHY SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY
ea4e040a
YR		 86
87#define GP_STATUS_PAUSE_RSOLUTION_TXSIDE \
88 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE
89#define GP_STATUS_PAUSE_RSOLUTION_RXSIDE \
90 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE
91#define GP_STATUS_SPEED_MASK \
92 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK
93#define GP_STATUS_10M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M
94#define GP_STATUS_100M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M
95#define GP_STATUS_1G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G
96#define GP_STATUS_2_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G
97#define GP_STATUS_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G
98#define GP_STATUS_6G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G
99#define GP_STATUS_10G_HIG \
100 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG
101#define GP_STATUS_10G_CX4 \
102 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4
103#define GP_STATUS_12G_HIG \
104 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG
105#define GP_STATUS_12_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G
106#define GP_STATUS_13G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G
107#define GP_STATUS_15G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G
108#define GP_STATUS_16G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G
109#define GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX
110#define GP_STATUS_10G_KX4 \
111 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4
112
113#define LINK_10THD LINK_STATUS_SPEED_AND_DUPLEX_10THD
114#define LINK_10TFD LINK_STATUS_SPEED_AND_DUPLEX_10TFD
115#define LINK_100TXHD LINK_STATUS_SPEED_AND_DUPLEX_100TXHD
116#define LINK_100T4 LINK_STATUS_SPEED_AND_DUPLEX_100T4
117#define LINK_100TXFD LINK_STATUS_SPEED_AND_DUPLEX_100TXFD
118#define LINK_1000THD LINK_STATUS_SPEED_AND_DUPLEX_1000THD
119#define LINK_1000TFD LINK_STATUS_SPEED_AND_DUPLEX_1000TFD
120#define LINK_1000XFD LINK_STATUS_SPEED_AND_DUPLEX_1000XFD
121#define LINK_2500THD LINK_STATUS_SPEED_AND_DUPLEX_2500THD
122#define LINK_2500TFD LINK_STATUS_SPEED_AND_DUPLEX_2500TFD
123#define LINK_2500XFD LINK_STATUS_SPEED_AND_DUPLEX_2500XFD
124#define LINK_10GTFD LINK_STATUS_SPEED_AND_DUPLEX_10GTFD
125#define LINK_10GXFD LINK_STATUS_SPEED_AND_DUPLEX_10GXFD
126#define LINK_12GTFD LINK_STATUS_SPEED_AND_DUPLEX_12GTFD
127#define LINK_12GXFD LINK_STATUS_SPEED_AND_DUPLEX_12GXFD
128#define LINK_12_5GTFD LINK_STATUS_SPEED_AND_DUPLEX_12_5GTFD
129#define LINK_12_5GXFD LINK_STATUS_SPEED_AND_DUPLEX_12_5GXFD
130#define LINK_13GTFD LINK_STATUS_SPEED_AND_DUPLEX_13GTFD
131#define LINK_13GXFD LINK_STATUS_SPEED_AND_DUPLEX_13GXFD
132#define LINK_15GTFD LINK_STATUS_SPEED_AND_DUPLEX_15GTFD
133#define LINK_15GXFD LINK_STATUS_SPEED_AND_DUPLEX_15GXFD
134#define LINK_16GTFD LINK_STATUS_SPEED_AND_DUPLEX_16GTFD
135#define LINK_16GXFD LINK_STATUS_SPEED_AND_DUPLEX_16GXFD
136
137#define PHY_XGXS_FLAG 0x1
138#define PHY_SGMII_FLAG 0x2
139#define PHY_SERDES_FLAG 0x4
140
589abe3a
EG		 141/* */
142#define SFP_EEPROM_CON_TYPE_ADDR 0x2
143 #define SFP_EEPROM_CON_TYPE_VAL_LC 0x7
144 #define SFP_EEPROM_CON_TYPE_VAL_COPPER 0x21
145
4d295db0
EG		 146
147#define SFP_EEPROM_COMP_CODE_ADDR 0x3
148 #define SFP_EEPROM_COMP_CODE_SR_MASK (1<<4)
149 #define SFP_EEPROM_COMP_CODE_LR_MASK (1<<5)
150 #define SFP_EEPROM_COMP_CODE_LRM_MASK (1<<6)
151
589abe3a
EG		 152#define SFP_EEPROM_FC_TX_TECH_ADDR 0x8
153 #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4
154 #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE 0x8
4d295db0 155
589abe3a
EG		 156#define SFP_EEPROM_OPTIONS_ADDR 0x40
157 #define SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1
158#define SFP_EEPROM_OPTIONS_SIZE 2
159
4d295db0
EG		 160#define EDC_MODE_LINEAR 0x0022
161#define EDC_MODE_LIMITING 0x0044
162#define EDC_MODE_PASSIVE_DAC 0x0055
163
164
589abe3a 165
ea4e040a
YR		 166/**********************************************************/
167/* INTERFACE */
168/**********************************************************/
169#define CL45_WR_OVER_CL22(_bp, _port, _phy_addr, _bank, _addr, _val) \
170 bnx2x_cl45_write(_bp, _port, 0, _phy_addr, \
171 DEFAULT_PHY_DEV_ADDR, \
172 (_bank + (_addr & 0xf)), \
173 _val)
174
175#define CL45_RD_OVER_CL22(_bp, _port, _phy_addr, _bank, _addr, _val) \
176 bnx2x_cl45_read(_bp, _port, 0, _phy_addr, \
177 DEFAULT_PHY_DEV_ADDR, \
178 (_bank + (_addr & 0xf)), \
179 _val)
180
c1b73990 181static void bnx2x_set_serdes_access(struct link_params *params)
ea4e040a
YR		 182{
183 struct bnx2x *bp = params->bp;
c1b73990 184 u32 emac_base = (params->port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
ab6ad5a4 185
c1b73990
EG		 186 /* Set Clause 22 */
187 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + params->port*0x10, 1);
188 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000);
189 udelay(500);
190 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f);
191 udelay(500);
192 /* Set Clause 45 */
193 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + params->port*0x10, 0);
194}
195static void bnx2x_set_phy_mdio(struct link_params *params, u8 phy_flags)
196{
197 struct bnx2x *bp = params->bp;
ab6ad5a4 198
c1b73990
EG		 199 if (phy_flags & PHY_XGXS_FLAG) {
200 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_ST +
201 params->port*0x18, 0);
202 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + params->port*0x18,
203 DEFAULT_PHY_DEV_ADDR);
204 } else {
205 bnx2x_set_serdes_access(params);
206
207 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_DEVAD +
208 params->port*0x10,
209 DEFAULT_PHY_DEV_ADDR);
210 }
ea4e040a
YR		 211}
212
213static u32 bnx2x_bits_en(struct bnx2x *bp, u32 reg, u32 bits)
214{
215 u32 val = REG_RD(bp, reg);
216
217 val |= bits;
218 REG_WR(bp, reg, val);
219 return val;
220}
221
222static u32 bnx2x_bits_dis(struct bnx2x *bp, u32 reg, u32 bits)
223{
224 u32 val = REG_RD(bp, reg);
225
226 val &= ~bits;
227 REG_WR(bp, reg, val);
228 return val;
229}
230
231static void bnx2x_emac_init(struct link_params *params,
232 struct link_vars *vars)
233{
234 /* reset and unreset the emac core */
235 struct bnx2x *bp = params->bp;
236 u8 port = params->port;
237 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
238 u32 val;
239 u16 timeout;
240
241 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
242 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
243 udelay(5);
244 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
245 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
246
247 /* init emac - use read-modify-write */
248 /* self clear reset */
249 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
3196a88a 250 EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_RESET));
ea4e040a
YR		 251
252 timeout = 200;
3196a88a 253 do {
ea4e040a
YR		 254 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
255 DP(NETIF_MSG_LINK, "EMAC reset reg is %u\n", val);
256 if (!timeout) {
257 DP(NETIF_MSG_LINK, "EMAC timeout!\n");
258 return;
259 }
260 timeout--;
3196a88a 261 } while (val & EMAC_MODE_RESET);
ea4e040a
YR		 262
263 /* Set mac address */
264 val = ((params->mac_addr[0] << 8) |
265 params->mac_addr[1]);
3196a88a 266 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH, val);
ea4e040a
YR		 267
268 val = ((params->mac_addr[2] << 24) |
269 (params->mac_addr[3] << 16) |
270 (params->mac_addr[4] << 8) |
271 params->mac_addr[5]);
3196a88a 272 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + 4, val);
ea4e040a
YR		 273}
274
275static u8 bnx2x_emac_enable(struct link_params *params,
276 struct link_vars *vars, u8 lb)
277{
278 struct bnx2x *bp = params->bp;
279 u8 port = params->port;
280 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
281 u32 val;
282
283 DP(NETIF_MSG_LINK, "enabling EMAC\n");
284
285 /* enable emac and not bmac */
286 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 1);
287
288 /* for paladium */
289 if (CHIP_REV_IS_EMUL(bp)) {
290 /* Use lane 1 (of lanes 0-3) */
291 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 1);
292 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL +
293 port*4, 1);
294 }
295 /* for fpga */
296 else
297
298 if (CHIP_REV_IS_FPGA(bp)) {
299 /* Use lane 1 (of lanes 0-3) */
300 DP(NETIF_MSG_LINK, "bnx2x_emac_enable: Setting FPGA\n");
301
302 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 1);
303 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4,
304 0);
305 } else
306 /* ASIC */
307 if (vars->phy_flags & PHY_XGXS_FLAG) {
308 u32 ser_lane = ((params->lane_config &
309 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
310 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
311
312 DP(NETIF_MSG_LINK, "XGXS\n");
313 /* select the master lanes (out of 0-3) */
314 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 +
315 port*4, ser_lane);
316 /* select XGXS */
317 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL +
318 port*4, 1);
319
320 } else { /* SerDes */
321 DP(NETIF_MSG_LINK, "SerDes\n");
322 /* select SerDes */
323 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL +
324 port*4, 0);
325 }
326
811a2f2d
EG		 327 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
328 EMAC_RX_MODE_RESET);
329 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
330 EMAC_TX_MODE_RESET);
ea4e040a
YR		 331
332 if (CHIP_REV_IS_SLOW(bp)) {
333 /* config GMII mode */
334 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
3196a88a 335 EMAC_WR(bp, EMAC_REG_EMAC_MODE,
ea4e040a
YR		 336 (val | EMAC_MODE_PORT_GMII));
337 } else { /* ASIC */
338 /* pause enable/disable */
339 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
340 EMAC_RX_MODE_FLOW_EN);
c0700f90 341 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
ea4e040a
YR		 342 bnx2x_bits_en(bp, emac_base +
343 EMAC_REG_EMAC_RX_MODE,
344 EMAC_RX_MODE_FLOW_EN);
345
346 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
8c99e7b0
YR		 347 (EMAC_TX_MODE_EXT_PAUSE_EN |
348 EMAC_TX_MODE_FLOW_EN));
c0700f90 349 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
ea4e040a
YR		 350 bnx2x_bits_en(bp, emac_base +
351 EMAC_REG_EMAC_TX_MODE,
8c99e7b0
YR		 352 (EMAC_TX_MODE_EXT_PAUSE_EN |
353 EMAC_TX_MODE_FLOW_EN));
ea4e040a
YR		 354 }
355
356 /* KEEP_VLAN_TAG, promiscuous */
357 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE);
358 val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS;
3196a88a 359 EMAC_WR(bp, EMAC_REG_EMAC_RX_MODE, val);
ea4e040a
YR		 360
361 /* Set Loopback */
362 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
363 if (lb)
364 val |= 0x810;
365 else
366 val &= ~0x810;
3196a88a 367 EMAC_WR(bp, EMAC_REG_EMAC_MODE, val);
ea4e040a 368
6c55c3cd
EG		 369 /* enable emac */
370 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 1);
371
ea4e040a 372 /* enable emac for jumbo packets */
3196a88a 373 EMAC_WR(bp, EMAC_REG_EMAC_RX_MTU_SIZE,
ea4e040a
YR		 374 (EMAC_RX_MTU_SIZE_JUMBO_ENA |
375 (ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD)));
376
377 /* strip CRC */
378 REG_WR(bp, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port*4, 0x1);
379
380 /* disable the NIG in/out to the bmac */
381 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x0);
382 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, 0x0);
383 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x0);
384
385 /* enable the NIG in/out to the emac */
386 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x1);
387 val = 0;
c0700f90 388 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
ea4e040a
YR		 389 val = 1;
390
391 REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, val);
392 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x1);
393
394 if (CHIP_REV_IS_EMUL(bp)) {
395 /* take the BigMac out of reset */
396 REG_WR(bp,
397 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
398 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
399
400 /* enable access for bmac registers */
401 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);
6f65497b
EG		 402 } else
403 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x0);
ea4e040a
YR		 404
405 vars->mac_type = MAC_TYPE_EMAC;
406 return 0;
407}
408
409
410
411static u8 bnx2x_bmac_enable(struct link_params *params, struct link_vars *vars,
412 u8 is_lb)
413{
414 struct bnx2x *bp = params->bp;
415 u8 port = params->port;
416 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
417 NIG_REG_INGRESS_BMAC0_MEM;
418 u32 wb_data[2];
419 u32 val;
420
421 DP(NETIF_MSG_LINK, "Enabling BigMAC\n");
422 /* reset and unreset the BigMac */
423 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
424 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
425 msleep(1);
426
427 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
428 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
429
430 /* enable access for bmac registers */
431 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);
432
433 /* XGXS control */
434 wb_data[0] = 0x3c;
435 wb_data[1] = 0;
436 REG_WR_DMAE(bp, bmac_addr +
437 BIGMAC_REGISTER_BMAC_XGXS_CONTROL,
438 wb_data, 2);
439
440 /* tx MAC SA */
441 wb_data[0] = ((params->mac_addr[2] << 24) |
442 (params->mac_addr[3] << 16) |
443 (params->mac_addr[4] << 8) |
444 params->mac_addr[5]);
445 wb_data[1] = ((params->mac_addr[0] << 8) |
446 params->mac_addr[1]);
447 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR,
448 wb_data, 2);
449
450 /* tx control */
451 val = 0xc0;
c0700f90 452 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
ea4e040a
YR		 453 val |= 0x800000;
454 wb_data[0] = val;
455 wb_data[1] = 0;
456 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_CONTROL,
457 wb_data, 2);
458
459 /* mac control */
460 val = 0x3;
461 if (is_lb) {
462 val |= 0x4;
463 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
464 }
465 wb_data[0] = val;
466 wb_data[1] = 0;
467 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL,
468 wb_data, 2);
469
ea4e040a
YR		 470 /* set rx mtu */
471 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
472 wb_data[1] = 0;
473 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE,
474 wb_data, 2);
475
476 /* rx control set to don't strip crc */
477 val = 0x14;
c0700f90 478 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
ea4e040a
YR		 479 val |= 0x20;
480 wb_data[0] = val;
481 wb_data[1] = 0;
482 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_CONTROL,
483 wb_data, 2);
484
485 /* set tx mtu */
486 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
487 wb_data[1] = 0;
488 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE,
489 wb_data, 2);
490
491 /* set cnt max size */
492 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
493 wb_data[1] = 0;
494 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE,
495 wb_data, 2);
496
497 /* configure safc */
498 wb_data[0] = 0x1000200;
499 wb_data[1] = 0;
500 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS,
501 wb_data, 2);
502 /* fix for emulation */
503 if (CHIP_REV_IS_EMUL(bp)) {
504 wb_data[0] = 0xf000;
505 wb_data[1] = 0;
506 REG_WR_DMAE(bp,
507 bmac_addr + BIGMAC_REGISTER_TX_PAUSE_THRESHOLD,
508 wb_data, 2);
509 }
510
511 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0x1);
512 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 0x0);
513 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 0x0);
514 val = 0;
c0700f90 515 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
ea4e040a
YR		 516 val = 1;
517 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, val);
518 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x0);
519 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x0);
520 REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, 0x0);
521 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x1);
522 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x1);
523
524 vars->mac_type = MAC_TYPE_BMAC;
525 return 0;
526}
527
528static void bnx2x_phy_deassert(struct link_params *params, u8 phy_flags)
529{
530 struct bnx2x *bp = params->bp;
531 u32 val;
532
533 if (phy_flags & PHY_XGXS_FLAG) {
534 DP(NETIF_MSG_LINK, "bnx2x_phy_deassert:XGXS\n");
535 val = XGXS_RESET_BITS;
536
537 } else { /* SerDes */
538 DP(NETIF_MSG_LINK, "bnx2x_phy_deassert:SerDes\n");
539 val = SERDES_RESET_BITS;
540 }
541
542 val = val << (params->port*16);
543
544 /* reset and unreset the SerDes/XGXS */
545 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR,
546 val);
547 udelay(500);
548 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET,
549 val);
c1b73990 550 bnx2x_set_phy_mdio(params, phy_flags);
ea4e040a
YR		 551}
552
553void bnx2x_link_status_update(struct link_params *params,
554 struct link_vars *vars)
555{
556 struct bnx2x *bp = params->bp;
557 u8 link_10g;
558 u8 port = params->port;
559
560 if (params->switch_cfg == SWITCH_CFG_1G)
561 vars->phy_flags = PHY_SERDES_FLAG;
562 else
563 vars->phy_flags = PHY_XGXS_FLAG;
564 vars->link_status = REG_RD(bp, params->shmem_base +
565 offsetof(struct shmem_region,
566 port_mb[port].link_status));
567
568 vars->link_up = (vars->link_status & LINK_STATUS_LINK_UP);
569
570 if (vars->link_up) {
571 DP(NETIF_MSG_LINK, "phy link up\n");
572
573 vars->phy_link_up = 1;
574 vars->duplex = DUPLEX_FULL;
575 switch (vars->link_status &
576 LINK_STATUS_SPEED_AND_DUPLEX_MASK) {
577 case LINK_10THD:
578 vars->duplex = DUPLEX_HALF;
579 /* fall thru */
580 case LINK_10TFD:
581 vars->line_speed = SPEED_10;
582 break;
583
584 case LINK_100TXHD:
585 vars->duplex = DUPLEX_HALF;
586 /* fall thru */
587 case LINK_100T4:
588 case LINK_100TXFD:
589 vars->line_speed = SPEED_100;
590 break;
591
592 case LINK_1000THD:
593 vars->duplex = DUPLEX_HALF;
594 /* fall thru */
595 case LINK_1000TFD:
596 vars->line_speed = SPEED_1000;
597 break;
598
599 case LINK_2500THD:
600 vars->duplex = DUPLEX_HALF;
601 /* fall thru */
602 case LINK_2500TFD:
603 vars->line_speed = SPEED_2500;
604 break;
605
606 case LINK_10GTFD:
607 vars->line_speed = SPEED_10000;
608 break;
609
610 case LINK_12GTFD:
611 vars->line_speed = SPEED_12000;
612 break;
613
614 case LINK_12_5GTFD:
615 vars->line_speed = SPEED_12500;
616 break;
617
618 case LINK_13GTFD:
619 vars->line_speed = SPEED_13000;
620 break;
621
622 case LINK_15GTFD:
623 vars->line_speed = SPEED_15000;
624 break;
625
626 case LINK_16GTFD:
627 vars->line_speed = SPEED_16000;
628 break;
629
630 default:
631 break;
632 }
633
634 if (vars->link_status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED)
c0700f90 635 vars->flow_ctrl |= BNX2X_FLOW_CTRL_TX;
ea4e040a 636 else
c0700f90 637 vars->flow_ctrl &= ~BNX2X_FLOW_CTRL_TX;
ea4e040a
YR		 638
639 if (vars->link_status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED)
c0700f90 640 vars->flow_ctrl |= BNX2X_FLOW_CTRL_RX;
ea4e040a 641 else
c0700f90 642 vars->flow_ctrl &= ~BNX2X_FLOW_CTRL_RX;
ea4e040a
YR		 643
644 if (vars->phy_flags & PHY_XGXS_FLAG) {
8c99e7b0
YR		 645 if (vars->line_speed &&
646 ((vars->line_speed == SPEED_10) ||
647 (vars->line_speed == SPEED_100))) {
ea4e040a
YR		 648 vars->phy_flags |= PHY_SGMII_FLAG;
649 } else {
650 vars->phy_flags &= ~PHY_SGMII_FLAG;
651 }
652 }
653
654 /* anything 10 and over uses the bmac */
655 link_10g = ((vars->line_speed == SPEED_10000) ||
656 (vars->line_speed == SPEED_12000) ||
657 (vars->line_speed == SPEED_12500) ||
658 (vars->line_speed == SPEED_13000) ||
659 (vars->line_speed == SPEED_15000) ||
660 (vars->line_speed == SPEED_16000));
661 if (link_10g)
662 vars->mac_type = MAC_TYPE_BMAC;
663 else
664 vars->mac_type = MAC_TYPE_EMAC;
665
666 } else { /* link down */
667 DP(NETIF_MSG_LINK, "phy link down\n");
668
669 vars->phy_link_up = 0;
670
671 vars->line_speed = 0;
672 vars->duplex = DUPLEX_FULL;
c0700f90 673 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
ea4e040a
YR		 674
675 /* indicate no mac active */
676 vars->mac_type = MAC_TYPE_NONE;
677 }
678
679 DP(NETIF_MSG_LINK, "link_status 0x%x phy_link_up %x\n",
680 vars->link_status, vars->phy_link_up);
681 DP(NETIF_MSG_LINK, "line_speed %x duplex %x flow_ctrl 0x%x\n",
682 vars->line_speed, vars->duplex, vars->flow_ctrl);
683}
684
685static void bnx2x_update_mng(struct link_params *params, u32 link_status)
686{
687 struct bnx2x *bp = params->bp;
ab6ad5a4 688
ea4e040a
YR		 689 REG_WR(bp, params->shmem_base +
690 offsetof(struct shmem_region,
691 port_mb[params->port].link_status),
692 link_status);
693}
694
695static void bnx2x_bmac_rx_disable(struct bnx2x *bp, u8 port)
696{
697 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
698 NIG_REG_INGRESS_BMAC0_MEM;
699 u32 wb_data[2];
3196a88a 700 u32 nig_bmac_enable = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4);
ea4e040a
YR		 701
702 /* Only if the bmac is out of reset */
703 if (REG_RD(bp, MISC_REG_RESET_REG_2) &
704 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port) &&
705 nig_bmac_enable) {
706
707 /* Clear Rx Enable bit in BMAC_CONTROL register */
708 REG_RD_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL,
709 wb_data, 2);
710 wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
711 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL,
712 wb_data, 2);
713
714 msleep(1);
715 }
716}
717
718static u8 bnx2x_pbf_update(struct link_params *params, u32 flow_ctrl,
719 u32 line_speed)
720{
721 struct bnx2x *bp = params->bp;
722 u8 port = params->port;
723 u32 init_crd, crd;
724 u32 count = 1000;
ea4e040a
YR		 725
726 /* disable port */
727 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1);
728
729 /* wait for init credit */
730 init_crd = REG_RD(bp, PBF_REG_P0_INIT_CRD + port*4);
731 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
732 DP(NETIF_MSG_LINK, "init_crd 0x%x crd 0x%x\n", init_crd, crd);
733
734 while ((init_crd != crd) && count) {
735 msleep(5);
736
737 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
738 count--;
739 }
740 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
741 if (init_crd != crd) {
742 DP(NETIF_MSG_LINK, "BUG! init_crd 0x%x != crd 0x%x\n",
743 init_crd, crd);
744 return -EINVAL;
745 }
746
c0700f90 747 if (flow_ctrl & BNX2X_FLOW_CTRL_RX ||
8c99e7b0
YR		 748 line_speed == SPEED_10 ||
749 line_speed == SPEED_100 ||
750 line_speed == SPEED_1000 ||
751 line_speed == SPEED_2500) {
752 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 1);
ea4e040a
YR		 753 /* update threshold */
754 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, 0);
755 /* update init credit */
8c99e7b0 756 init_crd = 778; /* (800-18-4) */
ea4e040a
YR		 757
758 } else {
759 u32 thresh = (ETH_MAX_JUMBO_PACKET_SIZE +
760 ETH_OVREHEAD)/16;
8c99e7b0 761 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
ea4e040a
YR		 762 /* update threshold */
763 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, thresh);
764 /* update init credit */
765 switch (line_speed) {
ea4e040a
YR		 766 case SPEED_10000:
767 init_crd = thresh + 553 - 22;
768 break;
769
770 case SPEED_12000:
771 init_crd = thresh + 664 - 22;
772 break;
773
774 case SPEED_13000:
775 init_crd = thresh + 742 - 22;
776 break;
777
778 case SPEED_16000:
779 init_crd = thresh + 778 - 22;
780 break;
781 default:
782 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
783 line_speed);
784 return -EINVAL;
ea4e040a
YR		 785 }
786 }
787 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, init_crd);
788 DP(NETIF_MSG_LINK, "PBF updated to speed %d credit %d\n",
789 line_speed, init_crd);
790
791 /* probe the credit changes */
792 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x1);
793 msleep(5);
794 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x0);
795
796 /* enable port */
797 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x0);
798 return 0;
799}
800
589abe3a 801static u32 bnx2x_get_emac_base(struct bnx2x *bp, u32 ext_phy_type, u8 port)
ea4e040a
YR		 802{
803 u32 emac_base;
ab6ad5a4 804
ea4e040a
YR		 805 switch (ext_phy_type) {
806 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
589abe3a 807 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
4d295db0 808 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
589abe3a
EG		 809 /* All MDC/MDIO is directed through single EMAC */
810 if (REG_RD(bp, NIG_REG_PORT_SWAP))
811 emac_base = GRCBASE_EMAC0;
812 else
813 emac_base = GRCBASE_EMAC1;
ea4e040a
YR		 814 break;
815 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
6378c025 816 emac_base = (port) ? GRCBASE_EMAC0 : GRCBASE_EMAC1;
ea4e040a
YR		 817 break;
818 default:
6378c025 819 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
ea4e040a
YR		 820 break;
821 }
822 return emac_base;
823
824}
825
826u8 bnx2x_cl45_write(struct bnx2x *bp, u8 port, u32 ext_phy_type,
827 u8 phy_addr, u8 devad, u16 reg, u16 val)
828{
829 u32 tmp, saved_mode;
830 u8 i, rc = 0;
589abe3a 831 u32 mdio_ctrl = bnx2x_get_emac_base(bp, ext_phy_type, port);
ea4e040a
YR		 832
833 /* set clause 45 mode, slow down the MDIO clock to 2.5MHz
834 * (a value of 49==0x31) and make sure that the AUTO poll is off
835 */
589abe3a 836
ea4e040a
YR		 837 saved_mode = REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
838 tmp = saved_mode & ~(EMAC_MDIO_MODE_AUTO_POLL |
839 EMAC_MDIO_MODE_CLOCK_CNT);
840 tmp |= (EMAC_MDIO_MODE_CLAUSE_45 |
841 (49 << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT));
842 REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, tmp);
843 REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
844 udelay(40);
845
846 /* address */
847
848 tmp = ((phy_addr << 21) | (devad << 16) | reg |
849 EMAC_MDIO_COMM_COMMAND_ADDRESS |
850 EMAC_MDIO_COMM_START_BUSY);
851 REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
852
853 for (i = 0; i < 50; i++) {
854 udelay(10);
855
856 tmp = REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
857 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
858 udelay(5);
859 break;
860 }
861 }
862 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
863 DP(NETIF_MSG_LINK, "write phy register failed\n");
864 rc = -EFAULT;
865 } else {
866 /* data */
867 tmp = ((phy_addr << 21) | (devad << 16) | val |
868 EMAC_MDIO_COMM_COMMAND_WRITE_45 |
869 EMAC_MDIO_COMM_START_BUSY);
870 REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
871
872 for (i = 0; i < 50; i++) {
873 udelay(10);
874
875 tmp = REG_RD(bp, mdio_ctrl +
876 EMAC_REG_EMAC_MDIO_COMM);
877 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
878 udelay(5);
879 break;
880 }
881 }
882 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
883 DP(NETIF_MSG_LINK, "write phy register failed\n");
884 rc = -EFAULT;
885 }
886 }
887
888 /* Restore the saved mode */
889 REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, saved_mode);
890
891 return rc;
892}
893
894u8 bnx2x_cl45_read(struct bnx2x *bp, u8 port, u32 ext_phy_type,
895 u8 phy_addr, u8 devad, u16 reg, u16 *ret_val)
896{
897 u32 val, saved_mode;
898 u16 i;
899 u8 rc = 0;
900
589abe3a 901 u32 mdio_ctrl = bnx2x_get_emac_base(bp, ext_phy_type, port);
ea4e040a
YR		 902 /* set clause 45 mode, slow down the MDIO clock to 2.5MHz
903 * (a value of 49==0x31) and make sure that the AUTO poll is off
904 */
589abe3a 905
ea4e040a
YR		 906 saved_mode = REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
907 val = saved_mode & ((EMAC_MDIO_MODE_AUTO_POLL |
908 EMAC_MDIO_MODE_CLOCK_CNT));
909 val |= (EMAC_MDIO_MODE_CLAUSE_45 |
ab6ad5a4 910 (49L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT));
ea4e040a
YR		 911 REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, val);
912 REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
913 udelay(40);
914
915 /* address */
916 val = ((phy_addr << 21) | (devad << 16) | reg |
917 EMAC_MDIO_COMM_COMMAND_ADDRESS |
918 EMAC_MDIO_COMM_START_BUSY);
919 REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
920
921 for (i = 0; i < 50; i++) {
922 udelay(10);
923
924 val = REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
925 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
926 udelay(5);
927 break;
928 }
929 }
930 if (val & EMAC_MDIO_COMM_START_BUSY) {
931 DP(NETIF_MSG_LINK, "read phy register failed\n");
932
933 *ret_val = 0;
934 rc = -EFAULT;
935
936 } else {
937 /* data */
938 val = ((phy_addr << 21) | (devad << 16) |
939 EMAC_MDIO_COMM_COMMAND_READ_45 |
940 EMAC_MDIO_COMM_START_BUSY);
941 REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
942
943 for (i = 0; i < 50; i++) {
944 udelay(10);
945
946 val = REG_RD(bp, mdio_ctrl +
947 EMAC_REG_EMAC_MDIO_COMM);
948 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
949 *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA);
950 break;
951 }
952 }
953 if (val & EMAC_MDIO_COMM_START_BUSY) {
954 DP(NETIF_MSG_LINK, "read phy register failed\n");
955
956 *ret_val = 0;
957 rc = -EFAULT;
958 }
959 }
960
961 /* Restore the saved mode */
962 REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, saved_mode);
963
964 return rc;
965}
966
967static void bnx2x_set_aer_mmd(struct link_params *params,
968 struct link_vars *vars)
969{
970 struct bnx2x *bp = params->bp;
971 u32 ser_lane;
972 u16 offset;
973
974 ser_lane = ((params->lane_config &
975 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
976 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
977
978 offset = (vars->phy_flags & PHY_XGXS_FLAG) ?
979 (params->phy_addr + ser_lane) : 0;
980
981 CL45_WR_OVER_CL22(bp, params->port,
982 params->phy_addr,
983 MDIO_REG_BANK_AER_BLOCK,
984 MDIO_AER_BLOCK_AER_REG, 0x3800 + offset);
985}
986
987static void bnx2x_set_master_ln(struct link_params *params)
988{
989 struct bnx2x *bp = params->bp;
990 u16 new_master_ln, ser_lane;
991 ser_lane = ((params->lane_config &
992 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
993 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
994
995 /* set the master_ln for AN */
996 CL45_RD_OVER_CL22(bp, params->port,
997 params->phy_addr,
998 MDIO_REG_BANK_XGXS_BLOCK2,
999 MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
1000 &new_master_ln);
1001
1002 CL45_WR_OVER_CL22(bp, params->port,
1003 params->phy_addr,
1004 MDIO_REG_BANK_XGXS_BLOCK2 ,
1005 MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
1006 (new_master_ln | ser_lane));
1007}
1008
1009static u8 bnx2x_reset_unicore(struct link_params *params)
1010{
1011 struct bnx2x *bp = params->bp;
1012 u16 mii_control;
1013 u16 i;
1014
1015 CL45_RD_OVER_CL22(bp, params->port,
1016 params->phy_addr,
1017 MDIO_REG_BANK_COMBO_IEEE0,
1018 MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control);
1019
1020 /* reset the unicore */
1021 CL45_WR_OVER_CL22(bp, params->port,
1022 params->phy_addr,
1023 MDIO_REG_BANK_COMBO_IEEE0,
1024 MDIO_COMBO_IEEE0_MII_CONTROL,
1025 (mii_control |
1026 MDIO_COMBO_IEEO_MII_CONTROL_RESET));
6f65497b
EG		 1027 if (params->switch_cfg == SWITCH_CFG_1G)
1028 bnx2x_set_serdes_access(params);
c1b73990 1029
ea4e040a
YR		 1030 /* wait for the reset to self clear */
1031 for (i = 0; i < MDIO_ACCESS_TIMEOUT; i++) {
1032 udelay(5);
1033
1034 /* the reset erased the previous bank value */
1035 CL45_RD_OVER_CL22(bp, params->port,
1036 params->phy_addr,
1037 MDIO_REG_BANK_COMBO_IEEE0,
1038 MDIO_COMBO_IEEE0_MII_CONTROL,
1039 &mii_control);
1040
1041 if (!(mii_control & MDIO_COMBO_IEEO_MII_CONTROL_RESET)) {
1042 udelay(5);
1043 return 0;
1044 }
1045 }
1046
1047 DP(NETIF_MSG_LINK, "BUG! XGXS is still in reset!\n");
1048 return -EINVAL;
1049
1050}
1051
1052static void bnx2x_set_swap_lanes(struct link_params *params)
1053{
1054 struct bnx2x *bp = params->bp;
1055 /* Each two bits represents a lane number:
1056 No swap is 0123 => 0x1b no need to enable the swap */
1057 u16 ser_lane, rx_lane_swap, tx_lane_swap;
1058
1059 ser_lane = ((params->lane_config &
1060 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
1061 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
1062 rx_lane_swap = ((params->lane_config &
1063 PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK) >>
1064 PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT);
1065 tx_lane_swap = ((params->lane_config &
1066 PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK) >>
1067 PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT);
1068
1069 if (rx_lane_swap != 0x1b) {
1070 CL45_WR_OVER_CL22(bp, params->port,
1071 params->phy_addr,
1072 MDIO_REG_BANK_XGXS_BLOCK2,
1073 MDIO_XGXS_BLOCK2_RX_LN_SWAP,
1074 (rx_lane_swap |
1075 MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE |
1076 MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE));
1077 } else {
1078 CL45_WR_OVER_CL22(bp, params->port,
1079 params->phy_addr,
1080 MDIO_REG_BANK_XGXS_BLOCK2,
1081 MDIO_XGXS_BLOCK2_RX_LN_SWAP, 0);
1082 }
1083
1084 if (tx_lane_swap != 0x1b) {
1085 CL45_WR_OVER_CL22(bp, params->port,
1086 params->phy_addr,
1087 MDIO_REG_BANK_XGXS_BLOCK2,
1088 MDIO_XGXS_BLOCK2_TX_LN_SWAP,
1089 (tx_lane_swap |
1090 MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE));
1091 } else {
1092 CL45_WR_OVER_CL22(bp, params->port,
1093 params->phy_addr,
1094 MDIO_REG_BANK_XGXS_BLOCK2,
1095 MDIO_XGXS_BLOCK2_TX_LN_SWAP, 0);
1096 }
1097}
1098
1099static void bnx2x_set_parallel_detection(struct link_params *params,
3196a88a 1100 u8 phy_flags)
ea4e040a
YR		 1101{
1102 struct bnx2x *bp = params->bp;
1103 u16 control2;
1104
1105 CL45_RD_OVER_CL22(bp, params->port,
1106 params->phy_addr,
1107 MDIO_REG_BANK_SERDES_DIGITAL,
1108 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
1109 &control2);
18afb0a6
YR		 1110 if (params->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
1111 control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
1112 else
1113 control2 &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
1114 DP(NETIF_MSG_LINK, "params->speed_cap_mask = 0x%x, control2 = 0x%x\n",
1115 params->speed_cap_mask, control2);
ea4e040a
YR		 1116 CL45_WR_OVER_CL22(bp, params->port,
1117 params->phy_addr,
1118 MDIO_REG_BANK_SERDES_DIGITAL,
1119 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
1120 control2);
1121
18afb0a6
YR		 1122 if ((phy_flags & PHY_XGXS_FLAG) &&
1123 (params->speed_cap_mask &
1124 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
ea4e040a
YR		 1125 DP(NETIF_MSG_LINK, "XGXS\n");
1126
1127 CL45_WR_OVER_CL22(bp, params->port,
1128 params->phy_addr,
1129 MDIO_REG_BANK_10G_PARALLEL_DETECT,
1130 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK,
1131 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT);
1132
1133 CL45_RD_OVER_CL22(bp, params->port,
1134 params->phy_addr,
1135 MDIO_REG_BANK_10G_PARALLEL_DETECT,
1136 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
1137 &control2);
1138
1139
1140 control2 |=
1141 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN;
1142
1143 CL45_WR_OVER_CL22(bp, params->port,
1144 params->phy_addr,
1145 MDIO_REG_BANK_10G_PARALLEL_DETECT,
1146 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
1147 control2);
1148
1149 /* Disable parallel detection of HiG */
1150 CL45_WR_OVER_CL22(bp, params->port,
1151 params->phy_addr,
1152 MDIO_REG_BANK_XGXS_BLOCK2,
1153 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G,
1154 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS |
1155 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS);
1156 }
1157}
1158
1159static void bnx2x_set_autoneg(struct link_params *params,
239d686d
EG		 1160 struct link_vars *vars,
1161 u8 enable_cl73)
ea4e040a
YR		 1162{
1163 struct bnx2x *bp = params->bp;
1164 u16 reg_val;
1165
1166 /* CL37 Autoneg */
1167
1168 CL45_RD_OVER_CL22(bp, params->port,
1169 params->phy_addr,
1170 MDIO_REG_BANK_COMBO_IEEE0,
1171 MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
1172
1173 /* CL37 Autoneg Enabled */
8c99e7b0 1174 if (vars->line_speed == SPEED_AUTO_NEG)
ea4e040a
YR		 1175 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN;
1176 else /* CL37 Autoneg Disabled */
1177 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
1178 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN);
1179
1180 CL45_WR_OVER_CL22(bp, params->port,
1181 params->phy_addr,
1182 MDIO_REG_BANK_COMBO_IEEE0,
1183 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
1184
1185 /* Enable/Disable Autodetection */
1186
1187 CL45_RD_OVER_CL22(bp, params->port,
1188 params->phy_addr,
1189 MDIO_REG_BANK_SERDES_DIGITAL,
1190 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, &reg_val);
239d686d
EG		 1191 reg_val &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN |
1192 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT);
1193 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE;
8c99e7b0 1194 if (vars->line_speed == SPEED_AUTO_NEG)
ea4e040a
YR		 1195 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
1196 else
1197 reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
1198
1199 CL45_WR_OVER_CL22(bp, params->port,
1200 params->phy_addr,
1201 MDIO_REG_BANK_SERDES_DIGITAL,
1202 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, reg_val);
1203
1204 /* Enable TetonII and BAM autoneg */
1205 CL45_RD_OVER_CL22(bp, params->port,
1206 params->phy_addr,
1207 MDIO_REG_BANK_BAM_NEXT_PAGE,
1208 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
1209 &reg_val);
8c99e7b0 1210 if (vars->line_speed == SPEED_AUTO_NEG) {
ea4e040a
YR		 1211 /* Enable BAM aneg Mode and TetonII aneg Mode */
1212 reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
1213 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
1214 } else {
1215 /* TetonII and BAM Autoneg Disabled */
1216 reg_val &= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
1217 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
1218 }
1219 CL45_WR_OVER_CL22(bp, params->port,
1220 params->phy_addr,
1221 MDIO_REG_BANK_BAM_NEXT_PAGE,
1222 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
1223 reg_val);
1224
239d686d
EG		 1225 if (enable_cl73) {
1226 /* Enable Cl73 FSM status bits */
1227 CL45_WR_OVER_CL22(bp, params->port,
1228 params->phy_addr,
1229 MDIO_REG_BANK_CL73_USERB0,
1230 MDIO_CL73_USERB0_CL73_UCTRL,
7846e471 1231 0xe);
239d686d
EG		 1232
1233 /* Enable BAM Station Manager*/
1234 CL45_WR_OVER_CL22(bp, params->port,
1235 params->phy_addr,
1236 MDIO_REG_BANK_CL73_USERB0,
1237 MDIO_CL73_USERB0_CL73_BAM_CTRL1,
1238 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN |
1239 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN |
1240 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN);
1241
7846e471 1242 /* Advertise CL73 link speeds */
239d686d
EG		 1243 CL45_RD_OVER_CL22(bp, params->port,
1244 params->phy_addr,
1245 MDIO_REG_BANK_CL73_IEEEB1,
1246 MDIO_CL73_IEEEB1_AN_ADV2,
1247 &reg_val);
7846e471
YR		 1248 if (params->speed_cap_mask &
1249 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
1250 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4;
1251 if (params->speed_cap_mask &
1252 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
1253 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX;
239d686d
EG		 1254
1255 CL45_WR_OVER_CL22(bp, params->port,
1256 params->phy_addr,
1257 MDIO_REG_BANK_CL73_IEEEB1,
1258 MDIO_CL73_IEEEB1_AN_ADV2,
7846e471 1259 reg_val);
239d686d 1260
239d686d
EG		 1261 /* CL73 Autoneg Enabled */
1262 reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN;
1263
1264 } else /* CL73 Autoneg Disabled */
1265 reg_val = 0;
ea4e040a 1266
ea4e040a
YR		 1267 CL45_WR_OVER_CL22(bp, params->port,
1268 params->phy_addr,
1269 MDIO_REG_BANK_CL73_IEEEB0,
1270 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, reg_val);
1271}
1272
1273/* program SerDes, forced speed */
8c99e7b0
YR		 1274static void bnx2x_program_serdes(struct link_params *params,
1275 struct link_vars *vars)
ea4e040a
YR		 1276{
1277 struct bnx2x *bp = params->bp;
1278 u16 reg_val;
1279
57937203 1280 /* program duplex, disable autoneg and sgmii*/
ea4e040a
YR		 1281 CL45_RD_OVER_CL22(bp, params->port,
1282 params->phy_addr,
1283 MDIO_REG_BANK_COMBO_IEEE0,
1284 MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
1285 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX |
57937203
EG		 1286 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
1287 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK);
ea4e040a
YR		 1288 if (params->req_duplex == DUPLEX_FULL)
1289 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
1290 CL45_WR_OVER_CL22(bp, params->port,
1291 params->phy_addr,
1292 MDIO_REG_BANK_COMBO_IEEE0,
1293 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
1294
1295 /* program speed
1296 - needed only if the speed is greater than 1G (2.5G or 10G) */
8c99e7b0 1297 CL45_RD_OVER_CL22(bp, params->port,
ea4e040a
YR		 1298 params->phy_addr,
1299 MDIO_REG_BANK_SERDES_DIGITAL,
1300 MDIO_SERDES_DIGITAL_MISC1, &reg_val);
8c99e7b0
YR		 1301 /* clearing the speed value before setting the right speed */
1302 DP(NETIF_MSG_LINK, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x\n", reg_val);
1303
1304 reg_val &= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK |
1305 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
1306
1307 if (!((vars->line_speed == SPEED_1000) ||
1308 (vars->line_speed == SPEED_100) ||
1309 (vars->line_speed == SPEED_10))) {
1310
ea4e040a
YR		 1311 reg_val |= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M |
1312 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
8c99e7b0 1313 if (vars->line_speed == SPEED_10000)
ea4e040a
YR		 1314 reg_val |=
1315 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4;
8c99e7b0 1316 if (vars->line_speed == SPEED_13000)
ea4e040a
YR		 1317 reg_val |=
1318 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_13G;
8c99e7b0
YR		 1319 }
1320
1321 CL45_WR_OVER_CL22(bp, params->port,
ea4e040a
YR		 1322 params->phy_addr,
1323 MDIO_REG_BANK_SERDES_DIGITAL,
1324 MDIO_SERDES_DIGITAL_MISC1, reg_val);
8c99e7b0 1325
ea4e040a
YR		 1326}
1327
1328static void bnx2x_set_brcm_cl37_advertisment(struct link_params *params)
1329{
1330 struct bnx2x *bp = params->bp;
1331 u16 val = 0;
1332
1333 /* configure the 48 bits for BAM AN */
1334
1335 /* set extended capabilities */
1336 if (params->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)
1337 val |= MDIO_OVER_1G_UP1_2_5G;
1338 if (params->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
1339 val |= MDIO_OVER_1G_UP1_10G;
1340 CL45_WR_OVER_CL22(bp, params->port,
1341 params->phy_addr,
1342 MDIO_REG_BANK_OVER_1G,
1343 MDIO_OVER_1G_UP1, val);
1344
1345 CL45_WR_OVER_CL22(bp, params->port,
1346 params->phy_addr,
1347 MDIO_REG_BANK_OVER_1G,
239d686d 1348 MDIO_OVER_1G_UP3, 0x400);
ea4e040a
YR		 1349}
1350
1ef70b9c 1351static void bnx2x_calc_ieee_aneg_adv(struct link_params *params, u16 *ieee_fc)
ea4e040a 1352{
d5cb9e99 1353 struct bnx2x *bp = params->bp;
8c99e7b0 1354 *ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX;
ea4e040a
YR		 1355 /* resolve pause mode and advertisement
1356 * Please refer to Table 28B-3 of the 802.3ab-1999 spec */
1357
1358 switch (params->req_flow_ctrl) {
c0700f90
DM		 1359 case BNX2X_FLOW_CTRL_AUTO:
1360 if (params->req_fc_auto_adv == BNX2X_FLOW_CTRL_BOTH) {
8c99e7b0 1361 *ieee_fc |=
ea4e040a
YR		 1362 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
1363 } else {
8c99e7b0 1364 *ieee_fc |=
ea4e040a
YR		 1365 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
1366 }
1367 break;
c0700f90 1368 case BNX2X_FLOW_CTRL_TX:
8c99e7b0 1369 *ieee_fc |=
ea4e040a
YR		 1370 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
1371 break;
1372
c0700f90
DM		 1373 case BNX2X_FLOW_CTRL_RX:
1374 case BNX2X_FLOW_CTRL_BOTH:
8c99e7b0 1375 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
ea4e040a
YR		 1376 break;
1377
c0700f90 1378 case BNX2X_FLOW_CTRL_NONE:
ea4e040a 1379 default:
8c99e7b0 1380 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE;
ea4e040a
YR		 1381 break;
1382 }
d5cb9e99 1383 DP(NETIF_MSG_LINK, "ieee_fc = 0x%x\n", *ieee_fc);
8c99e7b0 1384}
ea4e040a 1385
8c99e7b0 1386static void bnx2x_set_ieee_aneg_advertisment(struct link_params *params,
1ef70b9c 1387 u16 ieee_fc)
8c99e7b0
YR		 1388{
1389 struct bnx2x *bp = params->bp;
7846e471 1390 u16 val;
8c99e7b0 1391 /* for AN, we are always publishing full duplex */
ea4e040a
YR		 1392
1393 CL45_WR_OVER_CL22(bp, params->port,
1394 params->phy_addr,
1395 MDIO_REG_BANK_COMBO_IEEE0,
1ef70b9c 1396 MDIO_COMBO_IEEE0_AUTO_NEG_ADV, ieee_fc);
7846e471
YR		 1397 CL45_RD_OVER_CL22(bp, params->port,
1398 params->phy_addr,
1399 MDIO_REG_BANK_CL73_IEEEB1,
1400 MDIO_CL73_IEEEB1_AN_ADV1, &val);
1401 val &= ~MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH;
1402 val |= ((ieee_fc<<3) & MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK);
1403 CL45_WR_OVER_CL22(bp, params->port,
1404 params->phy_addr,
1405 MDIO_REG_BANK_CL73_IEEEB1,
1406 MDIO_CL73_IEEEB1_AN_ADV1, val);
ea4e040a
YR		 1407}
1408
239d686d 1409static void bnx2x_restart_autoneg(struct link_params *params, u8 enable_cl73)
ea4e040a
YR		 1410{
1411 struct bnx2x *bp = params->bp;
3a36f2ef 1412 u16 mii_control;
239d686d 1413
ea4e040a 1414 DP(NETIF_MSG_LINK, "bnx2x_restart_autoneg\n");
3a36f2ef 1415 /* Enable and restart BAM/CL37 aneg */
ea4e040a 1416
239d686d
EG		 1417 if (enable_cl73) {
1418 CL45_RD_OVER_CL22(bp, params->port,
1419 params->phy_addr,
1420 MDIO_REG_BANK_CL73_IEEEB0,
1421 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
1422 &mii_control);
1423
1424 CL45_WR_OVER_CL22(bp, params->port,
1425 params->phy_addr,
1426 MDIO_REG_BANK_CL73_IEEEB0,
1427 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
1428 (mii_control |
1429 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN |
1430 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN));
1431 } else {
1432
1433 CL45_RD_OVER_CL22(bp, params->port,
1434 params->phy_addr,
1435 MDIO_REG_BANK_COMBO_IEEE0,
1436 MDIO_COMBO_IEEE0_MII_CONTROL,
1437 &mii_control);
1438 DP(NETIF_MSG_LINK,
1439 "bnx2x_restart_autoneg mii_control before = 0x%x\n",
1440 mii_control);
1441 CL45_WR_OVER_CL22(bp, params->port,
1442 params->phy_addr,
1443 MDIO_REG_BANK_COMBO_IEEE0,
1444 MDIO_COMBO_IEEE0_MII_CONTROL,
1445 (mii_control |
1446 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
1447 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN));
1448 }
ea4e040a
YR		 1449}
1450
8c99e7b0
YR		 1451static void bnx2x_initialize_sgmii_process(struct link_params *params,
1452 struct link_vars *vars)
ea4e040a
YR		 1453{
1454 struct bnx2x *bp = params->bp;
1455 u16 control1;
1456
1457 /* in SGMII mode, the unicore is always slave */
1458
1459 CL45_RD_OVER_CL22(bp, params->port,
1460 params->phy_addr,
1461 MDIO_REG_BANK_SERDES_DIGITAL,
1462 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
1463 &control1);
1464 control1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT;
1465 /* set sgmii mode (and not fiber) */
1466 control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE |
1467 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET |
1468 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE);
1469 CL45_WR_OVER_CL22(bp, params->port,
1470 params->phy_addr,
1471 MDIO_REG_BANK_SERDES_DIGITAL,
1472 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
1473 control1);
1474
1475 /* if forced speed */
8c99e7b0 1476 if (!(vars->line_speed == SPEED_AUTO_NEG)) {
ea4e040a
YR		 1477 /* set speed, disable autoneg */
1478 u16 mii_control;
1479
1480 CL45_RD_OVER_CL22(bp, params->port,
1481 params->phy_addr,
1482 MDIO_REG_BANK_COMBO_IEEE0,
1483 MDIO_COMBO_IEEE0_MII_CONTROL,
1484 &mii_control);
1485 mii_control &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
1486 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK|
1487 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX);
1488
8c99e7b0 1489 switch (vars->line_speed) {
ea4e040a
YR		 1490 case SPEED_100:
1491 mii_control |=
1492 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100;
1493 break;
1494 case SPEED_1000:
1495 mii_control |=
1496 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000;
1497 break;
1498 case SPEED_10:
1499 /* there is nothing to set for 10M */
1500 break;
1501 default:
1502 /* invalid speed for SGMII */
8c99e7b0
YR		 1503 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
1504 vars->line_speed);
ea4e040a
YR		 1505 break;
1506 }
1507
1508 /* setting the full duplex */
1509 if (params->req_duplex == DUPLEX_FULL)
1510 mii_control |=
1511 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
1512 CL45_WR_OVER_CL22(bp, params->port,
1513 params->phy_addr,
1514 MDIO_REG_BANK_COMBO_IEEE0,
1515 MDIO_COMBO_IEEE0_MII_CONTROL,
1516 mii_control);
1517
1518 } else { /* AN mode */
1519 /* enable and restart AN */
239d686d 1520 bnx2x_restart_autoneg(params, 0);
ea4e040a
YR		 1521 }
1522}
1523
1524
1525/*
1526 * link management
1527 */
1528
1529static void bnx2x_pause_resolve(struct link_vars *vars, u32 pause_result)
8c99e7b0
YR		 1530{ /* LD LP */
1531 switch (pause_result) { /* ASYM P ASYM P */
1532 case 0xb: /* 1 0 1 1 */
c0700f90 1533 vars->flow_ctrl = BNX2X_FLOW_CTRL_TX;
ea4e040a
YR		 1534 break;
1535
8c99e7b0 1536 case 0xe: /* 1 1 1 0 */
c0700f90 1537 vars->flow_ctrl = BNX2X_FLOW_CTRL_RX;
ea4e040a
YR		 1538 break;
1539
8c99e7b0
YR		 1540 case 0x5: /* 0 1 0 1 */
1541 case 0x7: /* 0 1 1 1 */
1542 case 0xd: /* 1 1 0 1 */
1543 case 0xf: /* 1 1 1 1 */
c0700f90 1544 vars->flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
ea4e040a
YR		 1545 break;
1546
1547 default:
1548 break;
1549 }
1550}
1551
ab6ad5a4 1552static u8 bnx2x_ext_phy_resolve_fc(struct link_params *params,
ea4e040a
YR		 1553 struct link_vars *vars)
1554{
1555 struct bnx2x *bp = params->bp;
1556 u8 ext_phy_addr;
ab6ad5a4
EG		 1557 u16 ld_pause; /* local */
1558 u16 lp_pause; /* link partner */
1559 u16 an_complete; /* AN complete */
ea4e040a
YR		 1560 u16 pause_result;
1561 u8 ret = 0;
1562 u32 ext_phy_type;
1563 u8 port = params->port;
659bc5c4 1564 ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
ea4e040a
YR		 1565 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
1566 /* read twice */
1567
1568 bnx2x_cl45_read(bp, port,
1569 ext_phy_type,
1570 ext_phy_addr,
1571 MDIO_AN_DEVAD,
1572 MDIO_AN_REG_STATUS, &an_complete);
1573 bnx2x_cl45_read(bp, port,
1574 ext_phy_type,
1575 ext_phy_addr,
1576 MDIO_AN_DEVAD,
1577 MDIO_AN_REG_STATUS, &an_complete);
1578
1579 if (an_complete & MDIO_AN_REG_STATUS_AN_COMPLETE) {
1580 ret = 1;
1581 bnx2x_cl45_read(bp, port,
1582 ext_phy_type,
1583 ext_phy_addr,
1584 MDIO_AN_DEVAD,
1585 MDIO_AN_REG_ADV_PAUSE, &ld_pause);
1586 bnx2x_cl45_read(bp, port,
1587 ext_phy_type,
1588 ext_phy_addr,
1589 MDIO_AN_DEVAD,
1590 MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
1591 pause_result = (ld_pause &
1592 MDIO_AN_REG_ADV_PAUSE_MASK) >> 8;
1593 pause_result |= (lp_pause &
1594 MDIO_AN_REG_ADV_PAUSE_MASK) >> 10;
1595 DP(NETIF_MSG_LINK, "Ext PHY pause result 0x%x \n",
1596 pause_result);
1597 bnx2x_pause_resolve(vars, pause_result);
c0700f90 1598 if (vars->flow_ctrl == BNX2X_FLOW_CTRL_NONE &&
8c99e7b0
YR		 1599 ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073) {
1600 bnx2x_cl45_read(bp, port,
1601 ext_phy_type,
1602 ext_phy_addr,
1603 MDIO_AN_DEVAD,
1604 MDIO_AN_REG_CL37_FC_LD, &ld_pause);
1605
1606 bnx2x_cl45_read(bp, port,
1607 ext_phy_type,
1608 ext_phy_addr,
1609 MDIO_AN_DEVAD,
1610 MDIO_AN_REG_CL37_FC_LP, &lp_pause);
1611 pause_result = (ld_pause &
1612 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 5;
1613 pause_result |= (lp_pause &
1614 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 7;
1615
1616 bnx2x_pause_resolve(vars, pause_result);
1617 DP(NETIF_MSG_LINK, "Ext PHY CL37 pause result 0x%x \n",
1618 pause_result);
1619 }
ea4e040a
YR		 1620 }
1621 return ret;
1622}
1623
15ddd2d0
YR		 1624static u8 bnx2x_direct_parallel_detect_used(struct link_params *params)
1625{
1626 struct bnx2x *bp = params->bp;
1627 u16 pd_10g, status2_1000x;
1628 CL45_RD_OVER_CL22(bp, params->port,
1629 params->phy_addr,
1630 MDIO_REG_BANK_SERDES_DIGITAL,
1631 MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
1632 &status2_1000x);
1633 CL45_RD_OVER_CL22(bp, params->port,
1634 params->phy_addr,
1635 MDIO_REG_BANK_SERDES_DIGITAL,
1636 MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
1637 &status2_1000x);
1638 if (status2_1000x & MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED) {
1639 DP(NETIF_MSG_LINK, "1G parallel detect link on port %d\n",
1640 params->port);
1641 return 1;
1642 }
1643
1644 CL45_RD_OVER_CL22(bp, params->port,
1645 params->phy_addr,
1646 MDIO_REG_BANK_10G_PARALLEL_DETECT,
1647 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS,
1648 &pd_10g);
1649
1650 if (pd_10g & MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK) {
1651 DP(NETIF_MSG_LINK, "10G parallel detect link on port %d\n",
1652 params->port);
1653 return 1;
1654 }
1655 return 0;
1656}
ea4e040a
YR		 1657
1658static void bnx2x_flow_ctrl_resolve(struct link_params *params,
1659 struct link_vars *vars,
1660 u32 gp_status)
1661{
1662 struct bnx2x *bp = params->bp;
3196a88a
EG		 1663 u16 ld_pause; /* local driver */
1664 u16 lp_pause; /* link partner */
ea4e040a
YR		 1665 u16 pause_result;
1666
c0700f90 1667 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
ea4e040a
YR		 1668
1669 /* resolve from gp_status in case of AN complete and not sgmii */
c0700f90 1670 if ((params->req_flow_ctrl == BNX2X_FLOW_CTRL_AUTO) &&
ea4e040a
YR		 1671 (gp_status & MDIO_AN_CL73_OR_37_COMPLETE) &&
1672 (!(vars->phy_flags & PHY_SGMII_FLAG)) &&
1673 (XGXS_EXT_PHY_TYPE(params->ext_phy_config) ==
1674 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)) {
15ddd2d0
YR		 1675 if (bnx2x_direct_parallel_detect_used(params)) {
1676 vars->flow_ctrl = params->req_fc_auto_adv;
1677 return;
1678 }
7846e471
YR		 1679 if ((gp_status &
1680 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
1681 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) ==
1682 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
1683 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) {
1684
1685 CL45_RD_OVER_CL22(bp, params->port,
1686 params->phy_addr,
1687 MDIO_REG_BANK_CL73_IEEEB1,
1688 MDIO_CL73_IEEEB1_AN_ADV1,
1689 &ld_pause);
1690 CL45_RD_OVER_CL22(bp, params->port,
1691 params->phy_addr,
1692 MDIO_REG_BANK_CL73_IEEEB1,
1693 MDIO_CL73_IEEEB1_AN_LP_ADV1,
1694 &lp_pause);
1695 pause_result = (ld_pause &
1696 MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK)
1697 >> 8;
1698 pause_result |= (lp_pause &
1699 MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK)
1700 >> 10;
1701 DP(NETIF_MSG_LINK, "pause_result CL73 0x%x\n",
1702 pause_result);
1703 } else {
1704
1705 CL45_RD_OVER_CL22(bp, params->port,
1706 params->phy_addr,
1707 MDIO_REG_BANK_COMBO_IEEE0,
1708 MDIO_COMBO_IEEE0_AUTO_NEG_ADV,
1709 &ld_pause);
1710 CL45_RD_OVER_CL22(bp, params->port,
1711 params->phy_addr,
1712 MDIO_REG_BANK_COMBO_IEEE0,
1713 MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1,
1714 &lp_pause);
1715 pause_result = (ld_pause &
ea4e040a 1716 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>5;
7846e471 1717 pause_result |= (lp_pause &
ea4e040a 1718 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>7;
7846e471
YR		 1719 DP(NETIF_MSG_LINK, "pause_result CL37 0x%x\n",
1720 pause_result);
1721 }
ea4e040a 1722 bnx2x_pause_resolve(vars, pause_result);
c0700f90 1723 } else if ((params->req_flow_ctrl == BNX2X_FLOW_CTRL_AUTO) &&
ab6ad5a4 1724 (bnx2x_ext_phy_resolve_fc(params, vars))) {
ea4e040a
YR		 1725 return;
1726 } else {
c0700f90 1727 if (params->req_flow_ctrl == BNX2X_FLOW_CTRL_AUTO)
8c99e7b0
YR		 1728 vars->flow_ctrl = params->req_fc_auto_adv;
1729 else
1730 vars->flow_ctrl = params->req_flow_ctrl;
ea4e040a
YR		 1731 }
1732 DP(NETIF_MSG_LINK, "flow_ctrl 0x%x\n", vars->flow_ctrl);
1733}
1734
239d686d
EG		 1735static void bnx2x_check_fallback_to_cl37(struct link_params *params)
1736{
1737 struct bnx2x *bp = params->bp;
1738 u16 rx_status, ustat_val, cl37_fsm_recieved;
1739 DP(NETIF_MSG_LINK, "bnx2x_check_fallback_to_cl37\n");
1740 /* Step 1: Make sure signal is detected */
1741 CL45_RD_OVER_CL22(bp, params->port,
1742 params->phy_addr,
1743 MDIO_REG_BANK_RX0,
1744 MDIO_RX0_RX_STATUS,
1745 &rx_status);
1746 if ((rx_status & MDIO_RX0_RX_STATUS_SIGDET) !=
1747 (MDIO_RX0_RX_STATUS_SIGDET)) {
1748 DP(NETIF_MSG_LINK, "Signal is not detected. Restoring CL73."
1749 "rx_status(0x80b0) = 0x%x\n", rx_status);
1750 CL45_WR_OVER_CL22(bp, params->port,
1751 params->phy_addr,
1752 MDIO_REG_BANK_CL73_IEEEB0,
1753 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
1754 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN);
1755 return;
1756 }
1757 /* Step 2: Check CL73 state machine */
1758 CL45_RD_OVER_CL22(bp, params->port,
1759 params->phy_addr,
1760 MDIO_REG_BANK_CL73_USERB0,
1761 MDIO_CL73_USERB0_CL73_USTAT1,
1762 &ustat_val);
1763 if ((ustat_val &
1764 (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
1765 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) !=
1766 (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
1767 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) {
1768 DP(NETIF_MSG_LINK, "CL73 state-machine is not stable. "
1769 "ustat_val(0x8371) = 0x%x\n", ustat_val);
1770 return;
1771 }
1772 /* Step 3: Check CL37 Message Pages received to indicate LP
1773 supports only CL37 */
1774 CL45_RD_OVER_CL22(bp, params->port,
1775 params->phy_addr,
1776 MDIO_REG_BANK_REMOTE_PHY,
1777 MDIO_REMOTE_PHY_MISC_RX_STATUS,
1778 &cl37_fsm_recieved);
1779 if ((cl37_fsm_recieved &
1780 (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
1781 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) !=
1782 (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
1783 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) {
1784 DP(NETIF_MSG_LINK, "No CL37 FSM were received. "
1785 "misc_rx_status(0x8330) = 0x%x\n",
1786 cl37_fsm_recieved);
1787 return;
1788 }
1789 /* The combined cl37/cl73 fsm state information indicating that we are
1790 connected to a device which does not support cl73, but does support
1791 cl37 BAM. In this case we disable cl73 and restart cl37 auto-neg */
1792 /* Disable CL73 */
1793 CL45_WR_OVER_CL22(bp, params->port,
1794 params->phy_addr,
1795 MDIO_REG_BANK_CL73_IEEEB0,
1796 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
1797 0);
1798 /* Restart CL37 autoneg */
1799 bnx2x_restart_autoneg(params, 0);
1800 DP(NETIF_MSG_LINK, "Disabling CL73, and restarting CL37 autoneg\n");
1801}
ea4e040a 1802static u8 bnx2x_link_settings_status(struct link_params *params,
2f904460
EG		 1803 struct link_vars *vars,
1804 u32 gp_status,
1805 u8 ext_phy_link_up)
ea4e040a
YR		 1806{
1807 struct bnx2x *bp = params->bp;
6c55c3cd 1808 u16 new_line_speed;
ea4e040a
YR		 1809 u8 rc = 0;
1810 vars->link_status = 0;
1811
1812 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) {
1813 DP(NETIF_MSG_LINK, "phy link up gp_status=0x%x\n",
1814 gp_status);
1815
1816 vars->phy_link_up = 1;
1817 vars->link_status |= LINK_STATUS_LINK_UP;
1818
1819 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS)
1820 vars->duplex = DUPLEX_FULL;
1821 else
1822 vars->duplex = DUPLEX_HALF;
1823
1824 bnx2x_flow_ctrl_resolve(params, vars, gp_status);
1825
1826 switch (gp_status & GP_STATUS_SPEED_MASK) {
1827 case GP_STATUS_10M:
6c55c3cd 1828 new_line_speed = SPEED_10;
ea4e040a
YR		 1829 if (vars->duplex == DUPLEX_FULL)
1830 vars->link_status |= LINK_10TFD;
1831 else
1832 vars->link_status |= LINK_10THD;
1833 break;
1834
1835 case GP_STATUS_100M:
6c55c3cd 1836 new_line_speed = SPEED_100;
ea4e040a
YR		 1837 if (vars->duplex == DUPLEX_FULL)
1838 vars->link_status |= LINK_100TXFD;
1839 else
1840 vars->link_status |= LINK_100TXHD;
1841 break;
1842
1843 case GP_STATUS_1G:
1844 case GP_STATUS_1G_KX:
6c55c3cd 1845 new_line_speed = SPEED_1000;
ea4e040a
YR		 1846 if (vars->duplex == DUPLEX_FULL)
1847 vars->link_status |= LINK_1000TFD;
1848 else
1849 vars->link_status |= LINK_1000THD;
1850 break;
1851
1852 case GP_STATUS_2_5G:
6c55c3cd 1853 new_line_speed = SPEED_2500;
ea4e040a
YR		 1854 if (vars->duplex == DUPLEX_FULL)
1855 vars->link_status |= LINK_2500TFD;
1856 else
1857 vars->link_status |= LINK_2500THD;
1858 break;
1859
1860 case GP_STATUS_5G:
1861 case GP_STATUS_6G:
1862 DP(NETIF_MSG_LINK,
1863 "link speed unsupported gp_status 0x%x\n",
1864 gp_status);
1865 return -EINVAL;
ab6ad5a4 1866
ea4e040a
YR		 1867 case GP_STATUS_10G_KX4:
1868 case GP_STATUS_10G_HIG:
1869 case GP_STATUS_10G_CX4:
6c55c3cd 1870 new_line_speed = SPEED_10000;
ea4e040a
YR		 1871 vars->link_status |= LINK_10GTFD;
1872 break;
1873
1874 case GP_STATUS_12G_HIG:
6c55c3cd 1875 new_line_speed = SPEED_12000;
ea4e040a
YR		 1876 vars->link_status |= LINK_12GTFD;
1877 break;
1878
1879 case GP_STATUS_12_5G:
6c55c3cd 1880 new_line_speed = SPEED_12500;
ea4e040a
YR		 1881 vars->link_status |= LINK_12_5GTFD;
1882 break;
1883
1884 case GP_STATUS_13G:
6c55c3cd 1885 new_line_speed = SPEED_13000;
ea4e040a
YR		 1886 vars->link_status |= LINK_13GTFD;
1887 break;
1888
1889 case GP_STATUS_15G:
6c55c3cd 1890 new_line_speed = SPEED_15000;
ea4e040a
YR		 1891 vars->link_status |= LINK_15GTFD;
1892 break;
1893
1894 case GP_STATUS_16G:
6c55c3cd 1895 new_line_speed = SPEED_16000;
ea4e040a
YR		 1896 vars->link_status |= LINK_16GTFD;
1897 break;
1898
1899 default:
1900 DP(NETIF_MSG_LINK,
1901 "link speed unsupported gp_status 0x%x\n",
1902 gp_status);
ab6ad5a4 1903 return -EINVAL;
ea4e040a
YR		 1904 }
1905
6c55c3cd
EG		 1906 /* Upon link speed change set the NIG into drain mode.
1907 Comes to deals with possible FIFO glitch due to clk change
1908 when speed is decreased without link down indicator */
1909 if (new_line_speed != vars->line_speed) {
2f904460
EG		 1910 if (XGXS_EXT_PHY_TYPE(params->ext_phy_config) !=
1911 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT &&
1912 ext_phy_link_up) {
1913 DP(NETIF_MSG_LINK, "Internal link speed %d is"
1914 " different than the external"
1915 " link speed %d\n", new_line_speed,
1916 vars->line_speed);
1917 vars->phy_link_up = 0;
1918 return 0;
1919 }
6c55c3cd
EG		 1920 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE
1921 + params->port*4, 0);
1922 msleep(1);
1923 }
1924 vars->line_speed = new_line_speed;
ea4e040a
YR		 1925 vars->link_status |= LINK_STATUS_SERDES_LINK;
1926
57963ed9
YR		 1927 if ((params->req_line_speed == SPEED_AUTO_NEG) &&
1928 ((XGXS_EXT_PHY_TYPE(params->ext_phy_config) ==
1929 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ||
1930 (XGXS_EXT_PHY_TYPE(params->ext_phy_config) ==
589abe3a
EG		 1931 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705) ||
1932 (XGXS_EXT_PHY_TYPE(params->ext_phy_config) ==
2f904460 1933 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726))) {
ea4e040a
YR		 1934 vars->autoneg = AUTO_NEG_ENABLED;
1935
1936 if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE) {
1937 vars->autoneg |= AUTO_NEG_COMPLETE;
1938 vars->link_status |=
1939 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
1940 }
1941
1942 vars->autoneg |= AUTO_NEG_PARALLEL_DETECTION_USED;
1943 vars->link_status |=
1944 LINK_STATUS_PARALLEL_DETECTION_USED;
1945
1946 }
c0700f90 1947 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
8c99e7b0
YR		 1948 vars->link_status |=
1949 LINK_STATUS_TX_FLOW_CONTROL_ENABLED;
ea4e040a 1950
c0700f90 1951 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
8c99e7b0
YR		 1952 vars->link_status |=
1953 LINK_STATUS_RX_FLOW_CONTROL_ENABLED;
ea4e040a
YR		 1954
1955 } else { /* link_down */
1956 DP(NETIF_MSG_LINK, "phy link down\n");
1957
1958 vars->phy_link_up = 0;
57963ed9 1959
ea4e040a 1960 vars->duplex = DUPLEX_FULL;
c0700f90 1961 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
ea4e040a
YR		 1962 vars->autoneg = AUTO_NEG_DISABLED;
1963 vars->mac_type = MAC_TYPE_NONE;
239d686d
EG		 1964
1965 if ((params->req_line_speed == SPEED_AUTO_NEG) &&
1966 ((XGXS_EXT_PHY_TYPE(params->ext_phy_config) ==
1967 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT))) {
1968 /* Check signal is detected */
1969 bnx2x_check_fallback_to_cl37(params);
1970 }
ea4e040a
YR		 1971 }
1972
1973 DP(NETIF_MSG_LINK, "gp_status 0x%x phy_link_up %x line_speed %x \n",
1974 gp_status, vars->phy_link_up, vars->line_speed);
1975 DP(NETIF_MSG_LINK, "duplex %x flow_ctrl 0x%x"
1976 " autoneg 0x%x\n",
1977 vars->duplex,
1978 vars->flow_ctrl, vars->autoneg);
1979 DP(NETIF_MSG_LINK, "link_status 0x%x\n", vars->link_status);
1980
1981 return rc;
1982}
1983
ed8680a7 1984static void bnx2x_set_gmii_tx_driver(struct link_params *params)
ea4e040a
YR		 1985{
1986 struct bnx2x *bp = params->bp;
1987 u16 lp_up2;
1988 u16 tx_driver;
c2c8b03e 1989 u16 bank;
ea4e040a
YR		 1990
1991 /* read precomp */
ea4e040a
YR		 1992 CL45_RD_OVER_CL22(bp, params->port,
1993 params->phy_addr,
1994 MDIO_REG_BANK_OVER_1G,
1995 MDIO_OVER_1G_LP_UP2, &lp_up2);
1996
ea4e040a
YR		 1997 /* bits [10:7] at lp_up2, positioned at [15:12] */
1998 lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >>
1999 MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) <<
2000 MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT);
2001
c2c8b03e
EG		 2002 if (lp_up2 == 0)
2003 return;
2004
2005 for (bank = MDIO_REG_BANK_TX0; bank <= MDIO_REG_BANK_TX3;
2006 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) {
2007 CL45_RD_OVER_CL22(bp, params->port,
ea4e040a 2008 params->phy_addr,
c2c8b03e
EG		 2009 bank,
2010 MDIO_TX0_TX_DRIVER, &tx_driver);
2011
2012 /* replace tx_driver bits [15:12] */
2013 if (lp_up2 !=
2014 (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK)) {
2015 tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK;
2016 tx_driver |= lp_up2;
2017 CL45_WR_OVER_CL22(bp, params->port,
2018 params->phy_addr,
2019 bank,
2020 MDIO_TX0_TX_DRIVER, tx_driver);
2021 }
ea4e040a
YR		 2022 }
2023}
2024
2025static u8 bnx2x_emac_program(struct link_params *params,
2026 u32 line_speed, u32 duplex)
2027{
2028 struct bnx2x *bp = params->bp;
2029 u8 port = params->port;
2030 u16 mode = 0;
2031
2032 DP(NETIF_MSG_LINK, "setting link speed & duplex\n");
2033 bnx2x_bits_dis(bp, GRCBASE_EMAC0 + port*0x400 +
2034 EMAC_REG_EMAC_MODE,
2035 (EMAC_MODE_25G_MODE |
2036 EMAC_MODE_PORT_MII_10M |
2037 EMAC_MODE_HALF_DUPLEX));
2038 switch (line_speed) {
2039 case SPEED_10:
2040 mode |= EMAC_MODE_PORT_MII_10M;
2041 break;
2042
2043 case SPEED_100:
2044 mode |= EMAC_MODE_PORT_MII;
2045 break;
2046
2047 case SPEED_1000:
2048 mode |= EMAC_MODE_PORT_GMII;
2049 break;
2050
2051 case SPEED_2500:
2052 mode |= (EMAC_MODE_25G_MODE | EMAC_MODE_PORT_GMII);
2053 break;
2054
2055 default:
2056 /* 10G not valid for EMAC */
2057 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n", line_speed);
2058 return -EINVAL;
2059 }
2060
2061 if (duplex == DUPLEX_HALF)
2062 mode |= EMAC_MODE_HALF_DUPLEX;
2063 bnx2x_bits_en(bp,
2064 GRCBASE_EMAC0 + port*0x400 + EMAC_REG_EMAC_MODE,
2065 mode);
2066
7846e471 2067 bnx2x_set_led(params, LED_MODE_OPER, line_speed);
ea4e040a
YR		 2068 return 0;
2069}
2070
2071/*****************************************************************************/
17de50b7 2072/* External Phy section */
ea4e040a 2073/*****************************************************************************/
f57a6025 2074void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port)
ea4e040a
YR		 2075{
2076 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
17de50b7 2077 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
ea4e040a
YR		 2078 msleep(1);
2079 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
17de50b7 2080 MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
ea4e040a
YR		 2081}
2082
2083static void bnx2x_ext_phy_reset(struct link_params *params,
2084 struct link_vars *vars)
2085{
2086 struct bnx2x *bp = params->bp;
2087 u32 ext_phy_type;
659bc5c4
EG		 2088 u8 ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
2089
ea4e040a
YR		 2090 DP(NETIF_MSG_LINK, "Port %x: bnx2x_ext_phy_reset\n", params->port);
2091 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
2092 /* The PHY reset is controled by GPIO 1
2093 * Give it 1ms of reset pulse
2094 */
2095 if (vars->phy_flags & PHY_XGXS_FLAG) {
2096
2097 switch (ext_phy_type) {
2098 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
2099 DP(NETIF_MSG_LINK, "XGXS Direct\n");
2100 break;
2101
2102 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
2103 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
2104 DP(NETIF_MSG_LINK, "XGXS 8705/8706\n");
2105
2106 /* Restore normal power mode*/
2107 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
17de50b7
EG		 2108 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
2109 params->port);
ea4e040a
YR		 2110
2111 /* HW reset */
f57a6025 2112 bnx2x_ext_phy_hw_reset(bp, params->port);
ea4e040a
YR		 2113
2114 bnx2x_cl45_write(bp, params->port,
2115 ext_phy_type,
2116 ext_phy_addr,
2117 MDIO_PMA_DEVAD,
2118 MDIO_PMA_REG_CTRL, 0xa040);
2119 break;
4d295db0
EG		 2120
2121 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
2122 break;
2123
589abe3a
EG		 2124 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
2125
2126 /* Restore normal power mode*/
2127 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
2128 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
2129 params->port);
2130
2131 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
2132 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
2133 params->port);
2134
2135 bnx2x_cl45_write(bp, params->port,
2136 ext_phy_type,
2137 ext_phy_addr,
2138 MDIO_PMA_DEVAD,
2139 MDIO_PMA_REG_CTRL,
2140 1<<15);
589abe3a 2141 break;
ab6ad5a4 2142
ea4e040a 2143 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
ab6ad5a4
EG		 2144 DP(NETIF_MSG_LINK, "XGXS 8072\n");
2145
ea4e040a
YR		 2146 /* Unset Low Power Mode and SW reset */
2147 /* Restore normal power mode*/
2148 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
17de50b7
EG		 2149 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
2150 params->port);
ea4e040a 2151
ea4e040a
YR		 2152 bnx2x_cl45_write(bp, params->port,
2153 ext_phy_type,
2154 ext_phy_addr,
2155 MDIO_PMA_DEVAD,
2156 MDIO_PMA_REG_CTRL,
2157 1<<15);
2158 break;
ab6ad5a4 2159
ea4e040a 2160 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
ab6ad5a4 2161 DP(NETIF_MSG_LINK, "XGXS 8073\n");
ea4e040a
YR		 2162
2163 /* Restore normal power mode*/
2164 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
17de50b7
EG		 2165 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
2166 params->port);
ea4e040a
YR		 2167
2168 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
17de50b7
EG		 2169 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
2170 params->port);
ea4e040a
YR		 2171 break;
2172
2173 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
2174 DP(NETIF_MSG_LINK, "XGXS SFX7101\n");
2175
2176 /* Restore normal power mode*/
2177 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
17de50b7
EG		 2178 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
2179 params->port);
ea4e040a
YR		 2180
2181 /* HW reset */
f57a6025 2182 bnx2x_ext_phy_hw_reset(bp, params->port);
ea4e040a
YR		 2183 break;
2184
28577185 2185 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
28577185
EG		 2186 /* Restore normal power mode*/
2187 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
2188 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
2189 params->port);
2190
2191 /* HW reset */
f57a6025 2192 bnx2x_ext_phy_hw_reset(bp, params->port);
28577185
EG		 2193
2194 bnx2x_cl45_write(bp, params->port,
2195 ext_phy_type,
2196 ext_phy_addr,
2197 MDIO_PMA_DEVAD,
2198 MDIO_PMA_REG_CTRL,
2199 1<<15);
2200 break;
ea4e040a
YR		 2201 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
2202 DP(NETIF_MSG_LINK, "XGXS PHY Failure detected\n");
2203 break;
2204
2205 default:
2206 DP(NETIF_MSG_LINK, "BAD XGXS ext_phy_config 0x%x\n",
2207 params->ext_phy_config);
2208 break;
2209 }
2210
2211 } else { /* SerDes */
2212 ext_phy_type = SERDES_EXT_PHY_TYPE(params->ext_phy_config);
2213 switch (ext_phy_type) {
2214 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT:
2215 DP(NETIF_MSG_LINK, "SerDes Direct\n");
2216 break;
2217
2218 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482:
2219 DP(NETIF_MSG_LINK, "SerDes 5482\n");
f57a6025 2220 bnx2x_ext_phy_hw_reset(bp, params->port);
ea4e040a
YR		 2221 break;
2222
2223 default:
ab6ad5a4 2224 DP(NETIF_MSG_LINK, "BAD SerDes ext_phy_config 0x%x\n",
ea4e040a
YR		 2225 params->ext_phy_config);
2226 break;
2227 }
2228 }
2229}
2230
a35da8db
EG		 2231static void bnx2x_save_spirom_version(struct bnx2x *bp, u8 port,
2232 u32 shmem_base, u32 spirom_ver)
2233{
ab6ad5a4
EG		 2234 DP(NETIF_MSG_LINK, "FW version 0x%x:0x%x for port %d\n",
2235 (u16)(spirom_ver>>16), (u16)spirom_ver, port);
a35da8db
EG		 2236 REG_WR(bp, shmem_base +
2237 offsetof(struct shmem_region,
2238 port_mb[port].ext_phy_fw_version),
2239 spirom_ver);
2240}
2241
2242static void bnx2x_save_bcm_spirom_ver(struct bnx2x *bp, u8 port,
2243 u32 ext_phy_type, u8 ext_phy_addr,
2244 u32 shmem_base)
2245{
2246 u16 fw_ver1, fw_ver2;
ab6ad5a4 2247
a35da8db
EG		 2248 bnx2x_cl45_read(bp, port, ext_phy_type, ext_phy_addr, MDIO_PMA_DEVAD,
2249 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
2250 bnx2x_cl45_read(bp, port, ext_phy_type, ext_phy_addr, MDIO_PMA_DEVAD,
2251 MDIO_PMA_REG_ROM_VER2, &fw_ver2);
2252 bnx2x_save_spirom_version(bp, port, shmem_base,
2253 (u32)(fw_ver1<<16 | fw_ver2));
2254}
2255
b1607af5
EG		 2256
2257static void bnx2x_save_8481_spirom_version(struct bnx2x *bp, u8 port,
2258 u8 ext_phy_addr, u32 shmem_base)
2259{
2260 u16 val, fw_ver1, fw_ver2, cnt;
2261 /* For the 32 bits registers in 8481, access via MDIO2ARM interface.*/
2262 /* (1) set register 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */
2263 bnx2x_cl45_write(bp, port,
2264 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
2265 ext_phy_addr, MDIO_PMA_DEVAD,
2266 0xA819, 0x0014);
2267 bnx2x_cl45_write(bp, port,
2268 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
2269 ext_phy_addr,
2270 MDIO_PMA_DEVAD,
2271 0xA81A,
2272 0xc200);
2273 bnx2x_cl45_write(bp, port,
2274 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
2275 ext_phy_addr,
2276 MDIO_PMA_DEVAD,
2277 0xA81B,
2278 0x0000);
2279 bnx2x_cl45_write(bp, port,
2280 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
2281 ext_phy_addr,
2282 MDIO_PMA_DEVAD,
2283 0xA81C,
2284 0x0300);
2285 bnx2x_cl45_write(bp, port,
2286 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
2287 ext_phy_addr,
2288 MDIO_PMA_DEVAD,
2289 0xA817,
2290 0x0009);
2291
2292 for (cnt = 0; cnt < 100; cnt++) {
2293 bnx2x_cl45_read(bp, port,
2294 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
2295 ext_phy_addr,
2296 MDIO_PMA_DEVAD,
2297 0xA818,
2298 &val);
2299 if (val & 1)
2300 break;
2301 udelay(5);
2302 }
2303 if (cnt == 100) {
2304 DP(NETIF_MSG_LINK, "Unable to read 8481 phy fw version(1)\n");
2305 bnx2x_save_spirom_version(bp, port,
2306 shmem_base, 0);
2307 return;
2308 }
2309
2310
2311 /* 2) read register 0xc200_0000 (SPI_FW_STATUS) */
2312 bnx2x_cl45_write(bp, port,
2313 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
2314 ext_phy_addr, MDIO_PMA_DEVAD,
2315 0xA819, 0x0000);
2316 bnx2x_cl45_write(bp, port,
2317 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
2318 ext_phy_addr, MDIO_PMA_DEVAD,
2319 0xA81A, 0xc200);
2320 bnx2x_cl45_write(bp, port,
2321 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
2322 ext_phy_addr, MDIO_PMA_DEVAD,
2323 0xA817, 0x000A);
2324 for (cnt = 0; cnt < 100; cnt++) {
2325 bnx2x_cl45_read(bp, port,
2326 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
2327 ext_phy_addr,
2328 MDIO_PMA_DEVAD,
2329 0xA818,
2330 &val);
2331 if (val & 1)
2332 break;
2333 udelay(5);
2334 }
2335 if (cnt == 100) {
2336 DP(NETIF_MSG_LINK, "Unable to read 8481 phy fw version(2)\n");
2337 bnx2x_save_spirom_version(bp, port,
2338 shmem_base, 0);
2339 return;
2340 }
2341
2342 /* lower 16 bits of the register SPI_FW_STATUS */
2343 bnx2x_cl45_read(bp, port,
2344 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
2345 ext_phy_addr,
2346 MDIO_PMA_DEVAD,
2347 0xA81B,
2348 &fw_ver1);
2349 /* upper 16 bits of register SPI_FW_STATUS */
2350 bnx2x_cl45_read(bp, port,
2351 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
2352 ext_phy_addr,
2353 MDIO_PMA_DEVAD,
2354 0xA81C,
2355 &fw_ver2);
2356
2357 bnx2x_save_spirom_version(bp, port,
2358 shmem_base, (fw_ver2<<16) | fw_ver1);
2359}
2360
ea4e040a
YR		 2361static void bnx2x_bcm8072_external_rom_boot(struct link_params *params)
2362{
2363 struct bnx2x *bp = params->bp;
2364 u8 port = params->port;
659bc5c4 2365 u8 ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
ea4e040a 2366 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
ea4e040a
YR		 2367
2368 /* Need to wait 200ms after reset */
2369 msleep(200);
2370 /* Boot port from external ROM
2371 * Set ser_boot_ctl bit in the MISC_CTRL1 register
2372 */
2373 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2374 MDIO_PMA_DEVAD,
2375 MDIO_PMA_REG_MISC_CTRL1, 0x0001);
2376
2377 /* Reset internal microprocessor */
2378 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2379 MDIO_PMA_DEVAD,
2380 MDIO_PMA_REG_GEN_CTRL,
2381 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
2382 /* set micro reset = 0 */
2383 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2384 MDIO_PMA_DEVAD,
2385 MDIO_PMA_REG_GEN_CTRL,
2386 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
2387 /* Reset internal microprocessor */
2388 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2389 MDIO_PMA_DEVAD,
2390 MDIO_PMA_REG_GEN_CTRL,
2391 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
2392 /* wait for 100ms for code download via SPI port */
2393 msleep(100);
2394
2395 /* Clear ser_boot_ctl bit */
2396 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2397 MDIO_PMA_DEVAD,
2398 MDIO_PMA_REG_MISC_CTRL1, 0x0000);
2399 /* Wait 100ms */
2400 msleep(100);
2401
a35da8db
EG		 2402 bnx2x_save_bcm_spirom_ver(bp, port,
2403 ext_phy_type,
2404 ext_phy_addr,
2405 params->shmem_base);
ea4e040a
YR		 2406}
2407
2408static u8 bnx2x_8073_is_snr_needed(struct link_params *params)
2409{
2410 /* This is only required for 8073A1, version 102 only */
2411
2412 struct bnx2x *bp = params->bp;
659bc5c4 2413 u8 ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
ea4e040a
YR		 2414 u16 val;
2415
2416 /* Read 8073 HW revision*/
2417 bnx2x_cl45_read(bp, params->port,
2418 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
2419 ext_phy_addr,
2420 MDIO_PMA_DEVAD,
052a38e0 2421 MDIO_PMA_REG_8073_CHIP_REV, &val);
ea4e040a
YR		 2422
2423 if (val != 1) {
2424 /* No need to workaround in 8073 A1 */
2425 return 0;
2426 }
2427
2428 bnx2x_cl45_read(bp, params->port,
2429 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
2430 ext_phy_addr,
2431 MDIO_PMA_DEVAD,
2432 MDIO_PMA_REG_ROM_VER2, &val);
2433
2434 /* SNR should be applied only for version 0x102 */
2435 if (val != 0x102)
2436 return 0;
2437
2438 return 1;
2439}
2440
2441static u8 bnx2x_bcm8073_xaui_wa(struct link_params *params)
2442{
2443 struct bnx2x *bp = params->bp;
659bc5c4 2444 u8 ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
ea4e040a
YR		 2445 u16 val, cnt, cnt1 ;
2446
2447 bnx2x_cl45_read(bp, params->port,
2448 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
2449 ext_phy_addr,
2450 MDIO_PMA_DEVAD,
052a38e0 2451 MDIO_PMA_REG_8073_CHIP_REV, &val);
ea4e040a
YR		 2452
2453 if (val > 0) {
2454 /* No need to workaround in 8073 A1 */
2455 return 0;
2456 }
2457 /* XAUI workaround in 8073 A0: */
2458
2459 /* After loading the boot ROM and restarting Autoneg,
2460 poll Dev1, Reg $C820: */
2461
2462 for (cnt = 0; cnt < 1000; cnt++) {
2463 bnx2x_cl45_read(bp, params->port,
2464 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
2465 ext_phy_addr,
2466 MDIO_PMA_DEVAD,
052a38e0
EG		 2467 MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
2468 &val);
ea4e040a
YR		 2469 /* If bit [14] = 0 or bit [13] = 0, continue on with
2470 system initialization (XAUI work-around not required,
2471 as these bits indicate 2.5G or 1G link up). */
2472 if (!(val & (1<<14)) || !(val & (1<<13))) {
2473 DP(NETIF_MSG_LINK, "XAUI work-around not required\n");
2474 return 0;
2475 } else if (!(val & (1<<15))) {
2476 DP(NETIF_MSG_LINK, "clc bit 15 went off\n");
2477 /* If bit 15 is 0, then poll Dev1, Reg $C841 until
2478 it's MSB (bit 15) goes to 1 (indicating that the
2479 XAUI workaround has completed),
2480 then continue on with system initialization.*/
2481 for (cnt1 = 0; cnt1 < 1000; cnt1++) {
2482 bnx2x_cl45_read(bp, params->port,
2483 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
2484 ext_phy_addr,
2485 MDIO_PMA_DEVAD,
052a38e0 2486 MDIO_PMA_REG_8073_XAUI_WA, &val);
ea4e040a
YR		 2487 if (val & (1<<15)) {
2488 DP(NETIF_MSG_LINK,
2489 "XAUI workaround has completed\n");
2490 return 0;
2491 }
2492 msleep(3);
2493 }
2494 break;
2495 }
2496 msleep(3);
2497 }
2498 DP(NETIF_MSG_LINK, "Warning: XAUI work-around timeout !!!\n");
2499 return -EINVAL;
ea4e040a
YR		 2500}
2501
4d295db0
EG		 2502static void bnx2x_bcm8073_bcm8727_external_rom_boot(struct bnx2x *bp, u8 port,
2503 u8 ext_phy_addr,
2504 u32 ext_phy_type,
2505 u32 shmem_base)
ea4e040a 2506{
6bbca910 2507 /* Boot port from external ROM */
ea4e040a 2508 /* EDC grst */
6bbca910 2509 bnx2x_cl45_write(bp, port,
4d295db0 2510 ext_phy_type,
6bbca910 2511 ext_phy_addr,
ea4e040a
YR		 2512 MDIO_PMA_DEVAD,
2513 MDIO_PMA_REG_GEN_CTRL,
2514 0x0001);
2515
2516 /* ucode reboot and rst */
6bbca910 2517 bnx2x_cl45_write(bp, port,
4d295db0 2518 ext_phy_type,
6bbca910 2519 ext_phy_addr,
ea4e040a
YR		 2520 MDIO_PMA_DEVAD,
2521 MDIO_PMA_REG_GEN_CTRL,
2522 0x008c);
2523
6bbca910 2524 bnx2x_cl45_write(bp, port,
4d295db0 2525 ext_phy_type,
6bbca910 2526 ext_phy_addr,
ea4e040a
YR		 2527 MDIO_PMA_DEVAD,
2528 MDIO_PMA_REG_MISC_CTRL1, 0x0001);
2529
2530 /* Reset internal microprocessor */
6bbca910 2531 bnx2x_cl45_write(bp, port,
4d295db0 2532 ext_phy_type,
6bbca910 2533 ext_phy_addr,
ea4e040a
YR		 2534 MDIO_PMA_DEVAD,
2535 MDIO_PMA_REG_GEN_CTRL,
2536 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
2537
2538 /* Release srst bit */
6bbca910 2539 bnx2x_cl45_write(bp, port,
4d295db0 2540 ext_phy_type,
6bbca910 2541 ext_phy_addr,
ea4e040a
YR		 2542 MDIO_PMA_DEVAD,
2543 MDIO_PMA_REG_GEN_CTRL,
2544 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
2545
2546 /* wait for 100ms for code download via SPI port */
2547 msleep(100);
2548
2549 /* Clear ser_boot_ctl bit */
6bbca910 2550 bnx2x_cl45_write(bp, port,
4d295db0 2551 ext_phy_type,
6bbca910 2552 ext_phy_addr,
ea4e040a
YR		 2553 MDIO_PMA_DEVAD,
2554 MDIO_PMA_REG_MISC_CTRL1, 0x0000);
2555
a35da8db 2556 bnx2x_save_bcm_spirom_ver(bp, port,
4d295db0 2557 ext_phy_type,
a35da8db
EG		 2558 ext_phy_addr,
2559 shmem_base);
6bbca910 2560}
ea4e040a 2561
4d295db0
EG		 2562static void bnx2x_bcm8073_external_rom_boot(struct bnx2x *bp, u8 port,
2563 u8 ext_phy_addr,
2564 u32 shmem_base)
2565{
2566 bnx2x_bcm8073_bcm8727_external_rom_boot(bp, port, ext_phy_addr,
2567 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
2568 shmem_base);
2569}
2570
2571static void bnx2x_bcm8727_external_rom_boot(struct bnx2x *bp, u8 port,
2572 u8 ext_phy_addr,
2573 u32 shmem_base)
2574{
2575 bnx2x_bcm8073_bcm8727_external_rom_boot(bp, port, ext_phy_addr,
2576 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
2577 shmem_base);
2578
2579}
2580
589abe3a
EG		 2581static void bnx2x_bcm8726_external_rom_boot(struct link_params *params)
2582{
2583 struct bnx2x *bp = params->bp;
2584 u8 port = params->port;
659bc5c4 2585 u8 ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
589abe3a
EG		 2586 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
2587
2588 /* Need to wait 100ms after reset */
2589 msleep(100);
2590
2591 /* Set serial boot control for external load */
2592 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2593 MDIO_PMA_DEVAD,
2594 MDIO_PMA_REG_MISC_CTRL1, 0x0001);
2595
2596 /* Micro controller re-boot */
2597 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2598 MDIO_PMA_DEVAD,
2599 MDIO_PMA_REG_GEN_CTRL,
2600 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
2601
2602 /* Set soft reset */
2603 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2604 MDIO_PMA_DEVAD,
2605 MDIO_PMA_REG_GEN_CTRL,
2606 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
2607
4d295db0 2608 /* Set PLL register value to be same like in P13 ver */
cc1cb004
EG		 2609 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2610 MDIO_PMA_DEVAD,
4d295db0 2611 MDIO_PMA_REG_PLL_CTRL,
cc1cb004
EG		 2612 0x73A0);
2613
589abe3a
EG		 2614 /* Clear soft reset.
2615 Will automatically reset micro-controller re-boot */
2616 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2617 MDIO_PMA_DEVAD,
2618 MDIO_PMA_REG_GEN_CTRL,
2619 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
2620
cc1cb004
EG		 2621 /* wait for 150ms for microcode load */
2622 msleep(150);
589abe3a
EG		 2623
2624 /* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */
2625 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2626 MDIO_PMA_DEVAD,
2627 MDIO_PMA_REG_MISC_CTRL1, 0x0000);
2628
2629 msleep(200);
a35da8db
EG		 2630 bnx2x_save_bcm_spirom_ver(bp, port,
2631 ext_phy_type,
2632 ext_phy_addr,
2633 params->shmem_base);
589abe3a
EG		 2634}
2635
4d295db0
EG		 2636static void bnx2x_sfp_set_transmitter(struct bnx2x *bp, u8 port,
2637 u32 ext_phy_type, u8 ext_phy_addr,
2638 u8 tx_en)
589abe3a
EG		 2639{
2640 u16 val;
ab6ad5a4 2641
589abe3a
EG		 2642 DP(NETIF_MSG_LINK, "Setting transmitter tx_en=%x for port %x\n",
2643 tx_en, port);
2644 /* Disable/Enable transmitter ( TX laser of the SFP+ module.)*/
2645 bnx2x_cl45_read(bp, port,
4d295db0 2646 ext_phy_type,
589abe3a
EG		 2647 ext_phy_addr,
2648 MDIO_PMA_DEVAD,
2649 MDIO_PMA_REG_PHY_IDENTIFIER,
2650 &val);
2651
2652 if (tx_en)
2653 val &= ~(1<<15);
2654 else
2655 val |= (1<<15);
2656
2657 bnx2x_cl45_write(bp, port,
4d295db0 2658 ext_phy_type,
589abe3a
EG		 2659 ext_phy_addr,
2660 MDIO_PMA_DEVAD,
2661 MDIO_PMA_REG_PHY_IDENTIFIER,
2662 val);
2663}
2664
4d295db0
EG		 2665static u8 bnx2x_8726_read_sfp_module_eeprom(struct link_params *params,
2666 u16 addr, u8 byte_cnt, u8 *o_buf)
2667{
589abe3a 2668 struct bnx2x *bp = params->bp;
4d295db0
EG		 2669 u16 val = 0;
2670 u16 i;
589abe3a 2671 u8 port = params->port;
659bc5c4 2672 u8 ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
589abe3a 2673 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
ab6ad5a4 2674
589abe3a
EG		 2675 if (byte_cnt > 16) {
2676 DP(NETIF_MSG_LINK, "Reading from eeprom is"
2677 " is limited to 0xf\n");
2678 return -EINVAL;
2679 }
2680 /* Set the read command byte count */
2681 bnx2x_cl45_write(bp, port,
2682 ext_phy_type,
2683 ext_phy_addr,
2684 MDIO_PMA_DEVAD,
4d295db0 2685 MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
589abe3a
EG		 2686 (byte_cnt | 0xa000));
2687
2688 /* Set the read command address */
2689 bnx2x_cl45_write(bp, port,
2690 ext_phy_type,
2691 ext_phy_addr,
2692 MDIO_PMA_DEVAD,
4d295db0 2693 MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
589abe3a
EG		 2694 addr);
2695
2696 /* Activate read command */
2697 bnx2x_cl45_write(bp, port,
2698 ext_phy_type,
2699 ext_phy_addr,
2700 MDIO_PMA_DEVAD,
4d295db0 2701 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
589abe3a
EG		 2702 0x2c0f);
2703
2704 /* Wait up to 500us for command complete status */
2705 for (i = 0; i < 100; i++) {
2706 bnx2x_cl45_read(bp, port,
2707 ext_phy_type,
2708 ext_phy_addr,
2709 MDIO_PMA_DEVAD,
4d295db0
EG		 2710 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
2711 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
2712 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
589abe3a
EG		 2713 break;
2714 udelay(5);
2715 }
2716
4d295db0
EG		 2717 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
2718 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
589abe3a
EG		 2719 DP(NETIF_MSG_LINK,
2720 "Got bad status 0x%x when reading from SFP+ EEPROM\n",
4d295db0 2721 (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
589abe3a
EG		 2722 return -EINVAL;
2723 }
2724
2725 /* Read the buffer */
2726 for (i = 0; i < byte_cnt; i++) {
2727 bnx2x_cl45_read(bp, port,
2728 ext_phy_type,
2729 ext_phy_addr,
2730 MDIO_PMA_DEVAD,
2731 MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF + i, &val);
2732 o_buf[i] = (u8)(val & MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK);
2733 }
2734
2735 for (i = 0; i < 100; i++) {
2736 bnx2x_cl45_read(bp, port,
2737 ext_phy_type,
2738 ext_phy_addr,
2739 MDIO_PMA_DEVAD,
4d295db0
EG		 2740 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
2741 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
2742 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
2743 return 0;;
2744 msleep(1);
2745 }
2746 return -EINVAL;
2747}
2748
2749static u8 bnx2x_8727_read_sfp_module_eeprom(struct link_params *params,
2750 u16 addr, u8 byte_cnt, u8 *o_buf)
2751{
2752 struct bnx2x *bp = params->bp;
2753 u16 val, i;
2754 u8 port = params->port;
659bc5c4 2755 u8 ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
4d295db0
EG		 2756 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
2757
2758 if (byte_cnt > 16) {
2759 DP(NETIF_MSG_LINK, "Reading from eeprom is"
2760 " is limited to 0xf\n");
2761 return -EINVAL;
2762 }
2763
2764 /* Need to read from 1.8000 to clear it */
2765 bnx2x_cl45_read(bp, port,
2766 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
2767 ext_phy_addr,
2768 MDIO_PMA_DEVAD,
2769 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
2770 &val);
2771
2772 /* Set the read command byte count */
2773 bnx2x_cl45_write(bp, port,
2774 ext_phy_type,
2775 ext_phy_addr,
2776 MDIO_PMA_DEVAD,
2777 MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
2778 ((byte_cnt < 2) ? 2 : byte_cnt));
2779
2780 /* Set the read command address */
2781 bnx2x_cl45_write(bp, port,
2782 ext_phy_type,
2783 ext_phy_addr,
2784 MDIO_PMA_DEVAD,
2785 MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
2786 addr);
2787 /* Set the destination address */
2788 bnx2x_cl45_write(bp, port,
2789 ext_phy_type,
2790 ext_phy_addr,
2791 MDIO_PMA_DEVAD,
2792 0x8004,
2793 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF);
2794
2795 /* Activate read command */
2796 bnx2x_cl45_write(bp, port,
2797 ext_phy_type,
2798 ext_phy_addr,
2799 MDIO_PMA_DEVAD,
2800 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
2801 0x8002);
2802 /* Wait appropriate time for two-wire command to finish before
2803 polling the status register */
2804 msleep(1);
2805
2806 /* Wait up to 500us for command complete status */
2807 for (i = 0; i < 100; i++) {
2808 bnx2x_cl45_read(bp, port,
2809 ext_phy_type,
2810 ext_phy_addr,
2811 MDIO_PMA_DEVAD,
2812 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
2813 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
2814 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
2815 break;
2816 udelay(5);
2817 }
2818
2819 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
2820 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
2821 DP(NETIF_MSG_LINK,
2822 "Got bad status 0x%x when reading from SFP+ EEPROM\n",
2823 (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
2824 return -EINVAL;
2825 }
2826
2827 /* Read the buffer */
2828 for (i = 0; i < byte_cnt; i++) {
2829 bnx2x_cl45_read(bp, port,
2830 ext_phy_type,
2831 ext_phy_addr,
2832 MDIO_PMA_DEVAD,
2833 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF + i, &val);
2834 o_buf[i] = (u8)(val & MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK);
2835 }
2836
2837 for (i = 0; i < 100; i++) {
2838 bnx2x_cl45_read(bp, port,
2839 ext_phy_type,
2840 ext_phy_addr,
2841 MDIO_PMA_DEVAD,
2842 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
2843 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
2844 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
589abe3a
EG		 2845 return 0;;
2846 msleep(1);
2847 }
4d295db0 2848
589abe3a
EG		 2849 return -EINVAL;
2850}
2851
4d295db0
EG		 2852u8 bnx2x_read_sfp_module_eeprom(struct link_params *params, u16 addr,
2853 u8 byte_cnt, u8 *o_buf)
2854{
2855 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
2856
2857 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726)
2858 return bnx2x_8726_read_sfp_module_eeprom(params, addr,
2859 byte_cnt, o_buf);
2860 else if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727)
2861 return bnx2x_8727_read_sfp_module_eeprom(params, addr,
2862 byte_cnt, o_buf);
2863 return -EINVAL;
2864}
589abe3a 2865
4d295db0
EG		 2866static u8 bnx2x_get_edc_mode(struct link_params *params,
2867 u16 *edc_mode)
589abe3a
EG		 2868{
2869 struct bnx2x *bp = params->bp;
4d295db0
EG		 2870 u8 val, check_limiting_mode = 0;
2871 *edc_mode = EDC_MODE_LIMITING;
589abe3a
EG		 2872
2873 /* First check for copper cable */
2874 if (bnx2x_read_sfp_module_eeprom(params,
2875 SFP_EEPROM_CON_TYPE_ADDR,
2876 1,
2877 &val) != 0) {
4d295db0 2878 DP(NETIF_MSG_LINK, "Failed to read from SFP+ module EEPROM\n");
589abe3a
EG		 2879 return -EINVAL;
2880 }
2881
2882 switch (val) {
2883 case SFP_EEPROM_CON_TYPE_VAL_COPPER:
2884 {
2885 u8 copper_module_type;
ab6ad5a4 2886
589abe3a
EG		 2887 /* Check if its active cable( includes SFP+ module)
2888 of passive cable*/
2889 if (bnx2x_read_sfp_module_eeprom(params,
2890 SFP_EEPROM_FC_TX_TECH_ADDR,
2891 1,
2892 &copper_module_type) !=
2893 0) {
2894 DP(NETIF_MSG_LINK,
2895 "Failed to read copper-cable-type"
2896 " from SFP+ EEPROM\n");
2897 return -EINVAL;
2898 }
2899
2900 if (copper_module_type &
2901 SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) {
2902 DP(NETIF_MSG_LINK, "Active Copper cable detected\n");
4d295db0 2903 check_limiting_mode = 1;
589abe3a
EG		 2904 } else if (copper_module_type &
2905 SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE) {
2906 DP(NETIF_MSG_LINK, "Passive Copper"
2907 " cable detected\n");
4d295db0
EG		 2908 *edc_mode =
2909 EDC_MODE_PASSIVE_DAC;
589abe3a
EG		 2910 } else {
2911 DP(NETIF_MSG_LINK, "Unknown copper-cable-"
2912 "type 0x%x !!!\n", copper_module_type);
2913 return -EINVAL;
2914 }
2915 break;
2916 }
2917 case SFP_EEPROM_CON_TYPE_VAL_LC:
2918 DP(NETIF_MSG_LINK, "Optic module detected\n");
4d295db0 2919 check_limiting_mode = 1;
589abe3a 2920 break;
589abe3a
EG		 2921 default:
2922 DP(NETIF_MSG_LINK, "Unable to determine module type 0x%x !!!\n",
2923 val);
2924 return -EINVAL;
2925 }
4d295db0
EG		 2926
2927 if (check_limiting_mode) {
2928 u8 options[SFP_EEPROM_OPTIONS_SIZE];
2929 if (bnx2x_read_sfp_module_eeprom(params,
2930 SFP_EEPROM_OPTIONS_ADDR,
2931 SFP_EEPROM_OPTIONS_SIZE,
2932 options) != 0) {
2933 DP(NETIF_MSG_LINK, "Failed to read Option"
2934 " field from module EEPROM\n");
2935 return -EINVAL;
2936 }
2937 if ((options[0] & SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK))
2938 *edc_mode = EDC_MODE_LINEAR;
2939 else
2940 *edc_mode = EDC_MODE_LIMITING;
2941 }
2942 DP(NETIF_MSG_LINK, "EDC mode is set to 0x%x\n", *edc_mode);
589abe3a
EG		 2943 return 0;
2944}
2945
589abe3a
EG		 2946/* This function read the relevant field from the module ( SFP+ ),
2947 and verify it is compliant with this board */
4d295db0 2948static u8 bnx2x_verify_sfp_module(struct link_params *params)
589abe3a
EG		 2949{
2950 struct bnx2x *bp = params->bp;
4d295db0
EG		 2951 u32 val;
2952 u32 fw_resp;
2953 char vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE+1];
2954 char vendor_pn[SFP_EEPROM_PART_NO_SIZE+1];
2955
2956 val = REG_RD(bp, params->shmem_base +
2957 offsetof(struct shmem_region, dev_info.
2958 port_feature_config[params->port].config));
2959 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
2960 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT) {
589abe3a
EG		 2961 DP(NETIF_MSG_LINK, "NOT enforcing module verification\n");
2962 return 0;
2963 }
2964
4d295db0
EG		 2965 /* Ask the FW to validate the module */
2966 if (!(params->feature_config_flags &
2967 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY)) {
2968 DP(NETIF_MSG_LINK, "FW does not support OPT MDL "
2969 "verification\n");
2970 return -EINVAL;
2971 }
2972
2973 fw_resp = bnx2x_fw_command(bp, DRV_MSG_CODE_VRFY_OPT_MDL);
2974 if (fw_resp == FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS) {
2975 DP(NETIF_MSG_LINK, "Approved module\n");
589abe3a
EG		 2976 return 0;
2977 }
2978
4d295db0 2979 /* format the warning message */
589abe3a
EG		 2980 if (bnx2x_read_sfp_module_eeprom(params,
2981 SFP_EEPROM_VENDOR_NAME_ADDR,
2982 SFP_EEPROM_VENDOR_NAME_SIZE,
4d295db0
EG		 2983 (u8 *)vendor_name))
2984 vendor_name[0] = '\0';
2985 else
2986 vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE] = '\0';
2987 if (bnx2x_read_sfp_module_eeprom(params,
2988 SFP_EEPROM_PART_NO_ADDR,
2989 SFP_EEPROM_PART_NO_SIZE,
2990 (u8 *)vendor_pn))
2991 vendor_pn[0] = '\0';
2992 else
2993 vendor_pn[SFP_EEPROM_PART_NO_SIZE] = '\0';
589abe3a 2994
4d295db0
EG		 2995 printk(KERN_INFO PFX "Warning: "
2996 "Unqualified SFP+ module "
2997 "detected on %s, Port %d from %s part number %s\n"
2998 , bp->dev->name, params->port,
2999 vendor_name, vendor_pn);
589abe3a
EG		 3000 return -EINVAL;
3001}
3002
589abe3a 3003static u8 bnx2x_bcm8726_set_limiting_mode(struct link_params *params,
4d295db0 3004 u16 edc_mode)
589abe3a
EG		 3005{
3006 struct bnx2x *bp = params->bp;
3007 u8 port = params->port;
659bc5c4 3008 u8 ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
cc1cb004 3009 u16 cur_limiting_mode;
cc1cb004
EG		 3010
3011 bnx2x_cl45_read(bp, port,
3012 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
3013 ext_phy_addr,
3014 MDIO_PMA_DEVAD,
3015 MDIO_PMA_REG_ROM_VER2,
3016 &cur_limiting_mode);
3017 DP(NETIF_MSG_LINK, "Current Limiting mode is 0x%x\n",
3018 cur_limiting_mode);
3019
4d295db0 3020 if (edc_mode == EDC_MODE_LIMITING) {
589abe3a 3021 DP(NETIF_MSG_LINK,
4d295db0 3022 "Setting LIMITING MODE\n");
589abe3a
EG		 3023 bnx2x_cl45_write(bp, port,
3024 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
3025 ext_phy_addr,
3026 MDIO_PMA_DEVAD,
3027 MDIO_PMA_REG_ROM_VER2,
4d295db0 3028 EDC_MODE_LIMITING);
589abe3a 3029 } else { /* LRM mode ( default )*/
cc1cb004 3030
4d295db0 3031 DP(NETIF_MSG_LINK, "Setting LRM MODE\n");
589abe3a 3032
589abe3a
EG		 3033 /* Changing to LRM mode takes quite few seconds.
3034 So do it only if current mode is limiting
3035 ( default is LRM )*/
4d295db0 3036 if (cur_limiting_mode != EDC_MODE_LIMITING)
589abe3a
EG		 3037 return 0;
3038
3039 bnx2x_cl45_write(bp, port,
3040 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
3041 ext_phy_addr,
3042 MDIO_PMA_DEVAD,
3043 MDIO_PMA_REG_LRM_MODE,
3044 0);
3045 bnx2x_cl45_write(bp, port,
3046 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
3047 ext_phy_addr,
3048 MDIO_PMA_DEVAD,
3049 MDIO_PMA_REG_ROM_VER2,
3050 0x128);
3051 bnx2x_cl45_write(bp, port,
3052 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
3053 ext_phy_addr,
3054 MDIO_PMA_DEVAD,
3055 MDIO_PMA_REG_MISC_CTRL0,
3056 0x4008);
3057 bnx2x_cl45_write(bp, port,
3058 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
3059 ext_phy_addr,
3060 MDIO_PMA_DEVAD,
3061 MDIO_PMA_REG_LRM_MODE,
3062 0xaaaa);
3063 }
3064 return 0;
3065}
3066
4d295db0
EG		 3067static u8 bnx2x_bcm8727_set_limiting_mode(struct link_params *params,
3068 u16 edc_mode)
3069{
3070 struct bnx2x *bp = params->bp;
3071 u8 port = params->port;
3072 u16 phy_identifier;
3073 u16 rom_ver2_val;
659bc5c4 3074 u8 ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
4d295db0
EG		 3075
3076 bnx2x_cl45_read(bp, port,
3077 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
3078 ext_phy_addr,
3079 MDIO_PMA_DEVAD,
3080 MDIO_PMA_REG_PHY_IDENTIFIER,
3081 &phy_identifier);
3082
3083 bnx2x_cl45_write(bp, port,
3084 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
3085 ext_phy_addr,
3086 MDIO_PMA_DEVAD,
3087 MDIO_PMA_REG_PHY_IDENTIFIER,
3088 (phy_identifier & ~(1<<9)));
3089
3090 bnx2x_cl45_read(bp, port,
3091 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
3092 ext_phy_addr,
3093 MDIO_PMA_DEVAD,
3094 MDIO_PMA_REG_ROM_VER2,
3095 &rom_ver2_val);
3096 /* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */
3097 bnx2x_cl45_write(bp, port,
3098 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
3099 ext_phy_addr,
3100 MDIO_PMA_DEVAD,
3101 MDIO_PMA_REG_ROM_VER2,
3102 (rom_ver2_val & 0xff00) | (edc_mode & 0x00ff));
3103
3104 bnx2x_cl45_write(bp, port,
3105 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
3106 ext_phy_addr,
3107 MDIO_PMA_DEVAD,
3108 MDIO_PMA_REG_PHY_IDENTIFIER,
3109 (phy_identifier | (1<<9)));
3110
3111 return 0;
3112}
3113
3114
589abe3a
EG		 3115static u8 bnx2x_wait_for_sfp_module_initialized(struct link_params *params)
3116{
3117 u8 val;
3118 struct bnx2x *bp = params->bp;
3119 u16 timeout;
3120 /* Initialization time after hot-plug may take up to 300ms for some
3121 phys type ( e.g. JDSU ) */
3122 for (timeout = 0; timeout < 60; timeout++) {
3123 if (bnx2x_read_sfp_module_eeprom(params, 1, 1, &val)
3124 == 0) {
3125 DP(NETIF_MSG_LINK, "SFP+ module initialization "
3126 "took %d ms\n", timeout * 5);
3127 return 0;
3128 }
3129 msleep(5);
3130 }
3131 return -EINVAL;
3132}
3133
4d295db0
EG		 3134static void bnx2x_8727_power_module(struct bnx2x *bp,
3135 struct link_params *params,
3136 u8 ext_phy_addr, u8 is_power_up) {
3137 /* Make sure GPIOs are not using for LED mode */
3138 u16 val;
3139 u8 port = params->port;
3140 /*
3141 * In the GPIO register, bit 4 is use to detemine if the GPIOs are
3142 * operating as INPUT or as OUTPUT. Bit 1 is for input, and 0 for
3143 * output
3144 * Bits 0-1 determine the gpios value for OUTPUT in case bit 4 val is 0
3145 * Bits 8-9 determine the gpios value for INPUT in case bit 4 val is 1
3146 * where the 1st bit is the over-current(only input), and 2nd bit is
3147 * for power( only output )
3148 */
3149
3150 /*
3151 * In case of NOC feature is disabled and power is up, set GPIO control
3152 * as input to enable listening of over-current indication
3153 */
3154
3155 if (!(params->feature_config_flags &
3156 FEATURE_CONFIG_BCM8727_NOC) && is_power_up)
3157 val = (1<<4);
3158 else
3159 /*
3160 * Set GPIO control to OUTPUT, and set the power bit
3161 * to according to the is_power_up
3162 */
3163 val = ((!(is_power_up)) << 1);
3164
3165 bnx2x_cl45_write(bp, port,
3166 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
3167 ext_phy_addr,
3168 MDIO_PMA_DEVAD,
3169 MDIO_PMA_REG_8727_GPIO_CTRL,
3170 val);
3171}
3172
589abe3a
EG		 3173static u8 bnx2x_sfp_module_detection(struct link_params *params)
3174{
3175 struct bnx2x *bp = params->bp;
4d295db0
EG		 3176 u16 edc_mode;
3177 u8 rc = 0;
659bc5c4 3178 u8 ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
589abe3a 3179 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
4d295db0
EG		 3180 u32 val = REG_RD(bp, params->shmem_base +
3181 offsetof(struct shmem_region, dev_info.
3182 port_feature_config[params->port].config));
589abe3a
EG		 3183
3184 DP(NETIF_MSG_LINK, "SFP+ module plugged in/out detected on port %d\n",
3185 params->port);
3186
4d295db0 3187 if (bnx2x_get_edc_mode(params, &edc_mode) != 0) {
589abe3a 3188 DP(NETIF_MSG_LINK, "Failed to get valid module type\n");
4d295db0
EG		 3189 return -EINVAL;
3190 } else if (bnx2x_verify_sfp_module(params) !=
589abe3a
EG		 3191 0) {
3192 /* check SFP+ module compatibility */
3193 DP(NETIF_MSG_LINK, "Module verification failed!!\n");
4d295db0 3194 rc = -EINVAL;
589abe3a
EG		 3195 /* Turn on fault module-detected led */
3196 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
3197 MISC_REGISTERS_GPIO_HIGH,
3198 params->port);
4d295db0
EG		 3199 if ((ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) &&
3200 ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
3201 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN)) {
3202 /* Shutdown SFP+ module */
3203 DP(NETIF_MSG_LINK, "Shutdown SFP+ module!!\n");
3204 bnx2x_8727_power_module(bp, params,
3205 ext_phy_addr, 0);
3206 return rc;
3207 }
3208 } else {
3209 /* Turn off fault module-detected led */
3210 DP(NETIF_MSG_LINK, "Turn off fault module-detected led\n");
3211 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
3212 MISC_REGISTERS_GPIO_LOW,
3213 params->port);
589abe3a
EG		 3214 }
3215
4d295db0
EG		 3216 /* power up the SFP module */
3217 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727)
3218 bnx2x_8727_power_module(bp, params, ext_phy_addr, 1);
589abe3a 3219
4d295db0
EG		 3220 /* Check and set limiting mode / LRM mode on 8726.
3221 On 8727 it is done automatically */
3222 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726)
3223 bnx2x_bcm8726_set_limiting_mode(params, edc_mode);
3224 else
3225 bnx2x_bcm8727_set_limiting_mode(params, edc_mode);
3226 /*
3227 * Enable transmit for this module if the module is approved, or
3228 * if unapproved modules should also enable the Tx laser
3229 */
3230 if (rc == 0 ||
3231 (val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) !=
3232 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
3233 bnx2x_sfp_set_transmitter(bp, params->port,
3234 ext_phy_type, ext_phy_addr, 1);
3235 else
3236 bnx2x_sfp_set_transmitter(bp, params->port,
3237 ext_phy_type, ext_phy_addr, 0);
589abe3a 3238
4d295db0 3239 return rc;
589abe3a
EG		 3240}
3241
3242void bnx2x_handle_module_detect_int(struct link_params *params)
3243{
3244 struct bnx2x *bp = params->bp;
3245 u32 gpio_val;
3246 u8 port = params->port;
ab6ad5a4 3247
589abe3a
EG		 3248 /* Set valid module led off */
3249 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
3250 MISC_REGISTERS_GPIO_HIGH,
3251 params->port);
3252
3253 /* Get current gpio val refelecting module plugged in / out*/
3254 gpio_val = bnx2x_get_gpio(bp, MISC_REGISTERS_GPIO_3, port);
3255
3256 /* Call the handling function in case module is detected */
3257 if (gpio_val == 0) {
3258
3259 bnx2x_set_gpio_int(bp, MISC_REGISTERS_GPIO_3,
3260 MISC_REGISTERS_GPIO_INT_OUTPUT_CLR,
3261 port);
3262
4d295db0
EG		 3263 if (bnx2x_wait_for_sfp_module_initialized(params) ==
3264 0)
589abe3a
EG		 3265 bnx2x_sfp_module_detection(params);
3266 else
3267 DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
3268 } else {
659bc5c4
EG		 3269 u8 ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
3270
4d295db0
EG		 3271 u32 ext_phy_type =
3272 XGXS_EXT_PHY_TYPE(params->ext_phy_config);
3273 u32 val = REG_RD(bp, params->shmem_base +
3274 offsetof(struct shmem_region, dev_info.
3275 port_feature_config[params->port].
3276 config));
3277
589abe3a
EG		 3278 bnx2x_set_gpio_int(bp, MISC_REGISTERS_GPIO_3,
3279 MISC_REGISTERS_GPIO_INT_OUTPUT_SET,
3280 port);
3281 /* Module was plugged out. */
3282 /* Disable transmit for this module */
4d295db0
EG		 3283 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
3284 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
3285 bnx2x_sfp_set_transmitter(bp, params->port,
3286 ext_phy_type, ext_phy_addr, 0);
589abe3a
EG		 3287 }
3288}
3289
6bbca910
YR		 3290static void bnx2x_bcm807x_force_10G(struct link_params *params)
3291{
3292 struct bnx2x *bp = params->bp;
3293 u8 port = params->port;
659bc5c4 3294 u8 ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
6bbca910
YR		 3295 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
3296
3297 /* Force KR or KX */
ea4e040a
YR		 3298 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
3299 MDIO_PMA_DEVAD,
6bbca910
YR		 3300 MDIO_PMA_REG_CTRL,
3301 0x2040);
ea4e040a
YR		 3302 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
3303 MDIO_PMA_DEVAD,
6bbca910
YR		 3304 MDIO_PMA_REG_10G_CTRL2,
3305 0x000b);
3306 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
3307 MDIO_PMA_DEVAD,
3308 MDIO_PMA_REG_BCM_CTRL,
3309 0x0000);
3310 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
3311 MDIO_AN_DEVAD,
3312 MDIO_AN_REG_CTRL,
3313 0x0000);
ea4e040a 3314}
ab6ad5a4 3315
ea4e040a
YR		 3316static void bnx2x_bcm8073_set_xaui_low_power_mode(struct link_params *params)
3317{
3318 struct bnx2x *bp = params->bp;
3319 u8 port = params->port;
3320 u16 val;
659bc5c4 3321 u8 ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
ea4e040a
YR		 3322 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
3323
3324 bnx2x_cl45_read(bp, params->port,
3325 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
3326 ext_phy_addr,
3327 MDIO_PMA_DEVAD,
052a38e0 3328 MDIO_PMA_REG_8073_CHIP_REV, &val);
ea4e040a
YR		 3329
3330 if (val == 0) {
3331 /* Mustn't set low power mode in 8073 A0 */
3332 return;
3333 }
3334
3335 /* Disable PLL sequencer (use read-modify-write to clear bit 13) */
3336 bnx2x_cl45_read(bp, port, ext_phy_type, ext_phy_addr,
3337 MDIO_XS_DEVAD,
3338 MDIO_XS_PLL_SEQUENCER, &val);
3339 val &= ~(1<<13);
3340 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
3341 MDIO_XS_DEVAD, MDIO_XS_PLL_SEQUENCER, val);
3342
3343 /* PLL controls */
3344 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
3345 MDIO_XS_DEVAD, 0x805E, 0x1077);
3346 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
3347 MDIO_XS_DEVAD, 0x805D, 0x0000);
3348 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
3349 MDIO_XS_DEVAD, 0x805C, 0x030B);
3350 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
3351 MDIO_XS_DEVAD, 0x805B, 0x1240);
3352 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
3353 MDIO_XS_DEVAD, 0x805A, 0x2490);
3354
3355 /* Tx Controls */
3356 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
3357 MDIO_XS_DEVAD, 0x80A7, 0x0C74);
3358 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
3359 MDIO_XS_DEVAD, 0x80A6, 0x9041);
3360 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
3361 MDIO_XS_DEVAD, 0x80A5, 0x4640);
3362
3363 /* Rx Controls */
3364 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
3365 MDIO_XS_DEVAD, 0x80FE, 0x01C4);
3366 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
3367 MDIO_XS_DEVAD, 0x80FD, 0x9249);
3368 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
3369 MDIO_XS_DEVAD, 0x80FC, 0x2015);
3370
3371 /* Enable PLL sequencer (use read-modify-write to set bit 13) */
3372 bnx2x_cl45_read(bp, port, ext_phy_type, ext_phy_addr,
3373 MDIO_XS_DEVAD,
3374 MDIO_XS_PLL_SEQUENCER, &val);
3375 val |= (1<<13);
3376 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
3377 MDIO_XS_DEVAD, MDIO_XS_PLL_SEQUENCER, val);
3378}
6bbca910
YR		 3379
3380static void bnx2x_8073_set_pause_cl37(struct link_params *params,
3381 struct link_vars *vars)
ea4e040a
YR		 3382{
3383 struct bnx2x *bp = params->bp;
6bbca910 3384 u16 cl37_val;
659bc5c4 3385 u8 ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
ea4e040a
YR		 3386 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
3387
6bbca910
YR		 3388 bnx2x_cl45_read(bp, params->port,
3389 ext_phy_type,
3390 ext_phy_addr,
3391 MDIO_AN_DEVAD,
3392 MDIO_AN_REG_CL37_FC_LD, &cl37_val);
3393
3394 cl37_val &= ~MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3395 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
3396
3397 if ((vars->ieee_fc &
3398 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) ==
3399 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) {
3400 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC;
3401 }
3402 if ((vars->ieee_fc &
3403 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
3404 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
3405 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
3406 }
3407 if ((vars->ieee_fc &
3408 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
3409 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
3410 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3411 }
3412 DP(NETIF_MSG_LINK,
3413 "Ext phy AN advertize cl37 0x%x\n", cl37_val);
3414
3415 bnx2x_cl45_write(bp, params->port,
3416 ext_phy_type,
3417 ext_phy_addr,
ea4e040a 3418 MDIO_AN_DEVAD,
6bbca910
YR		 3419 MDIO_AN_REG_CL37_FC_LD, cl37_val);
3420 msleep(500);
ea4e040a
YR		 3421}
3422
3423static void bnx2x_ext_phy_set_pause(struct link_params *params,
3424 struct link_vars *vars)
3425{
3426 struct bnx2x *bp = params->bp;
3427 u16 val;
659bc5c4 3428 u8 ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
ea4e040a
YR		 3429 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
3430
3431 /* read modify write pause advertizing */
3432 bnx2x_cl45_read(bp, params->port,
3433 ext_phy_type,
3434 ext_phy_addr,
3435 MDIO_AN_DEVAD,
3436 MDIO_AN_REG_ADV_PAUSE, &val);
3437
3438 val &= ~MDIO_AN_REG_ADV_PAUSE_BOTH;
8c99e7b0 3439
ea4e040a
YR		 3440 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
3441
8c99e7b0
YR		 3442 if ((vars->ieee_fc &
3443 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
ea4e040a
YR		 3444 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
3445 val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
3446 }
8c99e7b0
YR		 3447 if ((vars->ieee_fc &
3448 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
ea4e040a
YR		 3449 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
3450 val |=
3451 MDIO_AN_REG_ADV_PAUSE_PAUSE;
3452 }
3453 DP(NETIF_MSG_LINK,
3454 "Ext phy AN advertize 0x%x\n", val);
3455 bnx2x_cl45_write(bp, params->port,
3456 ext_phy_type,
3457 ext_phy_addr,
3458 MDIO_AN_DEVAD,
3459 MDIO_AN_REG_ADV_PAUSE, val);
3460}
c2c8b03e
EG		 3461static void bnx2x_set_preemphasis(struct link_params *params)
3462{
3463 u16 bank, i = 0;
3464 struct bnx2x *bp = params->bp;
ea4e040a 3465
c2c8b03e
EG		 3466 for (bank = MDIO_REG_BANK_RX0, i = 0; bank <= MDIO_REG_BANK_RX3;
3467 bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0), i++) {
3468 CL45_WR_OVER_CL22(bp, params->port,
3469 params->phy_addr,
3470 bank,
3471 MDIO_RX0_RX_EQ_BOOST,
3472 params->xgxs_config_rx[i]);
3473 }
3474
3475 for (bank = MDIO_REG_BANK_TX0, i = 0; bank <= MDIO_REG_BANK_TX3;
3476 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0), i++) {
3477 CL45_WR_OVER_CL22(bp, params->port,
3478 params->phy_addr,
3479 bank,
3480 MDIO_TX0_TX_DRIVER,
3481 params->xgxs_config_tx[i]);
3482 }
3483}
57963ed9 3484
2f904460
EG		 3485
3486static void bnx2x_8481_set_led4(struct link_params *params,
3487 u32 ext_phy_type, u8 ext_phy_addr)
3488{
3489 struct bnx2x *bp = params->bp;
3490
3491 /* PHYC_CTL_LED_CTL */
3492 bnx2x_cl45_write(bp, params->port,
3493 ext_phy_type,
3494 ext_phy_addr,
3495 MDIO_PMA_DEVAD,
3496 MDIO_PMA_REG_8481_LINK_SIGNAL, 0xa482);
3497
3498 /* Unmask LED4 for 10G link */
3499 bnx2x_cl45_write(bp, params->port,
3500 ext_phy_type,
3501 ext_phy_addr,
3502 MDIO_PMA_DEVAD,
3503 MDIO_PMA_REG_8481_SIGNAL_MASK, (1<<6));
3504 /* 'Interrupt Mask' */
3505 bnx2x_cl45_write(bp, params->port,
3506 ext_phy_type,
3507 ext_phy_addr,
3508 MDIO_AN_DEVAD,
3509 0xFFFB, 0xFFFD);
3510}
3511static void bnx2x_8481_set_legacy_led_mode(struct link_params *params,
3512 u32 ext_phy_type, u8 ext_phy_addr)
3513{
3514 struct bnx2x *bp = params->bp;
3515
3516 /* LED1 (10G Link): Disable LED1 when 10/100/1000 link */
3517 /* LED2 (1G/100/10 Link): Enable LED2 when 10/100/1000 link) */
3518 bnx2x_cl45_write(bp, params->port,
3519 ext_phy_type,
3520 ext_phy_addr,
3521 MDIO_AN_DEVAD,
3522 MDIO_AN_REG_8481_LEGACY_SHADOW,
3523 (1<<15) | (0xd << 10) | (0xc<<4) | 0xe);
3524}
3525
3526static void bnx2x_8481_set_10G_led_mode(struct link_params *params,
3527 u32 ext_phy_type, u8 ext_phy_addr)
3528{
3529 struct bnx2x *bp = params->bp;
3530 u16 val1;
3531
3532 /* LED1 (10G Link) */
3533 /* Enable continuse based on source 7(10G-link) */
3534 bnx2x_cl45_read(bp, params->port,
3535 ext_phy_type,
3536 ext_phy_addr,
3537 MDIO_PMA_DEVAD,
3538 MDIO_PMA_REG_8481_LINK_SIGNAL,
3539 &val1);
3540 /* Set bit 2 to 0, and bits [1:0] to 10 */
3541 val1 &= ~((1<<0) | (1<<2)); /* Clear bits 0,2*/
3542 val1 |= (1<<1); /* Set bit 1 */
3543
3544 bnx2x_cl45_write(bp, params->port,
3545 ext_phy_type,
3546 ext_phy_addr,
3547 MDIO_PMA_DEVAD,
3548 MDIO_PMA_REG_8481_LINK_SIGNAL,
3549 val1);
3550
3551 /* Unmask LED1 for 10G link */
3552 bnx2x_cl45_read(bp, params->port,
3553 ext_phy_type,
3554 ext_phy_addr,
3555 MDIO_PMA_DEVAD,
3556 MDIO_PMA_REG_8481_LED1_MASK,
3557 &val1);
3558 /* Set bit 2 to 0, and bits [1:0] to 10 */
3559 val1 |= (1<<7);
3560 bnx2x_cl45_write(bp, params->port,
3561 ext_phy_type,
3562 ext_phy_addr,
3563 MDIO_PMA_DEVAD,
3564 MDIO_PMA_REG_8481_LED1_MASK,
3565 val1);
3566
3567 /* LED2 (1G/100/10G Link) */
3568 /* Mask LED2 for 10G link */
3569 bnx2x_cl45_write(bp, params->port,
3570 ext_phy_type,
3571 ext_phy_addr,
3572 MDIO_PMA_DEVAD,
3573 MDIO_PMA_REG_8481_LED2_MASK,
3574 0);
3575
3576 /* LED3 (10G/1G/100/10G Activity) */
3577 bnx2x_cl45_read(bp, params->port,
3578 ext_phy_type,
3579 ext_phy_addr,
3580 MDIO_PMA_DEVAD,
3581 MDIO_PMA_REG_8481_LINK_SIGNAL,
3582 &val1);
3583 /* Enable blink based on source 4(Activity) */
3584 val1 &= ~((1<<7) | (1<<8)); /* Clear bits 7,8 */
3585 val1 |= (1<<6); /* Set only bit 6 */
3586 bnx2x_cl45_write(bp, params->port,
3587 ext_phy_type,
3588 ext_phy_addr,
3589 MDIO_PMA_DEVAD,
3590 MDIO_PMA_REG_8481_LINK_SIGNAL,
3591 val1);
3592
3593 bnx2x_cl45_read(bp, params->port,
3594 ext_phy_type,
3595 ext_phy_addr,
3596 MDIO_PMA_DEVAD,
3597 MDIO_PMA_REG_8481_LED3_MASK,
3598 &val1);
3599 val1 |= (1<<4); /* Unmask LED3 for 10G link */
3600 bnx2x_cl45_write(bp, params->port,
3601 ext_phy_type,
3602 ext_phy_addr,
3603 MDIO_PMA_DEVAD,
3604 MDIO_PMA_REG_8481_LED3_MASK,
3605 val1);
3606}
3607
3608
57963ed9 3609static void bnx2x_init_internal_phy(struct link_params *params,
239d686d
EG		 3610 struct link_vars *vars,
3611 u8 enable_cl73)
57963ed9
YR		 3612{
3613 struct bnx2x *bp = params->bp;
ab6ad5a4 3614
57963ed9 3615 if (!(vars->phy_flags & PHY_SGMII_FLAG)) {
c2c8b03e
EG		 3616 if ((XGXS_EXT_PHY_TYPE(params->ext_phy_config) ==
3617 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
3618 (params->feature_config_flags &
3619 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED))
3620 bnx2x_set_preemphasis(params);
57963ed9
YR		 3621
3622 /* forced speed requested? */
7846e471
YR		 3623 if (vars->line_speed != SPEED_AUTO_NEG ||
3624 ((XGXS_EXT_PHY_TYPE(params->ext_phy_config) ==
3625 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
3626 params->loopback_mode == LOOPBACK_EXT)) {
57963ed9
YR		 3627 DP(NETIF_MSG_LINK, "not SGMII, no AN\n");
3628
3629 /* disable autoneg */
239d686d 3630 bnx2x_set_autoneg(params, vars, 0);
57963ed9
YR		 3631
3632 /* program speed and duplex */
8c99e7b0 3633 bnx2x_program_serdes(params, vars);
57963ed9
YR		 3634
3635 } else { /* AN_mode */
3636 DP(NETIF_MSG_LINK, "not SGMII, AN\n");
3637
3638 /* AN enabled */
3639 bnx2x_set_brcm_cl37_advertisment(params);
3640
3641 /* program duplex & pause advertisement (for aneg) */
3642 bnx2x_set_ieee_aneg_advertisment(params,
8c99e7b0 3643 vars->ieee_fc);
57963ed9
YR		 3644
3645 /* enable autoneg */
239d686d 3646 bnx2x_set_autoneg(params, vars, enable_cl73);
57963ed9
YR		 3647
3648 /* enable and restart AN */
239d686d 3649 bnx2x_restart_autoneg(params, enable_cl73);
57963ed9
YR		 3650 }
3651
3652 } else { /* SGMII mode */
3653 DP(NETIF_MSG_LINK, "SGMII\n");
3654
8c99e7b0 3655 bnx2x_initialize_sgmii_process(params, vars);
57963ed9
YR		 3656 }
3657}
3658
ea4e040a
YR		 3659static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars)
3660{
3661 struct bnx2x *bp = params->bp;
3662 u32 ext_phy_type;
3663 u8 ext_phy_addr;
3664 u16 cnt;
3665 u16 ctrl = 0;
3666 u16 val = 0;
3667 u8 rc = 0;
ab6ad5a4 3668
ea4e040a 3669 if (vars->phy_flags & PHY_XGXS_FLAG) {
659bc5c4 3670 ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
ea4e040a
YR		 3671
3672 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
3673 /* Make sure that the soft reset is off (expect for the 8072:
3674 * due to the lock, it will be done inside the specific
3675 * handling)
3676 */
3677 if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
3678 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
3679 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN) &&
3680 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072) &&
3681 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073)) {
3682 /* Wait for soft reset to get cleared upto 1 sec */
3683 for (cnt = 0; cnt < 1000; cnt++) {
3684 bnx2x_cl45_read(bp, params->port,
3685 ext_phy_type,
3686 ext_phy_addr,
3687 MDIO_PMA_DEVAD,
3688 MDIO_PMA_REG_CTRL, &ctrl);
3689 if (!(ctrl & (1<<15)))
3690 break;
3691 msleep(1);
3692 }
3693 DP(NETIF_MSG_LINK, "control reg 0x%x (after %d ms)\n",
3694 ctrl, cnt);
3695 }
3696
3697 switch (ext_phy_type) {
3698 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
ea4e040a
YR		 3699 break;
3700
3701 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
3702 DP(NETIF_MSG_LINK, "XGXS 8705\n");
3703
3704 bnx2x_cl45_write(bp, params->port,
3705 ext_phy_type,
3706 ext_phy_addr,
3707 MDIO_PMA_DEVAD,
3708 MDIO_PMA_REG_MISC_CTRL,
3709 0x8288);
3710 bnx2x_cl45_write(bp, params->port,
3711 ext_phy_type,
3712 ext_phy_addr,
3713 MDIO_PMA_DEVAD,
3714 MDIO_PMA_REG_PHY_IDENTIFIER,
3715 0x7fbf);
3716 bnx2x_cl45_write(bp, params->port,
3717 ext_phy_type,
3718 ext_phy_addr,
3719 MDIO_PMA_DEVAD,
3720 MDIO_PMA_REG_CMU_PLL_BYPASS,
3721 0x0100);
3722 bnx2x_cl45_write(bp, params->port,
3723 ext_phy_type,
3724 ext_phy_addr,
3725 MDIO_WIS_DEVAD,
3726 MDIO_WIS_REG_LASI_CNTL, 0x1);
a35da8db 3727
3b313b61
EG		 3728 /* BCM8705 doesn't have microcode, hence the 0 */
3729 bnx2x_save_spirom_version(bp, params->port,
3730 params->shmem_base, 0);
ea4e040a
YR		 3731 break;
3732
3733 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
a35da8db
EG		 3734 /* Wait until fw is loaded */
3735 for (cnt = 0; cnt < 100; cnt++) {
3736 bnx2x_cl45_read(bp, params->port, ext_phy_type,
3737 ext_phy_addr, MDIO_PMA_DEVAD,
3738 MDIO_PMA_REG_ROM_VER1, &val);
3739 if (val)
3740 break;
3741 msleep(10);
3742 }
3743 DP(NETIF_MSG_LINK, "XGXS 8706 is initialized "
3744 "after %d ms\n", cnt);
c2c8b03e
EG		 3745 if ((params->feature_config_flags &
3746 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
3747 u8 i;
3748 u16 reg;
3749 for (i = 0; i < 4; i++) {
3750 reg = MDIO_XS_8706_REG_BANK_RX0 +
3751 i*(MDIO_XS_8706_REG_BANK_RX1 -
3752 MDIO_XS_8706_REG_BANK_RX0);
3753 bnx2x_cl45_read(bp, params->port,
3754 ext_phy_type,
3755 ext_phy_addr,
3756 MDIO_XS_DEVAD,
3757 reg, &val);
3758 /* Clear first 3 bits of the control */
3759 val &= ~0x7;
3760 /* Set control bits according to
3761 configuation */
3762 val |= (params->xgxs_config_rx[i] &
3763 0x7);
3764 DP(NETIF_MSG_LINK, "Setting RX"
3765 "Equalizer to BCM8706 reg 0x%x"
3766 " <-- val 0x%x\n", reg, val);
3767 bnx2x_cl45_write(bp, params->port,
3768 ext_phy_type,
3769 ext_phy_addr,
3770 MDIO_XS_DEVAD,
3771 reg, val);
3772 }
3773 }
ea4e040a
YR		 3774 /* Force speed */
3775 /* First enable LASI */
3776 bnx2x_cl45_write(bp, params->port,
3777 ext_phy_type,
3778 ext_phy_addr,
3779 MDIO_PMA_DEVAD,
3780 MDIO_PMA_REG_RX_ALARM_CTRL,
3781 0x0400);
3782 bnx2x_cl45_write(bp, params->port,
3783 ext_phy_type,
3784 ext_phy_addr,
3785 MDIO_PMA_DEVAD,
3786 MDIO_PMA_REG_LASI_CTRL, 0x0004);
3787
3788 if (params->req_line_speed == SPEED_10000) {
3789 DP(NETIF_MSG_LINK, "XGXS 8706 force 10Gbps\n");
3790
3791 bnx2x_cl45_write(bp, params->port,
3792 ext_phy_type,
3793 ext_phy_addr,
3794 MDIO_PMA_DEVAD,
3795 MDIO_PMA_REG_DIGITAL_CTRL,
3796 0x400);
3797 } else {
3798 /* Force 1Gbps using autoneg with 1G
3799 advertisment */
3800
3801 /* Allow CL37 through CL73 */
3802 DP(NETIF_MSG_LINK, "XGXS 8706 AutoNeg\n");
3803 bnx2x_cl45_write(bp, params->port,
3804 ext_phy_type,
3805 ext_phy_addr,
3806 MDIO_AN_DEVAD,
3807 MDIO_AN_REG_CL37_CL73,
3808 0x040c);
3809
3810 /* Enable Full-Duplex advertisment on CL37 */
3811 bnx2x_cl45_write(bp, params->port,
3812 ext_phy_type,
3813 ext_phy_addr,
3814 MDIO_AN_DEVAD,
8c99e7b0 3815 MDIO_AN_REG_CL37_FC_LP,
ea4e040a
YR		 3816 0x0020);
3817 /* Enable CL37 AN */
3818 bnx2x_cl45_write(bp, params->port,
3819 ext_phy_type,
3820 ext_phy_addr,
3821 MDIO_AN_DEVAD,
3822 MDIO_AN_REG_CL37_AN,
3823 0x1000);
3824 /* 1G support */
3825 bnx2x_cl45_write(bp, params->port,
3826 ext_phy_type,
3827 ext_phy_addr,
3828 MDIO_AN_DEVAD,
3829 MDIO_AN_REG_ADV, (1<<5));
3830
3831 /* Enable clause 73 AN */
3832 bnx2x_cl45_write(bp, params->port,
3833 ext_phy_type,
3834 ext_phy_addr,
3835 MDIO_AN_DEVAD,
3836 MDIO_AN_REG_CTRL,
3837 0x1200);
3838
3839 }
a35da8db
EG		 3840 bnx2x_save_bcm_spirom_ver(bp, params->port,
3841 ext_phy_type,
3842 ext_phy_addr,
3843 params->shmem_base);
ea4e040a 3844 break;
589abe3a
EG		 3845 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
3846 DP(NETIF_MSG_LINK, "Initializing BCM8726\n");
3847 bnx2x_bcm8726_external_rom_boot(params);
3848
3849 /* Need to call module detected on initialization since
3850 the module detection triggered by actual module
3851 insertion might occur before driver is loaded, and when
3852 driver is loaded, it reset all registers, including the
3853 transmitter */
3854 bnx2x_sfp_module_detection(params);
4d295db0
EG		 3855
3856 /* Set Flow control */
3857 bnx2x_ext_phy_set_pause(params, vars);
589abe3a
EG		 3858 if (params->req_line_speed == SPEED_1000) {
3859 DP(NETIF_MSG_LINK, "Setting 1G force\n");
3860 bnx2x_cl45_write(bp, params->port, ext_phy_type,
3861 ext_phy_addr, MDIO_PMA_DEVAD,
3862 MDIO_PMA_REG_CTRL, 0x40);
3863 bnx2x_cl45_write(bp, params->port, ext_phy_type,
3864 ext_phy_addr, MDIO_PMA_DEVAD,
3865 MDIO_PMA_REG_10G_CTRL2, 0xD);
3866 bnx2x_cl45_write(bp, params->port, ext_phy_type,
3867 ext_phy_addr, MDIO_PMA_DEVAD,
3868 MDIO_PMA_REG_LASI_CTRL, 0x5);
3869 bnx2x_cl45_write(bp, params->port, ext_phy_type,
3870 ext_phy_addr, MDIO_PMA_DEVAD,
3871 MDIO_PMA_REG_RX_ALARM_CTRL,
3872 0x400);
3873 } else if ((params->req_line_speed ==
3874 SPEED_AUTO_NEG) &&
3875 ((params->speed_cap_mask &
3876 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))) {
3877 DP(NETIF_MSG_LINK, "Setting 1G clause37 \n");
3878 bnx2x_cl45_write(bp, params->port, ext_phy_type,
3879 ext_phy_addr, MDIO_AN_DEVAD,
3880 MDIO_AN_REG_ADV, 0x20);
3881 bnx2x_cl45_write(bp, params->port, ext_phy_type,
3882 ext_phy_addr, MDIO_AN_DEVAD,
3883 MDIO_AN_REG_CL37_CL73, 0x040c);
3884 bnx2x_cl45_write(bp, params->port, ext_phy_type,
3885 ext_phy_addr, MDIO_AN_DEVAD,
3886 MDIO_AN_REG_CL37_FC_LD, 0x0020);
3887 bnx2x_cl45_write(bp, params->port, ext_phy_type,
3888 ext_phy_addr, MDIO_AN_DEVAD,
3889 MDIO_AN_REG_CL37_AN, 0x1000);
3890 bnx2x_cl45_write(bp, params->port, ext_phy_type,
3891 ext_phy_addr, MDIO_AN_DEVAD,
3892 MDIO_AN_REG_CTRL, 0x1200);
3893
3894 /* Enable RX-ALARM control to receive
3895 interrupt for 1G speed change */
3896 bnx2x_cl45_write(bp, params->port, ext_phy_type,
3897 ext_phy_addr, MDIO_PMA_DEVAD,
3898 MDIO_PMA_REG_LASI_CTRL, 0x4);
3899 bnx2x_cl45_write(bp, params->port, ext_phy_type,
3900 ext_phy_addr, MDIO_PMA_DEVAD,
3901 MDIO_PMA_REG_RX_ALARM_CTRL,
3902 0x400);
ea4e040a 3903
589abe3a
EG		 3904 } else { /* Default 10G. Set only LASI control */
3905 bnx2x_cl45_write(bp, params->port, ext_phy_type,
3906 ext_phy_addr, MDIO_PMA_DEVAD,
3907 MDIO_PMA_REG_LASI_CTRL, 1);
3908 }
c2c8b03e
EG		 3909
3910 /* Set TX PreEmphasis if needed */
3911 if ((params->feature_config_flags &
3912 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
3913 DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x,"
3914 "TX_CTRL2 0x%x\n",
3915 params->xgxs_config_tx[0],
3916 params->xgxs_config_tx[1]);
3917 bnx2x_cl45_write(bp, params->port,
3918 ext_phy_type,
3919 ext_phy_addr,
3920 MDIO_PMA_DEVAD,
3921 MDIO_PMA_REG_8726_TX_CTRL1,
3922 params->xgxs_config_tx[0]);
3923
3924 bnx2x_cl45_write(bp, params->port,
3925 ext_phy_type,
3926 ext_phy_addr,
3927 MDIO_PMA_DEVAD,
3928 MDIO_PMA_REG_8726_TX_CTRL2,
3929 params->xgxs_config_tx[1]);
3930 }
589abe3a 3931 break;
ea4e040a
YR		 3932 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
3933 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
3934 {
3935 u16 tmp1;
3936 u16 rx_alarm_ctrl_val;
3937 u16 lasi_ctrl_val;
3938 if (ext_phy_type ==
3939 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072) {
3940 rx_alarm_ctrl_val = 0x400;
3941 lasi_ctrl_val = 0x0004;
3942 } else {
ea4e040a 3943 rx_alarm_ctrl_val = (1<<2);
ea4e040a
YR		 3944 lasi_ctrl_val = 0x0004;
3945 }
3946
6bbca910
YR		 3947 /* enable LASI */
3948 bnx2x_cl45_write(bp, params->port,
3949 ext_phy_type,
3950 ext_phy_addr,
3951 MDIO_PMA_DEVAD,
3952 MDIO_PMA_REG_RX_ALARM_CTRL,
3953 rx_alarm_ctrl_val);
3954
3955 bnx2x_cl45_write(bp, params->port,
3956 ext_phy_type,
3957 ext_phy_addr,
3958 MDIO_PMA_DEVAD,
3959 MDIO_PMA_REG_LASI_CTRL,
3960 lasi_ctrl_val);
3961
3962 bnx2x_8073_set_pause_cl37(params, vars);
ea4e040a
YR		 3963
3964 if (ext_phy_type ==
ab6ad5a4 3965 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072)
ea4e040a 3966 bnx2x_bcm8072_external_rom_boot(params);
ab6ad5a4 3967 else
ea4e040a
YR		 3968 /* In case of 8073 with long xaui lines,
3969 don't set the 8073 xaui low power*/
3970 bnx2x_bcm8073_set_xaui_low_power_mode(params);
ea4e040a 3971
6bbca910
YR		 3972 bnx2x_cl45_read(bp, params->port,
3973 ext_phy_type,
3974 ext_phy_addr,
3975 MDIO_PMA_DEVAD,
052a38e0 3976 MDIO_PMA_REG_M8051_MSGOUT_REG,
6bbca910 3977 &tmp1);
ea4e040a
YR		 3978
3979 bnx2x_cl45_read(bp, params->port,
3980 ext_phy_type,
3981 ext_phy_addr,
3982 MDIO_PMA_DEVAD,
3983 MDIO_PMA_REG_RX_ALARM, &tmp1);
3984
3985 DP(NETIF_MSG_LINK, "Before rom RX_ALARM(port1):"
3986 "0x%x\n", tmp1);
3987
3988 /* If this is forced speed, set to KR or KX
3989 * (all other are not supported)
3990 */
6bbca910
YR		 3991 if (params->loopback_mode == LOOPBACK_EXT) {
3992 bnx2x_bcm807x_force_10G(params);
3993 DP(NETIF_MSG_LINK,
3994 "Forced speed 10G on 807X\n");
3995 break;
3996 } else {
3997 bnx2x_cl45_write(bp, params->port,
3998 ext_phy_type, ext_phy_addr,
3999 MDIO_PMA_DEVAD,
4000 MDIO_PMA_REG_BCM_CTRL,
4001 0x0002);
4002 }
4003 if (params->req_line_speed != SPEED_AUTO_NEG) {
4004 if (params->req_line_speed == SPEED_10000) {
4005 val = (1<<7);
ea4e040a
YR		 4006 } else if (params->req_line_speed ==
4007 SPEED_2500) {
4008 val = (1<<5);
4009 /* Note that 2.5G works only
4010 when used with 1G advertisment */
4011 } else
4012 val = (1<<5);
4013 } else {
4014
4015 val = 0;
4016 if (params->speed_cap_mask &
4017 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
4018 val |= (1<<7);
4019
6bbca910
YR		 4020 /* Note that 2.5G works only when
4021 used with 1G advertisment */
ea4e040a 4022 if (params->speed_cap_mask &
6bbca910
YR		 4023 (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G |
4024 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
ea4e040a 4025 val |= (1<<5);
6bbca910
YR		 4026 DP(NETIF_MSG_LINK,
4027 "807x autoneg val = 0x%x\n", val);
ea4e040a
YR		 4028 }
4029
4030 bnx2x_cl45_write(bp, params->port,
4031 ext_phy_type,
4032 ext_phy_addr,
4033 MDIO_AN_DEVAD,
4034 MDIO_AN_REG_ADV, val);
ea4e040a
YR		 4035 if (ext_phy_type ==
4036 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073) {
ea4e040a
YR		 4037 bnx2x_cl45_read(bp, params->port,
4038 ext_phy_type,
4039 ext_phy_addr,
4040 MDIO_AN_DEVAD,
052a38e0 4041 MDIO_AN_REG_8073_2_5G, &tmp1);
6bbca910
YR		 4042
4043 if (((params->speed_cap_mask &
4044 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) &&
4045 (params->req_line_speed ==
4046 SPEED_AUTO_NEG)) ||
4047 (params->req_line_speed ==
4048 SPEED_2500)) {
ea4e040a
YR		 4049 u16 phy_ver;
4050 /* Allow 2.5G for A1 and above */
4051 bnx2x_cl45_read(bp, params->port,
4052 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
4053 ext_phy_addr,
4054 MDIO_PMA_DEVAD,
052a38e0 4055 MDIO_PMA_REG_8073_CHIP_REV, &phy_ver);
6bbca910 4056 DP(NETIF_MSG_LINK, "Add 2.5G\n");
ea4e040a
YR		 4057 if (phy_ver > 0)
4058 tmp1 |= 1;
4059 else
4060 tmp1 &= 0xfffe;
6bbca910
YR		 4061 } else {
4062 DP(NETIF_MSG_LINK, "Disable 2.5G\n");
ea4e040a 4063 tmp1 &= 0xfffe;
6bbca910 4064 }
ea4e040a 4065
6bbca910
YR		 4066 bnx2x_cl45_write(bp, params->port,
4067 ext_phy_type,
4068 ext_phy_addr,
4069 MDIO_AN_DEVAD,
052a38e0 4070 MDIO_AN_REG_8073_2_5G, tmp1);
ea4e040a 4071 }
6bbca910
YR		 4072
4073 /* Add support for CL37 (passive mode) II */
4074
4075 bnx2x_cl45_read(bp, params->port,
ea4e040a
YR		 4076 ext_phy_type,
4077 ext_phy_addr,
4078 MDIO_AN_DEVAD,
6bbca910
YR		 4079 MDIO_AN_REG_CL37_FC_LD,
4080 &tmp1);
4081
ea4e040a
YR		 4082 bnx2x_cl45_write(bp, params->port,
4083 ext_phy_type,
4084 ext_phy_addr,
4085 MDIO_AN_DEVAD,
6bbca910
YR		 4086 MDIO_AN_REG_CL37_FC_LD, (tmp1 |
4087 ((params->req_duplex == DUPLEX_FULL) ?
4088 0x20 : 0x40)));
4089
ea4e040a
YR		 4090 /* Add support for CL37 (passive mode) III */
4091 bnx2x_cl45_write(bp, params->port,
4092 ext_phy_type,
4093 ext_phy_addr,
4094 MDIO_AN_DEVAD,
4095 MDIO_AN_REG_CL37_AN, 0x1000);
ea4e040a
YR		 4096
4097 if (ext_phy_type ==
4098 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073) {
6bbca910 4099 /* The SNR will improve about 2db by changing
ea4e040a
YR		 4100 BW and FEE main tap. Rest commands are executed
4101 after link is up*/
6bbca910 4102 /*Change FFE main cursor to 5 in EDC register*/
ea4e040a
YR		 4103 if (bnx2x_8073_is_snr_needed(params))
4104 bnx2x_cl45_write(bp, params->port,
4105 ext_phy_type,
4106 ext_phy_addr,
4107 MDIO_PMA_DEVAD,
4108 MDIO_PMA_REG_EDC_FFE_MAIN,
4109 0xFB0C);
4110
6bbca910
YR		 4111 /* Enable FEC (Forware Error Correction)
4112 Request in the AN */
4113 bnx2x_cl45_read(bp, params->port,
4114 ext_phy_type,
4115 ext_phy_addr,
4116 MDIO_AN_DEVAD,
4117 MDIO_AN_REG_ADV2, &tmp1);
ea4e040a 4118
6bbca910
YR		 4119 tmp1 |= (1<<15);
4120
4121 bnx2x_cl45_write(bp, params->port,
4122 ext_phy_type,
4123 ext_phy_addr,
4124 MDIO_AN_DEVAD,
4125 MDIO_AN_REG_ADV2, tmp1);
ea4e040a 4126
ea4e040a
YR		 4127 }
4128
4129 bnx2x_ext_phy_set_pause(params, vars);
4130
6bbca910
YR		 4131 /* Restart autoneg */
4132 msleep(500);
ea4e040a
YR		 4133 bnx2x_cl45_write(bp, params->port,
4134 ext_phy_type,
4135 ext_phy_addr,
4136 MDIO_AN_DEVAD,
4137 MDIO_AN_REG_CTRL, 0x1200);
4138 DP(NETIF_MSG_LINK, "807x Autoneg Restart: "
4139 "Advertise 1G=%x, 10G=%x\n",
4140 ((val & (1<<5)) > 0),
4141 ((val & (1<<7)) > 0));
4142 break;
4143 }
4d295db0
EG		 4144
4145 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
a35da8db 4146 {
4d295db0
EG		 4147 u16 tmp1;
4148 u16 rx_alarm_ctrl_val;
4149 u16 lasi_ctrl_val;
ea4e040a 4150
4d295db0
EG		 4151 /* Enable PMD link, MOD_ABS_FLT, and 1G link alarm */
4152
4153 u16 mod_abs;
4154 rx_alarm_ctrl_val = (1<<2) | (1<<5) ;
4155 lasi_ctrl_val = 0x0004;
4156
4157 DP(NETIF_MSG_LINK, "Initializing BCM8727\n");
4158 /* enable LASI */
ea4e040a
YR		 4159 bnx2x_cl45_write(bp, params->port,
4160 ext_phy_type,
4161 ext_phy_addr,
4162 MDIO_PMA_DEVAD,
4d295db0
EG		 4163 MDIO_PMA_REG_RX_ALARM_CTRL,
4164 rx_alarm_ctrl_val);
4165
ea4e040a
YR		 4166 bnx2x_cl45_write(bp, params->port,
4167 ext_phy_type,
4168 ext_phy_addr,
4169 MDIO_PMA_DEVAD,
4d295db0
EG		 4170 MDIO_PMA_REG_LASI_CTRL,
4171 lasi_ctrl_val);
ea4e040a 4172
4d295db0
EG		 4173 /* Initially configure MOD_ABS to interrupt when
4174 module is presence( bit 8) */
ea4e040a
YR		 4175 bnx2x_cl45_read(bp, params->port,
4176 ext_phy_type,
4177 ext_phy_addr,
4d295db0
EG		 4178 MDIO_PMA_DEVAD,
4179 MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
4180 /* Set EDC off by setting OPTXLOS signal input to low
4181 (bit 9).
4182 When the EDC is off it locks onto a reference clock and
4183 avoids becoming 'lost'.*/
4184 mod_abs &= ~((1<<8) | (1<<9));
ea4e040a
YR		 4185 bnx2x_cl45_write(bp, params->port,
4186 ext_phy_type,
4187 ext_phy_addr,
4d295db0
EG		 4188 MDIO_PMA_DEVAD,
4189 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
28577185 4190
4d295db0
EG		 4191 /* Make MOD_ABS give interrupt on change */
4192 bnx2x_cl45_read(bp, params->port,
4193 ext_phy_type,
4194 ext_phy_addr,
4195 MDIO_PMA_DEVAD,
4196 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
4197 &val);
4198 val |= (1<<12);
4199 bnx2x_cl45_write(bp, params->port,
4200 ext_phy_type,
4201 ext_phy_addr,
4202 MDIO_PMA_DEVAD,
4203 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
4204 val);
4205
4206 /* Set 8727 GPIOs to input to allow reading from the
4207 8727 GPIO0 status which reflect SFP+ module
4208 over-current */
4209
4210 bnx2x_cl45_read(bp, params->port,
4211 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
4212 ext_phy_addr,
4213 MDIO_PMA_DEVAD,
4214 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
4215 &val);
4216 val &= 0xff8f; /* Reset bits 4-6 */
4217 bnx2x_cl45_write(bp, params->port,
4218 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
4219 ext_phy_addr,
4220 MDIO_PMA_DEVAD,
4221 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
4222 val);
4223
4224 bnx2x_8727_power_module(bp, params, ext_phy_addr, 1);
4225 bnx2x_bcm8073_set_xaui_low_power_mode(params);
4226
4227 bnx2x_cl45_read(bp, params->port,
4228 ext_phy_type,
4229 ext_phy_addr,
4230 MDIO_PMA_DEVAD,
4231 MDIO_PMA_REG_M8051_MSGOUT_REG,
4232 &tmp1);
4233
4234 bnx2x_cl45_read(bp, params->port,
4235 ext_phy_type,
4236 ext_phy_addr,
4237 MDIO_PMA_DEVAD,
4238 MDIO_PMA_REG_RX_ALARM, &tmp1);
4239
4240 /* Set option 1G speed */
4241 if (params->req_line_speed == SPEED_1000) {
4242
4243 DP(NETIF_MSG_LINK, "Setting 1G force\n");
4244 bnx2x_cl45_write(bp, params->port,
4245 ext_phy_type,
4246 ext_phy_addr,
4247 MDIO_PMA_DEVAD,
4248 MDIO_PMA_REG_CTRL, 0x40);
4249 bnx2x_cl45_write(bp, params->port,
4250 ext_phy_type,
4251 ext_phy_addr,
4252 MDIO_PMA_DEVAD,
4253 MDIO_PMA_REG_10G_CTRL2, 0xD);
4254 bnx2x_cl45_read(bp, params->port,
4255 ext_phy_type,
4256 ext_phy_addr,
4257 MDIO_PMA_DEVAD,
4258 MDIO_PMA_REG_10G_CTRL2, &tmp1);
4259 DP(NETIF_MSG_LINK, "1.7 = 0x%x \n", tmp1);
4260
4261 } else if ((params->req_line_speed ==
4262 SPEED_AUTO_NEG) &&
4263 ((params->speed_cap_mask &
4264 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))) {
4265
4266 DP(NETIF_MSG_LINK, "Setting 1G clause37 \n");
4267 bnx2x_cl45_write(bp, params->port, ext_phy_type,
4268 ext_phy_addr, MDIO_AN_DEVAD,
4269 MDIO_PMA_REG_8727_MISC_CTRL, 0);
4270 bnx2x_cl45_write(bp, params->port, ext_phy_type,
4271 ext_phy_addr, MDIO_AN_DEVAD,
4272 MDIO_AN_REG_CL37_AN, 0x1300);
4273 } else {
4274 /* Since the 8727 has only single reset pin,
4275 need to set the 10G registers although it is
4276 default */
4277 bnx2x_cl45_write(bp, params->port, ext_phy_type,
4278 ext_phy_addr, MDIO_AN_DEVAD,
4279 MDIO_AN_REG_CTRL, 0x0020);
4280 bnx2x_cl45_write(bp, params->port, ext_phy_type,
4281 ext_phy_addr, MDIO_AN_DEVAD,
4282 0x7, 0x0100);
4283 bnx2x_cl45_write(bp, params->port, ext_phy_type,
4284 ext_phy_addr, MDIO_PMA_DEVAD,
4285 MDIO_PMA_REG_CTRL, 0x2040);
4286 bnx2x_cl45_write(bp, params->port, ext_phy_type,
4287 ext_phy_addr, MDIO_PMA_DEVAD,
4288 MDIO_PMA_REG_10G_CTRL2, 0x0008);
4289 }
4290
4291 /* Set 2-wire transfer rate to 400Khz since 100Khz
4292 is not operational */
4293 bnx2x_cl45_write(bp, params->port,
4294 ext_phy_type,
4295 ext_phy_addr,
4296 MDIO_PMA_DEVAD,
4297 MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR,
4298 0xa101);
4299
4300 /* Set TX PreEmphasis if needed */
4301 if ((params->feature_config_flags &
4302 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
4303 DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x,"
4304 "TX_CTRL2 0x%x\n",
4305 params->xgxs_config_tx[0],
4306 params->xgxs_config_tx[1]);
4307 bnx2x_cl45_write(bp, params->port,
4308 ext_phy_type,
4309 ext_phy_addr,
4310 MDIO_PMA_DEVAD,
4311 MDIO_PMA_REG_8727_TX_CTRL1,
4312 params->xgxs_config_tx[0]);
4313
4314 bnx2x_cl45_write(bp, params->port,
4315 ext_phy_type,
4316 ext_phy_addr,
4317 MDIO_PMA_DEVAD,
4318 MDIO_PMA_REG_8727_TX_CTRL2,
4319 params->xgxs_config_tx[1]);
4320 }
4321
4322 break;
4323 }
4324
4325 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
4326 {
4327 u16 fw_ver1, fw_ver2;
4328 DP(NETIF_MSG_LINK,
4329 "Setting the SFX7101 LASI indication\n");
4330
4331 bnx2x_cl45_write(bp, params->port,
4332 ext_phy_type,
4333 ext_phy_addr,
4334 MDIO_PMA_DEVAD,
4335 MDIO_PMA_REG_LASI_CTRL, 0x1);
4336 DP(NETIF_MSG_LINK,
4337 "Setting the SFX7101 LED to blink on traffic\n");
4338 bnx2x_cl45_write(bp, params->port,
4339 ext_phy_type,
4340 ext_phy_addr,
4341 MDIO_PMA_DEVAD,
4342 MDIO_PMA_REG_7107_LED_CNTL, (1<<3));
4343
4344 bnx2x_ext_phy_set_pause(params, vars);
4345 /* Restart autoneg */
4346 bnx2x_cl45_read(bp, params->port,
4347 ext_phy_type,
4348 ext_phy_addr,
4349 MDIO_AN_DEVAD,
4350 MDIO_AN_REG_CTRL, &val);
4351 val |= 0x200;
4352 bnx2x_cl45_write(bp, params->port,
4353 ext_phy_type,
4354 ext_phy_addr,
4355 MDIO_AN_DEVAD,
4356 MDIO_AN_REG_CTRL, val);
4357
4358 /* Save spirom version */
4359 bnx2x_cl45_read(bp, params->port, ext_phy_type,
4360 ext_phy_addr, MDIO_PMA_DEVAD,
4361 MDIO_PMA_REG_7101_VER1, &fw_ver1);
a35da8db
EG		 4362
4363 bnx2x_cl45_read(bp, params->port, ext_phy_type,
4364 ext_phy_addr, MDIO_PMA_DEVAD,
4365 MDIO_PMA_REG_7101_VER2, &fw_ver2);
4366
4367 bnx2x_save_spirom_version(params->bp, params->port,
4368 params->shmem_base,
4369 (u32)(fw_ver1<<16 | fw_ver2));
28577185 4370 break;
a35da8db 4371 }
28577185 4372 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
2f904460
EG		 4373 /* This phy uses the NIG latch mechanism since link
4374 indication arrives through its LED4 and not via
4375 its LASI signal, so we get steady signal
4376 instead of clear on read */
4377 bnx2x_bits_en(bp, NIG_REG_LATCH_BC_0 + params->port*4,
4378 1 << NIG_LATCH_BC_ENABLE_MI_INT);
4379
4380 bnx2x_8481_set_led4(params, ext_phy_type, ext_phy_addr);
4381 if (params->req_line_speed == SPEED_AUTO_NEG) {
4382
4383 u16 autoneg_val, an_1000_val, an_10_100_val;
4384 /* set 1000 speed advertisement */
4385 bnx2x_cl45_read(bp, params->port,
4386 ext_phy_type,
4387 ext_phy_addr,
4388 MDIO_AN_DEVAD,
4389 MDIO_AN_REG_8481_1000T_CTRL,
4390 &an_1000_val);
28577185 4391
2f904460
EG		 4392 if (params->speed_cap_mask &
4393 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) {
4394 an_1000_val |= (1<<8);
4395 if (params->req_duplex == DUPLEX_FULL)
4396 an_1000_val |= (1<<9);
4397 DP(NETIF_MSG_LINK, "Advertising 1G\n");
4398 } else
4399 an_1000_val &= ~((1<<8) | (1<<9));
28577185 4400
2f904460
EG		 4401 bnx2x_cl45_write(bp, params->port,
4402 ext_phy_type,
4403 ext_phy_addr,
4404 MDIO_AN_DEVAD,
4405 MDIO_AN_REG_8481_1000T_CTRL,
4406 an_1000_val);
4407
4408 /* set 100 speed advertisement */
4409 bnx2x_cl45_read(bp, params->port,
4410 ext_phy_type,
4411 ext_phy_addr,
4412 MDIO_AN_DEVAD,
4413 MDIO_AN_REG_8481_LEGACY_AN_ADV,
4414 &an_10_100_val);
4415
4416 if (params->speed_cap_mask &
4417 (PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL |
4418 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)) {
4419 an_10_100_val |= (1<<7);
4420 if (params->req_duplex == DUPLEX_FULL)
4421 an_10_100_val |= (1<<8);
4422 DP(NETIF_MSG_LINK,
4423 "Advertising 100M\n");
4424 } else
4425 an_10_100_val &= ~((1<<7) | (1<<8));
4426
4427 /* set 10 speed advertisement */
4428 if (params->speed_cap_mask &
4429 (PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL |
4430 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) {
4431 an_10_100_val |= (1<<5);
4432 if (params->req_duplex == DUPLEX_FULL)
4433 an_10_100_val |= (1<<6);
4434 DP(NETIF_MSG_LINK, "Advertising 10M\n");
4435 }
4436 else
4437 an_10_100_val &= ~((1<<5) | (1<<6));
4438
4439 bnx2x_cl45_write(bp, params->port,
4440 ext_phy_type,
4441 ext_phy_addr,
4442 MDIO_AN_DEVAD,
4443 MDIO_AN_REG_8481_LEGACY_AN_ADV,
4444 an_10_100_val);
4445
4446 bnx2x_cl45_read(bp, params->port,
4447 ext_phy_type,
4448 ext_phy_addr,
4449 MDIO_AN_DEVAD,
4450 MDIO_AN_REG_8481_LEGACY_MII_CTRL,
4451 &autoneg_val);
4452
4453 /* Disable forced speed */
4454 autoneg_val &= ~(1<<6|1<<13);
4455
4456 /* Enable autoneg and restart autoneg
4457 for legacy speeds */
4458 autoneg_val |= (1<<9|1<<12);
4459
4460 if (params->req_duplex == DUPLEX_FULL)
4461 autoneg_val |= (1<<8);
4462 else
4463 autoneg_val &= ~(1<<8);
4464
4465 bnx2x_cl45_write(bp, params->port,
4466 ext_phy_type,
4467 ext_phy_addr,
4468 MDIO_AN_DEVAD,
4469 MDIO_AN_REG_8481_LEGACY_MII_CTRL,
4470 autoneg_val);
4471
4472 if (params->speed_cap_mask &
4473 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) {
4474 DP(NETIF_MSG_LINK, "Advertising 10G\n");
4475 /* Restart autoneg for 10G*/
28577185
EG		 4476 bnx2x_cl45_read(bp, params->port,
4477 ext_phy_type,
4478 ext_phy_addr,
4479 MDIO_AN_DEVAD,
4480 MDIO_AN_REG_CTRL, &val);
4481 val |= 0x200;
4482 bnx2x_cl45_write(bp, params->port,
4483 ext_phy_type,
4484 ext_phy_addr,
4485 MDIO_AN_DEVAD,
4486 MDIO_AN_REG_CTRL, val);
2f904460
EG		 4487 }
4488 } else {
4489 /* Force speed */
4490 u16 autoneg_ctrl, pma_ctrl;
4491 bnx2x_cl45_read(bp, params->port,
4492 ext_phy_type,
4493 ext_phy_addr,
4494 MDIO_AN_DEVAD,
4495 MDIO_AN_REG_8481_LEGACY_MII_CTRL,
4496 &autoneg_ctrl);
4497
4498 /* Disable autoneg */
4499 autoneg_ctrl &= ~(1<<12);
4500
4501 /* Set 1000 force */
4502 switch (params->req_line_speed) {
4503 case SPEED_10000:
4504 DP(NETIF_MSG_LINK,
4505 "Unable to set 10G force !\n");
4506 break;
4507 case SPEED_1000:
4508 bnx2x_cl45_read(bp, params->port,
4509 ext_phy_type,
4510 ext_phy_addr,
4511 MDIO_PMA_DEVAD,
4512 MDIO_PMA_REG_CTRL,
4513 &pma_ctrl);
4514 autoneg_ctrl &= ~(1<<13);
4515 autoneg_ctrl |= (1<<6);
4516 pma_ctrl &= ~(1<<13);
4517 pma_ctrl |= (1<<6);
4518 DP(NETIF_MSG_LINK,
4519 "Setting 1000M force\n");
4520 bnx2x_cl45_write(bp, params->port,
4521 ext_phy_type,
4522 ext_phy_addr,
4523 MDIO_PMA_DEVAD,
4524 MDIO_PMA_REG_CTRL,
4525 pma_ctrl);
4526 break;
4527 case SPEED_100:
4528 autoneg_ctrl |= (1<<13);
4529 autoneg_ctrl &= ~(1<<6);
4530 DP(NETIF_MSG_LINK,
4531 "Setting 100M force\n");
4532 break;
4533 case SPEED_10:
4534 autoneg_ctrl &= ~(1<<13);
4535 autoneg_ctrl &= ~(1<<6);
4536 DP(NETIF_MSG_LINK,
4537 "Setting 10M force\n");
4538 break;
4539 }
4540
4541 /* Duplex mode */
4542 if (params->req_duplex == DUPLEX_FULL) {
4543 autoneg_ctrl |= (1<<8);
4544 DP(NETIF_MSG_LINK,
4545 "Setting full duplex\n");
4546 } else
4547 autoneg_ctrl &= ~(1<<8);
4548
4549 /* Update autoneg ctrl and pma ctrl */
4550 bnx2x_cl45_write(bp, params->port,
4551 ext_phy_type,
4552 ext_phy_addr,
4553 MDIO_AN_DEVAD,
4554 MDIO_AN_REG_8481_LEGACY_MII_CTRL,
4555 autoneg_ctrl);
4556 }
28577185 4557
b1607af5
EG		 4558 /* Save spirom version */
4559 bnx2x_save_8481_spirom_version(bp, params->port,
4560 ext_phy_addr,
4561 params->shmem_base);
ea4e040a
YR		 4562 break;
4563 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
4564 DP(NETIF_MSG_LINK,
4565 "XGXS PHY Failure detected 0x%x\n",
4566 params->ext_phy_config);
4567 rc = -EINVAL;
4568 break;
4569 default:
4570 DP(NETIF_MSG_LINK, "BAD XGXS ext_phy_config 0x%x\n",
4571 params->ext_phy_config);
4572 rc = -EINVAL;
4573 break;
4574 }
4575
4576 } else { /* SerDes */
57963ed9 4577
ea4e040a
YR		 4578 ext_phy_type = SERDES_EXT_PHY_TYPE(params->ext_phy_config);
4579 switch (ext_phy_type) {
4580 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT:
4581 DP(NETIF_MSG_LINK, "SerDes Direct\n");
4582 break;
4583
4584 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482:
4585 DP(NETIF_MSG_LINK, "SerDes 5482\n");
4586 break;
4587
4588 default:
4589 DP(NETIF_MSG_LINK, "BAD SerDes ext_phy_config 0x%x\n",
4590 params->ext_phy_config);
4591 break;
4592 }
4593 }
4594 return rc;
4595}
4596
4d295db0
EG		 4597static void bnx2x_8727_handle_mod_abs(struct link_params *params)
4598{
4599 struct bnx2x *bp = params->bp;
4600 u16 mod_abs, rx_alarm_status;
659bc5c4 4601 u8 ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
4d295db0
EG		 4602 u32 val = REG_RD(bp, params->shmem_base +
4603 offsetof(struct shmem_region, dev_info.
4604 port_feature_config[params->port].
4605 config));
4606 bnx2x_cl45_read(bp, params->port,
4607 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
4608 ext_phy_addr,
4609 MDIO_PMA_DEVAD,
4610 MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
4611 if (mod_abs & (1<<8)) {
4612
4613 /* Module is absent */
4614 DP(NETIF_MSG_LINK, "MOD_ABS indication "
4615 "show module is absent\n");
4616
4617 /* 1. Set mod_abs to detect next module
4618 presence event
4619 2. Set EDC off by setting OPTXLOS signal input to low
4620 (bit 9).
4621 When the EDC is off it locks onto a reference clock and
4622 avoids becoming 'lost'.*/
4623 mod_abs &= ~((1<<8)|(1<<9));
4624 bnx2x_cl45_write(bp, params->port,
4625 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
4626 ext_phy_addr,
4627 MDIO_PMA_DEVAD,
4628 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
4629
4630 /* Clear RX alarm since it stays up as long as
4631 the mod_abs wasn't changed */
4632 bnx2x_cl45_read(bp, params->port,
4633 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
4634 ext_phy_addr,
4635 MDIO_PMA_DEVAD,
4636 MDIO_PMA_REG_RX_ALARM, &rx_alarm_status);
4637
4638 } else {
4639 /* Module is present */
4640 DP(NETIF_MSG_LINK, "MOD_ABS indication "
4641 "show module is present\n");
4642 /* First thing, disable transmitter,
4643 and if the module is ok, the
4644 module_detection will enable it*/
4645
4646 /* 1. Set mod_abs to detect next module
4647 absent event ( bit 8)
4648 2. Restore the default polarity of the OPRXLOS signal and
4649 this signal will then correctly indicate the presence or
4650 absence of the Rx signal. (bit 9) */
4651 mod_abs |= ((1<<8)|(1<<9));
4652 bnx2x_cl45_write(bp, params->port,
4653 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
4654 ext_phy_addr,
4655 MDIO_PMA_DEVAD,
4656 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
4657
4658 /* Clear RX alarm since it stays up as long as
4659 the mod_abs wasn't changed. This is need to be done
4660 before calling the module detection, otherwise it will clear
4661 the link update alarm */
4662 bnx2x_cl45_read(bp, params->port,
4663 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
4664 ext_phy_addr,
4665 MDIO_PMA_DEVAD,
4666 MDIO_PMA_REG_RX_ALARM, &rx_alarm_status);
4667
4668
4669 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
4670 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
4671 bnx2x_sfp_set_transmitter(bp, params->port,
4672 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
4673 ext_phy_addr, 0);
4674
4675 if (bnx2x_wait_for_sfp_module_initialized(params)
4676 == 0)
4677 bnx2x_sfp_module_detection(params);
4678 else
4679 DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
4680 }
4681
4682 DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n",
4683 rx_alarm_status);
4684 /* No need to check link status in case of
4685 module plugged in/out */
4686}
4687
ea4e040a
YR		 4688
4689static u8 bnx2x_ext_phy_is_link_up(struct link_params *params,
2f904460
EG		 4690 struct link_vars *vars,
4691 u8 is_mi_int)
ea4e040a
YR		 4692{
4693 struct bnx2x *bp = params->bp;
4694 u32 ext_phy_type;
4695 u8 ext_phy_addr;
4696 u16 val1 = 0, val2;
4697 u16 rx_sd, pcs_status;
4698 u8 ext_phy_link_up = 0;
4699 u8 port = params->port;
ab6ad5a4 4700
ea4e040a 4701 if (vars->phy_flags & PHY_XGXS_FLAG) {
659bc5c4 4702 ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
ea4e040a
YR		 4703 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
4704 switch (ext_phy_type) {
4705 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
4706 DP(NETIF_MSG_LINK, "XGXS Direct\n");
4707 ext_phy_link_up = 1;
4708 break;
4709
4710 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
4711 DP(NETIF_MSG_LINK, "XGXS 8705\n");
4712 bnx2x_cl45_read(bp, params->port, ext_phy_type,
4713 ext_phy_addr,
4714 MDIO_WIS_DEVAD,
4715 MDIO_WIS_REG_LASI_STATUS, &val1);
4716 DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
4717
4718 bnx2x_cl45_read(bp, params->port, ext_phy_type,
4719 ext_phy_addr,
4720 MDIO_WIS_DEVAD,
4721 MDIO_WIS_REG_LASI_STATUS, &val1);
4722 DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
4723
4724 bnx2x_cl45_read(bp, params->port, ext_phy_type,
4725 ext_phy_addr,
4726 MDIO_PMA_DEVAD,
4727 MDIO_PMA_REG_RX_SD, &rx_sd);
4d295db0
EG		 4728
4729 bnx2x_cl45_read(bp, params->port, ext_phy_type,
4730 ext_phy_addr,
4731 1,
4732 0xc809, &val1);
4733 bnx2x_cl45_read(bp, params->port, ext_phy_type,
4734 ext_phy_addr,
4735 1,
4736 0xc809, &val1);
4737
4738 DP(NETIF_MSG_LINK, "8705 1.c809 val=0x%x\n", val1);
4739 ext_phy_link_up = ((rx_sd & 0x1) && (val1 & (1<<9))
4740 && ((val1 & (1<<8)) == 0));
8c99e7b0
YR		 4741 if (ext_phy_link_up)
4742 vars->line_speed = SPEED_10000;
ea4e040a
YR		 4743 break;
4744
4745 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
589abe3a
EG		 4746 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
4747 DP(NETIF_MSG_LINK, "XGXS 8706/8726\n");
4748 /* Clear RX Alarm*/
ea4e040a
YR		 4749 bnx2x_cl45_read(bp, params->port, ext_phy_type,
4750 ext_phy_addr,
589abe3a
EG		 4751 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM,
4752 &val2);
4753 /* clear LASI indication*/
ea4e040a
YR		 4754 bnx2x_cl45_read(bp, params->port, ext_phy_type,
4755 ext_phy_addr,
589abe3a
EG		 4756 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS,
4757 &val1);
4758 bnx2x_cl45_read(bp, params->port, ext_phy_type,
4759 ext_phy_addr,
4760 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS,
4761 &val2);
4762 DP(NETIF_MSG_LINK, "8706/8726 LASI status 0x%x-->"
4763 "0x%x\n", val1, val2);
ea4e040a
YR		 4764
4765 bnx2x_cl45_read(bp, params->port, ext_phy_type,
4766 ext_phy_addr,
589abe3a
EG		 4767 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD,
4768 &rx_sd);
ea4e040a
YR		 4769 bnx2x_cl45_read(bp, params->port, ext_phy_type,
4770 ext_phy_addr,
589abe3a
EG		 4771 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS,
4772 &pcs_status);
ea4e040a
YR		 4773 bnx2x_cl45_read(bp, params->port, ext_phy_type,
4774 ext_phy_addr,
589abe3a
EG		 4775 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS,
4776 &val2);
ea4e040a
YR		 4777 bnx2x_cl45_read(bp, params->port, ext_phy_type,
4778 ext_phy_addr,
589abe3a
EG		 4779 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS,
4780 &val2);
ea4e040a 4781
589abe3a 4782 DP(NETIF_MSG_LINK, "8706/8726 rx_sd 0x%x"
ea4e040a
YR		 4783 " pcs_status 0x%x 1Gbps link_status 0x%x\n",
4784 rx_sd, pcs_status, val2);
4785 /* link is up if both bit 0 of pmd_rx_sd and
4786 * bit 0 of pcs_status are set, or if the autoneg bit
4787 1 is set
4788 */
4789 ext_phy_link_up = ((rx_sd & pcs_status & 0x1) ||
4790 (val2 & (1<<1)));
57963ed9 4791 if (ext_phy_link_up) {
589abe3a
EG		 4792 if (ext_phy_type ==
4793 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) {
4794 /* If transmitter is disabled,
4795 ignore false link up indication */
4796 bnx2x_cl45_read(bp, params->port,
4797 ext_phy_type,
4798 ext_phy_addr,
4799 MDIO_PMA_DEVAD,
4800 MDIO_PMA_REG_PHY_IDENTIFIER,
4801 &val1);
4802 if (val1 & (1<<15)) {
4803 DP(NETIF_MSG_LINK, "Tx is "
4804 "disabled\n");
4805 ext_phy_link_up = 0;
4806 break;
4807 }
4808 }
57963ed9
YR		 4809 if (val2 & (1<<1))
4810 vars->line_speed = SPEED_1000;
4811 else
4812 vars->line_speed = SPEED_10000;
4813 }
4d295db0
EG		 4814 break;
4815
4816 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
4817 {
4818 u16 link_status = 0;
4819 u16 rx_alarm_status;
4820 /* Check the LASI */
4821 bnx2x_cl45_read(bp, params->port,
4822 ext_phy_type,
4823 ext_phy_addr,
4824 MDIO_PMA_DEVAD,
4825 MDIO_PMA_REG_RX_ALARM, &rx_alarm_status);
4826
4827 DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n",
4828 rx_alarm_status);
4829
4830 bnx2x_cl45_read(bp, params->port,
4831 ext_phy_type,
4832 ext_phy_addr,
4833 MDIO_PMA_DEVAD,
4834 MDIO_PMA_REG_LASI_STATUS, &val1);
4835
4836 DP(NETIF_MSG_LINK,
4837 "8727 LASI status 0x%x\n",
4838 val1);
4839
4840 /* Clear MSG-OUT */
4841 bnx2x_cl45_read(bp, params->port,
4842 ext_phy_type,
4843 ext_phy_addr,
4844 MDIO_PMA_DEVAD,
4845 MDIO_PMA_REG_M8051_MSGOUT_REG,
4846 &val1);
4847
4848 /*
4849 * If a module is present and there is need to check
4850 * for over current
4851 */
4852 if (!(params->feature_config_flags &
4853 FEATURE_CONFIG_BCM8727_NOC) &&
4854 !(rx_alarm_status & (1<<5))) {
4855 /* Check over-current using 8727 GPIO0 input*/
4856 bnx2x_cl45_read(bp, params->port,
4857 ext_phy_type,
4858 ext_phy_addr,
4859 MDIO_PMA_DEVAD,
4860 MDIO_PMA_REG_8727_GPIO_CTRL,
4861 &val1);
4862
4863 if ((val1 & (1<<8)) == 0) {
4864 DP(NETIF_MSG_LINK, "8727 Power fault"
ab6ad5a4
EG		 4865 " has been detected on "
4866 "port %d\n",
4867 params->port);
4d295db0
EG		 4868 printk(KERN_ERR PFX "Error: Power"
4869 " fault on %s Port %d has"
4870 " been detected and the"
4871 " power to that SFP+ module"
4872 " has been removed to prevent"
4873 " failure of the card. Please"
4874 " remove the SFP+ module and"
4875 " restart the system to clear"
4876 " this error.\n"
4877 , bp->dev->name, params->port);
4878 /*
4879 * Disable all RX_ALARMs except for
4880 * mod_abs
4881 */
4882 bnx2x_cl45_write(bp, params->port,
4883 ext_phy_type,
4884 ext_phy_addr,
4885 MDIO_PMA_DEVAD,
4886 MDIO_PMA_REG_RX_ALARM_CTRL,
4887 (1<<5));
4888
4889 bnx2x_cl45_read(bp, params->port,
4890 ext_phy_type,
4891 ext_phy_addr,
4892 MDIO_PMA_DEVAD,
4893 MDIO_PMA_REG_PHY_IDENTIFIER,
4894 &val1);
4895 /* Wait for module_absent_event */
4896 val1 |= (1<<8);
4897 bnx2x_cl45_write(bp, params->port,
4898 ext_phy_type,
4899 ext_phy_addr,
4900 MDIO_PMA_DEVAD,
4901 MDIO_PMA_REG_PHY_IDENTIFIER,
4902 val1);
4903 /* Clear RX alarm */
4904 bnx2x_cl45_read(bp, params->port,
4905 ext_phy_type,
4906 ext_phy_addr,
4907 MDIO_PMA_DEVAD,
4908 MDIO_PMA_REG_RX_ALARM,
4909 &rx_alarm_status);
4910 break;
4911 }
4912 } /* Over current check */
4913
4914 /* When module absent bit is set, check module */
4915 if (rx_alarm_status & (1<<5)) {
4916 bnx2x_8727_handle_mod_abs(params);
4917 /* Enable all mod_abs and link detection bits */
4918 bnx2x_cl45_write(bp, params->port,
4919 ext_phy_type,
4920 ext_phy_addr,
4921 MDIO_PMA_DEVAD,
4922 MDIO_PMA_REG_RX_ALARM_CTRL,
4923 ((1<<5) | (1<<2)));
4924 }
4925
4926 /* If transmitter is disabled,
4927 ignore false link up indication */
4928 bnx2x_cl45_read(bp, params->port,
4929 ext_phy_type,
4930 ext_phy_addr,
4931 MDIO_PMA_DEVAD,
4932 MDIO_PMA_REG_PHY_IDENTIFIER,
4933 &val1);
4934 if (val1 & (1<<15)) {
4935 DP(NETIF_MSG_LINK, "Tx is disabled\n");
4936 ext_phy_link_up = 0;
4937 break;
4938 }
4939
4940 bnx2x_cl45_read(bp, params->port,
4941 ext_phy_type,
4942 ext_phy_addr,
4943 MDIO_PMA_DEVAD,
4944 MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
4945 &link_status);
57963ed9 4946
4d295db0
EG		 4947 /* Bits 0..2 --> speed detected,
4948 bits 13..15--> link is down */
4949 if ((link_status & (1<<2)) &&
4950 (!(link_status & (1<<15)))) {
4951 ext_phy_link_up = 1;
4952 vars->line_speed = SPEED_10000;
4953 } else if ((link_status & (1<<0)) &&
4954 (!(link_status & (1<<13)))) {
4955 ext_phy_link_up = 1;
4956 vars->line_speed = SPEED_1000;
4957 DP(NETIF_MSG_LINK,
4958 "port %x: External link"
4959 " up in 1G\n", params->port);
4960 } else {
4961 ext_phy_link_up = 0;
4962 DP(NETIF_MSG_LINK,
4963 "port %x: External link"
4964 " is down\n", params->port);
4965 }
ea4e040a 4966 break;
4d295db0
EG		 4967 }
4968
ea4e040a
YR		 4969 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
4970 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
4971 {
6bbca910
YR		 4972 u16 link_status = 0;
4973 u16 an1000_status = 0;
ab6ad5a4 4974
ea4e040a
YR		 4975 if (ext_phy_type ==
4976 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072) {
4977 bnx2x_cl45_read(bp, params->port,
4978 ext_phy_type,
4979 ext_phy_addr,
4980 MDIO_PCS_DEVAD,
4981 MDIO_PCS_REG_LASI_STATUS, &val1);
4982 bnx2x_cl45_read(bp, params->port,
4983 ext_phy_type,
4984 ext_phy_addr,
4985 MDIO_PCS_DEVAD,
4986 MDIO_PCS_REG_LASI_STATUS, &val2);
4987 DP(NETIF_MSG_LINK,
4988 "870x LASI status 0x%x->0x%x\n",
4989 val1, val2);
ea4e040a
YR		 4990 } else {
4991 /* In 8073, port1 is directed through emac0 and
4992 * port0 is directed through emac1
4993 */
4994 bnx2x_cl45_read(bp, params->port,
4995 ext_phy_type,
4996 ext_phy_addr,
4997 MDIO_PMA_DEVAD,
4998 MDIO_PMA_REG_LASI_STATUS, &val1);
4999
ea4e040a 5000 DP(NETIF_MSG_LINK,
6bbca910
YR		 5001 "8703 LASI status 0x%x\n",
5002 val1);
ea4e040a
YR		 5003 }
5004
5005 /* clear the interrupt LASI status register */
5006 bnx2x_cl45_read(bp, params->port,
5007 ext_phy_type,
5008 ext_phy_addr,
5009 MDIO_PCS_DEVAD,
5010 MDIO_PCS_REG_STATUS, &val2);
5011 bnx2x_cl45_read(bp, params->port,
5012 ext_phy_type,
5013 ext_phy_addr,
5014 MDIO_PCS_DEVAD,
5015 MDIO_PCS_REG_STATUS, &val1);
5016 DP(NETIF_MSG_LINK, "807x PCS status 0x%x->0x%x\n",
5017 val2, val1);
6bbca910 5018 /* Clear MSG-OUT */
ea4e040a
YR		 5019 bnx2x_cl45_read(bp, params->port,
5020 ext_phy_type,
5021 ext_phy_addr,
5022 MDIO_PMA_DEVAD,
052a38e0 5023 MDIO_PMA_REG_M8051_MSGOUT_REG,
6bbca910
YR		 5024 &val1);
5025
5026 /* Check the LASI */
ea4e040a
YR		 5027 bnx2x_cl45_read(bp, params->port,
5028 ext_phy_type,
5029 ext_phy_addr,
5030 MDIO_PMA_DEVAD,
6bbca910
YR		 5031 MDIO_PMA_REG_RX_ALARM, &val2);
5032
5033 DP(NETIF_MSG_LINK, "KR 0x9003 0x%x\n", val2);
5034
ea4e040a
YR		 5035 /* Check the link status */
5036 bnx2x_cl45_read(bp, params->port,
5037 ext_phy_type,
5038 ext_phy_addr,
5039 MDIO_PCS_DEVAD,
5040 MDIO_PCS_REG_STATUS, &val2);
5041 DP(NETIF_MSG_LINK, "KR PCS status 0x%x\n", val2);
5042
5043 bnx2x_cl45_read(bp, params->port,
5044 ext_phy_type,
5045 ext_phy_addr,
5046 MDIO_PMA_DEVAD,
5047 MDIO_PMA_REG_STATUS, &val2);
5048 bnx2x_cl45_read(bp, params->port,
5049 ext_phy_type,
5050 ext_phy_addr,
5051 MDIO_PMA_DEVAD,
5052 MDIO_PMA_REG_STATUS, &val1);
5053 ext_phy_link_up = ((val1 & 4) == 4);
5054 DP(NETIF_MSG_LINK, "PMA_REG_STATUS=0x%x\n", val1);
5055 if (ext_phy_type ==
5056 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073) {
6bbca910 5057
ea4e040a 5058 if (ext_phy_link_up &&
6bbca910
YR		 5059 ((params->req_line_speed !=
5060 SPEED_10000))) {
ea4e040a
YR		 5061 if (bnx2x_bcm8073_xaui_wa(params)
5062 != 0) {
5063 ext_phy_link_up = 0;
5064 break;
5065 }
6bbca910
YR		 5066 }
5067 bnx2x_cl45_read(bp, params->port,
052a38e0
EG		 5068 ext_phy_type,
5069 ext_phy_addr,
5070 MDIO_AN_DEVAD,
5071 MDIO_AN_REG_LINK_STATUS,
5072 &an1000_status);
6bbca910 5073 bnx2x_cl45_read(bp, params->port,
052a38e0
EG		 5074 ext_phy_type,
5075 ext_phy_addr,
5076 MDIO_AN_DEVAD,
5077 MDIO_AN_REG_LINK_STATUS,
5078 &an1000_status);
6bbca910 5079
ea4e040a
YR		 5080 /* Check the link status on 1.1.2 */
5081 bnx2x_cl45_read(bp, params->port,
5082 ext_phy_type,
5083 ext_phy_addr,
5084 MDIO_PMA_DEVAD,
5085 MDIO_PMA_REG_STATUS, &val2);
5086 bnx2x_cl45_read(bp, params->port,
5087 ext_phy_type,
5088 ext_phy_addr,
5089 MDIO_PMA_DEVAD,
5090 MDIO_PMA_REG_STATUS, &val1);
5091 DP(NETIF_MSG_LINK, "KR PMA status 0x%x->0x%x,"
5092 "an_link_status=0x%x\n",
5093 val2, val1, an1000_status);
5094
356e2385 5095 ext_phy_link_up = (((val1 & 4) == 4) ||
6bbca910 5096 (an1000_status & (1<<1)));
ea4e040a
YR		 5097 if (ext_phy_link_up &&
5098 bnx2x_8073_is_snr_needed(params)) {
5099 /* The SNR will improve about 2dbby
5100 changing the BW and FEE main tap.*/
5101
5102 /* The 1st write to change FFE main
5103 tap is set before restart AN */
5104 /* Change PLL Bandwidth in EDC
5105 register */
5106 bnx2x_cl45_write(bp, port, ext_phy_type,
5107 ext_phy_addr,
5108 MDIO_PMA_DEVAD,
5109 MDIO_PMA_REG_PLL_BANDWIDTH,
5110 0x26BC);
5111
5112 /* Change CDR Bandwidth in EDC
5113 register */
5114 bnx2x_cl45_write(bp, port, ext_phy_type,
5115 ext_phy_addr,
5116 MDIO_PMA_DEVAD,
5117 MDIO_PMA_REG_CDR_BANDWIDTH,
5118 0x0333);
6bbca910
YR		 5119 }
5120 bnx2x_cl45_read(bp, params->port,
052a38e0
EG		 5121 ext_phy_type,
5122 ext_phy_addr,
5123 MDIO_PMA_DEVAD,
5124 MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
5125 &link_status);
6bbca910
YR		 5126
5127 /* Bits 0..2 --> speed detected,
5128 bits 13..15--> link is down */
5129 if ((link_status & (1<<2)) &&
5130 (!(link_status & (1<<15)))) {
5131 ext_phy_link_up = 1;
5132 vars->line_speed = SPEED_10000;
5133 DP(NETIF_MSG_LINK,
5134 "port %x: External link"
5135 " up in 10G\n", params->port);
5136 } else if ((link_status & (1<<1)) &&
5137 (!(link_status & (1<<14)))) {
5138 ext_phy_link_up = 1;
5139 vars->line_speed = SPEED_2500;
5140 DP(NETIF_MSG_LINK,
5141 "port %x: External link"
5142 " up in 2.5G\n", params->port);
5143 } else if ((link_status & (1<<0)) &&
5144 (!(link_status & (1<<13)))) {
5145 ext_phy_link_up = 1;
5146 vars->line_speed = SPEED_1000;
5147 DP(NETIF_MSG_LINK,
5148 "port %x: External link"
5149 " up in 1G\n", params->port);
5150 } else {
5151 ext_phy_link_up = 0;
5152 DP(NETIF_MSG_LINK,
5153 "port %x: External link"
5154 " is down\n", params->port);
5155 }
5156 } else {
5157 /* See if 1G link is up for the 8072 */
5158 bnx2x_cl45_read(bp, params->port,
052a38e0
EG		 5159 ext_phy_type,
5160 ext_phy_addr,
5161 MDIO_AN_DEVAD,
5162 MDIO_AN_REG_LINK_STATUS,
5163 &an1000_status);
6bbca910 5164 bnx2x_cl45_read(bp, params->port,
052a38e0
EG		 5165 ext_phy_type,
5166 ext_phy_addr,
5167 MDIO_AN_DEVAD,
5168 MDIO_AN_REG_LINK_STATUS,
5169 &an1000_status);
6bbca910
YR		 5170 if (an1000_status & (1<<1)) {
5171 ext_phy_link_up = 1;
5172 vars->line_speed = SPEED_1000;
5173 DP(NETIF_MSG_LINK,
5174 "port %x: External link"
5175 " up in 1G\n", params->port);
5176 } else if (ext_phy_link_up) {
5177 ext_phy_link_up = 1;
5178 vars->line_speed = SPEED_10000;
5179 DP(NETIF_MSG_LINK,
5180 "port %x: External link"
5181 " up in 10G\n", params->port);
ea4e040a
YR		 5182 }
5183 }
6bbca910
YR		 5184
5185
ea4e040a
YR		 5186 break;
5187 }
5188 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
5189 bnx2x_cl45_read(bp, params->port, ext_phy_type,
5190 ext_phy_addr,
5191 MDIO_PMA_DEVAD,
5192 MDIO_PMA_REG_LASI_STATUS, &val2);
5193 bnx2x_cl45_read(bp, params->port, ext_phy_type,
5194 ext_phy_addr,
5195 MDIO_PMA_DEVAD,
5196 MDIO_PMA_REG_LASI_STATUS, &val1);
5197 DP(NETIF_MSG_LINK,
5198 "10G-base-T LASI status 0x%x->0x%x\n",
5199 val2, val1);
5200 bnx2x_cl45_read(bp, params->port, ext_phy_type,
5201 ext_phy_addr,
5202 MDIO_PMA_DEVAD,
5203 MDIO_PMA_REG_STATUS, &val2);
5204 bnx2x_cl45_read(bp, params->port, ext_phy_type,
5205 ext_phy_addr,
5206 MDIO_PMA_DEVAD,
5207 MDIO_PMA_REG_STATUS, &val1);
5208 DP(NETIF_MSG_LINK,
5209 "10G-base-T PMA status 0x%x->0x%x\n",
5210 val2, val1);
5211 ext_phy_link_up = ((val1 & 4) == 4);
5212 /* if link is up
5213 * print the AN outcome of the SFX7101 PHY
5214 */
5215 if (ext_phy_link_up) {
5216 bnx2x_cl45_read(bp, params->port,
5217 ext_phy_type,
5218 ext_phy_addr,
5219 MDIO_AN_DEVAD,
5220 MDIO_AN_REG_MASTER_STATUS,
5221 &val2);
57963ed9 5222 vars->line_speed = SPEED_10000;
ea4e040a
YR		 5223 DP(NETIF_MSG_LINK,
5224 "SFX7101 AN status 0x%x->Master=%x\n",
5225 val2,
5226 (val2 & (1<<14)));
5227 }
5228 break;
28577185 5229 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
28577185 5230 /* Check 10G-BaseT link status */
2f904460 5231 /* Check PMD signal ok */
28577185 5232 bnx2x_cl45_read(bp, params->port, ext_phy_type,
2f904460
EG		 5233 ext_phy_addr,
5234 MDIO_AN_DEVAD,
5235 0xFFFA,
5236 &val1);
28577185
EG		 5237 bnx2x_cl45_read(bp, params->port, ext_phy_type,
5238 ext_phy_addr,
2f904460
EG		 5239 MDIO_PMA_DEVAD,
5240 MDIO_PMA_REG_8481_PMD_SIGNAL,
5241 &val2);
5242 DP(NETIF_MSG_LINK, "PMD_SIGNAL 1.a811 = 0x%x\n", val2);
5243
5244 /* Check link 10G */
5245 if (val2 & (1<<11)) {
28577185
EG		 5246 vars->line_speed = SPEED_10000;
5247 ext_phy_link_up = 1;
2f904460
EG		 5248 bnx2x_8481_set_10G_led_mode(params,
5249 ext_phy_type,
5250 ext_phy_addr);
5251 } else { /* Check Legacy speed link */
5252 u16 legacy_status, legacy_speed;
5253
5254 /* Enable expansion register 0x42
5255 (Operation mode status) */
5256 bnx2x_cl45_write(bp, params->port,
5257 ext_phy_type,
5258 ext_phy_addr,
5259 MDIO_AN_DEVAD,
5260 MDIO_AN_REG_8481_EXPANSION_REG_ACCESS,
5261 0xf42);
ea4e040a 5262
2f904460
EG		 5263 /* Get legacy speed operation status */
5264 bnx2x_cl45_read(bp, params->port,
5265 ext_phy_type,
5266 ext_phy_addr,
5267 MDIO_AN_DEVAD,
5268 MDIO_AN_REG_8481_EXPANSION_REG_RD_RW,
5269 &legacy_status);
5270
5271 DP(NETIF_MSG_LINK, "Legacy speed status"
5272 " = 0x%x\n", legacy_status);
5273 ext_phy_link_up = ((legacy_status & (1<<11))
5274 == (1<<11));
5275 if (ext_phy_link_up) {
5276 legacy_speed = (legacy_status & (3<<9));
5277 if (legacy_speed == (0<<9))
5278 vars->line_speed = SPEED_10;
5279 else if (legacy_speed == (1<<9))
5280 vars->line_speed =
5281 SPEED_100;
5282 else if (legacy_speed == (2<<9))
5283 vars->line_speed =
5284 SPEED_1000;
5285 else /* Should not happen */
5286 vars->line_speed = 0;
5287
5288 if (legacy_status & (1<<8))
5289 vars->duplex = DUPLEX_FULL;
5290 else
5291 vars->duplex = DUPLEX_HALF;
5292
5293 DP(NETIF_MSG_LINK, "Link is up "
5294 "in %dMbps, is_duplex_full"
5295 "= %d\n",
5296 vars->line_speed,
5297 (vars->duplex == DUPLEX_FULL));
5298 bnx2x_8481_set_legacy_led_mode(params,
5299 ext_phy_type,
5300 ext_phy_addr);
28577185
EG		 5301 }
5302 }
28577185 5303 break;
ea4e040a
YR		 5304 default:
5305 DP(NETIF_MSG_LINK, "BAD XGXS ext_phy_config 0x%x\n",
5306 params->ext_phy_config);
5307 ext_phy_link_up = 0;
5308 break;
5309 }
57937203
EG		 5310 /* Set SGMII mode for external phy */
5311 if (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) {
5312 if (vars->line_speed < SPEED_1000)
5313 vars->phy_flags |= PHY_SGMII_FLAG;
5314 else
5315 vars->phy_flags &= ~PHY_SGMII_FLAG;
5316 }
ea4e040a
YR		 5317
5318 } else { /* SerDes */
5319 ext_phy_type = SERDES_EXT_PHY_TYPE(params->ext_phy_config);
5320 switch (ext_phy_type) {
5321 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT:
5322 DP(NETIF_MSG_LINK, "SerDes Direct\n");
5323 ext_phy_link_up = 1;
5324 break;
5325
5326 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482:
5327 DP(NETIF_MSG_LINK, "SerDes 5482\n");
5328 ext_phy_link_up = 1;
5329 break;
5330
5331 default:
5332 DP(NETIF_MSG_LINK,
5333 "BAD SerDes ext_phy_config 0x%x\n",
5334 params->ext_phy_config);
5335 ext_phy_link_up = 0;
5336 break;
5337 }
5338 }
5339
5340 return ext_phy_link_up;
5341}
5342
5343static void bnx2x_link_int_enable(struct link_params *params)
5344{
5345 u8 port = params->port;
5346 u32 ext_phy_type;
5347 u32 mask;
5348 struct bnx2x *bp = params->bp;
ab6ad5a4 5349
ea4e040a
YR		 5350 /* setting the status to report on link up
5351 for either XGXS or SerDes */
5352
5353 if (params->switch_cfg == SWITCH_CFG_10G) {
5354 mask = (NIG_MASK_XGXS0_LINK10G |
5355 NIG_MASK_XGXS0_LINK_STATUS);
5356 DP(NETIF_MSG_LINK, "enabled XGXS interrupt\n");
5357 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
5358 if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
5359 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
5360 (ext_phy_type !=
5361 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)) {
5362 mask |= NIG_MASK_MI_INT;
5363 DP(NETIF_MSG_LINK, "enabled external phy int\n");
5364 }
5365
5366 } else { /* SerDes */
5367 mask = NIG_MASK_SERDES0_LINK_STATUS;
5368 DP(NETIF_MSG_LINK, "enabled SerDes interrupt\n");
5369 ext_phy_type = SERDES_EXT_PHY_TYPE(params->ext_phy_config);
5370 if ((ext_phy_type !=
5371 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT) &&
5372 (ext_phy_type !=
5373 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN)) {
5374 mask |= NIG_MASK_MI_INT;
5375 DP(NETIF_MSG_LINK, "enabled external phy int\n");
5376 }
5377 }
5378 bnx2x_bits_en(bp,
5379 NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
5380 mask);
ab6ad5a4
EG		 5381
5382 DP(NETIF_MSG_LINK, "port %x, is_xgxs %x, int_status 0x%x\n", port,
ea4e040a
YR		 5383 (params->switch_cfg == SWITCH_CFG_10G),
5384 REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
ea4e040a
YR		 5385 DP(NETIF_MSG_LINK, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x\n",
5386 REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
5387 REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18),
5388 REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS+port*0x3c));
5389 DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
5390 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
5391 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
5392}
5393
2f904460
EG		 5394static void bnx2x_8481_rearm_latch_signal(struct bnx2x *bp, u8 port,
5395 u8 is_mi_int)
5396{
5397 u32 latch_status = 0, is_mi_int_status;
5398 /* Disable the MI INT ( external phy int )
5399 * by writing 1 to the status register. Link down indication
5400 * is high-active-signal, so in this case we need to write the
5401 * status to clear the XOR
5402 */
5403 /* Read Latched signals */
5404 latch_status = REG_RD(bp,
5405 NIG_REG_LATCH_STATUS_0 + port*8);
5406 is_mi_int_status = REG_RD(bp,
5407 NIG_REG_STATUS_INTERRUPT_PORT0 + port*4);
5408 DP(NETIF_MSG_LINK, "original_signal = 0x%x, nig_status = 0x%x,"
5409 "latch_status = 0x%x\n",
5410 is_mi_int, is_mi_int_status, latch_status);
5411 /* Handle only those with latched-signal=up.*/
5412 if (latch_status & 1) {
5413 /* For all latched-signal=up,Write original_signal to status */
5414 if (is_mi_int)
5415 bnx2x_bits_en(bp,
5416 NIG_REG_STATUS_INTERRUPT_PORT0
5417 + port*4,
5418 NIG_STATUS_EMAC0_MI_INT);
5419 else
5420 bnx2x_bits_dis(bp,
5421 NIG_REG_STATUS_INTERRUPT_PORT0
5422 + port*4,
5423 NIG_STATUS_EMAC0_MI_INT);
5424 /* For all latched-signal=up : Re-Arm Latch signals */
5425 REG_WR(bp, NIG_REG_LATCH_STATUS_0 + port*8,
5426 (latch_status & 0xfffe) | (latch_status & 1));
5427 }
5428}
ea4e040a
YR		 5429/*
5430 * link management
5431 */
5432static void bnx2x_link_int_ack(struct link_params *params,
2f904460
EG		 5433 struct link_vars *vars, u8 is_10g,
5434 u8 is_mi_int)
ea4e040a
YR		 5435{
5436 struct bnx2x *bp = params->bp;
5437 u8 port = params->port;
5438
5439 /* first reset all status
5440 * we assume only one line will be change at a time */
5441 bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
5442 (NIG_STATUS_XGXS0_LINK10G |
5443 NIG_STATUS_XGXS0_LINK_STATUS |
5444 NIG_STATUS_SERDES0_LINK_STATUS));
2f904460
EG		 5445 if (XGXS_EXT_PHY_TYPE(params->ext_phy_config)
5446 == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481) {
5447 bnx2x_8481_rearm_latch_signal(bp, port, is_mi_int);
5448 }
ea4e040a
YR		 5449 if (vars->phy_link_up) {
5450 if (is_10g) {
5451 /* Disable the 10G link interrupt
5452 * by writing 1 to the status register
5453 */
5454 DP(NETIF_MSG_LINK, "10G XGXS phy link up\n");
5455 bnx2x_bits_en(bp,
5456 NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
5457 NIG_STATUS_XGXS0_LINK10G);
5458
5459 } else if (params->switch_cfg == SWITCH_CFG_10G) {
5460 /* Disable the link interrupt
5461 * by writing 1 to the relevant lane
5462 * in the status register
5463 */
5464 u32 ser_lane = ((params->lane_config &
5465 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
5466 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
5467
2f904460
EG		 5468 DP(NETIF_MSG_LINK, "%d speed XGXS phy link up\n",
5469 vars->line_speed);
ea4e040a
YR		 5470 bnx2x_bits_en(bp,
5471 NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
5472 ((1 << ser_lane) <<
5473 NIG_STATUS_XGXS0_LINK_STATUS_SIZE));
5474
5475 } else { /* SerDes */
5476 DP(NETIF_MSG_LINK, "SerDes phy link up\n");
5477 /* Disable the link interrupt
5478 * by writing 1 to the status register
5479 */
5480 bnx2x_bits_en(bp,
5481 NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
5482 NIG_STATUS_SERDES0_LINK_STATUS);
5483 }
5484
5485 } else { /* link_down */
5486 }
5487}
5488
5489static u8 bnx2x_format_ver(u32 num, u8 *str, u16 len)
5490{
5491 u8 *str_ptr = str;
5492 u32 mask = 0xf0000000;
5493 u8 shift = 8*4;
5494 u8 digit;
5495 if (len < 10) {
025dfdaf 5496 /* Need more than 10chars for this format */
ea4e040a
YR		 5497 *str_ptr = '\0';
5498 return -EINVAL;
5499 }
5500 while (shift > 0) {
5501
5502 shift -= 4;
5503 digit = ((num & mask) >> shift);
5504 if (digit < 0xa)
5505 *str_ptr = digit + '0';
5506 else
5507 *str_ptr = digit - 0xa + 'a';
5508 str_ptr++;
5509 mask = mask >> 4;
5510 if (shift == 4*4) {
5511 *str_ptr = ':';
5512 str_ptr++;
5513 }
5514 }
5515 *str_ptr = '\0';
5516 return 0;
5517}
5518
ea4e040a
YR		 5519u8 bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 driver_loaded,
5520 u8 *version, u16 len)
5521{
0376d5b2 5522 struct bnx2x *bp;
ea4e040a 5523 u32 ext_phy_type = 0;
a35da8db 5524 u32 spirom_ver = 0;
97b41dad 5525 u8 status;
ea4e040a
YR		 5526
5527 if (version == NULL || params == NULL)
5528 return -EINVAL;
0376d5b2 5529 bp = params->bp;
ea4e040a 5530
a35da8db
EG		 5531 spirom_ver = REG_RD(bp, params->shmem_base +
5532 offsetof(struct shmem_region,
5533 port_mb[params->port].ext_phy_fw_version));
5534
97b41dad 5535 status = 0;
ea4e040a
YR		 5536 /* reset the returned value to zero */
5537 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
ea4e040a
YR		 5538 switch (ext_phy_type) {
5539 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
5540
5541 if (len < 5)
5542 return -EINVAL;
5543
a35da8db
EG		 5544 version[0] = (spirom_ver & 0xFF);
5545 version[1] = (spirom_ver & 0xFF00) >> 8;
5546 version[2] = (spirom_ver & 0xFF0000) >> 16;
5547 version[3] = (spirom_ver & 0xFF000000) >> 24;
ea4e040a
YR		 5548 version[4] = '\0';
5549
ea4e040a
YR		 5550 break;
5551 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
5552 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
4d295db0 5553 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
ea4e040a 5554 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
589abe3a 5555 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
b1607af5
EG		 5556 status = bnx2x_format_ver(spirom_ver, version, len);
5557 break;
9223dea6 5558 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
b1607af5
EG		 5559 spirom_ver = ((spirom_ver & 0xF80) >> 7) << 16 |
5560 (spirom_ver & 0x7F);
a35da8db 5561 status = bnx2x_format_ver(spirom_ver, version, len);
ea4e040a 5562 break;
ea4e040a 5563 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
97b41dad
EG		 5564 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
5565 version[0] = '\0';
ea4e040a
YR		 5566 break;
5567
5568 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
5569 DP(NETIF_MSG_LINK, "bnx2x_get_ext_phy_fw_version:"
5570 " type is FAILURE!\n");
5571 status = -EINVAL;
5572 break;
5573
5574 default:
5575 break;
5576 }
5577 return status;
5578}
5579
5580static void bnx2x_set_xgxs_loopback(struct link_params *params,
5581 struct link_vars *vars,
5582 u8 is_10g)
5583{
5584 u8 port = params->port;
5585 struct bnx2x *bp = params->bp;
5586
5587 if (is_10g) {
6378c025 5588 u32 md_devad;
ea4e040a
YR		 5589
5590 DP(NETIF_MSG_LINK, "XGXS 10G loopback enable\n");
5591
5592 /* change the uni_phy_addr in the nig */
5593 md_devad = REG_RD(bp, (NIG_REG_XGXS0_CTRL_MD_DEVAD +
5594 port*0x18));
5595
5596 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, 0x5);
5597
5598 bnx2x_cl45_write(bp, port, 0,
5599 params->phy_addr,
5600 5,
5601 (MDIO_REG_BANK_AER_BLOCK +
5602 (MDIO_AER_BLOCK_AER_REG & 0xf)),
5603 0x2800);
5604
5605 bnx2x_cl45_write(bp, port, 0,
5606 params->phy_addr,
5607 5,
5608 (MDIO_REG_BANK_CL73_IEEEB0 +
5609 (MDIO_CL73_IEEEB0_CL73_AN_CONTROL & 0xf)),
5610 0x6041);
3858276b 5611 msleep(200);
ea4e040a
YR		 5612 /* set aer mmd back */
5613 bnx2x_set_aer_mmd(params, vars);
5614
5615 /* and md_devad */
5616 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
5617 md_devad);
5618
5619 } else {
5620 u16 mii_control;
5621
5622 DP(NETIF_MSG_LINK, "XGXS 1G loopback enable\n");
5623
5624 CL45_RD_OVER_CL22(bp, port,
5625 params->phy_addr,
5626 MDIO_REG_BANK_COMBO_IEEE0,
5627 MDIO_COMBO_IEEE0_MII_CONTROL,
5628 &mii_control);
5629
5630 CL45_WR_OVER_CL22(bp, port,
5631 params->phy_addr,
5632 MDIO_REG_BANK_COMBO_IEEE0,
5633 MDIO_COMBO_IEEE0_MII_CONTROL,
5634 (mii_control |
5635 MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK));
5636 }
5637}
5638
5639
5640static void bnx2x_ext_phy_loopback(struct link_params *params)
5641{
5642 struct bnx2x *bp = params->bp;
5643 u8 ext_phy_addr;
5644 u32 ext_phy_type;
5645
5646 if (params->switch_cfg == SWITCH_CFG_10G) {
5647 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
659bc5c4 5648 ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
ea4e040a 5649 /* CL37 Autoneg Enabled */
ea4e040a
YR		 5650 switch (ext_phy_type) {
5651 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
5652 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN:
5653 DP(NETIF_MSG_LINK,
5654 "ext_phy_loopback: We should not get here\n");
5655 break;
5656 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
5657 DP(NETIF_MSG_LINK, "ext_phy_loopback: 8705\n");
5658 break;
5659 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
5660 DP(NETIF_MSG_LINK, "ext_phy_loopback: 8706\n");
5661 break;
589abe3a
EG		 5662 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
5663 DP(NETIF_MSG_LINK, "PMA/PMD ext_phy_loopback: 8726\n");
5664 bnx2x_cl45_write(bp, params->port, ext_phy_type,
5665 ext_phy_addr,
5666 MDIO_PMA_DEVAD,
5667 MDIO_PMA_REG_CTRL,
5668 0x0001);
5669 break;
ea4e040a
YR		 5670 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
5671 /* SFX7101_XGXS_TEST1 */
5672 bnx2x_cl45_write(bp, params->port, ext_phy_type,
5673 ext_phy_addr,
5674 MDIO_XS_DEVAD,
5675 MDIO_XS_SFX7101_XGXS_TEST1,
5676 0x100);
5677 DP(NETIF_MSG_LINK,
5678 "ext_phy_loopback: set ext phy loopback\n");
5679 break;
5680 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
5681
5682 break;
5683 } /* switch external PHY type */
5684 } else {
5685 /* serdes */
5686 ext_phy_type = SERDES_EXT_PHY_TYPE(params->ext_phy_config);
5687 ext_phy_addr = (params->ext_phy_config &
5688 PORT_HW_CFG_SERDES_EXT_PHY_ADDR_MASK)
5689 >> PORT_HW_CFG_SERDES_EXT_PHY_ADDR_SHIFT;
5690 }
5691}
5692
5693
5694/*
5695 *------------------------------------------------------------------------
5696 * bnx2x_override_led_value -
5697 *
5698 * Override the led value of the requsted led
5699 *
5700 *------------------------------------------------------------------------
5701 */
5702u8 bnx2x_override_led_value(struct bnx2x *bp, u8 port,
5703 u32 led_idx, u32 value)
5704{
5705 u32 reg_val;
5706
5707 /* If port 0 then use EMAC0, else use EMAC1*/
5708 u32 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
5709
5710 DP(NETIF_MSG_LINK,
5711 "bnx2x_override_led_value() port %x led_idx %d value %d\n",
5712 port, led_idx, value);
5713
5714 switch (led_idx) {
5715 case 0: /* 10MB led */
5716 /* Read the current value of the LED register in
5717 the EMAC block */
5718 reg_val = REG_RD(bp, emac_base + EMAC_REG_EMAC_LED);
5719 /* Set the OVERRIDE bit to 1 */
5720 reg_val |= EMAC_LED_OVERRIDE;
5721 /* If value is 1, set the 10M_OVERRIDE bit,
5722 otherwise reset it.*/
5723 reg_val = (value == 1) ? (reg_val | EMAC_LED_10MB_OVERRIDE) :
5724 (reg_val & ~EMAC_LED_10MB_OVERRIDE);
5725 REG_WR(bp, emac_base + EMAC_REG_EMAC_LED, reg_val);
5726 break;
5727 case 1: /*100MB led */
5728 /*Read the current value of the LED register in
5729 the EMAC block */
5730 reg_val = REG_RD(bp, emac_base + EMAC_REG_EMAC_LED);
5731 /* Set the OVERRIDE bit to 1 */
5732 reg_val |= EMAC_LED_OVERRIDE;
5733 /* If value is 1, set the 100M_OVERRIDE bit,
5734 otherwise reset it.*/
5735 reg_val = (value == 1) ? (reg_val | EMAC_LED_100MB_OVERRIDE) :
5736 (reg_val & ~EMAC_LED_100MB_OVERRIDE);
5737 REG_WR(bp, emac_base + EMAC_REG_EMAC_LED, reg_val);
5738 break;
5739 case 2: /* 1000MB led */
5740 /* Read the current value of the LED register in the
5741 EMAC block */
5742 reg_val = REG_RD(bp, emac_base + EMAC_REG_EMAC_LED);
5743 /* Set the OVERRIDE bit to 1 */
5744 reg_val |= EMAC_LED_OVERRIDE;
5745 /* If value is 1, set the 1000M_OVERRIDE bit, otherwise
5746 reset it. */
5747 reg_val = (value == 1) ? (reg_val | EMAC_LED_1000MB_OVERRIDE) :
5748 (reg_val & ~EMAC_LED_1000MB_OVERRIDE);
5749 REG_WR(bp, emac_base + EMAC_REG_EMAC_LED, reg_val);
5750 break;
5751 case 3: /* 2500MB led */
5752 /* Read the current value of the LED register in the
5753 EMAC block*/
5754 reg_val = REG_RD(bp, emac_base + EMAC_REG_EMAC_LED);
5755 /* Set the OVERRIDE bit to 1 */
5756 reg_val |= EMAC_LED_OVERRIDE;
5757 /* If value is 1, set the 2500M_OVERRIDE bit, otherwise
5758 reset it.*/
5759 reg_val = (value == 1) ? (reg_val | EMAC_LED_2500MB_OVERRIDE) :
5760 (reg_val & ~EMAC_LED_2500MB_OVERRIDE);
5761 REG_WR(bp, emac_base + EMAC_REG_EMAC_LED, reg_val);
5762 break;
5763 case 4: /*10G led */
5764 if (port == 0) {
5765 REG_WR(bp, NIG_REG_LED_10G_P0,
5766 value);
5767 } else {
5768 REG_WR(bp, NIG_REG_LED_10G_P1,
5769 value);
5770 }
5771 break;
5772 case 5: /* TRAFFIC led */
5773 /* Find if the traffic control is via BMAC or EMAC */
5774 if (port == 0)
5775 reg_val = REG_RD(bp, NIG_REG_NIG_EMAC0_EN);
5776 else
5777 reg_val = REG_RD(bp, NIG_REG_NIG_EMAC1_EN);
5778
5779 /* Override the traffic led in the EMAC:*/
5780 if (reg_val == 1) {
5781 /* Read the current value of the LED register in
5782 the EMAC block */
5783 reg_val = REG_RD(bp, emac_base +
5784 EMAC_REG_EMAC_LED);
5785 /* Set the TRAFFIC_OVERRIDE bit to 1 */
5786 reg_val |= EMAC_LED_OVERRIDE;
5787 /* If value is 1, set the TRAFFIC bit, otherwise
5788 reset it.*/
5789 reg_val = (value == 1) ? (reg_val | EMAC_LED_TRAFFIC) :
5790 (reg_val & ~EMAC_LED_TRAFFIC);
5791 REG_WR(bp, emac_base + EMAC_REG_EMAC_LED, reg_val);
5792 } else { /* Override the traffic led in the BMAC: */
5793 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0
5794 + port*4, 1);
5795 REG_WR(bp, NIG_REG_LED_CONTROL_TRAFFIC_P0 + port*4,
5796 value);
5797 }
5798 break;
5799 default:
5800 DP(NETIF_MSG_LINK,
5801 "bnx2x_override_led_value() unknown led index %d "
5802 "(should be 0-5)\n", led_idx);
5803 return -EINVAL;
5804 }
5805
5806 return 0;
5807}
5808
5809
7846e471 5810u8 bnx2x_set_led(struct link_params *params, u8 mode, u32 speed)
ea4e040a 5811{
7846e471
YR		 5812 u8 port = params->port;
5813 u16 hw_led_mode = params->hw_led_mode;
ea4e040a 5814 u8 rc = 0;
345b5d52
EG		 5815 u32 tmp;
5816 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
7846e471
YR		 5817 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
5818 struct bnx2x *bp = params->bp;
ea4e040a
YR		 5819 DP(NETIF_MSG_LINK, "bnx2x_set_led: port %x, mode %d\n", port, mode);
5820 DP(NETIF_MSG_LINK, "speed 0x%x, hw_led_mode 0x%x\n",
5821 speed, hw_led_mode);
5822 switch (mode) {
5823 case LED_MODE_OFF:
5824 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 0);
5825 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
5826 SHARED_HW_CFG_LED_MAC1);
345b5d52
EG		 5827
5828 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
3196a88a 5829 EMAC_WR(bp, EMAC_REG_EMAC_LED, (tmp | EMAC_LED_OVERRIDE));
ea4e040a
YR		 5830 break;
5831
5832 case LED_MODE_OPER:
7846e471
YR		 5833 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) {
5834 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
5835 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);
5836 } else {
5837 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
5838 hw_led_mode);
5839 }
5840
ea4e040a
YR		 5841 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 +
5842 port*4, 0);
5843 /* Set blinking rate to ~15.9Hz */
5844 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
5845 LED_BLINK_RATE_VAL);
5846 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 +
5847 port*4, 1);
345b5d52 5848 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
3196a88a 5849 EMAC_WR(bp, EMAC_REG_EMAC_LED,
345b5d52
EG		 5850 (tmp & (~EMAC_LED_OVERRIDE)));
5851
7846e471 5852 if (CHIP_IS_E1(bp) &&
34f80b04 5853 ((speed == SPEED_2500) ||
ea4e040a
YR		 5854 (speed == SPEED_1000) ||
5855 (speed == SPEED_100) ||
5856 (speed == SPEED_10))) {
5857 /* On Everest 1 Ax chip versions for speeds less than
5858 10G LED scheme is different */
5859 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0
5860 + port*4, 1);
5861 REG_WR(bp, NIG_REG_LED_CONTROL_TRAFFIC_P0 +
5862 port*4, 0);
5863 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 +
5864 port*4, 1);
5865 }
5866 break;
5867
5868 default:
5869 rc = -EINVAL;
5870 DP(NETIF_MSG_LINK, "bnx2x_set_led: Invalid led mode %d\n",
5871 mode);
5872 break;
5873 }
5874 return rc;
5875
5876}
5877
5878u8 bnx2x_test_link(struct link_params *params, struct link_vars *vars)
5879{
5880 struct bnx2x *bp = params->bp;
5881 u16 gp_status = 0;
5882
5883 CL45_RD_OVER_CL22(bp, params->port,
5884 params->phy_addr,
5885 MDIO_REG_BANK_GP_STATUS,
5886 MDIO_GP_STATUS_TOP_AN_STATUS1,
5887 &gp_status);
5888 /* link is up only if both local phy and external phy are up */
5889 if ((gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) &&
2f904460 5890 bnx2x_ext_phy_is_link_up(params, vars, 1))
ea4e040a
YR		 5891 return 0;
5892
5893 return -ESRCH;
5894}
5895
5896static u8 bnx2x_link_initialize(struct link_params *params,
5897 struct link_vars *vars)
5898{
5899 struct bnx2x *bp = params->bp;
5900 u8 port = params->port;
5901 u8 rc = 0;
57963ed9
YR		 5902 u8 non_ext_phy;
5903 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
ab6ad5a4 5904
ea4e040a
YR		 5905 /* Activate the external PHY */
5906 bnx2x_ext_phy_reset(params, vars);
5907
5908 bnx2x_set_aer_mmd(params, vars);
5909
5910 if (vars->phy_flags & PHY_XGXS_FLAG)
5911 bnx2x_set_master_ln(params);
5912
5913 rc = bnx2x_reset_unicore(params);
5914 /* reset the SerDes and wait for reset bit return low */
5915 if (rc != 0)
5916 return rc;
5917
5918 bnx2x_set_aer_mmd(params, vars);
5919
5920 /* setting the masterLn_def again after the reset */
5921 if (vars->phy_flags & PHY_XGXS_FLAG) {
5922 bnx2x_set_master_ln(params);
5923 bnx2x_set_swap_lanes(params);
5924 }
5925
ea4e040a 5926 if (vars->phy_flags & PHY_XGXS_FLAG) {
44722d1d 5927 if ((params->req_line_speed &&
ea4e040a 5928 ((params->req_line_speed == SPEED_100) ||
44722d1d
EG		 5929 (params->req_line_speed == SPEED_10))) ||
5930 (!params->req_line_speed &&
5931 (params->speed_cap_mask >=
5932 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) &&
5933 (params->speed_cap_mask <
5934 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
5935 )) {
ea4e040a
YR		 5936 vars->phy_flags |= PHY_SGMII_FLAG;
5937 } else {
5938 vars->phy_flags &= ~PHY_SGMII_FLAG;
5939 }
5940 }
57963ed9
YR		 5941 /* In case of external phy existance, the line speed would be the
5942 line speed linked up by the external phy. In case it is direct only,
5943 then the line_speed during initialization will be equal to the
5944 req_line_speed*/
5945 vars->line_speed = params->req_line_speed;
ea4e040a 5946
8c99e7b0 5947 bnx2x_calc_ieee_aneg_adv(params, &vars->ieee_fc);
ea4e040a 5948
57963ed9
YR		 5949 /* init ext phy and enable link state int */
5950 non_ext_phy = ((ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ||
8660d8c3 5951 (params->loopback_mode == LOOPBACK_XGXS_10));
57963ed9
YR		 5952
5953 if (non_ext_phy ||
589abe3a 5954 (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705) ||
28577185 5955 (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) ||
8660d8c3 5956 (params->loopback_mode == LOOPBACK_EXT_PHY)) {
57963ed9
YR		 5957 if (params->req_line_speed == SPEED_AUTO_NEG)
5958 bnx2x_set_parallel_detection(params, vars->phy_flags);
239d686d 5959 bnx2x_init_internal_phy(params, vars, non_ext_phy);
ea4e040a
YR		 5960 }
5961
57963ed9
YR		 5962 if (!non_ext_phy)
5963 rc |= bnx2x_ext_phy_init(params, vars);
ea4e040a
YR		 5964
5965 bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
57963ed9
YR		 5966 (NIG_STATUS_XGXS0_LINK10G |
5967 NIG_STATUS_XGXS0_LINK_STATUS |
5968 NIG_STATUS_SERDES0_LINK_STATUS));
ea4e040a
YR		 5969
5970 return rc;
5971
5972}
5973
5974
5975u8 bnx2x_phy_init(struct link_params *params, struct link_vars *vars)
5976{
5977 struct bnx2x *bp = params->bp;
ea4e040a 5978 u32 val;
ab6ad5a4
EG		 5979
5980 DP(NETIF_MSG_LINK, "Phy Initialization started\n");
5981 DP(NETIF_MSG_LINK, "req_speed %d, req_flowctrl %d\n",
5982 params->req_line_speed, params->req_flow_ctrl);
ea4e040a 5983 vars->link_status = 0;
57963ed9
YR		 5984 vars->phy_link_up = 0;
5985 vars->link_up = 0;
5986 vars->line_speed = 0;
5987 vars->duplex = DUPLEX_FULL;
c0700f90 5988 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
57963ed9
YR		 5989 vars->mac_type = MAC_TYPE_NONE;
5990
ea4e040a
YR		 5991 if (params->switch_cfg == SWITCH_CFG_1G)
5992 vars->phy_flags = PHY_SERDES_FLAG;
5993 else
5994 vars->phy_flags = PHY_XGXS_FLAG;
5995
5996 /* disable attentions */
5997 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
5998 (NIG_MASK_XGXS0_LINK_STATUS |
5999 NIG_MASK_XGXS0_LINK10G |
6000 NIG_MASK_SERDES0_LINK_STATUS |
6001 NIG_MASK_MI_INT));
6002
6003 bnx2x_emac_init(params, vars);
6004
6005 if (CHIP_REV_IS_FPGA(bp)) {
ab6ad5a4 6006
ea4e040a
YR		 6007 vars->link_up = 1;
6008 vars->line_speed = SPEED_10000;
6009 vars->duplex = DUPLEX_FULL;
c0700f90 6010 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
ea4e040a 6011 vars->link_status = (LINK_STATUS_LINK_UP | LINK_10GTFD);
34f80b04
EG		 6012 /* enable on E1.5 FPGA */
6013 if (CHIP_IS_E1H(bp)) {
6014 vars->flow_ctrl |=
ab6ad5a4
EG		 6015 (BNX2X_FLOW_CTRL_TX |
6016 BNX2X_FLOW_CTRL_RX);
34f80b04
EG		 6017 vars->link_status |=
6018 (LINK_STATUS_TX_FLOW_CONTROL_ENABLED |
6019 LINK_STATUS_RX_FLOW_CONTROL_ENABLED);
6020 }
ea4e040a
YR		 6021
6022 bnx2x_emac_enable(params, vars, 0);
6023 bnx2x_pbf_update(params, vars->flow_ctrl, vars->line_speed);
6024 /* disable drain */
ab6ad5a4 6025 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
ea4e040a
YR		 6026
6027 /* update shared memory */
6028 bnx2x_update_mng(params, vars->link_status);
6029
6030 return 0;
6031
6032 } else
6033 if (CHIP_REV_IS_EMUL(bp)) {
6034
6035 vars->link_up = 1;
6036 vars->line_speed = SPEED_10000;
6037 vars->duplex = DUPLEX_FULL;
c0700f90 6038 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
ea4e040a
YR		 6039 vars->link_status = (LINK_STATUS_LINK_UP | LINK_10GTFD);
6040
6041 bnx2x_bmac_enable(params, vars, 0);
6042
6043 bnx2x_pbf_update(params, vars->flow_ctrl, vars->line_speed);
6044 /* Disable drain */
6045 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE
6046 + params->port*4, 0);
6047
6048 /* update shared memory */
6049 bnx2x_update_mng(params, vars->link_status);
6050
6051 return 0;
6052
6053 } else
6054 if (params->loopback_mode == LOOPBACK_BMAC) {
ab6ad5a4 6055
ea4e040a
YR		 6056 vars->link_up = 1;
6057 vars->line_speed = SPEED_10000;
6058 vars->duplex = DUPLEX_FULL;
c0700f90 6059 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
ea4e040a
YR		 6060 vars->mac_type = MAC_TYPE_BMAC;
6061
6062 vars->phy_flags = PHY_XGXS_FLAG;
6063
6064 bnx2x_phy_deassert(params, vars->phy_flags);
6065 /* set bmac loopback */
6066 bnx2x_bmac_enable(params, vars, 1);
6067
6068 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE +
6069 params->port*4, 0);
ab6ad5a4 6070
ea4e040a 6071 } else if (params->loopback_mode == LOOPBACK_EMAC) {
ab6ad5a4 6072
ea4e040a
YR		 6073 vars->link_up = 1;
6074 vars->line_speed = SPEED_1000;
6075 vars->duplex = DUPLEX_FULL;
c0700f90 6076 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
ea4e040a
YR		 6077 vars->mac_type = MAC_TYPE_EMAC;
6078
6079 vars->phy_flags = PHY_XGXS_FLAG;
6080
6081 bnx2x_phy_deassert(params, vars->phy_flags);
6082 /* set bmac loopback */
6083 bnx2x_emac_enable(params, vars, 1);
6084 bnx2x_emac_program(params, vars->line_speed,
6085 vars->duplex);
6086 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE +
6087 params->port*4, 0);
ab6ad5a4 6088
ea4e040a 6089 } else if ((params->loopback_mode == LOOPBACK_XGXS_10) ||
ab6ad5a4
EG		 6090 (params->loopback_mode == LOOPBACK_EXT_PHY)) {
6091
ea4e040a
YR		 6092 vars->link_up = 1;
6093 vars->line_speed = SPEED_10000;
6094 vars->duplex = DUPLEX_FULL;
c0700f90 6095 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
ea4e040a
YR		 6096
6097 vars->phy_flags = PHY_XGXS_FLAG;
6098
6099 val = REG_RD(bp,
6100 NIG_REG_XGXS0_CTRL_PHY_ADDR+
6101 params->port*0x18);
6102 params->phy_addr = (u8)val;
6103
6104 bnx2x_phy_deassert(params, vars->phy_flags);
6105 bnx2x_link_initialize(params, vars);
6106
6107 vars->mac_type = MAC_TYPE_BMAC;
6108
6109 bnx2x_bmac_enable(params, vars, 0);
6110
6111 if (params->loopback_mode == LOOPBACK_XGXS_10) {
6112 /* set 10G XGXS loopback */
6113 bnx2x_set_xgxs_loopback(params, vars, 1);
6114 } else {
6115 /* set external phy loopback */
6116 bnx2x_ext_phy_loopback(params);
6117 }
6118 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE +
6119 params->port*4, 0);
ba71d313 6120
7846e471 6121 bnx2x_set_led(params, LED_MODE_OPER, vars->line_speed);
ea4e040a
YR		 6122 } else
6123 /* No loopback */
6124 {
ea4e040a
YR		 6125 bnx2x_phy_deassert(params, vars->phy_flags);
6126 switch (params->switch_cfg) {
6127 case SWITCH_CFG_1G:
6128 vars->phy_flags |= PHY_SERDES_FLAG;
6129 if ((params->ext_phy_config &
6130 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK) ==
6131 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482) {
ab6ad5a4 6132 vars->phy_flags |= PHY_SGMII_FLAG;
ea4e040a
YR		 6133 }
6134
6135 val = REG_RD(bp,
6136 NIG_REG_SERDES0_CTRL_PHY_ADDR+
6137 params->port*0x10);
6138
6139 params->phy_addr = (u8)val;
6140
6141 break;
6142 case SWITCH_CFG_10G:
6143 vars->phy_flags |= PHY_XGXS_FLAG;
6144 val = REG_RD(bp,
6145 NIG_REG_XGXS0_CTRL_PHY_ADDR+
6146 params->port*0x18);
6147 params->phy_addr = (u8)val;
6148
6149 break;
6150 default:
6151 DP(NETIF_MSG_LINK, "Invalid switch_cfg\n");
6152 return -EINVAL;
ea4e040a 6153 }
f5372251 6154 DP(NETIF_MSG_LINK, "Phy address = 0x%x\n", params->phy_addr);
ea4e040a
YR		 6155
6156 bnx2x_link_initialize(params, vars);
57963ed9 6157 msleep(30);
ea4e040a
YR		 6158 bnx2x_link_int_enable(params);
6159 }
6160 return 0;
6161}
6162
589abe3a
EG		 6163static void bnx2x_8726_reset_phy(struct bnx2x *bp, u8 port, u8 ext_phy_addr)
6164{
6165 DP(NETIF_MSG_LINK, "bnx2x_8726_reset_phy port %d\n", port);
6166
6167 /* Set serial boot control for external load */
6168 bnx2x_cl45_write(bp, port,
6169 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726, ext_phy_addr,
6170 MDIO_PMA_DEVAD,
6171 MDIO_PMA_REG_GEN_CTRL, 0x0001);
589abe3a
EG		 6172}
6173
6174u8 bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
6175 u8 reset_ext_phy)
ea4e040a 6176{
ea4e040a
YR		 6177 struct bnx2x *bp = params->bp;
6178 u32 ext_phy_config = params->ext_phy_config;
ea4e040a
YR		 6179 u8 port = params->port;
6180 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
4d295db0
EG		 6181 u32 val = REG_RD(bp, params->shmem_base +
6182 offsetof(struct shmem_region, dev_info.
6183 port_feature_config[params->port].
6184 config));
d5cb9e99 6185 DP(NETIF_MSG_LINK, "Resetting the link of port %d\n", port);
ea4e040a 6186 /* disable attentions */
ea4e040a
YR		 6187 vars->link_status = 0;
6188 bnx2x_update_mng(params, vars->link_status);
6189 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
6190 (NIG_MASK_XGXS0_LINK_STATUS |
6191 NIG_MASK_XGXS0_LINK10G |
6192 NIG_MASK_SERDES0_LINK_STATUS |
6193 NIG_MASK_MI_INT));
6194
6195 /* activate nig drain */
6196 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
6197
6198 /* disable nig egress interface */
6199 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0);
6200 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0);
6201
6202 /* Stop BigMac rx */
6203 bnx2x_bmac_rx_disable(bp, port);
6204
6205 /* disable emac */
6206 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
6207
6208 msleep(10);
6209 /* The PHY reset is controled by GPIO 1
6210 * Hold it as vars low
6211 */
6212 /* clear link led */
7846e471 6213 bnx2x_set_led(params, LED_MODE_OFF, 0);
589abe3a
EG		 6214 if (reset_ext_phy) {
6215 switch (ext_phy_type) {
6216 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
6217 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
6218 break;
4d295db0
EG		 6219
6220 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
6221 {
6222
6223 /* Disable Transmitter */
659bc5c4
EG		 6224 u8 ext_phy_addr =
6225 XGXS_EXT_PHY_ADDR(params->ext_phy_config);
4d295db0
EG		 6226 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
6227 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
6228 bnx2x_sfp_set_transmitter(bp, port,
6229 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
6230 ext_phy_addr, 0);
6231 break;
6232 }
589abe3a
EG		 6233 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
6234 DP(NETIF_MSG_LINK, "Setting 8073 port %d into "
6235 "low power mode\n",
6236 port);
6237 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
6238 MISC_REGISTERS_GPIO_OUTPUT_LOW,
6239 port);
6240 break;
6241 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
6242 {
659bc5c4
EG		 6243 u8 ext_phy_addr =
6244 XGXS_EXT_PHY_ADDR(params->ext_phy_config);
589abe3a
EG		 6245 /* Set soft reset */
6246 bnx2x_8726_reset_phy(bp, params->port, ext_phy_addr);
6247 break;
6248 }
6249 default:
ea4e040a 6250 /* HW reset */
ea4e040a 6251 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
17de50b7
EG		 6252 MISC_REGISTERS_GPIO_OUTPUT_LOW,
6253 port);
ea4e040a 6254 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
17de50b7
EG		 6255 MISC_REGISTERS_GPIO_OUTPUT_LOW,
6256 port);
ea4e040a 6257 DP(NETIF_MSG_LINK, "reset external PHY\n");
ea4e040a
YR		 6258 }
6259 }
6260 /* reset the SerDes/XGXS */
6261 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR,
6262 (0x1ff << (port*16)));
6263
6264 /* reset BigMac */
6265 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
6266 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
6267
6268 /* disable nig ingress interface */
6269 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0);
6270 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0);
6271 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0);
6272 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0);
6273 vars->link_up = 0;
6274 return 0;
6275}
6276
57963ed9
YR		 6277static u8 bnx2x_update_link_down(struct link_params *params,
6278 struct link_vars *vars)
6279{
6280 struct bnx2x *bp = params->bp;
6281 u8 port = params->port;
ab6ad5a4 6282
57963ed9 6283 DP(NETIF_MSG_LINK, "Port %x: Link is down\n", port);
7846e471 6284 bnx2x_set_led(params, LED_MODE_OFF, 0);
57963ed9
YR		 6285
6286 /* indicate no mac active */
6287 vars->mac_type = MAC_TYPE_NONE;
6288
6289 /* update shared memory */
6290 vars->link_status = 0;
6291 vars->line_speed = 0;
6292 bnx2x_update_mng(params, vars->link_status);
6293
6294 /* activate nig drain */
6295 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
6296
6c55c3cd
EG		 6297 /* disable emac */
6298 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
6299
6300 msleep(10);
6301
57963ed9
YR		 6302 /* reset BigMac */
6303 bnx2x_bmac_rx_disable(bp, params->port);
6304 REG_WR(bp, GRCBASE_MISC +
6305 MISC_REGISTERS_RESET_REG_2_CLEAR,
6306 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
6307 return 0;
6308}
6309
6310static u8 bnx2x_update_link_up(struct link_params *params,
6311 struct link_vars *vars,
6312 u8 link_10g, u32 gp_status)
6313{
6314 struct bnx2x *bp = params->bp;
6315 u8 port = params->port;
6316 u8 rc = 0;
ab6ad5a4 6317
57963ed9
YR		 6318 vars->link_status |= LINK_STATUS_LINK_UP;
6319 if (link_10g) {
6320 bnx2x_bmac_enable(params, vars, 0);
7846e471 6321 bnx2x_set_led(params, LED_MODE_OPER, SPEED_10000);
57963ed9
YR		 6322 } else {
6323 bnx2x_emac_enable(params, vars, 0);
6324 rc = bnx2x_emac_program(params, vars->line_speed,
6325 vars->duplex);
6326
6327 /* AN complete? */
6328 if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE) {
6329 if (!(vars->phy_flags &
6330 PHY_SGMII_FLAG))
ed8680a7 6331 bnx2x_set_gmii_tx_driver(params);
57963ed9
YR		 6332 }
6333 }
6334
6335 /* PBF - link up */
6336 rc |= bnx2x_pbf_update(params, vars->flow_ctrl,
6337 vars->line_speed);
6338
6339 /* disable drain */
6340 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0);
6341
6342 /* update shared memory */
6343 bnx2x_update_mng(params, vars->link_status);
6c55c3cd 6344 msleep(20);
57963ed9
YR		 6345 return rc;
6346}
ea4e040a
YR		 6347/* This function should called upon link interrupt */
6348/* In case vars->link_up, driver needs to
6349 1. Update the pbf
6350 2. Disable drain
6351 3. Update the shared memory
6352 4. Indicate link up
6353 5. Set LEDs
6354 Otherwise,
6355 1. Update shared memory
6356 2. Reset BigMac
6357 3. Report link down
6358 4. Unset LEDs
6359*/
6360u8 bnx2x_link_update(struct link_params *params, struct link_vars *vars)
6361{
6362 struct bnx2x *bp = params->bp;
6363 u8 port = params->port;
ea4e040a 6364 u16 gp_status;
57963ed9
YR		 6365 u8 link_10g;
6366 u8 ext_phy_link_up, rc = 0;
6367 u32 ext_phy_type;
2f904460 6368 u8 is_mi_int = 0;
ea4e040a
YR		 6369
6370 DP(NETIF_MSG_LINK, "port %x, XGXS?%x, int_status 0x%x\n",
2f904460
EG		 6371 port, (vars->phy_flags & PHY_XGXS_FLAG),
6372 REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
ea4e040a 6373
2f904460
EG		 6374 is_mi_int = (u8)(REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT +
6375 port*0x18) > 0);
ea4e040a 6376 DP(NETIF_MSG_LINK, "int_mask 0x%x MI_INT %x, SERDES_LINK %x\n",
2f904460
EG		 6377 REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
6378 is_mi_int,
6379 REG_RD(bp,
6380 NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c));
ea4e040a
YR		 6381
6382 DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
6383 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
6384 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
6385
6c55c3cd
EG		 6386 /* disable emac */
6387 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
6388
57963ed9 6389 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
ea4e040a 6390
57963ed9 6391 /* Check external link change only for non-direct */
2f904460 6392 ext_phy_link_up = bnx2x_ext_phy_is_link_up(params, vars, is_mi_int);
57963ed9
YR		 6393
6394 /* Read gp_status */
6395 CL45_RD_OVER_CL22(bp, port, params->phy_addr,
6396 MDIO_REG_BANK_GP_STATUS,
6397 MDIO_GP_STATUS_TOP_AN_STATUS1,
6398 &gp_status);
ea4e040a 6399
2f904460
EG		 6400 rc = bnx2x_link_settings_status(params, vars, gp_status,
6401 ext_phy_link_up);
ea4e040a
YR		 6402 if (rc != 0)
6403 return rc;
6404
6405 /* anything 10 and over uses the bmac */
6406 link_10g = ((vars->line_speed == SPEED_10000) ||
6407 (vars->line_speed == SPEED_12000) ||
6408 (vars->line_speed == SPEED_12500) ||
6409 (vars->line_speed == SPEED_13000) ||
6410 (vars->line_speed == SPEED_15000) ||
6411 (vars->line_speed == SPEED_16000));
6412
2f904460 6413 bnx2x_link_int_ack(params, vars, link_10g, is_mi_int);
ea4e040a 6414
57963ed9
YR		 6415 /* In case external phy link is up, and internal link is down
6416 ( not initialized yet probably after link initialization, it needs
6417 to be initialized.
6418 Note that after link down-up as result of cable plug,
6419 the xgxs link would probably become up again without the need to
6420 initialize it*/
ea4e040a 6421
57963ed9
YR		 6422 if ((ext_phy_type != PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT) &&
6423 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705) &&
589abe3a 6424 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) &&
57963ed9 6425 (ext_phy_link_up && !vars->phy_link_up))
239d686d 6426 bnx2x_init_internal_phy(params, vars, 0);
ea4e040a 6427
57963ed9
YR		 6428 /* link is up only if both local phy and external phy are up */
6429 vars->link_up = (ext_phy_link_up && vars->phy_link_up);
ea4e040a 6430
57963ed9
YR		 6431 if (vars->link_up)
6432 rc = bnx2x_update_link_up(params, vars, link_10g, gp_status);
6433 else
6434 rc = bnx2x_update_link_down(params, vars);
ea4e040a
YR		 6435
6436 return rc;
6437}
6438
6bbca910
YR		 6439static u8 bnx2x_8073_common_init_phy(struct bnx2x *bp, u32 shmem_base)
6440{
6441 u8 ext_phy_addr[PORT_MAX];
6442 u16 val;
6443 s8 port;
6444
6445 /* PART1 - Reset both phys */
6446 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
6447 /* Extract the ext phy address for the port */
6448 u32 ext_phy_config = REG_RD(bp, shmem_base +
6449 offsetof(struct shmem_region,
6450 dev_info.port_hw_config[port].external_phy_config));
6451
6452 /* disable attentions */
6453 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
6454 (NIG_MASK_XGXS0_LINK_STATUS |
6455 NIG_MASK_XGXS0_LINK10G |
6456 NIG_MASK_SERDES0_LINK_STATUS |
6457 NIG_MASK_MI_INT));
6458
659bc5c4 6459 ext_phy_addr[port] = XGXS_EXT_PHY_ADDR(ext_phy_config);
6bbca910
YR		 6460
6461 /* Need to take the phy out of low power mode in order
6462 to write to access its registers */
6463 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
6464 MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
6465
6466 /* Reset the phy */
6467 bnx2x_cl45_write(bp, port,
6468 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
6469 ext_phy_addr[port],
6470 MDIO_PMA_DEVAD,
6471 MDIO_PMA_REG_CTRL,
6472 1<<15);
6473 }
6474
6475 /* Add delay of 150ms after reset */
6476 msleep(150);
6477
6478 /* PART2 - Download firmware to both phys */
6479 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
6480 u16 fw_ver1;
6481
6482 bnx2x_bcm8073_external_rom_boot(bp, port,
a35da8db 6483 ext_phy_addr[port], shmem_base);
6bbca910
YR		 6484
6485 bnx2x_cl45_read(bp, port, PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
6486 ext_phy_addr[port],
6487 MDIO_PMA_DEVAD,
6488 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
16b311cc 6489 if (fw_ver1 == 0 || fw_ver1 == 0x4321) {
6bbca910 6490 DP(NETIF_MSG_LINK,
16b311cc
EG		 6491 "bnx2x_8073_common_init_phy port %x:"
6492 "Download failed. fw version = 0x%x\n",
6493 port, fw_ver1);
6bbca910
YR		 6494 return -EINVAL;
6495 }
6496
6497 /* Only set bit 10 = 1 (Tx power down) */
6498 bnx2x_cl45_read(bp, port,
6499 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
6500 ext_phy_addr[port],
6501 MDIO_PMA_DEVAD,
6502 MDIO_PMA_REG_TX_POWER_DOWN, &val);
6503
6504 /* Phase1 of TX_POWER_DOWN reset */
6505 bnx2x_cl45_write(bp, port,
6506 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
6507 ext_phy_addr[port],
6508 MDIO_PMA_DEVAD,
6509 MDIO_PMA_REG_TX_POWER_DOWN,
6510 (val | 1<<10));
6511 }
6512
6513 /* Toggle Transmitter: Power down and then up with 600ms
6514 delay between */
6515 msleep(600);
6516
6517 /* PART3 - complete TX_POWER_DOWN process, and set GPIO2 back to low */
6518 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
f5372251 6519 /* Phase2 of POWER_DOWN_RESET */
6bbca910
YR		 6520 /* Release bit 10 (Release Tx power down) */
6521 bnx2x_cl45_read(bp, port,
6522 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
6523 ext_phy_addr[port],
6524 MDIO_PMA_DEVAD,
6525 MDIO_PMA_REG_TX_POWER_DOWN, &val);
6526
6527 bnx2x_cl45_write(bp, port,
6528 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
6529 ext_phy_addr[port],
6530 MDIO_PMA_DEVAD,
6531 MDIO_PMA_REG_TX_POWER_DOWN, (val & (~(1<<10))));
6532 msleep(15);
6533
6534 /* Read modify write the SPI-ROM version select register */
6535 bnx2x_cl45_read(bp, port,
6536 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
6537 ext_phy_addr[port],
6538 MDIO_PMA_DEVAD,
6539 MDIO_PMA_REG_EDC_FFE_MAIN, &val);
6540 bnx2x_cl45_write(bp, port,
6541 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
6542 ext_phy_addr[port],
6543 MDIO_PMA_DEVAD,
6544 MDIO_PMA_REG_EDC_FFE_MAIN, (val | (1<<12)));
6545
6546 /* set GPIO2 back to LOW */
6547 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
6548 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
6549 }
6550 return 0;
6551
6552}
6553
4d295db0
EG		 6554static u8 bnx2x_8727_common_init_phy(struct bnx2x *bp, u32 shmem_base)
6555{
6556 u8 ext_phy_addr[PORT_MAX];
bc7f0a05 6557 s8 port, first_port, i;
4d295db0
EG		 6558 u32 swap_val, swap_override;
6559 DP(NETIF_MSG_LINK, "Executing BCM8727 common init\n");
6560 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
6561 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
6562
f57a6025 6563 bnx2x_ext_phy_hw_reset(bp, 1 ^ (swap_val && swap_override));
4d295db0
EG		 6564 msleep(5);
6565
bc7f0a05
EG		 6566 if (swap_val && swap_override)
6567 first_port = PORT_0;
6568 else
6569 first_port = PORT_1;
6570
4d295db0 6571 /* PART1 - Reset both phys */
bc7f0a05 6572 for (i = 0, port = first_port; i < PORT_MAX; i++, port = !port) {
4d295db0
EG		 6573 /* Extract the ext phy address for the port */
6574 u32 ext_phy_config = REG_RD(bp, shmem_base +
6575 offsetof(struct shmem_region,
6576 dev_info.port_hw_config[port].external_phy_config));
6577
6578 /* disable attentions */
6579 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
6580 (NIG_MASK_XGXS0_LINK_STATUS |
6581 NIG_MASK_XGXS0_LINK10G |
6582 NIG_MASK_SERDES0_LINK_STATUS |
6583 NIG_MASK_MI_INT));
6584
659bc5c4 6585 ext_phy_addr[port] = XGXS_EXT_PHY_ADDR(ext_phy_config);
4d295db0
EG		 6586
6587 /* Reset the phy */
6588 bnx2x_cl45_write(bp, port,
6589 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
6590 ext_phy_addr[port],
6591 MDIO_PMA_DEVAD,
6592 MDIO_PMA_REG_CTRL,
6593 1<<15);
6594 }
6595
6596 /* Add delay of 150ms after reset */
6597 msleep(150);
6598
6599 /* PART2 - Download firmware to both phys */
bc7f0a05 6600 for (i = 0, port = first_port; i < PORT_MAX; i++, port = !port) {
4d295db0
EG		 6601 u16 fw_ver1;
6602
6603 bnx2x_bcm8727_external_rom_boot(bp, port,
6604 ext_phy_addr[port], shmem_base);
6605
6606 bnx2x_cl45_read(bp, port, PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
6607 ext_phy_addr[port],
6608 MDIO_PMA_DEVAD,
6609 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
6610 if (fw_ver1 == 0 || fw_ver1 == 0x4321) {
6611 DP(NETIF_MSG_LINK,
bc7f0a05 6612 "bnx2x_8727_common_init_phy port %x:"
4d295db0
EG		 6613 "Download failed. fw version = 0x%x\n",
6614 port, fw_ver1);
6615 return -EINVAL;
6616 }
4d295db0
EG		 6617 }
6618
4d295db0
EG		 6619 return 0;
6620}
6621
589abe3a
EG		 6622
6623static u8 bnx2x_8726_common_init_phy(struct bnx2x *bp, u32 shmem_base)
6624{
6625 u8 ext_phy_addr;
6626 u32 val;
6627 s8 port;
ab6ad5a4 6628
589abe3a
EG		 6629 /* Use port1 because of the static port-swap */
6630 /* Enable the module detection interrupt */
6631 val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN);
6632 val |= ((1<<MISC_REGISTERS_GPIO_3)|
6633 (1<<(MISC_REGISTERS_GPIO_3 + MISC_REGISTERS_GPIO_PORT_SHIFT)));
6634 REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val);
6635
f57a6025 6636 bnx2x_ext_phy_hw_reset(bp, 1);
589abe3a
EG		 6637 msleep(5);
6638 for (port = 0; port < PORT_MAX; port++) {
6639 /* Extract the ext phy address for the port */
6640 u32 ext_phy_config = REG_RD(bp, shmem_base +
6641 offsetof(struct shmem_region,
6642 dev_info.port_hw_config[port].external_phy_config));
6643
659bc5c4 6644 ext_phy_addr = XGXS_EXT_PHY_ADDR(ext_phy_config);
589abe3a
EG		 6645 DP(NETIF_MSG_LINK, "8726_common_init : ext_phy_addr = 0x%x\n",
6646 ext_phy_addr);
6647
6648 bnx2x_8726_reset_phy(bp, port, ext_phy_addr);
6649
6650 /* Set fault module detected LED on */
6651 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
6652 MISC_REGISTERS_GPIO_HIGH,
6653 port);
6654 }
6655
6656 return 0;
6657}
6658
6bbca910
YR		 6659u8 bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base)
6660{
6661 u8 rc = 0;
6662 u32 ext_phy_type;
6663
f5372251 6664 DP(NETIF_MSG_LINK, "Begin common phy init\n");
6bbca910
YR		 6665
6666 /* Read the ext_phy_type for arbitrary port(0) */
6667 ext_phy_type = XGXS_EXT_PHY_TYPE(
6668 REG_RD(bp, shmem_base +
6669 offsetof(struct shmem_region,
6670 dev_info.port_hw_config[0].external_phy_config)));
6671
6672 switch (ext_phy_type) {
6673 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
6674 {
6675 rc = bnx2x_8073_common_init_phy(bp, shmem_base);
6676 break;
6677 }
4d295db0
EG		 6678
6679 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
6680 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
6681 rc = bnx2x_8727_common_init_phy(bp, shmem_base);
6682 break;
6683
589abe3a
EG		 6684 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
6685 /* GPIO1 affects both ports, so there's need to pull
6686 it for single port alone */
6687 rc = bnx2x_8726_common_init_phy(bp, shmem_base);
6688
6689 break;
6bbca910
YR		 6690 default:
6691 DP(NETIF_MSG_LINK,
6692 "bnx2x_common_init_phy: ext_phy 0x%x not required\n",
6693 ext_phy_type);
6694 break;
6695 }
6696
6697 return rc;
6698}
6699
f57a6025 6700void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, u8 port, u8 phy_addr)
ea4e040a
YR		 6701{
6702 u16 val, cnt;
6703
6704 bnx2x_cl45_read(bp, port,
6705 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
6706 phy_addr,
6707 MDIO_PMA_DEVAD,
6708 MDIO_PMA_REG_7101_RESET, &val);
6709
6710 for (cnt = 0; cnt < 10; cnt++) {
6711 msleep(50);
6712 /* Writes a self-clearing reset */
6713 bnx2x_cl45_write(bp, port,
6714 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
6715 phy_addr,
6716 MDIO_PMA_DEVAD,
6717 MDIO_PMA_REG_7101_RESET,
6718 (val | (1<<15)));
6719 /* Wait for clear */
6720 bnx2x_cl45_read(bp, port,
6721 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
6722 phy_addr,
6723 MDIO_PMA_DEVAD,
6724 MDIO_PMA_REG_7101_RESET, &val);
6725
6726 if ((val & (1<<15)) == 0)
6727 break;
6728 }
6729}
Linux kernel - Deliverables
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