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bnx2x: Missing smp_wmb for statistics state machine
[deliverable/linux.git] / drivers / net / bnx2x_link.c
CommitLineData
d05c26ce 1/* Copyright 2008-2009 Broadcom Corporation
ea4e040a
YR		 2 *
3 * Unless you and Broadcom execute a separate written software license
4 * agreement governing use of this software, this software is licensed to you
5 * under the terms of the GNU General Public License version 2, available
6 * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
7 *
8 * Notwithstanding the above, under no circumstances may you combine this
9 * software in any way with any other Broadcom software provided under a
10 * license other than the GPL, without Broadcom's express prior written
11 * consent.
12 *
13 * Written by Yaniv Rosner
14 *
15 */
16
17#include <linux/kernel.h>
18#include <linux/errno.h>
19#include <linux/pci.h>
20#include <linux/netdevice.h>
21#include <linux/delay.h>
22#include <linux/ethtool.h>
23#include <linux/mutex.h>
ea4e040a 24
ea4e040a
YR		 25#include "bnx2x.h"
26
27/********************************************************/
3196a88a 28#define ETH_HLEN 14
ea4e040a
YR		 29#define ETH_OVREHEAD (ETH_HLEN + 8)/* 8 for CRC + VLAN*/
30#define ETH_MIN_PACKET_SIZE 60
31#define ETH_MAX_PACKET_SIZE 1500
32#define ETH_MAX_JUMBO_PACKET_SIZE 9600
33#define MDIO_ACCESS_TIMEOUT 1000
34#define BMAC_CONTROL_RX_ENABLE 2
ea4e040a
YR		 35
36/***********************************************************/
3196a88a 37/* Shortcut definitions */
ea4e040a
YR		 38/***********************************************************/
39
2f904460
EG		 40#define NIG_LATCH_BC_ENABLE_MI_INT 0
41
42#define NIG_STATUS_EMAC0_MI_INT \
43 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT
ea4e040a
YR		 44#define NIG_STATUS_XGXS0_LINK10G \
45 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G
46#define NIG_STATUS_XGXS0_LINK_STATUS \
47 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS
48#define NIG_STATUS_XGXS0_LINK_STATUS_SIZE \
49 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE
50#define NIG_STATUS_SERDES0_LINK_STATUS \
51 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS
52#define NIG_MASK_MI_INT \
53 NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT
54#define NIG_MASK_XGXS0_LINK10G \
55 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G
56#define NIG_MASK_XGXS0_LINK_STATUS \
57 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS
58#define NIG_MASK_SERDES0_LINK_STATUS \
59 NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS
60
61#define MDIO_AN_CL73_OR_37_COMPLETE \
62 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \
63 MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE)
64
65#define XGXS_RESET_BITS \
66 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW | \
67 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ | \
68 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN | \
69 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \
70 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB)
71
72#define SERDES_RESET_BITS \
73 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \
74 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ | \
75 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN | \
76 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD)
77
78#define AUTONEG_CL37 SHARED_HW_CFG_AN_ENABLE_CL37
79#define AUTONEG_CL73 SHARED_HW_CFG_AN_ENABLE_CL73
3196a88a
EG		 80#define AUTONEG_BAM SHARED_HW_CFG_AN_ENABLE_BAM
81#define AUTONEG_PARALLEL \
ea4e040a 82 SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION
3196a88a 83#define AUTONEG_SGMII_FIBER_AUTODET \
ea4e040a 84 SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT
3196a88a 85#define AUTONEG_REMOTE_PHY SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY
ea4e040a
YR		 86
87#define GP_STATUS_PAUSE_RSOLUTION_TXSIDE \
88 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE
89#define GP_STATUS_PAUSE_RSOLUTION_RXSIDE \
90 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE
91#define GP_STATUS_SPEED_MASK \
92 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK
93#define GP_STATUS_10M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M
94#define GP_STATUS_100M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M
95#define GP_STATUS_1G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G
96#define GP_STATUS_2_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G
97#define GP_STATUS_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G
98#define GP_STATUS_6G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G
99#define GP_STATUS_10G_HIG \
100 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG
101#define GP_STATUS_10G_CX4 \
102 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4
103#define GP_STATUS_12G_HIG \
104 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG
105#define GP_STATUS_12_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G
106#define GP_STATUS_13G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G
107#define GP_STATUS_15G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G
108#define GP_STATUS_16G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G
109#define GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX
110#define GP_STATUS_10G_KX4 \
111 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4
112
113#define LINK_10THD LINK_STATUS_SPEED_AND_DUPLEX_10THD
114#define LINK_10TFD LINK_STATUS_SPEED_AND_DUPLEX_10TFD
115#define LINK_100TXHD LINK_STATUS_SPEED_AND_DUPLEX_100TXHD
116#define LINK_100T4 LINK_STATUS_SPEED_AND_DUPLEX_100T4
117#define LINK_100TXFD LINK_STATUS_SPEED_AND_DUPLEX_100TXFD
118#define LINK_1000THD LINK_STATUS_SPEED_AND_DUPLEX_1000THD
119#define LINK_1000TFD LINK_STATUS_SPEED_AND_DUPLEX_1000TFD
120#define LINK_1000XFD LINK_STATUS_SPEED_AND_DUPLEX_1000XFD
121#define LINK_2500THD LINK_STATUS_SPEED_AND_DUPLEX_2500THD
122#define LINK_2500TFD LINK_STATUS_SPEED_AND_DUPLEX_2500TFD
123#define LINK_2500XFD LINK_STATUS_SPEED_AND_DUPLEX_2500XFD
124#define LINK_10GTFD LINK_STATUS_SPEED_AND_DUPLEX_10GTFD
125#define LINK_10GXFD LINK_STATUS_SPEED_AND_DUPLEX_10GXFD
126#define LINK_12GTFD LINK_STATUS_SPEED_AND_DUPLEX_12GTFD
127#define LINK_12GXFD LINK_STATUS_SPEED_AND_DUPLEX_12GXFD
128#define LINK_12_5GTFD LINK_STATUS_SPEED_AND_DUPLEX_12_5GTFD
129#define LINK_12_5GXFD LINK_STATUS_SPEED_AND_DUPLEX_12_5GXFD
130#define LINK_13GTFD LINK_STATUS_SPEED_AND_DUPLEX_13GTFD
131#define LINK_13GXFD LINK_STATUS_SPEED_AND_DUPLEX_13GXFD
132#define LINK_15GTFD LINK_STATUS_SPEED_AND_DUPLEX_15GTFD
133#define LINK_15GXFD LINK_STATUS_SPEED_AND_DUPLEX_15GXFD
134#define LINK_16GTFD LINK_STATUS_SPEED_AND_DUPLEX_16GTFD
135#define LINK_16GXFD LINK_STATUS_SPEED_AND_DUPLEX_16GXFD
136
137#define PHY_XGXS_FLAG 0x1
138#define PHY_SGMII_FLAG 0x2
139#define PHY_SERDES_FLAG 0x4
140
589abe3a
EG		 141/* */
142#define SFP_EEPROM_CON_TYPE_ADDR 0x2
143 #define SFP_EEPROM_CON_TYPE_VAL_LC 0x7
144 #define SFP_EEPROM_CON_TYPE_VAL_COPPER 0x21
145
4d295db0
EG		 146
147#define SFP_EEPROM_COMP_CODE_ADDR 0x3
148 #define SFP_EEPROM_COMP_CODE_SR_MASK (1<<4)
149 #define SFP_EEPROM_COMP_CODE_LR_MASK (1<<5)
150 #define SFP_EEPROM_COMP_CODE_LRM_MASK (1<<6)
151
589abe3a
EG		 152#define SFP_EEPROM_FC_TX_TECH_ADDR 0x8
153 #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4
154 #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE 0x8
4d295db0 155
589abe3a
EG		 156#define SFP_EEPROM_OPTIONS_ADDR 0x40
157 #define SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1
158#define SFP_EEPROM_OPTIONS_SIZE 2
159
4d295db0
EG		 160#define EDC_MODE_LINEAR 0x0022
161#define EDC_MODE_LIMITING 0x0044
162#define EDC_MODE_PASSIVE_DAC 0x0055
163
164
589abe3a 165
ea4e040a
YR		 166/**********************************************************/
167/* INTERFACE */
168/**********************************************************/
169#define CL45_WR_OVER_CL22(_bp, _port, _phy_addr, _bank, _addr, _val) \
170 bnx2x_cl45_write(_bp, _port, 0, _phy_addr, \
171 DEFAULT_PHY_DEV_ADDR, \
172 (_bank + (_addr & 0xf)), \
173 _val)
174
175#define CL45_RD_OVER_CL22(_bp, _port, _phy_addr, _bank, _addr, _val) \
176 bnx2x_cl45_read(_bp, _port, 0, _phy_addr, \
177 DEFAULT_PHY_DEV_ADDR, \
178 (_bank + (_addr & 0xf)), \
179 _val)
180
c1b73990 181static void bnx2x_set_serdes_access(struct link_params *params)
ea4e040a
YR		 182{
183 struct bnx2x *bp = params->bp;
c1b73990
EG		 184 u32 emac_base = (params->port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
185 /* Set Clause 22 */
186 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + params->port*0x10, 1);
187 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000);
188 udelay(500);
189 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f);
190 udelay(500);
191 /* Set Clause 45 */
192 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + params->port*0x10, 0);
193}
194static void bnx2x_set_phy_mdio(struct link_params *params, u8 phy_flags)
195{
196 struct bnx2x *bp = params->bp;
197 if (phy_flags & PHY_XGXS_FLAG) {
198 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_ST +
199 params->port*0x18, 0);
200 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + params->port*0x18,
201 DEFAULT_PHY_DEV_ADDR);
202 } else {
203 bnx2x_set_serdes_access(params);
204
205 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_DEVAD +
206 params->port*0x10,
207 DEFAULT_PHY_DEV_ADDR);
208 }
ea4e040a
YR		 209}
210
211static u32 bnx2x_bits_en(struct bnx2x *bp, u32 reg, u32 bits)
212{
213 u32 val = REG_RD(bp, reg);
214
215 val |= bits;
216 REG_WR(bp, reg, val);
217 return val;
218}
219
220static u32 bnx2x_bits_dis(struct bnx2x *bp, u32 reg, u32 bits)
221{
222 u32 val = REG_RD(bp, reg);
223
224 val &= ~bits;
225 REG_WR(bp, reg, val);
226 return val;
227}
228
229static void bnx2x_emac_init(struct link_params *params,
230 struct link_vars *vars)
231{
232 /* reset and unreset the emac core */
233 struct bnx2x *bp = params->bp;
234 u8 port = params->port;
235 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
236 u32 val;
237 u16 timeout;
238
239 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
240 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
241 udelay(5);
242 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
243 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
244
245 /* init emac - use read-modify-write */
246 /* self clear reset */
247 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
3196a88a 248 EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_RESET));
ea4e040a
YR		 249
250 timeout = 200;
3196a88a 251 do {
ea4e040a
YR		 252 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
253 DP(NETIF_MSG_LINK, "EMAC reset reg is %u\n", val);
254 if (!timeout) {
255 DP(NETIF_MSG_LINK, "EMAC timeout!\n");
256 return;
257 }
258 timeout--;
3196a88a 259 } while (val & EMAC_MODE_RESET);
ea4e040a
YR		 260
261 /* Set mac address */
262 val = ((params->mac_addr[0] << 8) |
263 params->mac_addr[1]);
3196a88a 264 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH, val);
ea4e040a
YR		 265
266 val = ((params->mac_addr[2] << 24) |
267 (params->mac_addr[3] << 16) |
268 (params->mac_addr[4] << 8) |
269 params->mac_addr[5]);
3196a88a 270 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + 4, val);
ea4e040a
YR		 271}
272
273static u8 bnx2x_emac_enable(struct link_params *params,
274 struct link_vars *vars, u8 lb)
275{
276 struct bnx2x *bp = params->bp;
277 u8 port = params->port;
278 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
279 u32 val;
280
281 DP(NETIF_MSG_LINK, "enabling EMAC\n");
282
283 /* enable emac and not bmac */
284 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 1);
285
286 /* for paladium */
287 if (CHIP_REV_IS_EMUL(bp)) {
288 /* Use lane 1 (of lanes 0-3) */
289 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 1);
290 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL +
291 port*4, 1);
292 }
293 /* for fpga */
294 else
295
296 if (CHIP_REV_IS_FPGA(bp)) {
297 /* Use lane 1 (of lanes 0-3) */
298 DP(NETIF_MSG_LINK, "bnx2x_emac_enable: Setting FPGA\n");
299
300 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 1);
301 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4,
302 0);
303 } else
304 /* ASIC */
305 if (vars->phy_flags & PHY_XGXS_FLAG) {
306 u32 ser_lane = ((params->lane_config &
307 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
308 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
309
310 DP(NETIF_MSG_LINK, "XGXS\n");
311 /* select the master lanes (out of 0-3) */
312 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 +
313 port*4, ser_lane);
314 /* select XGXS */
315 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL +
316 port*4, 1);
317
318 } else { /* SerDes */
319 DP(NETIF_MSG_LINK, "SerDes\n");
320 /* select SerDes */
321 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL +
322 port*4, 0);
323 }
324
811a2f2d
EG		 325 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
326 EMAC_RX_MODE_RESET);
327 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
328 EMAC_TX_MODE_RESET);
ea4e040a
YR		 329
330 if (CHIP_REV_IS_SLOW(bp)) {
331 /* config GMII mode */
332 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
3196a88a 333 EMAC_WR(bp, EMAC_REG_EMAC_MODE,
ea4e040a
YR		 334 (val | EMAC_MODE_PORT_GMII));
335 } else { /* ASIC */
336 /* pause enable/disable */
337 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
338 EMAC_RX_MODE_FLOW_EN);
c0700f90 339 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
ea4e040a
YR		 340 bnx2x_bits_en(bp, emac_base +
341 EMAC_REG_EMAC_RX_MODE,
342 EMAC_RX_MODE_FLOW_EN);
343
344 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
8c99e7b0
YR		 345 (EMAC_TX_MODE_EXT_PAUSE_EN |
346 EMAC_TX_MODE_FLOW_EN));
c0700f90 347 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
ea4e040a
YR		 348 bnx2x_bits_en(bp, emac_base +
349 EMAC_REG_EMAC_TX_MODE,
8c99e7b0
YR		 350 (EMAC_TX_MODE_EXT_PAUSE_EN |
351 EMAC_TX_MODE_FLOW_EN));
ea4e040a
YR		 352 }
353
354 /* KEEP_VLAN_TAG, promiscuous */
355 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE);
356 val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS;
3196a88a 357 EMAC_WR(bp, EMAC_REG_EMAC_RX_MODE, val);
ea4e040a
YR		 358
359 /* Set Loopback */
360 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
361 if (lb)
362 val |= 0x810;
363 else
364 val &= ~0x810;
3196a88a 365 EMAC_WR(bp, EMAC_REG_EMAC_MODE, val);
ea4e040a 366
6c55c3cd
EG		 367 /* enable emac */
368 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 1);
369
ea4e040a 370 /* enable emac for jumbo packets */
3196a88a 371 EMAC_WR(bp, EMAC_REG_EMAC_RX_MTU_SIZE,
ea4e040a
YR		 372 (EMAC_RX_MTU_SIZE_JUMBO_ENA |
373 (ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD)));
374
375 /* strip CRC */
376 REG_WR(bp, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port*4, 0x1);
377
378 /* disable the NIG in/out to the bmac */
379 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x0);
380 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, 0x0);
381 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x0);
382
383 /* enable the NIG in/out to the emac */
384 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x1);
385 val = 0;
c0700f90 386 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
ea4e040a
YR		 387 val = 1;
388
389 REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, val);
390 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x1);
391
392 if (CHIP_REV_IS_EMUL(bp)) {
393 /* take the BigMac out of reset */
394 REG_WR(bp,
395 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
396 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
397
398 /* enable access for bmac registers */
399 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);
6f65497b
EG		 400 } else
401 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x0);
ea4e040a
YR		 402
403 vars->mac_type = MAC_TYPE_EMAC;
404 return 0;
405}
406
407
408
409static u8 bnx2x_bmac_enable(struct link_params *params, struct link_vars *vars,
410 u8 is_lb)
411{
412 struct bnx2x *bp = params->bp;
413 u8 port = params->port;
414 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
415 NIG_REG_INGRESS_BMAC0_MEM;
416 u32 wb_data[2];
417 u32 val;
418
419 DP(NETIF_MSG_LINK, "Enabling BigMAC\n");
420 /* reset and unreset the BigMac */
421 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
422 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
423 msleep(1);
424
425 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
426 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
427
428 /* enable access for bmac registers */
429 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);
430
431 /* XGXS control */
432 wb_data[0] = 0x3c;
433 wb_data[1] = 0;
434 REG_WR_DMAE(bp, bmac_addr +
435 BIGMAC_REGISTER_BMAC_XGXS_CONTROL,
436 wb_data, 2);
437
438 /* tx MAC SA */
439 wb_data[0] = ((params->mac_addr[2] << 24) |
440 (params->mac_addr[3] << 16) |
441 (params->mac_addr[4] << 8) |
442 params->mac_addr[5]);
443 wb_data[1] = ((params->mac_addr[0] << 8) |
444 params->mac_addr[1]);
445 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR,
446 wb_data, 2);
447
448 /* tx control */
449 val = 0xc0;
c0700f90 450 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
ea4e040a
YR		 451 val |= 0x800000;
452 wb_data[0] = val;
453 wb_data[1] = 0;
454 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_CONTROL,
455 wb_data, 2);
456
457 /* mac control */
458 val = 0x3;
459 if (is_lb) {
460 val |= 0x4;
461 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
462 }
463 wb_data[0] = val;
464 wb_data[1] = 0;
465 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL,
466 wb_data, 2);
467
468
469 /* set rx mtu */
470 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
471 wb_data[1] = 0;
472 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE,
473 wb_data, 2);
474
475 /* rx control set to don't strip crc */
476 val = 0x14;
c0700f90 477 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
ea4e040a
YR		 478 val |= 0x20;
479 wb_data[0] = val;
480 wb_data[1] = 0;
481 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_CONTROL,
482 wb_data, 2);
483
484 /* set tx mtu */
485 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
486 wb_data[1] = 0;
487 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE,
488 wb_data, 2);
489
490 /* set cnt max size */
491 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
492 wb_data[1] = 0;
493 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE,
494 wb_data, 2);
495
496 /* configure safc */
497 wb_data[0] = 0x1000200;
498 wb_data[1] = 0;
499 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS,
500 wb_data, 2);
501 /* fix for emulation */
502 if (CHIP_REV_IS_EMUL(bp)) {
503 wb_data[0] = 0xf000;
504 wb_data[1] = 0;
505 REG_WR_DMAE(bp,
506 bmac_addr + BIGMAC_REGISTER_TX_PAUSE_THRESHOLD,
507 wb_data, 2);
508 }
509
510 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0x1);
511 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 0x0);
512 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 0x0);
513 val = 0;
c0700f90 514 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
ea4e040a
YR		 515 val = 1;
516 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, val);
517 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x0);
518 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x0);
519 REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, 0x0);
520 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x1);
521 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x1);
522
523 vars->mac_type = MAC_TYPE_BMAC;
524 return 0;
525}
526
527static void bnx2x_phy_deassert(struct link_params *params, u8 phy_flags)
528{
529 struct bnx2x *bp = params->bp;
530 u32 val;
531
532 if (phy_flags & PHY_XGXS_FLAG) {
533 DP(NETIF_MSG_LINK, "bnx2x_phy_deassert:XGXS\n");
534 val = XGXS_RESET_BITS;
535
536 } else { /* SerDes */
537 DP(NETIF_MSG_LINK, "bnx2x_phy_deassert:SerDes\n");
538 val = SERDES_RESET_BITS;
539 }
540
541 val = val << (params->port*16);
542
543 /* reset and unreset the SerDes/XGXS */
544 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR,
545 val);
546 udelay(500);
547 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET,
548 val);
c1b73990 549 bnx2x_set_phy_mdio(params, phy_flags);
ea4e040a
YR		 550}
551
552void bnx2x_link_status_update(struct link_params *params,
553 struct link_vars *vars)
554{
555 struct bnx2x *bp = params->bp;
556 u8 link_10g;
557 u8 port = params->port;
558
559 if (params->switch_cfg == SWITCH_CFG_1G)
560 vars->phy_flags = PHY_SERDES_FLAG;
561 else
562 vars->phy_flags = PHY_XGXS_FLAG;
563 vars->link_status = REG_RD(bp, params->shmem_base +
564 offsetof(struct shmem_region,
565 port_mb[port].link_status));
566
567 vars->link_up = (vars->link_status & LINK_STATUS_LINK_UP);
568
569 if (vars->link_up) {
570 DP(NETIF_MSG_LINK, "phy link up\n");
571
572 vars->phy_link_up = 1;
573 vars->duplex = DUPLEX_FULL;
574 switch (vars->link_status &
575 LINK_STATUS_SPEED_AND_DUPLEX_MASK) {
576 case LINK_10THD:
577 vars->duplex = DUPLEX_HALF;
578 /* fall thru */
579 case LINK_10TFD:
580 vars->line_speed = SPEED_10;
581 break;
582
583 case LINK_100TXHD:
584 vars->duplex = DUPLEX_HALF;
585 /* fall thru */
586 case LINK_100T4:
587 case LINK_100TXFD:
588 vars->line_speed = SPEED_100;
589 break;
590
591 case LINK_1000THD:
592 vars->duplex = DUPLEX_HALF;
593 /* fall thru */
594 case LINK_1000TFD:
595 vars->line_speed = SPEED_1000;
596 break;
597
598 case LINK_2500THD:
599 vars->duplex = DUPLEX_HALF;
600 /* fall thru */
601 case LINK_2500TFD:
602 vars->line_speed = SPEED_2500;
603 break;
604
605 case LINK_10GTFD:
606 vars->line_speed = SPEED_10000;
607 break;
608
609 case LINK_12GTFD:
610 vars->line_speed = SPEED_12000;
611 break;
612
613 case LINK_12_5GTFD:
614 vars->line_speed = SPEED_12500;
615 break;
616
617 case LINK_13GTFD:
618 vars->line_speed = SPEED_13000;
619 break;
620
621 case LINK_15GTFD:
622 vars->line_speed = SPEED_15000;
623 break;
624
625 case LINK_16GTFD:
626 vars->line_speed = SPEED_16000;
627 break;
628
629 default:
630 break;
631 }
632
633 if (vars->link_status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED)
c0700f90 634 vars->flow_ctrl |= BNX2X_FLOW_CTRL_TX;
ea4e040a 635 else
c0700f90 636 vars->flow_ctrl &= ~BNX2X_FLOW_CTRL_TX;
ea4e040a
YR		 637
638 if (vars->link_status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED)
c0700f90 639 vars->flow_ctrl |= BNX2X_FLOW_CTRL_RX;
ea4e040a 640 else
c0700f90 641 vars->flow_ctrl &= ~BNX2X_FLOW_CTRL_RX;
ea4e040a
YR		 642
643 if (vars->phy_flags & PHY_XGXS_FLAG) {
8c99e7b0
YR		 644 if (vars->line_speed &&
645 ((vars->line_speed == SPEED_10) ||
646 (vars->line_speed == SPEED_100))) {
ea4e040a
YR		 647 vars->phy_flags |= PHY_SGMII_FLAG;
648 } else {
649 vars->phy_flags &= ~PHY_SGMII_FLAG;
650 }
651 }
652
653 /* anything 10 and over uses the bmac */
654 link_10g = ((vars->line_speed == SPEED_10000) ||
655 (vars->line_speed == SPEED_12000) ||
656 (vars->line_speed == SPEED_12500) ||
657 (vars->line_speed == SPEED_13000) ||
658 (vars->line_speed == SPEED_15000) ||
659 (vars->line_speed == SPEED_16000));
660 if (link_10g)
661 vars->mac_type = MAC_TYPE_BMAC;
662 else
663 vars->mac_type = MAC_TYPE_EMAC;
664
665 } else { /* link down */
666 DP(NETIF_MSG_LINK, "phy link down\n");
667
668 vars->phy_link_up = 0;
669
670 vars->line_speed = 0;
671 vars->duplex = DUPLEX_FULL;
c0700f90 672 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
ea4e040a
YR		 673
674 /* indicate no mac active */
675 vars->mac_type = MAC_TYPE_NONE;
676 }
677
678 DP(NETIF_MSG_LINK, "link_status 0x%x phy_link_up %x\n",
679 vars->link_status, vars->phy_link_up);
680 DP(NETIF_MSG_LINK, "line_speed %x duplex %x flow_ctrl 0x%x\n",
681 vars->line_speed, vars->duplex, vars->flow_ctrl);
682}
683
684static void bnx2x_update_mng(struct link_params *params, u32 link_status)
685{
686 struct bnx2x *bp = params->bp;
687 REG_WR(bp, params->shmem_base +
688 offsetof(struct shmem_region,
689 port_mb[params->port].link_status),
690 link_status);
691}
692
693static void bnx2x_bmac_rx_disable(struct bnx2x *bp, u8 port)
694{
695 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
696 NIG_REG_INGRESS_BMAC0_MEM;
697 u32 wb_data[2];
3196a88a 698 u32 nig_bmac_enable = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4);
ea4e040a
YR		 699
700 /* Only if the bmac is out of reset */
701 if (REG_RD(bp, MISC_REG_RESET_REG_2) &
702 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port) &&
703 nig_bmac_enable) {
704
705 /* Clear Rx Enable bit in BMAC_CONTROL register */
706 REG_RD_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL,
707 wb_data, 2);
708 wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
709 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL,
710 wb_data, 2);
711
712 msleep(1);
713 }
714}
715
716static u8 bnx2x_pbf_update(struct link_params *params, u32 flow_ctrl,
717 u32 line_speed)
718{
719 struct bnx2x *bp = params->bp;
720 u8 port = params->port;
721 u32 init_crd, crd;
722 u32 count = 1000;
ea4e040a
YR		 723
724 /* disable port */
725 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1);
726
727 /* wait for init credit */
728 init_crd = REG_RD(bp, PBF_REG_P0_INIT_CRD + port*4);
729 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
730 DP(NETIF_MSG_LINK, "init_crd 0x%x crd 0x%x\n", init_crd, crd);
731
732 while ((init_crd != crd) && count) {
733 msleep(5);
734
735 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
736 count--;
737 }
738 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
739 if (init_crd != crd) {
740 DP(NETIF_MSG_LINK, "BUG! init_crd 0x%x != crd 0x%x\n",
741 init_crd, crd);
742 return -EINVAL;
743 }
744
c0700f90 745 if (flow_ctrl & BNX2X_FLOW_CTRL_RX ||
8c99e7b0
YR		 746 line_speed == SPEED_10 ||
747 line_speed == SPEED_100 ||
748 line_speed == SPEED_1000 ||
749 line_speed == SPEED_2500) {
750 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 1);
ea4e040a
YR		 751 /* update threshold */
752 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, 0);
753 /* update init credit */
8c99e7b0 754 init_crd = 778; /* (800-18-4) */
ea4e040a
YR		 755
756 } else {
757 u32 thresh = (ETH_MAX_JUMBO_PACKET_SIZE +
758 ETH_OVREHEAD)/16;
8c99e7b0 759 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
ea4e040a
YR		 760 /* update threshold */
761 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, thresh);
762 /* update init credit */
763 switch (line_speed) {
ea4e040a
YR		 764 case SPEED_10000:
765 init_crd = thresh + 553 - 22;
766 break;
767
768 case SPEED_12000:
769 init_crd = thresh + 664 - 22;
770 break;
771
772 case SPEED_13000:
773 init_crd = thresh + 742 - 22;
774 break;
775
776 case SPEED_16000:
777 init_crd = thresh + 778 - 22;
778 break;
779 default:
780 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
781 line_speed);
782 return -EINVAL;
783 break;
784 }
785 }
786 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, init_crd);
787 DP(NETIF_MSG_LINK, "PBF updated to speed %d credit %d\n",
788 line_speed, init_crd);
789
790 /* probe the credit changes */
791 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x1);
792 msleep(5);
793 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x0);
794
795 /* enable port */
796 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x0);
797 return 0;
798}
799
589abe3a 800static u32 bnx2x_get_emac_base(struct bnx2x *bp, u32 ext_phy_type, u8 port)
ea4e040a
YR		 801{
802 u32 emac_base;
803 switch (ext_phy_type) {
804 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
589abe3a 805 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
4d295db0 806 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
589abe3a
EG		 807 /* All MDC/MDIO is directed through single EMAC */
808 if (REG_RD(bp, NIG_REG_PORT_SWAP))
809 emac_base = GRCBASE_EMAC0;
810 else
811 emac_base = GRCBASE_EMAC1;
ea4e040a
YR		 812 break;
813 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
6378c025 814 emac_base = (port) ? GRCBASE_EMAC0 : GRCBASE_EMAC1;
ea4e040a
YR		 815 break;
816 default:
6378c025 817 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
ea4e040a
YR		 818 break;
819 }
820 return emac_base;
821
822}
823
824u8 bnx2x_cl45_write(struct bnx2x *bp, u8 port, u32 ext_phy_type,
825 u8 phy_addr, u8 devad, u16 reg, u16 val)
826{
827 u32 tmp, saved_mode;
828 u8 i, rc = 0;
589abe3a 829 u32 mdio_ctrl = bnx2x_get_emac_base(bp, ext_phy_type, port);
ea4e040a
YR		 830
831 /* set clause 45 mode, slow down the MDIO clock to 2.5MHz
832 * (a value of 49==0x31) and make sure that the AUTO poll is off
833 */
589abe3a 834
ea4e040a
YR		 835 saved_mode = REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
836 tmp = saved_mode & ~(EMAC_MDIO_MODE_AUTO_POLL |
837 EMAC_MDIO_MODE_CLOCK_CNT);
838 tmp |= (EMAC_MDIO_MODE_CLAUSE_45 |
839 (49 << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT));
840 REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, tmp);
841 REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
842 udelay(40);
843
844 /* address */
845
846 tmp = ((phy_addr << 21) | (devad << 16) | reg |
847 EMAC_MDIO_COMM_COMMAND_ADDRESS |
848 EMAC_MDIO_COMM_START_BUSY);
849 REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
850
851 for (i = 0; i < 50; i++) {
852 udelay(10);
853
854 tmp = REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
855 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
856 udelay(5);
857 break;
858 }
859 }
860 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
861 DP(NETIF_MSG_LINK, "write phy register failed\n");
862 rc = -EFAULT;
863 } else {
864 /* data */
865 tmp = ((phy_addr << 21) | (devad << 16) | val |
866 EMAC_MDIO_COMM_COMMAND_WRITE_45 |
867 EMAC_MDIO_COMM_START_BUSY);
868 REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
869
870 for (i = 0; i < 50; i++) {
871 udelay(10);
872
873 tmp = REG_RD(bp, mdio_ctrl +
874 EMAC_REG_EMAC_MDIO_COMM);
875 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
876 udelay(5);
877 break;
878 }
879 }
880 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
881 DP(NETIF_MSG_LINK, "write phy register failed\n");
882 rc = -EFAULT;
883 }
884 }
885
886 /* Restore the saved mode */
887 REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, saved_mode);
888
889 return rc;
890}
891
892u8 bnx2x_cl45_read(struct bnx2x *bp, u8 port, u32 ext_phy_type,
893 u8 phy_addr, u8 devad, u16 reg, u16 *ret_val)
894{
895 u32 val, saved_mode;
896 u16 i;
897 u8 rc = 0;
898
589abe3a 899 u32 mdio_ctrl = bnx2x_get_emac_base(bp, ext_phy_type, port);
ea4e040a
YR		 900 /* set clause 45 mode, slow down the MDIO clock to 2.5MHz
901 * (a value of 49==0x31) and make sure that the AUTO poll is off
902 */
589abe3a 903
ea4e040a
YR		 904 saved_mode = REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
905 val = saved_mode & ((EMAC_MDIO_MODE_AUTO_POLL |
906 EMAC_MDIO_MODE_CLOCK_CNT));
907 val |= (EMAC_MDIO_MODE_CLAUSE_45 |
908 (49 << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT));
909 REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, val);
910 REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
911 udelay(40);
912
913 /* address */
914 val = ((phy_addr << 21) | (devad << 16) | reg |
915 EMAC_MDIO_COMM_COMMAND_ADDRESS |
916 EMAC_MDIO_COMM_START_BUSY);
917 REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
918
919 for (i = 0; i < 50; i++) {
920 udelay(10);
921
922 val = REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
923 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
924 udelay(5);
925 break;
926 }
927 }
928 if (val & EMAC_MDIO_COMM_START_BUSY) {
929 DP(NETIF_MSG_LINK, "read phy register failed\n");
930
931 *ret_val = 0;
932 rc = -EFAULT;
933
934 } else {
935 /* data */
936 val = ((phy_addr << 21) | (devad << 16) |
937 EMAC_MDIO_COMM_COMMAND_READ_45 |
938 EMAC_MDIO_COMM_START_BUSY);
939 REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
940
941 for (i = 0; i < 50; i++) {
942 udelay(10);
943
944 val = REG_RD(bp, mdio_ctrl +
945 EMAC_REG_EMAC_MDIO_COMM);
946 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
947 *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA);
948 break;
949 }
950 }
951 if (val & EMAC_MDIO_COMM_START_BUSY) {
952 DP(NETIF_MSG_LINK, "read phy register failed\n");
953
954 *ret_val = 0;
955 rc = -EFAULT;
956 }
957 }
958
959 /* Restore the saved mode */
960 REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, saved_mode);
961
962 return rc;
963}
964
965static void bnx2x_set_aer_mmd(struct link_params *params,
966 struct link_vars *vars)
967{
968 struct bnx2x *bp = params->bp;
969 u32 ser_lane;
970 u16 offset;
971
972 ser_lane = ((params->lane_config &
973 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
974 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
975
976 offset = (vars->phy_flags & PHY_XGXS_FLAG) ?
977 (params->phy_addr + ser_lane) : 0;
978
979 CL45_WR_OVER_CL22(bp, params->port,
980 params->phy_addr,
981 MDIO_REG_BANK_AER_BLOCK,
982 MDIO_AER_BLOCK_AER_REG, 0x3800 + offset);
983}
984
985static void bnx2x_set_master_ln(struct link_params *params)
986{
987 struct bnx2x *bp = params->bp;
988 u16 new_master_ln, ser_lane;
989 ser_lane = ((params->lane_config &
990 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
991 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
992
993 /* set the master_ln for AN */
994 CL45_RD_OVER_CL22(bp, params->port,
995 params->phy_addr,
996 MDIO_REG_BANK_XGXS_BLOCK2,
997 MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
998 &new_master_ln);
999
1000 CL45_WR_OVER_CL22(bp, params->port,
1001 params->phy_addr,
1002 MDIO_REG_BANK_XGXS_BLOCK2 ,
1003 MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
1004 (new_master_ln | ser_lane));
1005}
1006
1007static u8 bnx2x_reset_unicore(struct link_params *params)
1008{
1009 struct bnx2x *bp = params->bp;
1010 u16 mii_control;
1011 u16 i;
1012
1013 CL45_RD_OVER_CL22(bp, params->port,
1014 params->phy_addr,
1015 MDIO_REG_BANK_COMBO_IEEE0,
1016 MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control);
1017
1018 /* reset the unicore */
1019 CL45_WR_OVER_CL22(bp, params->port,
1020 params->phy_addr,
1021 MDIO_REG_BANK_COMBO_IEEE0,
1022 MDIO_COMBO_IEEE0_MII_CONTROL,
1023 (mii_control |
1024 MDIO_COMBO_IEEO_MII_CONTROL_RESET));
6f65497b
EG		 1025 if (params->switch_cfg == SWITCH_CFG_1G)
1026 bnx2x_set_serdes_access(params);
c1b73990 1027
ea4e040a
YR		 1028 /* wait for the reset to self clear */
1029 for (i = 0; i < MDIO_ACCESS_TIMEOUT; i++) {
1030 udelay(5);
1031
1032 /* the reset erased the previous bank value */
1033 CL45_RD_OVER_CL22(bp, params->port,
1034 params->phy_addr,
1035 MDIO_REG_BANK_COMBO_IEEE0,
1036 MDIO_COMBO_IEEE0_MII_CONTROL,
1037 &mii_control);
1038
1039 if (!(mii_control & MDIO_COMBO_IEEO_MII_CONTROL_RESET)) {
1040 udelay(5);
1041 return 0;
1042 }
1043 }
1044
1045 DP(NETIF_MSG_LINK, "BUG! XGXS is still in reset!\n");
1046 return -EINVAL;
1047
1048}
1049
1050static void bnx2x_set_swap_lanes(struct link_params *params)
1051{
1052 struct bnx2x *bp = params->bp;
1053 /* Each two bits represents a lane number:
1054 No swap is 0123 => 0x1b no need to enable the swap */
1055 u16 ser_lane, rx_lane_swap, tx_lane_swap;
1056
1057 ser_lane = ((params->lane_config &
1058 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
1059 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
1060 rx_lane_swap = ((params->lane_config &
1061 PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK) >>
1062 PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT);
1063 tx_lane_swap = ((params->lane_config &
1064 PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK) >>
1065 PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT);
1066
1067 if (rx_lane_swap != 0x1b) {
1068 CL45_WR_OVER_CL22(bp, params->port,
1069 params->phy_addr,
1070 MDIO_REG_BANK_XGXS_BLOCK2,
1071 MDIO_XGXS_BLOCK2_RX_LN_SWAP,
1072 (rx_lane_swap |
1073 MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE |
1074 MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE));
1075 } else {
1076 CL45_WR_OVER_CL22(bp, params->port,
1077 params->phy_addr,
1078 MDIO_REG_BANK_XGXS_BLOCK2,
1079 MDIO_XGXS_BLOCK2_RX_LN_SWAP, 0);
1080 }
1081
1082 if (tx_lane_swap != 0x1b) {
1083 CL45_WR_OVER_CL22(bp, params->port,
1084 params->phy_addr,
1085 MDIO_REG_BANK_XGXS_BLOCK2,
1086 MDIO_XGXS_BLOCK2_TX_LN_SWAP,
1087 (tx_lane_swap |
1088 MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE));
1089 } else {
1090 CL45_WR_OVER_CL22(bp, params->port,
1091 params->phy_addr,
1092 MDIO_REG_BANK_XGXS_BLOCK2,
1093 MDIO_XGXS_BLOCK2_TX_LN_SWAP, 0);
1094 }
1095}
1096
1097static void bnx2x_set_parallel_detection(struct link_params *params,
3196a88a 1098 u8 phy_flags)
ea4e040a
YR		 1099{
1100 struct bnx2x *bp = params->bp;
1101 u16 control2;
1102
1103 CL45_RD_OVER_CL22(bp, params->port,
1104 params->phy_addr,
1105 MDIO_REG_BANK_SERDES_DIGITAL,
1106 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
1107 &control2);
1108
1109
1110 control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
1111
1112
1113 CL45_WR_OVER_CL22(bp, params->port,
1114 params->phy_addr,
1115 MDIO_REG_BANK_SERDES_DIGITAL,
1116 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
1117 control2);
1118
1119 if (phy_flags & PHY_XGXS_FLAG) {
1120 DP(NETIF_MSG_LINK, "XGXS\n");
1121
1122 CL45_WR_OVER_CL22(bp, params->port,
1123 params->phy_addr,
1124 MDIO_REG_BANK_10G_PARALLEL_DETECT,
1125 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK,
1126 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT);
1127
1128 CL45_RD_OVER_CL22(bp, params->port,
1129 params->phy_addr,
1130 MDIO_REG_BANK_10G_PARALLEL_DETECT,
1131 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
1132 &control2);
1133
1134
1135 control2 |=
1136 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN;
1137
1138 CL45_WR_OVER_CL22(bp, params->port,
1139 params->phy_addr,
1140 MDIO_REG_BANK_10G_PARALLEL_DETECT,
1141 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
1142 control2);
1143
1144 /* Disable parallel detection of HiG */
1145 CL45_WR_OVER_CL22(bp, params->port,
1146 params->phy_addr,
1147 MDIO_REG_BANK_XGXS_BLOCK2,
1148 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G,
1149 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS |
1150 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS);
1151 }
1152}
1153
1154static void bnx2x_set_autoneg(struct link_params *params,
239d686d
EG		 1155 struct link_vars *vars,
1156 u8 enable_cl73)
ea4e040a
YR		 1157{
1158 struct bnx2x *bp = params->bp;
1159 u16 reg_val;
1160
1161 /* CL37 Autoneg */
1162
1163 CL45_RD_OVER_CL22(bp, params->port,
1164 params->phy_addr,
1165 MDIO_REG_BANK_COMBO_IEEE0,
1166 MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
1167
1168 /* CL37 Autoneg Enabled */
8c99e7b0 1169 if (vars->line_speed == SPEED_AUTO_NEG)
ea4e040a
YR		 1170 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN;
1171 else /* CL37 Autoneg Disabled */
1172 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
1173 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN);
1174
1175 CL45_WR_OVER_CL22(bp, params->port,
1176 params->phy_addr,
1177 MDIO_REG_BANK_COMBO_IEEE0,
1178 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
1179
1180 /* Enable/Disable Autodetection */
1181
1182 CL45_RD_OVER_CL22(bp, params->port,
1183 params->phy_addr,
1184 MDIO_REG_BANK_SERDES_DIGITAL,
1185 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, &reg_val);
239d686d
EG		 1186 reg_val &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN |
1187 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT);
1188 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE;
8c99e7b0 1189 if (vars->line_speed == SPEED_AUTO_NEG)
ea4e040a
YR		 1190 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
1191 else
1192 reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
1193
1194 CL45_WR_OVER_CL22(bp, params->port,
1195 params->phy_addr,
1196 MDIO_REG_BANK_SERDES_DIGITAL,
1197 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, reg_val);
1198
1199 /* Enable TetonII and BAM autoneg */
1200 CL45_RD_OVER_CL22(bp, params->port,
1201 params->phy_addr,
1202 MDIO_REG_BANK_BAM_NEXT_PAGE,
1203 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
1204 &reg_val);
8c99e7b0 1205 if (vars->line_speed == SPEED_AUTO_NEG) {
ea4e040a
YR		 1206 /* Enable BAM aneg Mode and TetonII aneg Mode */
1207 reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
1208 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
1209 } else {
1210 /* TetonII and BAM Autoneg Disabled */
1211 reg_val &= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
1212 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
1213 }
1214 CL45_WR_OVER_CL22(bp, params->port,
1215 params->phy_addr,
1216 MDIO_REG_BANK_BAM_NEXT_PAGE,
1217 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
1218 reg_val);
1219
239d686d
EG		 1220 if (enable_cl73) {
1221 /* Enable Cl73 FSM status bits */
1222 CL45_WR_OVER_CL22(bp, params->port,
1223 params->phy_addr,
1224 MDIO_REG_BANK_CL73_USERB0,
1225 MDIO_CL73_USERB0_CL73_UCTRL,
1226 MDIO_CL73_USERB0_CL73_UCTRL_USTAT1_MUXSEL);
1227
1228 /* Enable BAM Station Manager*/
1229 CL45_WR_OVER_CL22(bp, params->port,
1230 params->phy_addr,
1231 MDIO_REG_BANK_CL73_USERB0,
1232 MDIO_CL73_USERB0_CL73_BAM_CTRL1,
1233 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN |
1234 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN |
1235 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN);
1236
1237 /* Merge CL73 and CL37 aneg resolution */
1238 CL45_RD_OVER_CL22(bp, params->port,
1239 params->phy_addr,
1240 MDIO_REG_BANK_CL73_USERB0,
1241 MDIO_CL73_USERB0_CL73_BAM_CTRL3,
1242 &reg_val);
1243
1244 if (params->speed_cap_mask &
1245 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) {
1246 /* Set the CL73 AN speed */
1247 CL45_RD_OVER_CL22(bp, params->port,
1248 params->phy_addr,
1249 MDIO_REG_BANK_CL73_IEEEB1,
1250 MDIO_CL73_IEEEB1_AN_ADV2,
1251 &reg_val);
1252
1253 CL45_WR_OVER_CL22(bp, params->port,
1254 params->phy_addr,
1255 MDIO_REG_BANK_CL73_IEEEB1,
1256 MDIO_CL73_IEEEB1_AN_ADV2,
1257 reg_val | MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4);
1258
1259 }
1260 /* CL73 Autoneg Enabled */
1261 reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN;
1262
1263 } else /* CL73 Autoneg Disabled */
1264 reg_val = 0;
ea4e040a 1265
ea4e040a
YR		 1266 CL45_WR_OVER_CL22(bp, params->port,
1267 params->phy_addr,
1268 MDIO_REG_BANK_CL73_IEEEB0,
1269 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, reg_val);
1270}
1271
1272/* program SerDes, forced speed */
8c99e7b0
YR		 1273static void bnx2x_program_serdes(struct link_params *params,
1274 struct link_vars *vars)
ea4e040a
YR		 1275{
1276 struct bnx2x *bp = params->bp;
1277 u16 reg_val;
1278
57937203 1279 /* program duplex, disable autoneg and sgmii*/
ea4e040a
YR		 1280 CL45_RD_OVER_CL22(bp, params->port,
1281 params->phy_addr,
1282 MDIO_REG_BANK_COMBO_IEEE0,
1283 MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
1284 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX |
57937203
EG		 1285 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
1286 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK);
ea4e040a
YR		 1287 if (params->req_duplex == DUPLEX_FULL)
1288 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
1289 CL45_WR_OVER_CL22(bp, params->port,
1290 params->phy_addr,
1291 MDIO_REG_BANK_COMBO_IEEE0,
1292 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
1293
1294 /* program speed
1295 - needed only if the speed is greater than 1G (2.5G or 10G) */
8c99e7b0 1296 CL45_RD_OVER_CL22(bp, params->port,
ea4e040a
YR		 1297 params->phy_addr,
1298 MDIO_REG_BANK_SERDES_DIGITAL,
1299 MDIO_SERDES_DIGITAL_MISC1, &reg_val);
8c99e7b0
YR		 1300 /* clearing the speed value before setting the right speed */
1301 DP(NETIF_MSG_LINK, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x\n", reg_val);
1302
1303 reg_val &= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK |
1304 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
1305
1306 if (!((vars->line_speed == SPEED_1000) ||
1307 (vars->line_speed == SPEED_100) ||
1308 (vars->line_speed == SPEED_10))) {
1309
ea4e040a
YR		 1310 reg_val |= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M |
1311 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
8c99e7b0 1312 if (vars->line_speed == SPEED_10000)
ea4e040a
YR		 1313 reg_val |=
1314 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4;
8c99e7b0 1315 if (vars->line_speed == SPEED_13000)
ea4e040a
YR		 1316 reg_val |=
1317 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_13G;
8c99e7b0
YR		 1318 }
1319
1320 CL45_WR_OVER_CL22(bp, params->port,
ea4e040a
YR		 1321 params->phy_addr,
1322 MDIO_REG_BANK_SERDES_DIGITAL,
1323 MDIO_SERDES_DIGITAL_MISC1, reg_val);
8c99e7b0 1324
ea4e040a
YR		 1325}
1326
1327static void bnx2x_set_brcm_cl37_advertisment(struct link_params *params)
1328{
1329 struct bnx2x *bp = params->bp;
1330 u16 val = 0;
1331
1332 /* configure the 48 bits for BAM AN */
1333
1334 /* set extended capabilities */
1335 if (params->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)
1336 val |= MDIO_OVER_1G_UP1_2_5G;
1337 if (params->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
1338 val |= MDIO_OVER_1G_UP1_10G;
1339 CL45_WR_OVER_CL22(bp, params->port,
1340 params->phy_addr,
1341 MDIO_REG_BANK_OVER_1G,
1342 MDIO_OVER_1G_UP1, val);
1343
1344 CL45_WR_OVER_CL22(bp, params->port,
1345 params->phy_addr,
1346 MDIO_REG_BANK_OVER_1G,
239d686d 1347 MDIO_OVER_1G_UP3, 0x400);
ea4e040a
YR		 1348}
1349
8c99e7b0 1350static void bnx2x_calc_ieee_aneg_adv(struct link_params *params, u32 *ieee_fc)
ea4e040a 1351{
8c99e7b0 1352 *ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX;
ea4e040a
YR		 1353 /* resolve pause mode and advertisement
1354 * Please refer to Table 28B-3 of the 802.3ab-1999 spec */
1355
1356 switch (params->req_flow_ctrl) {
c0700f90
DM		 1357 case BNX2X_FLOW_CTRL_AUTO:
1358 if (params->req_fc_auto_adv == BNX2X_FLOW_CTRL_BOTH) {
8c99e7b0 1359 *ieee_fc |=
ea4e040a
YR		 1360 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
1361 } else {
8c99e7b0 1362 *ieee_fc |=
ea4e040a
YR		 1363 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
1364 }
1365 break;
c0700f90 1366 case BNX2X_FLOW_CTRL_TX:
8c99e7b0 1367 *ieee_fc |=
ea4e040a
YR		 1368 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
1369 break;
1370
c0700f90
DM		 1371 case BNX2X_FLOW_CTRL_RX:
1372 case BNX2X_FLOW_CTRL_BOTH:
8c99e7b0 1373 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
ea4e040a
YR		 1374 break;
1375
c0700f90 1376 case BNX2X_FLOW_CTRL_NONE:
ea4e040a 1377 default:
8c99e7b0 1378 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE;
ea4e040a
YR		 1379 break;
1380 }
8c99e7b0 1381}
ea4e040a 1382
8c99e7b0
YR		 1383static void bnx2x_set_ieee_aneg_advertisment(struct link_params *params,
1384 u32 ieee_fc)
1385{
1386 struct bnx2x *bp = params->bp;
1387 /* for AN, we are always publishing full duplex */
ea4e040a
YR		 1388
1389 CL45_WR_OVER_CL22(bp, params->port,
1390 params->phy_addr,
1391 MDIO_REG_BANK_COMBO_IEEE0,
8c99e7b0 1392 MDIO_COMBO_IEEE0_AUTO_NEG_ADV, (u16)ieee_fc);
ea4e040a
YR		 1393}
1394
239d686d 1395static void bnx2x_restart_autoneg(struct link_params *params, u8 enable_cl73)
ea4e040a
YR		 1396{
1397 struct bnx2x *bp = params->bp;
3a36f2ef 1398 u16 mii_control;
239d686d 1399
ea4e040a 1400 DP(NETIF_MSG_LINK, "bnx2x_restart_autoneg\n");
3a36f2ef 1401 /* Enable and restart BAM/CL37 aneg */
ea4e040a 1402
239d686d
EG		 1403 if (enable_cl73) {
1404 CL45_RD_OVER_CL22(bp, params->port,
1405 params->phy_addr,
1406 MDIO_REG_BANK_CL73_IEEEB0,
1407 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
1408 &mii_control);
1409
1410 CL45_WR_OVER_CL22(bp, params->port,
1411 params->phy_addr,
1412 MDIO_REG_BANK_CL73_IEEEB0,
1413 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
1414 (mii_control |
1415 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN |
1416 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN));
1417 } else {
1418
1419 CL45_RD_OVER_CL22(bp, params->port,
1420 params->phy_addr,
1421 MDIO_REG_BANK_COMBO_IEEE0,
1422 MDIO_COMBO_IEEE0_MII_CONTROL,
1423 &mii_control);
1424 DP(NETIF_MSG_LINK,
1425 "bnx2x_restart_autoneg mii_control before = 0x%x\n",
1426 mii_control);
1427 CL45_WR_OVER_CL22(bp, params->port,
1428 params->phy_addr,
1429 MDIO_REG_BANK_COMBO_IEEE0,
1430 MDIO_COMBO_IEEE0_MII_CONTROL,
1431 (mii_control |
1432 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
1433 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN));
1434 }
ea4e040a
YR		 1435}
1436
8c99e7b0
YR		 1437static void bnx2x_initialize_sgmii_process(struct link_params *params,
1438 struct link_vars *vars)
ea4e040a
YR		 1439{
1440 struct bnx2x *bp = params->bp;
1441 u16 control1;
1442
1443 /* in SGMII mode, the unicore is always slave */
1444
1445 CL45_RD_OVER_CL22(bp, params->port,
1446 params->phy_addr,
1447 MDIO_REG_BANK_SERDES_DIGITAL,
1448 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
1449 &control1);
1450 control1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT;
1451 /* set sgmii mode (and not fiber) */
1452 control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE |
1453 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET |
1454 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE);
1455 CL45_WR_OVER_CL22(bp, params->port,
1456 params->phy_addr,
1457 MDIO_REG_BANK_SERDES_DIGITAL,
1458 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
1459 control1);
1460
1461 /* if forced speed */
8c99e7b0 1462 if (!(vars->line_speed == SPEED_AUTO_NEG)) {
ea4e040a
YR		 1463 /* set speed, disable autoneg */
1464 u16 mii_control;
1465
1466 CL45_RD_OVER_CL22(bp, params->port,
1467 params->phy_addr,
1468 MDIO_REG_BANK_COMBO_IEEE0,
1469 MDIO_COMBO_IEEE0_MII_CONTROL,
1470 &mii_control);
1471 mii_control &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
1472 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK|
1473 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX);
1474
8c99e7b0 1475 switch (vars->line_speed) {
ea4e040a
YR		 1476 case SPEED_100:
1477 mii_control |=
1478 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100;
1479 break;
1480 case SPEED_1000:
1481 mii_control |=
1482 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000;
1483 break;
1484 case SPEED_10:
1485 /* there is nothing to set for 10M */
1486 break;
1487 default:
1488 /* invalid speed for SGMII */
8c99e7b0
YR		 1489 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
1490 vars->line_speed);
ea4e040a
YR		 1491 break;
1492 }
1493
1494 /* setting the full duplex */
1495 if (params->req_duplex == DUPLEX_FULL)
1496 mii_control |=
1497 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
1498 CL45_WR_OVER_CL22(bp, params->port,
1499 params->phy_addr,
1500 MDIO_REG_BANK_COMBO_IEEE0,
1501 MDIO_COMBO_IEEE0_MII_CONTROL,
1502 mii_control);
1503
1504 } else { /* AN mode */
1505 /* enable and restart AN */
239d686d 1506 bnx2x_restart_autoneg(params, 0);
ea4e040a
YR		 1507 }
1508}
1509
1510
1511/*
1512 * link management
1513 */
1514
1515static void bnx2x_pause_resolve(struct link_vars *vars, u32 pause_result)
8c99e7b0
YR		 1516{ /* LD LP */
1517 switch (pause_result) { /* ASYM P ASYM P */
1518 case 0xb: /* 1 0 1 1 */
c0700f90 1519 vars->flow_ctrl = BNX2X_FLOW_CTRL_TX;
ea4e040a
YR		 1520 break;
1521
8c99e7b0 1522 case 0xe: /* 1 1 1 0 */
c0700f90 1523 vars->flow_ctrl = BNX2X_FLOW_CTRL_RX;
ea4e040a
YR		 1524 break;
1525
8c99e7b0
YR		 1526 case 0x5: /* 0 1 0 1 */
1527 case 0x7: /* 0 1 1 1 */
1528 case 0xd: /* 1 1 0 1 */
1529 case 0xf: /* 1 1 1 1 */
c0700f90 1530 vars->flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
ea4e040a
YR		 1531 break;
1532
1533 default:
1534 break;
1535 }
1536}
1537
1538static u8 bnx2x_ext_phy_resove_fc(struct link_params *params,
1539 struct link_vars *vars)
1540{
1541 struct bnx2x *bp = params->bp;
1542 u8 ext_phy_addr;
3196a88a
EG		 1543 u16 ld_pause; /* local */
1544 u16 lp_pause; /* link partner */
ea4e040a
YR		 1545 u16 an_complete; /* AN complete */
1546 u16 pause_result;
1547 u8 ret = 0;
1548 u32 ext_phy_type;
1549 u8 port = params->port;
1550 ext_phy_addr = ((params->ext_phy_config &
1551 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
1552 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
1553
1554 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
1555 /* read twice */
1556
1557 bnx2x_cl45_read(bp, port,
1558 ext_phy_type,
1559 ext_phy_addr,
1560 MDIO_AN_DEVAD,
1561 MDIO_AN_REG_STATUS, &an_complete);
1562 bnx2x_cl45_read(bp, port,
1563 ext_phy_type,
1564 ext_phy_addr,
1565 MDIO_AN_DEVAD,
1566 MDIO_AN_REG_STATUS, &an_complete);
1567
1568 if (an_complete & MDIO_AN_REG_STATUS_AN_COMPLETE) {
1569 ret = 1;
1570 bnx2x_cl45_read(bp, port,
1571 ext_phy_type,
1572 ext_phy_addr,
1573 MDIO_AN_DEVAD,
1574 MDIO_AN_REG_ADV_PAUSE, &ld_pause);
1575 bnx2x_cl45_read(bp, port,
1576 ext_phy_type,
1577 ext_phy_addr,
1578 MDIO_AN_DEVAD,
1579 MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
1580 pause_result = (ld_pause &
1581 MDIO_AN_REG_ADV_PAUSE_MASK) >> 8;
1582 pause_result |= (lp_pause &
1583 MDIO_AN_REG_ADV_PAUSE_MASK) >> 10;
1584 DP(NETIF_MSG_LINK, "Ext PHY pause result 0x%x \n",
1585 pause_result);
1586 bnx2x_pause_resolve(vars, pause_result);
c0700f90 1587 if (vars->flow_ctrl == BNX2X_FLOW_CTRL_NONE &&
8c99e7b0
YR		 1588 ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073) {
1589 bnx2x_cl45_read(bp, port,
1590 ext_phy_type,
1591 ext_phy_addr,
1592 MDIO_AN_DEVAD,
1593 MDIO_AN_REG_CL37_FC_LD, &ld_pause);
1594
1595 bnx2x_cl45_read(bp, port,
1596 ext_phy_type,
1597 ext_phy_addr,
1598 MDIO_AN_DEVAD,
1599 MDIO_AN_REG_CL37_FC_LP, &lp_pause);
1600 pause_result = (ld_pause &
1601 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 5;
1602 pause_result |= (lp_pause &
1603 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 7;
1604
1605 bnx2x_pause_resolve(vars, pause_result);
1606 DP(NETIF_MSG_LINK, "Ext PHY CL37 pause result 0x%x \n",
1607 pause_result);
1608 }
ea4e040a
YR		 1609 }
1610 return ret;
1611}
1612
1613
1614static void bnx2x_flow_ctrl_resolve(struct link_params *params,
1615 struct link_vars *vars,
1616 u32 gp_status)
1617{
1618 struct bnx2x *bp = params->bp;
3196a88a
EG		 1619 u16 ld_pause; /* local driver */
1620 u16 lp_pause; /* link partner */
ea4e040a
YR		 1621 u16 pause_result;
1622
c0700f90 1623 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
ea4e040a
YR		 1624
1625 /* resolve from gp_status in case of AN complete and not sgmii */
c0700f90 1626 if ((params->req_flow_ctrl == BNX2X_FLOW_CTRL_AUTO) &&
ea4e040a
YR		 1627 (gp_status & MDIO_AN_CL73_OR_37_COMPLETE) &&
1628 (!(vars->phy_flags & PHY_SGMII_FLAG)) &&
1629 (XGXS_EXT_PHY_TYPE(params->ext_phy_config) ==
1630 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)) {
1631 CL45_RD_OVER_CL22(bp, params->port,
1632 params->phy_addr,
1633 MDIO_REG_BANK_COMBO_IEEE0,
1634 MDIO_COMBO_IEEE0_AUTO_NEG_ADV,
1635 &ld_pause);
1636 CL45_RD_OVER_CL22(bp, params->port,
1637 params->phy_addr,
1638 MDIO_REG_BANK_COMBO_IEEE0,
1639 MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1,
1640 &lp_pause);
1641 pause_result = (ld_pause &
1642 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>5;
1643 pause_result |= (lp_pause &
1644 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>7;
1645 DP(NETIF_MSG_LINK, "pause_result 0x%x\n", pause_result);
1646 bnx2x_pause_resolve(vars, pause_result);
c0700f90 1647 } else if ((params->req_flow_ctrl == BNX2X_FLOW_CTRL_AUTO) &&
ea4e040a
YR		 1648 (bnx2x_ext_phy_resove_fc(params, vars))) {
1649 return;
1650 } else {
c0700f90 1651 if (params->req_flow_ctrl == BNX2X_FLOW_CTRL_AUTO)
8c99e7b0
YR		 1652 vars->flow_ctrl = params->req_fc_auto_adv;
1653 else
1654 vars->flow_ctrl = params->req_flow_ctrl;
ea4e040a
YR		 1655 }
1656 DP(NETIF_MSG_LINK, "flow_ctrl 0x%x\n", vars->flow_ctrl);
1657}
1658
239d686d
EG		 1659static void bnx2x_check_fallback_to_cl37(struct link_params *params)
1660{
1661 struct bnx2x *bp = params->bp;
1662 u16 rx_status, ustat_val, cl37_fsm_recieved;
1663 DP(NETIF_MSG_LINK, "bnx2x_check_fallback_to_cl37\n");
1664 /* Step 1: Make sure signal is detected */
1665 CL45_RD_OVER_CL22(bp, params->port,
1666 params->phy_addr,
1667 MDIO_REG_BANK_RX0,
1668 MDIO_RX0_RX_STATUS,
1669 &rx_status);
1670 if ((rx_status & MDIO_RX0_RX_STATUS_SIGDET) !=
1671 (MDIO_RX0_RX_STATUS_SIGDET)) {
1672 DP(NETIF_MSG_LINK, "Signal is not detected. Restoring CL73."
1673 "rx_status(0x80b0) = 0x%x\n", rx_status);
1674 CL45_WR_OVER_CL22(bp, params->port,
1675 params->phy_addr,
1676 MDIO_REG_BANK_CL73_IEEEB0,
1677 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
1678 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN);
1679 return;
1680 }
1681 /* Step 2: Check CL73 state machine */
1682 CL45_RD_OVER_CL22(bp, params->port,
1683 params->phy_addr,
1684 MDIO_REG_BANK_CL73_USERB0,
1685 MDIO_CL73_USERB0_CL73_USTAT1,
1686 &ustat_val);
1687 if ((ustat_val &
1688 (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
1689 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) !=
1690 (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
1691 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) {
1692 DP(NETIF_MSG_LINK, "CL73 state-machine is not stable. "
1693 "ustat_val(0x8371) = 0x%x\n", ustat_val);
1694 return;
1695 }
1696 /* Step 3: Check CL37 Message Pages received to indicate LP
1697 supports only CL37 */
1698 CL45_RD_OVER_CL22(bp, params->port,
1699 params->phy_addr,
1700 MDIO_REG_BANK_REMOTE_PHY,
1701 MDIO_REMOTE_PHY_MISC_RX_STATUS,
1702 &cl37_fsm_recieved);
1703 if ((cl37_fsm_recieved &
1704 (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
1705 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) !=
1706 (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
1707 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) {
1708 DP(NETIF_MSG_LINK, "No CL37 FSM were received. "
1709 "misc_rx_status(0x8330) = 0x%x\n",
1710 cl37_fsm_recieved);
1711 return;
1712 }
1713 /* The combined cl37/cl73 fsm state information indicating that we are
1714 connected to a device which does not support cl73, but does support
1715 cl37 BAM. In this case we disable cl73 and restart cl37 auto-neg */
1716 /* Disable CL73 */
1717 CL45_WR_OVER_CL22(bp, params->port,
1718 params->phy_addr,
1719 MDIO_REG_BANK_CL73_IEEEB0,
1720 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
1721 0);
1722 /* Restart CL37 autoneg */
1723 bnx2x_restart_autoneg(params, 0);
1724 DP(NETIF_MSG_LINK, "Disabling CL73, and restarting CL37 autoneg\n");
1725}
ea4e040a 1726static u8 bnx2x_link_settings_status(struct link_params *params,
2f904460
EG		 1727 struct link_vars *vars,
1728 u32 gp_status,
1729 u8 ext_phy_link_up)
ea4e040a
YR		 1730{
1731 struct bnx2x *bp = params->bp;
6c55c3cd 1732 u16 new_line_speed;
ea4e040a
YR		 1733 u8 rc = 0;
1734 vars->link_status = 0;
1735
1736 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) {
1737 DP(NETIF_MSG_LINK, "phy link up gp_status=0x%x\n",
1738 gp_status);
1739
1740 vars->phy_link_up = 1;
1741 vars->link_status |= LINK_STATUS_LINK_UP;
1742
1743 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS)
1744 vars->duplex = DUPLEX_FULL;
1745 else
1746 vars->duplex = DUPLEX_HALF;
1747
1748 bnx2x_flow_ctrl_resolve(params, vars, gp_status);
1749
1750 switch (gp_status & GP_STATUS_SPEED_MASK) {
1751 case GP_STATUS_10M:
6c55c3cd 1752 new_line_speed = SPEED_10;
ea4e040a
YR		 1753 if (vars->duplex == DUPLEX_FULL)
1754 vars->link_status |= LINK_10TFD;
1755 else
1756 vars->link_status |= LINK_10THD;
1757 break;
1758
1759 case GP_STATUS_100M:
6c55c3cd 1760 new_line_speed = SPEED_100;
ea4e040a
YR		 1761 if (vars->duplex == DUPLEX_FULL)
1762 vars->link_status |= LINK_100TXFD;
1763 else
1764 vars->link_status |= LINK_100TXHD;
1765 break;
1766
1767 case GP_STATUS_1G:
1768 case GP_STATUS_1G_KX:
6c55c3cd 1769 new_line_speed = SPEED_1000;
ea4e040a
YR		 1770 if (vars->duplex == DUPLEX_FULL)
1771 vars->link_status |= LINK_1000TFD;
1772 else
1773 vars->link_status |= LINK_1000THD;
1774 break;
1775
1776 case GP_STATUS_2_5G:
6c55c3cd 1777 new_line_speed = SPEED_2500;
ea4e040a
YR		 1778 if (vars->duplex == DUPLEX_FULL)
1779 vars->link_status |= LINK_2500TFD;
1780 else
1781 vars->link_status |= LINK_2500THD;
1782 break;
1783
1784 case GP_STATUS_5G:
1785 case GP_STATUS_6G:
1786 DP(NETIF_MSG_LINK,
1787 "link speed unsupported gp_status 0x%x\n",
1788 gp_status);
1789 return -EINVAL;
1790 break;
1791 case GP_STATUS_10G_KX4:
1792 case GP_STATUS_10G_HIG:
1793 case GP_STATUS_10G_CX4:
6c55c3cd 1794 new_line_speed = SPEED_10000;
ea4e040a
YR		 1795 vars->link_status |= LINK_10GTFD;
1796 break;
1797
1798 case GP_STATUS_12G_HIG:
6c55c3cd 1799 new_line_speed = SPEED_12000;
ea4e040a
YR		 1800 vars->link_status |= LINK_12GTFD;
1801 break;
1802
1803 case GP_STATUS_12_5G:
6c55c3cd 1804 new_line_speed = SPEED_12500;
ea4e040a
YR		 1805 vars->link_status |= LINK_12_5GTFD;
1806 break;
1807
1808 case GP_STATUS_13G:
6c55c3cd 1809 new_line_speed = SPEED_13000;
ea4e040a
YR		 1810 vars->link_status |= LINK_13GTFD;
1811 break;
1812
1813 case GP_STATUS_15G:
6c55c3cd 1814 new_line_speed = SPEED_15000;
ea4e040a
YR		 1815 vars->link_status |= LINK_15GTFD;
1816 break;
1817
1818 case GP_STATUS_16G:
6c55c3cd 1819 new_line_speed = SPEED_16000;
ea4e040a
YR		 1820 vars->link_status |= LINK_16GTFD;
1821 break;
1822
1823 default:
1824 DP(NETIF_MSG_LINK,
1825 "link speed unsupported gp_status 0x%x\n",
1826 gp_status);
1827 return -EINVAL;
1828 break;
1829 }
1830
6c55c3cd
EG		 1831 /* Upon link speed change set the NIG into drain mode.
1832 Comes to deals with possible FIFO glitch due to clk change
1833 when speed is decreased without link down indicator */
1834 if (new_line_speed != vars->line_speed) {
2f904460
EG		 1835 if (XGXS_EXT_PHY_TYPE(params->ext_phy_config) !=
1836 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT &&
1837 ext_phy_link_up) {
1838 DP(NETIF_MSG_LINK, "Internal link speed %d is"
1839 " different than the external"
1840 " link speed %d\n", new_line_speed,
1841 vars->line_speed);
1842 vars->phy_link_up = 0;
1843 return 0;
1844 }
6c55c3cd
EG		 1845 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE
1846 + params->port*4, 0);
1847 msleep(1);
1848 }
1849 vars->line_speed = new_line_speed;
ea4e040a
YR		 1850 vars->link_status |= LINK_STATUS_SERDES_LINK;
1851
57963ed9
YR		 1852 if ((params->req_line_speed == SPEED_AUTO_NEG) &&
1853 ((XGXS_EXT_PHY_TYPE(params->ext_phy_config) ==
1854 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ||
1855 (XGXS_EXT_PHY_TYPE(params->ext_phy_config) ==
589abe3a
EG		 1856 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705) ||
1857 (XGXS_EXT_PHY_TYPE(params->ext_phy_config) ==
2f904460 1858 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726))) {
ea4e040a
YR		 1859 vars->autoneg = AUTO_NEG_ENABLED;
1860
1861 if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE) {
1862 vars->autoneg |= AUTO_NEG_COMPLETE;
1863 vars->link_status |=
1864 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
1865 }
1866
1867 vars->autoneg |= AUTO_NEG_PARALLEL_DETECTION_USED;
1868 vars->link_status |=
1869 LINK_STATUS_PARALLEL_DETECTION_USED;
1870
1871 }
c0700f90 1872 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
8c99e7b0
YR		 1873 vars->link_status |=
1874 LINK_STATUS_TX_FLOW_CONTROL_ENABLED;
ea4e040a 1875
c0700f90 1876 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
8c99e7b0
YR		 1877 vars->link_status |=
1878 LINK_STATUS_RX_FLOW_CONTROL_ENABLED;
ea4e040a
YR		 1879
1880 } else { /* link_down */
1881 DP(NETIF_MSG_LINK, "phy link down\n");
1882
1883 vars->phy_link_up = 0;
57963ed9 1884
ea4e040a 1885 vars->duplex = DUPLEX_FULL;
c0700f90 1886 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
ea4e040a
YR		 1887 vars->autoneg = AUTO_NEG_DISABLED;
1888 vars->mac_type = MAC_TYPE_NONE;
239d686d
EG		 1889
1890 if ((params->req_line_speed == SPEED_AUTO_NEG) &&
1891 ((XGXS_EXT_PHY_TYPE(params->ext_phy_config) ==
1892 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT))) {
1893 /* Check signal is detected */
1894 bnx2x_check_fallback_to_cl37(params);
1895 }
ea4e040a
YR		 1896 }
1897
1898 DP(NETIF_MSG_LINK, "gp_status 0x%x phy_link_up %x line_speed %x \n",
1899 gp_status, vars->phy_link_up, vars->line_speed);
1900 DP(NETIF_MSG_LINK, "duplex %x flow_ctrl 0x%x"
1901 " autoneg 0x%x\n",
1902 vars->duplex,
1903 vars->flow_ctrl, vars->autoneg);
1904 DP(NETIF_MSG_LINK, "link_status 0x%x\n", vars->link_status);
1905
1906 return rc;
1907}
1908
ed8680a7 1909static void bnx2x_set_gmii_tx_driver(struct link_params *params)
ea4e040a
YR		 1910{
1911 struct bnx2x *bp = params->bp;
1912 u16 lp_up2;
1913 u16 tx_driver;
c2c8b03e 1914 u16 bank;
ea4e040a
YR		 1915
1916 /* read precomp */
ea4e040a
YR		 1917 CL45_RD_OVER_CL22(bp, params->port,
1918 params->phy_addr,
1919 MDIO_REG_BANK_OVER_1G,
1920 MDIO_OVER_1G_LP_UP2, &lp_up2);
1921
ea4e040a
YR		 1922 /* bits [10:7] at lp_up2, positioned at [15:12] */
1923 lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >>
1924 MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) <<
1925 MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT);
1926
c2c8b03e
EG		 1927 if (lp_up2 == 0)
1928 return;
1929
1930 for (bank = MDIO_REG_BANK_TX0; bank <= MDIO_REG_BANK_TX3;
1931 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) {
1932 CL45_RD_OVER_CL22(bp, params->port,
ea4e040a 1933 params->phy_addr,
c2c8b03e
EG		 1934 bank,
1935 MDIO_TX0_TX_DRIVER, &tx_driver);
1936
1937 /* replace tx_driver bits [15:12] */
1938 if (lp_up2 !=
1939 (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK)) {
1940 tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK;
1941 tx_driver |= lp_up2;
1942 CL45_WR_OVER_CL22(bp, params->port,
1943 params->phy_addr,
1944 bank,
1945 MDIO_TX0_TX_DRIVER, tx_driver);
1946 }
ea4e040a
YR		 1947 }
1948}
1949
1950static u8 bnx2x_emac_program(struct link_params *params,
1951 u32 line_speed, u32 duplex)
1952{
1953 struct bnx2x *bp = params->bp;
1954 u8 port = params->port;
1955 u16 mode = 0;
1956
1957 DP(NETIF_MSG_LINK, "setting link speed & duplex\n");
1958 bnx2x_bits_dis(bp, GRCBASE_EMAC0 + port*0x400 +
1959 EMAC_REG_EMAC_MODE,
1960 (EMAC_MODE_25G_MODE |
1961 EMAC_MODE_PORT_MII_10M |
1962 EMAC_MODE_HALF_DUPLEX));
1963 switch (line_speed) {
1964 case SPEED_10:
1965 mode |= EMAC_MODE_PORT_MII_10M;
1966 break;
1967
1968 case SPEED_100:
1969 mode |= EMAC_MODE_PORT_MII;
1970 break;
1971
1972 case SPEED_1000:
1973 mode |= EMAC_MODE_PORT_GMII;
1974 break;
1975
1976 case SPEED_2500:
1977 mode |= (EMAC_MODE_25G_MODE | EMAC_MODE_PORT_GMII);
1978 break;
1979
1980 default:
1981 /* 10G not valid for EMAC */
1982 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n", line_speed);
1983 return -EINVAL;
1984 }
1985
1986 if (duplex == DUPLEX_HALF)
1987 mode |= EMAC_MODE_HALF_DUPLEX;
1988 bnx2x_bits_en(bp,
1989 GRCBASE_EMAC0 + port*0x400 + EMAC_REG_EMAC_MODE,
1990 mode);
1991
1992 bnx2x_set_led(bp, params->port, LED_MODE_OPER,
1993 line_speed, params->hw_led_mode, params->chip_id);
1994 return 0;
1995}
1996
1997/*****************************************************************************/
17de50b7 1998/* External Phy section */
ea4e040a 1999/*****************************************************************************/
f57a6025 2000void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port)
ea4e040a
YR		 2001{
2002 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
17de50b7 2003 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
ea4e040a
YR		 2004 msleep(1);
2005 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
17de50b7 2006 MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
ea4e040a
YR		 2007}
2008
2009static void bnx2x_ext_phy_reset(struct link_params *params,
2010 struct link_vars *vars)
2011{
2012 struct bnx2x *bp = params->bp;
2013 u32 ext_phy_type;
2014 u8 ext_phy_addr = ((params->ext_phy_config &
2015 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
2016 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
2017 DP(NETIF_MSG_LINK, "Port %x: bnx2x_ext_phy_reset\n", params->port);
2018 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
2019 /* The PHY reset is controled by GPIO 1
2020 * Give it 1ms of reset pulse
2021 */
2022 if (vars->phy_flags & PHY_XGXS_FLAG) {
2023
2024 switch (ext_phy_type) {
2025 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
2026 DP(NETIF_MSG_LINK, "XGXS Direct\n");
2027 break;
2028
2029 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
2030 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
2031 DP(NETIF_MSG_LINK, "XGXS 8705/8706\n");
2032
2033 /* Restore normal power mode*/
2034 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
17de50b7
EG		 2035 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
2036 params->port);
ea4e040a
YR		 2037
2038 /* HW reset */
f57a6025 2039 bnx2x_ext_phy_hw_reset(bp, params->port);
ea4e040a
YR		 2040
2041 bnx2x_cl45_write(bp, params->port,
2042 ext_phy_type,
2043 ext_phy_addr,
2044 MDIO_PMA_DEVAD,
2045 MDIO_PMA_REG_CTRL, 0xa040);
2046 break;
4d295db0
EG		 2047
2048 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
2049 break;
2050
589abe3a
EG		 2051 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
2052
2053 /* Restore normal power mode*/
2054 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
2055 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
2056 params->port);
2057
2058 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
2059 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
2060 params->port);
2061
2062 bnx2x_cl45_write(bp, params->port,
2063 ext_phy_type,
2064 ext_phy_addr,
2065 MDIO_PMA_DEVAD,
2066 MDIO_PMA_REG_CTRL,
2067 1<<15);
2068
2069 break;
ea4e040a
YR		 2070 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
2071 /* Unset Low Power Mode and SW reset */
2072 /* Restore normal power mode*/
2073 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
17de50b7
EG		 2074 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
2075 params->port);
ea4e040a
YR		 2076
2077 DP(NETIF_MSG_LINK, "XGXS 8072\n");
2078 bnx2x_cl45_write(bp, params->port,
2079 ext_phy_type,
2080 ext_phy_addr,
2081 MDIO_PMA_DEVAD,
2082 MDIO_PMA_REG_CTRL,
2083 1<<15);
2084 break;
2085 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
2086 {
ea4e040a
YR		 2087
2088 /* Restore normal power mode*/
2089 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
17de50b7
EG		 2090 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
2091 params->port);
ea4e040a
YR		 2092
2093 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
17de50b7
EG		 2094 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
2095 params->port);
ea4e040a
YR		 2096
2097 DP(NETIF_MSG_LINK, "XGXS 8073\n");
ea4e040a
YR		 2098 }
2099 break;
2100
2101 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
2102 DP(NETIF_MSG_LINK, "XGXS SFX7101\n");
2103
2104 /* Restore normal power mode*/
2105 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
17de50b7
EG		 2106 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
2107 params->port);
ea4e040a
YR		 2108
2109 /* HW reset */
f57a6025 2110 bnx2x_ext_phy_hw_reset(bp, params->port);
ea4e040a
YR		 2111 break;
2112
28577185
EG		 2113 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
2114
2115 /* Restore normal power mode*/
2116 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
2117 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
2118 params->port);
2119
2120 /* HW reset */
f57a6025 2121 bnx2x_ext_phy_hw_reset(bp, params->port);
28577185
EG		 2122
2123 bnx2x_cl45_write(bp, params->port,
2124 ext_phy_type,
2125 ext_phy_addr,
2126 MDIO_PMA_DEVAD,
2127 MDIO_PMA_REG_CTRL,
2128 1<<15);
2129 break;
ea4e040a
YR		 2130 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
2131 DP(NETIF_MSG_LINK, "XGXS PHY Failure detected\n");
2132 break;
2133
2134 default:
2135 DP(NETIF_MSG_LINK, "BAD XGXS ext_phy_config 0x%x\n",
2136 params->ext_phy_config);
2137 break;
2138 }
2139
2140 } else { /* SerDes */
2141 ext_phy_type = SERDES_EXT_PHY_TYPE(params->ext_phy_config);
2142 switch (ext_phy_type) {
2143 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT:
2144 DP(NETIF_MSG_LINK, "SerDes Direct\n");
2145 break;
2146
2147 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482:
2148 DP(NETIF_MSG_LINK, "SerDes 5482\n");
f57a6025 2149 bnx2x_ext_phy_hw_reset(bp, params->port);
ea4e040a
YR		 2150 break;
2151
2152 default:
2153 DP(NETIF_MSG_LINK,
2154 "BAD SerDes ext_phy_config 0x%x\n",
2155 params->ext_phy_config);
2156 break;
2157 }
2158 }
2159}
2160
a35da8db
EG		 2161
2162static void bnx2x_save_spirom_version(struct bnx2x *bp, u8 port,
2163 u32 shmem_base, u32 spirom_ver)
2164{
2165 DP(NETIF_MSG_LINK, "FW version 0x%x:0x%x\n",
2166 (u16)(spirom_ver>>16), (u16)spirom_ver);
2167 REG_WR(bp, shmem_base +
2168 offsetof(struct shmem_region,
2169 port_mb[port].ext_phy_fw_version),
2170 spirom_ver);
2171}
2172
2173static void bnx2x_save_bcm_spirom_ver(struct bnx2x *bp, u8 port,
2174 u32 ext_phy_type, u8 ext_phy_addr,
2175 u32 shmem_base)
2176{
2177 u16 fw_ver1, fw_ver2;
2178 bnx2x_cl45_read(bp, port, ext_phy_type, ext_phy_addr, MDIO_PMA_DEVAD,
2179 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
2180 bnx2x_cl45_read(bp, port, ext_phy_type, ext_phy_addr, MDIO_PMA_DEVAD,
2181 MDIO_PMA_REG_ROM_VER2, &fw_ver2);
2182 bnx2x_save_spirom_version(bp, port, shmem_base,
2183 (u32)(fw_ver1<<16 | fw_ver2));
2184}
2185
b1607af5
EG		 2186
2187static void bnx2x_save_8481_spirom_version(struct bnx2x *bp, u8 port,
2188 u8 ext_phy_addr, u32 shmem_base)
2189{
2190 u16 val, fw_ver1, fw_ver2, cnt;
2191 /* For the 32 bits registers in 8481, access via MDIO2ARM interface.*/
2192 /* (1) set register 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */
2193 bnx2x_cl45_write(bp, port,
2194 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
2195 ext_phy_addr, MDIO_PMA_DEVAD,
2196 0xA819, 0x0014);
2197 bnx2x_cl45_write(bp, port,
2198 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
2199 ext_phy_addr,
2200 MDIO_PMA_DEVAD,
2201 0xA81A,
2202 0xc200);
2203 bnx2x_cl45_write(bp, port,
2204 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
2205 ext_phy_addr,
2206 MDIO_PMA_DEVAD,
2207 0xA81B,
2208 0x0000);
2209 bnx2x_cl45_write(bp, port,
2210 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
2211 ext_phy_addr,
2212 MDIO_PMA_DEVAD,
2213 0xA81C,
2214 0x0300);
2215 bnx2x_cl45_write(bp, port,
2216 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
2217 ext_phy_addr,
2218 MDIO_PMA_DEVAD,
2219 0xA817,
2220 0x0009);
2221
2222 for (cnt = 0; cnt < 100; cnt++) {
2223 bnx2x_cl45_read(bp, port,
2224 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
2225 ext_phy_addr,
2226 MDIO_PMA_DEVAD,
2227 0xA818,
2228 &val);
2229 if (val & 1)
2230 break;
2231 udelay(5);
2232 }
2233 if (cnt == 100) {
2234 DP(NETIF_MSG_LINK, "Unable to read 8481 phy fw version(1)\n");
2235 bnx2x_save_spirom_version(bp, port,
2236 shmem_base, 0);
2237 return;
2238 }
2239
2240
2241 /* 2) read register 0xc200_0000 (SPI_FW_STATUS) */
2242 bnx2x_cl45_write(bp, port,
2243 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
2244 ext_phy_addr, MDIO_PMA_DEVAD,
2245 0xA819, 0x0000);
2246 bnx2x_cl45_write(bp, port,
2247 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
2248 ext_phy_addr, MDIO_PMA_DEVAD,
2249 0xA81A, 0xc200);
2250 bnx2x_cl45_write(bp, port,
2251 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
2252 ext_phy_addr, MDIO_PMA_DEVAD,
2253 0xA817, 0x000A);
2254 for (cnt = 0; cnt < 100; cnt++) {
2255 bnx2x_cl45_read(bp, port,
2256 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
2257 ext_phy_addr,
2258 MDIO_PMA_DEVAD,
2259 0xA818,
2260 &val);
2261 if (val & 1)
2262 break;
2263 udelay(5);
2264 }
2265 if (cnt == 100) {
2266 DP(NETIF_MSG_LINK, "Unable to read 8481 phy fw version(2)\n");
2267 bnx2x_save_spirom_version(bp, port,
2268 shmem_base, 0);
2269 return;
2270 }
2271
2272 /* lower 16 bits of the register SPI_FW_STATUS */
2273 bnx2x_cl45_read(bp, port,
2274 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
2275 ext_phy_addr,
2276 MDIO_PMA_DEVAD,
2277 0xA81B,
2278 &fw_ver1);
2279 /* upper 16 bits of register SPI_FW_STATUS */
2280 bnx2x_cl45_read(bp, port,
2281 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
2282 ext_phy_addr,
2283 MDIO_PMA_DEVAD,
2284 0xA81C,
2285 &fw_ver2);
2286
2287 bnx2x_save_spirom_version(bp, port,
2288 shmem_base, (fw_ver2<<16) | fw_ver1);
2289}
2290
ea4e040a
YR		 2291static void bnx2x_bcm8072_external_rom_boot(struct link_params *params)
2292{
2293 struct bnx2x *bp = params->bp;
2294 u8 port = params->port;
2295 u8 ext_phy_addr = ((params->ext_phy_config &
2296 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
2297 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
2298 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
ea4e040a
YR		 2299
2300 /* Need to wait 200ms after reset */
2301 msleep(200);
2302 /* Boot port from external ROM
2303 * Set ser_boot_ctl bit in the MISC_CTRL1 register
2304 */
2305 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2306 MDIO_PMA_DEVAD,
2307 MDIO_PMA_REG_MISC_CTRL1, 0x0001);
2308
2309 /* Reset internal microprocessor */
2310 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2311 MDIO_PMA_DEVAD,
2312 MDIO_PMA_REG_GEN_CTRL,
2313 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
2314 /* set micro reset = 0 */
2315 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2316 MDIO_PMA_DEVAD,
2317 MDIO_PMA_REG_GEN_CTRL,
2318 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
2319 /* Reset internal microprocessor */
2320 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2321 MDIO_PMA_DEVAD,
2322 MDIO_PMA_REG_GEN_CTRL,
2323 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
2324 /* wait for 100ms for code download via SPI port */
2325 msleep(100);
2326
2327 /* Clear ser_boot_ctl bit */
2328 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2329 MDIO_PMA_DEVAD,
2330 MDIO_PMA_REG_MISC_CTRL1, 0x0000);
2331 /* Wait 100ms */
2332 msleep(100);
2333
a35da8db
EG		 2334 bnx2x_save_bcm_spirom_ver(bp, port,
2335 ext_phy_type,
2336 ext_phy_addr,
2337 params->shmem_base);
ea4e040a
YR		 2338}
2339
2340static u8 bnx2x_8073_is_snr_needed(struct link_params *params)
2341{
2342 /* This is only required for 8073A1, version 102 only */
2343
2344 struct bnx2x *bp = params->bp;
2345 u8 ext_phy_addr = ((params->ext_phy_config &
2346 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
2347 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
2348 u16 val;
2349
2350 /* Read 8073 HW revision*/
2351 bnx2x_cl45_read(bp, params->port,
2352 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
2353 ext_phy_addr,
2354 MDIO_PMA_DEVAD,
052a38e0 2355 MDIO_PMA_REG_8073_CHIP_REV, &val);
ea4e040a
YR		 2356
2357 if (val != 1) {
2358 /* No need to workaround in 8073 A1 */
2359 return 0;
2360 }
2361
2362 bnx2x_cl45_read(bp, params->port,
2363 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
2364 ext_phy_addr,
2365 MDIO_PMA_DEVAD,
2366 MDIO_PMA_REG_ROM_VER2, &val);
2367
2368 /* SNR should be applied only for version 0x102 */
2369 if (val != 0x102)
2370 return 0;
2371
2372 return 1;
2373}
2374
2375static u8 bnx2x_bcm8073_xaui_wa(struct link_params *params)
2376{
2377 struct bnx2x *bp = params->bp;
2378 u8 ext_phy_addr = ((params->ext_phy_config &
2379 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
2380 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
2381 u16 val, cnt, cnt1 ;
2382
2383 bnx2x_cl45_read(bp, params->port,
2384 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
2385 ext_phy_addr,
2386 MDIO_PMA_DEVAD,
052a38e0 2387 MDIO_PMA_REG_8073_CHIP_REV, &val);
ea4e040a
YR		 2388
2389 if (val > 0) {
2390 /* No need to workaround in 8073 A1 */
2391 return 0;
2392 }
2393 /* XAUI workaround in 8073 A0: */
2394
2395 /* After loading the boot ROM and restarting Autoneg,
2396 poll Dev1, Reg $C820: */
2397
2398 for (cnt = 0; cnt < 1000; cnt++) {
2399 bnx2x_cl45_read(bp, params->port,
2400 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
2401 ext_phy_addr,
2402 MDIO_PMA_DEVAD,
052a38e0
EG		 2403 MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
2404 &val);
ea4e040a
YR		 2405 /* If bit [14] = 0 or bit [13] = 0, continue on with
2406 system initialization (XAUI work-around not required,
2407 as these bits indicate 2.5G or 1G link up). */
2408 if (!(val & (1<<14)) || !(val & (1<<13))) {
2409 DP(NETIF_MSG_LINK, "XAUI work-around not required\n");
2410 return 0;
2411 } else if (!(val & (1<<15))) {
2412 DP(NETIF_MSG_LINK, "clc bit 15 went off\n");
2413 /* If bit 15 is 0, then poll Dev1, Reg $C841 until
2414 it's MSB (bit 15) goes to 1 (indicating that the
2415 XAUI workaround has completed),
2416 then continue on with system initialization.*/
2417 for (cnt1 = 0; cnt1 < 1000; cnt1++) {
2418 bnx2x_cl45_read(bp, params->port,
2419 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
2420 ext_phy_addr,
2421 MDIO_PMA_DEVAD,
052a38e0 2422 MDIO_PMA_REG_8073_XAUI_WA, &val);
ea4e040a
YR		 2423 if (val & (1<<15)) {
2424 DP(NETIF_MSG_LINK,
2425 "XAUI workaround has completed\n");
2426 return 0;
2427 }
2428 msleep(3);
2429 }
2430 break;
2431 }
2432 msleep(3);
2433 }
2434 DP(NETIF_MSG_LINK, "Warning: XAUI work-around timeout !!!\n");
2435 return -EINVAL;
2436
2437}
2438
4d295db0
EG		 2439static void bnx2x_bcm8073_bcm8727_external_rom_boot(struct bnx2x *bp, u8 port,
2440 u8 ext_phy_addr,
2441 u32 ext_phy_type,
2442 u32 shmem_base)
ea4e040a 2443{
6bbca910 2444 /* Boot port from external ROM */
ea4e040a 2445 /* EDC grst */
6bbca910 2446 bnx2x_cl45_write(bp, port,
4d295db0 2447 ext_phy_type,
6bbca910 2448 ext_phy_addr,
ea4e040a
YR		 2449 MDIO_PMA_DEVAD,
2450 MDIO_PMA_REG_GEN_CTRL,
2451 0x0001);
2452
2453 /* ucode reboot and rst */
6bbca910 2454 bnx2x_cl45_write(bp, port,
4d295db0 2455 ext_phy_type,
6bbca910 2456 ext_phy_addr,
ea4e040a
YR		 2457 MDIO_PMA_DEVAD,
2458 MDIO_PMA_REG_GEN_CTRL,
2459 0x008c);
2460
6bbca910 2461 bnx2x_cl45_write(bp, port,
4d295db0 2462 ext_phy_type,
6bbca910 2463 ext_phy_addr,
ea4e040a
YR		 2464 MDIO_PMA_DEVAD,
2465 MDIO_PMA_REG_MISC_CTRL1, 0x0001);
2466
2467 /* Reset internal microprocessor */
6bbca910 2468 bnx2x_cl45_write(bp, port,
4d295db0 2469 ext_phy_type,
6bbca910 2470 ext_phy_addr,
ea4e040a
YR		 2471 MDIO_PMA_DEVAD,
2472 MDIO_PMA_REG_GEN_CTRL,
2473 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
2474
2475 /* Release srst bit */
6bbca910 2476 bnx2x_cl45_write(bp, port,
4d295db0 2477 ext_phy_type,
6bbca910 2478 ext_phy_addr,
ea4e040a
YR		 2479 MDIO_PMA_DEVAD,
2480 MDIO_PMA_REG_GEN_CTRL,
2481 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
2482
2483 /* wait for 100ms for code download via SPI port */
2484 msleep(100);
2485
2486 /* Clear ser_boot_ctl bit */
6bbca910 2487 bnx2x_cl45_write(bp, port,
4d295db0 2488 ext_phy_type,
6bbca910 2489 ext_phy_addr,
ea4e040a
YR		 2490 MDIO_PMA_DEVAD,
2491 MDIO_PMA_REG_MISC_CTRL1, 0x0000);
2492
a35da8db 2493 bnx2x_save_bcm_spirom_ver(bp, port,
4d295db0 2494 ext_phy_type,
a35da8db
EG		 2495 ext_phy_addr,
2496 shmem_base);
6bbca910 2497}
ea4e040a 2498
4d295db0
EG		 2499static void bnx2x_bcm8073_external_rom_boot(struct bnx2x *bp, u8 port,
2500 u8 ext_phy_addr,
2501 u32 shmem_base)
2502{
2503 bnx2x_bcm8073_bcm8727_external_rom_boot(bp, port, ext_phy_addr,
2504 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
2505 shmem_base);
2506}
2507
2508static void bnx2x_bcm8727_external_rom_boot(struct bnx2x *bp, u8 port,
2509 u8 ext_phy_addr,
2510 u32 shmem_base)
2511{
2512 bnx2x_bcm8073_bcm8727_external_rom_boot(bp, port, ext_phy_addr,
2513 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
2514 shmem_base);
2515
2516}
2517
589abe3a
EG		 2518static void bnx2x_bcm8726_external_rom_boot(struct link_params *params)
2519{
2520 struct bnx2x *bp = params->bp;
2521 u8 port = params->port;
2522 u8 ext_phy_addr = ((params->ext_phy_config &
2523 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
2524 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
2525 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
2526
2527 /* Need to wait 100ms after reset */
2528 msleep(100);
2529
2530 /* Set serial boot control for external load */
2531 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2532 MDIO_PMA_DEVAD,
2533 MDIO_PMA_REG_MISC_CTRL1, 0x0001);
2534
2535 /* Micro controller re-boot */
2536 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2537 MDIO_PMA_DEVAD,
2538 MDIO_PMA_REG_GEN_CTRL,
2539 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
2540
2541 /* Set soft reset */
2542 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2543 MDIO_PMA_DEVAD,
2544 MDIO_PMA_REG_GEN_CTRL,
2545 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
2546
4d295db0 2547 /* Set PLL register value to be same like in P13 ver */
cc1cb004
EG		 2548 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2549 MDIO_PMA_DEVAD,
4d295db0 2550 MDIO_PMA_REG_PLL_CTRL,
cc1cb004
EG		 2551 0x73A0);
2552
589abe3a
EG		 2553 /* Clear soft reset.
2554 Will automatically reset micro-controller re-boot */
2555 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2556 MDIO_PMA_DEVAD,
2557 MDIO_PMA_REG_GEN_CTRL,
2558 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
2559
cc1cb004
EG		 2560 /* wait for 150ms for microcode load */
2561 msleep(150);
589abe3a
EG		 2562
2563 /* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */
2564 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2565 MDIO_PMA_DEVAD,
2566 MDIO_PMA_REG_MISC_CTRL1, 0x0000);
2567
2568 msleep(200);
a35da8db
EG		 2569 bnx2x_save_bcm_spirom_ver(bp, port,
2570 ext_phy_type,
2571 ext_phy_addr,
2572 params->shmem_base);
589abe3a
EG		 2573}
2574
4d295db0
EG		 2575static void bnx2x_sfp_set_transmitter(struct bnx2x *bp, u8 port,
2576 u32 ext_phy_type, u8 ext_phy_addr,
2577 u8 tx_en)
589abe3a
EG		 2578{
2579 u16 val;
2580 DP(NETIF_MSG_LINK, "Setting transmitter tx_en=%x for port %x\n",
2581 tx_en, port);
2582 /* Disable/Enable transmitter ( TX laser of the SFP+ module.)*/
2583 bnx2x_cl45_read(bp, port,
4d295db0 2584 ext_phy_type,
589abe3a
EG		 2585 ext_phy_addr,
2586 MDIO_PMA_DEVAD,
2587 MDIO_PMA_REG_PHY_IDENTIFIER,
2588 &val);
2589
2590 if (tx_en)
2591 val &= ~(1<<15);
2592 else
2593 val |= (1<<15);
2594
2595 bnx2x_cl45_write(bp, port,
4d295db0 2596 ext_phy_type,
589abe3a
EG		 2597 ext_phy_addr,
2598 MDIO_PMA_DEVAD,
2599 MDIO_PMA_REG_PHY_IDENTIFIER,
2600 val);
2601}
2602
4d295db0
EG		 2603static u8 bnx2x_8726_read_sfp_module_eeprom(struct link_params *params,
2604 u16 addr, u8 byte_cnt, u8 *o_buf)
2605{
589abe3a 2606 struct bnx2x *bp = params->bp;
4d295db0
EG		 2607 u16 val = 0;
2608 u16 i;
589abe3a
EG		 2609 u8 port = params->port;
2610 u8 ext_phy_addr = ((params->ext_phy_config &
2611 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
2612 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
2613 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
2614 if (byte_cnt > 16) {
2615 DP(NETIF_MSG_LINK, "Reading from eeprom is"
2616 " is limited to 0xf\n");
2617 return -EINVAL;
2618 }
2619 /* Set the read command byte count */
2620 bnx2x_cl45_write(bp, port,
2621 ext_phy_type,
2622 ext_phy_addr,
2623 MDIO_PMA_DEVAD,
4d295db0 2624 MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
589abe3a
EG		 2625 (byte_cnt | 0xa000));
2626
2627 /* Set the read command address */
2628 bnx2x_cl45_write(bp, port,
2629 ext_phy_type,
2630 ext_phy_addr,
2631 MDIO_PMA_DEVAD,
4d295db0 2632 MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
589abe3a
EG		 2633 addr);
2634
2635 /* Activate read command */
2636 bnx2x_cl45_write(bp, port,
2637 ext_phy_type,
2638 ext_phy_addr,
2639 MDIO_PMA_DEVAD,
4d295db0 2640 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
589abe3a
EG		 2641 0x2c0f);
2642
2643 /* Wait up to 500us for command complete status */
2644 for (i = 0; i < 100; i++) {
2645 bnx2x_cl45_read(bp, port,
2646 ext_phy_type,
2647 ext_phy_addr,
2648 MDIO_PMA_DEVAD,
4d295db0
EG		 2649 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
2650 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
2651 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
589abe3a
EG		 2652 break;
2653 udelay(5);
2654 }
2655
4d295db0
EG		 2656 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
2657 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
589abe3a
EG		 2658 DP(NETIF_MSG_LINK,
2659 "Got bad status 0x%x when reading from SFP+ EEPROM\n",
4d295db0 2660 (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
589abe3a
EG		 2661 return -EINVAL;
2662 }
2663
2664 /* Read the buffer */
2665 for (i = 0; i < byte_cnt; i++) {
2666 bnx2x_cl45_read(bp, port,
2667 ext_phy_type,
2668 ext_phy_addr,
2669 MDIO_PMA_DEVAD,
2670 MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF + i, &val);
2671 o_buf[i] = (u8)(val & MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK);
2672 }
2673
2674 for (i = 0; i < 100; i++) {
2675 bnx2x_cl45_read(bp, port,
2676 ext_phy_type,
2677 ext_phy_addr,
2678 MDIO_PMA_DEVAD,
4d295db0
EG		 2679 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
2680 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
2681 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
2682 return 0;;
2683 msleep(1);
2684 }
2685 return -EINVAL;
2686}
2687
2688static u8 bnx2x_8727_read_sfp_module_eeprom(struct link_params *params,
2689 u16 addr, u8 byte_cnt, u8 *o_buf)
2690{
2691 struct bnx2x *bp = params->bp;
2692 u16 val, i;
2693 u8 port = params->port;
2694 u8 ext_phy_addr = ((params->ext_phy_config &
2695 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
2696 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
2697 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
2698
2699 if (byte_cnt > 16) {
2700 DP(NETIF_MSG_LINK, "Reading from eeprom is"
2701 " is limited to 0xf\n");
2702 return -EINVAL;
2703 }
2704
2705 /* Need to read from 1.8000 to clear it */
2706 bnx2x_cl45_read(bp, port,
2707 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
2708 ext_phy_addr,
2709 MDIO_PMA_DEVAD,
2710 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
2711 &val);
2712
2713 /* Set the read command byte count */
2714 bnx2x_cl45_write(bp, port,
2715 ext_phy_type,
2716 ext_phy_addr,
2717 MDIO_PMA_DEVAD,
2718 MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
2719 ((byte_cnt < 2) ? 2 : byte_cnt));
2720
2721 /* Set the read command address */
2722 bnx2x_cl45_write(bp, port,
2723 ext_phy_type,
2724 ext_phy_addr,
2725 MDIO_PMA_DEVAD,
2726 MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
2727 addr);
2728 /* Set the destination address */
2729 bnx2x_cl45_write(bp, port,
2730 ext_phy_type,
2731 ext_phy_addr,
2732 MDIO_PMA_DEVAD,
2733 0x8004,
2734 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF);
2735
2736 /* Activate read command */
2737 bnx2x_cl45_write(bp, port,
2738 ext_phy_type,
2739 ext_phy_addr,
2740 MDIO_PMA_DEVAD,
2741 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
2742 0x8002);
2743 /* Wait appropriate time for two-wire command to finish before
2744 polling the status register */
2745 msleep(1);
2746
2747 /* Wait up to 500us for command complete status */
2748 for (i = 0; i < 100; i++) {
2749 bnx2x_cl45_read(bp, port,
2750 ext_phy_type,
2751 ext_phy_addr,
2752 MDIO_PMA_DEVAD,
2753 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
2754 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
2755 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
2756 break;
2757 udelay(5);
2758 }
2759
2760 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
2761 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
2762 DP(NETIF_MSG_LINK,
2763 "Got bad status 0x%x when reading from SFP+ EEPROM\n",
2764 (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
2765 return -EINVAL;
2766 }
2767
2768 /* Read the buffer */
2769 for (i = 0; i < byte_cnt; i++) {
2770 bnx2x_cl45_read(bp, port,
2771 ext_phy_type,
2772 ext_phy_addr,
2773 MDIO_PMA_DEVAD,
2774 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF + i, &val);
2775 o_buf[i] = (u8)(val & MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK);
2776 }
2777
2778 for (i = 0; i < 100; i++) {
2779 bnx2x_cl45_read(bp, port,
2780 ext_phy_type,
2781 ext_phy_addr,
2782 MDIO_PMA_DEVAD,
2783 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
2784 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
2785 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
589abe3a
EG		 2786 return 0;;
2787 msleep(1);
2788 }
4d295db0 2789
589abe3a
EG		 2790 return -EINVAL;
2791}
2792
4d295db0
EG		 2793u8 bnx2x_read_sfp_module_eeprom(struct link_params *params, u16 addr,
2794 u8 byte_cnt, u8 *o_buf)
2795{
2796 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
2797
2798 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726)
2799 return bnx2x_8726_read_sfp_module_eeprom(params, addr,
2800 byte_cnt, o_buf);
2801 else if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727)
2802 return bnx2x_8727_read_sfp_module_eeprom(params, addr,
2803 byte_cnt, o_buf);
2804 return -EINVAL;
2805}
589abe3a 2806
4d295db0
EG		 2807static u8 bnx2x_get_edc_mode(struct link_params *params,
2808 u16 *edc_mode)
589abe3a
EG		 2809{
2810 struct bnx2x *bp = params->bp;
4d295db0
EG		 2811 u8 val, check_limiting_mode = 0;
2812 *edc_mode = EDC_MODE_LIMITING;
589abe3a
EG		 2813
2814 /* First check for copper cable */
2815 if (bnx2x_read_sfp_module_eeprom(params,
2816 SFP_EEPROM_CON_TYPE_ADDR,
2817 1,
2818 &val) != 0) {
4d295db0 2819 DP(NETIF_MSG_LINK, "Failed to read from SFP+ module EEPROM\n");
589abe3a
EG		 2820 return -EINVAL;
2821 }
2822
2823 switch (val) {
2824 case SFP_EEPROM_CON_TYPE_VAL_COPPER:
2825 {
2826 u8 copper_module_type;
2827 /* Check if its active cable( includes SFP+ module)
2828 of passive cable*/
2829 if (bnx2x_read_sfp_module_eeprom(params,
2830 SFP_EEPROM_FC_TX_TECH_ADDR,
2831 1,
2832 &copper_module_type) !=
2833 0) {
2834 DP(NETIF_MSG_LINK,
2835 "Failed to read copper-cable-type"
2836 " from SFP+ EEPROM\n");
2837 return -EINVAL;
2838 }
2839
2840 if (copper_module_type &
2841 SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) {
2842 DP(NETIF_MSG_LINK, "Active Copper cable detected\n");
4d295db0 2843 check_limiting_mode = 1;
589abe3a
EG		 2844 } else if (copper_module_type &
2845 SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE) {
2846 DP(NETIF_MSG_LINK, "Passive Copper"
2847 " cable detected\n");
4d295db0
EG		 2848 *edc_mode =
2849 EDC_MODE_PASSIVE_DAC;
589abe3a
EG		 2850 } else {
2851 DP(NETIF_MSG_LINK, "Unknown copper-cable-"
2852 "type 0x%x !!!\n", copper_module_type);
2853 return -EINVAL;
2854 }
2855 break;
2856 }
2857 case SFP_EEPROM_CON_TYPE_VAL_LC:
2858 DP(NETIF_MSG_LINK, "Optic module detected\n");
4d295db0 2859 check_limiting_mode = 1;
589abe3a
EG		 2860 break;
2861
2862 default:
2863 DP(NETIF_MSG_LINK, "Unable to determine module type 0x%x !!!\n",
2864 val);
2865 return -EINVAL;
2866 }
4d295db0
EG		 2867
2868 if (check_limiting_mode) {
2869 u8 options[SFP_EEPROM_OPTIONS_SIZE];
2870 if (bnx2x_read_sfp_module_eeprom(params,
2871 SFP_EEPROM_OPTIONS_ADDR,
2872 SFP_EEPROM_OPTIONS_SIZE,
2873 options) != 0) {
2874 DP(NETIF_MSG_LINK, "Failed to read Option"
2875 " field from module EEPROM\n");
2876 return -EINVAL;
2877 }
2878 if ((options[0] & SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK))
2879 *edc_mode = EDC_MODE_LINEAR;
2880 else
2881 *edc_mode = EDC_MODE_LIMITING;
2882 }
2883 DP(NETIF_MSG_LINK, "EDC mode is set to 0x%x\n", *edc_mode);
589abe3a
EG		 2884 return 0;
2885}
2886
589abe3a
EG		 2887/* This function read the relevant field from the module ( SFP+ ),
2888 and verify it is compliant with this board */
4d295db0 2889static u8 bnx2x_verify_sfp_module(struct link_params *params)
589abe3a
EG		 2890{
2891 struct bnx2x *bp = params->bp;
4d295db0
EG		 2892 u32 val;
2893 u32 fw_resp;
2894 char vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE+1];
2895 char vendor_pn[SFP_EEPROM_PART_NO_SIZE+1];
2896
2897 val = REG_RD(bp, params->shmem_base +
2898 offsetof(struct shmem_region, dev_info.
2899 port_feature_config[params->port].config));
2900 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
2901 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT) {
589abe3a
EG		 2902 DP(NETIF_MSG_LINK, "NOT enforcing module verification\n");
2903 return 0;
2904 }
2905
4d295db0
EG		 2906 /* Ask the FW to validate the module */
2907 if (!(params->feature_config_flags &
2908 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY)) {
2909 DP(NETIF_MSG_LINK, "FW does not support OPT MDL "
2910 "verification\n");
2911 return -EINVAL;
2912 }
2913
2914 fw_resp = bnx2x_fw_command(bp, DRV_MSG_CODE_VRFY_OPT_MDL);
2915 if (fw_resp == FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS) {
2916 DP(NETIF_MSG_LINK, "Approved module\n");
589abe3a
EG		 2917 return 0;
2918 }
2919
4d295db0 2920 /* format the warning message */
589abe3a
EG		 2921 if (bnx2x_read_sfp_module_eeprom(params,
2922 SFP_EEPROM_VENDOR_NAME_ADDR,
2923 SFP_EEPROM_VENDOR_NAME_SIZE,
4d295db0
EG		 2924 (u8 *)vendor_name))
2925 vendor_name[0] = '\0';
2926 else
2927 vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE] = '\0';
2928 if (bnx2x_read_sfp_module_eeprom(params,
2929 SFP_EEPROM_PART_NO_ADDR,
2930 SFP_EEPROM_PART_NO_SIZE,
2931 (u8 *)vendor_pn))
2932 vendor_pn[0] = '\0';
2933 else
2934 vendor_pn[SFP_EEPROM_PART_NO_SIZE] = '\0';
589abe3a 2935
4d295db0
EG		 2936 printk(KERN_INFO PFX "Warning: "
2937 "Unqualified SFP+ module "
2938 "detected on %s, Port %d from %s part number %s\n"
2939 , bp->dev->name, params->port,
2940 vendor_name, vendor_pn);
589abe3a
EG		 2941 return -EINVAL;
2942}
2943
589abe3a 2944static u8 bnx2x_bcm8726_set_limiting_mode(struct link_params *params,
4d295db0 2945 u16 edc_mode)
589abe3a
EG		 2946{
2947 struct bnx2x *bp = params->bp;
2948 u8 port = params->port;
589abe3a
EG		 2949 u8 ext_phy_addr = ((params->ext_phy_config &
2950 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
2951 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
cc1cb004 2952 u16 cur_limiting_mode;
cc1cb004
EG		 2953
2954 bnx2x_cl45_read(bp, port,
2955 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
2956 ext_phy_addr,
2957 MDIO_PMA_DEVAD,
2958 MDIO_PMA_REG_ROM_VER2,
2959 &cur_limiting_mode);
2960 DP(NETIF_MSG_LINK, "Current Limiting mode is 0x%x\n",
2961 cur_limiting_mode);
2962
4d295db0 2963 if (edc_mode == EDC_MODE_LIMITING) {
589abe3a 2964 DP(NETIF_MSG_LINK,
4d295db0 2965 "Setting LIMITING MODE\n");
589abe3a
EG		 2966 bnx2x_cl45_write(bp, port,
2967 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
2968 ext_phy_addr,
2969 MDIO_PMA_DEVAD,
2970 MDIO_PMA_REG_ROM_VER2,
4d295db0 2971 EDC_MODE_LIMITING);
589abe3a 2972 } else { /* LRM mode ( default )*/
cc1cb004 2973
4d295db0 2974 DP(NETIF_MSG_LINK, "Setting LRM MODE\n");
589abe3a 2975
589abe3a
EG		 2976 /* Changing to LRM mode takes quite few seconds.
2977 So do it only if current mode is limiting
2978 ( default is LRM )*/
4d295db0 2979 if (cur_limiting_mode != EDC_MODE_LIMITING)
589abe3a
EG		 2980 return 0;
2981
2982 bnx2x_cl45_write(bp, port,
2983 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
2984 ext_phy_addr,
2985 MDIO_PMA_DEVAD,
2986 MDIO_PMA_REG_LRM_MODE,
2987 0);
2988 bnx2x_cl45_write(bp, port,
2989 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
2990 ext_phy_addr,
2991 MDIO_PMA_DEVAD,
2992 MDIO_PMA_REG_ROM_VER2,
2993 0x128);
2994 bnx2x_cl45_write(bp, port,
2995 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
2996 ext_phy_addr,
2997 MDIO_PMA_DEVAD,
2998 MDIO_PMA_REG_MISC_CTRL0,
2999 0x4008);
3000 bnx2x_cl45_write(bp, port,
3001 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
3002 ext_phy_addr,
3003 MDIO_PMA_DEVAD,
3004 MDIO_PMA_REG_LRM_MODE,
3005 0xaaaa);
3006 }
3007 return 0;
3008}
3009
4d295db0
EG		 3010static u8 bnx2x_bcm8727_set_limiting_mode(struct link_params *params,
3011 u16 edc_mode)
3012{
3013 struct bnx2x *bp = params->bp;
3014 u8 port = params->port;
3015 u16 phy_identifier;
3016 u16 rom_ver2_val;
3017 u8 ext_phy_addr = ((params->ext_phy_config &
3018 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
3019 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
3020
3021 bnx2x_cl45_read(bp, port,
3022 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
3023 ext_phy_addr,
3024 MDIO_PMA_DEVAD,
3025 MDIO_PMA_REG_PHY_IDENTIFIER,
3026 &phy_identifier);
3027
3028 bnx2x_cl45_write(bp, port,
3029 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
3030 ext_phy_addr,
3031 MDIO_PMA_DEVAD,
3032 MDIO_PMA_REG_PHY_IDENTIFIER,
3033 (phy_identifier & ~(1<<9)));
3034
3035 bnx2x_cl45_read(bp, port,
3036 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
3037 ext_phy_addr,
3038 MDIO_PMA_DEVAD,
3039 MDIO_PMA_REG_ROM_VER2,
3040 &rom_ver2_val);
3041 /* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */
3042 bnx2x_cl45_write(bp, port,
3043 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
3044 ext_phy_addr,
3045 MDIO_PMA_DEVAD,
3046 MDIO_PMA_REG_ROM_VER2,
3047 (rom_ver2_val & 0xff00) | (edc_mode & 0x00ff));
3048
3049 bnx2x_cl45_write(bp, port,
3050 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
3051 ext_phy_addr,
3052 MDIO_PMA_DEVAD,
3053 MDIO_PMA_REG_PHY_IDENTIFIER,
3054 (phy_identifier | (1<<9)));
3055
3056 return 0;
3057}
3058
3059
589abe3a
EG		 3060static u8 bnx2x_wait_for_sfp_module_initialized(struct link_params *params)
3061{
3062 u8 val;
3063 struct bnx2x *bp = params->bp;
3064 u16 timeout;
3065 /* Initialization time after hot-plug may take up to 300ms for some
3066 phys type ( e.g. JDSU ) */
3067 for (timeout = 0; timeout < 60; timeout++) {
3068 if (bnx2x_read_sfp_module_eeprom(params, 1, 1, &val)
3069 == 0) {
3070 DP(NETIF_MSG_LINK, "SFP+ module initialization "
3071 "took %d ms\n", timeout * 5);
3072 return 0;
3073 }
3074 msleep(5);
3075 }
3076 return -EINVAL;
3077}
3078
4d295db0
EG		 3079static void bnx2x_8727_power_module(struct bnx2x *bp,
3080 struct link_params *params,
3081 u8 ext_phy_addr, u8 is_power_up) {
3082 /* Make sure GPIOs are not using for LED mode */
3083 u16 val;
3084 u8 port = params->port;
3085 /*
3086 * In the GPIO register, bit 4 is use to detemine if the GPIOs are
3087 * operating as INPUT or as OUTPUT. Bit 1 is for input, and 0 for
3088 * output
3089 * Bits 0-1 determine the gpios value for OUTPUT in case bit 4 val is 0
3090 * Bits 8-9 determine the gpios value for INPUT in case bit 4 val is 1
3091 * where the 1st bit is the over-current(only input), and 2nd bit is
3092 * for power( only output )
3093 */
3094
3095 /*
3096 * In case of NOC feature is disabled and power is up, set GPIO control
3097 * as input to enable listening of over-current indication
3098 */
3099
3100 if (!(params->feature_config_flags &
3101 FEATURE_CONFIG_BCM8727_NOC) && is_power_up)
3102 val = (1<<4);
3103 else
3104 /*
3105 * Set GPIO control to OUTPUT, and set the power bit
3106 * to according to the is_power_up
3107 */
3108 val = ((!(is_power_up)) << 1);
3109
3110 bnx2x_cl45_write(bp, port,
3111 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
3112 ext_phy_addr,
3113 MDIO_PMA_DEVAD,
3114 MDIO_PMA_REG_8727_GPIO_CTRL,
3115 val);
3116}
3117
589abe3a
EG		 3118static u8 bnx2x_sfp_module_detection(struct link_params *params)
3119{
3120 struct bnx2x *bp = params->bp;
4d295db0
EG		 3121 u16 edc_mode;
3122 u8 rc = 0;
589abe3a
EG		 3123 u8 ext_phy_addr = ((params->ext_phy_config &
3124 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
3125 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
3126 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
4d295db0
EG		 3127 u32 val = REG_RD(bp, params->shmem_base +
3128 offsetof(struct shmem_region, dev_info.
3129 port_feature_config[params->port].config));
589abe3a
EG		 3130
3131 DP(NETIF_MSG_LINK, "SFP+ module plugged in/out detected on port %d\n",
3132 params->port);
3133
4d295db0 3134 if (bnx2x_get_edc_mode(params, &edc_mode) != 0) {
589abe3a 3135 DP(NETIF_MSG_LINK, "Failed to get valid module type\n");
4d295db0
EG		 3136 return -EINVAL;
3137 } else if (bnx2x_verify_sfp_module(params) !=
589abe3a
EG		 3138 0) {
3139 /* check SFP+ module compatibility */
3140 DP(NETIF_MSG_LINK, "Module verification failed!!\n");
4d295db0 3141 rc = -EINVAL;
589abe3a
EG		 3142 /* Turn on fault module-detected led */
3143 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
3144 MISC_REGISTERS_GPIO_HIGH,
3145 params->port);
4d295db0
EG		 3146 if ((ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) &&
3147 ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
3148 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN)) {
3149 /* Shutdown SFP+ module */
3150 DP(NETIF_MSG_LINK, "Shutdown SFP+ module!!\n");
3151 bnx2x_8727_power_module(bp, params,
3152 ext_phy_addr, 0);
3153 return rc;
3154 }
3155 } else {
3156 /* Turn off fault module-detected led */
3157 DP(NETIF_MSG_LINK, "Turn off fault module-detected led\n");
3158 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
3159 MISC_REGISTERS_GPIO_LOW,
3160 params->port);
589abe3a
EG		 3161 }
3162
4d295db0
EG		 3163 /* power up the SFP module */
3164 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727)
3165 bnx2x_8727_power_module(bp, params, ext_phy_addr, 1);
589abe3a 3166
4d295db0
EG		 3167 /* Check and set limiting mode / LRM mode on 8726.
3168 On 8727 it is done automatically */
3169 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726)
3170 bnx2x_bcm8726_set_limiting_mode(params, edc_mode);
3171 else
3172 bnx2x_bcm8727_set_limiting_mode(params, edc_mode);
3173 /*
3174 * Enable transmit for this module if the module is approved, or
3175 * if unapproved modules should also enable the Tx laser
3176 */
3177 if (rc == 0 ||
3178 (val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) !=
3179 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
3180 bnx2x_sfp_set_transmitter(bp, params->port,
3181 ext_phy_type, ext_phy_addr, 1);
3182 else
3183 bnx2x_sfp_set_transmitter(bp, params->port,
3184 ext_phy_type, ext_phy_addr, 0);
589abe3a 3185
4d295db0 3186 return rc;
589abe3a
EG		 3187}
3188
3189void bnx2x_handle_module_detect_int(struct link_params *params)
3190{
3191 struct bnx2x *bp = params->bp;
3192 u32 gpio_val;
3193 u8 port = params->port;
3194 /* Set valid module led off */
3195 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
3196 MISC_REGISTERS_GPIO_HIGH,
3197 params->port);
3198
3199 /* Get current gpio val refelecting module plugged in / out*/
3200 gpio_val = bnx2x_get_gpio(bp, MISC_REGISTERS_GPIO_3, port);
3201
3202 /* Call the handling function in case module is detected */
3203 if (gpio_val == 0) {
3204
3205 bnx2x_set_gpio_int(bp, MISC_REGISTERS_GPIO_3,
3206 MISC_REGISTERS_GPIO_INT_OUTPUT_CLR,
3207 port);
3208
4d295db0
EG		 3209 if (bnx2x_wait_for_sfp_module_initialized(params) ==
3210 0)
589abe3a
EG		 3211 bnx2x_sfp_module_detection(params);
3212 else
3213 DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
3214 } else {
3215 u8 ext_phy_addr = ((params->ext_phy_config &
3216 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
3217 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
4d295db0
EG		 3218 u32 ext_phy_type =
3219 XGXS_EXT_PHY_TYPE(params->ext_phy_config);
3220 u32 val = REG_RD(bp, params->shmem_base +
3221 offsetof(struct shmem_region, dev_info.
3222 port_feature_config[params->port].
3223 config));
3224
589abe3a
EG		 3225 bnx2x_set_gpio_int(bp, MISC_REGISTERS_GPIO_3,
3226 MISC_REGISTERS_GPIO_INT_OUTPUT_SET,
3227 port);
3228 /* Module was plugged out. */
3229 /* Disable transmit for this module */
4d295db0
EG		 3230 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
3231 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
3232 bnx2x_sfp_set_transmitter(bp, params->port,
3233 ext_phy_type, ext_phy_addr, 0);
589abe3a
EG		 3234 }
3235}
3236
6bbca910
YR		 3237static void bnx2x_bcm807x_force_10G(struct link_params *params)
3238{
3239 struct bnx2x *bp = params->bp;
3240 u8 port = params->port;
3241 u8 ext_phy_addr = ((params->ext_phy_config &
3242 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
3243 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
3244 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
3245
3246 /* Force KR or KX */
ea4e040a
YR		 3247 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
3248 MDIO_PMA_DEVAD,
6bbca910
YR		 3249 MDIO_PMA_REG_CTRL,
3250 0x2040);
ea4e040a
YR		 3251 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
3252 MDIO_PMA_DEVAD,
6bbca910
YR		 3253 MDIO_PMA_REG_10G_CTRL2,
3254 0x000b);
3255 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
3256 MDIO_PMA_DEVAD,
3257 MDIO_PMA_REG_BCM_CTRL,
3258 0x0000);
3259 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
3260 MDIO_AN_DEVAD,
3261 MDIO_AN_REG_CTRL,
3262 0x0000);
ea4e040a 3263}
ea4e040a
YR		 3264static void bnx2x_bcm8073_set_xaui_low_power_mode(struct link_params *params)
3265{
3266 struct bnx2x *bp = params->bp;
3267 u8 port = params->port;
3268 u16 val;
3269 u8 ext_phy_addr = ((params->ext_phy_config &
3270 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
3271 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
3272 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
3273
3274 bnx2x_cl45_read(bp, params->port,
3275 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
3276 ext_phy_addr,
3277 MDIO_PMA_DEVAD,
052a38e0 3278 MDIO_PMA_REG_8073_CHIP_REV, &val);
ea4e040a
YR		 3279
3280 if (val == 0) {
3281 /* Mustn't set low power mode in 8073 A0 */
3282 return;
3283 }
3284
3285 /* Disable PLL sequencer (use read-modify-write to clear bit 13) */
3286 bnx2x_cl45_read(bp, port, ext_phy_type, ext_phy_addr,
3287 MDIO_XS_DEVAD,
3288 MDIO_XS_PLL_SEQUENCER, &val);
3289 val &= ~(1<<13);
3290 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
3291 MDIO_XS_DEVAD, MDIO_XS_PLL_SEQUENCER, val);
3292
3293 /* PLL controls */
3294 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
3295 MDIO_XS_DEVAD, 0x805E, 0x1077);
3296 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
3297 MDIO_XS_DEVAD, 0x805D, 0x0000);
3298 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
3299 MDIO_XS_DEVAD, 0x805C, 0x030B);
3300 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
3301 MDIO_XS_DEVAD, 0x805B, 0x1240);
3302 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
3303 MDIO_XS_DEVAD, 0x805A, 0x2490);
3304
3305 /* Tx Controls */
3306 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
3307 MDIO_XS_DEVAD, 0x80A7, 0x0C74);
3308 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
3309 MDIO_XS_DEVAD, 0x80A6, 0x9041);
3310 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
3311 MDIO_XS_DEVAD, 0x80A5, 0x4640);
3312
3313 /* Rx Controls */
3314 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
3315 MDIO_XS_DEVAD, 0x80FE, 0x01C4);
3316 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
3317 MDIO_XS_DEVAD, 0x80FD, 0x9249);
3318 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
3319 MDIO_XS_DEVAD, 0x80FC, 0x2015);
3320
3321 /* Enable PLL sequencer (use read-modify-write to set bit 13) */
3322 bnx2x_cl45_read(bp, port, ext_phy_type, ext_phy_addr,
3323 MDIO_XS_DEVAD,
3324 MDIO_XS_PLL_SEQUENCER, &val);
3325 val |= (1<<13);
3326 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
3327 MDIO_XS_DEVAD, MDIO_XS_PLL_SEQUENCER, val);
3328}
6bbca910
YR		 3329
3330static void bnx2x_8073_set_pause_cl37(struct link_params *params,
3331 struct link_vars *vars)
ea4e040a 3332{
6bbca910 3333
ea4e040a 3334 struct bnx2x *bp = params->bp;
6bbca910 3335 u16 cl37_val;
ea4e040a
YR		 3336 u8 ext_phy_addr = ((params->ext_phy_config &
3337 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
3338 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
3339 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
3340
6bbca910
YR		 3341 bnx2x_cl45_read(bp, params->port,
3342 ext_phy_type,
3343 ext_phy_addr,
3344 MDIO_AN_DEVAD,
3345 MDIO_AN_REG_CL37_FC_LD, &cl37_val);
3346
3347 cl37_val &= ~MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3348 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
3349
3350 if ((vars->ieee_fc &
3351 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) ==
3352 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) {
3353 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC;
3354 }
3355 if ((vars->ieee_fc &
3356 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
3357 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
3358 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
3359 }
3360 if ((vars->ieee_fc &
3361 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
3362 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
3363 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3364 }
3365 DP(NETIF_MSG_LINK,
3366 "Ext phy AN advertize cl37 0x%x\n", cl37_val);
3367
3368 bnx2x_cl45_write(bp, params->port,
3369 ext_phy_type,
3370 ext_phy_addr,
ea4e040a 3371 MDIO_AN_DEVAD,
6bbca910
YR		 3372 MDIO_AN_REG_CL37_FC_LD, cl37_val);
3373 msleep(500);
ea4e040a
YR		 3374}
3375
3376static void bnx2x_ext_phy_set_pause(struct link_params *params,
3377 struct link_vars *vars)
3378{
3379 struct bnx2x *bp = params->bp;
3380 u16 val;
3381 u8 ext_phy_addr = ((params->ext_phy_config &
3382 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
3383 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
3384 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
3385
3386 /* read modify write pause advertizing */
3387 bnx2x_cl45_read(bp, params->port,
3388 ext_phy_type,
3389 ext_phy_addr,
3390 MDIO_AN_DEVAD,
3391 MDIO_AN_REG_ADV_PAUSE, &val);
3392
3393 val &= ~MDIO_AN_REG_ADV_PAUSE_BOTH;
8c99e7b0 3394
ea4e040a
YR		 3395 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
3396
8c99e7b0
YR		 3397 if ((vars->ieee_fc &
3398 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
ea4e040a
YR		 3399 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
3400 val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
3401 }
8c99e7b0
YR		 3402 if ((vars->ieee_fc &
3403 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
ea4e040a
YR		 3404 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
3405 val |=
3406 MDIO_AN_REG_ADV_PAUSE_PAUSE;
3407 }
3408 DP(NETIF_MSG_LINK,
3409 "Ext phy AN advertize 0x%x\n", val);
3410 bnx2x_cl45_write(bp, params->port,
3411 ext_phy_type,
3412 ext_phy_addr,
3413 MDIO_AN_DEVAD,
3414 MDIO_AN_REG_ADV_PAUSE, val);
3415}
c2c8b03e
EG		 3416static void bnx2x_set_preemphasis(struct link_params *params)
3417{
3418 u16 bank, i = 0;
3419 struct bnx2x *bp = params->bp;
ea4e040a 3420
c2c8b03e
EG		 3421 for (bank = MDIO_REG_BANK_RX0, i = 0; bank <= MDIO_REG_BANK_RX3;
3422 bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0), i++) {
3423 CL45_WR_OVER_CL22(bp, params->port,
3424 params->phy_addr,
3425 bank,
3426 MDIO_RX0_RX_EQ_BOOST,
3427 params->xgxs_config_rx[i]);
3428 }
3429
3430 for (bank = MDIO_REG_BANK_TX0, i = 0; bank <= MDIO_REG_BANK_TX3;
3431 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0), i++) {
3432 CL45_WR_OVER_CL22(bp, params->port,
3433 params->phy_addr,
3434 bank,
3435 MDIO_TX0_TX_DRIVER,
3436 params->xgxs_config_tx[i]);
3437 }
3438}
57963ed9 3439
2f904460
EG		 3440
3441static void bnx2x_8481_set_led4(struct link_params *params,
3442 u32 ext_phy_type, u8 ext_phy_addr)
3443{
3444 struct bnx2x *bp = params->bp;
3445
3446 /* PHYC_CTL_LED_CTL */
3447 bnx2x_cl45_write(bp, params->port,
3448 ext_phy_type,
3449 ext_phy_addr,
3450 MDIO_PMA_DEVAD,
3451 MDIO_PMA_REG_8481_LINK_SIGNAL, 0xa482);
3452
3453 /* Unmask LED4 for 10G link */
3454 bnx2x_cl45_write(bp, params->port,
3455 ext_phy_type,
3456 ext_phy_addr,
3457 MDIO_PMA_DEVAD,
3458 MDIO_PMA_REG_8481_SIGNAL_MASK, (1<<6));
3459 /* 'Interrupt Mask' */
3460 bnx2x_cl45_write(bp, params->port,
3461 ext_phy_type,
3462 ext_phy_addr,
3463 MDIO_AN_DEVAD,
3464 0xFFFB, 0xFFFD);
3465}
3466static void bnx2x_8481_set_legacy_led_mode(struct link_params *params,
3467 u32 ext_phy_type, u8 ext_phy_addr)
3468{
3469 struct bnx2x *bp = params->bp;
3470
3471 /* LED1 (10G Link): Disable LED1 when 10/100/1000 link */
3472 /* LED2 (1G/100/10 Link): Enable LED2 when 10/100/1000 link) */
3473 bnx2x_cl45_write(bp, params->port,
3474 ext_phy_type,
3475 ext_phy_addr,
3476 MDIO_AN_DEVAD,
3477 MDIO_AN_REG_8481_LEGACY_SHADOW,
3478 (1<<15) | (0xd << 10) | (0xc<<4) | 0xe);
3479}
3480
3481static void bnx2x_8481_set_10G_led_mode(struct link_params *params,
3482 u32 ext_phy_type, u8 ext_phy_addr)
3483{
3484 struct bnx2x *bp = params->bp;
3485 u16 val1;
3486
3487 /* LED1 (10G Link) */
3488 /* Enable continuse based on source 7(10G-link) */
3489 bnx2x_cl45_read(bp, params->port,
3490 ext_phy_type,
3491 ext_phy_addr,
3492 MDIO_PMA_DEVAD,
3493 MDIO_PMA_REG_8481_LINK_SIGNAL,
3494 &val1);
3495 /* Set bit 2 to 0, and bits [1:0] to 10 */
3496 val1 &= ~((1<<0) | (1<<2)); /* Clear bits 0,2*/
3497 val1 |= (1<<1); /* Set bit 1 */
3498
3499 bnx2x_cl45_write(bp, params->port,
3500 ext_phy_type,
3501 ext_phy_addr,
3502 MDIO_PMA_DEVAD,
3503 MDIO_PMA_REG_8481_LINK_SIGNAL,
3504 val1);
3505
3506 /* Unmask LED1 for 10G link */
3507 bnx2x_cl45_read(bp, params->port,
3508 ext_phy_type,
3509 ext_phy_addr,
3510 MDIO_PMA_DEVAD,
3511 MDIO_PMA_REG_8481_LED1_MASK,
3512 &val1);
3513 /* Set bit 2 to 0, and bits [1:0] to 10 */
3514 val1 |= (1<<7);
3515 bnx2x_cl45_write(bp, params->port,
3516 ext_phy_type,
3517 ext_phy_addr,
3518 MDIO_PMA_DEVAD,
3519 MDIO_PMA_REG_8481_LED1_MASK,
3520 val1);
3521
3522 /* LED2 (1G/100/10G Link) */
3523 /* Mask LED2 for 10G link */
3524 bnx2x_cl45_write(bp, params->port,
3525 ext_phy_type,
3526 ext_phy_addr,
3527 MDIO_PMA_DEVAD,
3528 MDIO_PMA_REG_8481_LED2_MASK,
3529 0);
3530
3531 /* LED3 (10G/1G/100/10G Activity) */
3532 bnx2x_cl45_read(bp, params->port,
3533 ext_phy_type,
3534 ext_phy_addr,
3535 MDIO_PMA_DEVAD,
3536 MDIO_PMA_REG_8481_LINK_SIGNAL,
3537 &val1);
3538 /* Enable blink based on source 4(Activity) */
3539 val1 &= ~((1<<7) | (1<<8)); /* Clear bits 7,8 */
3540 val1 |= (1<<6); /* Set only bit 6 */
3541 bnx2x_cl45_write(bp, params->port,
3542 ext_phy_type,
3543 ext_phy_addr,
3544 MDIO_PMA_DEVAD,
3545 MDIO_PMA_REG_8481_LINK_SIGNAL,
3546 val1);
3547
3548 bnx2x_cl45_read(bp, params->port,
3549 ext_phy_type,
3550 ext_phy_addr,
3551 MDIO_PMA_DEVAD,
3552 MDIO_PMA_REG_8481_LED3_MASK,
3553 &val1);
3554 val1 |= (1<<4); /* Unmask LED3 for 10G link */
3555 bnx2x_cl45_write(bp, params->port,
3556 ext_phy_type,
3557 ext_phy_addr,
3558 MDIO_PMA_DEVAD,
3559 MDIO_PMA_REG_8481_LED3_MASK,
3560 val1);
3561}
3562
3563
57963ed9 3564static void bnx2x_init_internal_phy(struct link_params *params,
239d686d
EG		 3565 struct link_vars *vars,
3566 u8 enable_cl73)
57963ed9
YR		 3567{
3568 struct bnx2x *bp = params->bp;
57963ed9 3569 if (!(vars->phy_flags & PHY_SGMII_FLAG)) {
c2c8b03e
EG		 3570 if ((XGXS_EXT_PHY_TYPE(params->ext_phy_config) ==
3571 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
3572 (params->feature_config_flags &
3573 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED))
3574 bnx2x_set_preemphasis(params);
57963ed9
YR		 3575
3576 /* forced speed requested? */
3577 if (vars->line_speed != SPEED_AUTO_NEG) {
3578 DP(NETIF_MSG_LINK, "not SGMII, no AN\n");
3579
3580 /* disable autoneg */
239d686d 3581 bnx2x_set_autoneg(params, vars, 0);
57963ed9
YR		 3582
3583 /* program speed and duplex */
8c99e7b0 3584 bnx2x_program_serdes(params, vars);
57963ed9
YR		 3585
3586 } else { /* AN_mode */
3587 DP(NETIF_MSG_LINK, "not SGMII, AN\n");
3588
3589 /* AN enabled */
3590 bnx2x_set_brcm_cl37_advertisment(params);
3591
3592 /* program duplex & pause advertisement (for aneg) */
3593 bnx2x_set_ieee_aneg_advertisment(params,
8c99e7b0 3594 vars->ieee_fc);
57963ed9
YR		 3595
3596 /* enable autoneg */
239d686d 3597 bnx2x_set_autoneg(params, vars, enable_cl73);
57963ed9
YR		 3598
3599 /* enable and restart AN */
239d686d 3600 bnx2x_restart_autoneg(params, enable_cl73);
57963ed9
YR		 3601 }
3602
3603 } else { /* SGMII mode */
3604 DP(NETIF_MSG_LINK, "SGMII\n");
3605
8c99e7b0 3606 bnx2x_initialize_sgmii_process(params, vars);
57963ed9
YR		 3607 }
3608}
3609
ea4e040a
YR		 3610static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars)
3611{
3612 struct bnx2x *bp = params->bp;
3613 u32 ext_phy_type;
3614 u8 ext_phy_addr;
3615 u16 cnt;
3616 u16 ctrl = 0;
3617 u16 val = 0;
3618 u8 rc = 0;
3619 if (vars->phy_flags & PHY_XGXS_FLAG) {
3620 ext_phy_addr = ((params->ext_phy_config &
3621 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
3622 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
3623
3624 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
3625 /* Make sure that the soft reset is off (expect for the 8072:
3626 * due to the lock, it will be done inside the specific
3627 * handling)
3628 */
3629 if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
3630 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
3631 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN) &&
3632 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072) &&
3633 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073)) {
3634 /* Wait for soft reset to get cleared upto 1 sec */
3635 for (cnt = 0; cnt < 1000; cnt++) {
3636 bnx2x_cl45_read(bp, params->port,
3637 ext_phy_type,
3638 ext_phy_addr,
3639 MDIO_PMA_DEVAD,
3640 MDIO_PMA_REG_CTRL, &ctrl);
3641 if (!(ctrl & (1<<15)))
3642 break;
3643 msleep(1);
3644 }
3645 DP(NETIF_MSG_LINK, "control reg 0x%x (after %d ms)\n",
3646 ctrl, cnt);
3647 }
3648
3649 switch (ext_phy_type) {
3650 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
ea4e040a
YR		 3651 break;
3652
3653 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
3654 DP(NETIF_MSG_LINK, "XGXS 8705\n");
3655
3656 bnx2x_cl45_write(bp, params->port,
3657 ext_phy_type,
3658 ext_phy_addr,
3659 MDIO_PMA_DEVAD,
3660 MDIO_PMA_REG_MISC_CTRL,
3661 0x8288);
3662 bnx2x_cl45_write(bp, params->port,
3663 ext_phy_type,
3664 ext_phy_addr,
3665 MDIO_PMA_DEVAD,
3666 MDIO_PMA_REG_PHY_IDENTIFIER,
3667 0x7fbf);
3668 bnx2x_cl45_write(bp, params->port,
3669 ext_phy_type,
3670 ext_phy_addr,
3671 MDIO_PMA_DEVAD,
3672 MDIO_PMA_REG_CMU_PLL_BYPASS,
3673 0x0100);
3674 bnx2x_cl45_write(bp, params->port,
3675 ext_phy_type,
3676 ext_phy_addr,
3677 MDIO_WIS_DEVAD,
3678 MDIO_WIS_REG_LASI_CNTL, 0x1);
a35da8db 3679
3b313b61
EG		 3680 /* BCM8705 doesn't have microcode, hence the 0 */
3681 bnx2x_save_spirom_version(bp, params->port,
3682 params->shmem_base, 0);
ea4e040a
YR		 3683 break;
3684
3685 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
a35da8db
EG		 3686 /* Wait until fw is loaded */
3687 for (cnt = 0; cnt < 100; cnt++) {
3688 bnx2x_cl45_read(bp, params->port, ext_phy_type,
3689 ext_phy_addr, MDIO_PMA_DEVAD,
3690 MDIO_PMA_REG_ROM_VER1, &val);
3691 if (val)
3692 break;
3693 msleep(10);
3694 }
3695 DP(NETIF_MSG_LINK, "XGXS 8706 is initialized "
3696 "after %d ms\n", cnt);
c2c8b03e
EG		 3697 if ((params->feature_config_flags &
3698 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
3699 u8 i;
3700 u16 reg;
3701 for (i = 0; i < 4; i++) {
3702 reg = MDIO_XS_8706_REG_BANK_RX0 +
3703 i*(MDIO_XS_8706_REG_BANK_RX1 -
3704 MDIO_XS_8706_REG_BANK_RX0);
3705 bnx2x_cl45_read(bp, params->port,
3706 ext_phy_type,
3707 ext_phy_addr,
3708 MDIO_XS_DEVAD,
3709 reg, &val);
3710 /* Clear first 3 bits of the control */
3711 val &= ~0x7;
3712 /* Set control bits according to
3713 configuation */
3714 val |= (params->xgxs_config_rx[i] &
3715 0x7);
3716 DP(NETIF_MSG_LINK, "Setting RX"
3717 "Equalizer to BCM8706 reg 0x%x"
3718 " <-- val 0x%x\n", reg, val);
3719 bnx2x_cl45_write(bp, params->port,
3720 ext_phy_type,
3721 ext_phy_addr,
3722 MDIO_XS_DEVAD,
3723 reg, val);
3724 }
3725 }
ea4e040a
YR		 3726 /* Force speed */
3727 /* First enable LASI */
3728 bnx2x_cl45_write(bp, params->port,
3729 ext_phy_type,
3730 ext_phy_addr,
3731 MDIO_PMA_DEVAD,
3732 MDIO_PMA_REG_RX_ALARM_CTRL,
3733 0x0400);
3734 bnx2x_cl45_write(bp, params->port,
3735 ext_phy_type,
3736 ext_phy_addr,
3737 MDIO_PMA_DEVAD,
3738 MDIO_PMA_REG_LASI_CTRL, 0x0004);
3739
3740 if (params->req_line_speed == SPEED_10000) {
3741 DP(NETIF_MSG_LINK, "XGXS 8706 force 10Gbps\n");
3742
3743 bnx2x_cl45_write(bp, params->port,
3744 ext_phy_type,
3745 ext_phy_addr,
3746 MDIO_PMA_DEVAD,
3747 MDIO_PMA_REG_DIGITAL_CTRL,
3748 0x400);
3749 } else {
3750 /* Force 1Gbps using autoneg with 1G
3751 advertisment */
3752
3753 /* Allow CL37 through CL73 */
3754 DP(NETIF_MSG_LINK, "XGXS 8706 AutoNeg\n");
3755 bnx2x_cl45_write(bp, params->port,
3756 ext_phy_type,
3757 ext_phy_addr,
3758 MDIO_AN_DEVAD,
3759 MDIO_AN_REG_CL37_CL73,
3760 0x040c);
3761
3762 /* Enable Full-Duplex advertisment on CL37 */
3763 bnx2x_cl45_write(bp, params->port,
3764 ext_phy_type,
3765 ext_phy_addr,
3766 MDIO_AN_DEVAD,
8c99e7b0 3767 MDIO_AN_REG_CL37_FC_LP,
ea4e040a
YR		 3768 0x0020);
3769 /* Enable CL37 AN */
3770 bnx2x_cl45_write(bp, params->port,
3771 ext_phy_type,
3772 ext_phy_addr,
3773 MDIO_AN_DEVAD,
3774 MDIO_AN_REG_CL37_AN,
3775 0x1000);
3776 /* 1G support */
3777 bnx2x_cl45_write(bp, params->port,
3778 ext_phy_type,
3779 ext_phy_addr,
3780 MDIO_AN_DEVAD,
3781 MDIO_AN_REG_ADV, (1<<5));
3782
3783 /* Enable clause 73 AN */
3784 bnx2x_cl45_write(bp, params->port,
3785 ext_phy_type,
3786 ext_phy_addr,
3787 MDIO_AN_DEVAD,
3788 MDIO_AN_REG_CTRL,
3789 0x1200);
3790
3791 }
a35da8db
EG		 3792 bnx2x_save_bcm_spirom_ver(bp, params->port,
3793 ext_phy_type,
3794 ext_phy_addr,
3795 params->shmem_base);
ea4e040a 3796 break;
589abe3a
EG		 3797 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
3798 DP(NETIF_MSG_LINK, "Initializing BCM8726\n");
3799 bnx2x_bcm8726_external_rom_boot(params);
3800
3801 /* Need to call module detected on initialization since
3802 the module detection triggered by actual module
3803 insertion might occur before driver is loaded, and when
3804 driver is loaded, it reset all registers, including the
3805 transmitter */
3806 bnx2x_sfp_module_detection(params);
4d295db0
EG		 3807
3808 /* Set Flow control */
3809 bnx2x_ext_phy_set_pause(params, vars);
589abe3a
EG		 3810 if (params->req_line_speed == SPEED_1000) {
3811 DP(NETIF_MSG_LINK, "Setting 1G force\n");
3812 bnx2x_cl45_write(bp, params->port, ext_phy_type,
3813 ext_phy_addr, MDIO_PMA_DEVAD,
3814 MDIO_PMA_REG_CTRL, 0x40);
3815 bnx2x_cl45_write(bp, params->port, ext_phy_type,
3816 ext_phy_addr, MDIO_PMA_DEVAD,
3817 MDIO_PMA_REG_10G_CTRL2, 0xD);
3818 bnx2x_cl45_write(bp, params->port, ext_phy_type,
3819 ext_phy_addr, MDIO_PMA_DEVAD,
3820 MDIO_PMA_REG_LASI_CTRL, 0x5);
3821 bnx2x_cl45_write(bp, params->port, ext_phy_type,
3822 ext_phy_addr, MDIO_PMA_DEVAD,
3823 MDIO_PMA_REG_RX_ALARM_CTRL,
3824 0x400);
3825 } else if ((params->req_line_speed ==
3826 SPEED_AUTO_NEG) &&
3827 ((params->speed_cap_mask &
3828 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))) {
3829 DP(NETIF_MSG_LINK, "Setting 1G clause37 \n");
3830 bnx2x_cl45_write(bp, params->port, ext_phy_type,
3831 ext_phy_addr, MDIO_AN_DEVAD,
3832 MDIO_AN_REG_ADV, 0x20);
3833 bnx2x_cl45_write(bp, params->port, ext_phy_type,
3834 ext_phy_addr, MDIO_AN_DEVAD,
3835 MDIO_AN_REG_CL37_CL73, 0x040c);
3836 bnx2x_cl45_write(bp, params->port, ext_phy_type,
3837 ext_phy_addr, MDIO_AN_DEVAD,
3838 MDIO_AN_REG_CL37_FC_LD, 0x0020);
3839 bnx2x_cl45_write(bp, params->port, ext_phy_type,
3840 ext_phy_addr, MDIO_AN_DEVAD,
3841 MDIO_AN_REG_CL37_AN, 0x1000);
3842 bnx2x_cl45_write(bp, params->port, ext_phy_type,
3843 ext_phy_addr, MDIO_AN_DEVAD,
3844 MDIO_AN_REG_CTRL, 0x1200);
3845
3846 /* Enable RX-ALARM control to receive
3847 interrupt for 1G speed change */
3848 bnx2x_cl45_write(bp, params->port, ext_phy_type,
3849 ext_phy_addr, MDIO_PMA_DEVAD,
3850 MDIO_PMA_REG_LASI_CTRL, 0x4);
3851 bnx2x_cl45_write(bp, params->port, ext_phy_type,
3852 ext_phy_addr, MDIO_PMA_DEVAD,
3853 MDIO_PMA_REG_RX_ALARM_CTRL,
3854 0x400);
ea4e040a 3855
589abe3a
EG		 3856 } else { /* Default 10G. Set only LASI control */
3857 bnx2x_cl45_write(bp, params->port, ext_phy_type,
3858 ext_phy_addr, MDIO_PMA_DEVAD,
3859 MDIO_PMA_REG_LASI_CTRL, 1);
3860 }
c2c8b03e
EG		 3861
3862 /* Set TX PreEmphasis if needed */
3863 if ((params->feature_config_flags &
3864 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
3865 DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x,"
3866 "TX_CTRL2 0x%x\n",
3867 params->xgxs_config_tx[0],
3868 params->xgxs_config_tx[1]);
3869 bnx2x_cl45_write(bp, params->port,
3870 ext_phy_type,
3871 ext_phy_addr,
3872 MDIO_PMA_DEVAD,
3873 MDIO_PMA_REG_8726_TX_CTRL1,
3874 params->xgxs_config_tx[0]);
3875
3876 bnx2x_cl45_write(bp, params->port,
3877 ext_phy_type,
3878 ext_phy_addr,
3879 MDIO_PMA_DEVAD,
3880 MDIO_PMA_REG_8726_TX_CTRL2,
3881 params->xgxs_config_tx[1]);
3882 }
589abe3a 3883 break;
ea4e040a
YR		 3884 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
3885 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
3886 {
3887 u16 tmp1;
3888 u16 rx_alarm_ctrl_val;
3889 u16 lasi_ctrl_val;
3890 if (ext_phy_type ==
3891 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072) {
3892 rx_alarm_ctrl_val = 0x400;
3893 lasi_ctrl_val = 0x0004;
3894 } else {
ea4e040a 3895 rx_alarm_ctrl_val = (1<<2);
ea4e040a
YR		 3896 lasi_ctrl_val = 0x0004;
3897 }
3898
6bbca910
YR		 3899 /* enable LASI */
3900 bnx2x_cl45_write(bp, params->port,
3901 ext_phy_type,
3902 ext_phy_addr,
3903 MDIO_PMA_DEVAD,
3904 MDIO_PMA_REG_RX_ALARM_CTRL,
3905 rx_alarm_ctrl_val);
3906
3907 bnx2x_cl45_write(bp, params->port,
3908 ext_phy_type,
3909 ext_phy_addr,
3910 MDIO_PMA_DEVAD,
3911 MDIO_PMA_REG_LASI_CTRL,
3912 lasi_ctrl_val);
3913
3914 bnx2x_8073_set_pause_cl37(params, vars);
ea4e040a
YR		 3915
3916 if (ext_phy_type ==
3917 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072){
3918 bnx2x_bcm8072_external_rom_boot(params);
3919 } else {
6bbca910 3920
ea4e040a
YR		 3921 /* In case of 8073 with long xaui lines,
3922 don't set the 8073 xaui low power*/
3923 bnx2x_bcm8073_set_xaui_low_power_mode(params);
3924 }
3925
6bbca910
YR		 3926 bnx2x_cl45_read(bp, params->port,
3927 ext_phy_type,
3928 ext_phy_addr,
3929 MDIO_PMA_DEVAD,
052a38e0 3930 MDIO_PMA_REG_M8051_MSGOUT_REG,
6bbca910 3931 &tmp1);
ea4e040a
YR		 3932
3933 bnx2x_cl45_read(bp, params->port,
3934 ext_phy_type,
3935 ext_phy_addr,
3936 MDIO_PMA_DEVAD,
3937 MDIO_PMA_REG_RX_ALARM, &tmp1);
3938
3939 DP(NETIF_MSG_LINK, "Before rom RX_ALARM(port1):"
3940 "0x%x\n", tmp1);
3941
3942 /* If this is forced speed, set to KR or KX
3943 * (all other are not supported)
3944 */
6bbca910
YR		 3945 if (params->loopback_mode == LOOPBACK_EXT) {
3946 bnx2x_bcm807x_force_10G(params);
3947 DP(NETIF_MSG_LINK,
3948 "Forced speed 10G on 807X\n");
3949 break;
3950 } else {
3951 bnx2x_cl45_write(bp, params->port,
3952 ext_phy_type, ext_phy_addr,
3953 MDIO_PMA_DEVAD,
3954 MDIO_PMA_REG_BCM_CTRL,
3955 0x0002);
3956 }
3957 if (params->req_line_speed != SPEED_AUTO_NEG) {
3958 if (params->req_line_speed == SPEED_10000) {
3959 val = (1<<7);
ea4e040a
YR		 3960 } else if (params->req_line_speed ==
3961 SPEED_2500) {
3962 val = (1<<5);
3963 /* Note that 2.5G works only
3964 when used with 1G advertisment */
3965 } else
3966 val = (1<<5);
3967 } else {
3968
3969 val = 0;
3970 if (params->speed_cap_mask &
3971 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
3972 val |= (1<<7);
3973
6bbca910
YR		 3974 /* Note that 2.5G works only when
3975 used with 1G advertisment */
ea4e040a 3976 if (params->speed_cap_mask &
6bbca910
YR		 3977 (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G |
3978 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
ea4e040a 3979 val |= (1<<5);
6bbca910
YR		 3980 DP(NETIF_MSG_LINK,
3981 "807x autoneg val = 0x%x\n", val);
ea4e040a
YR		 3982 }
3983
3984 bnx2x_cl45_write(bp, params->port,
3985 ext_phy_type,
3986 ext_phy_addr,
3987 MDIO_AN_DEVAD,
3988 MDIO_AN_REG_ADV, val);
3989
3990 if (ext_phy_type ==
3991 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073) {
6bbca910 3992
ea4e040a
YR		 3993 bnx2x_cl45_read(bp, params->port,
3994 ext_phy_type,
3995 ext_phy_addr,
3996 MDIO_AN_DEVAD,
052a38e0 3997 MDIO_AN_REG_8073_2_5G, &tmp1);
6bbca910
YR		 3998
3999 if (((params->speed_cap_mask &
4000 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) &&
4001 (params->req_line_speed ==
4002 SPEED_AUTO_NEG)) ||
4003 (params->req_line_speed ==
4004 SPEED_2500)) {
ea4e040a
YR		 4005 u16 phy_ver;
4006 /* Allow 2.5G for A1 and above */
4007 bnx2x_cl45_read(bp, params->port,
4008 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
4009 ext_phy_addr,
4010 MDIO_PMA_DEVAD,
052a38e0 4011 MDIO_PMA_REG_8073_CHIP_REV, &phy_ver);
6bbca910 4012 DP(NETIF_MSG_LINK, "Add 2.5G\n");
ea4e040a
YR		 4013 if (phy_ver > 0)
4014 tmp1 |= 1;
4015 else
4016 tmp1 &= 0xfffe;
6bbca910
YR		 4017 } else {
4018 DP(NETIF_MSG_LINK, "Disable 2.5G\n");
ea4e040a 4019 tmp1 &= 0xfffe;
6bbca910 4020 }
ea4e040a 4021
6bbca910
YR		 4022 bnx2x_cl45_write(bp, params->port,
4023 ext_phy_type,
4024 ext_phy_addr,
4025 MDIO_AN_DEVAD,
052a38e0 4026 MDIO_AN_REG_8073_2_5G, tmp1);
ea4e040a 4027 }
6bbca910
YR		 4028
4029 /* Add support for CL37 (passive mode) II */
4030
4031 bnx2x_cl45_read(bp, params->port,
ea4e040a
YR		 4032 ext_phy_type,
4033 ext_phy_addr,
4034 MDIO_AN_DEVAD,
6bbca910
YR		 4035 MDIO_AN_REG_CL37_FC_LD,
4036 &tmp1);
4037
ea4e040a
YR		 4038 bnx2x_cl45_write(bp, params->port,
4039 ext_phy_type,
4040 ext_phy_addr,
4041 MDIO_AN_DEVAD,
6bbca910
YR		 4042 MDIO_AN_REG_CL37_FC_LD, (tmp1 |
4043 ((params->req_duplex == DUPLEX_FULL) ?
4044 0x20 : 0x40)));
4045
ea4e040a
YR		 4046 /* Add support for CL37 (passive mode) III */
4047 bnx2x_cl45_write(bp, params->port,
4048 ext_phy_type,
4049 ext_phy_addr,
4050 MDIO_AN_DEVAD,
4051 MDIO_AN_REG_CL37_AN, 0x1000);
ea4e040a
YR		 4052
4053 if (ext_phy_type ==
4054 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073) {
6bbca910 4055 /* The SNR will improve about 2db by changing
ea4e040a
YR		 4056 BW and FEE main tap. Rest commands are executed
4057 after link is up*/
6bbca910 4058 /*Change FFE main cursor to 5 in EDC register*/
ea4e040a
YR		 4059 if (bnx2x_8073_is_snr_needed(params))
4060 bnx2x_cl45_write(bp, params->port,
4061 ext_phy_type,
4062 ext_phy_addr,
4063 MDIO_PMA_DEVAD,
4064 MDIO_PMA_REG_EDC_FFE_MAIN,
4065 0xFB0C);
4066
6bbca910
YR		 4067 /* Enable FEC (Forware Error Correction)
4068 Request in the AN */
4069 bnx2x_cl45_read(bp, params->port,
4070 ext_phy_type,
4071 ext_phy_addr,
4072 MDIO_AN_DEVAD,
4073 MDIO_AN_REG_ADV2, &tmp1);
ea4e040a 4074
6bbca910
YR		 4075 tmp1 |= (1<<15);
4076
4077 bnx2x_cl45_write(bp, params->port,
4078 ext_phy_type,
4079 ext_phy_addr,
4080 MDIO_AN_DEVAD,
4081 MDIO_AN_REG_ADV2, tmp1);
ea4e040a 4082
ea4e040a
YR		 4083 }
4084
4085 bnx2x_ext_phy_set_pause(params, vars);
4086
6bbca910
YR		 4087 /* Restart autoneg */
4088 msleep(500);
ea4e040a
YR		 4089 bnx2x_cl45_write(bp, params->port,
4090 ext_phy_type,
4091 ext_phy_addr,
4092 MDIO_AN_DEVAD,
4093 MDIO_AN_REG_CTRL, 0x1200);
4094 DP(NETIF_MSG_LINK, "807x Autoneg Restart: "
4095 "Advertise 1G=%x, 10G=%x\n",
4096 ((val & (1<<5)) > 0),
4097 ((val & (1<<7)) > 0));
4098 break;
4099 }
4d295db0
EG		 4100
4101 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
a35da8db 4102 {
4d295db0
EG		 4103 u16 tmp1;
4104 u16 rx_alarm_ctrl_val;
4105 u16 lasi_ctrl_val;
ea4e040a 4106
4d295db0
EG		 4107 /* Enable PMD link, MOD_ABS_FLT, and 1G link alarm */
4108
4109 u16 mod_abs;
4110 rx_alarm_ctrl_val = (1<<2) | (1<<5) ;
4111 lasi_ctrl_val = 0x0004;
4112
4113 DP(NETIF_MSG_LINK, "Initializing BCM8727\n");
4114 /* enable LASI */
ea4e040a
YR		 4115 bnx2x_cl45_write(bp, params->port,
4116 ext_phy_type,
4117 ext_phy_addr,
4118 MDIO_PMA_DEVAD,
4d295db0
EG		 4119 MDIO_PMA_REG_RX_ALARM_CTRL,
4120 rx_alarm_ctrl_val);
4121
ea4e040a
YR		 4122 bnx2x_cl45_write(bp, params->port,
4123 ext_phy_type,
4124 ext_phy_addr,
4125 MDIO_PMA_DEVAD,
4d295db0
EG		 4126 MDIO_PMA_REG_LASI_CTRL,
4127 lasi_ctrl_val);
ea4e040a 4128
4d295db0
EG		 4129 /* Initially configure MOD_ABS to interrupt when
4130 module is presence( bit 8) */
ea4e040a
YR		 4131 bnx2x_cl45_read(bp, params->port,
4132 ext_phy_type,
4133 ext_phy_addr,
4d295db0
EG		 4134 MDIO_PMA_DEVAD,
4135 MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
4136 /* Set EDC off by setting OPTXLOS signal input to low
4137 (bit 9).
4138 When the EDC is off it locks onto a reference clock and
4139 avoids becoming 'lost'.*/
4140 mod_abs &= ~((1<<8) | (1<<9));
ea4e040a
YR		 4141 bnx2x_cl45_write(bp, params->port,
4142 ext_phy_type,
4143 ext_phy_addr,
4d295db0
EG		 4144 MDIO_PMA_DEVAD,
4145 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
28577185 4146
4d295db0
EG		 4147 /* Make MOD_ABS give interrupt on change */
4148 bnx2x_cl45_read(bp, params->port,
4149 ext_phy_type,
4150 ext_phy_addr,
4151 MDIO_PMA_DEVAD,
4152 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
4153 &val);
4154 val |= (1<<12);
4155 bnx2x_cl45_write(bp, params->port,
4156 ext_phy_type,
4157 ext_phy_addr,
4158 MDIO_PMA_DEVAD,
4159 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
4160 val);
4161
4162 /* Set 8727 GPIOs to input to allow reading from the
4163 8727 GPIO0 status which reflect SFP+ module
4164 over-current */
4165
4166 bnx2x_cl45_read(bp, params->port,
4167 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
4168 ext_phy_addr,
4169 MDIO_PMA_DEVAD,
4170 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
4171 &val);
4172 val &= 0xff8f; /* Reset bits 4-6 */
4173 bnx2x_cl45_write(bp, params->port,
4174 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
4175 ext_phy_addr,
4176 MDIO_PMA_DEVAD,
4177 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
4178 val);
4179
4180 bnx2x_8727_power_module(bp, params, ext_phy_addr, 1);
4181 bnx2x_bcm8073_set_xaui_low_power_mode(params);
4182
4183 bnx2x_cl45_read(bp, params->port,
4184 ext_phy_type,
4185 ext_phy_addr,
4186 MDIO_PMA_DEVAD,
4187 MDIO_PMA_REG_M8051_MSGOUT_REG,
4188 &tmp1);
4189
4190 bnx2x_cl45_read(bp, params->port,
4191 ext_phy_type,
4192 ext_phy_addr,
4193 MDIO_PMA_DEVAD,
4194 MDIO_PMA_REG_RX_ALARM, &tmp1);
4195
4196 /* Set option 1G speed */
4197 if (params->req_line_speed == SPEED_1000) {
4198
4199 DP(NETIF_MSG_LINK, "Setting 1G force\n");
4200 bnx2x_cl45_write(bp, params->port,
4201 ext_phy_type,
4202 ext_phy_addr,
4203 MDIO_PMA_DEVAD,
4204 MDIO_PMA_REG_CTRL, 0x40);
4205 bnx2x_cl45_write(bp, params->port,
4206 ext_phy_type,
4207 ext_phy_addr,
4208 MDIO_PMA_DEVAD,
4209 MDIO_PMA_REG_10G_CTRL2, 0xD);
4210 bnx2x_cl45_read(bp, params->port,
4211 ext_phy_type,
4212 ext_phy_addr,
4213 MDIO_PMA_DEVAD,
4214 MDIO_PMA_REG_10G_CTRL2, &tmp1);
4215 DP(NETIF_MSG_LINK, "1.7 = 0x%x \n", tmp1);
4216
4217 } else if ((params->req_line_speed ==
4218 SPEED_AUTO_NEG) &&
4219 ((params->speed_cap_mask &
4220 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))) {
4221
4222 DP(NETIF_MSG_LINK, "Setting 1G clause37 \n");
4223 bnx2x_cl45_write(bp, params->port, ext_phy_type,
4224 ext_phy_addr, MDIO_AN_DEVAD,
4225 MDIO_PMA_REG_8727_MISC_CTRL, 0);
4226 bnx2x_cl45_write(bp, params->port, ext_phy_type,
4227 ext_phy_addr, MDIO_AN_DEVAD,
4228 MDIO_AN_REG_CL37_AN, 0x1300);
4229 } else {
4230 /* Since the 8727 has only single reset pin,
4231 need to set the 10G registers although it is
4232 default */
4233 bnx2x_cl45_write(bp, params->port, ext_phy_type,
4234 ext_phy_addr, MDIO_AN_DEVAD,
4235 MDIO_AN_REG_CTRL, 0x0020);
4236 bnx2x_cl45_write(bp, params->port, ext_phy_type,
4237 ext_phy_addr, MDIO_AN_DEVAD,
4238 0x7, 0x0100);
4239 bnx2x_cl45_write(bp, params->port, ext_phy_type,
4240 ext_phy_addr, MDIO_PMA_DEVAD,
4241 MDIO_PMA_REG_CTRL, 0x2040);
4242 bnx2x_cl45_write(bp, params->port, ext_phy_type,
4243 ext_phy_addr, MDIO_PMA_DEVAD,
4244 MDIO_PMA_REG_10G_CTRL2, 0x0008);
4245 }
4246
4247 /* Set 2-wire transfer rate to 400Khz since 100Khz
4248 is not operational */
4249 bnx2x_cl45_write(bp, params->port,
4250 ext_phy_type,
4251 ext_phy_addr,
4252 MDIO_PMA_DEVAD,
4253 MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR,
4254 0xa101);
4255
4256 /* Set TX PreEmphasis if needed */
4257 if ((params->feature_config_flags &
4258 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
4259 DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x,"
4260 "TX_CTRL2 0x%x\n",
4261 params->xgxs_config_tx[0],
4262 params->xgxs_config_tx[1]);
4263 bnx2x_cl45_write(bp, params->port,
4264 ext_phy_type,
4265 ext_phy_addr,
4266 MDIO_PMA_DEVAD,
4267 MDIO_PMA_REG_8727_TX_CTRL1,
4268 params->xgxs_config_tx[0]);
4269
4270 bnx2x_cl45_write(bp, params->port,
4271 ext_phy_type,
4272 ext_phy_addr,
4273 MDIO_PMA_DEVAD,
4274 MDIO_PMA_REG_8727_TX_CTRL2,
4275 params->xgxs_config_tx[1]);
4276 }
4277
4278 break;
4279 }
4280
4281 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
4282 {
4283 u16 fw_ver1, fw_ver2;
4284 DP(NETIF_MSG_LINK,
4285 "Setting the SFX7101 LASI indication\n");
4286
4287 bnx2x_cl45_write(bp, params->port,
4288 ext_phy_type,
4289 ext_phy_addr,
4290 MDIO_PMA_DEVAD,
4291 MDIO_PMA_REG_LASI_CTRL, 0x1);
4292 DP(NETIF_MSG_LINK,
4293 "Setting the SFX7101 LED to blink on traffic\n");
4294 bnx2x_cl45_write(bp, params->port,
4295 ext_phy_type,
4296 ext_phy_addr,
4297 MDIO_PMA_DEVAD,
4298 MDIO_PMA_REG_7107_LED_CNTL, (1<<3));
4299
4300 bnx2x_ext_phy_set_pause(params, vars);
4301 /* Restart autoneg */
4302 bnx2x_cl45_read(bp, params->port,
4303 ext_phy_type,
4304 ext_phy_addr,
4305 MDIO_AN_DEVAD,
4306 MDIO_AN_REG_CTRL, &val);
4307 val |= 0x200;
4308 bnx2x_cl45_write(bp, params->port,
4309 ext_phy_type,
4310 ext_phy_addr,
4311 MDIO_AN_DEVAD,
4312 MDIO_AN_REG_CTRL, val);
4313
4314 /* Save spirom version */
4315 bnx2x_cl45_read(bp, params->port, ext_phy_type,
4316 ext_phy_addr, MDIO_PMA_DEVAD,
4317 MDIO_PMA_REG_7101_VER1, &fw_ver1);
a35da8db
EG		 4318
4319 bnx2x_cl45_read(bp, params->port, ext_phy_type,
4320 ext_phy_addr, MDIO_PMA_DEVAD,
4321 MDIO_PMA_REG_7101_VER2, &fw_ver2);
4322
4323 bnx2x_save_spirom_version(params->bp, params->port,
4324 params->shmem_base,
4325 (u32)(fw_ver1<<16 | fw_ver2));
4326
28577185 4327 break;
a35da8db 4328 }
28577185 4329 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
2f904460
EG		 4330 /* This phy uses the NIG latch mechanism since link
4331 indication arrives through its LED4 and not via
4332 its LASI signal, so we get steady signal
4333 instead of clear on read */
4334 bnx2x_bits_en(bp, NIG_REG_LATCH_BC_0 + params->port*4,
4335 1 << NIG_LATCH_BC_ENABLE_MI_INT);
4336
4337 bnx2x_8481_set_led4(params, ext_phy_type, ext_phy_addr);
4338 if (params->req_line_speed == SPEED_AUTO_NEG) {
4339
4340 u16 autoneg_val, an_1000_val, an_10_100_val;
4341 /* set 1000 speed advertisement */
4342 bnx2x_cl45_read(bp, params->port,
4343 ext_phy_type,
4344 ext_phy_addr,
4345 MDIO_AN_DEVAD,
4346 MDIO_AN_REG_8481_1000T_CTRL,
4347 &an_1000_val);
28577185 4348
2f904460
EG		 4349 if (params->speed_cap_mask &
4350 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) {
4351 an_1000_val |= (1<<8);
4352 if (params->req_duplex == DUPLEX_FULL)
4353 an_1000_val |= (1<<9);
4354 DP(NETIF_MSG_LINK, "Advertising 1G\n");
4355 } else
4356 an_1000_val &= ~((1<<8) | (1<<9));
28577185 4357
2f904460
EG		 4358 bnx2x_cl45_write(bp, params->port,
4359 ext_phy_type,
4360 ext_phy_addr,
4361 MDIO_AN_DEVAD,
4362 MDIO_AN_REG_8481_1000T_CTRL,
4363 an_1000_val);
4364
4365 /* set 100 speed advertisement */
4366 bnx2x_cl45_read(bp, params->port,
4367 ext_phy_type,
4368 ext_phy_addr,
4369 MDIO_AN_DEVAD,
4370 MDIO_AN_REG_8481_LEGACY_AN_ADV,
4371 &an_10_100_val);
4372
4373 if (params->speed_cap_mask &
4374 (PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL |
4375 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)) {
4376 an_10_100_val |= (1<<7);
4377 if (params->req_duplex == DUPLEX_FULL)
4378 an_10_100_val |= (1<<8);
4379 DP(NETIF_MSG_LINK,
4380 "Advertising 100M\n");
4381 } else
4382 an_10_100_val &= ~((1<<7) | (1<<8));
4383
4384 /* set 10 speed advertisement */
4385 if (params->speed_cap_mask &
4386 (PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL |
4387 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) {
4388 an_10_100_val |= (1<<5);
4389 if (params->req_duplex == DUPLEX_FULL)
4390 an_10_100_val |= (1<<6);
4391 DP(NETIF_MSG_LINK, "Advertising 10M\n");
4392 }
4393 else
4394 an_10_100_val &= ~((1<<5) | (1<<6));
4395
4396 bnx2x_cl45_write(bp, params->port,
4397 ext_phy_type,
4398 ext_phy_addr,
4399 MDIO_AN_DEVAD,
4400 MDIO_AN_REG_8481_LEGACY_AN_ADV,
4401 an_10_100_val);
4402
4403 bnx2x_cl45_read(bp, params->port,
4404 ext_phy_type,
4405 ext_phy_addr,
4406 MDIO_AN_DEVAD,
4407 MDIO_AN_REG_8481_LEGACY_MII_CTRL,
4408 &autoneg_val);
4409
4410 /* Disable forced speed */
4411 autoneg_val &= ~(1<<6|1<<13);
4412
4413 /* Enable autoneg and restart autoneg
4414 for legacy speeds */
4415 autoneg_val |= (1<<9|1<<12);
4416
4417 if (params->req_duplex == DUPLEX_FULL)
4418 autoneg_val |= (1<<8);
4419 else
4420 autoneg_val &= ~(1<<8);
4421
4422 bnx2x_cl45_write(bp, params->port,
4423 ext_phy_type,
4424 ext_phy_addr,
4425 MDIO_AN_DEVAD,
4426 MDIO_AN_REG_8481_LEGACY_MII_CTRL,
4427 autoneg_val);
4428
4429 if (params->speed_cap_mask &
4430 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) {
4431 DP(NETIF_MSG_LINK, "Advertising 10G\n");
4432 /* Restart autoneg for 10G*/
28577185
EG		 4433 bnx2x_cl45_read(bp, params->port,
4434 ext_phy_type,
4435 ext_phy_addr,
4436 MDIO_AN_DEVAD,
4437 MDIO_AN_REG_CTRL, &val);
4438 val |= 0x200;
4439 bnx2x_cl45_write(bp, params->port,
4440 ext_phy_type,
4441 ext_phy_addr,
4442 MDIO_AN_DEVAD,
4443 MDIO_AN_REG_CTRL, val);
2f904460
EG		 4444 }
4445 } else {
4446 /* Force speed */
4447 u16 autoneg_ctrl, pma_ctrl;
4448 bnx2x_cl45_read(bp, params->port,
4449 ext_phy_type,
4450 ext_phy_addr,
4451 MDIO_AN_DEVAD,
4452 MDIO_AN_REG_8481_LEGACY_MII_CTRL,
4453 &autoneg_ctrl);
4454
4455 /* Disable autoneg */
4456 autoneg_ctrl &= ~(1<<12);
4457
4458 /* Set 1000 force */
4459 switch (params->req_line_speed) {
4460 case SPEED_10000:
4461 DP(NETIF_MSG_LINK,
4462 "Unable to set 10G force !\n");
4463 break;
4464 case SPEED_1000:
4465 bnx2x_cl45_read(bp, params->port,
4466 ext_phy_type,
4467 ext_phy_addr,
4468 MDIO_PMA_DEVAD,
4469 MDIO_PMA_REG_CTRL,
4470 &pma_ctrl);
4471 autoneg_ctrl &= ~(1<<13);
4472 autoneg_ctrl |= (1<<6);
4473 pma_ctrl &= ~(1<<13);
4474 pma_ctrl |= (1<<6);
4475 DP(NETIF_MSG_LINK,
4476 "Setting 1000M force\n");
4477 bnx2x_cl45_write(bp, params->port,
4478 ext_phy_type,
4479 ext_phy_addr,
4480 MDIO_PMA_DEVAD,
4481 MDIO_PMA_REG_CTRL,
4482 pma_ctrl);
4483 break;
4484 case SPEED_100:
4485 autoneg_ctrl |= (1<<13);
4486 autoneg_ctrl &= ~(1<<6);
4487 DP(NETIF_MSG_LINK,
4488 "Setting 100M force\n");
4489 break;
4490 case SPEED_10:
4491 autoneg_ctrl &= ~(1<<13);
4492 autoneg_ctrl &= ~(1<<6);
4493 DP(NETIF_MSG_LINK,
4494 "Setting 10M force\n");
4495 break;
4496 }
4497
4498 /* Duplex mode */
4499 if (params->req_duplex == DUPLEX_FULL) {
4500 autoneg_ctrl |= (1<<8);
4501 DP(NETIF_MSG_LINK,
4502 "Setting full duplex\n");
4503 } else
4504 autoneg_ctrl &= ~(1<<8);
4505
4506 /* Update autoneg ctrl and pma ctrl */
4507 bnx2x_cl45_write(bp, params->port,
4508 ext_phy_type,
4509 ext_phy_addr,
4510 MDIO_AN_DEVAD,
4511 MDIO_AN_REG_8481_LEGACY_MII_CTRL,
4512 autoneg_ctrl);
4513 }
28577185 4514
b1607af5
EG		 4515 /* Save spirom version */
4516 bnx2x_save_8481_spirom_version(bp, params->port,
4517 ext_phy_addr,
4518 params->shmem_base);
ea4e040a
YR		 4519 break;
4520 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
4521 DP(NETIF_MSG_LINK,
4522 "XGXS PHY Failure detected 0x%x\n",
4523 params->ext_phy_config);
4524 rc = -EINVAL;
4525 break;
4526 default:
4527 DP(NETIF_MSG_LINK, "BAD XGXS ext_phy_config 0x%x\n",
4528 params->ext_phy_config);
4529 rc = -EINVAL;
4530 break;
4531 }
4532
4533 } else { /* SerDes */
57963ed9 4534
ea4e040a
YR		 4535 ext_phy_type = SERDES_EXT_PHY_TYPE(params->ext_phy_config);
4536 switch (ext_phy_type) {
4537 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT:
4538 DP(NETIF_MSG_LINK, "SerDes Direct\n");
4539 break;
4540
4541 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482:
4542 DP(NETIF_MSG_LINK, "SerDes 5482\n");
4543 break;
4544
4545 default:
4546 DP(NETIF_MSG_LINK, "BAD SerDes ext_phy_config 0x%x\n",
4547 params->ext_phy_config);
4548 break;
4549 }
4550 }
4551 return rc;
4552}
4553
4d295db0
EG		 4554static void bnx2x_8727_handle_mod_abs(struct link_params *params)
4555{
4556 struct bnx2x *bp = params->bp;
4557 u16 mod_abs, rx_alarm_status;
4558 u8 ext_phy_addr = ((params->ext_phy_config &
4559 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
4560 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
4561 u32 val = REG_RD(bp, params->shmem_base +
4562 offsetof(struct shmem_region, dev_info.
4563 port_feature_config[params->port].
4564 config));
4565 bnx2x_cl45_read(bp, params->port,
4566 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
4567 ext_phy_addr,
4568 MDIO_PMA_DEVAD,
4569 MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
4570 if (mod_abs & (1<<8)) {
4571
4572 /* Module is absent */
4573 DP(NETIF_MSG_LINK, "MOD_ABS indication "
4574 "show module is absent\n");
4575
4576 /* 1. Set mod_abs to detect next module
4577 presence event
4578 2. Set EDC off by setting OPTXLOS signal input to low
4579 (bit 9).
4580 When the EDC is off it locks onto a reference clock and
4581 avoids becoming 'lost'.*/
4582 mod_abs &= ~((1<<8)|(1<<9));
4583 bnx2x_cl45_write(bp, params->port,
4584 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
4585 ext_phy_addr,
4586 MDIO_PMA_DEVAD,
4587 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
4588
4589 /* Clear RX alarm since it stays up as long as
4590 the mod_abs wasn't changed */
4591 bnx2x_cl45_read(bp, params->port,
4592 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
4593 ext_phy_addr,
4594 MDIO_PMA_DEVAD,
4595 MDIO_PMA_REG_RX_ALARM, &rx_alarm_status);
4596
4597 } else {
4598 /* Module is present */
4599 DP(NETIF_MSG_LINK, "MOD_ABS indication "
4600 "show module is present\n");
4601 /* First thing, disable transmitter,
4602 and if the module is ok, the
4603 module_detection will enable it*/
4604
4605 /* 1. Set mod_abs to detect next module
4606 absent event ( bit 8)
4607 2. Restore the default polarity of the OPRXLOS signal and
4608 this signal will then correctly indicate the presence or
4609 absence of the Rx signal. (bit 9) */
4610 mod_abs |= ((1<<8)|(1<<9));
4611 bnx2x_cl45_write(bp, params->port,
4612 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
4613 ext_phy_addr,
4614 MDIO_PMA_DEVAD,
4615 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
4616
4617 /* Clear RX alarm since it stays up as long as
4618 the mod_abs wasn't changed. This is need to be done
4619 before calling the module detection, otherwise it will clear
4620 the link update alarm */
4621 bnx2x_cl45_read(bp, params->port,
4622 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
4623 ext_phy_addr,
4624 MDIO_PMA_DEVAD,
4625 MDIO_PMA_REG_RX_ALARM, &rx_alarm_status);
4626
4627
4628 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
4629 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
4630 bnx2x_sfp_set_transmitter(bp, params->port,
4631 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
4632 ext_phy_addr, 0);
4633
4634 if (bnx2x_wait_for_sfp_module_initialized(params)
4635 == 0)
4636 bnx2x_sfp_module_detection(params);
4637 else
4638 DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
4639 }
4640
4641 DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n",
4642 rx_alarm_status);
4643 /* No need to check link status in case of
4644 module plugged in/out */
4645}
4646
ea4e040a
YR		 4647
4648static u8 bnx2x_ext_phy_is_link_up(struct link_params *params,
2f904460
EG		 4649 struct link_vars *vars,
4650 u8 is_mi_int)
ea4e040a
YR		 4651{
4652 struct bnx2x *bp = params->bp;
4653 u32 ext_phy_type;
4654 u8 ext_phy_addr;
4655 u16 val1 = 0, val2;
4656 u16 rx_sd, pcs_status;
4657 u8 ext_phy_link_up = 0;
4658 u8 port = params->port;
4659 if (vars->phy_flags & PHY_XGXS_FLAG) {
4660 ext_phy_addr = ((params->ext_phy_config &
4661 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
4662 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
4663
4664 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
4665 switch (ext_phy_type) {
4666 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
4667 DP(NETIF_MSG_LINK, "XGXS Direct\n");
4668 ext_phy_link_up = 1;
4669 break;
4670
4671 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
4672 DP(NETIF_MSG_LINK, "XGXS 8705\n");
4673 bnx2x_cl45_read(bp, params->port, ext_phy_type,
4674 ext_phy_addr,
4675 MDIO_WIS_DEVAD,
4676 MDIO_WIS_REG_LASI_STATUS, &val1);
4677 DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
4678
4679 bnx2x_cl45_read(bp, params->port, ext_phy_type,
4680 ext_phy_addr,
4681 MDIO_WIS_DEVAD,
4682 MDIO_WIS_REG_LASI_STATUS, &val1);
4683 DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
4684
4685 bnx2x_cl45_read(bp, params->port, ext_phy_type,
4686 ext_phy_addr,
4687 MDIO_PMA_DEVAD,
4688 MDIO_PMA_REG_RX_SD, &rx_sd);
4d295db0
EG		 4689
4690 bnx2x_cl45_read(bp, params->port, ext_phy_type,
4691 ext_phy_addr,
4692 1,
4693 0xc809, &val1);
4694 bnx2x_cl45_read(bp, params->port, ext_phy_type,
4695 ext_phy_addr,
4696 1,
4697 0xc809, &val1);
4698
4699 DP(NETIF_MSG_LINK, "8705 1.c809 val=0x%x\n", val1);
4700 ext_phy_link_up = ((rx_sd & 0x1) && (val1 & (1<<9))
4701 && ((val1 & (1<<8)) == 0));
8c99e7b0
YR		 4702 if (ext_phy_link_up)
4703 vars->line_speed = SPEED_10000;
ea4e040a
YR		 4704 break;
4705
4706 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
589abe3a
EG		 4707 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
4708 DP(NETIF_MSG_LINK, "XGXS 8706/8726\n");
4709 /* Clear RX Alarm*/
ea4e040a
YR		 4710 bnx2x_cl45_read(bp, params->port, ext_phy_type,
4711 ext_phy_addr,
589abe3a
EG		 4712 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM,
4713 &val2);
4714 /* clear LASI indication*/
ea4e040a
YR		 4715 bnx2x_cl45_read(bp, params->port, ext_phy_type,
4716 ext_phy_addr,
589abe3a
EG		 4717 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS,
4718 &val1);
4719 bnx2x_cl45_read(bp, params->port, ext_phy_type,
4720 ext_phy_addr,
4721 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS,
4722 &val2);
4723 DP(NETIF_MSG_LINK, "8706/8726 LASI status 0x%x-->"
4724 "0x%x\n", val1, val2);
ea4e040a
YR		 4725
4726 bnx2x_cl45_read(bp, params->port, ext_phy_type,
4727 ext_phy_addr,
589abe3a
EG		 4728 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD,
4729 &rx_sd);
ea4e040a
YR		 4730 bnx2x_cl45_read(bp, params->port, ext_phy_type,
4731 ext_phy_addr,
589abe3a
EG		 4732 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS,
4733 &pcs_status);
ea4e040a
YR		 4734 bnx2x_cl45_read(bp, params->port, ext_phy_type,
4735 ext_phy_addr,
589abe3a
EG		 4736 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS,
4737 &val2);
ea4e040a
YR		 4738 bnx2x_cl45_read(bp, params->port, ext_phy_type,
4739 ext_phy_addr,
589abe3a
EG		 4740 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS,
4741 &val2);
ea4e040a 4742
589abe3a 4743 DP(NETIF_MSG_LINK, "8706/8726 rx_sd 0x%x"
ea4e040a
YR		 4744 " pcs_status 0x%x 1Gbps link_status 0x%x\n",
4745 rx_sd, pcs_status, val2);
4746 /* link is up if both bit 0 of pmd_rx_sd and
4747 * bit 0 of pcs_status are set, or if the autoneg bit
4748 1 is set
4749 */
4750 ext_phy_link_up = ((rx_sd & pcs_status & 0x1) ||
4751 (val2 & (1<<1)));
57963ed9 4752 if (ext_phy_link_up) {
589abe3a
EG		 4753 if (ext_phy_type ==
4754 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) {
4755 /* If transmitter is disabled,
4756 ignore false link up indication */
4757 bnx2x_cl45_read(bp, params->port,
4758 ext_phy_type,
4759 ext_phy_addr,
4760 MDIO_PMA_DEVAD,
4761 MDIO_PMA_REG_PHY_IDENTIFIER,
4762 &val1);
4763 if (val1 & (1<<15)) {
4764 DP(NETIF_MSG_LINK, "Tx is "
4765 "disabled\n");
4766 ext_phy_link_up = 0;
4767 break;
4768 }
4769 }
4770
57963ed9
YR		 4771 if (val2 & (1<<1))
4772 vars->line_speed = SPEED_1000;
4773 else
4774 vars->line_speed = SPEED_10000;
4775 }
4d295db0
EG		 4776 break;
4777
4778 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
4779 {
4780 u16 link_status = 0;
4781 u16 rx_alarm_status;
4782 /* Check the LASI */
4783 bnx2x_cl45_read(bp, params->port,
4784 ext_phy_type,
4785 ext_phy_addr,
4786 MDIO_PMA_DEVAD,
4787 MDIO_PMA_REG_RX_ALARM, &rx_alarm_status);
4788
4789 DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n",
4790 rx_alarm_status);
4791
4792 bnx2x_cl45_read(bp, params->port,
4793 ext_phy_type,
4794 ext_phy_addr,
4795 MDIO_PMA_DEVAD,
4796 MDIO_PMA_REG_LASI_STATUS, &val1);
4797
4798 DP(NETIF_MSG_LINK,
4799 "8727 LASI status 0x%x\n",
4800 val1);
4801
4802 /* Clear MSG-OUT */
4803 bnx2x_cl45_read(bp, params->port,
4804 ext_phy_type,
4805 ext_phy_addr,
4806 MDIO_PMA_DEVAD,
4807 MDIO_PMA_REG_M8051_MSGOUT_REG,
4808 &val1);
4809
4810 /*
4811 * If a module is present and there is need to check
4812 * for over current
4813 */
4814 if (!(params->feature_config_flags &
4815 FEATURE_CONFIG_BCM8727_NOC) &&
4816 !(rx_alarm_status & (1<<5))) {
4817 /* Check over-current using 8727 GPIO0 input*/
4818 bnx2x_cl45_read(bp, params->port,
4819 ext_phy_type,
4820 ext_phy_addr,
4821 MDIO_PMA_DEVAD,
4822 MDIO_PMA_REG_8727_GPIO_CTRL,
4823 &val1);
4824
4825 if ((val1 & (1<<8)) == 0) {
4826 DP(NETIF_MSG_LINK, "8727 Power fault"
4827 " has been detected on port"
4828 " %d\n", params->port);
4829 printk(KERN_ERR PFX "Error: Power"
4830 " fault on %s Port %d has"
4831 " been detected and the"
4832 " power to that SFP+ module"
4833 " has been removed to prevent"
4834 " failure of the card. Please"
4835 " remove the SFP+ module and"
4836 " restart the system to clear"
4837 " this error.\n"
4838 , bp->dev->name, params->port);
4839 /*
4840 * Disable all RX_ALARMs except for
4841 * mod_abs
4842 */
4843 bnx2x_cl45_write(bp, params->port,
4844 ext_phy_type,
4845 ext_phy_addr,
4846 MDIO_PMA_DEVAD,
4847 MDIO_PMA_REG_RX_ALARM_CTRL,
4848 (1<<5));
4849
4850 bnx2x_cl45_read(bp, params->port,
4851 ext_phy_type,
4852 ext_phy_addr,
4853 MDIO_PMA_DEVAD,
4854 MDIO_PMA_REG_PHY_IDENTIFIER,
4855 &val1);
4856 /* Wait for module_absent_event */
4857 val1 |= (1<<8);
4858 bnx2x_cl45_write(bp, params->port,
4859 ext_phy_type,
4860 ext_phy_addr,
4861 MDIO_PMA_DEVAD,
4862 MDIO_PMA_REG_PHY_IDENTIFIER,
4863 val1);
4864 /* Clear RX alarm */
4865 bnx2x_cl45_read(bp, params->port,
4866 ext_phy_type,
4867 ext_phy_addr,
4868 MDIO_PMA_DEVAD,
4869 MDIO_PMA_REG_RX_ALARM,
4870 &rx_alarm_status);
4871 break;
4872 }
4873 } /* Over current check */
4874
4875 /* When module absent bit is set, check module */
4876 if (rx_alarm_status & (1<<5)) {
4877 bnx2x_8727_handle_mod_abs(params);
4878 /* Enable all mod_abs and link detection bits */
4879 bnx2x_cl45_write(bp, params->port,
4880 ext_phy_type,
4881 ext_phy_addr,
4882 MDIO_PMA_DEVAD,
4883 MDIO_PMA_REG_RX_ALARM_CTRL,
4884 ((1<<5) | (1<<2)));
4885 }
4886
4887 /* If transmitter is disabled,
4888 ignore false link up indication */
4889 bnx2x_cl45_read(bp, params->port,
4890 ext_phy_type,
4891 ext_phy_addr,
4892 MDIO_PMA_DEVAD,
4893 MDIO_PMA_REG_PHY_IDENTIFIER,
4894 &val1);
4895 if (val1 & (1<<15)) {
4896 DP(NETIF_MSG_LINK, "Tx is disabled\n");
4897 ext_phy_link_up = 0;
4898 break;
4899 }
4900
4901 bnx2x_cl45_read(bp, params->port,
4902 ext_phy_type,
4903 ext_phy_addr,
4904 MDIO_PMA_DEVAD,
4905 MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
4906 &link_status);
57963ed9 4907
4d295db0
EG		 4908 /* Bits 0..2 --> speed detected,
4909 bits 13..15--> link is down */
4910 if ((link_status & (1<<2)) &&
4911 (!(link_status & (1<<15)))) {
4912 ext_phy_link_up = 1;
4913 vars->line_speed = SPEED_10000;
4914 } else if ((link_status & (1<<0)) &&
4915 (!(link_status & (1<<13)))) {
4916 ext_phy_link_up = 1;
4917 vars->line_speed = SPEED_1000;
4918 DP(NETIF_MSG_LINK,
4919 "port %x: External link"
4920 " up in 1G\n", params->port);
4921 } else {
4922 ext_phy_link_up = 0;
4923 DP(NETIF_MSG_LINK,
4924 "port %x: External link"
4925 " is down\n", params->port);
4926 }
ea4e040a 4927 break;
4d295db0
EG		 4928 }
4929
ea4e040a
YR		 4930 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
4931 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
4932 {
6bbca910
YR		 4933 u16 link_status = 0;
4934 u16 an1000_status = 0;
ea4e040a
YR		 4935 if (ext_phy_type ==
4936 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072) {
4937 bnx2x_cl45_read(bp, params->port,
4938 ext_phy_type,
4939 ext_phy_addr,
4940 MDIO_PCS_DEVAD,
4941 MDIO_PCS_REG_LASI_STATUS, &val1);
4942 bnx2x_cl45_read(bp, params->port,
4943 ext_phy_type,
4944 ext_phy_addr,
4945 MDIO_PCS_DEVAD,
4946 MDIO_PCS_REG_LASI_STATUS, &val2);
4947 DP(NETIF_MSG_LINK,
4948 "870x LASI status 0x%x->0x%x\n",
4949 val1, val2);
4950
4951 } else {
4952 /* In 8073, port1 is directed through emac0 and
4953 * port0 is directed through emac1
4954 */
4955 bnx2x_cl45_read(bp, params->port,
4956 ext_phy_type,
4957 ext_phy_addr,
4958 MDIO_PMA_DEVAD,
4959 MDIO_PMA_REG_LASI_STATUS, &val1);
4960
ea4e040a 4961 DP(NETIF_MSG_LINK,
6bbca910
YR		 4962 "8703 LASI status 0x%x\n",
4963 val1);
ea4e040a
YR		 4964 }
4965
4966 /* clear the interrupt LASI status register */
4967 bnx2x_cl45_read(bp, params->port,
4968 ext_phy_type,
4969 ext_phy_addr,
4970 MDIO_PCS_DEVAD,
4971 MDIO_PCS_REG_STATUS, &val2);
4972 bnx2x_cl45_read(bp, params->port,
4973 ext_phy_type,
4974 ext_phy_addr,
4975 MDIO_PCS_DEVAD,
4976 MDIO_PCS_REG_STATUS, &val1);
4977 DP(NETIF_MSG_LINK, "807x PCS status 0x%x->0x%x\n",
4978 val2, val1);
6bbca910 4979 /* Clear MSG-OUT */
ea4e040a
YR		 4980 bnx2x_cl45_read(bp, params->port,
4981 ext_phy_type,
4982 ext_phy_addr,
4983 MDIO_PMA_DEVAD,
052a38e0 4984 MDIO_PMA_REG_M8051_MSGOUT_REG,
6bbca910
YR		 4985 &val1);
4986
4987 /* Check the LASI */
ea4e040a
YR		 4988 bnx2x_cl45_read(bp, params->port,
4989 ext_phy_type,
4990 ext_phy_addr,
4991 MDIO_PMA_DEVAD,
6bbca910
YR		 4992 MDIO_PMA_REG_RX_ALARM, &val2);
4993
4994 DP(NETIF_MSG_LINK, "KR 0x9003 0x%x\n", val2);
4995
ea4e040a
YR		 4996 /* Check the link status */
4997 bnx2x_cl45_read(bp, params->port,
4998 ext_phy_type,
4999 ext_phy_addr,
5000 MDIO_PCS_DEVAD,
5001 MDIO_PCS_REG_STATUS, &val2);
5002 DP(NETIF_MSG_LINK, "KR PCS status 0x%x\n", val2);
5003
5004 bnx2x_cl45_read(bp, params->port,
5005 ext_phy_type,
5006 ext_phy_addr,
5007 MDIO_PMA_DEVAD,
5008 MDIO_PMA_REG_STATUS, &val2);
5009 bnx2x_cl45_read(bp, params->port,
5010 ext_phy_type,
5011 ext_phy_addr,
5012 MDIO_PMA_DEVAD,
5013 MDIO_PMA_REG_STATUS, &val1);
5014 ext_phy_link_up = ((val1 & 4) == 4);
5015 DP(NETIF_MSG_LINK, "PMA_REG_STATUS=0x%x\n", val1);
5016 if (ext_phy_type ==
5017 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073) {
6bbca910 5018
ea4e040a 5019 if (ext_phy_link_up &&
6bbca910
YR		 5020 ((params->req_line_speed !=
5021 SPEED_10000))) {
ea4e040a
YR		 5022 if (bnx2x_bcm8073_xaui_wa(params)
5023 != 0) {
5024 ext_phy_link_up = 0;
5025 break;
5026 }
6bbca910
YR		 5027 }
5028 bnx2x_cl45_read(bp, params->port,
052a38e0
EG		 5029 ext_phy_type,
5030 ext_phy_addr,
5031 MDIO_AN_DEVAD,
5032 MDIO_AN_REG_LINK_STATUS,
5033 &an1000_status);
6bbca910 5034 bnx2x_cl45_read(bp, params->port,
052a38e0
EG		 5035 ext_phy_type,
5036 ext_phy_addr,
5037 MDIO_AN_DEVAD,
5038 MDIO_AN_REG_LINK_STATUS,
5039 &an1000_status);
6bbca910 5040
ea4e040a
YR		 5041 /* Check the link status on 1.1.2 */
5042 bnx2x_cl45_read(bp, params->port,
5043 ext_phy_type,
5044 ext_phy_addr,
5045 MDIO_PMA_DEVAD,
5046 MDIO_PMA_REG_STATUS, &val2);
5047 bnx2x_cl45_read(bp, params->port,
5048 ext_phy_type,
5049 ext_phy_addr,
5050 MDIO_PMA_DEVAD,
5051 MDIO_PMA_REG_STATUS, &val1);
5052 DP(NETIF_MSG_LINK, "KR PMA status 0x%x->0x%x,"
5053 "an_link_status=0x%x\n",
5054 val2, val1, an1000_status);
5055
356e2385 5056 ext_phy_link_up = (((val1 & 4) == 4) ||
6bbca910 5057 (an1000_status & (1<<1)));
ea4e040a
YR		 5058 if (ext_phy_link_up &&
5059 bnx2x_8073_is_snr_needed(params)) {
5060 /* The SNR will improve about 2dbby
5061 changing the BW and FEE main tap.*/
5062
5063 /* The 1st write to change FFE main
5064 tap is set before restart AN */
5065 /* Change PLL Bandwidth in EDC
5066 register */
5067 bnx2x_cl45_write(bp, port, ext_phy_type,
5068 ext_phy_addr,
5069 MDIO_PMA_DEVAD,
5070 MDIO_PMA_REG_PLL_BANDWIDTH,
5071 0x26BC);
5072
5073 /* Change CDR Bandwidth in EDC
5074 register */
5075 bnx2x_cl45_write(bp, port, ext_phy_type,
5076 ext_phy_addr,
5077 MDIO_PMA_DEVAD,
5078 MDIO_PMA_REG_CDR_BANDWIDTH,
5079 0x0333);
5080
6bbca910
YR		 5081
5082 }
5083 bnx2x_cl45_read(bp, params->port,
052a38e0
EG		 5084 ext_phy_type,
5085 ext_phy_addr,
5086 MDIO_PMA_DEVAD,
5087 MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
5088 &link_status);
6bbca910
YR		 5089
5090 /* Bits 0..2 --> speed detected,
5091 bits 13..15--> link is down */
5092 if ((link_status & (1<<2)) &&
5093 (!(link_status & (1<<15)))) {
5094 ext_phy_link_up = 1;
5095 vars->line_speed = SPEED_10000;
5096 DP(NETIF_MSG_LINK,
5097 "port %x: External link"
5098 " up in 10G\n", params->port);
5099 } else if ((link_status & (1<<1)) &&
5100 (!(link_status & (1<<14)))) {
5101 ext_phy_link_up = 1;
5102 vars->line_speed = SPEED_2500;
5103 DP(NETIF_MSG_LINK,
5104 "port %x: External link"
5105 " up in 2.5G\n", params->port);
5106 } else if ((link_status & (1<<0)) &&
5107 (!(link_status & (1<<13)))) {
5108 ext_phy_link_up = 1;
5109 vars->line_speed = SPEED_1000;
5110 DP(NETIF_MSG_LINK,
5111 "port %x: External link"
5112 " up in 1G\n", params->port);
5113 } else {
5114 ext_phy_link_up = 0;
5115 DP(NETIF_MSG_LINK,
5116 "port %x: External link"
5117 " is down\n", params->port);
5118 }
5119 } else {
5120 /* See if 1G link is up for the 8072 */
5121 bnx2x_cl45_read(bp, params->port,
052a38e0
EG		 5122 ext_phy_type,
5123 ext_phy_addr,
5124 MDIO_AN_DEVAD,
5125 MDIO_AN_REG_LINK_STATUS,
5126 &an1000_status);
6bbca910 5127 bnx2x_cl45_read(bp, params->port,
052a38e0
EG		 5128 ext_phy_type,
5129 ext_phy_addr,
5130 MDIO_AN_DEVAD,
5131 MDIO_AN_REG_LINK_STATUS,
5132 &an1000_status);
6bbca910
YR		 5133 if (an1000_status & (1<<1)) {
5134 ext_phy_link_up = 1;
5135 vars->line_speed = SPEED_1000;
5136 DP(NETIF_MSG_LINK,
5137 "port %x: External link"
5138 " up in 1G\n", params->port);
5139 } else if (ext_phy_link_up) {
5140 ext_phy_link_up = 1;
5141 vars->line_speed = SPEED_10000;
5142 DP(NETIF_MSG_LINK,
5143 "port %x: External link"
5144 " up in 10G\n", params->port);
ea4e040a
YR		 5145 }
5146 }
6bbca910
YR		 5147
5148
ea4e040a
YR		 5149 break;
5150 }
5151 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
5152 bnx2x_cl45_read(bp, params->port, ext_phy_type,
5153 ext_phy_addr,
5154 MDIO_PMA_DEVAD,
5155 MDIO_PMA_REG_LASI_STATUS, &val2);
5156 bnx2x_cl45_read(bp, params->port, ext_phy_type,
5157 ext_phy_addr,
5158 MDIO_PMA_DEVAD,
5159 MDIO_PMA_REG_LASI_STATUS, &val1);
5160 DP(NETIF_MSG_LINK,
5161 "10G-base-T LASI status 0x%x->0x%x\n",
5162 val2, val1);
5163 bnx2x_cl45_read(bp, params->port, ext_phy_type,
5164 ext_phy_addr,
5165 MDIO_PMA_DEVAD,
5166 MDIO_PMA_REG_STATUS, &val2);
5167 bnx2x_cl45_read(bp, params->port, ext_phy_type,
5168 ext_phy_addr,
5169 MDIO_PMA_DEVAD,
5170 MDIO_PMA_REG_STATUS, &val1);
5171 DP(NETIF_MSG_LINK,
5172 "10G-base-T PMA status 0x%x->0x%x\n",
5173 val2, val1);
5174 ext_phy_link_up = ((val1 & 4) == 4);
5175 /* if link is up
5176 * print the AN outcome of the SFX7101 PHY
5177 */
5178 if (ext_phy_link_up) {
5179 bnx2x_cl45_read(bp, params->port,
5180 ext_phy_type,
5181 ext_phy_addr,
5182 MDIO_AN_DEVAD,
5183 MDIO_AN_REG_MASTER_STATUS,
5184 &val2);
57963ed9 5185 vars->line_speed = SPEED_10000;
ea4e040a
YR		 5186 DP(NETIF_MSG_LINK,
5187 "SFX7101 AN status 0x%x->Master=%x\n",
5188 val2,
5189 (val2 & (1<<14)));
5190 }
5191 break;
28577185 5192 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
28577185 5193 /* Check 10G-BaseT link status */
2f904460 5194 /* Check PMD signal ok */
28577185 5195 bnx2x_cl45_read(bp, params->port, ext_phy_type,
2f904460
EG		 5196 ext_phy_addr,
5197 MDIO_AN_DEVAD,
5198 0xFFFA,
5199 &val1);
28577185
EG		 5200 bnx2x_cl45_read(bp, params->port, ext_phy_type,
5201 ext_phy_addr,
2f904460
EG		 5202 MDIO_PMA_DEVAD,
5203 MDIO_PMA_REG_8481_PMD_SIGNAL,
5204 &val2);
5205 DP(NETIF_MSG_LINK, "PMD_SIGNAL 1.a811 = 0x%x\n", val2);
5206
5207 /* Check link 10G */
5208 if (val2 & (1<<11)) {
28577185
EG		 5209 vars->line_speed = SPEED_10000;
5210 ext_phy_link_up = 1;
2f904460
EG		 5211 bnx2x_8481_set_10G_led_mode(params,
5212 ext_phy_type,
5213 ext_phy_addr);
5214 } else { /* Check Legacy speed link */
5215 u16 legacy_status, legacy_speed;
5216
5217 /* Enable expansion register 0x42
5218 (Operation mode status) */
5219 bnx2x_cl45_write(bp, params->port,
5220 ext_phy_type,
5221 ext_phy_addr,
5222 MDIO_AN_DEVAD,
5223 MDIO_AN_REG_8481_EXPANSION_REG_ACCESS,
5224 0xf42);
ea4e040a 5225
2f904460
EG		 5226 /* Get legacy speed operation status */
5227 bnx2x_cl45_read(bp, params->port,
5228 ext_phy_type,
5229 ext_phy_addr,
5230 MDIO_AN_DEVAD,
5231 MDIO_AN_REG_8481_EXPANSION_REG_RD_RW,
5232 &legacy_status);
5233
5234 DP(NETIF_MSG_LINK, "Legacy speed status"
5235 " = 0x%x\n", legacy_status);
5236 ext_phy_link_up = ((legacy_status & (1<<11))
5237 == (1<<11));
5238 if (ext_phy_link_up) {
5239 legacy_speed = (legacy_status & (3<<9));
5240 if (legacy_speed == (0<<9))
5241 vars->line_speed = SPEED_10;
5242 else if (legacy_speed == (1<<9))
5243 vars->line_speed =
5244 SPEED_100;
5245 else if (legacy_speed == (2<<9))
5246 vars->line_speed =
5247 SPEED_1000;
5248 else /* Should not happen */
5249 vars->line_speed = 0;
5250
5251 if (legacy_status & (1<<8))
5252 vars->duplex = DUPLEX_FULL;
5253 else
5254 vars->duplex = DUPLEX_HALF;
5255
5256 DP(NETIF_MSG_LINK, "Link is up "
5257 "in %dMbps, is_duplex_full"
5258 "= %d\n",
5259 vars->line_speed,
5260 (vars->duplex == DUPLEX_FULL));
5261 bnx2x_8481_set_legacy_led_mode(params,
5262 ext_phy_type,
5263 ext_phy_addr);
28577185
EG		 5264 }
5265 }
5266
5267 break;
ea4e040a
YR		 5268 default:
5269 DP(NETIF_MSG_LINK, "BAD XGXS ext_phy_config 0x%x\n",
5270 params->ext_phy_config);
5271 ext_phy_link_up = 0;
5272 break;
5273 }
57937203
EG		 5274 /* Set SGMII mode for external phy */
5275 if (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) {
5276 if (vars->line_speed < SPEED_1000)
5277 vars->phy_flags |= PHY_SGMII_FLAG;
5278 else
5279 vars->phy_flags &= ~PHY_SGMII_FLAG;
5280 }
ea4e040a
YR		 5281
5282 } else { /* SerDes */
5283 ext_phy_type = SERDES_EXT_PHY_TYPE(params->ext_phy_config);
5284 switch (ext_phy_type) {
5285 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT:
5286 DP(NETIF_MSG_LINK, "SerDes Direct\n");
5287 ext_phy_link_up = 1;
5288 break;
5289
5290 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482:
5291 DP(NETIF_MSG_LINK, "SerDes 5482\n");
5292 ext_phy_link_up = 1;
5293 break;
5294
5295 default:
5296 DP(NETIF_MSG_LINK,
5297 "BAD SerDes ext_phy_config 0x%x\n",
5298 params->ext_phy_config);
5299 ext_phy_link_up = 0;
5300 break;
5301 }
5302 }
5303
5304 return ext_phy_link_up;
5305}
5306
5307static void bnx2x_link_int_enable(struct link_params *params)
5308{
5309 u8 port = params->port;
5310 u32 ext_phy_type;
5311 u32 mask;
5312 struct bnx2x *bp = params->bp;
5313 /* setting the status to report on link up
5314 for either XGXS or SerDes */
5315
5316 if (params->switch_cfg == SWITCH_CFG_10G) {
5317 mask = (NIG_MASK_XGXS0_LINK10G |
5318 NIG_MASK_XGXS0_LINK_STATUS);
5319 DP(NETIF_MSG_LINK, "enabled XGXS interrupt\n");
5320 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
5321 if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
5322 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
5323 (ext_phy_type !=
5324 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)) {
5325 mask |= NIG_MASK_MI_INT;
5326 DP(NETIF_MSG_LINK, "enabled external phy int\n");
5327 }
5328
5329 } else { /* SerDes */
5330 mask = NIG_MASK_SERDES0_LINK_STATUS;
5331 DP(NETIF_MSG_LINK, "enabled SerDes interrupt\n");
5332 ext_phy_type = SERDES_EXT_PHY_TYPE(params->ext_phy_config);
5333 if ((ext_phy_type !=
5334 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT) &&
5335 (ext_phy_type !=
5336 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN)) {
5337 mask |= NIG_MASK_MI_INT;
5338 DP(NETIF_MSG_LINK, "enabled external phy int\n");
5339 }
5340 }
5341 bnx2x_bits_en(bp,
5342 NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
5343 mask);
5344 DP(NETIF_MSG_LINK, "port %x, is_xgxs=%x, int_status 0x%x\n", port,
5345 (params->switch_cfg == SWITCH_CFG_10G),
5346 REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
5347
5348 DP(NETIF_MSG_LINK, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x\n",
5349 REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
5350 REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18),
5351 REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS+port*0x3c));
5352 DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
5353 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
5354 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
5355}
5356
2f904460
EG		 5357static void bnx2x_8481_rearm_latch_signal(struct bnx2x *bp, u8 port,
5358 u8 is_mi_int)
5359{
5360 u32 latch_status = 0, is_mi_int_status;
5361 /* Disable the MI INT ( external phy int )
5362 * by writing 1 to the status register. Link down indication
5363 * is high-active-signal, so in this case we need to write the
5364 * status to clear the XOR
5365 */
5366 /* Read Latched signals */
5367 latch_status = REG_RD(bp,
5368 NIG_REG_LATCH_STATUS_0 + port*8);
5369 is_mi_int_status = REG_RD(bp,
5370 NIG_REG_STATUS_INTERRUPT_PORT0 + port*4);
5371 DP(NETIF_MSG_LINK, "original_signal = 0x%x, nig_status = 0x%x,"
5372 "latch_status = 0x%x\n",
5373 is_mi_int, is_mi_int_status, latch_status);
5374 /* Handle only those with latched-signal=up.*/
5375 if (latch_status & 1) {
5376 /* For all latched-signal=up,Write original_signal to status */
5377 if (is_mi_int)
5378 bnx2x_bits_en(bp,
5379 NIG_REG_STATUS_INTERRUPT_PORT0
5380 + port*4,
5381 NIG_STATUS_EMAC0_MI_INT);
5382 else
5383 bnx2x_bits_dis(bp,
5384 NIG_REG_STATUS_INTERRUPT_PORT0
5385 + port*4,
5386 NIG_STATUS_EMAC0_MI_INT);
5387 /* For all latched-signal=up : Re-Arm Latch signals */
5388 REG_WR(bp, NIG_REG_LATCH_STATUS_0 + port*8,
5389 (latch_status & 0xfffe) | (latch_status & 1));
5390 }
5391}
ea4e040a
YR		 5392/*
5393 * link management
5394 */
5395static void bnx2x_link_int_ack(struct link_params *params,
2f904460
EG		 5396 struct link_vars *vars, u8 is_10g,
5397 u8 is_mi_int)
ea4e040a
YR		 5398{
5399 struct bnx2x *bp = params->bp;
5400 u8 port = params->port;
5401
5402 /* first reset all status
5403 * we assume only one line will be change at a time */
5404 bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
5405 (NIG_STATUS_XGXS0_LINK10G |
5406 NIG_STATUS_XGXS0_LINK_STATUS |
5407 NIG_STATUS_SERDES0_LINK_STATUS));
2f904460
EG		 5408 if (XGXS_EXT_PHY_TYPE(params->ext_phy_config)
5409 == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481) {
5410 bnx2x_8481_rearm_latch_signal(bp, port, is_mi_int);
5411 }
ea4e040a
YR		 5412 if (vars->phy_link_up) {
5413 if (is_10g) {
5414 /* Disable the 10G link interrupt
5415 * by writing 1 to the status register
5416 */
5417 DP(NETIF_MSG_LINK, "10G XGXS phy link up\n");
5418 bnx2x_bits_en(bp,
5419 NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
5420 NIG_STATUS_XGXS0_LINK10G);
5421
5422 } else if (params->switch_cfg == SWITCH_CFG_10G) {
5423 /* Disable the link interrupt
5424 * by writing 1 to the relevant lane
5425 * in the status register
5426 */
5427 u32 ser_lane = ((params->lane_config &
5428 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
5429 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
5430
2f904460
EG		 5431 DP(NETIF_MSG_LINK, "%d speed XGXS phy link up\n",
5432 vars->line_speed);
ea4e040a
YR		 5433 bnx2x_bits_en(bp,
5434 NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
5435 ((1 << ser_lane) <<
5436 NIG_STATUS_XGXS0_LINK_STATUS_SIZE));
5437
5438 } else { /* SerDes */
5439 DP(NETIF_MSG_LINK, "SerDes phy link up\n");
5440 /* Disable the link interrupt
5441 * by writing 1 to the status register
5442 */
5443 bnx2x_bits_en(bp,
5444 NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
5445 NIG_STATUS_SERDES0_LINK_STATUS);
5446 }
5447
5448 } else { /* link_down */
5449 }
5450}
5451
5452static u8 bnx2x_format_ver(u32 num, u8 *str, u16 len)
5453{
5454 u8 *str_ptr = str;
5455 u32 mask = 0xf0000000;
5456 u8 shift = 8*4;
5457 u8 digit;
5458 if (len < 10) {
025dfdaf 5459 /* Need more than 10chars for this format */
ea4e040a
YR		 5460 *str_ptr = '\0';
5461 return -EINVAL;
5462 }
5463 while (shift > 0) {
5464
5465 shift -= 4;
5466 digit = ((num & mask) >> shift);
5467 if (digit < 0xa)
5468 *str_ptr = digit + '0';
5469 else
5470 *str_ptr = digit - 0xa + 'a';
5471 str_ptr++;
5472 mask = mask >> 4;
5473 if (shift == 4*4) {
5474 *str_ptr = ':';
5475 str_ptr++;
5476 }
5477 }
5478 *str_ptr = '\0';
5479 return 0;
5480}
5481
ea4e040a
YR		 5482u8 bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 driver_loaded,
5483 u8 *version, u16 len)
5484{
0376d5b2 5485 struct bnx2x *bp;
ea4e040a 5486 u32 ext_phy_type = 0;
a35da8db 5487 u32 spirom_ver = 0;
97b41dad 5488 u8 status;
ea4e040a
YR		 5489
5490 if (version == NULL || params == NULL)
5491 return -EINVAL;
0376d5b2 5492 bp = params->bp;
ea4e040a 5493
a35da8db
EG		 5494 spirom_ver = REG_RD(bp, params->shmem_base +
5495 offsetof(struct shmem_region,
5496 port_mb[params->port].ext_phy_fw_version));
5497
97b41dad 5498 status = 0;
ea4e040a
YR		 5499 /* reset the returned value to zero */
5500 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
ea4e040a
YR		 5501 switch (ext_phy_type) {
5502 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
5503
5504 if (len < 5)
5505 return -EINVAL;
5506
a35da8db
EG		 5507 version[0] = (spirom_ver & 0xFF);
5508 version[1] = (spirom_ver & 0xFF00) >> 8;
5509 version[2] = (spirom_ver & 0xFF0000) >> 16;
5510 version[3] = (spirom_ver & 0xFF000000) >> 24;
ea4e040a
YR		 5511 version[4] = '\0';
5512
ea4e040a
YR		 5513 break;
5514 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
5515 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
4d295db0 5516 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
ea4e040a 5517 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
589abe3a 5518 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
b1607af5
EG		 5519 status = bnx2x_format_ver(spirom_ver, version, len);
5520 break;
9223dea6 5521 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
b1607af5
EG		 5522 spirom_ver = ((spirom_ver & 0xF80) >> 7) << 16 |
5523 (spirom_ver & 0x7F);
a35da8db 5524 status = bnx2x_format_ver(spirom_ver, version, len);
ea4e040a 5525 break;
ea4e040a 5526 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
97b41dad
EG		 5527 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
5528 version[0] = '\0';
ea4e040a
YR		 5529 break;
5530
5531 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
5532 DP(NETIF_MSG_LINK, "bnx2x_get_ext_phy_fw_version:"
5533 " type is FAILURE!\n");
5534 status = -EINVAL;
5535 break;
5536
5537 default:
5538 break;
5539 }
5540 return status;
5541}
5542
5543static void bnx2x_set_xgxs_loopback(struct link_params *params,
5544 struct link_vars *vars,
5545 u8 is_10g)
5546{
5547 u8 port = params->port;
5548 struct bnx2x *bp = params->bp;
5549
5550 if (is_10g) {
6378c025 5551 u32 md_devad;
ea4e040a
YR		 5552
5553 DP(NETIF_MSG_LINK, "XGXS 10G loopback enable\n");
5554
5555 /* change the uni_phy_addr in the nig */
5556 md_devad = REG_RD(bp, (NIG_REG_XGXS0_CTRL_MD_DEVAD +
5557 port*0x18));
5558
5559 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, 0x5);
5560
5561 bnx2x_cl45_write(bp, port, 0,
5562 params->phy_addr,
5563 5,
5564 (MDIO_REG_BANK_AER_BLOCK +
5565 (MDIO_AER_BLOCK_AER_REG & 0xf)),
5566 0x2800);
5567
5568 bnx2x_cl45_write(bp, port, 0,
5569 params->phy_addr,
5570 5,
5571 (MDIO_REG_BANK_CL73_IEEEB0 +
5572 (MDIO_CL73_IEEEB0_CL73_AN_CONTROL & 0xf)),
5573 0x6041);
3858276b 5574 msleep(200);
ea4e040a
YR		 5575 /* set aer mmd back */
5576 bnx2x_set_aer_mmd(params, vars);
5577
5578 /* and md_devad */
5579 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
5580 md_devad);
5581
5582 } else {
5583 u16 mii_control;
5584
5585 DP(NETIF_MSG_LINK, "XGXS 1G loopback enable\n");
5586
5587 CL45_RD_OVER_CL22(bp, port,
5588 params->phy_addr,
5589 MDIO_REG_BANK_COMBO_IEEE0,
5590 MDIO_COMBO_IEEE0_MII_CONTROL,
5591 &mii_control);
5592
5593 CL45_WR_OVER_CL22(bp, port,
5594 params->phy_addr,
5595 MDIO_REG_BANK_COMBO_IEEE0,
5596 MDIO_COMBO_IEEE0_MII_CONTROL,
5597 (mii_control |
5598 MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK));
5599 }
5600}
5601
5602
5603static void bnx2x_ext_phy_loopback(struct link_params *params)
5604{
5605 struct bnx2x *bp = params->bp;
5606 u8 ext_phy_addr;
5607 u32 ext_phy_type;
5608
5609 if (params->switch_cfg == SWITCH_CFG_10G) {
5610 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
5611 /* CL37 Autoneg Enabled */
5612 ext_phy_addr = ((params->ext_phy_config &
5613 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
5614 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
5615 switch (ext_phy_type) {
5616 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
5617 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN:
5618 DP(NETIF_MSG_LINK,
5619 "ext_phy_loopback: We should not get here\n");
5620 break;
5621 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
5622 DP(NETIF_MSG_LINK, "ext_phy_loopback: 8705\n");
5623 break;
5624 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
5625 DP(NETIF_MSG_LINK, "ext_phy_loopback: 8706\n");
5626 break;
589abe3a
EG		 5627 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
5628 DP(NETIF_MSG_LINK, "PMA/PMD ext_phy_loopback: 8726\n");
5629 bnx2x_cl45_write(bp, params->port, ext_phy_type,
5630 ext_phy_addr,
5631 MDIO_PMA_DEVAD,
5632 MDIO_PMA_REG_CTRL,
5633 0x0001);
5634 break;
ea4e040a
YR		 5635 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
5636 /* SFX7101_XGXS_TEST1 */
5637 bnx2x_cl45_write(bp, params->port, ext_phy_type,
5638 ext_phy_addr,
5639 MDIO_XS_DEVAD,
5640 MDIO_XS_SFX7101_XGXS_TEST1,
5641 0x100);
5642 DP(NETIF_MSG_LINK,
5643 "ext_phy_loopback: set ext phy loopback\n");
5644 break;
5645 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
5646
5647 break;
5648 } /* switch external PHY type */
5649 } else {
5650 /* serdes */
5651 ext_phy_type = SERDES_EXT_PHY_TYPE(params->ext_phy_config);
5652 ext_phy_addr = (params->ext_phy_config &
5653 PORT_HW_CFG_SERDES_EXT_PHY_ADDR_MASK)
5654 >> PORT_HW_CFG_SERDES_EXT_PHY_ADDR_SHIFT;
5655 }
5656}
5657
5658
5659/*
5660 *------------------------------------------------------------------------
5661 * bnx2x_override_led_value -
5662 *
5663 * Override the led value of the requsted led
5664 *
5665 *------------------------------------------------------------------------
5666 */
5667u8 bnx2x_override_led_value(struct bnx2x *bp, u8 port,
5668 u32 led_idx, u32 value)
5669{
5670 u32 reg_val;
5671
5672 /* If port 0 then use EMAC0, else use EMAC1*/
5673 u32 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
5674
5675 DP(NETIF_MSG_LINK,
5676 "bnx2x_override_led_value() port %x led_idx %d value %d\n",
5677 port, led_idx, value);
5678
5679 switch (led_idx) {
5680 case 0: /* 10MB led */
5681 /* Read the current value of the LED register in
5682 the EMAC block */
5683 reg_val = REG_RD(bp, emac_base + EMAC_REG_EMAC_LED);
5684 /* Set the OVERRIDE bit to 1 */
5685 reg_val |= EMAC_LED_OVERRIDE;
5686 /* If value is 1, set the 10M_OVERRIDE bit,
5687 otherwise reset it.*/
5688 reg_val = (value == 1) ? (reg_val | EMAC_LED_10MB_OVERRIDE) :
5689 (reg_val & ~EMAC_LED_10MB_OVERRIDE);
5690 REG_WR(bp, emac_base + EMAC_REG_EMAC_LED, reg_val);
5691 break;
5692 case 1: /*100MB led */
5693 /*Read the current value of the LED register in
5694 the EMAC block */
5695 reg_val = REG_RD(bp, emac_base + EMAC_REG_EMAC_LED);
5696 /* Set the OVERRIDE bit to 1 */
5697 reg_val |= EMAC_LED_OVERRIDE;
5698 /* If value is 1, set the 100M_OVERRIDE bit,
5699 otherwise reset it.*/
5700 reg_val = (value == 1) ? (reg_val | EMAC_LED_100MB_OVERRIDE) :
5701 (reg_val & ~EMAC_LED_100MB_OVERRIDE);
5702 REG_WR(bp, emac_base + EMAC_REG_EMAC_LED, reg_val);
5703 break;
5704 case 2: /* 1000MB led */
5705 /* Read the current value of the LED register in the
5706 EMAC block */
5707 reg_val = REG_RD(bp, emac_base + EMAC_REG_EMAC_LED);
5708 /* Set the OVERRIDE bit to 1 */
5709 reg_val |= EMAC_LED_OVERRIDE;
5710 /* If value is 1, set the 1000M_OVERRIDE bit, otherwise
5711 reset it. */
5712 reg_val = (value == 1) ? (reg_val | EMAC_LED_1000MB_OVERRIDE) :
5713 (reg_val & ~EMAC_LED_1000MB_OVERRIDE);
5714 REG_WR(bp, emac_base + EMAC_REG_EMAC_LED, reg_val);
5715 break;
5716 case 3: /* 2500MB led */
5717 /* Read the current value of the LED register in the
5718 EMAC block*/
5719 reg_val = REG_RD(bp, emac_base + EMAC_REG_EMAC_LED);
5720 /* Set the OVERRIDE bit to 1 */
5721 reg_val |= EMAC_LED_OVERRIDE;
5722 /* If value is 1, set the 2500M_OVERRIDE bit, otherwise
5723 reset it.*/
5724 reg_val = (value == 1) ? (reg_val | EMAC_LED_2500MB_OVERRIDE) :
5725 (reg_val & ~EMAC_LED_2500MB_OVERRIDE);
5726 REG_WR(bp, emac_base + EMAC_REG_EMAC_LED, reg_val);
5727 break;
5728 case 4: /*10G led */
5729 if (port == 0) {
5730 REG_WR(bp, NIG_REG_LED_10G_P0,
5731 value);
5732 } else {
5733 REG_WR(bp, NIG_REG_LED_10G_P1,
5734 value);
5735 }
5736 break;
5737 case 5: /* TRAFFIC led */
5738 /* Find if the traffic control is via BMAC or EMAC */
5739 if (port == 0)
5740 reg_val = REG_RD(bp, NIG_REG_NIG_EMAC0_EN);
5741 else
5742 reg_val = REG_RD(bp, NIG_REG_NIG_EMAC1_EN);
5743
5744 /* Override the traffic led in the EMAC:*/
5745 if (reg_val == 1) {
5746 /* Read the current value of the LED register in
5747 the EMAC block */
5748 reg_val = REG_RD(bp, emac_base +
5749 EMAC_REG_EMAC_LED);
5750 /* Set the TRAFFIC_OVERRIDE bit to 1 */
5751 reg_val |= EMAC_LED_OVERRIDE;
5752 /* If value is 1, set the TRAFFIC bit, otherwise
5753 reset it.*/
5754 reg_val = (value == 1) ? (reg_val | EMAC_LED_TRAFFIC) :
5755 (reg_val & ~EMAC_LED_TRAFFIC);
5756 REG_WR(bp, emac_base + EMAC_REG_EMAC_LED, reg_val);
5757 } else { /* Override the traffic led in the BMAC: */
5758 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0
5759 + port*4, 1);
5760 REG_WR(bp, NIG_REG_LED_CONTROL_TRAFFIC_P0 + port*4,
5761 value);
5762 }
5763 break;
5764 default:
5765 DP(NETIF_MSG_LINK,
5766 "bnx2x_override_led_value() unknown led index %d "
5767 "(should be 0-5)\n", led_idx);
5768 return -EINVAL;
5769 }
5770
5771 return 0;
5772}
5773
5774
5775u8 bnx2x_set_led(struct bnx2x *bp, u8 port, u8 mode, u32 speed,
5776 u16 hw_led_mode, u32 chip_id)
5777{
5778 u8 rc = 0;
345b5d52
EG		 5779 u32 tmp;
5780 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
ea4e040a
YR		 5781 DP(NETIF_MSG_LINK, "bnx2x_set_led: port %x, mode %d\n", port, mode);
5782 DP(NETIF_MSG_LINK, "speed 0x%x, hw_led_mode 0x%x\n",
5783 speed, hw_led_mode);
5784 switch (mode) {
5785 case LED_MODE_OFF:
5786 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 0);
5787 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
5788 SHARED_HW_CFG_LED_MAC1);
345b5d52
EG		 5789
5790 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
3196a88a 5791 EMAC_WR(bp, EMAC_REG_EMAC_LED, (tmp | EMAC_LED_OVERRIDE));
ea4e040a
YR		 5792 break;
5793
5794 case LED_MODE_OPER:
5795 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, hw_led_mode);
5796 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 +
5797 port*4, 0);
5798 /* Set blinking rate to ~15.9Hz */
5799 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
5800 LED_BLINK_RATE_VAL);
5801 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 +
5802 port*4, 1);
345b5d52 5803 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
3196a88a 5804 EMAC_WR(bp, EMAC_REG_EMAC_LED,
345b5d52
EG		 5805 (tmp & (~EMAC_LED_OVERRIDE)));
5806
34f80b04
EG		 5807 if (!CHIP_IS_E1H(bp) &&
5808 ((speed == SPEED_2500) ||
ea4e040a
YR		 5809 (speed == SPEED_1000) ||
5810 (speed == SPEED_100) ||
5811 (speed == SPEED_10))) {
5812 /* On Everest 1 Ax chip versions for speeds less than
5813 10G LED scheme is different */
5814 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0
5815 + port*4, 1);
5816 REG_WR(bp, NIG_REG_LED_CONTROL_TRAFFIC_P0 +
5817 port*4, 0);
5818 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 +
5819 port*4, 1);
5820 }
5821 break;
5822
5823 default:
5824 rc = -EINVAL;
5825 DP(NETIF_MSG_LINK, "bnx2x_set_led: Invalid led mode %d\n",
5826 mode);
5827 break;
5828 }
5829 return rc;
5830
5831}
5832
5833u8 bnx2x_test_link(struct link_params *params, struct link_vars *vars)
5834{
5835 struct bnx2x *bp = params->bp;
5836 u16 gp_status = 0;
5837
5838 CL45_RD_OVER_CL22(bp, params->port,
5839 params->phy_addr,
5840 MDIO_REG_BANK_GP_STATUS,
5841 MDIO_GP_STATUS_TOP_AN_STATUS1,
5842 &gp_status);
5843 /* link is up only if both local phy and external phy are up */
5844 if ((gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) &&
2f904460 5845 bnx2x_ext_phy_is_link_up(params, vars, 1))
ea4e040a
YR		 5846 return 0;
5847
5848 return -ESRCH;
5849}
5850
5851static u8 bnx2x_link_initialize(struct link_params *params,
5852 struct link_vars *vars)
5853{
5854 struct bnx2x *bp = params->bp;
5855 u8 port = params->port;
5856 u8 rc = 0;
57963ed9
YR		 5857 u8 non_ext_phy;
5858 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
ea4e040a
YR		 5859 /* Activate the external PHY */
5860 bnx2x_ext_phy_reset(params, vars);
5861
5862 bnx2x_set_aer_mmd(params, vars);
5863
5864 if (vars->phy_flags & PHY_XGXS_FLAG)
5865 bnx2x_set_master_ln(params);
5866
5867 rc = bnx2x_reset_unicore(params);
5868 /* reset the SerDes and wait for reset bit return low */
5869 if (rc != 0)
5870 return rc;
5871
5872 bnx2x_set_aer_mmd(params, vars);
5873
5874 /* setting the masterLn_def again after the reset */
5875 if (vars->phy_flags & PHY_XGXS_FLAG) {
5876 bnx2x_set_master_ln(params);
5877 bnx2x_set_swap_lanes(params);
5878 }
5879
ea4e040a 5880 if (vars->phy_flags & PHY_XGXS_FLAG) {
44722d1d 5881 if ((params->req_line_speed &&
ea4e040a 5882 ((params->req_line_speed == SPEED_100) ||
44722d1d
EG		 5883 (params->req_line_speed == SPEED_10))) ||
5884 (!params->req_line_speed &&
5885 (params->speed_cap_mask >=
5886 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) &&
5887 (params->speed_cap_mask <
5888 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
5889 )) {
ea4e040a
YR		 5890 vars->phy_flags |= PHY_SGMII_FLAG;
5891 } else {
5892 vars->phy_flags &= ~PHY_SGMII_FLAG;
5893 }
5894 }
57963ed9
YR		 5895 /* In case of external phy existance, the line speed would be the
5896 line speed linked up by the external phy. In case it is direct only,
5897 then the line_speed during initialization will be equal to the
5898 req_line_speed*/
5899 vars->line_speed = params->req_line_speed;
ea4e040a 5900
8c99e7b0 5901 bnx2x_calc_ieee_aneg_adv(params, &vars->ieee_fc);
ea4e040a 5902
57963ed9
YR		 5903 /* init ext phy and enable link state int */
5904 non_ext_phy = ((ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ||
8660d8c3 5905 (params->loopback_mode == LOOPBACK_XGXS_10));
57963ed9
YR		 5906
5907 if (non_ext_phy ||
589abe3a 5908 (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705) ||
28577185 5909 (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) ||
8660d8c3 5910 (params->loopback_mode == LOOPBACK_EXT_PHY)) {
57963ed9
YR		 5911 if (params->req_line_speed == SPEED_AUTO_NEG)
5912 bnx2x_set_parallel_detection(params, vars->phy_flags);
239d686d 5913 bnx2x_init_internal_phy(params, vars, non_ext_phy);
ea4e040a
YR		 5914 }
5915
57963ed9
YR		 5916 if (!non_ext_phy)
5917 rc |= bnx2x_ext_phy_init(params, vars);
ea4e040a
YR		 5918
5919 bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
57963ed9
YR		 5920 (NIG_STATUS_XGXS0_LINK10G |
5921 NIG_STATUS_XGXS0_LINK_STATUS |
5922 NIG_STATUS_SERDES0_LINK_STATUS));
ea4e040a
YR		 5923
5924 return rc;
5925
5926}
5927
5928
5929u8 bnx2x_phy_init(struct link_params *params, struct link_vars *vars)
5930{
5931 struct bnx2x *bp = params->bp;
5932
5933 u32 val;
3196a88a 5934 DP(NETIF_MSG_LINK, "Phy Initialization started \n");
ea4e040a
YR		 5935 DP(NETIF_MSG_LINK, "req_speed = %d, req_flowctrl=%d\n",
5936 params->req_line_speed, params->req_flow_ctrl);
5937 vars->link_status = 0;
57963ed9
YR		 5938 vars->phy_link_up = 0;
5939 vars->link_up = 0;
5940 vars->line_speed = 0;
5941 vars->duplex = DUPLEX_FULL;
c0700f90 5942 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
57963ed9
YR		 5943 vars->mac_type = MAC_TYPE_NONE;
5944
ea4e040a
YR		 5945 if (params->switch_cfg == SWITCH_CFG_1G)
5946 vars->phy_flags = PHY_SERDES_FLAG;
5947 else
5948 vars->phy_flags = PHY_XGXS_FLAG;
5949
3196a88a 5950
ea4e040a
YR		 5951 /* disable attentions */
5952 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
5953 (NIG_MASK_XGXS0_LINK_STATUS |
5954 NIG_MASK_XGXS0_LINK10G |
5955 NIG_MASK_SERDES0_LINK_STATUS |
5956 NIG_MASK_MI_INT));
5957
5958 bnx2x_emac_init(params, vars);
5959
5960 if (CHIP_REV_IS_FPGA(bp)) {
5961 vars->link_up = 1;
5962 vars->line_speed = SPEED_10000;
5963 vars->duplex = DUPLEX_FULL;
c0700f90 5964 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
ea4e040a 5965 vars->link_status = (LINK_STATUS_LINK_UP | LINK_10GTFD);
34f80b04
EG		 5966 /* enable on E1.5 FPGA */
5967 if (CHIP_IS_E1H(bp)) {
5968 vars->flow_ctrl |=
c0700f90 5969 (BNX2X_FLOW_CTRL_TX | BNX2X_FLOW_CTRL_RX);
34f80b04
EG		 5970 vars->link_status |=
5971 (LINK_STATUS_TX_FLOW_CONTROL_ENABLED |
5972 LINK_STATUS_RX_FLOW_CONTROL_ENABLED);
5973 }
ea4e040a
YR		 5974
5975 bnx2x_emac_enable(params, vars, 0);
5976 bnx2x_pbf_update(params, vars->flow_ctrl, vars->line_speed);
5977 /* disable drain */
5978 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE
5979 + params->port*4, 0);
5980
5981 /* update shared memory */
5982 bnx2x_update_mng(params, vars->link_status);
5983
5984 return 0;
5985
5986 } else
5987 if (CHIP_REV_IS_EMUL(bp)) {
5988
5989 vars->link_up = 1;
5990 vars->line_speed = SPEED_10000;
5991 vars->duplex = DUPLEX_FULL;
c0700f90 5992 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
ea4e040a
YR		 5993 vars->link_status = (LINK_STATUS_LINK_UP | LINK_10GTFD);
5994
5995 bnx2x_bmac_enable(params, vars, 0);
5996
5997 bnx2x_pbf_update(params, vars->flow_ctrl, vars->line_speed);
5998 /* Disable drain */
5999 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE
6000 + params->port*4, 0);
6001
6002 /* update shared memory */
6003 bnx2x_update_mng(params, vars->link_status);
6004
6005 return 0;
6006
6007 } else
6008 if (params->loopback_mode == LOOPBACK_BMAC) {
6009 vars->link_up = 1;
6010 vars->line_speed = SPEED_10000;
6011 vars->duplex = DUPLEX_FULL;
c0700f90 6012 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
ea4e040a
YR		 6013 vars->mac_type = MAC_TYPE_BMAC;
6014
6015 vars->phy_flags = PHY_XGXS_FLAG;
6016
6017 bnx2x_phy_deassert(params, vars->phy_flags);
6018 /* set bmac loopback */
6019 bnx2x_bmac_enable(params, vars, 1);
6020
6021 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE +
6022 params->port*4, 0);
6023 } else if (params->loopback_mode == LOOPBACK_EMAC) {
6024 vars->link_up = 1;
6025 vars->line_speed = SPEED_1000;
6026 vars->duplex = DUPLEX_FULL;
c0700f90 6027 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
ea4e040a
YR		 6028 vars->mac_type = MAC_TYPE_EMAC;
6029
6030 vars->phy_flags = PHY_XGXS_FLAG;
6031
6032 bnx2x_phy_deassert(params, vars->phy_flags);
6033 /* set bmac loopback */
6034 bnx2x_emac_enable(params, vars, 1);
6035 bnx2x_emac_program(params, vars->line_speed,
6036 vars->duplex);
6037 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE +
6038 params->port*4, 0);
6039 } else if ((params->loopback_mode == LOOPBACK_XGXS_10) ||
6040 (params->loopback_mode == LOOPBACK_EXT_PHY)) {
6041 vars->link_up = 1;
6042 vars->line_speed = SPEED_10000;
6043 vars->duplex = DUPLEX_FULL;
c0700f90 6044 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
ea4e040a
YR		 6045
6046 vars->phy_flags = PHY_XGXS_FLAG;
6047
6048 val = REG_RD(bp,
6049 NIG_REG_XGXS0_CTRL_PHY_ADDR+
6050 params->port*0x18);
6051 params->phy_addr = (u8)val;
6052
6053 bnx2x_phy_deassert(params, vars->phy_flags);
6054 bnx2x_link_initialize(params, vars);
6055
6056 vars->mac_type = MAC_TYPE_BMAC;
6057
6058 bnx2x_bmac_enable(params, vars, 0);
6059
6060 if (params->loopback_mode == LOOPBACK_XGXS_10) {
6061 /* set 10G XGXS loopback */
6062 bnx2x_set_xgxs_loopback(params, vars, 1);
6063 } else {
6064 /* set external phy loopback */
6065 bnx2x_ext_phy_loopback(params);
6066 }
6067 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE +
6068 params->port*4, 0);
ba71d313
EG		 6069
6070 bnx2x_set_led(bp, params->port, LED_MODE_OPER,
6071 vars->line_speed, params->hw_led_mode,
6072 params->chip_id);
6073
ea4e040a
YR		 6074 } else
6075 /* No loopback */
6076 {
6077
6078 bnx2x_phy_deassert(params, vars->phy_flags);
6079 switch (params->switch_cfg) {
6080 case SWITCH_CFG_1G:
6081 vars->phy_flags |= PHY_SERDES_FLAG;
6082 if ((params->ext_phy_config &
6083 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK) ==
6084 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482) {
6085 vars->phy_flags |=
6086 PHY_SGMII_FLAG;
6087 }
6088
6089 val = REG_RD(bp,
6090 NIG_REG_SERDES0_CTRL_PHY_ADDR+
6091 params->port*0x10);
6092
6093 params->phy_addr = (u8)val;
6094
6095 break;
6096 case SWITCH_CFG_10G:
6097 vars->phy_flags |= PHY_XGXS_FLAG;
6098 val = REG_RD(bp,
6099 NIG_REG_XGXS0_CTRL_PHY_ADDR+
6100 params->port*0x18);
6101 params->phy_addr = (u8)val;
6102
6103 break;
6104 default:
6105 DP(NETIF_MSG_LINK, "Invalid switch_cfg\n");
6106 return -EINVAL;
6107 break;
6108 }
f5372251 6109 DP(NETIF_MSG_LINK, "Phy address = 0x%x\n", params->phy_addr);
ea4e040a
YR		 6110
6111 bnx2x_link_initialize(params, vars);
57963ed9 6112 msleep(30);
ea4e040a
YR		 6113 bnx2x_link_int_enable(params);
6114 }
6115 return 0;
6116}
6117
589abe3a
EG		 6118static void bnx2x_8726_reset_phy(struct bnx2x *bp, u8 port, u8 ext_phy_addr)
6119{
6120 DP(NETIF_MSG_LINK, "bnx2x_8726_reset_phy port %d\n", port);
6121
6122 /* Set serial boot control for external load */
6123 bnx2x_cl45_write(bp, port,
6124 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726, ext_phy_addr,
6125 MDIO_PMA_DEVAD,
6126 MDIO_PMA_REG_GEN_CTRL, 0x0001);
589abe3a
EG		 6127}
6128
6129u8 bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
6130 u8 reset_ext_phy)
ea4e040a
YR		 6131{
6132
6133 struct bnx2x *bp = params->bp;
6134 u32 ext_phy_config = params->ext_phy_config;
6135 u16 hw_led_mode = params->hw_led_mode;
6136 u32 chip_id = params->chip_id;
6137 u8 port = params->port;
6138 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
4d295db0
EG		 6139 u32 val = REG_RD(bp, params->shmem_base +
6140 offsetof(struct shmem_region, dev_info.
6141 port_feature_config[params->port].
6142 config));
6143
ea4e040a
YR		 6144 /* disable attentions */
6145
6146 vars->link_status = 0;
6147 bnx2x_update_mng(params, vars->link_status);
6148 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
6149 (NIG_MASK_XGXS0_LINK_STATUS |
6150 NIG_MASK_XGXS0_LINK10G |
6151 NIG_MASK_SERDES0_LINK_STATUS |
6152 NIG_MASK_MI_INT));
6153
6154 /* activate nig drain */
6155 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
6156
6157 /* disable nig egress interface */
6158 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0);
6159 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0);
6160
6161 /* Stop BigMac rx */
6162 bnx2x_bmac_rx_disable(bp, port);
6163
6164 /* disable emac */
6165 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
6166
6167 msleep(10);
6168 /* The PHY reset is controled by GPIO 1
6169 * Hold it as vars low
6170 */
6171 /* clear link led */
6172 bnx2x_set_led(bp, port, LED_MODE_OFF, 0, hw_led_mode, chip_id);
589abe3a
EG		 6173 if (reset_ext_phy) {
6174 switch (ext_phy_type) {
6175 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
6176 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
6177 break;
4d295db0
EG		 6178
6179 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
6180 {
6181
6182 /* Disable Transmitter */
6183 u8 ext_phy_addr = ((params->ext_phy_config &
6184 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
6185 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
6186 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
6187 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
6188 bnx2x_sfp_set_transmitter(bp, port,
6189 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
6190 ext_phy_addr, 0);
6191 break;
6192 }
589abe3a
EG		 6193 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
6194 DP(NETIF_MSG_LINK, "Setting 8073 port %d into "
6195 "low power mode\n",
6196 port);
6197 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
6198 MISC_REGISTERS_GPIO_OUTPUT_LOW,
6199 port);
6200 break;
6201 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
6202 {
6203 u8 ext_phy_addr = ((params->ext_phy_config &
6204 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
6205 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
6206 /* Set soft reset */
6207 bnx2x_8726_reset_phy(bp, params->port, ext_phy_addr);
6208 break;
6209 }
6210 default:
ea4e040a 6211 /* HW reset */
ea4e040a 6212 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
17de50b7
EG		 6213 MISC_REGISTERS_GPIO_OUTPUT_LOW,
6214 port);
ea4e040a 6215 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
17de50b7
EG		 6216 MISC_REGISTERS_GPIO_OUTPUT_LOW,
6217 port);
ea4e040a 6218 DP(NETIF_MSG_LINK, "reset external PHY\n");
ea4e040a
YR		 6219 }
6220 }
6221 /* reset the SerDes/XGXS */
6222 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR,
6223 (0x1ff << (port*16)));
6224
6225 /* reset BigMac */
6226 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
6227 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
6228
6229 /* disable nig ingress interface */
6230 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0);
6231 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0);
6232 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0);
6233 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0);
6234 vars->link_up = 0;
6235 return 0;
6236}
6237
57963ed9
YR		 6238static u8 bnx2x_update_link_down(struct link_params *params,
6239 struct link_vars *vars)
6240{
6241 struct bnx2x *bp = params->bp;
6242 u8 port = params->port;
6243 DP(NETIF_MSG_LINK, "Port %x: Link is down\n", port);
6244 bnx2x_set_led(bp, port, LED_MODE_OFF,
6245 0, params->hw_led_mode,
6246 params->chip_id);
6247
6248 /* indicate no mac active */
6249 vars->mac_type = MAC_TYPE_NONE;
6250
6251 /* update shared memory */
6252 vars->link_status = 0;
6253 vars->line_speed = 0;
6254 bnx2x_update_mng(params, vars->link_status);
6255
6256 /* activate nig drain */
6257 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
6258
6c55c3cd
EG		 6259 /* disable emac */
6260 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
6261
6262 msleep(10);
6263
57963ed9
YR		 6264 /* reset BigMac */
6265 bnx2x_bmac_rx_disable(bp, params->port);
6266 REG_WR(bp, GRCBASE_MISC +
6267 MISC_REGISTERS_RESET_REG_2_CLEAR,
6268 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
6269 return 0;
6270}
6271
6272static u8 bnx2x_update_link_up(struct link_params *params,
6273 struct link_vars *vars,
6274 u8 link_10g, u32 gp_status)
6275{
6276 struct bnx2x *bp = params->bp;
6277 u8 port = params->port;
6278 u8 rc = 0;
6279 vars->link_status |= LINK_STATUS_LINK_UP;
6280 if (link_10g) {
6281 bnx2x_bmac_enable(params, vars, 0);
6282 bnx2x_set_led(bp, port, LED_MODE_OPER,
6283 SPEED_10000, params->hw_led_mode,
6284 params->chip_id);
6285
6286 } else {
6287 bnx2x_emac_enable(params, vars, 0);
6288 rc = bnx2x_emac_program(params, vars->line_speed,
6289 vars->duplex);
6290
6291 /* AN complete? */
6292 if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE) {
6293 if (!(vars->phy_flags &
6294 PHY_SGMII_FLAG))
ed8680a7 6295 bnx2x_set_gmii_tx_driver(params);
57963ed9
YR		 6296 }
6297 }
6298
6299 /* PBF - link up */
6300 rc |= bnx2x_pbf_update(params, vars->flow_ctrl,
6301 vars->line_speed);
6302
6303 /* disable drain */
6304 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0);
6305
6306 /* update shared memory */
6307 bnx2x_update_mng(params, vars->link_status);
6c55c3cd 6308 msleep(20);
57963ed9
YR		 6309 return rc;
6310}
ea4e040a
YR		 6311/* This function should called upon link interrupt */
6312/* In case vars->link_up, driver needs to
6313 1. Update the pbf
6314 2. Disable drain
6315 3. Update the shared memory
6316 4. Indicate link up
6317 5. Set LEDs
6318 Otherwise,
6319 1. Update shared memory
6320 2. Reset BigMac
6321 3. Report link down
6322 4. Unset LEDs
6323*/
6324u8 bnx2x_link_update(struct link_params *params, struct link_vars *vars)
6325{
6326 struct bnx2x *bp = params->bp;
6327 u8 port = params->port;
ea4e040a 6328 u16 gp_status;
57963ed9
YR		 6329 u8 link_10g;
6330 u8 ext_phy_link_up, rc = 0;
6331 u32 ext_phy_type;
2f904460 6332 u8 is_mi_int = 0;
ea4e040a
YR		 6333
6334 DP(NETIF_MSG_LINK, "port %x, XGXS?%x, int_status 0x%x\n",
2f904460
EG		 6335 port, (vars->phy_flags & PHY_XGXS_FLAG),
6336 REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
ea4e040a 6337
2f904460
EG		 6338 is_mi_int = (u8)(REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT +
6339 port*0x18) > 0);
ea4e040a 6340 DP(NETIF_MSG_LINK, "int_mask 0x%x MI_INT %x, SERDES_LINK %x\n",
2f904460
EG		 6341 REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
6342 is_mi_int,
6343 REG_RD(bp,
6344 NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c));
ea4e040a
YR		 6345
6346 DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
6347 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
6348 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
6349
6c55c3cd
EG		 6350 /* disable emac */
6351 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
6352
57963ed9 6353 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
ea4e040a 6354
57963ed9 6355 /* Check external link change only for non-direct */
2f904460 6356 ext_phy_link_up = bnx2x_ext_phy_is_link_up(params, vars, is_mi_int);
57963ed9
YR		 6357
6358 /* Read gp_status */
6359 CL45_RD_OVER_CL22(bp, port, params->phy_addr,
6360 MDIO_REG_BANK_GP_STATUS,
6361 MDIO_GP_STATUS_TOP_AN_STATUS1,
6362 &gp_status);
ea4e040a 6363
2f904460
EG		 6364 rc = bnx2x_link_settings_status(params, vars, gp_status,
6365 ext_phy_link_up);
ea4e040a
YR		 6366 if (rc != 0)
6367 return rc;
6368
6369 /* anything 10 and over uses the bmac */
6370 link_10g = ((vars->line_speed == SPEED_10000) ||
6371 (vars->line_speed == SPEED_12000) ||
6372 (vars->line_speed == SPEED_12500) ||
6373 (vars->line_speed == SPEED_13000) ||
6374 (vars->line_speed == SPEED_15000) ||
6375 (vars->line_speed == SPEED_16000));
6376
2f904460 6377 bnx2x_link_int_ack(params, vars, link_10g, is_mi_int);
ea4e040a 6378
57963ed9
YR		 6379 /* In case external phy link is up, and internal link is down
6380 ( not initialized yet probably after link initialization, it needs
6381 to be initialized.
6382 Note that after link down-up as result of cable plug,
6383 the xgxs link would probably become up again without the need to
6384 initialize it*/
ea4e040a 6385
57963ed9
YR		 6386 if ((ext_phy_type != PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT) &&
6387 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705) &&
589abe3a 6388 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) &&
57963ed9 6389 (ext_phy_link_up && !vars->phy_link_up))
239d686d 6390 bnx2x_init_internal_phy(params, vars, 0);
ea4e040a 6391
57963ed9
YR		 6392 /* link is up only if both local phy and external phy are up */
6393 vars->link_up = (ext_phy_link_up && vars->phy_link_up);
ea4e040a 6394
57963ed9
YR		 6395 if (vars->link_up)
6396 rc = bnx2x_update_link_up(params, vars, link_10g, gp_status);
6397 else
6398 rc = bnx2x_update_link_down(params, vars);
ea4e040a
YR		 6399
6400 return rc;
6401}
6402
6bbca910
YR		 6403static u8 bnx2x_8073_common_init_phy(struct bnx2x *bp, u32 shmem_base)
6404{
6405 u8 ext_phy_addr[PORT_MAX];
6406 u16 val;
6407 s8 port;
6408
6409 /* PART1 - Reset both phys */
6410 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
6411 /* Extract the ext phy address for the port */
6412 u32 ext_phy_config = REG_RD(bp, shmem_base +
6413 offsetof(struct shmem_region,
6414 dev_info.port_hw_config[port].external_phy_config));
6415
6416 /* disable attentions */
6417 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
6418 (NIG_MASK_XGXS0_LINK_STATUS |
6419 NIG_MASK_XGXS0_LINK10G |
6420 NIG_MASK_SERDES0_LINK_STATUS |
6421 NIG_MASK_MI_INT));
6422
6423 ext_phy_addr[port] =
6424 ((ext_phy_config &
6425 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
6426 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
6427
6428 /* Need to take the phy out of low power mode in order
6429 to write to access its registers */
6430 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
6431 MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
6432
6433 /* Reset the phy */
6434 bnx2x_cl45_write(bp, port,
6435 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
6436 ext_phy_addr[port],
6437 MDIO_PMA_DEVAD,
6438 MDIO_PMA_REG_CTRL,
6439 1<<15);
6440 }
6441
6442 /* Add delay of 150ms after reset */
6443 msleep(150);
6444
6445 /* PART2 - Download firmware to both phys */
6446 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
6447 u16 fw_ver1;
6448
6449 bnx2x_bcm8073_external_rom_boot(bp, port,
a35da8db 6450 ext_phy_addr[port], shmem_base);
6bbca910
YR		 6451
6452 bnx2x_cl45_read(bp, port, PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
6453 ext_phy_addr[port],
6454 MDIO_PMA_DEVAD,
6455 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
16b311cc 6456 if (fw_ver1 == 0 || fw_ver1 == 0x4321) {
6bbca910 6457 DP(NETIF_MSG_LINK,
16b311cc
EG		 6458 "bnx2x_8073_common_init_phy port %x:"
6459 "Download failed. fw version = 0x%x\n",
6460 port, fw_ver1);
6bbca910
YR		 6461 return -EINVAL;
6462 }
6463
6464 /* Only set bit 10 = 1 (Tx power down) */
6465 bnx2x_cl45_read(bp, port,
6466 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
6467 ext_phy_addr[port],
6468 MDIO_PMA_DEVAD,
6469 MDIO_PMA_REG_TX_POWER_DOWN, &val);
6470
6471 /* Phase1 of TX_POWER_DOWN reset */
6472 bnx2x_cl45_write(bp, port,
6473 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
6474 ext_phy_addr[port],
6475 MDIO_PMA_DEVAD,
6476 MDIO_PMA_REG_TX_POWER_DOWN,
6477 (val | 1<<10));
6478 }
6479
6480 /* Toggle Transmitter: Power down and then up with 600ms
6481 delay between */
6482 msleep(600);
6483
6484 /* PART3 - complete TX_POWER_DOWN process, and set GPIO2 back to low */
6485 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
f5372251 6486 /* Phase2 of POWER_DOWN_RESET */
6bbca910
YR		 6487 /* Release bit 10 (Release Tx power down) */
6488 bnx2x_cl45_read(bp, port,
6489 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
6490 ext_phy_addr[port],
6491 MDIO_PMA_DEVAD,
6492 MDIO_PMA_REG_TX_POWER_DOWN, &val);
6493
6494 bnx2x_cl45_write(bp, port,
6495 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
6496 ext_phy_addr[port],
6497 MDIO_PMA_DEVAD,
6498 MDIO_PMA_REG_TX_POWER_DOWN, (val & (~(1<<10))));
6499 msleep(15);
6500
6501 /* Read modify write the SPI-ROM version select register */
6502 bnx2x_cl45_read(bp, port,
6503 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
6504 ext_phy_addr[port],
6505 MDIO_PMA_DEVAD,
6506 MDIO_PMA_REG_EDC_FFE_MAIN, &val);
6507 bnx2x_cl45_write(bp, port,
6508 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
6509 ext_phy_addr[port],
6510 MDIO_PMA_DEVAD,
6511 MDIO_PMA_REG_EDC_FFE_MAIN, (val | (1<<12)));
6512
6513 /* set GPIO2 back to LOW */
6514 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
6515 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
6516 }
6517 return 0;
6518
6519}
6520
4d295db0
EG		 6521static u8 bnx2x_8727_common_init_phy(struct bnx2x *bp, u32 shmem_base)
6522{
6523 u8 ext_phy_addr[PORT_MAX];
bc7f0a05 6524 s8 port, first_port, i;
4d295db0
EG		 6525 u32 swap_val, swap_override;
6526 DP(NETIF_MSG_LINK, "Executing BCM8727 common init\n");
6527 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
6528 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
6529
f57a6025 6530 bnx2x_ext_phy_hw_reset(bp, 1 ^ (swap_val && swap_override));
4d295db0
EG		 6531 msleep(5);
6532
bc7f0a05
EG		 6533 if (swap_val && swap_override)
6534 first_port = PORT_0;
6535 else
6536 first_port = PORT_1;
6537
4d295db0 6538 /* PART1 - Reset both phys */
bc7f0a05 6539 for (i = 0, port = first_port; i < PORT_MAX; i++, port = !port) {
4d295db0
EG		 6540 /* Extract the ext phy address for the port */
6541 u32 ext_phy_config = REG_RD(bp, shmem_base +
6542 offsetof(struct shmem_region,
6543 dev_info.port_hw_config[port].external_phy_config));
6544
6545 /* disable attentions */
6546 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
6547 (NIG_MASK_XGXS0_LINK_STATUS |
6548 NIG_MASK_XGXS0_LINK10G |
6549 NIG_MASK_SERDES0_LINK_STATUS |
6550 NIG_MASK_MI_INT));
6551
6552 ext_phy_addr[port] = ((ext_phy_config &
6553 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
6554 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
6555
6556 /* Reset the phy */
6557 bnx2x_cl45_write(bp, port,
6558 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
6559 ext_phy_addr[port],
6560 MDIO_PMA_DEVAD,
6561 MDIO_PMA_REG_CTRL,
6562 1<<15);
6563 }
6564
6565 /* Add delay of 150ms after reset */
6566 msleep(150);
6567
6568 /* PART2 - Download firmware to both phys */
bc7f0a05 6569 for (i = 0, port = first_port; i < PORT_MAX; i++, port = !port) {
4d295db0
EG		 6570 u16 fw_ver1;
6571
6572 bnx2x_bcm8727_external_rom_boot(bp, port,
6573 ext_phy_addr[port], shmem_base);
6574
6575 bnx2x_cl45_read(bp, port, PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
6576 ext_phy_addr[port],
6577 MDIO_PMA_DEVAD,
6578 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
6579 if (fw_ver1 == 0 || fw_ver1 == 0x4321) {
6580 DP(NETIF_MSG_LINK,
bc7f0a05 6581 "bnx2x_8727_common_init_phy port %x:"
4d295db0
EG		 6582 "Download failed. fw version = 0x%x\n",
6583 port, fw_ver1);
6584 return -EINVAL;
6585 }
4d295db0
EG		 6586 }
6587
4d295db0
EG		 6588 return 0;
6589}
6590
589abe3a
EG		 6591
6592static u8 bnx2x_8726_common_init_phy(struct bnx2x *bp, u32 shmem_base)
6593{
6594 u8 ext_phy_addr;
6595 u32 val;
6596 s8 port;
6597 /* Use port1 because of the static port-swap */
6598 /* Enable the module detection interrupt */
6599 val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN);
6600 val |= ((1<<MISC_REGISTERS_GPIO_3)|
6601 (1<<(MISC_REGISTERS_GPIO_3 + MISC_REGISTERS_GPIO_PORT_SHIFT)));
6602 REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val);
6603
f57a6025 6604 bnx2x_ext_phy_hw_reset(bp, 1);
589abe3a
EG		 6605 msleep(5);
6606 for (port = 0; port < PORT_MAX; port++) {
6607 /* Extract the ext phy address for the port */
6608 u32 ext_phy_config = REG_RD(bp, shmem_base +
6609 offsetof(struct shmem_region,
6610 dev_info.port_hw_config[port].external_phy_config));
6611
6612 ext_phy_addr =
6613 ((ext_phy_config &
6614 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
6615 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
6616 DP(NETIF_MSG_LINK, "8726_common_init : ext_phy_addr = 0x%x\n",
6617 ext_phy_addr);
6618
6619 bnx2x_8726_reset_phy(bp, port, ext_phy_addr);
6620
6621 /* Set fault module detected LED on */
6622 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
6623 MISC_REGISTERS_GPIO_HIGH,
6624 port);
6625 }
6626
6627 return 0;
6628}
6629
6bbca910
YR		 6630u8 bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base)
6631{
6632 u8 rc = 0;
6633 u32 ext_phy_type;
6634
f5372251 6635 DP(NETIF_MSG_LINK, "Begin common phy init\n");
6bbca910
YR		 6636
6637 /* Read the ext_phy_type for arbitrary port(0) */
6638 ext_phy_type = XGXS_EXT_PHY_TYPE(
6639 REG_RD(bp, shmem_base +
6640 offsetof(struct shmem_region,
6641 dev_info.port_hw_config[0].external_phy_config)));
6642
6643 switch (ext_phy_type) {
6644 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
6645 {
6646 rc = bnx2x_8073_common_init_phy(bp, shmem_base);
6647 break;
6648 }
4d295db0
EG		 6649
6650 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
6651 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
6652 rc = bnx2x_8727_common_init_phy(bp, shmem_base);
6653 break;
6654
589abe3a
EG		 6655 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
6656 /* GPIO1 affects both ports, so there's need to pull
6657 it for single port alone */
6658 rc = bnx2x_8726_common_init_phy(bp, shmem_base);
6659
6660 break;
6bbca910
YR		 6661 default:
6662 DP(NETIF_MSG_LINK,
6663 "bnx2x_common_init_phy: ext_phy 0x%x not required\n",
6664 ext_phy_type);
6665 break;
6666 }
6667
6668 return rc;
6669}
6670
f57a6025 6671void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, u8 port, u8 phy_addr)
ea4e040a
YR		 6672{
6673 u16 val, cnt;
6674
6675 bnx2x_cl45_read(bp, port,
6676 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
6677 phy_addr,
6678 MDIO_PMA_DEVAD,
6679 MDIO_PMA_REG_7101_RESET, &val);
6680
6681 for (cnt = 0; cnt < 10; cnt++) {
6682 msleep(50);
6683 /* Writes a self-clearing reset */
6684 bnx2x_cl45_write(bp, port,
6685 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
6686 phy_addr,
6687 MDIO_PMA_DEVAD,
6688 MDIO_PMA_REG_7101_RESET,
6689 (val | (1<<15)));
6690 /* Wait for clear */
6691 bnx2x_cl45_read(bp, port,
6692 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
6693 phy_addr,
6694 MDIO_PMA_DEVAD,
6695 MDIO_PMA_REG_7101_RESET, &val);
6696
6697 if ((val & (1<<15)) == 0)
6698 break;
6699 }
6700}
Linux kernel - Deliverables
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