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99c4a634 DM |
1 | /* |
2 | * at91_can.c - CAN network driver for AT91 SoC CAN controller | |
3 | * | |
3e9ebd3c | 4 | * (C) 2007 by Hans J. Koch <hjk@hansjkoch.de> |
0909c1ec | 5 | * (C) 2008, 2009, 2010, 2011 by Marc Kleine-Budde <kernel@pengutronix.de> |
99c4a634 DM |
6 | * |
7 | * This software may be distributed under the terms of the GNU General | |
8 | * Public License ("GPL") version 2 as distributed in the 'COPYING' | |
9 | * file from the main directory of the linux kernel source. | |
10 | * | |
11 | * Send feedback to <socketcan-users@lists.berlios.de> | |
12 | * | |
13 | * | |
14 | * Your platform definition file should specify something like: | |
15 | * | |
16 | * static struct at91_can_data ek_can_data = { | |
17 | * transceiver_switch = sam9263ek_transceiver_switch, | |
18 | * }; | |
19 | * | |
20 | * at91_add_device_can(&ek_can_data); | |
21 | * | |
22 | */ | |
23 | ||
24 | #include <linux/clk.h> | |
25 | #include <linux/errno.h> | |
26 | #include <linux/if_arp.h> | |
27 | #include <linux/init.h> | |
28 | #include <linux/interrupt.h> | |
29 | #include <linux/kernel.h> | |
30 | #include <linux/module.h> | |
31 | #include <linux/netdevice.h> | |
32 | #include <linux/platform_device.h> | |
3a5655a5 | 33 | #include <linux/rtnetlink.h> |
99c4a634 DM |
34 | #include <linux/skbuff.h> |
35 | #include <linux/spinlock.h> | |
36 | #include <linux/string.h> | |
37 | #include <linux/types.h> | |
38 | ||
99c4a634 DM |
39 | #include <linux/can/dev.h> |
40 | #include <linux/can/error.h> | |
41 | ||
42 | #include <mach/board.h> | |
43 | ||
9e0a2d1c | 44 | #define AT91_NAPI_WEIGHT 11 |
99c4a634 DM |
45 | |
46 | /* | |
47 | * RX/TX Mailbox split | |
48 | * don't dare to touch | |
49 | */ | |
9e0a2d1c | 50 | #define AT91_MB_RX_NUM 11 |
99c4a634 DM |
51 | #define AT91_MB_TX_SHIFT 2 |
52 | ||
9e0a2d1c | 53 | #define AT91_MB_RX_FIRST 1 |
99c4a634 DM |
54 | #define AT91_MB_RX_LAST (AT91_MB_RX_FIRST + AT91_MB_RX_NUM - 1) |
55 | ||
56 | #define AT91_MB_RX_MASK(i) ((1 << (i)) - 1) | |
57 | #define AT91_MB_RX_SPLIT 8 | |
58 | #define AT91_MB_RX_LOW_LAST (AT91_MB_RX_SPLIT - 1) | |
0909c1ec MKB |
59 | #define AT91_MB_RX_LOW_MASK (AT91_MB_RX_MASK(AT91_MB_RX_SPLIT) & \ |
60 | ~AT91_MB_RX_MASK(AT91_MB_RX_FIRST)) | |
99c4a634 DM |
61 | |
62 | #define AT91_MB_TX_NUM (1 << AT91_MB_TX_SHIFT) | |
63 | #define AT91_MB_TX_FIRST (AT91_MB_RX_LAST + 1) | |
64 | #define AT91_MB_TX_LAST (AT91_MB_TX_FIRST + AT91_MB_TX_NUM - 1) | |
65 | ||
66 | #define AT91_NEXT_PRIO_SHIFT (AT91_MB_TX_SHIFT) | |
67 | #define AT91_NEXT_PRIO_MASK (0xf << AT91_MB_TX_SHIFT) | |
68 | #define AT91_NEXT_MB_MASK (AT91_MB_TX_NUM - 1) | |
69 | #define AT91_NEXT_MASK ((AT91_MB_TX_NUM - 1) | AT91_NEXT_PRIO_MASK) | |
70 | ||
71 | /* Common registers */ | |
72 | enum at91_reg { | |
73 | AT91_MR = 0x000, | |
74 | AT91_IER = 0x004, | |
75 | AT91_IDR = 0x008, | |
76 | AT91_IMR = 0x00C, | |
77 | AT91_SR = 0x010, | |
78 | AT91_BR = 0x014, | |
79 | AT91_TIM = 0x018, | |
80 | AT91_TIMESTP = 0x01C, | |
81 | AT91_ECR = 0x020, | |
82 | AT91_TCR = 0x024, | |
83 | AT91_ACR = 0x028, | |
84 | }; | |
85 | ||
86 | /* Mailbox registers (0 <= i <= 15) */ | |
87 | #define AT91_MMR(i) (enum at91_reg)(0x200 + ((i) * 0x20)) | |
88 | #define AT91_MAM(i) (enum at91_reg)(0x204 + ((i) * 0x20)) | |
89 | #define AT91_MID(i) (enum at91_reg)(0x208 + ((i) * 0x20)) | |
90 | #define AT91_MFID(i) (enum at91_reg)(0x20C + ((i) * 0x20)) | |
91 | #define AT91_MSR(i) (enum at91_reg)(0x210 + ((i) * 0x20)) | |
92 | #define AT91_MDL(i) (enum at91_reg)(0x214 + ((i) * 0x20)) | |
93 | #define AT91_MDH(i) (enum at91_reg)(0x218 + ((i) * 0x20)) | |
94 | #define AT91_MCR(i) (enum at91_reg)(0x21C + ((i) * 0x20)) | |
95 | ||
96 | /* Register bits */ | |
97 | #define AT91_MR_CANEN BIT(0) | |
98 | #define AT91_MR_LPM BIT(1) | |
99 | #define AT91_MR_ABM BIT(2) | |
100 | #define AT91_MR_OVL BIT(3) | |
101 | #define AT91_MR_TEOF BIT(4) | |
102 | #define AT91_MR_TTM BIT(5) | |
103 | #define AT91_MR_TIMFRZ BIT(6) | |
104 | #define AT91_MR_DRPT BIT(7) | |
105 | ||
106 | #define AT91_SR_RBSY BIT(29) | |
107 | ||
108 | #define AT91_MMR_PRIO_SHIFT (16) | |
109 | ||
110 | #define AT91_MID_MIDE BIT(29) | |
111 | ||
112 | #define AT91_MSR_MRTR BIT(20) | |
113 | #define AT91_MSR_MABT BIT(22) | |
114 | #define AT91_MSR_MRDY BIT(23) | |
115 | #define AT91_MSR_MMI BIT(24) | |
116 | ||
117 | #define AT91_MCR_MRTR BIT(20) | |
118 | #define AT91_MCR_MTCR BIT(23) | |
119 | ||
120 | /* Mailbox Modes */ | |
121 | enum at91_mb_mode { | |
122 | AT91_MB_MODE_DISABLED = 0, | |
123 | AT91_MB_MODE_RX = 1, | |
124 | AT91_MB_MODE_RX_OVRWR = 2, | |
125 | AT91_MB_MODE_TX = 3, | |
126 | AT91_MB_MODE_CONSUMER = 4, | |
127 | AT91_MB_MODE_PRODUCER = 5, | |
128 | }; | |
129 | ||
130 | /* Interrupt mask bits */ | |
131 | #define AT91_IRQ_MB_RX ((1 << (AT91_MB_RX_LAST + 1)) \ | |
132 | - (1 << AT91_MB_RX_FIRST)) | |
133 | #define AT91_IRQ_MB_TX ((1 << (AT91_MB_TX_LAST + 1)) \ | |
134 | - (1 << AT91_MB_TX_FIRST)) | |
135 | #define AT91_IRQ_MB_ALL (AT91_IRQ_MB_RX | AT91_IRQ_MB_TX) | |
136 | ||
137 | #define AT91_IRQ_ERRA (1 << 16) | |
138 | #define AT91_IRQ_WARN (1 << 17) | |
139 | #define AT91_IRQ_ERRP (1 << 18) | |
140 | #define AT91_IRQ_BOFF (1 << 19) | |
141 | #define AT91_IRQ_SLEEP (1 << 20) | |
142 | #define AT91_IRQ_WAKEUP (1 << 21) | |
143 | #define AT91_IRQ_TOVF (1 << 22) | |
144 | #define AT91_IRQ_TSTP (1 << 23) | |
145 | #define AT91_IRQ_CERR (1 << 24) | |
146 | #define AT91_IRQ_SERR (1 << 25) | |
147 | #define AT91_IRQ_AERR (1 << 26) | |
148 | #define AT91_IRQ_FERR (1 << 27) | |
149 | #define AT91_IRQ_BERR (1 << 28) | |
150 | ||
151 | #define AT91_IRQ_ERR_ALL (0x1fff0000) | |
152 | #define AT91_IRQ_ERR_FRAME (AT91_IRQ_CERR | AT91_IRQ_SERR | \ | |
153 | AT91_IRQ_AERR | AT91_IRQ_FERR | AT91_IRQ_BERR) | |
154 | #define AT91_IRQ_ERR_LINE (AT91_IRQ_ERRA | AT91_IRQ_WARN | \ | |
155 | AT91_IRQ_ERRP | AT91_IRQ_BOFF) | |
156 | ||
157 | #define AT91_IRQ_ALL (0x1fffffff) | |
158 | ||
159 | struct at91_priv { | |
160 | struct can_priv can; /* must be the first member! */ | |
161 | struct net_device *dev; | |
162 | struct napi_struct napi; | |
163 | ||
164 | void __iomem *reg_base; | |
165 | ||
166 | u32 reg_sr; | |
167 | unsigned int tx_next; | |
168 | unsigned int tx_echo; | |
169 | unsigned int rx_next; | |
170 | ||
171 | struct clk *clk; | |
172 | struct at91_can_data *pdata; | |
3a5655a5 MKB |
173 | |
174 | canid_t mb0_id; | |
99c4a634 DM |
175 | }; |
176 | ||
177 | static struct can_bittiming_const at91_bittiming_const = { | |
00389b08 | 178 | .name = KBUILD_MODNAME, |
99c4a634 DM |
179 | .tseg1_min = 4, |
180 | .tseg1_max = 16, | |
181 | .tseg2_min = 2, | |
182 | .tseg2_max = 8, | |
183 | .sjw_max = 4, | |
184 | .brp_min = 2, | |
185 | .brp_max = 128, | |
186 | .brp_inc = 1, | |
187 | }; | |
188 | ||
189 | static inline int get_tx_next_mb(const struct at91_priv *priv) | |
190 | { | |
191 | return (priv->tx_next & AT91_NEXT_MB_MASK) + AT91_MB_TX_FIRST; | |
192 | } | |
193 | ||
194 | static inline int get_tx_next_prio(const struct at91_priv *priv) | |
195 | { | |
196 | return (priv->tx_next >> AT91_NEXT_PRIO_SHIFT) & 0xf; | |
197 | } | |
198 | ||
199 | static inline int get_tx_echo_mb(const struct at91_priv *priv) | |
200 | { | |
201 | return (priv->tx_echo & AT91_NEXT_MB_MASK) + AT91_MB_TX_FIRST; | |
202 | } | |
203 | ||
204 | static inline u32 at91_read(const struct at91_priv *priv, enum at91_reg reg) | |
205 | { | |
7672fe73 | 206 | return __raw_readl(priv->reg_base + reg); |
99c4a634 DM |
207 | } |
208 | ||
209 | static inline void at91_write(const struct at91_priv *priv, enum at91_reg reg, | |
210 | u32 value) | |
211 | { | |
7672fe73 | 212 | __raw_writel(value, priv->reg_base + reg); |
99c4a634 DM |
213 | } |
214 | ||
215 | static inline void set_mb_mode_prio(const struct at91_priv *priv, | |
216 | unsigned int mb, enum at91_mb_mode mode, int prio) | |
217 | { | |
218 | at91_write(priv, AT91_MMR(mb), (mode << 24) | (prio << 16)); | |
219 | } | |
220 | ||
221 | static inline void set_mb_mode(const struct at91_priv *priv, unsigned int mb, | |
222 | enum at91_mb_mode mode) | |
223 | { | |
224 | set_mb_mode_prio(priv, mb, mode, 0); | |
225 | } | |
226 | ||
3a5655a5 MKB |
227 | static inline u32 at91_can_id_to_reg_mid(canid_t can_id) |
228 | { | |
229 | u32 reg_mid; | |
230 | ||
231 | if (can_id & CAN_EFF_FLAG) | |
232 | reg_mid = (can_id & CAN_EFF_MASK) | AT91_MID_MIDE; | |
233 | else | |
234 | reg_mid = (can_id & CAN_SFF_MASK) << 18; | |
235 | ||
236 | return reg_mid; | |
237 | } | |
238 | ||
99c4a634 DM |
239 | /* |
240 | * Swtich transceiver on or off | |
241 | */ | |
242 | static void at91_transceiver_switch(const struct at91_priv *priv, int on) | |
243 | { | |
244 | if (priv->pdata && priv->pdata->transceiver_switch) | |
245 | priv->pdata->transceiver_switch(on); | |
246 | } | |
247 | ||
248 | static void at91_setup_mailboxes(struct net_device *dev) | |
249 | { | |
250 | struct at91_priv *priv = netdev_priv(dev); | |
251 | unsigned int i; | |
3a5655a5 | 252 | u32 reg_mid; |
99c4a634 DM |
253 | |
254 | /* | |
9e0a2d1c MKB |
255 | * Due to a chip bug (errata 50.2.6.3 & 50.3.5.3) the first |
256 | * mailbox is disabled. The next 11 mailboxes are used as a | |
257 | * reception FIFO. The last mailbox is configured with | |
258 | * overwrite option. The overwrite flag indicates a FIFO | |
259 | * overflow. | |
99c4a634 | 260 | */ |
3a5655a5 MKB |
261 | reg_mid = at91_can_id_to_reg_mid(priv->mb0_id); |
262 | for (i = 0; i < AT91_MB_RX_FIRST; i++) { | |
9e0a2d1c | 263 | set_mb_mode(priv, i, AT91_MB_MODE_DISABLED); |
3a5655a5 MKB |
264 | at91_write(priv, AT91_MID(i), reg_mid); |
265 | at91_write(priv, AT91_MCR(i), 0x0); /* clear dlc */ | |
266 | } | |
267 | ||
99c4a634 DM |
268 | for (i = AT91_MB_RX_FIRST; i < AT91_MB_RX_LAST; i++) |
269 | set_mb_mode(priv, i, AT91_MB_MODE_RX); | |
270 | set_mb_mode(priv, AT91_MB_RX_LAST, AT91_MB_MODE_RX_OVRWR); | |
271 | ||
8a0e0a49 MKB |
272 | /* reset acceptance mask and id register */ |
273 | for (i = AT91_MB_RX_FIRST; i <= AT91_MB_RX_LAST; i++) { | |
274 | at91_write(priv, AT91_MAM(i), 0x0 ); | |
275 | at91_write(priv, AT91_MID(i), AT91_MID_MIDE); | |
276 | } | |
277 | ||
99c4a634 DM |
278 | /* The last 4 mailboxes are used for transmitting. */ |
279 | for (i = AT91_MB_TX_FIRST; i <= AT91_MB_TX_LAST; i++) | |
280 | set_mb_mode_prio(priv, i, AT91_MB_MODE_TX, 0); | |
281 | ||
282 | /* Reset tx and rx helper pointers */ | |
0909c1ec MKB |
283 | priv->tx_next = priv->tx_echo = 0; |
284 | priv->rx_next = AT91_MB_RX_FIRST; | |
99c4a634 DM |
285 | } |
286 | ||
287 | static int at91_set_bittiming(struct net_device *dev) | |
288 | { | |
289 | const struct at91_priv *priv = netdev_priv(dev); | |
290 | const struct can_bittiming *bt = &priv->can.bittiming; | |
291 | u32 reg_br; | |
292 | ||
dbe91325 MKB |
293 | reg_br = ((priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) ? 1 << 24 : 0) | |
294 | ((bt->brp - 1) << 16) | ((bt->sjw - 1) << 12) | | |
99c4a634 DM |
295 | ((bt->prop_seg - 1) << 8) | ((bt->phase_seg1 - 1) << 4) | |
296 | ((bt->phase_seg2 - 1) << 0); | |
297 | ||
882055c8 | 298 | netdev_info(dev, "writing AT91_BR: 0x%08x\n", reg_br); |
99c4a634 DM |
299 | |
300 | at91_write(priv, AT91_BR, reg_br); | |
301 | ||
302 | return 0; | |
303 | } | |
304 | ||
33a6f298 MKB |
305 | static int at91_get_berr_counter(const struct net_device *dev, |
306 | struct can_berr_counter *bec) | |
307 | { | |
308 | const struct at91_priv *priv = netdev_priv(dev); | |
309 | u32 reg_ecr = at91_read(priv, AT91_ECR); | |
310 | ||
311 | bec->rxerr = reg_ecr & 0xff; | |
312 | bec->txerr = reg_ecr >> 16; | |
313 | ||
314 | return 0; | |
315 | } | |
316 | ||
99c4a634 DM |
317 | static void at91_chip_start(struct net_device *dev) |
318 | { | |
319 | struct at91_priv *priv = netdev_priv(dev); | |
320 | u32 reg_mr, reg_ier; | |
321 | ||
322 | /* disable interrupts */ | |
323 | at91_write(priv, AT91_IDR, AT91_IRQ_ALL); | |
324 | ||
325 | /* disable chip */ | |
326 | reg_mr = at91_read(priv, AT91_MR); | |
327 | at91_write(priv, AT91_MR, reg_mr & ~AT91_MR_CANEN); | |
328 | ||
b156fd04 | 329 | at91_set_bittiming(dev); |
99c4a634 DM |
330 | at91_setup_mailboxes(dev); |
331 | at91_transceiver_switch(priv, 1); | |
332 | ||
333 | /* enable chip */ | |
334 | at91_write(priv, AT91_MR, AT91_MR_CANEN); | |
335 | ||
336 | priv->can.state = CAN_STATE_ERROR_ACTIVE; | |
337 | ||
338 | /* Enable interrupts */ | |
339 | reg_ier = AT91_IRQ_MB_RX | AT91_IRQ_ERRP | AT91_IRQ_ERR_FRAME; | |
340 | at91_write(priv, AT91_IDR, AT91_IRQ_ALL); | |
341 | at91_write(priv, AT91_IER, reg_ier); | |
342 | } | |
343 | ||
344 | static void at91_chip_stop(struct net_device *dev, enum can_state state) | |
345 | { | |
346 | struct at91_priv *priv = netdev_priv(dev); | |
347 | u32 reg_mr; | |
348 | ||
349 | /* disable interrupts */ | |
350 | at91_write(priv, AT91_IDR, AT91_IRQ_ALL); | |
351 | ||
352 | reg_mr = at91_read(priv, AT91_MR); | |
353 | at91_write(priv, AT91_MR, reg_mr & ~AT91_MR_CANEN); | |
354 | ||
355 | at91_transceiver_switch(priv, 0); | |
356 | priv->can.state = state; | |
357 | } | |
358 | ||
359 | /* | |
360 | * theory of operation: | |
361 | * | |
362 | * According to the datasheet priority 0 is the highest priority, 15 | |
363 | * is the lowest. If two mailboxes have the same priority level the | |
364 | * message of the mailbox with the lowest number is sent first. | |
365 | * | |
366 | * We use the first TX mailbox (AT91_MB_TX_FIRST) with prio 0, then | |
367 | * the next mailbox with prio 0, and so on, until all mailboxes are | |
368 | * used. Then we start from the beginning with mailbox | |
369 | * AT91_MB_TX_FIRST, but with prio 1, mailbox AT91_MB_TX_FIRST + 1 | |
370 | * prio 1. When we reach the last mailbox with prio 15, we have to | |
371 | * stop sending, waiting for all messages to be delivered, then start | |
372 | * again with mailbox AT91_MB_TX_FIRST prio 0. | |
373 | * | |
374 | * We use the priv->tx_next as counter for the next transmission | |
375 | * mailbox, but without the offset AT91_MB_TX_FIRST. The lower bits | |
376 | * encode the mailbox number, the upper 4 bits the mailbox priority: | |
377 | * | |
378 | * priv->tx_next = (prio << AT91_NEXT_PRIO_SHIFT) || | |
379 | * (mb - AT91_MB_TX_FIRST); | |
380 | * | |
381 | */ | |
382 | static netdev_tx_t at91_start_xmit(struct sk_buff *skb, struct net_device *dev) | |
383 | { | |
384 | struct at91_priv *priv = netdev_priv(dev); | |
385 | struct net_device_stats *stats = &dev->stats; | |
386 | struct can_frame *cf = (struct can_frame *)skb->data; | |
387 | unsigned int mb, prio; | |
388 | u32 reg_mid, reg_mcr; | |
389 | ||
3ccd4c61 OH |
390 | if (can_dropped_invalid_skb(dev, skb)) |
391 | return NETDEV_TX_OK; | |
392 | ||
99c4a634 DM |
393 | mb = get_tx_next_mb(priv); |
394 | prio = get_tx_next_prio(priv); | |
395 | ||
396 | if (unlikely(!(at91_read(priv, AT91_MSR(mb)) & AT91_MSR_MRDY))) { | |
397 | netif_stop_queue(dev); | |
398 | ||
882055c8 | 399 | netdev_err(dev, "BUG! TX buffer full when queue awake!\n"); |
99c4a634 DM |
400 | return NETDEV_TX_BUSY; |
401 | } | |
3a5655a5 | 402 | reg_mid = at91_can_id_to_reg_mid(cf->can_id); |
99c4a634 DM |
403 | reg_mcr = ((cf->can_id & CAN_RTR_FLAG) ? AT91_MCR_MRTR : 0) | |
404 | (cf->can_dlc << 16) | AT91_MCR_MTCR; | |
405 | ||
406 | /* disable MB while writing ID (see datasheet) */ | |
407 | set_mb_mode(priv, mb, AT91_MB_MODE_DISABLED); | |
408 | at91_write(priv, AT91_MID(mb), reg_mid); | |
409 | set_mb_mode_prio(priv, mb, AT91_MB_MODE_TX, prio); | |
410 | ||
411 | at91_write(priv, AT91_MDL(mb), *(u32 *)(cf->data + 0)); | |
412 | at91_write(priv, AT91_MDH(mb), *(u32 *)(cf->data + 4)); | |
413 | ||
414 | /* This triggers transmission */ | |
415 | at91_write(priv, AT91_MCR(mb), reg_mcr); | |
416 | ||
417 | stats->tx_bytes += cf->can_dlc; | |
99c4a634 | 418 | |
25985edc | 419 | /* _NOTE_: subtract AT91_MB_TX_FIRST offset from mb! */ |
99c4a634 DM |
420 | can_put_echo_skb(skb, dev, mb - AT91_MB_TX_FIRST); |
421 | ||
422 | /* | |
423 | * we have to stop the queue and deliver all messages in case | |
424 | * of a prio+mb counter wrap around. This is the case if | |
425 | * tx_next buffer prio and mailbox equals 0. | |
426 | * | |
427 | * also stop the queue if next buffer is still in use | |
428 | * (== not ready) | |
429 | */ | |
430 | priv->tx_next++; | |
431 | if (!(at91_read(priv, AT91_MSR(get_tx_next_mb(priv))) & | |
432 | AT91_MSR_MRDY) || | |
433 | (priv->tx_next & AT91_NEXT_MASK) == 0) | |
434 | netif_stop_queue(dev); | |
435 | ||
436 | /* Enable interrupt for this mailbox */ | |
437 | at91_write(priv, AT91_IER, 1 << mb); | |
438 | ||
439 | return NETDEV_TX_OK; | |
440 | } | |
441 | ||
442 | /** | |
443 | * at91_activate_rx_low - activate lower rx mailboxes | |
444 | * @priv: a91 context | |
445 | * | |
446 | * Reenables the lower mailboxes for reception of new CAN messages | |
447 | */ | |
448 | static inline void at91_activate_rx_low(const struct at91_priv *priv) | |
449 | { | |
450 | u32 mask = AT91_MB_RX_LOW_MASK; | |
451 | at91_write(priv, AT91_TCR, mask); | |
452 | } | |
453 | ||
454 | /** | |
455 | * at91_activate_rx_mb - reactive single rx mailbox | |
456 | * @priv: a91 context | |
457 | * @mb: mailbox to reactivate | |
458 | * | |
459 | * Reenables given mailbox for reception of new CAN messages | |
460 | */ | |
461 | static inline void at91_activate_rx_mb(const struct at91_priv *priv, | |
462 | unsigned int mb) | |
463 | { | |
464 | u32 mask = 1 << mb; | |
465 | at91_write(priv, AT91_TCR, mask); | |
466 | } | |
467 | ||
468 | /** | |
469 | * at91_rx_overflow_err - send error frame due to rx overflow | |
470 | * @dev: net device | |
471 | */ | |
472 | static void at91_rx_overflow_err(struct net_device *dev) | |
473 | { | |
474 | struct net_device_stats *stats = &dev->stats; | |
475 | struct sk_buff *skb; | |
476 | struct can_frame *cf; | |
477 | ||
882055c8 | 478 | netdev_dbg(dev, "RX buffer overflow\n"); |
99c4a634 DM |
479 | stats->rx_over_errors++; |
480 | stats->rx_errors++; | |
481 | ||
482 | skb = alloc_can_err_skb(dev, &cf); | |
483 | if (unlikely(!skb)) | |
484 | return; | |
485 | ||
486 | cf->can_id |= CAN_ERR_CRTL; | |
487 | cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW; | |
488 | netif_receive_skb(skb); | |
489 | ||
490 | stats->rx_packets++; | |
491 | stats->rx_bytes += cf->can_dlc; | |
492 | } | |
493 | ||
494 | /** | |
495 | * at91_read_mb - read CAN msg from mailbox (lowlevel impl) | |
496 | * @dev: net device | |
497 | * @mb: mailbox number to read from | |
498 | * @cf: can frame where to store message | |
499 | * | |
500 | * Reads a CAN message from the given mailbox and stores data into | |
501 | * given can frame. "mb" and "cf" must be valid. | |
502 | */ | |
503 | static void at91_read_mb(struct net_device *dev, unsigned int mb, | |
504 | struct can_frame *cf) | |
505 | { | |
506 | const struct at91_priv *priv = netdev_priv(dev); | |
507 | u32 reg_msr, reg_mid; | |
508 | ||
509 | reg_mid = at91_read(priv, AT91_MID(mb)); | |
510 | if (reg_mid & AT91_MID_MIDE) | |
511 | cf->can_id = ((reg_mid >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG; | |
512 | else | |
513 | cf->can_id = (reg_mid >> 18) & CAN_SFF_MASK; | |
514 | ||
515 | reg_msr = at91_read(priv, AT91_MSR(mb)); | |
516 | if (reg_msr & AT91_MSR_MRTR) | |
517 | cf->can_id |= CAN_RTR_FLAG; | |
c7cd606f | 518 | cf->can_dlc = get_can_dlc((reg_msr >> 16) & 0xf); |
99c4a634 DM |
519 | |
520 | *(u32 *)(cf->data + 0) = at91_read(priv, AT91_MDL(mb)); | |
521 | *(u32 *)(cf->data + 4) = at91_read(priv, AT91_MDH(mb)); | |
522 | ||
8a0e0a49 MKB |
523 | /* allow RX of extended frames */ |
524 | at91_write(priv, AT91_MID(mb), AT91_MID_MIDE); | |
525 | ||
99c4a634 DM |
526 | if (unlikely(mb == AT91_MB_RX_LAST && reg_msr & AT91_MSR_MMI)) |
527 | at91_rx_overflow_err(dev); | |
528 | } | |
529 | ||
530 | /** | |
531 | * at91_read_msg - read CAN message from mailbox | |
532 | * @dev: net device | |
533 | * @mb: mail box to read from | |
534 | * | |
535 | * Reads a CAN message from given mailbox, and put into linux network | |
536 | * RX queue, does all housekeeping chores (stats, ...) | |
537 | */ | |
538 | static void at91_read_msg(struct net_device *dev, unsigned int mb) | |
539 | { | |
540 | struct net_device_stats *stats = &dev->stats; | |
541 | struct can_frame *cf; | |
542 | struct sk_buff *skb; | |
543 | ||
544 | skb = alloc_can_skb(dev, &cf); | |
545 | if (unlikely(!skb)) { | |
546 | stats->rx_dropped++; | |
547 | return; | |
548 | } | |
549 | ||
550 | at91_read_mb(dev, mb, cf); | |
551 | netif_receive_skb(skb); | |
552 | ||
553 | stats->rx_packets++; | |
554 | stats->rx_bytes += cf->can_dlc; | |
555 | } | |
556 | ||
557 | /** | |
558 | * at91_poll_rx - read multiple CAN messages from mailboxes | |
559 | * @dev: net device | |
560 | * @quota: max number of pkgs we're allowed to receive | |
561 | * | |
562 | * Theory of Operation: | |
563 | * | |
9e0a2d1c MKB |
564 | * 11 of the 16 mailboxes on the chip are reserved for RX. we split |
565 | * them into 2 groups. The lower group holds 7 and upper 4 mailboxes. | |
99c4a634 DM |
566 | * |
567 | * Like it or not, but the chip always saves a received CAN message | |
568 | * into the first free mailbox it finds (starting with the | |
569 | * lowest). This makes it very difficult to read the messages in the | |
570 | * right order from the chip. This is how we work around that problem: | |
571 | * | |
9e0a2d1c | 572 | * The first message goes into mb nr. 1 and issues an interrupt. All |
99c4a634 DM |
573 | * rx ints are disabled in the interrupt handler and a napi poll is |
574 | * scheduled. We read the mailbox, but do _not_ reenable the mb (to | |
575 | * receive another message). | |
576 | * | |
577 | * lower mbxs upper | |
9e0a2d1c MKB |
578 | * ____^______ __^__ |
579 | * / \ / \ | |
99c4a634 | 580 | * +-+-+-+-+-+-+-+-++-+-+-+-+ |
9e0a2d1c | 581 | * | |x|x|x|x|x|x|x|| | | | | |
99c4a634 DM |
582 | * +-+-+-+-+-+-+-+-++-+-+-+-+ |
583 | * 0 0 0 0 0 0 0 0 0 0 1 1 \ mail | |
584 | * 0 1 2 3 4 5 6 7 8 9 0 1 / box | |
9e0a2d1c MKB |
585 | * ^ |
586 | * | | |
587 | * \ | |
588 | * unused, due to chip bug | |
99c4a634 DM |
589 | * |
590 | * The variable priv->rx_next points to the next mailbox to read a | |
591 | * message from. As long we're in the lower mailboxes we just read the | |
592 | * mailbox but not reenable it. | |
593 | * | |
594 | * With completion of the last of the lower mailboxes, we reenable the | |
595 | * whole first group, but continue to look for filled mailboxes in the | |
596 | * upper mailboxes. Imagine the second group like overflow mailboxes, | |
597 | * which takes CAN messages if the lower goup is full. While in the | |
598 | * upper group we reenable the mailbox right after reading it. Giving | |
599 | * the chip more room to store messages. | |
600 | * | |
601 | * After finishing we look again in the lower group if we've still | |
602 | * quota. | |
603 | * | |
604 | */ | |
605 | static int at91_poll_rx(struct net_device *dev, int quota) | |
606 | { | |
607 | struct at91_priv *priv = netdev_priv(dev); | |
608 | u32 reg_sr = at91_read(priv, AT91_SR); | |
609 | const unsigned long *addr = (unsigned long *)®_sr; | |
610 | unsigned int mb; | |
611 | int received = 0; | |
612 | ||
613 | if (priv->rx_next > AT91_MB_RX_LOW_LAST && | |
614 | reg_sr & AT91_MB_RX_LOW_MASK) | |
882055c8 MKB |
615 | netdev_info(dev, |
616 | "order of incoming frames cannot be guaranteed\n"); | |
99c4a634 DM |
617 | |
618 | again: | |
0909c1ec MKB |
619 | for (mb = find_next_bit(addr, AT91_MB_RX_LAST + 1, priv->rx_next); |
620 | mb < AT91_MB_RX_LAST + 1 && quota > 0; | |
99c4a634 | 621 | reg_sr = at91_read(priv, AT91_SR), |
0909c1ec | 622 | mb = find_next_bit(addr, AT91_MB_RX_LAST + 1, ++priv->rx_next)) { |
99c4a634 DM |
623 | at91_read_msg(dev, mb); |
624 | ||
625 | /* reactivate mailboxes */ | |
626 | if (mb == AT91_MB_RX_LOW_LAST) | |
627 | /* all lower mailboxed, if just finished it */ | |
628 | at91_activate_rx_low(priv); | |
629 | else if (mb > AT91_MB_RX_LOW_LAST) | |
630 | /* only the mailbox we read */ | |
631 | at91_activate_rx_mb(priv, mb); | |
632 | ||
633 | received++; | |
634 | quota--; | |
635 | } | |
636 | ||
637 | /* upper group completed, look again in lower */ | |
638 | if (priv->rx_next > AT91_MB_RX_LOW_LAST && | |
0909c1ec MKB |
639 | quota > 0 && mb > AT91_MB_RX_LAST) { |
640 | priv->rx_next = AT91_MB_RX_FIRST; | |
99c4a634 DM |
641 | goto again; |
642 | } | |
643 | ||
644 | return received; | |
645 | } | |
646 | ||
647 | static void at91_poll_err_frame(struct net_device *dev, | |
648 | struct can_frame *cf, u32 reg_sr) | |
649 | { | |
650 | struct at91_priv *priv = netdev_priv(dev); | |
651 | ||
652 | /* CRC error */ | |
653 | if (reg_sr & AT91_IRQ_CERR) { | |
882055c8 | 654 | netdev_dbg(dev, "CERR irq\n"); |
99c4a634 DM |
655 | dev->stats.rx_errors++; |
656 | priv->can.can_stats.bus_error++; | |
657 | cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; | |
658 | } | |
659 | ||
660 | /* Stuffing Error */ | |
661 | if (reg_sr & AT91_IRQ_SERR) { | |
882055c8 | 662 | netdev_dbg(dev, "SERR irq\n"); |
99c4a634 DM |
663 | dev->stats.rx_errors++; |
664 | priv->can.can_stats.bus_error++; | |
665 | cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; | |
666 | cf->data[2] |= CAN_ERR_PROT_STUFF; | |
667 | } | |
668 | ||
669 | /* Acknowledgement Error */ | |
670 | if (reg_sr & AT91_IRQ_AERR) { | |
882055c8 | 671 | netdev_dbg(dev, "AERR irq\n"); |
99c4a634 DM |
672 | dev->stats.tx_errors++; |
673 | cf->can_id |= CAN_ERR_ACK; | |
674 | } | |
675 | ||
676 | /* Form error */ | |
677 | if (reg_sr & AT91_IRQ_FERR) { | |
882055c8 | 678 | netdev_dbg(dev, "FERR irq\n"); |
99c4a634 DM |
679 | dev->stats.rx_errors++; |
680 | priv->can.can_stats.bus_error++; | |
681 | cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; | |
682 | cf->data[2] |= CAN_ERR_PROT_FORM; | |
683 | } | |
684 | ||
685 | /* Bit Error */ | |
686 | if (reg_sr & AT91_IRQ_BERR) { | |
882055c8 | 687 | netdev_dbg(dev, "BERR irq\n"); |
99c4a634 DM |
688 | dev->stats.tx_errors++; |
689 | priv->can.can_stats.bus_error++; | |
690 | cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; | |
691 | cf->data[2] |= CAN_ERR_PROT_BIT; | |
692 | } | |
693 | } | |
694 | ||
695 | static int at91_poll_err(struct net_device *dev, int quota, u32 reg_sr) | |
696 | { | |
697 | struct sk_buff *skb; | |
698 | struct can_frame *cf; | |
699 | ||
700 | if (quota == 0) | |
701 | return 0; | |
702 | ||
703 | skb = alloc_can_err_skb(dev, &cf); | |
704 | if (unlikely(!skb)) | |
705 | return 0; | |
706 | ||
707 | at91_poll_err_frame(dev, cf, reg_sr); | |
708 | netif_receive_skb(skb); | |
709 | ||
99c4a634 DM |
710 | dev->stats.rx_packets++; |
711 | dev->stats.rx_bytes += cf->can_dlc; | |
712 | ||
713 | return 1; | |
714 | } | |
715 | ||
716 | static int at91_poll(struct napi_struct *napi, int quota) | |
717 | { | |
718 | struct net_device *dev = napi->dev; | |
719 | const struct at91_priv *priv = netdev_priv(dev); | |
720 | u32 reg_sr = at91_read(priv, AT91_SR); | |
721 | int work_done = 0; | |
722 | ||
723 | if (reg_sr & AT91_IRQ_MB_RX) | |
724 | work_done += at91_poll_rx(dev, quota - work_done); | |
725 | ||
726 | /* | |
727 | * The error bits are clear on read, | |
728 | * so use saved value from irq handler. | |
729 | */ | |
730 | reg_sr |= priv->reg_sr; | |
731 | if (reg_sr & AT91_IRQ_ERR_FRAME) | |
732 | work_done += at91_poll_err(dev, quota - work_done, reg_sr); | |
733 | ||
734 | if (work_done < quota) { | |
735 | /* enable IRQs for frame errors and all mailboxes >= rx_next */ | |
736 | u32 reg_ier = AT91_IRQ_ERR_FRAME; | |
737 | reg_ier |= AT91_IRQ_MB_RX & ~AT91_MB_RX_MASK(priv->rx_next); | |
738 | ||
739 | napi_complete(napi); | |
740 | at91_write(priv, AT91_IER, reg_ier); | |
741 | } | |
742 | ||
743 | return work_done; | |
744 | } | |
745 | ||
746 | /* | |
747 | * theory of operation: | |
748 | * | |
749 | * priv->tx_echo holds the number of the oldest can_frame put for | |
750 | * transmission into the hardware, but not yet ACKed by the CAN tx | |
751 | * complete IRQ. | |
752 | * | |
753 | * We iterate from priv->tx_echo to priv->tx_next and check if the | |
754 | * packet has been transmitted, echo it back to the CAN framework. If | |
755 | * we discover a not yet transmitted package, stop looking for more. | |
756 | * | |
757 | */ | |
758 | static void at91_irq_tx(struct net_device *dev, u32 reg_sr) | |
759 | { | |
760 | struct at91_priv *priv = netdev_priv(dev); | |
761 | u32 reg_msr; | |
762 | unsigned int mb; | |
763 | ||
764 | /* masking of reg_sr not needed, already done by at91_irq */ | |
765 | ||
766 | for (/* nix */; (priv->tx_next - priv->tx_echo) > 0; priv->tx_echo++) { | |
767 | mb = get_tx_echo_mb(priv); | |
768 | ||
769 | /* no event in mailbox? */ | |
770 | if (!(reg_sr & (1 << mb))) | |
771 | break; | |
772 | ||
773 | /* Disable irq for this TX mailbox */ | |
774 | at91_write(priv, AT91_IDR, 1 << mb); | |
775 | ||
776 | /* | |
777 | * only echo if mailbox signals us a transfer | |
778 | * complete (MSR_MRDY). Otherwise it's a tansfer | |
779 | * abort. "can_bus_off()" takes care about the skbs | |
780 | * parked in the echo queue. | |
781 | */ | |
782 | reg_msr = at91_read(priv, AT91_MSR(mb)); | |
783 | if (likely(reg_msr & AT91_MSR_MRDY && | |
784 | ~reg_msr & AT91_MSR_MABT)) { | |
25985edc | 785 | /* _NOTE_: subtract AT91_MB_TX_FIRST offset from mb! */ |
99c4a634 DM |
786 | can_get_echo_skb(dev, mb - AT91_MB_TX_FIRST); |
787 | dev->stats.tx_packets++; | |
788 | } | |
789 | } | |
790 | ||
791 | /* | |
792 | * restart queue if we don't have a wrap around but restart if | |
793 | * we get a TX int for the last can frame directly before a | |
794 | * wrap around. | |
795 | */ | |
796 | if ((priv->tx_next & AT91_NEXT_MASK) != 0 || | |
797 | (priv->tx_echo & AT91_NEXT_MASK) == 0) | |
798 | netif_wake_queue(dev); | |
799 | } | |
800 | ||
801 | static void at91_irq_err_state(struct net_device *dev, | |
802 | struct can_frame *cf, enum can_state new_state) | |
803 | { | |
804 | struct at91_priv *priv = netdev_priv(dev); | |
33a6f298 MKB |
805 | u32 reg_idr = 0, reg_ier = 0; |
806 | struct can_berr_counter bec; | |
99c4a634 | 807 | |
33a6f298 | 808 | at91_get_berr_counter(dev, &bec); |
99c4a634 DM |
809 | |
810 | switch (priv->can.state) { | |
811 | case CAN_STATE_ERROR_ACTIVE: | |
812 | /* | |
813 | * from: ERROR_ACTIVE | |
814 | * to : ERROR_WARNING, ERROR_PASSIVE, BUS_OFF | |
815 | * => : there was a warning int | |
816 | */ | |
817 | if (new_state >= CAN_STATE_ERROR_WARNING && | |
818 | new_state <= CAN_STATE_BUS_OFF) { | |
882055c8 | 819 | netdev_dbg(dev, "Error Warning IRQ\n"); |
99c4a634 DM |
820 | priv->can.can_stats.error_warning++; |
821 | ||
822 | cf->can_id |= CAN_ERR_CRTL; | |
33a6f298 | 823 | cf->data[1] = (bec.txerr > bec.rxerr) ? |
99c4a634 DM |
824 | CAN_ERR_CRTL_TX_WARNING : |
825 | CAN_ERR_CRTL_RX_WARNING; | |
826 | } | |
827 | case CAN_STATE_ERROR_WARNING: /* fallthrough */ | |
828 | /* | |
829 | * from: ERROR_ACTIVE, ERROR_WARNING | |
830 | * to : ERROR_PASSIVE, BUS_OFF | |
831 | * => : error passive int | |
832 | */ | |
833 | if (new_state >= CAN_STATE_ERROR_PASSIVE && | |
834 | new_state <= CAN_STATE_BUS_OFF) { | |
882055c8 | 835 | netdev_dbg(dev, "Error Passive IRQ\n"); |
99c4a634 DM |
836 | priv->can.can_stats.error_passive++; |
837 | ||
838 | cf->can_id |= CAN_ERR_CRTL; | |
33a6f298 | 839 | cf->data[1] = (bec.txerr > bec.rxerr) ? |
99c4a634 DM |
840 | CAN_ERR_CRTL_TX_PASSIVE : |
841 | CAN_ERR_CRTL_RX_PASSIVE; | |
842 | } | |
843 | break; | |
844 | case CAN_STATE_BUS_OFF: | |
845 | /* | |
846 | * from: BUS_OFF | |
847 | * to : ERROR_ACTIVE, ERROR_WARNING, ERROR_PASSIVE | |
848 | */ | |
849 | if (new_state <= CAN_STATE_ERROR_PASSIVE) { | |
850 | cf->can_id |= CAN_ERR_RESTARTED; | |
851 | ||
882055c8 | 852 | netdev_dbg(dev, "restarted\n"); |
99c4a634 DM |
853 | priv->can.can_stats.restarts++; |
854 | ||
855 | netif_carrier_on(dev); | |
856 | netif_wake_queue(dev); | |
857 | } | |
858 | break; | |
859 | default: | |
860 | break; | |
861 | } | |
862 | ||
863 | ||
864 | /* process state changes depending on the new state */ | |
865 | switch (new_state) { | |
866 | case CAN_STATE_ERROR_ACTIVE: | |
867 | /* | |
868 | * actually we want to enable AT91_IRQ_WARN here, but | |
869 | * it screws up the system under certain | |
870 | * circumstances. so just enable AT91_IRQ_ERRP, thus | |
871 | * the "fallthrough" | |
872 | */ | |
882055c8 | 873 | netdev_dbg(dev, "Error Active\n"); |
99c4a634 DM |
874 | cf->can_id |= CAN_ERR_PROT; |
875 | cf->data[2] = CAN_ERR_PROT_ACTIVE; | |
876 | case CAN_STATE_ERROR_WARNING: /* fallthrough */ | |
877 | reg_idr = AT91_IRQ_ERRA | AT91_IRQ_WARN | AT91_IRQ_BOFF; | |
878 | reg_ier = AT91_IRQ_ERRP; | |
879 | break; | |
880 | case CAN_STATE_ERROR_PASSIVE: | |
881 | reg_idr = AT91_IRQ_ERRA | AT91_IRQ_WARN | AT91_IRQ_ERRP; | |
882 | reg_ier = AT91_IRQ_BOFF; | |
883 | break; | |
884 | case CAN_STATE_BUS_OFF: | |
885 | reg_idr = AT91_IRQ_ERRA | AT91_IRQ_ERRP | | |
886 | AT91_IRQ_WARN | AT91_IRQ_BOFF; | |
887 | reg_ier = 0; | |
888 | ||
889 | cf->can_id |= CAN_ERR_BUSOFF; | |
890 | ||
882055c8 | 891 | netdev_dbg(dev, "bus-off\n"); |
99c4a634 DM |
892 | netif_carrier_off(dev); |
893 | priv->can.can_stats.bus_off++; | |
894 | ||
895 | /* turn off chip, if restart is disabled */ | |
896 | if (!priv->can.restart_ms) { | |
897 | at91_chip_stop(dev, CAN_STATE_BUS_OFF); | |
898 | return; | |
899 | } | |
900 | break; | |
901 | default: | |
902 | break; | |
903 | } | |
904 | ||
905 | at91_write(priv, AT91_IDR, reg_idr); | |
906 | at91_write(priv, AT91_IER, reg_ier); | |
907 | } | |
908 | ||
909 | static void at91_irq_err(struct net_device *dev) | |
910 | { | |
911 | struct at91_priv *priv = netdev_priv(dev); | |
912 | struct sk_buff *skb; | |
913 | struct can_frame *cf; | |
914 | enum can_state new_state; | |
915 | u32 reg_sr; | |
916 | ||
917 | reg_sr = at91_read(priv, AT91_SR); | |
918 | ||
919 | /* we need to look at the unmasked reg_sr */ | |
920 | if (unlikely(reg_sr & AT91_IRQ_BOFF)) | |
921 | new_state = CAN_STATE_BUS_OFF; | |
922 | else if (unlikely(reg_sr & AT91_IRQ_ERRP)) | |
923 | new_state = CAN_STATE_ERROR_PASSIVE; | |
924 | else if (unlikely(reg_sr & AT91_IRQ_WARN)) | |
925 | new_state = CAN_STATE_ERROR_WARNING; | |
926 | else if (likely(reg_sr & AT91_IRQ_ERRA)) | |
927 | new_state = CAN_STATE_ERROR_ACTIVE; | |
928 | else { | |
882055c8 | 929 | netdev_err(dev, "BUG! hardware in undefined state\n"); |
99c4a634 DM |
930 | return; |
931 | } | |
932 | ||
933 | /* state hasn't changed */ | |
934 | if (likely(new_state == priv->can.state)) | |
935 | return; | |
936 | ||
937 | skb = alloc_can_err_skb(dev, &cf); | |
938 | if (unlikely(!skb)) | |
939 | return; | |
940 | ||
941 | at91_irq_err_state(dev, cf, new_state); | |
942 | netif_rx(skb); | |
943 | ||
99c4a634 DM |
944 | dev->stats.rx_packets++; |
945 | dev->stats.rx_bytes += cf->can_dlc; | |
946 | ||
947 | priv->can.state = new_state; | |
948 | } | |
949 | ||
950 | /* | |
951 | * interrupt handler | |
952 | */ | |
953 | static irqreturn_t at91_irq(int irq, void *dev_id) | |
954 | { | |
955 | struct net_device *dev = dev_id; | |
956 | struct at91_priv *priv = netdev_priv(dev); | |
957 | irqreturn_t handled = IRQ_NONE; | |
958 | u32 reg_sr, reg_imr; | |
959 | ||
960 | reg_sr = at91_read(priv, AT91_SR); | |
961 | reg_imr = at91_read(priv, AT91_IMR); | |
962 | ||
963 | /* Ignore masked interrupts */ | |
964 | reg_sr &= reg_imr; | |
965 | if (!reg_sr) | |
966 | goto exit; | |
967 | ||
968 | handled = IRQ_HANDLED; | |
969 | ||
970 | /* Receive or error interrupt? -> napi */ | |
971 | if (reg_sr & (AT91_IRQ_MB_RX | AT91_IRQ_ERR_FRAME)) { | |
972 | /* | |
973 | * The error bits are clear on read, | |
974 | * save for later use. | |
975 | */ | |
976 | priv->reg_sr = reg_sr; | |
977 | at91_write(priv, AT91_IDR, | |
978 | AT91_IRQ_MB_RX | AT91_IRQ_ERR_FRAME); | |
979 | napi_schedule(&priv->napi); | |
980 | } | |
981 | ||
982 | /* Transmission complete interrupt */ | |
983 | if (reg_sr & AT91_IRQ_MB_TX) | |
984 | at91_irq_tx(dev, reg_sr); | |
985 | ||
986 | at91_irq_err(dev); | |
987 | ||
988 | exit: | |
989 | return handled; | |
990 | } | |
991 | ||
992 | static int at91_open(struct net_device *dev) | |
993 | { | |
994 | struct at91_priv *priv = netdev_priv(dev); | |
995 | int err; | |
996 | ||
997 | clk_enable(priv->clk); | |
998 | ||
999 | /* check or determine and set bittime */ | |
1000 | err = open_candev(dev); | |
1001 | if (err) | |
1002 | goto out; | |
1003 | ||
1004 | /* register interrupt handler */ | |
1005 | if (request_irq(dev->irq, at91_irq, IRQF_SHARED, | |
1006 | dev->name, dev)) { | |
1007 | err = -EAGAIN; | |
1008 | goto out_close; | |
1009 | } | |
1010 | ||
1011 | /* start chip and queuing */ | |
1012 | at91_chip_start(dev); | |
1013 | napi_enable(&priv->napi); | |
1014 | netif_start_queue(dev); | |
1015 | ||
1016 | return 0; | |
1017 | ||
1018 | out_close: | |
1019 | close_candev(dev); | |
1020 | out: | |
1021 | clk_disable(priv->clk); | |
1022 | ||
1023 | return err; | |
1024 | } | |
1025 | ||
1026 | /* | |
1027 | * stop CAN bus activity | |
1028 | */ | |
1029 | static int at91_close(struct net_device *dev) | |
1030 | { | |
1031 | struct at91_priv *priv = netdev_priv(dev); | |
1032 | ||
1033 | netif_stop_queue(dev); | |
1034 | napi_disable(&priv->napi); | |
1035 | at91_chip_stop(dev, CAN_STATE_STOPPED); | |
1036 | ||
1037 | free_irq(dev->irq, dev); | |
1038 | clk_disable(priv->clk); | |
1039 | ||
1040 | close_candev(dev); | |
1041 | ||
1042 | return 0; | |
1043 | } | |
1044 | ||
1045 | static int at91_set_mode(struct net_device *dev, enum can_mode mode) | |
1046 | { | |
1047 | switch (mode) { | |
1048 | case CAN_MODE_START: | |
1049 | at91_chip_start(dev); | |
1050 | netif_wake_queue(dev); | |
1051 | break; | |
1052 | ||
1053 | default: | |
1054 | return -EOPNOTSUPP; | |
1055 | } | |
1056 | ||
1057 | return 0; | |
1058 | } | |
1059 | ||
1060 | static const struct net_device_ops at91_netdev_ops = { | |
1061 | .ndo_open = at91_open, | |
1062 | .ndo_stop = at91_close, | |
1063 | .ndo_start_xmit = at91_start_xmit, | |
1064 | }; | |
1065 | ||
3a5655a5 MKB |
1066 | static ssize_t at91_sysfs_show_mb0_id(struct device *dev, |
1067 | struct device_attribute *attr, char *buf) | |
1068 | { | |
1069 | struct at91_priv *priv = netdev_priv(to_net_dev(dev)); | |
1070 | ||
1071 | if (priv->mb0_id & CAN_EFF_FLAG) | |
1072 | return snprintf(buf, PAGE_SIZE, "0x%08x\n", priv->mb0_id); | |
1073 | else | |
1074 | return snprintf(buf, PAGE_SIZE, "0x%03x\n", priv->mb0_id); | |
1075 | } | |
1076 | ||
1077 | static ssize_t at91_sysfs_set_mb0_id(struct device *dev, | |
1078 | struct device_attribute *attr, const char *buf, size_t count) | |
1079 | { | |
1080 | struct net_device *ndev = to_net_dev(dev); | |
1081 | struct at91_priv *priv = netdev_priv(ndev); | |
1082 | unsigned long can_id; | |
1083 | ssize_t ret; | |
1084 | int err; | |
1085 | ||
1086 | rtnl_lock(); | |
1087 | ||
1088 | if (ndev->flags & IFF_UP) { | |
1089 | ret = -EBUSY; | |
1090 | goto out; | |
1091 | } | |
1092 | ||
1093 | err = strict_strtoul(buf, 0, &can_id); | |
1094 | if (err) { | |
1095 | ret = err; | |
1096 | goto out; | |
1097 | } | |
1098 | ||
1099 | if (can_id & CAN_EFF_FLAG) | |
1100 | can_id &= CAN_EFF_MASK | CAN_EFF_FLAG; | |
1101 | else | |
1102 | can_id &= CAN_SFF_MASK; | |
1103 | ||
1104 | priv->mb0_id = can_id; | |
1105 | ret = count; | |
1106 | ||
1107 | out: | |
1108 | rtnl_unlock(); | |
1109 | return ret; | |
1110 | } | |
1111 | ||
fef52b01 | 1112 | static DEVICE_ATTR(mb0_id, S_IWUSR | S_IRUGO, |
3a5655a5 MKB |
1113 | at91_sysfs_show_mb0_id, at91_sysfs_set_mb0_id); |
1114 | ||
1115 | static struct attribute *at91_sysfs_attrs[] = { | |
1116 | &dev_attr_mb0_id.attr, | |
1117 | NULL, | |
1118 | }; | |
1119 | ||
1120 | static struct attribute_group at91_sysfs_attr_group = { | |
1121 | .attrs = at91_sysfs_attrs, | |
1122 | }; | |
1123 | ||
a9d992ec | 1124 | static int __devinit at91_can_probe(struct platform_device *pdev) |
99c4a634 DM |
1125 | { |
1126 | struct net_device *dev; | |
1127 | struct at91_priv *priv; | |
1128 | struct resource *res; | |
1129 | struct clk *clk; | |
1130 | void __iomem *addr; | |
1131 | int err, irq; | |
1132 | ||
1133 | clk = clk_get(&pdev->dev, "can_clk"); | |
1134 | if (IS_ERR(clk)) { | |
1135 | dev_err(&pdev->dev, "no clock defined\n"); | |
1136 | err = -ENODEV; | |
1137 | goto exit; | |
1138 | } | |
1139 | ||
1140 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1141 | irq = platform_get_irq(pdev, 0); | |
4773a47d | 1142 | if (!res || irq <= 0) { |
99c4a634 DM |
1143 | err = -ENODEV; |
1144 | goto exit_put; | |
1145 | } | |
1146 | ||
1147 | if (!request_mem_region(res->start, | |
1148 | resource_size(res), | |
1149 | pdev->name)) { | |
1150 | err = -EBUSY; | |
1151 | goto exit_put; | |
1152 | } | |
1153 | ||
1154 | addr = ioremap_nocache(res->start, resource_size(res)); | |
1155 | if (!addr) { | |
1156 | err = -ENOMEM; | |
1157 | goto exit_release; | |
1158 | } | |
1159 | ||
a6e4bc53 | 1160 | dev = alloc_candev(sizeof(struct at91_priv), AT91_MB_TX_NUM); |
99c4a634 DM |
1161 | if (!dev) { |
1162 | err = -ENOMEM; | |
1163 | goto exit_iounmap; | |
1164 | } | |
1165 | ||
1166 | dev->netdev_ops = &at91_netdev_ops; | |
1167 | dev->irq = irq; | |
1168 | dev->flags |= IFF_ECHO; | |
3a5655a5 | 1169 | dev->sysfs_groups[0] = &at91_sysfs_attr_group; |
99c4a634 DM |
1170 | |
1171 | priv = netdev_priv(dev); | |
1172 | priv->can.clock.freq = clk_get_rate(clk); | |
1173 | priv->can.bittiming_const = &at91_bittiming_const; | |
99c4a634 | 1174 | priv->can.do_set_mode = at91_set_mode; |
33a6f298 | 1175 | priv->can.do_get_berr_counter = at91_get_berr_counter; |
ad72c347 | 1176 | priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES; |
99c4a634 DM |
1177 | priv->reg_base = addr; |
1178 | priv->dev = dev; | |
1179 | priv->clk = clk; | |
1180 | priv->pdata = pdev->dev.platform_data; | |
3a5655a5 | 1181 | priv->mb0_id = 0x7ff; |
99c4a634 DM |
1182 | |
1183 | netif_napi_add(dev, &priv->napi, at91_poll, AT91_NAPI_WEIGHT); | |
1184 | ||
1185 | dev_set_drvdata(&pdev->dev, dev); | |
1186 | SET_NETDEV_DEV(dev, &pdev->dev); | |
1187 | ||
1188 | err = register_candev(dev); | |
1189 | if (err) { | |
1190 | dev_err(&pdev->dev, "registering netdev failed\n"); | |
1191 | goto exit_free; | |
1192 | } | |
1193 | ||
1194 | dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%d)\n", | |
1195 | priv->reg_base, dev->irq); | |
1196 | ||
1197 | return 0; | |
1198 | ||
1199 | exit_free: | |
759a6c76 | 1200 | free_candev(dev); |
99c4a634 DM |
1201 | exit_iounmap: |
1202 | iounmap(addr); | |
1203 | exit_release: | |
1204 | release_mem_region(res->start, resource_size(res)); | |
1205 | exit_put: | |
1206 | clk_put(clk); | |
1207 | exit: | |
1208 | return err; | |
1209 | } | |
1210 | ||
1211 | static int __devexit at91_can_remove(struct platform_device *pdev) | |
1212 | { | |
1213 | struct net_device *dev = platform_get_drvdata(pdev); | |
1214 | struct at91_priv *priv = netdev_priv(dev); | |
1215 | struct resource *res; | |
1216 | ||
1217 | unregister_netdev(dev); | |
1218 | ||
1219 | platform_set_drvdata(pdev, NULL); | |
1220 | ||
99c4a634 DM |
1221 | iounmap(priv->reg_base); |
1222 | ||
1223 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1224 | release_mem_region(res->start, resource_size(res)); | |
1225 | ||
1226 | clk_put(priv->clk); | |
1227 | ||
759a6c76 MKB |
1228 | free_candev(dev); |
1229 | ||
99c4a634 DM |
1230 | return 0; |
1231 | } | |
1232 | ||
1233 | static struct platform_driver at91_can_driver = { | |
1234 | .probe = at91_can_probe, | |
1235 | .remove = __devexit_p(at91_can_remove), | |
1236 | .driver = { | |
00389b08 | 1237 | .name = KBUILD_MODNAME, |
99c4a634 DM |
1238 | .owner = THIS_MODULE, |
1239 | }, | |
1240 | }; | |
1241 | ||
1242 | static int __init at91_can_module_init(void) | |
1243 | { | |
99c4a634 DM |
1244 | return platform_driver_register(&at91_can_driver); |
1245 | } | |
1246 | ||
1247 | static void __exit at91_can_module_exit(void) | |
1248 | { | |
1249 | platform_driver_unregister(&at91_can_driver); | |
99c4a634 DM |
1250 | } |
1251 | ||
1252 | module_init(at91_can_module_init); | |
1253 | module_exit(at91_can_module_exit); | |
1254 | ||
1255 | MODULE_AUTHOR("Marc Kleine-Budde <mkl@pengutronix.de>"); | |
1256 | MODULE_LICENSE("GPL v2"); | |
00389b08 | 1257 | MODULE_DESCRIPTION(KBUILD_MODNAME " CAN netdevice driver"); |