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bbb84619 BS |
1 | /* |
2 | * Blackfin On-Chip CAN Driver | |
3 | * | |
4 | * Copyright 2004-2009 Analog Devices Inc. | |
5 | * | |
6 | * Enter bugs at http://blackfin.uclinux.org/ | |
7 | * | |
8 | * Licensed under the GPL-2 or later. | |
9 | */ | |
10 | ||
11 | #include <linux/module.h> | |
bbb84619 BS |
12 | #include <linux/kernel.h> |
13 | #include <linux/bitops.h> | |
14 | #include <linux/interrupt.h> | |
15 | #include <linux/errno.h> | |
16 | #include <linux/netdevice.h> | |
17 | #include <linux/skbuff.h> | |
18 | #include <linux/platform_device.h> | |
19 | ||
bbb84619 BS |
20 | #include <linux/can/dev.h> |
21 | #include <linux/can/error.h> | |
22 | ||
21afc27c | 23 | #include <asm/bfin_can.h> |
bbb84619 BS |
24 | #include <asm/portmux.h> |
25 | ||
26 | #define DRV_NAME "bfin_can" | |
27 | #define BFIN_CAN_TIMEOUT 100 | |
e9dcd161 | 28 | #define TX_ECHO_SKB_MAX 1 |
bbb84619 | 29 | |
bbb84619 BS |
30 | /* |
31 | * bfin can private data | |
32 | */ | |
33 | struct bfin_can_priv { | |
34 | struct can_priv can; /* must be the first member */ | |
35 | struct net_device *dev; | |
36 | void __iomem *membase; | |
37 | int rx_irq; | |
38 | int tx_irq; | |
39 | int err_irq; | |
40 | unsigned short *pin_list; | |
41 | }; | |
42 | ||
43 | /* | |
44 | * bfin can timing parameters | |
45 | */ | |
194b9a4c | 46 | static const struct can_bittiming_const bfin_can_bittiming_const = { |
bbb84619 BS |
47 | .name = DRV_NAME, |
48 | .tseg1_min = 1, | |
49 | .tseg1_max = 16, | |
50 | .tseg2_min = 1, | |
51 | .tseg2_max = 8, | |
52 | .sjw_max = 4, | |
53 | /* | |
54 | * Although the BRP field can be set to any value, it is recommended | |
55 | * that the value be greater than or equal to 4, as restrictions | |
56 | * apply to the bit timing configuration when BRP is less than 4. | |
57 | */ | |
58 | .brp_min = 4, | |
59 | .brp_max = 1024, | |
60 | .brp_inc = 1, | |
61 | }; | |
62 | ||
63 | static int bfin_can_set_bittiming(struct net_device *dev) | |
64 | { | |
65 | struct bfin_can_priv *priv = netdev_priv(dev); | |
66 | struct bfin_can_regs __iomem *reg = priv->membase; | |
67 | struct can_bittiming *bt = &priv->can.bittiming; | |
68 | u16 clk, timing; | |
69 | ||
70 | clk = bt->brp - 1; | |
71 | timing = ((bt->sjw - 1) << 8) | (bt->prop_seg + bt->phase_seg1 - 1) | | |
72 | ((bt->phase_seg2 - 1) << 4); | |
73 | ||
74 | /* | |
75 | * If the SAM bit is set, the input signal is oversampled three times | |
76 | * at the SCLK rate. | |
77 | */ | |
78 | if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) | |
79 | timing |= SAM; | |
80 | ||
cfbf7586 MF |
81 | bfin_write(®->clock, clk); |
82 | bfin_write(®->timing, timing); | |
bbb84619 | 83 | |
aabdfd6a | 84 | netdev_info(dev, "setting CLOCK=0x%04x TIMING=0x%04x\n", clk, timing); |
bbb84619 BS |
85 | |
86 | return 0; | |
87 | } | |
88 | ||
89 | static void bfin_can_set_reset_mode(struct net_device *dev) | |
90 | { | |
91 | struct bfin_can_priv *priv = netdev_priv(dev); | |
92 | struct bfin_can_regs __iomem *reg = priv->membase; | |
93 | int timeout = BFIN_CAN_TIMEOUT; | |
94 | int i; | |
95 | ||
96 | /* disable interrupts */ | |
cfbf7586 MF |
97 | bfin_write(®->mbim1, 0); |
98 | bfin_write(®->mbim2, 0); | |
99 | bfin_write(®->gim, 0); | |
bbb84619 BS |
100 | |
101 | /* reset can and enter configuration mode */ | |
cfbf7586 | 102 | bfin_write(®->control, SRS | CCR); |
bbb84619 | 103 | SSYNC(); |
cfbf7586 | 104 | bfin_write(®->control, CCR); |
bbb84619 | 105 | SSYNC(); |
cfbf7586 | 106 | while (!(bfin_read(®->control) & CCA)) { |
bbb84619 BS |
107 | udelay(10); |
108 | if (--timeout == 0) { | |
aabdfd6a | 109 | netdev_err(dev, "fail to enter configuration mode\n"); |
bbb84619 BS |
110 | BUG(); |
111 | } | |
112 | } | |
113 | ||
114 | /* | |
115 | * All mailbox configurations are marked as inactive | |
116 | * by writing to CAN Mailbox Configuration Registers 1 and 2 | |
117 | * For all bits: 0 - Mailbox disabled, 1 - Mailbox enabled | |
118 | */ | |
cfbf7586 MF |
119 | bfin_write(®->mc1, 0); |
120 | bfin_write(®->mc2, 0); | |
bbb84619 BS |
121 | |
122 | /* Set Mailbox Direction */ | |
cfbf7586 MF |
123 | bfin_write(®->md1, 0xFFFF); /* mailbox 1-16 are RX */ |
124 | bfin_write(®->md2, 0); /* mailbox 17-32 are TX */ | |
bbb84619 BS |
125 | |
126 | /* RECEIVE_STD_CHL */ | |
127 | for (i = 0; i < 2; i++) { | |
cfbf7586 MF |
128 | bfin_write(®->chl[RECEIVE_STD_CHL + i].id0, 0); |
129 | bfin_write(®->chl[RECEIVE_STD_CHL + i].id1, AME); | |
130 | bfin_write(®->chl[RECEIVE_STD_CHL + i].dlc, 0); | |
131 | bfin_write(®->msk[RECEIVE_STD_CHL + i].amh, 0x1FFF); | |
132 | bfin_write(®->msk[RECEIVE_STD_CHL + i].aml, 0xFFFF); | |
bbb84619 BS |
133 | } |
134 | ||
135 | /* RECEIVE_EXT_CHL */ | |
136 | for (i = 0; i < 2; i++) { | |
cfbf7586 MF |
137 | bfin_write(®->chl[RECEIVE_EXT_CHL + i].id0, 0); |
138 | bfin_write(®->chl[RECEIVE_EXT_CHL + i].id1, AME | IDE); | |
139 | bfin_write(®->chl[RECEIVE_EXT_CHL + i].dlc, 0); | |
140 | bfin_write(®->msk[RECEIVE_EXT_CHL + i].amh, 0x1FFF); | |
141 | bfin_write(®->msk[RECEIVE_EXT_CHL + i].aml, 0xFFFF); | |
bbb84619 BS |
142 | } |
143 | ||
cfbf7586 MF |
144 | bfin_write(®->mc2, BIT(TRANSMIT_CHL - 16)); |
145 | bfin_write(®->mc1, BIT(RECEIVE_STD_CHL) + BIT(RECEIVE_EXT_CHL)); | |
bbb84619 BS |
146 | SSYNC(); |
147 | ||
148 | priv->can.state = CAN_STATE_STOPPED; | |
149 | } | |
150 | ||
151 | static void bfin_can_set_normal_mode(struct net_device *dev) | |
152 | { | |
153 | struct bfin_can_priv *priv = netdev_priv(dev); | |
154 | struct bfin_can_regs __iomem *reg = priv->membase; | |
155 | int timeout = BFIN_CAN_TIMEOUT; | |
156 | ||
157 | /* | |
158 | * leave configuration mode | |
159 | */ | |
cfbf7586 | 160 | bfin_write(®->control, bfin_read(®->control) & ~CCR); |
bbb84619 | 161 | |
cfbf7586 | 162 | while (bfin_read(®->status) & CCA) { |
bbb84619 BS |
163 | udelay(10); |
164 | if (--timeout == 0) { | |
aabdfd6a | 165 | netdev_err(dev, "fail to leave configuration mode\n"); |
bbb84619 BS |
166 | BUG(); |
167 | } | |
168 | } | |
169 | ||
170 | /* | |
171 | * clear _All_ tx and rx interrupts | |
172 | */ | |
cfbf7586 MF |
173 | bfin_write(®->mbtif1, 0xFFFF); |
174 | bfin_write(®->mbtif2, 0xFFFF); | |
175 | bfin_write(®->mbrif1, 0xFFFF); | |
176 | bfin_write(®->mbrif2, 0xFFFF); | |
bbb84619 BS |
177 | |
178 | /* | |
179 | * clear global interrupt status register | |
180 | */ | |
cfbf7586 | 181 | bfin_write(®->gis, 0x7FF); /* overwrites with '1' */ |
bbb84619 BS |
182 | |
183 | /* | |
184 | * Initialize Interrupts | |
185 | * - set bits in the mailbox interrupt mask register | |
186 | * - global interrupt mask | |
187 | */ | |
cfbf7586 MF |
188 | bfin_write(®->mbim1, BIT(RECEIVE_STD_CHL) + BIT(RECEIVE_EXT_CHL)); |
189 | bfin_write(®->mbim2, BIT(TRANSMIT_CHL - 16)); | |
bbb84619 | 190 | |
cfbf7586 | 191 | bfin_write(®->gim, EPIM | BOIM | RMLIM); |
bbb84619 BS |
192 | SSYNC(); |
193 | } | |
194 | ||
195 | static void bfin_can_start(struct net_device *dev) | |
196 | { | |
197 | struct bfin_can_priv *priv = netdev_priv(dev); | |
198 | ||
199 | /* enter reset mode */ | |
200 | if (priv->can.state != CAN_STATE_STOPPED) | |
201 | bfin_can_set_reset_mode(dev); | |
202 | ||
203 | /* leave reset mode */ | |
204 | bfin_can_set_normal_mode(dev); | |
205 | } | |
206 | ||
207 | static int bfin_can_set_mode(struct net_device *dev, enum can_mode mode) | |
208 | { | |
209 | switch (mode) { | |
210 | case CAN_MODE_START: | |
211 | bfin_can_start(dev); | |
212 | if (netif_queue_stopped(dev)) | |
213 | netif_wake_queue(dev); | |
214 | break; | |
215 | ||
216 | default: | |
217 | return -EOPNOTSUPP; | |
218 | } | |
219 | ||
220 | return 0; | |
221 | } | |
222 | ||
79d0d8a7 WG |
223 | static int bfin_can_get_berr_counter(const struct net_device *dev, |
224 | struct can_berr_counter *bec) | |
225 | { | |
226 | struct bfin_can_priv *priv = netdev_priv(dev); | |
227 | struct bfin_can_regs __iomem *reg = priv->membase; | |
228 | ||
229 | u16 cec = bfin_read(®->cec); | |
230 | ||
231 | bec->txerr = cec >> 8; | |
232 | bec->rxerr = cec; | |
233 | ||
234 | return 0; | |
235 | } | |
236 | ||
bbb84619 BS |
237 | static int bfin_can_start_xmit(struct sk_buff *skb, struct net_device *dev) |
238 | { | |
239 | struct bfin_can_priv *priv = netdev_priv(dev); | |
240 | struct bfin_can_regs __iomem *reg = priv->membase; | |
241 | struct can_frame *cf = (struct can_frame *)skb->data; | |
242 | u8 dlc = cf->can_dlc; | |
243 | canid_t id = cf->can_id; | |
244 | u8 *data = cf->data; | |
245 | u16 val; | |
246 | int i; | |
247 | ||
3ccd4c61 OH |
248 | if (can_dropped_invalid_skb(dev, skb)) |
249 | return NETDEV_TX_OK; | |
250 | ||
bbb84619 BS |
251 | netif_stop_queue(dev); |
252 | ||
253 | /* fill id */ | |
254 | if (id & CAN_EFF_FLAG) { | |
cfbf7586 | 255 | bfin_write(®->chl[TRANSMIT_CHL].id0, id); |
9118f08a MF |
256 | val = ((id & 0x1FFF0000) >> 16) | IDE; |
257 | } else | |
258 | val = (id << 2); | |
259 | if (id & CAN_RTR_FLAG) | |
260 | val |= RTR; | |
cfbf7586 | 261 | bfin_write(®->chl[TRANSMIT_CHL].id1, val | AME); |
bbb84619 BS |
262 | |
263 | /* fill payload */ | |
264 | for (i = 0; i < 8; i += 2) { | |
265 | val = ((7 - i) < dlc ? (data[7 - i]) : 0) + | |
266 | ((6 - i) < dlc ? (data[6 - i] << 8) : 0); | |
cfbf7586 | 267 | bfin_write(®->chl[TRANSMIT_CHL].data[i], val); |
bbb84619 BS |
268 | } |
269 | ||
270 | /* fill data length code */ | |
cfbf7586 | 271 | bfin_write(®->chl[TRANSMIT_CHL].dlc, dlc); |
bbb84619 | 272 | |
bbb84619 BS |
273 | can_put_echo_skb(skb, dev, 0); |
274 | ||
275 | /* set transmit request */ | |
cfbf7586 | 276 | bfin_write(®->trs2, BIT(TRANSMIT_CHL - 16)); |
bbb84619 BS |
277 | |
278 | return 0; | |
279 | } | |
280 | ||
281 | static void bfin_can_rx(struct net_device *dev, u16 isrc) | |
282 | { | |
283 | struct bfin_can_priv *priv = netdev_priv(dev); | |
284 | struct net_device_stats *stats = &dev->stats; | |
285 | struct bfin_can_regs __iomem *reg = priv->membase; | |
286 | struct can_frame *cf; | |
287 | struct sk_buff *skb; | |
288 | int obj; | |
289 | int i; | |
290 | u16 val; | |
291 | ||
292 | skb = alloc_can_skb(dev, &cf); | |
293 | if (skb == NULL) | |
294 | return; | |
295 | ||
296 | /* get id */ | |
297 | if (isrc & BIT(RECEIVE_EXT_CHL)) { | |
298 | /* extended frame format (EFF) */ | |
cfbf7586 | 299 | cf->can_id = ((bfin_read(®->chl[RECEIVE_EXT_CHL].id1) |
bbb84619 | 300 | & 0x1FFF) << 16) |
cfbf7586 | 301 | + bfin_read(®->chl[RECEIVE_EXT_CHL].id0); |
bbb84619 BS |
302 | cf->can_id |= CAN_EFF_FLAG; |
303 | obj = RECEIVE_EXT_CHL; | |
304 | } else { | |
305 | /* standard frame format (SFF) */ | |
cfbf7586 | 306 | cf->can_id = (bfin_read(®->chl[RECEIVE_STD_CHL].id1) |
bbb84619 BS |
307 | & 0x1ffc) >> 2; |
308 | obj = RECEIVE_STD_CHL; | |
309 | } | |
cfbf7586 | 310 | if (bfin_read(®->chl[obj].id1) & RTR) |
bbb84619 BS |
311 | cf->can_id |= CAN_RTR_FLAG; |
312 | ||
313 | /* get data length code */ | |
cfbf7586 | 314 | cf->can_dlc = get_can_dlc(bfin_read(®->chl[obj].dlc) & 0xF); |
bbb84619 BS |
315 | |
316 | /* get payload */ | |
317 | for (i = 0; i < 8; i += 2) { | |
cfbf7586 | 318 | val = bfin_read(®->chl[obj].data[i]); |
bbb84619 BS |
319 | cf->data[7 - i] = (7 - i) < cf->can_dlc ? val : 0; |
320 | cf->data[6 - i] = (6 - i) < cf->can_dlc ? (val >> 8) : 0; | |
321 | } | |
322 | ||
323 | netif_rx(skb); | |
324 | ||
325 | stats->rx_packets++; | |
326 | stats->rx_bytes += cf->can_dlc; | |
327 | } | |
328 | ||
329 | static int bfin_can_err(struct net_device *dev, u16 isrc, u16 status) | |
330 | { | |
331 | struct bfin_can_priv *priv = netdev_priv(dev); | |
332 | struct bfin_can_regs __iomem *reg = priv->membase; | |
333 | struct net_device_stats *stats = &dev->stats; | |
334 | struct can_frame *cf; | |
335 | struct sk_buff *skb; | |
336 | enum can_state state = priv->can.state; | |
337 | ||
338 | skb = alloc_can_err_skb(dev, &cf); | |
339 | if (skb == NULL) | |
340 | return -ENOMEM; | |
341 | ||
342 | if (isrc & RMLIS) { | |
343 | /* data overrun interrupt */ | |
aabdfd6a | 344 | netdev_dbg(dev, "data overrun interrupt\n"); |
bbb84619 BS |
345 | cf->can_id |= CAN_ERR_CRTL; |
346 | cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW; | |
347 | stats->rx_over_errors++; | |
348 | stats->rx_errors++; | |
349 | } | |
350 | ||
351 | if (isrc & BOIS) { | |
aabdfd6a | 352 | netdev_dbg(dev, "bus-off mode interrupt\n"); |
bbb84619 BS |
353 | state = CAN_STATE_BUS_OFF; |
354 | cf->can_id |= CAN_ERR_BUSOFF; | |
355 | can_bus_off(dev); | |
356 | } | |
357 | ||
358 | if (isrc & EPIS) { | |
359 | /* error passive interrupt */ | |
aabdfd6a | 360 | netdev_dbg(dev, "error passive interrupt\n"); |
bbb84619 BS |
361 | state = CAN_STATE_ERROR_PASSIVE; |
362 | } | |
363 | ||
364 | if ((isrc & EWTIS) || (isrc & EWRIS)) { | |
aabdfd6a | 365 | netdev_dbg(dev, "Error Warning Transmit/Receive Interrupt\n"); |
bbb84619 BS |
366 | state = CAN_STATE_ERROR_WARNING; |
367 | } | |
368 | ||
369 | if (state != priv->can.state && (state == CAN_STATE_ERROR_WARNING || | |
370 | state == CAN_STATE_ERROR_PASSIVE)) { | |
cfbf7586 | 371 | u16 cec = bfin_read(®->cec); |
bbb84619 BS |
372 | u8 rxerr = cec; |
373 | u8 txerr = cec >> 8; | |
374 | ||
375 | cf->can_id |= CAN_ERR_CRTL; | |
376 | if (state == CAN_STATE_ERROR_WARNING) { | |
377 | priv->can.can_stats.error_warning++; | |
378 | cf->data[1] = (txerr > rxerr) ? | |
379 | CAN_ERR_CRTL_TX_WARNING : | |
380 | CAN_ERR_CRTL_RX_WARNING; | |
381 | } else { | |
382 | priv->can.can_stats.error_passive++; | |
383 | cf->data[1] = (txerr > rxerr) ? | |
384 | CAN_ERR_CRTL_TX_PASSIVE : | |
385 | CAN_ERR_CRTL_RX_PASSIVE; | |
386 | } | |
387 | } | |
388 | ||
389 | if (status) { | |
390 | priv->can.can_stats.bus_error++; | |
391 | ||
392 | cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; | |
393 | ||
394 | if (status & BEF) | |
395 | cf->data[2] |= CAN_ERR_PROT_BIT; | |
396 | else if (status & FER) | |
397 | cf->data[2] |= CAN_ERR_PROT_FORM; | |
398 | else if (status & SER) | |
399 | cf->data[2] |= CAN_ERR_PROT_STUFF; | |
400 | else | |
401 | cf->data[2] |= CAN_ERR_PROT_UNSPEC; | |
402 | } | |
403 | ||
404 | priv->can.state = state; | |
405 | ||
406 | netif_rx(skb); | |
407 | ||
408 | stats->rx_packets++; | |
409 | stats->rx_bytes += cf->can_dlc; | |
410 | ||
411 | return 0; | |
412 | } | |
413 | ||
21c11bc5 | 414 | static irqreturn_t bfin_can_interrupt(int irq, void *dev_id) |
bbb84619 BS |
415 | { |
416 | struct net_device *dev = dev_id; | |
417 | struct bfin_can_priv *priv = netdev_priv(dev); | |
418 | struct bfin_can_regs __iomem *reg = priv->membase; | |
419 | struct net_device_stats *stats = &dev->stats; | |
420 | u16 status, isrc; | |
421 | ||
cfbf7586 | 422 | if ((irq == priv->tx_irq) && bfin_read(®->mbtif2)) { |
bbb84619 | 423 | /* transmission complete interrupt */ |
cfbf7586 | 424 | bfin_write(®->mbtif2, 0xFFFF); |
bbb84619 | 425 | stats->tx_packets++; |
cfbf7586 | 426 | stats->tx_bytes += bfin_read(®->chl[TRANSMIT_CHL].dlc); |
bbb84619 BS |
427 | can_get_echo_skb(dev, 0); |
428 | netif_wake_queue(dev); | |
cfbf7586 | 429 | } else if ((irq == priv->rx_irq) && bfin_read(®->mbrif1)) { |
bbb84619 | 430 | /* receive interrupt */ |
cfbf7586 MF |
431 | isrc = bfin_read(®->mbrif1); |
432 | bfin_write(®->mbrif1, 0xFFFF); | |
bbb84619 | 433 | bfin_can_rx(dev, isrc); |
cfbf7586 | 434 | } else if ((irq == priv->err_irq) && bfin_read(®->gis)) { |
bbb84619 | 435 | /* error interrupt */ |
cfbf7586 MF |
436 | isrc = bfin_read(®->gis); |
437 | status = bfin_read(®->esr); | |
438 | bfin_write(®->gis, 0x7FF); | |
bbb84619 BS |
439 | bfin_can_err(dev, isrc, status); |
440 | } else { | |
441 | return IRQ_NONE; | |
442 | } | |
443 | ||
444 | return IRQ_HANDLED; | |
445 | } | |
446 | ||
447 | static int bfin_can_open(struct net_device *dev) | |
448 | { | |
449 | struct bfin_can_priv *priv = netdev_priv(dev); | |
450 | int err; | |
451 | ||
452 | /* set chip into reset mode */ | |
453 | bfin_can_set_reset_mode(dev); | |
454 | ||
455 | /* common open */ | |
456 | err = open_candev(dev); | |
457 | if (err) | |
458 | goto exit_open; | |
459 | ||
460 | /* register interrupt handler */ | |
461 | err = request_irq(priv->rx_irq, &bfin_can_interrupt, 0, | |
462 | "bfin-can-rx", dev); | |
463 | if (err) | |
464 | goto exit_rx_irq; | |
465 | err = request_irq(priv->tx_irq, &bfin_can_interrupt, 0, | |
466 | "bfin-can-tx", dev); | |
467 | if (err) | |
468 | goto exit_tx_irq; | |
469 | err = request_irq(priv->err_irq, &bfin_can_interrupt, 0, | |
470 | "bfin-can-err", dev); | |
471 | if (err) | |
472 | goto exit_err_irq; | |
473 | ||
474 | bfin_can_start(dev); | |
475 | ||
476 | netif_start_queue(dev); | |
477 | ||
478 | return 0; | |
479 | ||
480 | exit_err_irq: | |
481 | free_irq(priv->tx_irq, dev); | |
482 | exit_tx_irq: | |
483 | free_irq(priv->rx_irq, dev); | |
484 | exit_rx_irq: | |
485 | close_candev(dev); | |
486 | exit_open: | |
487 | return err; | |
488 | } | |
489 | ||
490 | static int bfin_can_close(struct net_device *dev) | |
491 | { | |
492 | struct bfin_can_priv *priv = netdev_priv(dev); | |
493 | ||
494 | netif_stop_queue(dev); | |
495 | bfin_can_set_reset_mode(dev); | |
496 | ||
497 | close_candev(dev); | |
498 | ||
499 | free_irq(priv->rx_irq, dev); | |
500 | free_irq(priv->tx_irq, dev); | |
501 | free_irq(priv->err_irq, dev); | |
502 | ||
503 | return 0; | |
504 | } | |
505 | ||
21c11bc5 | 506 | static struct net_device *alloc_bfin_candev(void) |
bbb84619 BS |
507 | { |
508 | struct net_device *dev; | |
509 | struct bfin_can_priv *priv; | |
510 | ||
e9dcd161 | 511 | dev = alloc_candev(sizeof(*priv), TX_ECHO_SKB_MAX); |
bbb84619 BS |
512 | if (!dev) |
513 | return NULL; | |
514 | ||
515 | priv = netdev_priv(dev); | |
516 | ||
517 | priv->dev = dev; | |
518 | priv->can.bittiming_const = &bfin_can_bittiming_const; | |
519 | priv->can.do_set_bittiming = bfin_can_set_bittiming; | |
520 | priv->can.do_set_mode = bfin_can_set_mode; | |
79d0d8a7 | 521 | priv->can.do_get_berr_counter = bfin_can_get_berr_counter; |
ad72c347 | 522 | priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES; |
bbb84619 BS |
523 | |
524 | return dev; | |
525 | } | |
526 | ||
527 | static const struct net_device_ops bfin_can_netdev_ops = { | |
528 | .ndo_open = bfin_can_open, | |
529 | .ndo_stop = bfin_can_close, | |
530 | .ndo_start_xmit = bfin_can_start_xmit, | |
c971fa2a | 531 | .ndo_change_mtu = can_change_mtu, |
bbb84619 BS |
532 | }; |
533 | ||
3c8ac0f2 | 534 | static int bfin_can_probe(struct platform_device *pdev) |
bbb84619 BS |
535 | { |
536 | int err; | |
537 | struct net_device *dev; | |
538 | struct bfin_can_priv *priv; | |
539 | struct resource *res_mem, *rx_irq, *tx_irq, *err_irq; | |
540 | unsigned short *pdata; | |
541 | ||
321165c3 | 542 | pdata = dev_get_platdata(&pdev->dev); |
bbb84619 BS |
543 | if (!pdata) { |
544 | dev_err(&pdev->dev, "No platform data provided!\n"); | |
545 | err = -EINVAL; | |
546 | goto exit; | |
547 | } | |
548 | ||
549 | res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
550 | rx_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | |
551 | tx_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 1); | |
552 | err_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 2); | |
553 | if (!res_mem || !rx_irq || !tx_irq || !err_irq) { | |
554 | err = -EINVAL; | |
555 | goto exit; | |
556 | } | |
557 | ||
558 | if (!request_mem_region(res_mem->start, resource_size(res_mem), | |
559 | dev_name(&pdev->dev))) { | |
560 | err = -EBUSY; | |
561 | goto exit; | |
562 | } | |
563 | ||
564 | /* request peripheral pins */ | |
565 | err = peripheral_request_list(pdata, dev_name(&pdev->dev)); | |
566 | if (err) | |
567 | goto exit_mem_release; | |
568 | ||
569 | dev = alloc_bfin_candev(); | |
570 | if (!dev) { | |
571 | err = -ENOMEM; | |
572 | goto exit_peri_pin_free; | |
573 | } | |
574 | ||
575 | priv = netdev_priv(dev); | |
576 | priv->membase = (void __iomem *)res_mem->start; | |
577 | priv->rx_irq = rx_irq->start; | |
578 | priv->tx_irq = tx_irq->start; | |
579 | priv->err_irq = err_irq->start; | |
580 | priv->pin_list = pdata; | |
581 | priv->can.clock.freq = get_sclk(); | |
582 | ||
00e4bbc8 | 583 | platform_set_drvdata(pdev, dev); |
bbb84619 BS |
584 | SET_NETDEV_DEV(dev, &pdev->dev); |
585 | ||
586 | dev->flags |= IFF_ECHO; /* we support local echo */ | |
587 | dev->netdev_ops = &bfin_can_netdev_ops; | |
588 | ||
589 | bfin_can_set_reset_mode(dev); | |
590 | ||
591 | err = register_candev(dev); | |
592 | if (err) { | |
593 | dev_err(&pdev->dev, "registering failed (err=%d)\n", err); | |
594 | goto exit_candev_free; | |
595 | } | |
596 | ||
597 | dev_info(&pdev->dev, | |
598 | "%s device registered" | |
599 | "(®_base=%p, rx_irq=%d, tx_irq=%d, err_irq=%d, sclk=%d)\n", | |
c2fd03a0 | 600 | DRV_NAME, priv->membase, priv->rx_irq, |
bbb84619 BS |
601 | priv->tx_irq, priv->err_irq, priv->can.clock.freq); |
602 | return 0; | |
603 | ||
604 | exit_candev_free: | |
605 | free_candev(dev); | |
606 | exit_peri_pin_free: | |
607 | peripheral_free_list(pdata); | |
608 | exit_mem_release: | |
609 | release_mem_region(res_mem->start, resource_size(res_mem)); | |
610 | exit: | |
611 | return err; | |
612 | } | |
613 | ||
3c8ac0f2 | 614 | static int bfin_can_remove(struct platform_device *pdev) |
bbb84619 | 615 | { |
00e4bbc8 | 616 | struct net_device *dev = platform_get_drvdata(pdev); |
bbb84619 BS |
617 | struct bfin_can_priv *priv = netdev_priv(dev); |
618 | struct resource *res; | |
619 | ||
620 | bfin_can_set_reset_mode(dev); | |
621 | ||
622 | unregister_candev(dev); | |
623 | ||
bbb84619 BS |
624 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
625 | release_mem_region(res->start, resource_size(res)); | |
626 | ||
627 | peripheral_free_list(priv->pin_list); | |
628 | ||
629 | free_candev(dev); | |
630 | return 0; | |
631 | } | |
632 | ||
633 | #ifdef CONFIG_PM | |
634 | static int bfin_can_suspend(struct platform_device *pdev, pm_message_t mesg) | |
635 | { | |
00e4bbc8 | 636 | struct net_device *dev = platform_get_drvdata(pdev); |
bbb84619 BS |
637 | struct bfin_can_priv *priv = netdev_priv(dev); |
638 | struct bfin_can_regs __iomem *reg = priv->membase; | |
639 | int timeout = BFIN_CAN_TIMEOUT; | |
640 | ||
641 | if (netif_running(dev)) { | |
642 | /* enter sleep mode */ | |
cfbf7586 | 643 | bfin_write(®->control, bfin_read(®->control) | SMR); |
bbb84619 | 644 | SSYNC(); |
cfbf7586 | 645 | while (!(bfin_read(®->intr) & SMACK)) { |
bbb84619 BS |
646 | udelay(10); |
647 | if (--timeout == 0) { | |
aabdfd6a | 648 | netdev_err(dev, "fail to enter sleep mode\n"); |
bbb84619 BS |
649 | BUG(); |
650 | } | |
651 | } | |
652 | } | |
653 | ||
654 | return 0; | |
655 | } | |
656 | ||
657 | static int bfin_can_resume(struct platform_device *pdev) | |
658 | { | |
00e4bbc8 | 659 | struct net_device *dev = platform_get_drvdata(pdev); |
bbb84619 BS |
660 | struct bfin_can_priv *priv = netdev_priv(dev); |
661 | struct bfin_can_regs __iomem *reg = priv->membase; | |
662 | ||
663 | if (netif_running(dev)) { | |
664 | /* leave sleep mode */ | |
cfbf7586 | 665 | bfin_write(®->intr, 0); |
bbb84619 BS |
666 | SSYNC(); |
667 | } | |
668 | ||
669 | return 0; | |
670 | } | |
671 | #else | |
672 | #define bfin_can_suspend NULL | |
673 | #define bfin_can_resume NULL | |
674 | #endif /* CONFIG_PM */ | |
675 | ||
676 | static struct platform_driver bfin_can_driver = { | |
677 | .probe = bfin_can_probe, | |
3c8ac0f2 | 678 | .remove = bfin_can_remove, |
bbb84619 BS |
679 | .suspend = bfin_can_suspend, |
680 | .resume = bfin_can_resume, | |
681 | .driver = { | |
682 | .name = DRV_NAME, | |
683 | .owner = THIS_MODULE, | |
684 | }, | |
685 | }; | |
686 | ||
871d3372 | 687 | module_platform_driver(bfin_can_driver); |
bbb84619 BS |
688 | |
689 | MODULE_AUTHOR("Barry Song <21cnbao@gmail.com>"); | |
690 | MODULE_LICENSE("GPL"); | |
691 | MODULE_DESCRIPTION("Blackfin on-chip CAN netdevice driver"); | |
73ae9499 | 692 | MODULE_ALIAS("platform:" DRV_NAME); |