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881ff67a BS |
1 | /* |
2 | * CAN bus driver for Bosch C_CAN controller | |
3 | * | |
4 | * Copyright (C) 2010 ST Microelectronics | |
5 | * Bhupesh Sharma <bhupesh.sharma@st.com> | |
6 | * | |
7 | * Borrowed heavily from the C_CAN driver originally written by: | |
8 | * Copyright (C) 2007 | |
9 | * - Sascha Hauer, Marc Kleine-Budde, Pengutronix <s.hauer@pengutronix.de> | |
10 | * - Simon Kallweit, intefo AG <simon.kallweit@intefo.ch> | |
11 | * | |
12 | * TX and RX NAPI implementation has been borrowed from at91 CAN driver | |
13 | * written by: | |
14 | * Copyright | |
15 | * (C) 2007 by Hans J. Koch <hjk@hansjkoch.de> | |
16 | * (C) 2008, 2009 by Marc Kleine-Budde <kernel@pengutronix.de> | |
17 | * | |
18 | * Bosch C_CAN controller is compliant to CAN protocol version 2.0 part A and B. | |
19 | * Bosch C_CAN user manual can be obtained from: | |
20 | * http://www.semiconductors.bosch.de/media/en/pdf/ipmodules_1/c_can/ | |
21 | * users_manual_c_can.pdf | |
22 | * | |
23 | * This file is licensed under the terms of the GNU General Public | |
24 | * License version 2. This program is licensed "as is" without any | |
25 | * warranty of any kind, whether express or implied. | |
26 | */ | |
27 | ||
28 | #include <linux/kernel.h> | |
881ff67a BS |
29 | #include <linux/module.h> |
30 | #include <linux/interrupt.h> | |
31 | #include <linux/delay.h> | |
32 | #include <linux/netdevice.h> | |
33 | #include <linux/if_arp.h> | |
34 | #include <linux/if_ether.h> | |
35 | #include <linux/list.h> | |
881ff67a | 36 | #include <linux/io.h> |
4cdd34b2 | 37 | #include <linux/pm_runtime.h> |
881ff67a BS |
38 | |
39 | #include <linux/can.h> | |
40 | #include <linux/can/dev.h> | |
41 | #include <linux/can/error.h> | |
5090f805 | 42 | #include <linux/can/led.h> |
881ff67a BS |
43 | |
44 | #include "c_can.h" | |
45 | ||
33f81009 AC |
46 | /* Number of interface registers */ |
47 | #define IF_ENUM_REG_LEN 11 | |
48 | #define C_CAN_IFACE(reg, iface) (C_CAN_IF1_##reg + (iface) * IF_ENUM_REG_LEN) | |
49 | ||
82120032 AC |
50 | /* control extension register D_CAN specific */ |
51 | #define CONTROL_EX_PDR BIT(8) | |
52 | ||
881ff67a BS |
53 | /* control register */ |
54 | #define CONTROL_TEST BIT(7) | |
55 | #define CONTROL_CCE BIT(6) | |
56 | #define CONTROL_DISABLE_AR BIT(5) | |
57 | #define CONTROL_ENABLE_AR (0 << 5) | |
58 | #define CONTROL_EIE BIT(3) | |
59 | #define CONTROL_SIE BIT(2) | |
60 | #define CONTROL_IE BIT(1) | |
61 | #define CONTROL_INIT BIT(0) | |
62 | ||
63 | /* test register */ | |
64 | #define TEST_RX BIT(7) | |
65 | #define TEST_TX1 BIT(6) | |
66 | #define TEST_TX2 BIT(5) | |
67 | #define TEST_LBACK BIT(4) | |
68 | #define TEST_SILENT BIT(3) | |
69 | #define TEST_BASIC BIT(2) | |
70 | ||
71 | /* status register */ | |
82120032 | 72 | #define STATUS_PDA BIT(10) |
881ff67a BS |
73 | #define STATUS_BOFF BIT(7) |
74 | #define STATUS_EWARN BIT(6) | |
75 | #define STATUS_EPASS BIT(5) | |
76 | #define STATUS_RXOK BIT(4) | |
77 | #define STATUS_TXOK BIT(3) | |
78 | ||
79 | /* error counter register */ | |
80 | #define ERR_CNT_TEC_MASK 0xff | |
81 | #define ERR_CNT_TEC_SHIFT 0 | |
82 | #define ERR_CNT_REC_SHIFT 8 | |
83 | #define ERR_CNT_REC_MASK (0x7f << ERR_CNT_REC_SHIFT) | |
84 | #define ERR_CNT_RP_SHIFT 15 | |
85 | #define ERR_CNT_RP_MASK (0x1 << ERR_CNT_RP_SHIFT) | |
86 | ||
87 | /* bit-timing register */ | |
88 | #define BTR_BRP_MASK 0x3f | |
89 | #define BTR_BRP_SHIFT 0 | |
90 | #define BTR_SJW_SHIFT 6 | |
91 | #define BTR_SJW_MASK (0x3 << BTR_SJW_SHIFT) | |
92 | #define BTR_TSEG1_SHIFT 8 | |
93 | #define BTR_TSEG1_MASK (0xf << BTR_TSEG1_SHIFT) | |
94 | #define BTR_TSEG2_SHIFT 12 | |
95 | #define BTR_TSEG2_MASK (0x7 << BTR_TSEG2_SHIFT) | |
96 | ||
97 | /* brp extension register */ | |
98 | #define BRP_EXT_BRPE_MASK 0x0f | |
99 | #define BRP_EXT_BRPE_SHIFT 0 | |
100 | ||
101 | /* IFx command request */ | |
102 | #define IF_COMR_BUSY BIT(15) | |
103 | ||
104 | /* IFx command mask */ | |
105 | #define IF_COMM_WR BIT(7) | |
106 | #define IF_COMM_MASK BIT(6) | |
107 | #define IF_COMM_ARB BIT(5) | |
108 | #define IF_COMM_CONTROL BIT(4) | |
109 | #define IF_COMM_CLR_INT_PND BIT(3) | |
110 | #define IF_COMM_TXRQST BIT(2) | |
111 | #define IF_COMM_DATAA BIT(1) | |
112 | #define IF_COMM_DATAB BIT(0) | |
113 | #define IF_COMM_ALL (IF_COMM_MASK | IF_COMM_ARB | \ | |
114 | IF_COMM_CONTROL | IF_COMM_TXRQST | \ | |
115 | IF_COMM_DATAA | IF_COMM_DATAB) | |
116 | ||
117 | /* IFx arbitration */ | |
118 | #define IF_ARB_MSGVAL BIT(15) | |
119 | #define IF_ARB_MSGXTD BIT(14) | |
120 | #define IF_ARB_TRANSMIT BIT(13) | |
121 | ||
122 | /* IFx message control */ | |
123 | #define IF_MCONT_NEWDAT BIT(15) | |
124 | #define IF_MCONT_MSGLST BIT(14) | |
125 | #define IF_MCONT_CLR_MSGLST (0 << 14) | |
126 | #define IF_MCONT_INTPND BIT(13) | |
127 | #define IF_MCONT_UMASK BIT(12) | |
128 | #define IF_MCONT_TXIE BIT(11) | |
129 | #define IF_MCONT_RXIE BIT(10) | |
130 | #define IF_MCONT_RMTEN BIT(9) | |
131 | #define IF_MCONT_TXRQST BIT(8) | |
132 | #define IF_MCONT_EOB BIT(7) | |
133 | #define IF_MCONT_DLC_MASK 0xf | |
134 | ||
135 | /* | |
136 | * IFx register masks: | |
137 | * allow easy operation on 16-bit registers when the | |
138 | * argument is 32-bit instead | |
139 | */ | |
140 | #define IFX_WRITE_LOW_16BIT(x) ((x) & 0xFFFF) | |
141 | #define IFX_WRITE_HIGH_16BIT(x) (((x) & 0xFFFF0000) >> 16) | |
142 | ||
143 | /* message object split */ | |
144 | #define C_CAN_NO_OF_OBJECTS 32 | |
145 | #define C_CAN_MSG_OBJ_RX_NUM 16 | |
146 | #define C_CAN_MSG_OBJ_TX_NUM 16 | |
147 | ||
148 | #define C_CAN_MSG_OBJ_RX_FIRST 1 | |
149 | #define C_CAN_MSG_OBJ_RX_LAST (C_CAN_MSG_OBJ_RX_FIRST + \ | |
150 | C_CAN_MSG_OBJ_RX_NUM - 1) | |
151 | ||
152 | #define C_CAN_MSG_OBJ_TX_FIRST (C_CAN_MSG_OBJ_RX_LAST + 1) | |
153 | #define C_CAN_MSG_OBJ_TX_LAST (C_CAN_MSG_OBJ_TX_FIRST + \ | |
154 | C_CAN_MSG_OBJ_TX_NUM - 1) | |
155 | ||
156 | #define C_CAN_MSG_OBJ_RX_SPLIT 9 | |
157 | #define C_CAN_MSG_RX_LOW_LAST (C_CAN_MSG_OBJ_RX_SPLIT - 1) | |
158 | ||
159 | #define C_CAN_NEXT_MSG_OBJ_MASK (C_CAN_MSG_OBJ_TX_NUM - 1) | |
160 | #define RECEIVE_OBJECT_BITS 0x0000ffff | |
161 | ||
162 | /* status interrupt */ | |
163 | #define STATUS_INTERRUPT 0x8000 | |
164 | ||
165 | /* global interrupt masks */ | |
166 | #define ENABLE_ALL_INTERRUPTS 1 | |
167 | #define DISABLE_ALL_INTERRUPTS 0 | |
168 | ||
169 | /* minimum timeout for checking BUSY status */ | |
170 | #define MIN_TIMEOUT_VALUE 6 | |
171 | ||
82120032 AC |
172 | /* Wait for ~1 sec for INIT bit */ |
173 | #define INIT_WAIT_MS 1000 | |
174 | ||
881ff67a BS |
175 | /* napi related */ |
176 | #define C_CAN_NAPI_WEIGHT C_CAN_MSG_OBJ_RX_NUM | |
177 | ||
178 | /* c_can lec values */ | |
179 | enum c_can_lec_type { | |
180 | LEC_NO_ERROR = 0, | |
181 | LEC_STUFF_ERROR, | |
182 | LEC_FORM_ERROR, | |
183 | LEC_ACK_ERROR, | |
184 | LEC_BIT1_ERROR, | |
185 | LEC_BIT0_ERROR, | |
186 | LEC_CRC_ERROR, | |
187 | LEC_UNUSED, | |
188 | }; | |
189 | ||
190 | /* | |
191 | * c_can error types: | |
192 | * Bus errors (BUS_OFF, ERROR_WARNING, ERROR_PASSIVE) are supported | |
193 | */ | |
194 | enum c_can_bus_error_types { | |
195 | C_CAN_NO_ERROR = 0, | |
196 | C_CAN_BUS_OFF, | |
197 | C_CAN_ERROR_WARNING, | |
198 | C_CAN_ERROR_PASSIVE, | |
199 | }; | |
200 | ||
194b9a4c | 201 | static const struct can_bittiming_const c_can_bittiming_const = { |
881ff67a BS |
202 | .name = KBUILD_MODNAME, |
203 | .tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */ | |
204 | .tseg1_max = 16, | |
205 | .tseg2_min = 1, /* Time segment 2 = phase_seg2 */ | |
206 | .tseg2_max = 8, | |
207 | .sjw_max = 4, | |
208 | .brp_min = 1, | |
209 | .brp_max = 1024, /* 6-bit BRP field + 4-bit BRPE field*/ | |
210 | .brp_inc = 1, | |
211 | }; | |
212 | ||
4cdd34b2 AC |
213 | static inline void c_can_pm_runtime_enable(const struct c_can_priv *priv) |
214 | { | |
215 | if (priv->device) | |
216 | pm_runtime_enable(priv->device); | |
217 | } | |
218 | ||
219 | static inline void c_can_pm_runtime_disable(const struct c_can_priv *priv) | |
220 | { | |
221 | if (priv->device) | |
222 | pm_runtime_disable(priv->device); | |
223 | } | |
224 | ||
225 | static inline void c_can_pm_runtime_get_sync(const struct c_can_priv *priv) | |
226 | { | |
227 | if (priv->device) | |
228 | pm_runtime_get_sync(priv->device); | |
229 | } | |
230 | ||
231 | static inline void c_can_pm_runtime_put_sync(const struct c_can_priv *priv) | |
232 | { | |
233 | if (priv->device) | |
234 | pm_runtime_put_sync(priv->device); | |
235 | } | |
236 | ||
52cde85a AC |
237 | static inline void c_can_reset_ram(const struct c_can_priv *priv, bool enable) |
238 | { | |
239 | if (priv->raminit) | |
240 | priv->raminit(priv, enable); | |
241 | } | |
242 | ||
881ff67a BS |
243 | static inline int get_tx_next_msg_obj(const struct c_can_priv *priv) |
244 | { | |
245 | return (priv->tx_next & C_CAN_NEXT_MSG_OBJ_MASK) + | |
246 | C_CAN_MSG_OBJ_TX_FIRST; | |
247 | } | |
248 | ||
249 | static inline int get_tx_echo_msg_obj(const struct c_can_priv *priv) | |
250 | { | |
251 | return (priv->tx_echo & C_CAN_NEXT_MSG_OBJ_MASK) + | |
252 | C_CAN_MSG_OBJ_TX_FIRST; | |
253 | } | |
254 | ||
33f81009 | 255 | static u32 c_can_read_reg32(struct c_can_priv *priv, enum reg index) |
881ff67a | 256 | { |
33f81009 AC |
257 | u32 val = priv->read_reg(priv, index); |
258 | val |= ((u32) priv->read_reg(priv, index + 1)) << 16; | |
881ff67a BS |
259 | return val; |
260 | } | |
261 | ||
262 | static void c_can_enable_all_interrupts(struct c_can_priv *priv, | |
263 | int enable) | |
264 | { | |
265 | unsigned int cntrl_save = priv->read_reg(priv, | |
33f81009 | 266 | C_CAN_CTRL_REG); |
881ff67a BS |
267 | |
268 | if (enable) | |
269 | cntrl_save |= (CONTROL_SIE | CONTROL_EIE | CONTROL_IE); | |
270 | else | |
271 | cntrl_save &= ~(CONTROL_EIE | CONTROL_IE | CONTROL_SIE); | |
272 | ||
33f81009 | 273 | priv->write_reg(priv, C_CAN_CTRL_REG, cntrl_save); |
881ff67a BS |
274 | } |
275 | ||
276 | static inline int c_can_msg_obj_is_busy(struct c_can_priv *priv, int iface) | |
277 | { | |
278 | int count = MIN_TIMEOUT_VALUE; | |
279 | ||
280 | while (count && priv->read_reg(priv, | |
33f81009 | 281 | C_CAN_IFACE(COMREQ_REG, iface)) & |
881ff67a BS |
282 | IF_COMR_BUSY) { |
283 | count--; | |
284 | udelay(1); | |
285 | } | |
286 | ||
287 | if (!count) | |
288 | return 1; | |
289 | ||
290 | return 0; | |
291 | } | |
292 | ||
293 | static inline void c_can_object_get(struct net_device *dev, | |
294 | int iface, int objno, int mask) | |
295 | { | |
296 | struct c_can_priv *priv = netdev_priv(dev); | |
297 | ||
298 | /* | |
299 | * As per specs, after writting the message object number in the | |
300 | * IF command request register the transfer b/w interface | |
301 | * register and message RAM must be complete in 6 CAN-CLK | |
302 | * period. | |
303 | */ | |
33f81009 | 304 | priv->write_reg(priv, C_CAN_IFACE(COMMSK_REG, iface), |
881ff67a | 305 | IFX_WRITE_LOW_16BIT(mask)); |
33f81009 | 306 | priv->write_reg(priv, C_CAN_IFACE(COMREQ_REG, iface), |
881ff67a BS |
307 | IFX_WRITE_LOW_16BIT(objno)); |
308 | ||
309 | if (c_can_msg_obj_is_busy(priv, iface)) | |
310 | netdev_err(dev, "timed out in object get\n"); | |
311 | } | |
312 | ||
313 | static inline void c_can_object_put(struct net_device *dev, | |
314 | int iface, int objno, int mask) | |
315 | { | |
316 | struct c_can_priv *priv = netdev_priv(dev); | |
317 | ||
318 | /* | |
319 | * As per specs, after writting the message object number in the | |
320 | * IF command request register the transfer b/w interface | |
321 | * register and message RAM must be complete in 6 CAN-CLK | |
322 | * period. | |
323 | */ | |
33f81009 | 324 | priv->write_reg(priv, C_CAN_IFACE(COMMSK_REG, iface), |
881ff67a | 325 | (IF_COMM_WR | IFX_WRITE_LOW_16BIT(mask))); |
33f81009 | 326 | priv->write_reg(priv, C_CAN_IFACE(COMREQ_REG, iface), |
881ff67a BS |
327 | IFX_WRITE_LOW_16BIT(objno)); |
328 | ||
329 | if (c_can_msg_obj_is_busy(priv, iface)) | |
330 | netdev_err(dev, "timed out in object put\n"); | |
331 | } | |
332 | ||
333 | static void c_can_write_msg_object(struct net_device *dev, | |
334 | int iface, struct can_frame *frame, int objno) | |
335 | { | |
336 | int i; | |
337 | u16 flags = 0; | |
338 | unsigned int id; | |
339 | struct c_can_priv *priv = netdev_priv(dev); | |
340 | ||
341 | if (!(frame->can_id & CAN_RTR_FLAG)) | |
342 | flags |= IF_ARB_TRANSMIT; | |
343 | ||
344 | if (frame->can_id & CAN_EFF_FLAG) { | |
345 | id = frame->can_id & CAN_EFF_MASK; | |
346 | flags |= IF_ARB_MSGXTD; | |
347 | } else | |
348 | id = ((frame->can_id & CAN_SFF_MASK) << 18); | |
349 | ||
350 | flags |= IF_ARB_MSGVAL; | |
351 | ||
33f81009 | 352 | priv->write_reg(priv, C_CAN_IFACE(ARB1_REG, iface), |
881ff67a | 353 | IFX_WRITE_LOW_16BIT(id)); |
33f81009 | 354 | priv->write_reg(priv, C_CAN_IFACE(ARB2_REG, iface), flags | |
881ff67a BS |
355 | IFX_WRITE_HIGH_16BIT(id)); |
356 | ||
357 | for (i = 0; i < frame->can_dlc; i += 2) { | |
33f81009 | 358 | priv->write_reg(priv, C_CAN_IFACE(DATA1_REG, iface) + i / 2, |
881ff67a BS |
359 | frame->data[i] | (frame->data[i + 1] << 8)); |
360 | } | |
361 | ||
362 | /* enable interrupt for this message object */ | |
33f81009 | 363 | priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), |
881ff67a BS |
364 | IF_MCONT_TXIE | IF_MCONT_TXRQST | IF_MCONT_EOB | |
365 | frame->can_dlc); | |
366 | c_can_object_put(dev, iface, objno, IF_COMM_ALL); | |
367 | } | |
368 | ||
369 | static inline void c_can_mark_rx_msg_obj(struct net_device *dev, | |
370 | int iface, int ctrl_mask, | |
371 | int obj) | |
372 | { | |
373 | struct c_can_priv *priv = netdev_priv(dev); | |
374 | ||
33f81009 | 375 | priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), |
881ff67a BS |
376 | ctrl_mask & ~(IF_MCONT_MSGLST | IF_MCONT_INTPND)); |
377 | c_can_object_put(dev, iface, obj, IF_COMM_CONTROL); | |
378 | ||
379 | } | |
380 | ||
381 | static inline void c_can_activate_all_lower_rx_msg_obj(struct net_device *dev, | |
382 | int iface, | |
383 | int ctrl_mask) | |
384 | { | |
385 | int i; | |
386 | struct c_can_priv *priv = netdev_priv(dev); | |
387 | ||
388 | for (i = C_CAN_MSG_OBJ_RX_FIRST; i <= C_CAN_MSG_RX_LOW_LAST; i++) { | |
33f81009 | 389 | priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), |
881ff67a BS |
390 | ctrl_mask & ~(IF_MCONT_MSGLST | |
391 | IF_MCONT_INTPND | IF_MCONT_NEWDAT)); | |
392 | c_can_object_put(dev, iface, i, IF_COMM_CONTROL); | |
393 | } | |
394 | } | |
395 | ||
396 | static inline void c_can_activate_rx_msg_obj(struct net_device *dev, | |
397 | int iface, int ctrl_mask, | |
398 | int obj) | |
399 | { | |
400 | struct c_can_priv *priv = netdev_priv(dev); | |
401 | ||
33f81009 | 402 | priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), |
881ff67a BS |
403 | ctrl_mask & ~(IF_MCONT_MSGLST | |
404 | IF_MCONT_INTPND | IF_MCONT_NEWDAT)); | |
405 | c_can_object_put(dev, iface, obj, IF_COMM_CONTROL); | |
406 | } | |
407 | ||
408 | static void c_can_handle_lost_msg_obj(struct net_device *dev, | |
409 | int iface, int objno) | |
410 | { | |
411 | struct c_can_priv *priv = netdev_priv(dev); | |
412 | struct net_device_stats *stats = &dev->stats; | |
413 | struct sk_buff *skb; | |
414 | struct can_frame *frame; | |
415 | ||
416 | netdev_err(dev, "msg lost in buffer %d\n", objno); | |
417 | ||
418 | c_can_object_get(dev, iface, objno, IF_COMM_ALL & ~IF_COMM_TXRQST); | |
419 | ||
33f81009 | 420 | priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), |
881ff67a BS |
421 | IF_MCONT_CLR_MSGLST); |
422 | ||
423 | c_can_object_put(dev, 0, objno, IF_COMM_CONTROL); | |
424 | ||
425 | /* create an error msg */ | |
426 | skb = alloc_can_err_skb(dev, &frame); | |
427 | if (unlikely(!skb)) | |
428 | return; | |
429 | ||
430 | frame->can_id |= CAN_ERR_CRTL; | |
431 | frame->data[1] = CAN_ERR_CRTL_RX_OVERFLOW; | |
432 | stats->rx_errors++; | |
433 | stats->rx_over_errors++; | |
434 | ||
435 | netif_receive_skb(skb); | |
436 | } | |
437 | ||
438 | static int c_can_read_msg_object(struct net_device *dev, int iface, int ctrl) | |
439 | { | |
440 | u16 flags, data; | |
441 | int i; | |
442 | unsigned int val; | |
443 | struct c_can_priv *priv = netdev_priv(dev); | |
444 | struct net_device_stats *stats = &dev->stats; | |
445 | struct sk_buff *skb; | |
446 | struct can_frame *frame; | |
447 | ||
448 | skb = alloc_can_skb(dev, &frame); | |
449 | if (!skb) { | |
450 | stats->rx_dropped++; | |
451 | return -ENOMEM; | |
452 | } | |
453 | ||
454 | frame->can_dlc = get_can_dlc(ctrl & 0x0F); | |
455 | ||
33f81009 AC |
456 | flags = priv->read_reg(priv, C_CAN_IFACE(ARB2_REG, iface)); |
457 | val = priv->read_reg(priv, C_CAN_IFACE(ARB1_REG, iface)) | | |
881ff67a BS |
458 | (flags << 16); |
459 | ||
460 | if (flags & IF_ARB_MSGXTD) | |
461 | frame->can_id = (val & CAN_EFF_MASK) | CAN_EFF_FLAG; | |
462 | else | |
463 | frame->can_id = (val >> 18) & CAN_SFF_MASK; | |
464 | ||
465 | if (flags & IF_ARB_TRANSMIT) | |
466 | frame->can_id |= CAN_RTR_FLAG; | |
467 | else { | |
468 | for (i = 0; i < frame->can_dlc; i += 2) { | |
469 | data = priv->read_reg(priv, | |
33f81009 | 470 | C_CAN_IFACE(DATA1_REG, iface) + i / 2); |
881ff67a BS |
471 | frame->data[i] = data; |
472 | frame->data[i + 1] = data >> 8; | |
473 | } | |
474 | } | |
475 | ||
476 | netif_receive_skb(skb); | |
477 | ||
478 | stats->rx_packets++; | |
479 | stats->rx_bytes += frame->can_dlc; | |
480 | ||
5090f805 FB |
481 | can_led_event(dev, CAN_LED_EVENT_RX); |
482 | ||
881ff67a BS |
483 | return 0; |
484 | } | |
485 | ||
486 | static void c_can_setup_receive_object(struct net_device *dev, int iface, | |
487 | int objno, unsigned int mask, | |
488 | unsigned int id, unsigned int mcont) | |
489 | { | |
490 | struct c_can_priv *priv = netdev_priv(dev); | |
491 | ||
33f81009 | 492 | priv->write_reg(priv, C_CAN_IFACE(MASK1_REG, iface), |
881ff67a | 493 | IFX_WRITE_LOW_16BIT(mask)); |
2bd3bc4e AS |
494 | |
495 | /* According to C_CAN documentation, the reserved bit | |
496 | * in IFx_MASK2 register is fixed 1 | |
497 | */ | |
33f81009 | 498 | priv->write_reg(priv, C_CAN_IFACE(MASK2_REG, iface), |
2bd3bc4e | 499 | IFX_WRITE_HIGH_16BIT(mask) | BIT(13)); |
881ff67a | 500 | |
33f81009 | 501 | priv->write_reg(priv, C_CAN_IFACE(ARB1_REG, iface), |
881ff67a | 502 | IFX_WRITE_LOW_16BIT(id)); |
33f81009 | 503 | priv->write_reg(priv, C_CAN_IFACE(ARB2_REG, iface), |
881ff67a BS |
504 | (IF_ARB_MSGVAL | IFX_WRITE_HIGH_16BIT(id))); |
505 | ||
33f81009 | 506 | priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), mcont); |
881ff67a BS |
507 | c_can_object_put(dev, iface, objno, IF_COMM_ALL & ~IF_COMM_TXRQST); |
508 | ||
509 | netdev_dbg(dev, "obj no:%d, msgval:0x%08x\n", objno, | |
33f81009 | 510 | c_can_read_reg32(priv, C_CAN_MSGVAL1_REG)); |
881ff67a BS |
511 | } |
512 | ||
513 | static void c_can_inval_msg_object(struct net_device *dev, int iface, int objno) | |
514 | { | |
515 | struct c_can_priv *priv = netdev_priv(dev); | |
516 | ||
33f81009 AC |
517 | priv->write_reg(priv, C_CAN_IFACE(ARB1_REG, iface), 0); |
518 | priv->write_reg(priv, C_CAN_IFACE(ARB2_REG, iface), 0); | |
519 | priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), 0); | |
881ff67a BS |
520 | |
521 | c_can_object_put(dev, iface, objno, IF_COMM_ARB | IF_COMM_CONTROL); | |
522 | ||
523 | netdev_dbg(dev, "obj no:%d, msgval:0x%08x\n", objno, | |
33f81009 | 524 | c_can_read_reg32(priv, C_CAN_MSGVAL1_REG)); |
881ff67a BS |
525 | } |
526 | ||
527 | static inline int c_can_is_next_tx_obj_busy(struct c_can_priv *priv, int objno) | |
528 | { | |
33f81009 | 529 | int val = c_can_read_reg32(priv, C_CAN_TXRQST1_REG); |
881ff67a BS |
530 | |
531 | /* | |
532 | * as transmission request register's bit n-1 corresponds to | |
533 | * message object n, we need to handle the same properly. | |
534 | */ | |
535 | if (val & (1 << (objno - 1))) | |
536 | return 1; | |
537 | ||
538 | return 0; | |
539 | } | |
540 | ||
541 | static netdev_tx_t c_can_start_xmit(struct sk_buff *skb, | |
542 | struct net_device *dev) | |
543 | { | |
544 | u32 msg_obj_no; | |
545 | struct c_can_priv *priv = netdev_priv(dev); | |
546 | struct can_frame *frame = (struct can_frame *)skb->data; | |
547 | ||
548 | if (can_dropped_invalid_skb(dev, skb)) | |
549 | return NETDEV_TX_OK; | |
550 | ||
551 | msg_obj_no = get_tx_next_msg_obj(priv); | |
552 | ||
553 | /* prepare message object for transmission */ | |
554 | c_can_write_msg_object(dev, 0, frame, msg_obj_no); | |
555 | can_put_echo_skb(skb, dev, msg_obj_no - C_CAN_MSG_OBJ_TX_FIRST); | |
556 | ||
557 | /* | |
558 | * we have to stop the queue in case of a wrap around or | |
559 | * if the next TX message object is still in use | |
560 | */ | |
561 | priv->tx_next++; | |
562 | if (c_can_is_next_tx_obj_busy(priv, get_tx_next_msg_obj(priv)) || | |
563 | (priv->tx_next & C_CAN_NEXT_MSG_OBJ_MASK) == 0) | |
564 | netif_stop_queue(dev); | |
565 | ||
566 | return NETDEV_TX_OK; | |
567 | } | |
568 | ||
569 | static int c_can_set_bittiming(struct net_device *dev) | |
570 | { | |
571 | unsigned int reg_btr, reg_brpe, ctrl_save; | |
572 | u8 brp, brpe, sjw, tseg1, tseg2; | |
573 | u32 ten_bit_brp; | |
574 | struct c_can_priv *priv = netdev_priv(dev); | |
575 | const struct can_bittiming *bt = &priv->can.bittiming; | |
576 | ||
577 | /* c_can provides a 6-bit brp and 4-bit brpe fields */ | |
578 | ten_bit_brp = bt->brp - 1; | |
579 | brp = ten_bit_brp & BTR_BRP_MASK; | |
580 | brpe = ten_bit_brp >> 6; | |
581 | ||
582 | sjw = bt->sjw - 1; | |
583 | tseg1 = bt->prop_seg + bt->phase_seg1 - 1; | |
584 | tseg2 = bt->phase_seg2 - 1; | |
585 | reg_btr = brp | (sjw << BTR_SJW_SHIFT) | (tseg1 << BTR_TSEG1_SHIFT) | | |
586 | (tseg2 << BTR_TSEG2_SHIFT); | |
587 | reg_brpe = brpe & BRP_EXT_BRPE_MASK; | |
588 | ||
589 | netdev_info(dev, | |
590 | "setting BTR=%04x BRPE=%04x\n", reg_btr, reg_brpe); | |
591 | ||
33f81009 AC |
592 | ctrl_save = priv->read_reg(priv, C_CAN_CTRL_REG); |
593 | priv->write_reg(priv, C_CAN_CTRL_REG, | |
881ff67a | 594 | ctrl_save | CONTROL_CCE | CONTROL_INIT); |
33f81009 AC |
595 | priv->write_reg(priv, C_CAN_BTR_REG, reg_btr); |
596 | priv->write_reg(priv, C_CAN_BRPEXT_REG, reg_brpe); | |
597 | priv->write_reg(priv, C_CAN_CTRL_REG, ctrl_save); | |
881ff67a BS |
598 | |
599 | return 0; | |
600 | } | |
601 | ||
602 | /* | |
603 | * Configure C_CAN message objects for Tx and Rx purposes: | |
604 | * C_CAN provides a total of 32 message objects that can be configured | |
605 | * either for Tx or Rx purposes. Here the first 16 message objects are used as | |
606 | * a reception FIFO. The end of reception FIFO is signified by the EoB bit | |
607 | * being SET. The remaining 16 message objects are kept aside for Tx purposes. | |
608 | * See user guide document for further details on configuring message | |
609 | * objects. | |
610 | */ | |
611 | static void c_can_configure_msg_objects(struct net_device *dev) | |
612 | { | |
613 | int i; | |
614 | ||
615 | /* first invalidate all message objects */ | |
616 | for (i = C_CAN_MSG_OBJ_RX_FIRST; i <= C_CAN_NO_OF_OBJECTS; i++) | |
617 | c_can_inval_msg_object(dev, 0, i); | |
618 | ||
619 | /* setup receive message objects */ | |
620 | for (i = C_CAN_MSG_OBJ_RX_FIRST; i < C_CAN_MSG_OBJ_RX_LAST; i++) | |
621 | c_can_setup_receive_object(dev, 0, i, 0, 0, | |
622 | (IF_MCONT_RXIE | IF_MCONT_UMASK) & ~IF_MCONT_EOB); | |
623 | ||
624 | c_can_setup_receive_object(dev, 0, C_CAN_MSG_OBJ_RX_LAST, 0, 0, | |
625 | IF_MCONT_EOB | IF_MCONT_RXIE | IF_MCONT_UMASK); | |
626 | } | |
627 | ||
628 | /* | |
629 | * Configure C_CAN chip: | |
630 | * - enable/disable auto-retransmission | |
631 | * - set operating mode | |
632 | * - configure message objects | |
633 | */ | |
634 | static void c_can_chip_config(struct net_device *dev) | |
635 | { | |
636 | struct c_can_priv *priv = netdev_priv(dev); | |
637 | ||
ee6f0988 | 638 | /* enable automatic retransmission */ |
33f81009 | 639 | priv->write_reg(priv, C_CAN_CTRL_REG, |
ee6f0988 | 640 | CONTROL_ENABLE_AR); |
881ff67a | 641 | |
d9cb9bd6 DC |
642 | if ((priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) && |
643 | (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)) { | |
881ff67a | 644 | /* loopback + silent mode : useful for hot self-test */ |
33f81009 | 645 | priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_EIE | |
881ff67a | 646 | CONTROL_SIE | CONTROL_IE | CONTROL_TEST); |
33f81009 | 647 | priv->write_reg(priv, C_CAN_TEST_REG, |
881ff67a BS |
648 | TEST_LBACK | TEST_SILENT); |
649 | } else if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) { | |
650 | /* loopback mode : useful for self-test function */ | |
33f81009 | 651 | priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_EIE | |
881ff67a | 652 | CONTROL_SIE | CONTROL_IE | CONTROL_TEST); |
33f81009 | 653 | priv->write_reg(priv, C_CAN_TEST_REG, TEST_LBACK); |
881ff67a BS |
654 | } else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) { |
655 | /* silent mode : bus-monitoring mode */ | |
33f81009 | 656 | priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_EIE | |
881ff67a | 657 | CONTROL_SIE | CONTROL_IE | CONTROL_TEST); |
33f81009 | 658 | priv->write_reg(priv, C_CAN_TEST_REG, TEST_SILENT); |
881ff67a BS |
659 | } else |
660 | /* normal mode*/ | |
33f81009 | 661 | priv->write_reg(priv, C_CAN_CTRL_REG, |
881ff67a BS |
662 | CONTROL_EIE | CONTROL_SIE | CONTROL_IE); |
663 | ||
664 | /* configure message objects */ | |
665 | c_can_configure_msg_objects(dev); | |
666 | ||
667 | /* set a `lec` value so that we can check for updates later */ | |
33f81009 | 668 | priv->write_reg(priv, C_CAN_STS_REG, LEC_UNUSED); |
881ff67a BS |
669 | |
670 | /* set bittiming params */ | |
671 | c_can_set_bittiming(dev); | |
672 | } | |
673 | ||
674 | static void c_can_start(struct net_device *dev) | |
675 | { | |
676 | struct c_can_priv *priv = netdev_priv(dev); | |
677 | ||
881ff67a BS |
678 | /* basic c_can configuration */ |
679 | c_can_chip_config(dev); | |
680 | ||
681 | priv->can.state = CAN_STATE_ERROR_ACTIVE; | |
682 | ||
683 | /* reset tx helper pointers */ | |
684 | priv->tx_next = priv->tx_echo = 0; | |
4f2d56c4 JA |
685 | |
686 | /* enable status change, error and module interrupts */ | |
687 | c_can_enable_all_interrupts(priv, ENABLE_ALL_INTERRUPTS); | |
881ff67a BS |
688 | } |
689 | ||
690 | static void c_can_stop(struct net_device *dev) | |
691 | { | |
692 | struct c_can_priv *priv = netdev_priv(dev); | |
693 | ||
694 | /* disable all interrupts */ | |
695 | c_can_enable_all_interrupts(priv, DISABLE_ALL_INTERRUPTS); | |
696 | ||
697 | /* set the state as STOPPED */ | |
698 | priv->can.state = CAN_STATE_STOPPED; | |
699 | } | |
700 | ||
701 | static int c_can_set_mode(struct net_device *dev, enum can_mode mode) | |
702 | { | |
703 | switch (mode) { | |
704 | case CAN_MODE_START: | |
705 | c_can_start(dev); | |
706 | netif_wake_queue(dev); | |
707 | break; | |
708 | default: | |
709 | return -EOPNOTSUPP; | |
710 | } | |
711 | ||
712 | return 0; | |
713 | } | |
714 | ||
715 | static int c_can_get_berr_counter(const struct net_device *dev, | |
716 | struct can_berr_counter *bec) | |
717 | { | |
718 | unsigned int reg_err_counter; | |
719 | struct c_can_priv *priv = netdev_priv(dev); | |
720 | ||
4cdd34b2 AC |
721 | c_can_pm_runtime_get_sync(priv); |
722 | ||
33f81009 | 723 | reg_err_counter = priv->read_reg(priv, C_CAN_ERR_CNT_REG); |
881ff67a BS |
724 | bec->rxerr = (reg_err_counter & ERR_CNT_REC_MASK) >> |
725 | ERR_CNT_REC_SHIFT; | |
726 | bec->txerr = reg_err_counter & ERR_CNT_TEC_MASK; | |
727 | ||
4cdd34b2 AC |
728 | c_can_pm_runtime_put_sync(priv); |
729 | ||
881ff67a BS |
730 | return 0; |
731 | } | |
732 | ||
733 | /* | |
734 | * theory of operation: | |
735 | * | |
736 | * priv->tx_echo holds the number of the oldest can_frame put for | |
737 | * transmission into the hardware, but not yet ACKed by the CAN tx | |
738 | * complete IRQ. | |
739 | * | |
740 | * We iterate from priv->tx_echo to priv->tx_next and check if the | |
741 | * packet has been transmitted, echo it back to the CAN framework. | |
617cacce | 742 | * If we discover a not yet transmitted packet, stop looking for more. |
881ff67a BS |
743 | */ |
744 | static void c_can_do_tx(struct net_device *dev) | |
745 | { | |
746 | u32 val; | |
747 | u32 msg_obj_no; | |
748 | struct c_can_priv *priv = netdev_priv(dev); | |
749 | struct net_device_stats *stats = &dev->stats; | |
750 | ||
751 | for (/* nix */; (priv->tx_next - priv->tx_echo) > 0; priv->tx_echo++) { | |
752 | msg_obj_no = get_tx_echo_msg_obj(priv); | |
33f81009 | 753 | val = c_can_read_reg32(priv, C_CAN_TXRQST1_REG); |
617cacce | 754 | if (!(val & (1 << (msg_obj_no - 1)))) { |
881ff67a BS |
755 | can_get_echo_skb(dev, |
756 | msg_obj_no - C_CAN_MSG_OBJ_TX_FIRST); | |
757 | stats->tx_bytes += priv->read_reg(priv, | |
33f81009 | 758 | C_CAN_IFACE(MSGCTRL_REG, 0)) |
881ff67a BS |
759 | & IF_MCONT_DLC_MASK; |
760 | stats->tx_packets++; | |
5090f805 | 761 | can_led_event(dev, CAN_LED_EVENT_TX); |
dc760b37 | 762 | c_can_inval_msg_object(dev, 0, msg_obj_no); |
617cacce AC |
763 | } else { |
764 | break; | |
881ff67a BS |
765 | } |
766 | } | |
767 | ||
768 | /* restart queue if wrap-up or if queue stalled on last pkt */ | |
769 | if (((priv->tx_next & C_CAN_NEXT_MSG_OBJ_MASK) != 0) || | |
770 | ((priv->tx_echo & C_CAN_NEXT_MSG_OBJ_MASK) == 0)) | |
771 | netif_wake_queue(dev); | |
772 | } | |
773 | ||
774 | /* | |
775 | * theory of operation: | |
776 | * | |
777 | * c_can core saves a received CAN message into the first free message | |
778 | * object it finds free (starting with the lowest). Bits NEWDAT and | |
779 | * INTPND are set for this message object indicating that a new message | |
780 | * has arrived. To work-around this issue, we keep two groups of message | |
781 | * objects whose partitioning is defined by C_CAN_MSG_OBJ_RX_SPLIT. | |
782 | * | |
783 | * To ensure in-order frame reception we use the following | |
784 | * approach while re-activating a message object to receive further | |
785 | * frames: | |
786 | * - if the current message object number is lower than | |
787 | * C_CAN_MSG_RX_LOW_LAST, do not clear the NEWDAT bit while clearing | |
788 | * the INTPND bit. | |
789 | * - if the current message object number is equal to | |
790 | * C_CAN_MSG_RX_LOW_LAST then clear the NEWDAT bit of all lower | |
791 | * receive message objects. | |
792 | * - if the current message object number is greater than | |
793 | * C_CAN_MSG_RX_LOW_LAST then clear the NEWDAT bit of | |
794 | * only this message object. | |
795 | */ | |
796 | static int c_can_do_rx_poll(struct net_device *dev, int quota) | |
797 | { | |
798 | u32 num_rx_pkts = 0; | |
799 | unsigned int msg_obj, msg_ctrl_save; | |
800 | struct c_can_priv *priv = netdev_priv(dev); | |
33f81009 | 801 | u32 val = c_can_read_reg32(priv, C_CAN_INTPND1_REG); |
881ff67a BS |
802 | |
803 | for (msg_obj = C_CAN_MSG_OBJ_RX_FIRST; | |
804 | msg_obj <= C_CAN_MSG_OBJ_RX_LAST && quota > 0; | |
33f81009 | 805 | val = c_can_read_reg32(priv, C_CAN_INTPND1_REG), |
881ff67a BS |
806 | msg_obj++) { |
807 | /* | |
808 | * as interrupt pending register's bit n-1 corresponds to | |
809 | * message object n, we need to handle the same properly. | |
810 | */ | |
811 | if (val & (1 << (msg_obj - 1))) { | |
812 | c_can_object_get(dev, 0, msg_obj, IF_COMM_ALL & | |
813 | ~IF_COMM_TXRQST); | |
814 | msg_ctrl_save = priv->read_reg(priv, | |
33f81009 | 815 | C_CAN_IFACE(MSGCTRL_REG, 0)); |
881ff67a BS |
816 | |
817 | if (msg_ctrl_save & IF_MCONT_EOB) | |
818 | return num_rx_pkts; | |
819 | ||
820 | if (msg_ctrl_save & IF_MCONT_MSGLST) { | |
821 | c_can_handle_lost_msg_obj(dev, 0, msg_obj); | |
822 | num_rx_pkts++; | |
823 | quota--; | |
824 | continue; | |
825 | } | |
826 | ||
827 | if (!(msg_ctrl_save & IF_MCONT_NEWDAT)) | |
828 | continue; | |
829 | ||
830 | /* read the data from the message object */ | |
831 | c_can_read_msg_object(dev, 0, msg_ctrl_save); | |
832 | ||
833 | if (msg_obj < C_CAN_MSG_RX_LOW_LAST) | |
834 | c_can_mark_rx_msg_obj(dev, 0, | |
835 | msg_ctrl_save, msg_obj); | |
836 | else if (msg_obj > C_CAN_MSG_RX_LOW_LAST) | |
837 | /* activate this msg obj */ | |
838 | c_can_activate_rx_msg_obj(dev, 0, | |
839 | msg_ctrl_save, msg_obj); | |
840 | else if (msg_obj == C_CAN_MSG_RX_LOW_LAST) | |
841 | /* activate all lower message objects */ | |
842 | c_can_activate_all_lower_rx_msg_obj(dev, | |
843 | 0, msg_ctrl_save); | |
844 | ||
845 | num_rx_pkts++; | |
846 | quota--; | |
847 | } | |
848 | } | |
849 | ||
850 | return num_rx_pkts; | |
851 | } | |
852 | ||
853 | static inline int c_can_has_and_handle_berr(struct c_can_priv *priv) | |
854 | { | |
855 | return (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) && | |
856 | (priv->current_status & LEC_UNUSED); | |
857 | } | |
858 | ||
859 | static int c_can_handle_state_change(struct net_device *dev, | |
860 | enum c_can_bus_error_types error_type) | |
861 | { | |
862 | unsigned int reg_err_counter; | |
863 | unsigned int rx_err_passive; | |
864 | struct c_can_priv *priv = netdev_priv(dev); | |
865 | struct net_device_stats *stats = &dev->stats; | |
866 | struct can_frame *cf; | |
867 | struct sk_buff *skb; | |
868 | struct can_berr_counter bec; | |
869 | ||
25985edc | 870 | /* propagate the error condition to the CAN stack */ |
881ff67a BS |
871 | skb = alloc_can_err_skb(dev, &cf); |
872 | if (unlikely(!skb)) | |
873 | return 0; | |
874 | ||
875 | c_can_get_berr_counter(dev, &bec); | |
33f81009 | 876 | reg_err_counter = priv->read_reg(priv, C_CAN_ERR_CNT_REG); |
881ff67a BS |
877 | rx_err_passive = (reg_err_counter & ERR_CNT_RP_MASK) >> |
878 | ERR_CNT_RP_SHIFT; | |
879 | ||
880 | switch (error_type) { | |
881 | case C_CAN_ERROR_WARNING: | |
882 | /* error warning state */ | |
883 | priv->can.can_stats.error_warning++; | |
884 | priv->can.state = CAN_STATE_ERROR_WARNING; | |
885 | cf->can_id |= CAN_ERR_CRTL; | |
886 | cf->data[1] = (bec.txerr > bec.rxerr) ? | |
887 | CAN_ERR_CRTL_TX_WARNING : | |
888 | CAN_ERR_CRTL_RX_WARNING; | |
889 | cf->data[6] = bec.txerr; | |
890 | cf->data[7] = bec.rxerr; | |
891 | ||
892 | break; | |
893 | case C_CAN_ERROR_PASSIVE: | |
894 | /* error passive state */ | |
895 | priv->can.can_stats.error_passive++; | |
896 | priv->can.state = CAN_STATE_ERROR_PASSIVE; | |
897 | cf->can_id |= CAN_ERR_CRTL; | |
898 | if (rx_err_passive) | |
899 | cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE; | |
900 | if (bec.txerr > 127) | |
901 | cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE; | |
902 | ||
903 | cf->data[6] = bec.txerr; | |
904 | cf->data[7] = bec.rxerr; | |
905 | break; | |
906 | case C_CAN_BUS_OFF: | |
907 | /* bus-off state */ | |
908 | priv->can.state = CAN_STATE_BUS_OFF; | |
909 | cf->can_id |= CAN_ERR_BUSOFF; | |
910 | /* | |
911 | * disable all interrupts in bus-off mode to ensure that | |
912 | * the CPU is not hogged down | |
913 | */ | |
914 | c_can_enable_all_interrupts(priv, DISABLE_ALL_INTERRUPTS); | |
915 | can_bus_off(dev); | |
916 | break; | |
917 | default: | |
918 | break; | |
919 | } | |
920 | ||
921 | netif_receive_skb(skb); | |
922 | stats->rx_packets++; | |
923 | stats->rx_bytes += cf->can_dlc; | |
924 | ||
925 | return 1; | |
926 | } | |
927 | ||
928 | static int c_can_handle_bus_err(struct net_device *dev, | |
929 | enum c_can_lec_type lec_type) | |
930 | { | |
931 | struct c_can_priv *priv = netdev_priv(dev); | |
932 | struct net_device_stats *stats = &dev->stats; | |
933 | struct can_frame *cf; | |
934 | struct sk_buff *skb; | |
935 | ||
936 | /* | |
937 | * early exit if no lec update or no error. | |
938 | * no lec update means that no CAN bus event has been detected | |
939 | * since CPU wrote 0x7 value to status reg. | |
940 | */ | |
941 | if (lec_type == LEC_UNUSED || lec_type == LEC_NO_ERROR) | |
942 | return 0; | |
943 | ||
25985edc | 944 | /* propagate the error condition to the CAN stack */ |
881ff67a BS |
945 | skb = alloc_can_err_skb(dev, &cf); |
946 | if (unlikely(!skb)) | |
947 | return 0; | |
948 | ||
949 | /* | |
950 | * check for 'last error code' which tells us the | |
951 | * type of the last error to occur on the CAN bus | |
952 | */ | |
953 | ||
954 | /* common for all type of bus errors */ | |
955 | priv->can.can_stats.bus_error++; | |
956 | stats->rx_errors++; | |
957 | cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; | |
958 | cf->data[2] |= CAN_ERR_PROT_UNSPEC; | |
959 | ||
960 | switch (lec_type) { | |
961 | case LEC_STUFF_ERROR: | |
962 | netdev_dbg(dev, "stuff error\n"); | |
963 | cf->data[2] |= CAN_ERR_PROT_STUFF; | |
964 | break; | |
965 | case LEC_FORM_ERROR: | |
966 | netdev_dbg(dev, "form error\n"); | |
967 | cf->data[2] |= CAN_ERR_PROT_FORM; | |
968 | break; | |
969 | case LEC_ACK_ERROR: | |
970 | netdev_dbg(dev, "ack error\n"); | |
6ea45886 | 971 | cf->data[3] |= (CAN_ERR_PROT_LOC_ACK | |
881ff67a BS |
972 | CAN_ERR_PROT_LOC_ACK_DEL); |
973 | break; | |
974 | case LEC_BIT1_ERROR: | |
975 | netdev_dbg(dev, "bit1 error\n"); | |
976 | cf->data[2] |= CAN_ERR_PROT_BIT1; | |
977 | break; | |
978 | case LEC_BIT0_ERROR: | |
979 | netdev_dbg(dev, "bit0 error\n"); | |
980 | cf->data[2] |= CAN_ERR_PROT_BIT0; | |
981 | break; | |
982 | case LEC_CRC_ERROR: | |
983 | netdev_dbg(dev, "CRC error\n"); | |
6ea45886 | 984 | cf->data[3] |= (CAN_ERR_PROT_LOC_CRC_SEQ | |
881ff67a BS |
985 | CAN_ERR_PROT_LOC_CRC_DEL); |
986 | break; | |
987 | default: | |
988 | break; | |
989 | } | |
990 | ||
991 | /* set a `lec` value so that we can check for updates later */ | |
33f81009 | 992 | priv->write_reg(priv, C_CAN_STS_REG, LEC_UNUSED); |
881ff67a BS |
993 | |
994 | netif_receive_skb(skb); | |
995 | stats->rx_packets++; | |
996 | stats->rx_bytes += cf->can_dlc; | |
997 | ||
998 | return 1; | |
999 | } | |
1000 | ||
1001 | static int c_can_poll(struct napi_struct *napi, int quota) | |
1002 | { | |
1003 | u16 irqstatus; | |
1004 | int lec_type = 0; | |
1005 | int work_done = 0; | |
1006 | struct net_device *dev = napi->dev; | |
1007 | struct c_can_priv *priv = netdev_priv(dev); | |
1008 | ||
148c87c8 | 1009 | irqstatus = priv->irqstatus; |
881ff67a BS |
1010 | if (!irqstatus) |
1011 | goto end; | |
1012 | ||
1013 | /* status events have the highest priority */ | |
1014 | if (irqstatus == STATUS_INTERRUPT) { | |
1015 | priv->current_status = priv->read_reg(priv, | |
33f81009 | 1016 | C_CAN_STS_REG); |
881ff67a BS |
1017 | |
1018 | /* handle Tx/Rx events */ | |
1019 | if (priv->current_status & STATUS_TXOK) | |
33f81009 | 1020 | priv->write_reg(priv, C_CAN_STS_REG, |
881ff67a BS |
1021 | priv->current_status & ~STATUS_TXOK); |
1022 | ||
1023 | if (priv->current_status & STATUS_RXOK) | |
33f81009 | 1024 | priv->write_reg(priv, C_CAN_STS_REG, |
881ff67a BS |
1025 | priv->current_status & ~STATUS_RXOK); |
1026 | ||
1027 | /* handle state changes */ | |
1028 | if ((priv->current_status & STATUS_EWARN) && | |
1029 | (!(priv->last_status & STATUS_EWARN))) { | |
1030 | netdev_dbg(dev, "entered error warning state\n"); | |
1031 | work_done += c_can_handle_state_change(dev, | |
1032 | C_CAN_ERROR_WARNING); | |
1033 | } | |
1034 | if ((priv->current_status & STATUS_EPASS) && | |
1035 | (!(priv->last_status & STATUS_EPASS))) { | |
1036 | netdev_dbg(dev, "entered error passive state\n"); | |
1037 | work_done += c_can_handle_state_change(dev, | |
1038 | C_CAN_ERROR_PASSIVE); | |
1039 | } | |
1040 | if ((priv->current_status & STATUS_BOFF) && | |
1041 | (!(priv->last_status & STATUS_BOFF))) { | |
1042 | netdev_dbg(dev, "entered bus off state\n"); | |
1043 | work_done += c_can_handle_state_change(dev, | |
1044 | C_CAN_BUS_OFF); | |
1045 | } | |
1046 | ||
1047 | /* handle bus recovery events */ | |
1048 | if ((!(priv->current_status & STATUS_BOFF)) && | |
1049 | (priv->last_status & STATUS_BOFF)) { | |
1050 | netdev_dbg(dev, "left bus off state\n"); | |
1051 | priv->can.state = CAN_STATE_ERROR_ACTIVE; | |
1052 | } | |
1053 | if ((!(priv->current_status & STATUS_EPASS)) && | |
1054 | (priv->last_status & STATUS_EPASS)) { | |
1055 | netdev_dbg(dev, "left error passive state\n"); | |
1056 | priv->can.state = CAN_STATE_ERROR_ACTIVE; | |
1057 | } | |
1058 | ||
1059 | priv->last_status = priv->current_status; | |
1060 | ||
1061 | /* handle lec errors on the bus */ | |
1062 | lec_type = c_can_has_and_handle_berr(priv); | |
1063 | if (lec_type) | |
1064 | work_done += c_can_handle_bus_err(dev, lec_type); | |
1065 | } else if ((irqstatus >= C_CAN_MSG_OBJ_RX_FIRST) && | |
1066 | (irqstatus <= C_CAN_MSG_OBJ_RX_LAST)) { | |
1067 | /* handle events corresponding to receive message objects */ | |
1068 | work_done += c_can_do_rx_poll(dev, (quota - work_done)); | |
1069 | } else if ((irqstatus >= C_CAN_MSG_OBJ_TX_FIRST) && | |
1070 | (irqstatus <= C_CAN_MSG_OBJ_TX_LAST)) { | |
1071 | /* handle events corresponding to transmit message objects */ | |
1072 | c_can_do_tx(dev); | |
1073 | } | |
1074 | ||
1075 | end: | |
1076 | if (work_done < quota) { | |
1077 | napi_complete(napi); | |
1078 | /* enable all IRQs */ | |
1079 | c_can_enable_all_interrupts(priv, ENABLE_ALL_INTERRUPTS); | |
1080 | } | |
1081 | ||
1082 | return work_done; | |
1083 | } | |
1084 | ||
1085 | static irqreturn_t c_can_isr(int irq, void *dev_id) | |
1086 | { | |
881ff67a BS |
1087 | struct net_device *dev = (struct net_device *)dev_id; |
1088 | struct c_can_priv *priv = netdev_priv(dev); | |
1089 | ||
33f81009 | 1090 | priv->irqstatus = priv->read_reg(priv, C_CAN_INT_REG); |
148c87c8 | 1091 | if (!priv->irqstatus) |
881ff67a BS |
1092 | return IRQ_NONE; |
1093 | ||
1094 | /* disable all interrupts and schedule the NAPI */ | |
1095 | c_can_enable_all_interrupts(priv, DISABLE_ALL_INTERRUPTS); | |
1096 | napi_schedule(&priv->napi); | |
1097 | ||
1098 | return IRQ_HANDLED; | |
1099 | } | |
1100 | ||
1101 | static int c_can_open(struct net_device *dev) | |
1102 | { | |
1103 | int err; | |
1104 | struct c_can_priv *priv = netdev_priv(dev); | |
1105 | ||
4cdd34b2 | 1106 | c_can_pm_runtime_get_sync(priv); |
52cde85a | 1107 | c_can_reset_ram(priv, true); |
4cdd34b2 | 1108 | |
881ff67a BS |
1109 | /* open the can device */ |
1110 | err = open_candev(dev); | |
1111 | if (err) { | |
1112 | netdev_err(dev, "failed to open can device\n"); | |
4cdd34b2 | 1113 | goto exit_open_fail; |
881ff67a BS |
1114 | } |
1115 | ||
1116 | /* register interrupt handler */ | |
1117 | err = request_irq(dev->irq, &c_can_isr, IRQF_SHARED, dev->name, | |
1118 | dev); | |
1119 | if (err < 0) { | |
1120 | netdev_err(dev, "failed to request interrupt\n"); | |
1121 | goto exit_irq_fail; | |
1122 | } | |
1123 | ||
f461f27a AC |
1124 | napi_enable(&priv->napi); |
1125 | ||
5090f805 FB |
1126 | can_led_event(dev, CAN_LED_EVENT_OPEN); |
1127 | ||
881ff67a BS |
1128 | /* start the c_can controller */ |
1129 | c_can_start(dev); | |
1130 | ||
881ff67a BS |
1131 | netif_start_queue(dev); |
1132 | ||
1133 | return 0; | |
1134 | ||
1135 | exit_irq_fail: | |
1136 | close_candev(dev); | |
4cdd34b2 | 1137 | exit_open_fail: |
52cde85a | 1138 | c_can_reset_ram(priv, false); |
4cdd34b2 | 1139 | c_can_pm_runtime_put_sync(priv); |
881ff67a BS |
1140 | return err; |
1141 | } | |
1142 | ||
1143 | static int c_can_close(struct net_device *dev) | |
1144 | { | |
1145 | struct c_can_priv *priv = netdev_priv(dev); | |
1146 | ||
1147 | netif_stop_queue(dev); | |
1148 | napi_disable(&priv->napi); | |
1149 | c_can_stop(dev); | |
1150 | free_irq(dev->irq, dev); | |
1151 | close_candev(dev); | |
52cde85a AC |
1152 | |
1153 | c_can_reset_ram(priv, false); | |
4cdd34b2 | 1154 | c_can_pm_runtime_put_sync(priv); |
881ff67a | 1155 | |
5090f805 FB |
1156 | can_led_event(dev, CAN_LED_EVENT_STOP); |
1157 | ||
881ff67a BS |
1158 | return 0; |
1159 | } | |
1160 | ||
1161 | struct net_device *alloc_c_can_dev(void) | |
1162 | { | |
1163 | struct net_device *dev; | |
1164 | struct c_can_priv *priv; | |
1165 | ||
1166 | dev = alloc_candev(sizeof(struct c_can_priv), C_CAN_MSG_OBJ_TX_NUM); | |
1167 | if (!dev) | |
1168 | return NULL; | |
1169 | ||
1170 | priv = netdev_priv(dev); | |
1171 | netif_napi_add(dev, &priv->napi, c_can_poll, C_CAN_NAPI_WEIGHT); | |
1172 | ||
1173 | priv->dev = dev; | |
1174 | priv->can.bittiming_const = &c_can_bittiming_const; | |
1175 | priv->can.do_set_mode = c_can_set_mode; | |
1176 | priv->can.do_get_berr_counter = c_can_get_berr_counter; | |
ee6f0988 | 1177 | priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK | |
881ff67a BS |
1178 | CAN_CTRLMODE_LISTENONLY | |
1179 | CAN_CTRLMODE_BERR_REPORTING; | |
1180 | ||
1181 | return dev; | |
1182 | } | |
1183 | EXPORT_SYMBOL_GPL(alloc_c_can_dev); | |
1184 | ||
82120032 AC |
1185 | #ifdef CONFIG_PM |
1186 | int c_can_power_down(struct net_device *dev) | |
1187 | { | |
1188 | u32 val; | |
1189 | unsigned long time_out; | |
1190 | struct c_can_priv *priv = netdev_priv(dev); | |
1191 | ||
1192 | if (!(dev->flags & IFF_UP)) | |
1193 | return 0; | |
1194 | ||
1195 | WARN_ON(priv->type != BOSCH_D_CAN); | |
1196 | ||
1197 | /* set PDR value so the device goes to power down mode */ | |
1198 | val = priv->read_reg(priv, C_CAN_CTRL_EX_REG); | |
1199 | val |= CONTROL_EX_PDR; | |
1200 | priv->write_reg(priv, C_CAN_CTRL_EX_REG, val); | |
1201 | ||
1202 | /* Wait for the PDA bit to get set */ | |
1203 | time_out = jiffies + msecs_to_jiffies(INIT_WAIT_MS); | |
1204 | while (!(priv->read_reg(priv, C_CAN_STS_REG) & STATUS_PDA) && | |
1205 | time_after(time_out, jiffies)) | |
1206 | cpu_relax(); | |
1207 | ||
1208 | if (time_after(jiffies, time_out)) | |
1209 | return -ETIMEDOUT; | |
1210 | ||
1211 | c_can_stop(dev); | |
1212 | ||
52cde85a | 1213 | c_can_reset_ram(priv, false); |
82120032 AC |
1214 | c_can_pm_runtime_put_sync(priv); |
1215 | ||
1216 | return 0; | |
1217 | } | |
1218 | EXPORT_SYMBOL_GPL(c_can_power_down); | |
1219 | ||
1220 | int c_can_power_up(struct net_device *dev) | |
1221 | { | |
1222 | u32 val; | |
1223 | unsigned long time_out; | |
1224 | struct c_can_priv *priv = netdev_priv(dev); | |
1225 | ||
1226 | if (!(dev->flags & IFF_UP)) | |
1227 | return 0; | |
1228 | ||
1229 | WARN_ON(priv->type != BOSCH_D_CAN); | |
1230 | ||
1231 | c_can_pm_runtime_get_sync(priv); | |
52cde85a | 1232 | c_can_reset_ram(priv, true); |
82120032 AC |
1233 | |
1234 | /* Clear PDR and INIT bits */ | |
1235 | val = priv->read_reg(priv, C_CAN_CTRL_EX_REG); | |
1236 | val &= ~CONTROL_EX_PDR; | |
1237 | priv->write_reg(priv, C_CAN_CTRL_EX_REG, val); | |
1238 | val = priv->read_reg(priv, C_CAN_CTRL_REG); | |
1239 | val &= ~CONTROL_INIT; | |
1240 | priv->write_reg(priv, C_CAN_CTRL_REG, val); | |
1241 | ||
1242 | /* Wait for the PDA bit to get clear */ | |
1243 | time_out = jiffies + msecs_to_jiffies(INIT_WAIT_MS); | |
1244 | while ((priv->read_reg(priv, C_CAN_STS_REG) & STATUS_PDA) && | |
1245 | time_after(time_out, jiffies)) | |
1246 | cpu_relax(); | |
1247 | ||
1248 | if (time_after(jiffies, time_out)) | |
1249 | return -ETIMEDOUT; | |
1250 | ||
1251 | c_can_start(dev); | |
1252 | ||
1253 | return 0; | |
1254 | } | |
1255 | EXPORT_SYMBOL_GPL(c_can_power_up); | |
1256 | #endif | |
1257 | ||
881ff67a BS |
1258 | void free_c_can_dev(struct net_device *dev) |
1259 | { | |
1260 | free_candev(dev); | |
1261 | } | |
1262 | EXPORT_SYMBOL_GPL(free_c_can_dev); | |
1263 | ||
1264 | static const struct net_device_ops c_can_netdev_ops = { | |
1265 | .ndo_open = c_can_open, | |
1266 | .ndo_stop = c_can_close, | |
1267 | .ndo_start_xmit = c_can_start_xmit, | |
1268 | }; | |
1269 | ||
1270 | int register_c_can_dev(struct net_device *dev) | |
1271 | { | |
4cdd34b2 AC |
1272 | struct c_can_priv *priv = netdev_priv(dev); |
1273 | int err; | |
1274 | ||
1275 | c_can_pm_runtime_enable(priv); | |
1276 | ||
881ff67a BS |
1277 | dev->flags |= IFF_ECHO; /* we support local echo */ |
1278 | dev->netdev_ops = &c_can_netdev_ops; | |
1279 | ||
4cdd34b2 AC |
1280 | err = register_candev(dev); |
1281 | if (err) | |
1282 | c_can_pm_runtime_disable(priv); | |
5090f805 FB |
1283 | else |
1284 | devm_can_led_init(dev); | |
4cdd34b2 AC |
1285 | |
1286 | return err; | |
881ff67a BS |
1287 | } |
1288 | EXPORT_SYMBOL_GPL(register_c_can_dev); | |
1289 | ||
1290 | void unregister_c_can_dev(struct net_device *dev) | |
1291 | { | |
1292 | struct c_can_priv *priv = netdev_priv(dev); | |
1293 | ||
881ff67a | 1294 | unregister_candev(dev); |
4cdd34b2 AC |
1295 | |
1296 | c_can_pm_runtime_disable(priv); | |
881ff67a BS |
1297 | } |
1298 | EXPORT_SYMBOL_GPL(unregister_c_can_dev); | |
1299 | ||
1300 | MODULE_AUTHOR("Bhupesh Sharma <bhupesh.sharma@st.com>"); | |
1301 | MODULE_LICENSE("GPL v2"); | |
1302 | MODULE_DESCRIPTION("CAN bus driver for Bosch C_CAN controller"); |