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tcp: Reject invalid ack_seq to Fast Open sockets
[deliverable/linux.git] / drivers / net / can / flexcan.c
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e955cead
MKB		 1/*
2 * flexcan.c - FLEXCAN CAN controller driver
3 *
4 * Copyright (c) 2005-2006 Varma Electronics Oy
5 * Copyright (c) 2009 Sascha Hauer, Pengutronix
6 * Copyright (c) 2010 Marc Kleine-Budde, Pengutronix
7 *
8 * Based on code originally by Andrey Volkov <avolkov@varma-el.com>
9 *
10 * LICENCE:
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation version 2.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 */
21
22#include <linux/netdevice.h>
23#include <linux/can.h>
24#include <linux/can/dev.h>
25#include <linux/can/error.h>
26#include <linux/can/platform/flexcan.h>
27#include <linux/clk.h>
28#include <linux/delay.h>
29#include <linux/if_arp.h>
30#include <linux/if_ether.h>
31#include <linux/interrupt.h>
32#include <linux/io.h>
33#include <linux/kernel.h>
34#include <linux/list.h>
35#include <linux/module.h>
97efe9ae 36#include <linux/of.h>
30c1e672 37#include <linux/of_device.h>
e955cead 38#include <linux/platform_device.h>
a53157c2 39#include <linux/pinctrl/consumer.h>
e955cead 40
e955cead
MKB		 41#define DRV_NAME "flexcan"
42
43/* 8 for RX fifo and 2 error handling */
44#define FLEXCAN_NAPI_WEIGHT (8 + 2)
45
46/* FLEXCAN module configuration register (CANMCR) bits */
47#define FLEXCAN_MCR_MDIS BIT(31)
48#define FLEXCAN_MCR_FRZ BIT(30)
49#define FLEXCAN_MCR_FEN BIT(29)
50#define FLEXCAN_MCR_HALT BIT(28)
51#define FLEXCAN_MCR_NOT_RDY BIT(27)
52#define FLEXCAN_MCR_WAK_MSK BIT(26)
53#define FLEXCAN_MCR_SOFTRST BIT(25)
54#define FLEXCAN_MCR_FRZ_ACK BIT(24)
55#define FLEXCAN_MCR_SUPV BIT(23)
56#define FLEXCAN_MCR_SLF_WAK BIT(22)
57#define FLEXCAN_MCR_WRN_EN BIT(21)
58#define FLEXCAN_MCR_LPM_ACK BIT(20)
59#define FLEXCAN_MCR_WAK_SRC BIT(19)
60#define FLEXCAN_MCR_DOZE BIT(18)
61#define FLEXCAN_MCR_SRX_DIS BIT(17)
62#define FLEXCAN_MCR_BCC BIT(16)
63#define FLEXCAN_MCR_LPRIO_EN BIT(13)
64#define FLEXCAN_MCR_AEN BIT(12)
65#define FLEXCAN_MCR_MAXMB(x) ((x) & 0xf)
66#define FLEXCAN_MCR_IDAM_A (0 << 8)
67#define FLEXCAN_MCR_IDAM_B (1 << 8)
68#define FLEXCAN_MCR_IDAM_C (2 << 8)
69#define FLEXCAN_MCR_IDAM_D (3 << 8)
70
71/* FLEXCAN control register (CANCTRL) bits */
72#define FLEXCAN_CTRL_PRESDIV(x) (((x) & 0xff) << 24)
73#define FLEXCAN_CTRL_RJW(x) (((x) & 0x03) << 22)
74#define FLEXCAN_CTRL_PSEG1(x) (((x) & 0x07) << 19)
75#define FLEXCAN_CTRL_PSEG2(x) (((x) & 0x07) << 16)
76#define FLEXCAN_CTRL_BOFF_MSK BIT(15)
77#define FLEXCAN_CTRL_ERR_MSK BIT(14)
78#define FLEXCAN_CTRL_CLK_SRC BIT(13)
79#define FLEXCAN_CTRL_LPB BIT(12)
80#define FLEXCAN_CTRL_TWRN_MSK BIT(11)
81#define FLEXCAN_CTRL_RWRN_MSK BIT(10)
82#define FLEXCAN_CTRL_SMP BIT(7)
83#define FLEXCAN_CTRL_BOFF_REC BIT(6)
84#define FLEXCAN_CTRL_TSYN BIT(5)
85#define FLEXCAN_CTRL_LBUF BIT(4)
86#define FLEXCAN_CTRL_LOM BIT(3)
87#define FLEXCAN_CTRL_PROPSEG(x) ((x) & 0x07)
88#define FLEXCAN_CTRL_ERR_BUS (FLEXCAN_CTRL_ERR_MSK)
89#define FLEXCAN_CTRL_ERR_STATE \
90 (FLEXCAN_CTRL_TWRN_MSK | FLEXCAN_CTRL_RWRN_MSK | \
91 FLEXCAN_CTRL_BOFF_MSK)
92#define FLEXCAN_CTRL_ERR_ALL \
93 (FLEXCAN_CTRL_ERR_BUS | FLEXCAN_CTRL_ERR_STATE)
94
95/* FLEXCAN error and status register (ESR) bits */
96#define FLEXCAN_ESR_TWRN_INT BIT(17)
97#define FLEXCAN_ESR_RWRN_INT BIT(16)
98#define FLEXCAN_ESR_BIT1_ERR BIT(15)
99#define FLEXCAN_ESR_BIT0_ERR BIT(14)
100#define FLEXCAN_ESR_ACK_ERR BIT(13)
101#define FLEXCAN_ESR_CRC_ERR BIT(12)
102#define FLEXCAN_ESR_FRM_ERR BIT(11)
103#define FLEXCAN_ESR_STF_ERR BIT(10)
104#define FLEXCAN_ESR_TX_WRN BIT(9)
105#define FLEXCAN_ESR_RX_WRN BIT(8)
106#define FLEXCAN_ESR_IDLE BIT(7)
107#define FLEXCAN_ESR_TXRX BIT(6)
108#define FLEXCAN_EST_FLT_CONF_SHIFT (4)
109#define FLEXCAN_ESR_FLT_CONF_MASK (0x3 << FLEXCAN_EST_FLT_CONF_SHIFT)
110#define FLEXCAN_ESR_FLT_CONF_ACTIVE (0x0 << FLEXCAN_EST_FLT_CONF_SHIFT)
111#define FLEXCAN_ESR_FLT_CONF_PASSIVE (0x1 << FLEXCAN_EST_FLT_CONF_SHIFT)
112#define FLEXCAN_ESR_BOFF_INT BIT(2)
113#define FLEXCAN_ESR_ERR_INT BIT(1)
114#define FLEXCAN_ESR_WAK_INT BIT(0)
115#define FLEXCAN_ESR_ERR_BUS \
116 (FLEXCAN_ESR_BIT1_ERR | FLEXCAN_ESR_BIT0_ERR | \
117 FLEXCAN_ESR_ACK_ERR | FLEXCAN_ESR_CRC_ERR | \
118 FLEXCAN_ESR_FRM_ERR | FLEXCAN_ESR_STF_ERR)
119#define FLEXCAN_ESR_ERR_STATE \
120 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | FLEXCAN_ESR_BOFF_INT)
121#define FLEXCAN_ESR_ERR_ALL \
122 (FLEXCAN_ESR_ERR_BUS | FLEXCAN_ESR_ERR_STATE)
6e9d554f
WG		 123#define FLEXCAN_ESR_ALL_INT \
124 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | \
125 FLEXCAN_ESR_BOFF_INT | FLEXCAN_ESR_ERR_INT)
e955cead
MKB		 126
127/* FLEXCAN interrupt flag register (IFLAG) bits */
128#define FLEXCAN_TX_BUF_ID 8
129#define FLEXCAN_IFLAG_BUF(x) BIT(x)
130#define FLEXCAN_IFLAG_RX_FIFO_OVERFLOW BIT(7)
131#define FLEXCAN_IFLAG_RX_FIFO_WARN BIT(6)
132#define FLEXCAN_IFLAG_RX_FIFO_AVAILABLE BIT(5)
133#define FLEXCAN_IFLAG_DEFAULT \
134 (FLEXCAN_IFLAG_RX_FIFO_OVERFLOW | FLEXCAN_IFLAG_RX_FIFO_AVAILABLE | \
135 FLEXCAN_IFLAG_BUF(FLEXCAN_TX_BUF_ID))
136
137/* FLEXCAN message buffers */
138#define FLEXCAN_MB_CNT_CODE(x) (((x) & 0xf) << 24)
139#define FLEXCAN_MB_CNT_SRR BIT(22)
140#define FLEXCAN_MB_CNT_IDE BIT(21)
141#define FLEXCAN_MB_CNT_RTR BIT(20)
142#define FLEXCAN_MB_CNT_LENGTH(x) (((x) & 0xf) << 16)
143#define FLEXCAN_MB_CNT_TIMESTAMP(x) ((x) & 0xffff)
144
145#define FLEXCAN_MB_CODE_MASK (0xf0ffffff)
146
4f72e5f0
WG		 147/* FLEXCAN hardware feature flags */
148#define FLEXCAN_HAS_V10_FEATURES BIT(1) /* For core version >= 10 */
149#define FLEXCAN_HAS_BROKEN_ERR_STATE BIT(2) /* Broken error state handling */
150
e955cead
MKB		 151/* Structure of the message buffer */
152struct flexcan_mb {
153 u32 can_ctrl;
154 u32 can_id;
155 u32 data[2];
156};
157
158/* Structure of the hardware registers */
159struct flexcan_regs {
160 u32 mcr; /* 0x00 */
161 u32 ctrl; /* 0x04 */
162 u32 timer; /* 0x08 */
163 u32 _reserved1; /* 0x0c */
164 u32 rxgmask; /* 0x10 */
165 u32 rx14mask; /* 0x14 */
166 u32 rx15mask; /* 0x18 */
167 u32 ecr; /* 0x1c */
168 u32 esr; /* 0x20 */
169 u32 imask2; /* 0x24 */
170 u32 imask1; /* 0x28 */
171 u32 iflag2; /* 0x2c */
172 u32 iflag1; /* 0x30 */
30c1e672
HW		 173 u32 crl2; /* 0x34 */
174 u32 esr2; /* 0x38 */
175 u32 imeur; /* 0x3c */
176 u32 lrfr; /* 0x40 */
177 u32 crcr; /* 0x44 */
178 u32 rxfgmask; /* 0x48 */
179 u32 rxfir; /* 0x4c */
180 u32 _reserved3[12];
e955cead
MKB		 181 struct flexcan_mb cantxfg[64];
182};
183
30c1e672 184struct flexcan_devtype_data {
4f72e5f0 185 u32 features; /* hardware controller features */
30c1e672
HW		 186};
187
e955cead
MKB		 188struct flexcan_priv {
189 struct can_priv can;
190 struct net_device *dev;
191 struct napi_struct napi;
192
193 void __iomem *base;
194 u32 reg_esr;
195 u32 reg_ctrl_default;
196
3d42a379
ST		 197 struct clk *clk_ipg;
198 struct clk *clk_per;
e955cead 199 struct flexcan_platform_data *pdata;
dda0b3bd 200 const struct flexcan_devtype_data *devtype_data;
30c1e672
HW		 201};
202
203static struct flexcan_devtype_data fsl_p1010_devtype_data = {
4f72e5f0 204 .features = FLEXCAN_HAS_BROKEN_ERR_STATE,
30c1e672 205};
4f72e5f0 206static struct flexcan_devtype_data fsl_imx28_devtype_data;
30c1e672 207static struct flexcan_devtype_data fsl_imx6q_devtype_data = {
4f72e5f0 208 .features = FLEXCAN_HAS_V10_FEATURES | FLEXCAN_HAS_BROKEN_ERR_STATE,
e955cead
MKB		 209};
210
194b9a4c 211static const struct can_bittiming_const flexcan_bittiming_const = {
e955cead
MKB		 212 .name = DRV_NAME,
213 .tseg1_min = 4,
214 .tseg1_max = 16,
215 .tseg2_min = 2,
216 .tseg2_max = 8,
217 .sjw_max = 4,
218 .brp_min = 1,
219 .brp_max = 256,
220 .brp_inc = 1,
221};
222
61e271ee 223/*
224 * Abstract off the read/write for arm versus ppc.
225 */
226#if defined(__BIG_ENDIAN)
227static inline u32 flexcan_read(void __iomem *addr)
228{
229 return in_be32(addr);
230}
231
232static inline void flexcan_write(u32 val, void __iomem *addr)
233{
234 out_be32(addr, val);
235}
236#else
237static inline u32 flexcan_read(void __iomem *addr)
238{
239 return readl(addr);
240}
241
242static inline void flexcan_write(u32 val, void __iomem *addr)
243{
244 writel(val, addr);
245}
246#endif
247
e955cead
MKB		 248/*
249 * Swtich transceiver on or off
250 */
251static void flexcan_transceiver_switch(const struct flexcan_priv *priv, int on)
252{
253 if (priv->pdata && priv->pdata->transceiver_switch)
254 priv->pdata->transceiver_switch(on);
255}
256
257static inline int flexcan_has_and_handle_berr(const struct flexcan_priv *priv,
258 u32 reg_esr)
259{
260 return (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) &&
261 (reg_esr & FLEXCAN_ESR_ERR_BUS);
262}
263
264static inline void flexcan_chip_enable(struct flexcan_priv *priv)
265{
266 struct flexcan_regs __iomem *regs = priv->base;
267 u32 reg;
268
61e271ee 269 reg = flexcan_read(&regs->mcr);
e955cead 270 reg &= ~FLEXCAN_MCR_MDIS;
61e271ee 271 flexcan_write(reg, &regs->mcr);
e955cead
MKB		 272
273 udelay(10);
274}
275
276static inline void flexcan_chip_disable(struct flexcan_priv *priv)
277{
278 struct flexcan_regs __iomem *regs = priv->base;
279 u32 reg;
280
61e271ee 281 reg = flexcan_read(&regs->mcr);
e955cead 282 reg |= FLEXCAN_MCR_MDIS;
61e271ee 283 flexcan_write(reg, &regs->mcr);
e955cead
MKB		 284}
285
286static int flexcan_get_berr_counter(const struct net_device *dev,
287 struct can_berr_counter *bec)
288{
289 const struct flexcan_priv *priv = netdev_priv(dev);
290 struct flexcan_regs __iomem *regs = priv->base;
61e271ee 291 u32 reg = flexcan_read(&regs->ecr);
e955cead
MKB		 292
293 bec->txerr = (reg >> 0) & 0xff;
294 bec->rxerr = (reg >> 8) & 0xff;
295
296 return 0;
297}
298
299static int flexcan_start_xmit(struct sk_buff *skb, struct net_device *dev)
300{
301 const struct flexcan_priv *priv = netdev_priv(dev);
e955cead
MKB		 302 struct flexcan_regs __iomem *regs = priv->base;
303 struct can_frame *cf = (struct can_frame *)skb->data;
304 u32 can_id;
305 u32 ctrl = FLEXCAN_MB_CNT_CODE(0xc) | (cf->can_dlc << 16);
306
307 if (can_dropped_invalid_skb(dev, skb))
308 return NETDEV_TX_OK;
309
310 netif_stop_queue(dev);
311
312 if (cf->can_id & CAN_EFF_FLAG) {
313 can_id = cf->can_id & CAN_EFF_MASK;
314 ctrl |= FLEXCAN_MB_CNT_IDE | FLEXCAN_MB_CNT_SRR;
315 } else {
316 can_id = (cf->can_id & CAN_SFF_MASK) << 18;
317 }
318
319 if (cf->can_id & CAN_RTR_FLAG)
320 ctrl |= FLEXCAN_MB_CNT_RTR;
321
322 if (cf->can_dlc > 0) {
323 u32 data = be32_to_cpup((__be32 *)&cf->data[0]);
61e271ee 324 flexcan_write(data, &regs->cantxfg[FLEXCAN_TX_BUF_ID].data[0]);
e955cead
MKB		 325 }
326 if (cf->can_dlc > 3) {
327 u32 data = be32_to_cpup((__be32 *)&cf->data[4]);
61e271ee 328 flexcan_write(data, &regs->cantxfg[FLEXCAN_TX_BUF_ID].data[1]);
e955cead
MKB		 329 }
330
9a123496
RD		 331 can_put_echo_skb(skb, dev, 0);
332
61e271ee 333 flexcan_write(can_id, &regs->cantxfg[FLEXCAN_TX_BUF_ID].can_id);
334 flexcan_write(ctrl, &regs->cantxfg[FLEXCAN_TX_BUF_ID].can_ctrl);
e955cead 335
e955cead
MKB		 336 return NETDEV_TX_OK;
337}
338
339static void do_bus_err(struct net_device *dev,
340 struct can_frame *cf, u32 reg_esr)
341{
342 struct flexcan_priv *priv = netdev_priv(dev);
343 int rx_errors = 0, tx_errors = 0;
344
345 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
346
347 if (reg_esr & FLEXCAN_ESR_BIT1_ERR) {
aabdfd6a 348 netdev_dbg(dev, "BIT1_ERR irq\n");
e955cead
MKB		 349 cf->data[2] |= CAN_ERR_PROT_BIT1;
350 tx_errors = 1;
351 }
352 if (reg_esr & FLEXCAN_ESR_BIT0_ERR) {
aabdfd6a 353 netdev_dbg(dev, "BIT0_ERR irq\n");
e955cead
MKB		 354 cf->data[2] |= CAN_ERR_PROT_BIT0;
355 tx_errors = 1;
356 }
357 if (reg_esr & FLEXCAN_ESR_ACK_ERR) {
aabdfd6a 358 netdev_dbg(dev, "ACK_ERR irq\n");
e955cead
MKB		 359 cf->can_id |= CAN_ERR_ACK;
360 cf->data[3] |= CAN_ERR_PROT_LOC_ACK;
361 tx_errors = 1;
362 }
363 if (reg_esr & FLEXCAN_ESR_CRC_ERR) {
aabdfd6a 364 netdev_dbg(dev, "CRC_ERR irq\n");
e955cead
MKB		 365 cf->data[2] |= CAN_ERR_PROT_BIT;
366 cf->data[3] |= CAN_ERR_PROT_LOC_CRC_SEQ;
367 rx_errors = 1;
368 }
369 if (reg_esr & FLEXCAN_ESR_FRM_ERR) {
aabdfd6a 370 netdev_dbg(dev, "FRM_ERR irq\n");
e955cead
MKB		 371 cf->data[2] |= CAN_ERR_PROT_FORM;
372 rx_errors = 1;
373 }
374 if (reg_esr & FLEXCAN_ESR_STF_ERR) {
aabdfd6a 375 netdev_dbg(dev, "STF_ERR irq\n");
e955cead
MKB		 376 cf->data[2] |= CAN_ERR_PROT_STUFF;
377 rx_errors = 1;
378 }
379
380 priv->can.can_stats.bus_error++;
381 if (rx_errors)
382 dev->stats.rx_errors++;
383 if (tx_errors)
384 dev->stats.tx_errors++;
385}
386
387static int flexcan_poll_bus_err(struct net_device *dev, u32 reg_esr)
388{
389 struct sk_buff *skb;
390 struct can_frame *cf;
391
392 skb = alloc_can_err_skb(dev, &cf);
393 if (unlikely(!skb))
394 return 0;
395
396 do_bus_err(dev, cf, reg_esr);
397 netif_receive_skb(skb);
398
399 dev->stats.rx_packets++;
400 dev->stats.rx_bytes += cf->can_dlc;
401
402 return 1;
403}
404
405static void do_state(struct net_device *dev,
406 struct can_frame *cf, enum can_state new_state)
407{
408 struct flexcan_priv *priv = netdev_priv(dev);
409 struct can_berr_counter bec;
410
411 flexcan_get_berr_counter(dev, &bec);
412
413 switch (priv->can.state) {
414 case CAN_STATE_ERROR_ACTIVE:
415 /*
416 * from: ERROR_ACTIVE
417 * to : ERROR_WARNING, ERROR_PASSIVE, BUS_OFF
418 * => : there was a warning int
419 */
420 if (new_state >= CAN_STATE_ERROR_WARNING &&
421 new_state <= CAN_STATE_BUS_OFF) {
aabdfd6a 422 netdev_dbg(dev, "Error Warning IRQ\n");
e955cead
MKB		 423 priv->can.can_stats.error_warning++;
424
425 cf->can_id |= CAN_ERR_CRTL;
426 cf->data[1] = (bec.txerr > bec.rxerr) ?
427 CAN_ERR_CRTL_TX_WARNING :
428 CAN_ERR_CRTL_RX_WARNING;
429 }
430 case CAN_STATE_ERROR_WARNING: /* fallthrough */
431 /*
432 * from: ERROR_ACTIVE, ERROR_WARNING
433 * to : ERROR_PASSIVE, BUS_OFF
434 * => : error passive int
435 */
436 if (new_state >= CAN_STATE_ERROR_PASSIVE &&
437 new_state <= CAN_STATE_BUS_OFF) {
aabdfd6a 438 netdev_dbg(dev, "Error Passive IRQ\n");
e955cead
MKB		 439 priv->can.can_stats.error_passive++;
440
441 cf->can_id |= CAN_ERR_CRTL;
442 cf->data[1] = (bec.txerr > bec.rxerr) ?
443 CAN_ERR_CRTL_TX_PASSIVE :
444 CAN_ERR_CRTL_RX_PASSIVE;
445 }
446 break;
447 case CAN_STATE_BUS_OFF:
aabdfd6a
WG		 448 netdev_err(dev, "BUG! "
449 "hardware recovered automatically from BUS_OFF\n");
e955cead
MKB		 450 break;
451 default:
452 break;
453 }
454
455 /* process state changes depending on the new state */
456 switch (new_state) {
457 case CAN_STATE_ERROR_ACTIVE:
aabdfd6a 458 netdev_dbg(dev, "Error Active\n");
e955cead
MKB		 459 cf->can_id |= CAN_ERR_PROT;
460 cf->data[2] = CAN_ERR_PROT_ACTIVE;
461 break;
462 case CAN_STATE_BUS_OFF:
463 cf->can_id |= CAN_ERR_BUSOFF;
464 can_bus_off(dev);
465 break;
466 default:
467 break;
468 }
469}
470
471static int flexcan_poll_state(struct net_device *dev, u32 reg_esr)
472{
473 struct flexcan_priv *priv = netdev_priv(dev);
474 struct sk_buff *skb;
475 struct can_frame *cf;
476 enum can_state new_state;
477 int flt;
478
479 flt = reg_esr & FLEXCAN_ESR_FLT_CONF_MASK;
480 if (likely(flt == FLEXCAN_ESR_FLT_CONF_ACTIVE)) {
481 if (likely(!(reg_esr & (FLEXCAN_ESR_TX_WRN |
482 FLEXCAN_ESR_RX_WRN))))
483 new_state = CAN_STATE_ERROR_ACTIVE;
484 else
485 new_state = CAN_STATE_ERROR_WARNING;
486 } else if (unlikely(flt == FLEXCAN_ESR_FLT_CONF_PASSIVE))
487 new_state = CAN_STATE_ERROR_PASSIVE;
488 else
489 new_state = CAN_STATE_BUS_OFF;
490
491 /* state hasn't changed */
492 if (likely(new_state == priv->can.state))
493 return 0;
494
495 skb = alloc_can_err_skb(dev, &cf);
496 if (unlikely(!skb))
497 return 0;
498
499 do_state(dev, cf, new_state);
500 priv->can.state = new_state;
501 netif_receive_skb(skb);
502
503 dev->stats.rx_packets++;
504 dev->stats.rx_bytes += cf->can_dlc;
505
506 return 1;
507}
508
509static void flexcan_read_fifo(const struct net_device *dev,
510 struct can_frame *cf)
511{
512 const struct flexcan_priv *priv = netdev_priv(dev);
513 struct flexcan_regs __iomem *regs = priv->base;
514 struct flexcan_mb __iomem *mb = &regs->cantxfg[0];
515 u32 reg_ctrl, reg_id;
516
61e271ee 517 reg_ctrl = flexcan_read(&mb->can_ctrl);
518 reg_id = flexcan_read(&mb->can_id);
e955cead
MKB		 519 if (reg_ctrl & FLEXCAN_MB_CNT_IDE)
520 cf->can_id = ((reg_id >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG;
521 else
522 cf->can_id = (reg_id >> 18) & CAN_SFF_MASK;
523
524 if (reg_ctrl & FLEXCAN_MB_CNT_RTR)
525 cf->can_id |= CAN_RTR_FLAG;
526 cf->can_dlc = get_can_dlc((reg_ctrl >> 16) & 0xf);
527
61e271ee 528 *(__be32 *)(cf->data + 0) = cpu_to_be32(flexcan_read(&mb->data[0]));
529 *(__be32 *)(cf->data + 4) = cpu_to_be32(flexcan_read(&mb->data[1]));
e955cead
MKB		 530
531 /* mark as read */
61e271ee 532 flexcan_write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, &regs->iflag1);
533 flexcan_read(&regs->timer);
e955cead
MKB		 534}
535
536static int flexcan_read_frame(struct net_device *dev)
537{
538 struct net_device_stats *stats = &dev->stats;
539 struct can_frame *cf;
540 struct sk_buff *skb;
541
542 skb = alloc_can_skb(dev, &cf);
543 if (unlikely(!skb)) {
544 stats->rx_dropped++;
545 return 0;
546 }
547
548 flexcan_read_fifo(dev, cf);
549 netif_receive_skb(skb);
550
551 stats->rx_packets++;
552 stats->rx_bytes += cf->can_dlc;
553
554 return 1;
555}
556
557static int flexcan_poll(struct napi_struct *napi, int quota)
558{
559 struct net_device *dev = napi->dev;
560 const struct flexcan_priv *priv = netdev_priv(dev);
561 struct flexcan_regs __iomem *regs = priv->base;
562 u32 reg_iflag1, reg_esr;
563 int work_done = 0;
564
565 /*
566 * The error bits are cleared on read,
567 * use saved value from irq handler.
568 */
61e271ee 569 reg_esr = flexcan_read(&regs->esr) | priv->reg_esr;
e955cead
MKB		 570
571 /* handle state changes */
572 work_done += flexcan_poll_state(dev, reg_esr);
573
574 /* handle RX-FIFO */
61e271ee 575 reg_iflag1 = flexcan_read(&regs->iflag1);
e955cead
MKB		 576 while (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE &&
577 work_done < quota) {
578 work_done += flexcan_read_frame(dev);
61e271ee 579 reg_iflag1 = flexcan_read(&regs->iflag1);
e955cead
MKB		 580 }
581
582 /* report bus errors */
583 if (flexcan_has_and_handle_berr(priv, reg_esr) && work_done < quota)
584 work_done += flexcan_poll_bus_err(dev, reg_esr);
585
586 if (work_done < quota) {
587 napi_complete(napi);
588 /* enable IRQs */
61e271ee 589 flexcan_write(FLEXCAN_IFLAG_DEFAULT, &regs->imask1);
590 flexcan_write(priv->reg_ctrl_default, &regs->ctrl);
e955cead
MKB		 591 }
592
593 return work_done;
594}
595
596static irqreturn_t flexcan_irq(int irq, void *dev_id)
597{
598 struct net_device *dev = dev_id;
599 struct net_device_stats *stats = &dev->stats;
600 struct flexcan_priv *priv = netdev_priv(dev);
601 struct flexcan_regs __iomem *regs = priv->base;
602 u32 reg_iflag1, reg_esr;
603
61e271ee 604 reg_iflag1 = flexcan_read(&regs->iflag1);
605 reg_esr = flexcan_read(&regs->esr);
6e9d554f
WG		 606 /* ACK all bus error and state change IRQ sources */
607 if (reg_esr & FLEXCAN_ESR_ALL_INT)
608 flexcan_write(reg_esr & FLEXCAN_ESR_ALL_INT, &regs->esr);
e955cead
MKB		 609
610 /*
611 * schedule NAPI in case of:
612 * - rx IRQ
613 * - state change IRQ
614 * - bus error IRQ and bus error reporting is activated
615 */
616 if ((reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE) ||
617 (reg_esr & FLEXCAN_ESR_ERR_STATE) ||
618 flexcan_has_and_handle_berr(priv, reg_esr)) {
619 /*
620 * The error bits are cleared on read,
621 * save them for later use.
622 */
623 priv->reg_esr = reg_esr & FLEXCAN_ESR_ERR_BUS;
61e271ee 624 flexcan_write(FLEXCAN_IFLAG_DEFAULT &
625 ~FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, &regs->imask1);
626 flexcan_write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
e955cead
MKB		 627 &regs->ctrl);
628 napi_schedule(&priv->napi);
629 }
630
631 /* FIFO overflow */
632 if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_OVERFLOW) {
61e271ee 633 flexcan_write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW, &regs->iflag1);
e955cead
MKB		 634 dev->stats.rx_over_errors++;
635 dev->stats.rx_errors++;
636 }
637
638 /* transmission complete interrupt */
639 if (reg_iflag1 & (1 << FLEXCAN_TX_BUF_ID)) {
9a123496 640 stats->tx_bytes += can_get_echo_skb(dev, 0);
e955cead 641 stats->tx_packets++;
61e271ee 642 flexcan_write((1 << FLEXCAN_TX_BUF_ID), &regs->iflag1);
e955cead
MKB		 643 netif_wake_queue(dev);
644 }
645
646 return IRQ_HANDLED;
647}
648
649static void flexcan_set_bittiming(struct net_device *dev)
650{
651 const struct flexcan_priv *priv = netdev_priv(dev);
652 const struct can_bittiming *bt = &priv->can.bittiming;
653 struct flexcan_regs __iomem *regs = priv->base;
654 u32 reg;
655
61e271ee 656 reg = flexcan_read(&regs->ctrl);
e955cead
MKB		 657 reg &= ~(FLEXCAN_CTRL_PRESDIV(0xff) |
658 FLEXCAN_CTRL_RJW(0x3) |
659 FLEXCAN_CTRL_PSEG1(0x7) |
660 FLEXCAN_CTRL_PSEG2(0x7) |
661 FLEXCAN_CTRL_PROPSEG(0x7) |
662 FLEXCAN_CTRL_LPB |
663 FLEXCAN_CTRL_SMP |
664 FLEXCAN_CTRL_LOM);
665
666 reg |= FLEXCAN_CTRL_PRESDIV(bt->brp - 1) |
667 FLEXCAN_CTRL_PSEG1(bt->phase_seg1 - 1) |
668 FLEXCAN_CTRL_PSEG2(bt->phase_seg2 - 1) |
669 FLEXCAN_CTRL_RJW(bt->sjw - 1) |
670 FLEXCAN_CTRL_PROPSEG(bt->prop_seg - 1);
671
672 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
673 reg |= FLEXCAN_CTRL_LPB;
674 if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
675 reg |= FLEXCAN_CTRL_LOM;
676 if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES)
677 reg |= FLEXCAN_CTRL_SMP;
678
aabdfd6a 679 netdev_info(dev, "writing ctrl=0x%08x\n", reg);
61e271ee 680 flexcan_write(reg, &regs->ctrl);
e955cead
MKB		 681
682 /* print chip status */
aabdfd6a
WG		 683 netdev_dbg(dev, "%s: mcr=0x%08x ctrl=0x%08x\n", __func__,
684 flexcan_read(&regs->mcr), flexcan_read(&regs->ctrl));
e955cead
MKB		 685}
686
687/*
688 * flexcan_chip_start
689 *
690 * this functions is entered with clocks enabled
691 *
692 */
693static int flexcan_chip_start(struct net_device *dev)
694{
695 struct flexcan_priv *priv = netdev_priv(dev);
696 struct flexcan_regs __iomem *regs = priv->base;
697 unsigned int i;
698 int err;
699 u32 reg_mcr, reg_ctrl;
700
701 /* enable module */
702 flexcan_chip_enable(priv);
703
704 /* soft reset */
61e271ee 705 flexcan_write(FLEXCAN_MCR_SOFTRST, &regs->mcr);
e955cead
MKB		 706 udelay(10);
707
61e271ee 708 reg_mcr = flexcan_read(&regs->mcr);
e955cead 709 if (reg_mcr & FLEXCAN_MCR_SOFTRST) {
aabdfd6a
WG		 710 netdev_err(dev, "Failed to softreset can module (mcr=0x%08x)\n",
711 reg_mcr);
e955cead
MKB		 712 err = -ENODEV;
713 goto out;
714 }
715
716 flexcan_set_bittiming(dev);
717
718 /*
719 * MCR
720 *
721 * enable freeze
722 * enable fifo
723 * halt now
724 * only supervisor access
725 * enable warning int
726 * choose format C
9a123496 727 * disable local echo
e955cead
MKB		 728 *
729 */
61e271ee 730 reg_mcr = flexcan_read(&regs->mcr);
e955cead
MKB		 731 reg_mcr |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_FEN | FLEXCAN_MCR_HALT |
732 FLEXCAN_MCR_SUPV | FLEXCAN_MCR_WRN_EN |
9a123496 733 FLEXCAN_MCR_IDAM_C | FLEXCAN_MCR_SRX_DIS;
aabdfd6a 734 netdev_dbg(dev, "%s: writing mcr=0x%08x", __func__, reg_mcr);
61e271ee 735 flexcan_write(reg_mcr, &regs->mcr);
e955cead
MKB		 736
737 /*
738 * CTRL
739 *
740 * disable timer sync feature
741 *
742 * disable auto busoff recovery
743 * transmit lowest buffer first
744 *
745 * enable tx and rx warning interrupt
746 * enable bus off interrupt
747 * (== FLEXCAN_CTRL_ERR_STATE)
e955cead 748 */
61e271ee 749 reg_ctrl = flexcan_read(&regs->ctrl);
e955cead
MKB		 750 reg_ctrl &= ~FLEXCAN_CTRL_TSYN;
751 reg_ctrl |= FLEXCAN_CTRL_BOFF_REC | FLEXCAN_CTRL_LBUF |
4f72e5f0
WG		 752 FLEXCAN_CTRL_ERR_STATE;
753 /*
754 * enable the "error interrupt" (FLEXCAN_CTRL_ERR_MSK),
755 * on most Flexcan cores, too. Otherwise we don't get
756 * any error warning or passive interrupts.
757 */
758 if (priv->devtype_data->features & FLEXCAN_HAS_BROKEN_ERR_STATE ||
759 priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)
760 reg_ctrl |= FLEXCAN_CTRL_ERR_MSK;
e955cead
MKB		 761
762 /* save for later use */
763 priv->reg_ctrl_default = reg_ctrl;
aabdfd6a 764 netdev_dbg(dev, "%s: writing ctrl=0x%08x", __func__, reg_ctrl);
61e271ee 765 flexcan_write(reg_ctrl, &regs->ctrl);
e955cead
MKB		 766
767 for (i = 0; i < ARRAY_SIZE(regs->cantxfg); i++) {
61e271ee 768 flexcan_write(0, &regs->cantxfg[i].can_ctrl);
769 flexcan_write(0, &regs->cantxfg[i].can_id);
770 flexcan_write(0, &regs->cantxfg[i].data[0]);
771 flexcan_write(0, &regs->cantxfg[i].data[1]);
e955cead
MKB		 772
773 /* put MB into rx queue */
61e271ee 774 flexcan_write(FLEXCAN_MB_CNT_CODE(0x4),
775 &regs->cantxfg[i].can_ctrl);
e955cead
MKB		 776 }
777
778 /* acceptance mask/acceptance code (accept everything) */
61e271ee 779 flexcan_write(0x0, &regs->rxgmask);
780 flexcan_write(0x0, &regs->rx14mask);
781 flexcan_write(0x0, &regs->rx15mask);
e955cead 782
4f72e5f0 783 if (priv->devtype_data->features & FLEXCAN_HAS_V10_FEATURES)
30c1e672
HW		 784 flexcan_write(0x0, &regs->rxfgmask);
785
e955cead
MKB		 786 flexcan_transceiver_switch(priv, 1);
787
788 /* synchronize with the can bus */
61e271ee 789 reg_mcr = flexcan_read(&regs->mcr);
e955cead 790 reg_mcr &= ~FLEXCAN_MCR_HALT;
61e271ee 791 flexcan_write(reg_mcr, &regs->mcr);
e955cead
MKB		 792
793 priv->can.state = CAN_STATE_ERROR_ACTIVE;
794
795 /* enable FIFO interrupts */
61e271ee 796 flexcan_write(FLEXCAN_IFLAG_DEFAULT, &regs->imask1);
e955cead
MKB		 797
798 /* print chip status */
aabdfd6a
WG		 799 netdev_dbg(dev, "%s: reading mcr=0x%08x ctrl=0x%08x\n", __func__,
800 flexcan_read(&regs->mcr), flexcan_read(&regs->ctrl));
e955cead
MKB		 801
802 return 0;
803
804 out:
805 flexcan_chip_disable(priv);
806 return err;
807}
808
809/*
810 * flexcan_chip_stop
811 *
812 * this functions is entered with clocks enabled
813 *
814 */
815static void flexcan_chip_stop(struct net_device *dev)
816{
817 struct flexcan_priv *priv = netdev_priv(dev);
818 struct flexcan_regs __iomem *regs = priv->base;
819 u32 reg;
820
821 /* Disable all interrupts */
61e271ee 822 flexcan_write(0, &regs->imask1);
e955cead
MKB		 823
824 /* Disable + halt module */
61e271ee 825 reg = flexcan_read(&regs->mcr);
e955cead 826 reg |= FLEXCAN_MCR_MDIS | FLEXCAN_MCR_HALT;
61e271ee 827 flexcan_write(reg, &regs->mcr);
e955cead
MKB		 828
829 flexcan_transceiver_switch(priv, 0);
830 priv->can.state = CAN_STATE_STOPPED;
831
832 return;
833}
834
835static int flexcan_open(struct net_device *dev)
836{
837 struct flexcan_priv *priv = netdev_priv(dev);
838 int err;
839
3d42a379
ST		 840 clk_prepare_enable(priv->clk_ipg);
841 clk_prepare_enable(priv->clk_per);
e955cead
MKB		 842
843 err = open_candev(dev);
844 if (err)
845 goto out;
846
847 err = request_irq(dev->irq, flexcan_irq, IRQF_SHARED, dev->name, dev);
848 if (err)
849 goto out_close;
850
851 /* start chip and queuing */
852 err = flexcan_chip_start(dev);
853 if (err)
854 goto out_close;
855 napi_enable(&priv->napi);
856 netif_start_queue(dev);
857
858 return 0;
859
860 out_close:
861 close_candev(dev);
862 out:
3d42a379
ST		 863 clk_disable_unprepare(priv->clk_per);
864 clk_disable_unprepare(priv->clk_ipg);
e955cead
MKB		 865
866 return err;
867}
868
869static int flexcan_close(struct net_device *dev)
870{
871 struct flexcan_priv *priv = netdev_priv(dev);
872
873 netif_stop_queue(dev);
874 napi_disable(&priv->napi);
875 flexcan_chip_stop(dev);
876
877 free_irq(dev->irq, dev);
3d42a379
ST		 878 clk_disable_unprepare(priv->clk_per);
879 clk_disable_unprepare(priv->clk_ipg);
e955cead
MKB		 880
881 close_candev(dev);
882
883 return 0;
884}
885
886static int flexcan_set_mode(struct net_device *dev, enum can_mode mode)
887{
888 int err;
889
890 switch (mode) {
891 case CAN_MODE_START:
892 err = flexcan_chip_start(dev);
893 if (err)
894 return err;
895
896 netif_wake_queue(dev);
897 break;
898
899 default:
900 return -EOPNOTSUPP;
901 }
902
903 return 0;
904}
905
906static const struct net_device_ops flexcan_netdev_ops = {
907 .ndo_open = flexcan_open,
908 .ndo_stop = flexcan_close,
909 .ndo_start_xmit = flexcan_start_xmit,
910};
911
912static int __devinit register_flexcandev(struct net_device *dev)
913{
914 struct flexcan_priv *priv = netdev_priv(dev);
915 struct flexcan_regs __iomem *regs = priv->base;
916 u32 reg, err;
917
3d42a379
ST		 918 clk_prepare_enable(priv->clk_ipg);
919 clk_prepare_enable(priv->clk_per);
e955cead
MKB		 920
921 /* select "bus clock", chip must be disabled */
922 flexcan_chip_disable(priv);
61e271ee 923 reg = flexcan_read(&regs->ctrl);
e955cead 924 reg |= FLEXCAN_CTRL_CLK_SRC;
61e271ee 925 flexcan_write(reg, &regs->ctrl);
e955cead
MKB		 926
927 flexcan_chip_enable(priv);
928
929 /* set freeze, halt and activate FIFO, restrict register access */
61e271ee 930 reg = flexcan_read(&regs->mcr);
e955cead
MKB		 931 reg |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT |
932 FLEXCAN_MCR_FEN | FLEXCAN_MCR_SUPV;
61e271ee 933 flexcan_write(reg, &regs->mcr);
e955cead
MKB		 934
935 /*
936 * Currently we only support newer versions of this core
937 * featuring a RX FIFO. Older cores found on some Coldfire
938 * derivates are not yet supported.
939 */
61e271ee 940 reg = flexcan_read(&regs->mcr);
e955cead 941 if (!(reg & FLEXCAN_MCR_FEN)) {
aabdfd6a 942 netdev_err(dev, "Could not enable RX FIFO, unsupported core\n");
e955cead
MKB		 943 err = -ENODEV;
944 goto out;
945 }
946
947 err = register_candev(dev);
948
949 out:
950 /* disable core and turn off clocks */
951 flexcan_chip_disable(priv);
3d42a379
ST		 952 clk_disable_unprepare(priv->clk_per);
953 clk_disable_unprepare(priv->clk_ipg);
e955cead
MKB		 954
955 return err;
956}
957
958static void __devexit unregister_flexcandev(struct net_device *dev)
959{
960 unregister_candev(dev);
961}
962
30c1e672
HW		 963static const struct of_device_id flexcan_of_match[] = {
964 { .compatible = "fsl,p1010-flexcan", .data = &fsl_p1010_devtype_data, },
4f72e5f0 965 { .compatible = "fsl,imx28-flexcan", .data = &fsl_imx28_devtype_data, },
30c1e672
HW		 966 { .compatible = "fsl,imx6q-flexcan", .data = &fsl_imx6q_devtype_data, },
967 { /* sentinel */ },
968};
969
970static const struct platform_device_id flexcan_id_table[] = {
971 { .name = "flexcan", .driver_data = (kernel_ulong_t)&fsl_p1010_devtype_data, },
972 { /* sentinel */ },
973};
974
e955cead
MKB		 975static int __devinit flexcan_probe(struct platform_device *pdev)
976{
30c1e672 977 const struct of_device_id *of_id;
dda0b3bd 978 const struct flexcan_devtype_data *devtype_data;
e955cead
MKB		 979 struct net_device *dev;
980 struct flexcan_priv *priv;
981 struct resource *mem;
3d42a379 982 struct clk *clk_ipg = NULL, *clk_per = NULL;
a53157c2 983 struct pinctrl *pinctrl;
e955cead
MKB		 984 void __iomem *base;
985 resource_size_t mem_size;
986 int err, irq;
97efe9ae 987 u32 clock_freq = 0;
988
a53157c2
SG		 989 pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
990 if (IS_ERR(pinctrl))
991 return PTR_ERR(pinctrl);
992
afc016d8
HW		 993 if (pdev->dev.of_node)
994 of_property_read_u32(pdev->dev.of_node,
995 "clock-frequency", &clock_freq);
97efe9ae 996
997 if (!clock_freq) {
3d42a379
ST		 998 clk_ipg = devm_clk_get(&pdev->dev, "ipg");
999 if (IS_ERR(clk_ipg)) {
1000 dev_err(&pdev->dev, "no ipg clock defined\n");
1001 err = PTR_ERR(clk_ipg);
1002 goto failed_clock;
1003 }
1004 clock_freq = clk_get_rate(clk_ipg);
1005
1006 clk_per = devm_clk_get(&pdev->dev, "per");
1007 if (IS_ERR(clk_per)) {
1008 dev_err(&pdev->dev, "no per clock defined\n");
1009 err = PTR_ERR(clk_per);
97efe9ae 1010 goto failed_clock;
1011 }
e955cead
MKB		 1012 }
1013
1014 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1015 irq = platform_get_irq(pdev, 0);
1016 if (!mem || irq <= 0) {
1017 err = -ENODEV;
1018 goto failed_get;
1019 }
1020
1021 mem_size = resource_size(mem);
1022 if (!request_mem_region(mem->start, mem_size, pdev->name)) {
1023 err = -EBUSY;
2e4ceec4 1024 goto failed_get;
e955cead
MKB		 1025 }
1026
1027 base = ioremap(mem->start, mem_size);
1028 if (!base) {
1029 err = -ENOMEM;
1030 goto failed_map;
1031 }
1032
9a123496 1033 dev = alloc_candev(sizeof(struct flexcan_priv), 1);
e955cead
MKB		 1034 if (!dev) {
1035 err = -ENOMEM;
1036 goto failed_alloc;
1037 }
1038
30c1e672
HW		 1039 of_id = of_match_device(flexcan_of_match, &pdev->dev);
1040 if (of_id) {
1041 devtype_data = of_id->data;
1042 } else if (pdev->id_entry->driver_data) {
1043 devtype_data = (struct flexcan_devtype_data *)
1044 pdev->id_entry->driver_data;
1045 } else {
1046 err = -ENODEV;
1047 goto failed_devtype;
1048 }
1049
e955cead
MKB		 1050 dev->netdev_ops = &flexcan_netdev_ops;
1051 dev->irq = irq;
9a123496 1052 dev->flags |= IFF_ECHO;
e955cead
MKB		 1053
1054 priv = netdev_priv(dev);
97efe9ae 1055 priv->can.clock.freq = clock_freq;
e955cead
MKB		 1056 priv->can.bittiming_const = &flexcan_bittiming_const;
1057 priv->can.do_set_mode = flexcan_set_mode;
1058 priv->can.do_get_berr_counter = flexcan_get_berr_counter;
1059 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
1060 CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_3_SAMPLES |
1061 CAN_CTRLMODE_BERR_REPORTING;
1062 priv->base = base;
1063 priv->dev = dev;
3d42a379
ST		 1064 priv->clk_ipg = clk_ipg;
1065 priv->clk_per = clk_per;
e955cead 1066 priv->pdata = pdev->dev.platform_data;
30c1e672 1067 priv->devtype_data = devtype_data;
e955cead
MKB		 1068
1069 netif_napi_add(dev, &priv->napi, flexcan_poll, FLEXCAN_NAPI_WEIGHT);
1070
1071 dev_set_drvdata(&pdev->dev, dev);
1072 SET_NETDEV_DEV(dev, &pdev->dev);
1073
1074 err = register_flexcandev(dev);
1075 if (err) {
1076 dev_err(&pdev->dev, "registering netdev failed\n");
1077 goto failed_register;
1078 }
1079
1080 dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%d)\n",
1081 priv->base, dev->irq);
1082
1083 return 0;
1084
1085 failed_register:
30c1e672 1086 failed_devtype:
e955cead
MKB		 1087 free_candev(dev);
1088 failed_alloc:
1089 iounmap(base);
1090 failed_map:
1091 release_mem_region(mem->start, mem_size);
e955cead
MKB		 1092 failed_get:
1093 failed_clock:
1094 return err;
1095}
1096
1097static int __devexit flexcan_remove(struct platform_device *pdev)
1098{
1099 struct net_device *dev = platform_get_drvdata(pdev);
1100 struct flexcan_priv *priv = netdev_priv(dev);
1101 struct resource *mem;
1102
1103 unregister_flexcandev(dev);
1104 platform_set_drvdata(pdev, NULL);
e955cead
MKB		 1105 iounmap(priv->base);
1106
1107 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1108 release_mem_region(mem->start, resource_size(mem));
1109
9a27586d
MKB		 1110 free_candev(dev);
1111
e955cead
MKB		 1112 return 0;
1113}
1114
8b5e218d
EB		 1115#ifdef CONFIG_PM
1116static int flexcan_suspend(struct platform_device *pdev, pm_message_t state)
1117{
1118 struct net_device *dev = platform_get_drvdata(pdev);
1119 struct flexcan_priv *priv = netdev_priv(dev);
1120
1121 flexcan_chip_disable(priv);
1122
1123 if (netif_running(dev)) {
1124 netif_stop_queue(dev);
1125 netif_device_detach(dev);
1126 }
1127 priv->can.state = CAN_STATE_SLEEPING;
1128
1129 return 0;
1130}
1131
1132static int flexcan_resume(struct platform_device *pdev)
1133{
1134 struct net_device *dev = platform_get_drvdata(pdev);
1135 struct flexcan_priv *priv = netdev_priv(dev);
1136
1137 priv->can.state = CAN_STATE_ERROR_ACTIVE;
1138 if (netif_running(dev)) {
1139 netif_device_attach(dev);
1140 netif_start_queue(dev);
1141 }
1142 flexcan_chip_enable(priv);
1143
1144 return 0;
1145}
1146#else
1147#define flexcan_suspend NULL
1148#define flexcan_resume NULL
1149#endif
1150
e955cead 1151static struct platform_driver flexcan_driver = {
c8aef4cb 1152 .driver = {
1153 .name = DRV_NAME,
1154 .owner = THIS_MODULE,
1155 .of_match_table = flexcan_of_match,
1156 },
e955cead
MKB		 1157 .probe = flexcan_probe,
1158 .remove = __devexit_p(flexcan_remove),
8b5e218d
EB		 1159 .suspend = flexcan_suspend,
1160 .resume = flexcan_resume,
30c1e672 1161 .id_table = flexcan_id_table,
e955cead
MKB		 1162};
1163
871d3372 1164module_platform_driver(flexcan_driver);
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MKB		 1165
1166MODULE_AUTHOR("Sascha Hauer <kernel@pengutronix.de>, "
1167 "Marc Kleine-Budde <kernel@pengutronix.de>");
1168MODULE_LICENSE("GPL v2");
1169MODULE_DESCRIPTION("CAN port driver for flexcan based chip");
Linux kernel - Deliverables
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