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e955cead MKB |
1 | /* |
2 | * flexcan.c - FLEXCAN CAN controller driver | |
3 | * | |
4 | * Copyright (c) 2005-2006 Varma Electronics Oy | |
5 | * Copyright (c) 2009 Sascha Hauer, Pengutronix | |
6 | * Copyright (c) 2010 Marc Kleine-Budde, Pengutronix | |
7 | * | |
8 | * Based on code originally by Andrey Volkov <avolkov@varma-el.com> | |
9 | * | |
10 | * LICENCE: | |
11 | * This program is free software; you can redistribute it and/or | |
12 | * modify it under the terms of the GNU General Public License as | |
13 | * published by the Free Software Foundation version 2. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | */ | |
21 | ||
22 | #include <linux/netdevice.h> | |
23 | #include <linux/can.h> | |
24 | #include <linux/can/dev.h> | |
25 | #include <linux/can/error.h> | |
26 | #include <linux/can/platform/flexcan.h> | |
27 | #include <linux/clk.h> | |
28 | #include <linux/delay.h> | |
29 | #include <linux/if_arp.h> | |
30 | #include <linux/if_ether.h> | |
31 | #include <linux/interrupt.h> | |
32 | #include <linux/io.h> | |
33 | #include <linux/kernel.h> | |
34 | #include <linux/list.h> | |
35 | #include <linux/module.h> | |
97efe9ae | 36 | #include <linux/of.h> |
30c1e672 | 37 | #include <linux/of_device.h> |
e955cead | 38 | #include <linux/platform_device.h> |
a53157c2 | 39 | #include <linux/pinctrl/consumer.h> |
e955cead | 40 | |
e955cead MKB |
41 | #define DRV_NAME "flexcan" |
42 | ||
43 | /* 8 for RX fifo and 2 error handling */ | |
44 | #define FLEXCAN_NAPI_WEIGHT (8 + 2) | |
45 | ||
46 | /* FLEXCAN module configuration register (CANMCR) bits */ | |
47 | #define FLEXCAN_MCR_MDIS BIT(31) | |
48 | #define FLEXCAN_MCR_FRZ BIT(30) | |
49 | #define FLEXCAN_MCR_FEN BIT(29) | |
50 | #define FLEXCAN_MCR_HALT BIT(28) | |
51 | #define FLEXCAN_MCR_NOT_RDY BIT(27) | |
52 | #define FLEXCAN_MCR_WAK_MSK BIT(26) | |
53 | #define FLEXCAN_MCR_SOFTRST BIT(25) | |
54 | #define FLEXCAN_MCR_FRZ_ACK BIT(24) | |
55 | #define FLEXCAN_MCR_SUPV BIT(23) | |
56 | #define FLEXCAN_MCR_SLF_WAK BIT(22) | |
57 | #define FLEXCAN_MCR_WRN_EN BIT(21) | |
58 | #define FLEXCAN_MCR_LPM_ACK BIT(20) | |
59 | #define FLEXCAN_MCR_WAK_SRC BIT(19) | |
60 | #define FLEXCAN_MCR_DOZE BIT(18) | |
61 | #define FLEXCAN_MCR_SRX_DIS BIT(17) | |
62 | #define FLEXCAN_MCR_BCC BIT(16) | |
63 | #define FLEXCAN_MCR_LPRIO_EN BIT(13) | |
64 | #define FLEXCAN_MCR_AEN BIT(12) | |
65 | #define FLEXCAN_MCR_MAXMB(x) ((x) & 0xf) | |
66 | #define FLEXCAN_MCR_IDAM_A (0 << 8) | |
67 | #define FLEXCAN_MCR_IDAM_B (1 << 8) | |
68 | #define FLEXCAN_MCR_IDAM_C (2 << 8) | |
69 | #define FLEXCAN_MCR_IDAM_D (3 << 8) | |
70 | ||
71 | /* FLEXCAN control register (CANCTRL) bits */ | |
72 | #define FLEXCAN_CTRL_PRESDIV(x) (((x) & 0xff) << 24) | |
73 | #define FLEXCAN_CTRL_RJW(x) (((x) & 0x03) << 22) | |
74 | #define FLEXCAN_CTRL_PSEG1(x) (((x) & 0x07) << 19) | |
75 | #define FLEXCAN_CTRL_PSEG2(x) (((x) & 0x07) << 16) | |
76 | #define FLEXCAN_CTRL_BOFF_MSK BIT(15) | |
77 | #define FLEXCAN_CTRL_ERR_MSK BIT(14) | |
78 | #define FLEXCAN_CTRL_CLK_SRC BIT(13) | |
79 | #define FLEXCAN_CTRL_LPB BIT(12) | |
80 | #define FLEXCAN_CTRL_TWRN_MSK BIT(11) | |
81 | #define FLEXCAN_CTRL_RWRN_MSK BIT(10) | |
82 | #define FLEXCAN_CTRL_SMP BIT(7) | |
83 | #define FLEXCAN_CTRL_BOFF_REC BIT(6) | |
84 | #define FLEXCAN_CTRL_TSYN BIT(5) | |
85 | #define FLEXCAN_CTRL_LBUF BIT(4) | |
86 | #define FLEXCAN_CTRL_LOM BIT(3) | |
87 | #define FLEXCAN_CTRL_PROPSEG(x) ((x) & 0x07) | |
88 | #define FLEXCAN_CTRL_ERR_BUS (FLEXCAN_CTRL_ERR_MSK) | |
89 | #define FLEXCAN_CTRL_ERR_STATE \ | |
90 | (FLEXCAN_CTRL_TWRN_MSK | FLEXCAN_CTRL_RWRN_MSK | \ | |
91 | FLEXCAN_CTRL_BOFF_MSK) | |
92 | #define FLEXCAN_CTRL_ERR_ALL \ | |
93 | (FLEXCAN_CTRL_ERR_BUS | FLEXCAN_CTRL_ERR_STATE) | |
94 | ||
95 | /* FLEXCAN error and status register (ESR) bits */ | |
96 | #define FLEXCAN_ESR_TWRN_INT BIT(17) | |
97 | #define FLEXCAN_ESR_RWRN_INT BIT(16) | |
98 | #define FLEXCAN_ESR_BIT1_ERR BIT(15) | |
99 | #define FLEXCAN_ESR_BIT0_ERR BIT(14) | |
100 | #define FLEXCAN_ESR_ACK_ERR BIT(13) | |
101 | #define FLEXCAN_ESR_CRC_ERR BIT(12) | |
102 | #define FLEXCAN_ESR_FRM_ERR BIT(11) | |
103 | #define FLEXCAN_ESR_STF_ERR BIT(10) | |
104 | #define FLEXCAN_ESR_TX_WRN BIT(9) | |
105 | #define FLEXCAN_ESR_RX_WRN BIT(8) | |
106 | #define FLEXCAN_ESR_IDLE BIT(7) | |
107 | #define FLEXCAN_ESR_TXRX BIT(6) | |
108 | #define FLEXCAN_EST_FLT_CONF_SHIFT (4) | |
109 | #define FLEXCAN_ESR_FLT_CONF_MASK (0x3 << FLEXCAN_EST_FLT_CONF_SHIFT) | |
110 | #define FLEXCAN_ESR_FLT_CONF_ACTIVE (0x0 << FLEXCAN_EST_FLT_CONF_SHIFT) | |
111 | #define FLEXCAN_ESR_FLT_CONF_PASSIVE (0x1 << FLEXCAN_EST_FLT_CONF_SHIFT) | |
112 | #define FLEXCAN_ESR_BOFF_INT BIT(2) | |
113 | #define FLEXCAN_ESR_ERR_INT BIT(1) | |
114 | #define FLEXCAN_ESR_WAK_INT BIT(0) | |
115 | #define FLEXCAN_ESR_ERR_BUS \ | |
116 | (FLEXCAN_ESR_BIT1_ERR | FLEXCAN_ESR_BIT0_ERR | \ | |
117 | FLEXCAN_ESR_ACK_ERR | FLEXCAN_ESR_CRC_ERR | \ | |
118 | FLEXCAN_ESR_FRM_ERR | FLEXCAN_ESR_STF_ERR) | |
119 | #define FLEXCAN_ESR_ERR_STATE \ | |
120 | (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | FLEXCAN_ESR_BOFF_INT) | |
121 | #define FLEXCAN_ESR_ERR_ALL \ | |
122 | (FLEXCAN_ESR_ERR_BUS | FLEXCAN_ESR_ERR_STATE) | |
6e9d554f WG |
123 | #define FLEXCAN_ESR_ALL_INT \ |
124 | (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | \ | |
125 | FLEXCAN_ESR_BOFF_INT | FLEXCAN_ESR_ERR_INT) | |
e955cead MKB |
126 | |
127 | /* FLEXCAN interrupt flag register (IFLAG) bits */ | |
128 | #define FLEXCAN_TX_BUF_ID 8 | |
129 | #define FLEXCAN_IFLAG_BUF(x) BIT(x) | |
130 | #define FLEXCAN_IFLAG_RX_FIFO_OVERFLOW BIT(7) | |
131 | #define FLEXCAN_IFLAG_RX_FIFO_WARN BIT(6) | |
132 | #define FLEXCAN_IFLAG_RX_FIFO_AVAILABLE BIT(5) | |
133 | #define FLEXCAN_IFLAG_DEFAULT \ | |
134 | (FLEXCAN_IFLAG_RX_FIFO_OVERFLOW | FLEXCAN_IFLAG_RX_FIFO_AVAILABLE | \ | |
135 | FLEXCAN_IFLAG_BUF(FLEXCAN_TX_BUF_ID)) | |
136 | ||
137 | /* FLEXCAN message buffers */ | |
138 | #define FLEXCAN_MB_CNT_CODE(x) (((x) & 0xf) << 24) | |
139 | #define FLEXCAN_MB_CNT_SRR BIT(22) | |
140 | #define FLEXCAN_MB_CNT_IDE BIT(21) | |
141 | #define FLEXCAN_MB_CNT_RTR BIT(20) | |
142 | #define FLEXCAN_MB_CNT_LENGTH(x) (((x) & 0xf) << 16) | |
143 | #define FLEXCAN_MB_CNT_TIMESTAMP(x) ((x) & 0xffff) | |
144 | ||
145 | #define FLEXCAN_MB_CODE_MASK (0xf0ffffff) | |
146 | ||
bb698ca4 WG |
147 | /* |
148 | * FLEXCAN hardware feature flags | |
149 | * | |
150 | * Below is some version info we got: | |
151 | * SOC Version IP-Version Glitch- [TR]WRN_INT | |
152 | * Filter? connected? | |
153 | * MX25 FlexCAN2 03.00.00.00 no no | |
154 | * MX28 FlexCAN2 03.00.04.00 yes yes | |
155 | * MX35 FlexCAN2 03.00.00.00 no no | |
156 | * MX53 FlexCAN2 03.00.00.00 yes no | |
157 | * MX6s FlexCAN3 10.00.12.00 yes yes | |
158 | * | |
159 | * Some SOCs do not have the RX_WARN & TX_WARN interrupt line connected. | |
160 | */ | |
4f72e5f0 | 161 | #define FLEXCAN_HAS_V10_FEATURES BIT(1) /* For core version >= 10 */ |
bb698ca4 | 162 | #define FLEXCAN_HAS_BROKEN_ERR_STATE BIT(2) /* [TR]WRN_INT not connected */ |
4f72e5f0 | 163 | |
e955cead MKB |
164 | /* Structure of the message buffer */ |
165 | struct flexcan_mb { | |
166 | u32 can_ctrl; | |
167 | u32 can_id; | |
168 | u32 data[2]; | |
169 | }; | |
170 | ||
171 | /* Structure of the hardware registers */ | |
172 | struct flexcan_regs { | |
173 | u32 mcr; /* 0x00 */ | |
174 | u32 ctrl; /* 0x04 */ | |
175 | u32 timer; /* 0x08 */ | |
176 | u32 _reserved1; /* 0x0c */ | |
177 | u32 rxgmask; /* 0x10 */ | |
178 | u32 rx14mask; /* 0x14 */ | |
179 | u32 rx15mask; /* 0x18 */ | |
180 | u32 ecr; /* 0x1c */ | |
181 | u32 esr; /* 0x20 */ | |
182 | u32 imask2; /* 0x24 */ | |
183 | u32 imask1; /* 0x28 */ | |
184 | u32 iflag2; /* 0x2c */ | |
185 | u32 iflag1; /* 0x30 */ | |
30c1e672 HW |
186 | u32 crl2; /* 0x34 */ |
187 | u32 esr2; /* 0x38 */ | |
188 | u32 imeur; /* 0x3c */ | |
189 | u32 lrfr; /* 0x40 */ | |
190 | u32 crcr; /* 0x44 */ | |
191 | u32 rxfgmask; /* 0x48 */ | |
192 | u32 rxfir; /* 0x4c */ | |
193 | u32 _reserved3[12]; | |
e955cead MKB |
194 | struct flexcan_mb cantxfg[64]; |
195 | }; | |
196 | ||
30c1e672 | 197 | struct flexcan_devtype_data { |
4f72e5f0 | 198 | u32 features; /* hardware controller features */ |
30c1e672 HW |
199 | }; |
200 | ||
e955cead MKB |
201 | struct flexcan_priv { |
202 | struct can_priv can; | |
203 | struct net_device *dev; | |
204 | struct napi_struct napi; | |
205 | ||
206 | void __iomem *base; | |
207 | u32 reg_esr; | |
208 | u32 reg_ctrl_default; | |
209 | ||
3d42a379 ST |
210 | struct clk *clk_ipg; |
211 | struct clk *clk_per; | |
e955cead | 212 | struct flexcan_platform_data *pdata; |
dda0b3bd | 213 | const struct flexcan_devtype_data *devtype_data; |
30c1e672 HW |
214 | }; |
215 | ||
216 | static struct flexcan_devtype_data fsl_p1010_devtype_data = { | |
4f72e5f0 | 217 | .features = FLEXCAN_HAS_BROKEN_ERR_STATE, |
30c1e672 | 218 | }; |
4f72e5f0 | 219 | static struct flexcan_devtype_data fsl_imx28_devtype_data; |
30c1e672 | 220 | static struct flexcan_devtype_data fsl_imx6q_devtype_data = { |
bb698ca4 | 221 | .features = FLEXCAN_HAS_V10_FEATURES, |
e955cead MKB |
222 | }; |
223 | ||
194b9a4c | 224 | static const struct can_bittiming_const flexcan_bittiming_const = { |
e955cead MKB |
225 | .name = DRV_NAME, |
226 | .tseg1_min = 4, | |
227 | .tseg1_max = 16, | |
228 | .tseg2_min = 2, | |
229 | .tseg2_max = 8, | |
230 | .sjw_max = 4, | |
231 | .brp_min = 1, | |
232 | .brp_max = 256, | |
233 | .brp_inc = 1, | |
234 | }; | |
235 | ||
61e271ee | 236 | /* |
237 | * Abstract off the read/write for arm versus ppc. | |
238 | */ | |
239 | #if defined(__BIG_ENDIAN) | |
240 | static inline u32 flexcan_read(void __iomem *addr) | |
241 | { | |
242 | return in_be32(addr); | |
243 | } | |
244 | ||
245 | static inline void flexcan_write(u32 val, void __iomem *addr) | |
246 | { | |
247 | out_be32(addr, val); | |
248 | } | |
249 | #else | |
250 | static inline u32 flexcan_read(void __iomem *addr) | |
251 | { | |
252 | return readl(addr); | |
253 | } | |
254 | ||
255 | static inline void flexcan_write(u32 val, void __iomem *addr) | |
256 | { | |
257 | writel(val, addr); | |
258 | } | |
259 | #endif | |
260 | ||
e955cead MKB |
261 | /* |
262 | * Swtich transceiver on or off | |
263 | */ | |
264 | static void flexcan_transceiver_switch(const struct flexcan_priv *priv, int on) | |
265 | { | |
266 | if (priv->pdata && priv->pdata->transceiver_switch) | |
267 | priv->pdata->transceiver_switch(on); | |
268 | } | |
269 | ||
270 | static inline int flexcan_has_and_handle_berr(const struct flexcan_priv *priv, | |
271 | u32 reg_esr) | |
272 | { | |
273 | return (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) && | |
274 | (reg_esr & FLEXCAN_ESR_ERR_BUS); | |
275 | } | |
276 | ||
277 | static inline void flexcan_chip_enable(struct flexcan_priv *priv) | |
278 | { | |
279 | struct flexcan_regs __iomem *regs = priv->base; | |
280 | u32 reg; | |
281 | ||
61e271ee | 282 | reg = flexcan_read(®s->mcr); |
e955cead | 283 | reg &= ~FLEXCAN_MCR_MDIS; |
61e271ee | 284 | flexcan_write(reg, ®s->mcr); |
e955cead MKB |
285 | |
286 | udelay(10); | |
287 | } | |
288 | ||
289 | static inline void flexcan_chip_disable(struct flexcan_priv *priv) | |
290 | { | |
291 | struct flexcan_regs __iomem *regs = priv->base; | |
292 | u32 reg; | |
293 | ||
61e271ee | 294 | reg = flexcan_read(®s->mcr); |
e955cead | 295 | reg |= FLEXCAN_MCR_MDIS; |
61e271ee | 296 | flexcan_write(reg, ®s->mcr); |
e955cead MKB |
297 | } |
298 | ||
299 | static int flexcan_get_berr_counter(const struct net_device *dev, | |
300 | struct can_berr_counter *bec) | |
301 | { | |
302 | const struct flexcan_priv *priv = netdev_priv(dev); | |
303 | struct flexcan_regs __iomem *regs = priv->base; | |
61e271ee | 304 | u32 reg = flexcan_read(®s->ecr); |
e955cead MKB |
305 | |
306 | bec->txerr = (reg >> 0) & 0xff; | |
307 | bec->rxerr = (reg >> 8) & 0xff; | |
308 | ||
309 | return 0; | |
310 | } | |
311 | ||
312 | static int flexcan_start_xmit(struct sk_buff *skb, struct net_device *dev) | |
313 | { | |
314 | const struct flexcan_priv *priv = netdev_priv(dev); | |
e955cead MKB |
315 | struct flexcan_regs __iomem *regs = priv->base; |
316 | struct can_frame *cf = (struct can_frame *)skb->data; | |
317 | u32 can_id; | |
318 | u32 ctrl = FLEXCAN_MB_CNT_CODE(0xc) | (cf->can_dlc << 16); | |
319 | ||
320 | if (can_dropped_invalid_skb(dev, skb)) | |
321 | return NETDEV_TX_OK; | |
322 | ||
323 | netif_stop_queue(dev); | |
324 | ||
325 | if (cf->can_id & CAN_EFF_FLAG) { | |
326 | can_id = cf->can_id & CAN_EFF_MASK; | |
327 | ctrl |= FLEXCAN_MB_CNT_IDE | FLEXCAN_MB_CNT_SRR; | |
328 | } else { | |
329 | can_id = (cf->can_id & CAN_SFF_MASK) << 18; | |
330 | } | |
331 | ||
332 | if (cf->can_id & CAN_RTR_FLAG) | |
333 | ctrl |= FLEXCAN_MB_CNT_RTR; | |
334 | ||
335 | if (cf->can_dlc > 0) { | |
336 | u32 data = be32_to_cpup((__be32 *)&cf->data[0]); | |
61e271ee | 337 | flexcan_write(data, ®s->cantxfg[FLEXCAN_TX_BUF_ID].data[0]); |
e955cead MKB |
338 | } |
339 | if (cf->can_dlc > 3) { | |
340 | u32 data = be32_to_cpup((__be32 *)&cf->data[4]); | |
61e271ee | 341 | flexcan_write(data, ®s->cantxfg[FLEXCAN_TX_BUF_ID].data[1]); |
e955cead MKB |
342 | } |
343 | ||
9a123496 RD |
344 | can_put_echo_skb(skb, dev, 0); |
345 | ||
61e271ee | 346 | flexcan_write(can_id, ®s->cantxfg[FLEXCAN_TX_BUF_ID].can_id); |
347 | flexcan_write(ctrl, ®s->cantxfg[FLEXCAN_TX_BUF_ID].can_ctrl); | |
e955cead | 348 | |
e955cead MKB |
349 | return NETDEV_TX_OK; |
350 | } | |
351 | ||
352 | static void do_bus_err(struct net_device *dev, | |
353 | struct can_frame *cf, u32 reg_esr) | |
354 | { | |
355 | struct flexcan_priv *priv = netdev_priv(dev); | |
356 | int rx_errors = 0, tx_errors = 0; | |
357 | ||
358 | cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; | |
359 | ||
360 | if (reg_esr & FLEXCAN_ESR_BIT1_ERR) { | |
aabdfd6a | 361 | netdev_dbg(dev, "BIT1_ERR irq\n"); |
e955cead MKB |
362 | cf->data[2] |= CAN_ERR_PROT_BIT1; |
363 | tx_errors = 1; | |
364 | } | |
365 | if (reg_esr & FLEXCAN_ESR_BIT0_ERR) { | |
aabdfd6a | 366 | netdev_dbg(dev, "BIT0_ERR irq\n"); |
e955cead MKB |
367 | cf->data[2] |= CAN_ERR_PROT_BIT0; |
368 | tx_errors = 1; | |
369 | } | |
370 | if (reg_esr & FLEXCAN_ESR_ACK_ERR) { | |
aabdfd6a | 371 | netdev_dbg(dev, "ACK_ERR irq\n"); |
e955cead MKB |
372 | cf->can_id |= CAN_ERR_ACK; |
373 | cf->data[3] |= CAN_ERR_PROT_LOC_ACK; | |
374 | tx_errors = 1; | |
375 | } | |
376 | if (reg_esr & FLEXCAN_ESR_CRC_ERR) { | |
aabdfd6a | 377 | netdev_dbg(dev, "CRC_ERR irq\n"); |
e955cead MKB |
378 | cf->data[2] |= CAN_ERR_PROT_BIT; |
379 | cf->data[3] |= CAN_ERR_PROT_LOC_CRC_SEQ; | |
380 | rx_errors = 1; | |
381 | } | |
382 | if (reg_esr & FLEXCAN_ESR_FRM_ERR) { | |
aabdfd6a | 383 | netdev_dbg(dev, "FRM_ERR irq\n"); |
e955cead MKB |
384 | cf->data[2] |= CAN_ERR_PROT_FORM; |
385 | rx_errors = 1; | |
386 | } | |
387 | if (reg_esr & FLEXCAN_ESR_STF_ERR) { | |
aabdfd6a | 388 | netdev_dbg(dev, "STF_ERR irq\n"); |
e955cead MKB |
389 | cf->data[2] |= CAN_ERR_PROT_STUFF; |
390 | rx_errors = 1; | |
391 | } | |
392 | ||
393 | priv->can.can_stats.bus_error++; | |
394 | if (rx_errors) | |
395 | dev->stats.rx_errors++; | |
396 | if (tx_errors) | |
397 | dev->stats.tx_errors++; | |
398 | } | |
399 | ||
400 | static int flexcan_poll_bus_err(struct net_device *dev, u32 reg_esr) | |
401 | { | |
402 | struct sk_buff *skb; | |
403 | struct can_frame *cf; | |
404 | ||
405 | skb = alloc_can_err_skb(dev, &cf); | |
406 | if (unlikely(!skb)) | |
407 | return 0; | |
408 | ||
409 | do_bus_err(dev, cf, reg_esr); | |
410 | netif_receive_skb(skb); | |
411 | ||
412 | dev->stats.rx_packets++; | |
413 | dev->stats.rx_bytes += cf->can_dlc; | |
414 | ||
415 | return 1; | |
416 | } | |
417 | ||
418 | static void do_state(struct net_device *dev, | |
419 | struct can_frame *cf, enum can_state new_state) | |
420 | { | |
421 | struct flexcan_priv *priv = netdev_priv(dev); | |
422 | struct can_berr_counter bec; | |
423 | ||
424 | flexcan_get_berr_counter(dev, &bec); | |
425 | ||
426 | switch (priv->can.state) { | |
427 | case CAN_STATE_ERROR_ACTIVE: | |
428 | /* | |
429 | * from: ERROR_ACTIVE | |
430 | * to : ERROR_WARNING, ERROR_PASSIVE, BUS_OFF | |
431 | * => : there was a warning int | |
432 | */ | |
433 | if (new_state >= CAN_STATE_ERROR_WARNING && | |
434 | new_state <= CAN_STATE_BUS_OFF) { | |
aabdfd6a | 435 | netdev_dbg(dev, "Error Warning IRQ\n"); |
e955cead MKB |
436 | priv->can.can_stats.error_warning++; |
437 | ||
438 | cf->can_id |= CAN_ERR_CRTL; | |
439 | cf->data[1] = (bec.txerr > bec.rxerr) ? | |
440 | CAN_ERR_CRTL_TX_WARNING : | |
441 | CAN_ERR_CRTL_RX_WARNING; | |
442 | } | |
443 | case CAN_STATE_ERROR_WARNING: /* fallthrough */ | |
444 | /* | |
445 | * from: ERROR_ACTIVE, ERROR_WARNING | |
446 | * to : ERROR_PASSIVE, BUS_OFF | |
447 | * => : error passive int | |
448 | */ | |
449 | if (new_state >= CAN_STATE_ERROR_PASSIVE && | |
450 | new_state <= CAN_STATE_BUS_OFF) { | |
aabdfd6a | 451 | netdev_dbg(dev, "Error Passive IRQ\n"); |
e955cead MKB |
452 | priv->can.can_stats.error_passive++; |
453 | ||
454 | cf->can_id |= CAN_ERR_CRTL; | |
455 | cf->data[1] = (bec.txerr > bec.rxerr) ? | |
456 | CAN_ERR_CRTL_TX_PASSIVE : | |
457 | CAN_ERR_CRTL_RX_PASSIVE; | |
458 | } | |
459 | break; | |
460 | case CAN_STATE_BUS_OFF: | |
aabdfd6a WG |
461 | netdev_err(dev, "BUG! " |
462 | "hardware recovered automatically from BUS_OFF\n"); | |
e955cead MKB |
463 | break; |
464 | default: | |
465 | break; | |
466 | } | |
467 | ||
468 | /* process state changes depending on the new state */ | |
469 | switch (new_state) { | |
470 | case CAN_STATE_ERROR_ACTIVE: | |
aabdfd6a | 471 | netdev_dbg(dev, "Error Active\n"); |
e955cead MKB |
472 | cf->can_id |= CAN_ERR_PROT; |
473 | cf->data[2] = CAN_ERR_PROT_ACTIVE; | |
474 | break; | |
475 | case CAN_STATE_BUS_OFF: | |
476 | cf->can_id |= CAN_ERR_BUSOFF; | |
477 | can_bus_off(dev); | |
478 | break; | |
479 | default: | |
480 | break; | |
481 | } | |
482 | } | |
483 | ||
484 | static int flexcan_poll_state(struct net_device *dev, u32 reg_esr) | |
485 | { | |
486 | struct flexcan_priv *priv = netdev_priv(dev); | |
487 | struct sk_buff *skb; | |
488 | struct can_frame *cf; | |
489 | enum can_state new_state; | |
490 | int flt; | |
491 | ||
492 | flt = reg_esr & FLEXCAN_ESR_FLT_CONF_MASK; | |
493 | if (likely(flt == FLEXCAN_ESR_FLT_CONF_ACTIVE)) { | |
494 | if (likely(!(reg_esr & (FLEXCAN_ESR_TX_WRN | | |
495 | FLEXCAN_ESR_RX_WRN)))) | |
496 | new_state = CAN_STATE_ERROR_ACTIVE; | |
497 | else | |
498 | new_state = CAN_STATE_ERROR_WARNING; | |
499 | } else if (unlikely(flt == FLEXCAN_ESR_FLT_CONF_PASSIVE)) | |
500 | new_state = CAN_STATE_ERROR_PASSIVE; | |
501 | else | |
502 | new_state = CAN_STATE_BUS_OFF; | |
503 | ||
504 | /* state hasn't changed */ | |
505 | if (likely(new_state == priv->can.state)) | |
506 | return 0; | |
507 | ||
508 | skb = alloc_can_err_skb(dev, &cf); | |
509 | if (unlikely(!skb)) | |
510 | return 0; | |
511 | ||
512 | do_state(dev, cf, new_state); | |
513 | priv->can.state = new_state; | |
514 | netif_receive_skb(skb); | |
515 | ||
516 | dev->stats.rx_packets++; | |
517 | dev->stats.rx_bytes += cf->can_dlc; | |
518 | ||
519 | return 1; | |
520 | } | |
521 | ||
522 | static void flexcan_read_fifo(const struct net_device *dev, | |
523 | struct can_frame *cf) | |
524 | { | |
525 | const struct flexcan_priv *priv = netdev_priv(dev); | |
526 | struct flexcan_regs __iomem *regs = priv->base; | |
527 | struct flexcan_mb __iomem *mb = ®s->cantxfg[0]; | |
528 | u32 reg_ctrl, reg_id; | |
529 | ||
61e271ee | 530 | reg_ctrl = flexcan_read(&mb->can_ctrl); |
531 | reg_id = flexcan_read(&mb->can_id); | |
e955cead MKB |
532 | if (reg_ctrl & FLEXCAN_MB_CNT_IDE) |
533 | cf->can_id = ((reg_id >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG; | |
534 | else | |
535 | cf->can_id = (reg_id >> 18) & CAN_SFF_MASK; | |
536 | ||
537 | if (reg_ctrl & FLEXCAN_MB_CNT_RTR) | |
538 | cf->can_id |= CAN_RTR_FLAG; | |
539 | cf->can_dlc = get_can_dlc((reg_ctrl >> 16) & 0xf); | |
540 | ||
61e271ee | 541 | *(__be32 *)(cf->data + 0) = cpu_to_be32(flexcan_read(&mb->data[0])); |
542 | *(__be32 *)(cf->data + 4) = cpu_to_be32(flexcan_read(&mb->data[1])); | |
e955cead MKB |
543 | |
544 | /* mark as read */ | |
61e271ee | 545 | flexcan_write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, ®s->iflag1); |
546 | flexcan_read(®s->timer); | |
e955cead MKB |
547 | } |
548 | ||
549 | static int flexcan_read_frame(struct net_device *dev) | |
550 | { | |
551 | struct net_device_stats *stats = &dev->stats; | |
552 | struct can_frame *cf; | |
553 | struct sk_buff *skb; | |
554 | ||
555 | skb = alloc_can_skb(dev, &cf); | |
556 | if (unlikely(!skb)) { | |
557 | stats->rx_dropped++; | |
558 | return 0; | |
559 | } | |
560 | ||
561 | flexcan_read_fifo(dev, cf); | |
562 | netif_receive_skb(skb); | |
563 | ||
564 | stats->rx_packets++; | |
565 | stats->rx_bytes += cf->can_dlc; | |
566 | ||
567 | return 1; | |
568 | } | |
569 | ||
570 | static int flexcan_poll(struct napi_struct *napi, int quota) | |
571 | { | |
572 | struct net_device *dev = napi->dev; | |
573 | const struct flexcan_priv *priv = netdev_priv(dev); | |
574 | struct flexcan_regs __iomem *regs = priv->base; | |
575 | u32 reg_iflag1, reg_esr; | |
576 | int work_done = 0; | |
577 | ||
578 | /* | |
579 | * The error bits are cleared on read, | |
580 | * use saved value from irq handler. | |
581 | */ | |
61e271ee | 582 | reg_esr = flexcan_read(®s->esr) | priv->reg_esr; |
e955cead MKB |
583 | |
584 | /* handle state changes */ | |
585 | work_done += flexcan_poll_state(dev, reg_esr); | |
586 | ||
587 | /* handle RX-FIFO */ | |
61e271ee | 588 | reg_iflag1 = flexcan_read(®s->iflag1); |
e955cead MKB |
589 | while (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE && |
590 | work_done < quota) { | |
591 | work_done += flexcan_read_frame(dev); | |
61e271ee | 592 | reg_iflag1 = flexcan_read(®s->iflag1); |
e955cead MKB |
593 | } |
594 | ||
595 | /* report bus errors */ | |
596 | if (flexcan_has_and_handle_berr(priv, reg_esr) && work_done < quota) | |
597 | work_done += flexcan_poll_bus_err(dev, reg_esr); | |
598 | ||
599 | if (work_done < quota) { | |
600 | napi_complete(napi); | |
601 | /* enable IRQs */ | |
61e271ee | 602 | flexcan_write(FLEXCAN_IFLAG_DEFAULT, ®s->imask1); |
603 | flexcan_write(priv->reg_ctrl_default, ®s->ctrl); | |
e955cead MKB |
604 | } |
605 | ||
606 | return work_done; | |
607 | } | |
608 | ||
609 | static irqreturn_t flexcan_irq(int irq, void *dev_id) | |
610 | { | |
611 | struct net_device *dev = dev_id; | |
612 | struct net_device_stats *stats = &dev->stats; | |
613 | struct flexcan_priv *priv = netdev_priv(dev); | |
614 | struct flexcan_regs __iomem *regs = priv->base; | |
615 | u32 reg_iflag1, reg_esr; | |
616 | ||
61e271ee | 617 | reg_iflag1 = flexcan_read(®s->iflag1); |
618 | reg_esr = flexcan_read(®s->esr); | |
6e9d554f WG |
619 | /* ACK all bus error and state change IRQ sources */ |
620 | if (reg_esr & FLEXCAN_ESR_ALL_INT) | |
621 | flexcan_write(reg_esr & FLEXCAN_ESR_ALL_INT, ®s->esr); | |
e955cead MKB |
622 | |
623 | /* | |
624 | * schedule NAPI in case of: | |
625 | * - rx IRQ | |
626 | * - state change IRQ | |
627 | * - bus error IRQ and bus error reporting is activated | |
628 | */ | |
629 | if ((reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE) || | |
630 | (reg_esr & FLEXCAN_ESR_ERR_STATE) || | |
631 | flexcan_has_and_handle_berr(priv, reg_esr)) { | |
632 | /* | |
633 | * The error bits are cleared on read, | |
634 | * save them for later use. | |
635 | */ | |
636 | priv->reg_esr = reg_esr & FLEXCAN_ESR_ERR_BUS; | |
61e271ee | 637 | flexcan_write(FLEXCAN_IFLAG_DEFAULT & |
638 | ~FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, ®s->imask1); | |
639 | flexcan_write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL, | |
e955cead MKB |
640 | ®s->ctrl); |
641 | napi_schedule(&priv->napi); | |
642 | } | |
643 | ||
644 | /* FIFO overflow */ | |
645 | if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_OVERFLOW) { | |
61e271ee | 646 | flexcan_write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW, ®s->iflag1); |
e955cead MKB |
647 | dev->stats.rx_over_errors++; |
648 | dev->stats.rx_errors++; | |
649 | } | |
650 | ||
651 | /* transmission complete interrupt */ | |
652 | if (reg_iflag1 & (1 << FLEXCAN_TX_BUF_ID)) { | |
9a123496 | 653 | stats->tx_bytes += can_get_echo_skb(dev, 0); |
e955cead | 654 | stats->tx_packets++; |
61e271ee | 655 | flexcan_write((1 << FLEXCAN_TX_BUF_ID), ®s->iflag1); |
e955cead MKB |
656 | netif_wake_queue(dev); |
657 | } | |
658 | ||
659 | return IRQ_HANDLED; | |
660 | } | |
661 | ||
662 | static void flexcan_set_bittiming(struct net_device *dev) | |
663 | { | |
664 | const struct flexcan_priv *priv = netdev_priv(dev); | |
665 | const struct can_bittiming *bt = &priv->can.bittiming; | |
666 | struct flexcan_regs __iomem *regs = priv->base; | |
667 | u32 reg; | |
668 | ||
61e271ee | 669 | reg = flexcan_read(®s->ctrl); |
e955cead MKB |
670 | reg &= ~(FLEXCAN_CTRL_PRESDIV(0xff) | |
671 | FLEXCAN_CTRL_RJW(0x3) | | |
672 | FLEXCAN_CTRL_PSEG1(0x7) | | |
673 | FLEXCAN_CTRL_PSEG2(0x7) | | |
674 | FLEXCAN_CTRL_PROPSEG(0x7) | | |
675 | FLEXCAN_CTRL_LPB | | |
676 | FLEXCAN_CTRL_SMP | | |
677 | FLEXCAN_CTRL_LOM); | |
678 | ||
679 | reg |= FLEXCAN_CTRL_PRESDIV(bt->brp - 1) | | |
680 | FLEXCAN_CTRL_PSEG1(bt->phase_seg1 - 1) | | |
681 | FLEXCAN_CTRL_PSEG2(bt->phase_seg2 - 1) | | |
682 | FLEXCAN_CTRL_RJW(bt->sjw - 1) | | |
683 | FLEXCAN_CTRL_PROPSEG(bt->prop_seg - 1); | |
684 | ||
685 | if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) | |
686 | reg |= FLEXCAN_CTRL_LPB; | |
687 | if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) | |
688 | reg |= FLEXCAN_CTRL_LOM; | |
689 | if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) | |
690 | reg |= FLEXCAN_CTRL_SMP; | |
691 | ||
aabdfd6a | 692 | netdev_info(dev, "writing ctrl=0x%08x\n", reg); |
61e271ee | 693 | flexcan_write(reg, ®s->ctrl); |
e955cead MKB |
694 | |
695 | /* print chip status */ | |
aabdfd6a WG |
696 | netdev_dbg(dev, "%s: mcr=0x%08x ctrl=0x%08x\n", __func__, |
697 | flexcan_read(®s->mcr), flexcan_read(®s->ctrl)); | |
e955cead MKB |
698 | } |
699 | ||
700 | /* | |
701 | * flexcan_chip_start | |
702 | * | |
703 | * this functions is entered with clocks enabled | |
704 | * | |
705 | */ | |
706 | static int flexcan_chip_start(struct net_device *dev) | |
707 | { | |
708 | struct flexcan_priv *priv = netdev_priv(dev); | |
709 | struct flexcan_regs __iomem *regs = priv->base; | |
710 | unsigned int i; | |
711 | int err; | |
712 | u32 reg_mcr, reg_ctrl; | |
713 | ||
714 | /* enable module */ | |
715 | flexcan_chip_enable(priv); | |
716 | ||
717 | /* soft reset */ | |
61e271ee | 718 | flexcan_write(FLEXCAN_MCR_SOFTRST, ®s->mcr); |
e955cead MKB |
719 | udelay(10); |
720 | ||
61e271ee | 721 | reg_mcr = flexcan_read(®s->mcr); |
e955cead | 722 | if (reg_mcr & FLEXCAN_MCR_SOFTRST) { |
aabdfd6a WG |
723 | netdev_err(dev, "Failed to softreset can module (mcr=0x%08x)\n", |
724 | reg_mcr); | |
e955cead MKB |
725 | err = -ENODEV; |
726 | goto out; | |
727 | } | |
728 | ||
729 | flexcan_set_bittiming(dev); | |
730 | ||
731 | /* | |
732 | * MCR | |
733 | * | |
734 | * enable freeze | |
735 | * enable fifo | |
736 | * halt now | |
737 | * only supervisor access | |
738 | * enable warning int | |
739 | * choose format C | |
9a123496 | 740 | * disable local echo |
e955cead MKB |
741 | * |
742 | */ | |
61e271ee | 743 | reg_mcr = flexcan_read(®s->mcr); |
e955cead MKB |
744 | reg_mcr |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_FEN | FLEXCAN_MCR_HALT | |
745 | FLEXCAN_MCR_SUPV | FLEXCAN_MCR_WRN_EN | | |
9a123496 | 746 | FLEXCAN_MCR_IDAM_C | FLEXCAN_MCR_SRX_DIS; |
aabdfd6a | 747 | netdev_dbg(dev, "%s: writing mcr=0x%08x", __func__, reg_mcr); |
61e271ee | 748 | flexcan_write(reg_mcr, ®s->mcr); |
e955cead MKB |
749 | |
750 | /* | |
751 | * CTRL | |
752 | * | |
753 | * disable timer sync feature | |
754 | * | |
755 | * disable auto busoff recovery | |
756 | * transmit lowest buffer first | |
757 | * | |
758 | * enable tx and rx warning interrupt | |
759 | * enable bus off interrupt | |
760 | * (== FLEXCAN_CTRL_ERR_STATE) | |
e955cead | 761 | */ |
61e271ee | 762 | reg_ctrl = flexcan_read(®s->ctrl); |
e955cead MKB |
763 | reg_ctrl &= ~FLEXCAN_CTRL_TSYN; |
764 | reg_ctrl |= FLEXCAN_CTRL_BOFF_REC | FLEXCAN_CTRL_LBUF | | |
4f72e5f0 WG |
765 | FLEXCAN_CTRL_ERR_STATE; |
766 | /* | |
767 | * enable the "error interrupt" (FLEXCAN_CTRL_ERR_MSK), | |
768 | * on most Flexcan cores, too. Otherwise we don't get | |
769 | * any error warning or passive interrupts. | |
770 | */ | |
771 | if (priv->devtype_data->features & FLEXCAN_HAS_BROKEN_ERR_STATE || | |
772 | priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) | |
773 | reg_ctrl |= FLEXCAN_CTRL_ERR_MSK; | |
e955cead MKB |
774 | |
775 | /* save for later use */ | |
776 | priv->reg_ctrl_default = reg_ctrl; | |
aabdfd6a | 777 | netdev_dbg(dev, "%s: writing ctrl=0x%08x", __func__, reg_ctrl); |
61e271ee | 778 | flexcan_write(reg_ctrl, ®s->ctrl); |
e955cead MKB |
779 | |
780 | for (i = 0; i < ARRAY_SIZE(regs->cantxfg); i++) { | |
61e271ee | 781 | flexcan_write(0, ®s->cantxfg[i].can_ctrl); |
782 | flexcan_write(0, ®s->cantxfg[i].can_id); | |
783 | flexcan_write(0, ®s->cantxfg[i].data[0]); | |
784 | flexcan_write(0, ®s->cantxfg[i].data[1]); | |
e955cead MKB |
785 | |
786 | /* put MB into rx queue */ | |
61e271ee | 787 | flexcan_write(FLEXCAN_MB_CNT_CODE(0x4), |
788 | ®s->cantxfg[i].can_ctrl); | |
e955cead MKB |
789 | } |
790 | ||
791 | /* acceptance mask/acceptance code (accept everything) */ | |
61e271ee | 792 | flexcan_write(0x0, ®s->rxgmask); |
793 | flexcan_write(0x0, ®s->rx14mask); | |
794 | flexcan_write(0x0, ®s->rx15mask); | |
e955cead | 795 | |
4f72e5f0 | 796 | if (priv->devtype_data->features & FLEXCAN_HAS_V10_FEATURES) |
30c1e672 HW |
797 | flexcan_write(0x0, ®s->rxfgmask); |
798 | ||
e955cead MKB |
799 | flexcan_transceiver_switch(priv, 1); |
800 | ||
801 | /* synchronize with the can bus */ | |
61e271ee | 802 | reg_mcr = flexcan_read(®s->mcr); |
e955cead | 803 | reg_mcr &= ~FLEXCAN_MCR_HALT; |
61e271ee | 804 | flexcan_write(reg_mcr, ®s->mcr); |
e955cead MKB |
805 | |
806 | priv->can.state = CAN_STATE_ERROR_ACTIVE; | |
807 | ||
808 | /* enable FIFO interrupts */ | |
61e271ee | 809 | flexcan_write(FLEXCAN_IFLAG_DEFAULT, ®s->imask1); |
e955cead MKB |
810 | |
811 | /* print chip status */ | |
aabdfd6a WG |
812 | netdev_dbg(dev, "%s: reading mcr=0x%08x ctrl=0x%08x\n", __func__, |
813 | flexcan_read(®s->mcr), flexcan_read(®s->ctrl)); | |
e955cead MKB |
814 | |
815 | return 0; | |
816 | ||
817 | out: | |
818 | flexcan_chip_disable(priv); | |
819 | return err; | |
820 | } | |
821 | ||
822 | /* | |
823 | * flexcan_chip_stop | |
824 | * | |
825 | * this functions is entered with clocks enabled | |
826 | * | |
827 | */ | |
828 | static void flexcan_chip_stop(struct net_device *dev) | |
829 | { | |
830 | struct flexcan_priv *priv = netdev_priv(dev); | |
831 | struct flexcan_regs __iomem *regs = priv->base; | |
832 | u32 reg; | |
833 | ||
834 | /* Disable all interrupts */ | |
61e271ee | 835 | flexcan_write(0, ®s->imask1); |
e955cead MKB |
836 | |
837 | /* Disable + halt module */ | |
61e271ee | 838 | reg = flexcan_read(®s->mcr); |
e955cead | 839 | reg |= FLEXCAN_MCR_MDIS | FLEXCAN_MCR_HALT; |
61e271ee | 840 | flexcan_write(reg, ®s->mcr); |
e955cead MKB |
841 | |
842 | flexcan_transceiver_switch(priv, 0); | |
843 | priv->can.state = CAN_STATE_STOPPED; | |
844 | ||
845 | return; | |
846 | } | |
847 | ||
848 | static int flexcan_open(struct net_device *dev) | |
849 | { | |
850 | struct flexcan_priv *priv = netdev_priv(dev); | |
851 | int err; | |
852 | ||
3d42a379 ST |
853 | clk_prepare_enable(priv->clk_ipg); |
854 | clk_prepare_enable(priv->clk_per); | |
e955cead MKB |
855 | |
856 | err = open_candev(dev); | |
857 | if (err) | |
858 | goto out; | |
859 | ||
860 | err = request_irq(dev->irq, flexcan_irq, IRQF_SHARED, dev->name, dev); | |
861 | if (err) | |
862 | goto out_close; | |
863 | ||
864 | /* start chip and queuing */ | |
865 | err = flexcan_chip_start(dev); | |
866 | if (err) | |
867 | goto out_close; | |
868 | napi_enable(&priv->napi); | |
869 | netif_start_queue(dev); | |
870 | ||
871 | return 0; | |
872 | ||
873 | out_close: | |
874 | close_candev(dev); | |
875 | out: | |
3d42a379 ST |
876 | clk_disable_unprepare(priv->clk_per); |
877 | clk_disable_unprepare(priv->clk_ipg); | |
e955cead MKB |
878 | |
879 | return err; | |
880 | } | |
881 | ||
882 | static int flexcan_close(struct net_device *dev) | |
883 | { | |
884 | struct flexcan_priv *priv = netdev_priv(dev); | |
885 | ||
886 | netif_stop_queue(dev); | |
887 | napi_disable(&priv->napi); | |
888 | flexcan_chip_stop(dev); | |
889 | ||
890 | free_irq(dev->irq, dev); | |
3d42a379 ST |
891 | clk_disable_unprepare(priv->clk_per); |
892 | clk_disable_unprepare(priv->clk_ipg); | |
e955cead MKB |
893 | |
894 | close_candev(dev); | |
895 | ||
896 | return 0; | |
897 | } | |
898 | ||
899 | static int flexcan_set_mode(struct net_device *dev, enum can_mode mode) | |
900 | { | |
901 | int err; | |
902 | ||
903 | switch (mode) { | |
904 | case CAN_MODE_START: | |
905 | err = flexcan_chip_start(dev); | |
906 | if (err) | |
907 | return err; | |
908 | ||
909 | netif_wake_queue(dev); | |
910 | break; | |
911 | ||
912 | default: | |
913 | return -EOPNOTSUPP; | |
914 | } | |
915 | ||
916 | return 0; | |
917 | } | |
918 | ||
919 | static const struct net_device_ops flexcan_netdev_ops = { | |
920 | .ndo_open = flexcan_open, | |
921 | .ndo_stop = flexcan_close, | |
922 | .ndo_start_xmit = flexcan_start_xmit, | |
923 | }; | |
924 | ||
925 | static int __devinit register_flexcandev(struct net_device *dev) | |
926 | { | |
927 | struct flexcan_priv *priv = netdev_priv(dev); | |
928 | struct flexcan_regs __iomem *regs = priv->base; | |
929 | u32 reg, err; | |
930 | ||
3d42a379 ST |
931 | clk_prepare_enable(priv->clk_ipg); |
932 | clk_prepare_enable(priv->clk_per); | |
e955cead MKB |
933 | |
934 | /* select "bus clock", chip must be disabled */ | |
935 | flexcan_chip_disable(priv); | |
61e271ee | 936 | reg = flexcan_read(®s->ctrl); |
e955cead | 937 | reg |= FLEXCAN_CTRL_CLK_SRC; |
61e271ee | 938 | flexcan_write(reg, ®s->ctrl); |
e955cead MKB |
939 | |
940 | flexcan_chip_enable(priv); | |
941 | ||
942 | /* set freeze, halt and activate FIFO, restrict register access */ | |
61e271ee | 943 | reg = flexcan_read(®s->mcr); |
e955cead MKB |
944 | reg |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT | |
945 | FLEXCAN_MCR_FEN | FLEXCAN_MCR_SUPV; | |
61e271ee | 946 | flexcan_write(reg, ®s->mcr); |
e955cead MKB |
947 | |
948 | /* | |
949 | * Currently we only support newer versions of this core | |
950 | * featuring a RX FIFO. Older cores found on some Coldfire | |
951 | * derivates are not yet supported. | |
952 | */ | |
61e271ee | 953 | reg = flexcan_read(®s->mcr); |
e955cead | 954 | if (!(reg & FLEXCAN_MCR_FEN)) { |
aabdfd6a | 955 | netdev_err(dev, "Could not enable RX FIFO, unsupported core\n"); |
e955cead MKB |
956 | err = -ENODEV; |
957 | goto out; | |
958 | } | |
959 | ||
960 | err = register_candev(dev); | |
961 | ||
962 | out: | |
963 | /* disable core and turn off clocks */ | |
964 | flexcan_chip_disable(priv); | |
3d42a379 ST |
965 | clk_disable_unprepare(priv->clk_per); |
966 | clk_disable_unprepare(priv->clk_ipg); | |
e955cead MKB |
967 | |
968 | return err; | |
969 | } | |
970 | ||
971 | static void __devexit unregister_flexcandev(struct net_device *dev) | |
972 | { | |
973 | unregister_candev(dev); | |
974 | } | |
975 | ||
30c1e672 HW |
976 | static const struct of_device_id flexcan_of_match[] = { |
977 | { .compatible = "fsl,p1010-flexcan", .data = &fsl_p1010_devtype_data, }, | |
4f72e5f0 | 978 | { .compatible = "fsl,imx28-flexcan", .data = &fsl_imx28_devtype_data, }, |
30c1e672 HW |
979 | { .compatible = "fsl,imx6q-flexcan", .data = &fsl_imx6q_devtype_data, }, |
980 | { /* sentinel */ }, | |
981 | }; | |
4358a9dc | 982 | MODULE_DEVICE_TABLE(of, flexcan_of_match); |
30c1e672 HW |
983 | |
984 | static const struct platform_device_id flexcan_id_table[] = { | |
985 | { .name = "flexcan", .driver_data = (kernel_ulong_t)&fsl_p1010_devtype_data, }, | |
986 | { /* sentinel */ }, | |
987 | }; | |
4358a9dc | 988 | MODULE_DEVICE_TABLE(platform, flexcan_id_table); |
30c1e672 | 989 | |
e955cead MKB |
990 | static int __devinit flexcan_probe(struct platform_device *pdev) |
991 | { | |
30c1e672 | 992 | const struct of_device_id *of_id; |
dda0b3bd | 993 | const struct flexcan_devtype_data *devtype_data; |
e955cead MKB |
994 | struct net_device *dev; |
995 | struct flexcan_priv *priv; | |
996 | struct resource *mem; | |
3d42a379 | 997 | struct clk *clk_ipg = NULL, *clk_per = NULL; |
a53157c2 | 998 | struct pinctrl *pinctrl; |
e955cead MKB |
999 | void __iomem *base; |
1000 | resource_size_t mem_size; | |
1001 | int err, irq; | |
97efe9ae | 1002 | u32 clock_freq = 0; |
1003 | ||
a53157c2 SG |
1004 | pinctrl = devm_pinctrl_get_select_default(&pdev->dev); |
1005 | if (IS_ERR(pinctrl)) | |
1006 | return PTR_ERR(pinctrl); | |
1007 | ||
afc016d8 HW |
1008 | if (pdev->dev.of_node) |
1009 | of_property_read_u32(pdev->dev.of_node, | |
1010 | "clock-frequency", &clock_freq); | |
97efe9ae | 1011 | |
1012 | if (!clock_freq) { | |
3d42a379 ST |
1013 | clk_ipg = devm_clk_get(&pdev->dev, "ipg"); |
1014 | if (IS_ERR(clk_ipg)) { | |
1015 | dev_err(&pdev->dev, "no ipg clock defined\n"); | |
1016 | err = PTR_ERR(clk_ipg); | |
1017 | goto failed_clock; | |
1018 | } | |
1019 | clock_freq = clk_get_rate(clk_ipg); | |
1020 | ||
1021 | clk_per = devm_clk_get(&pdev->dev, "per"); | |
1022 | if (IS_ERR(clk_per)) { | |
1023 | dev_err(&pdev->dev, "no per clock defined\n"); | |
1024 | err = PTR_ERR(clk_per); | |
97efe9ae | 1025 | goto failed_clock; |
1026 | } | |
e955cead MKB |
1027 | } |
1028 | ||
1029 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1030 | irq = platform_get_irq(pdev, 0); | |
1031 | if (!mem || irq <= 0) { | |
1032 | err = -ENODEV; | |
1033 | goto failed_get; | |
1034 | } | |
1035 | ||
1036 | mem_size = resource_size(mem); | |
1037 | if (!request_mem_region(mem->start, mem_size, pdev->name)) { | |
1038 | err = -EBUSY; | |
2e4ceec4 | 1039 | goto failed_get; |
e955cead MKB |
1040 | } |
1041 | ||
1042 | base = ioremap(mem->start, mem_size); | |
1043 | if (!base) { | |
1044 | err = -ENOMEM; | |
1045 | goto failed_map; | |
1046 | } | |
1047 | ||
9a123496 | 1048 | dev = alloc_candev(sizeof(struct flexcan_priv), 1); |
e955cead MKB |
1049 | if (!dev) { |
1050 | err = -ENOMEM; | |
1051 | goto failed_alloc; | |
1052 | } | |
1053 | ||
30c1e672 HW |
1054 | of_id = of_match_device(flexcan_of_match, &pdev->dev); |
1055 | if (of_id) { | |
1056 | devtype_data = of_id->data; | |
1057 | } else if (pdev->id_entry->driver_data) { | |
1058 | devtype_data = (struct flexcan_devtype_data *) | |
1059 | pdev->id_entry->driver_data; | |
1060 | } else { | |
1061 | err = -ENODEV; | |
1062 | goto failed_devtype; | |
1063 | } | |
1064 | ||
e955cead MKB |
1065 | dev->netdev_ops = &flexcan_netdev_ops; |
1066 | dev->irq = irq; | |
9a123496 | 1067 | dev->flags |= IFF_ECHO; |
e955cead MKB |
1068 | |
1069 | priv = netdev_priv(dev); | |
97efe9ae | 1070 | priv->can.clock.freq = clock_freq; |
e955cead MKB |
1071 | priv->can.bittiming_const = &flexcan_bittiming_const; |
1072 | priv->can.do_set_mode = flexcan_set_mode; | |
1073 | priv->can.do_get_berr_counter = flexcan_get_berr_counter; | |
1074 | priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK | | |
1075 | CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_3_SAMPLES | | |
1076 | CAN_CTRLMODE_BERR_REPORTING; | |
1077 | priv->base = base; | |
1078 | priv->dev = dev; | |
3d42a379 ST |
1079 | priv->clk_ipg = clk_ipg; |
1080 | priv->clk_per = clk_per; | |
e955cead | 1081 | priv->pdata = pdev->dev.platform_data; |
30c1e672 | 1082 | priv->devtype_data = devtype_data; |
e955cead MKB |
1083 | |
1084 | netif_napi_add(dev, &priv->napi, flexcan_poll, FLEXCAN_NAPI_WEIGHT); | |
1085 | ||
1086 | dev_set_drvdata(&pdev->dev, dev); | |
1087 | SET_NETDEV_DEV(dev, &pdev->dev); | |
1088 | ||
1089 | err = register_flexcandev(dev); | |
1090 | if (err) { | |
1091 | dev_err(&pdev->dev, "registering netdev failed\n"); | |
1092 | goto failed_register; | |
1093 | } | |
1094 | ||
1095 | dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%d)\n", | |
1096 | priv->base, dev->irq); | |
1097 | ||
1098 | return 0; | |
1099 | ||
1100 | failed_register: | |
30c1e672 | 1101 | failed_devtype: |
e955cead MKB |
1102 | free_candev(dev); |
1103 | failed_alloc: | |
1104 | iounmap(base); | |
1105 | failed_map: | |
1106 | release_mem_region(mem->start, mem_size); | |
e955cead MKB |
1107 | failed_get: |
1108 | failed_clock: | |
1109 | return err; | |
1110 | } | |
1111 | ||
1112 | static int __devexit flexcan_remove(struct platform_device *pdev) | |
1113 | { | |
1114 | struct net_device *dev = platform_get_drvdata(pdev); | |
1115 | struct flexcan_priv *priv = netdev_priv(dev); | |
1116 | struct resource *mem; | |
1117 | ||
1118 | unregister_flexcandev(dev); | |
1119 | platform_set_drvdata(pdev, NULL); | |
e955cead MKB |
1120 | iounmap(priv->base); |
1121 | ||
1122 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1123 | release_mem_region(mem->start, resource_size(mem)); | |
1124 | ||
9a27586d MKB |
1125 | free_candev(dev); |
1126 | ||
e955cead MKB |
1127 | return 0; |
1128 | } | |
1129 | ||
8b5e218d EB |
1130 | #ifdef CONFIG_PM |
1131 | static int flexcan_suspend(struct platform_device *pdev, pm_message_t state) | |
1132 | { | |
1133 | struct net_device *dev = platform_get_drvdata(pdev); | |
1134 | struct flexcan_priv *priv = netdev_priv(dev); | |
1135 | ||
1136 | flexcan_chip_disable(priv); | |
1137 | ||
1138 | if (netif_running(dev)) { | |
1139 | netif_stop_queue(dev); | |
1140 | netif_device_detach(dev); | |
1141 | } | |
1142 | priv->can.state = CAN_STATE_SLEEPING; | |
1143 | ||
1144 | return 0; | |
1145 | } | |
1146 | ||
1147 | static int flexcan_resume(struct platform_device *pdev) | |
1148 | { | |
1149 | struct net_device *dev = platform_get_drvdata(pdev); | |
1150 | struct flexcan_priv *priv = netdev_priv(dev); | |
1151 | ||
1152 | priv->can.state = CAN_STATE_ERROR_ACTIVE; | |
1153 | if (netif_running(dev)) { | |
1154 | netif_device_attach(dev); | |
1155 | netif_start_queue(dev); | |
1156 | } | |
1157 | flexcan_chip_enable(priv); | |
1158 | ||
1159 | return 0; | |
1160 | } | |
1161 | #else | |
1162 | #define flexcan_suspend NULL | |
1163 | #define flexcan_resume NULL | |
1164 | #endif | |
1165 | ||
e955cead | 1166 | static struct platform_driver flexcan_driver = { |
c8aef4cb | 1167 | .driver = { |
1168 | .name = DRV_NAME, | |
1169 | .owner = THIS_MODULE, | |
1170 | .of_match_table = flexcan_of_match, | |
1171 | }, | |
e955cead MKB |
1172 | .probe = flexcan_probe, |
1173 | .remove = __devexit_p(flexcan_remove), | |
8b5e218d EB |
1174 | .suspend = flexcan_suspend, |
1175 | .resume = flexcan_resume, | |
30c1e672 | 1176 | .id_table = flexcan_id_table, |
e955cead MKB |
1177 | }; |
1178 | ||
871d3372 | 1179 | module_platform_driver(flexcan_driver); |
e955cead MKB |
1180 | |
1181 | MODULE_AUTHOR("Sascha Hauer <kernel@pengutronix.de>, " | |
1182 | "Marc Kleine-Budde <kernel@pengutronix.de>"); | |
1183 | MODULE_LICENSE("GPL v2"); | |
1184 | MODULE_DESCRIPTION("CAN port driver for flexcan based chip"); |