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net: fec: adopt pinctrl support
[deliverable/linux.git] / drivers / net / can / flexcan.c
CommitLineData
e955cead
MKB		 1/*
2 * flexcan.c - FLEXCAN CAN controller driver
3 *
4 * Copyright (c) 2005-2006 Varma Electronics Oy
5 * Copyright (c) 2009 Sascha Hauer, Pengutronix
6 * Copyright (c) 2010 Marc Kleine-Budde, Pengutronix
7 *
8 * Based on code originally by Andrey Volkov <avolkov@varma-el.com>
9 *
10 * LICENCE:
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation version 2.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 */
21
22#include <linux/netdevice.h>
23#include <linux/can.h>
24#include <linux/can/dev.h>
25#include <linux/can/error.h>
26#include <linux/can/platform/flexcan.h>
27#include <linux/clk.h>
28#include <linux/delay.h>
29#include <linux/if_arp.h>
30#include <linux/if_ether.h>
31#include <linux/interrupt.h>
32#include <linux/io.h>
33#include <linux/kernel.h>
34#include <linux/list.h>
35#include <linux/module.h>
97efe9ae 36#include <linux/of.h>
e955cead
MKB		 37#include <linux/platform_device.h>
38
e955cead
MKB		 39#define DRV_NAME "flexcan"
40
41/* 8 for RX fifo and 2 error handling */
42#define FLEXCAN_NAPI_WEIGHT (8 + 2)
43
44/* FLEXCAN module configuration register (CANMCR) bits */
45#define FLEXCAN_MCR_MDIS BIT(31)
46#define FLEXCAN_MCR_FRZ BIT(30)
47#define FLEXCAN_MCR_FEN BIT(29)
48#define FLEXCAN_MCR_HALT BIT(28)
49#define FLEXCAN_MCR_NOT_RDY BIT(27)
50#define FLEXCAN_MCR_WAK_MSK BIT(26)
51#define FLEXCAN_MCR_SOFTRST BIT(25)
52#define FLEXCAN_MCR_FRZ_ACK BIT(24)
53#define FLEXCAN_MCR_SUPV BIT(23)
54#define FLEXCAN_MCR_SLF_WAK BIT(22)
55#define FLEXCAN_MCR_WRN_EN BIT(21)
56#define FLEXCAN_MCR_LPM_ACK BIT(20)
57#define FLEXCAN_MCR_WAK_SRC BIT(19)
58#define FLEXCAN_MCR_DOZE BIT(18)
59#define FLEXCAN_MCR_SRX_DIS BIT(17)
60#define FLEXCAN_MCR_BCC BIT(16)
61#define FLEXCAN_MCR_LPRIO_EN BIT(13)
62#define FLEXCAN_MCR_AEN BIT(12)
63#define FLEXCAN_MCR_MAXMB(x) ((x) & 0xf)
64#define FLEXCAN_MCR_IDAM_A (0 << 8)
65#define FLEXCAN_MCR_IDAM_B (1 << 8)
66#define FLEXCAN_MCR_IDAM_C (2 << 8)
67#define FLEXCAN_MCR_IDAM_D (3 << 8)
68
69/* FLEXCAN control register (CANCTRL) bits */
70#define FLEXCAN_CTRL_PRESDIV(x) (((x) & 0xff) << 24)
71#define FLEXCAN_CTRL_RJW(x) (((x) & 0x03) << 22)
72#define FLEXCAN_CTRL_PSEG1(x) (((x) & 0x07) << 19)
73#define FLEXCAN_CTRL_PSEG2(x) (((x) & 0x07) << 16)
74#define FLEXCAN_CTRL_BOFF_MSK BIT(15)
75#define FLEXCAN_CTRL_ERR_MSK BIT(14)
76#define FLEXCAN_CTRL_CLK_SRC BIT(13)
77#define FLEXCAN_CTRL_LPB BIT(12)
78#define FLEXCAN_CTRL_TWRN_MSK BIT(11)
79#define FLEXCAN_CTRL_RWRN_MSK BIT(10)
80#define FLEXCAN_CTRL_SMP BIT(7)
81#define FLEXCAN_CTRL_BOFF_REC BIT(6)
82#define FLEXCAN_CTRL_TSYN BIT(5)
83#define FLEXCAN_CTRL_LBUF BIT(4)
84#define FLEXCAN_CTRL_LOM BIT(3)
85#define FLEXCAN_CTRL_PROPSEG(x) ((x) & 0x07)
86#define FLEXCAN_CTRL_ERR_BUS (FLEXCAN_CTRL_ERR_MSK)
87#define FLEXCAN_CTRL_ERR_STATE \
88 (FLEXCAN_CTRL_TWRN_MSK | FLEXCAN_CTRL_RWRN_MSK | \
89 FLEXCAN_CTRL_BOFF_MSK)
90#define FLEXCAN_CTRL_ERR_ALL \
91 (FLEXCAN_CTRL_ERR_BUS | FLEXCAN_CTRL_ERR_STATE)
92
93/* FLEXCAN error and status register (ESR) bits */
94#define FLEXCAN_ESR_TWRN_INT BIT(17)
95#define FLEXCAN_ESR_RWRN_INT BIT(16)
96#define FLEXCAN_ESR_BIT1_ERR BIT(15)
97#define FLEXCAN_ESR_BIT0_ERR BIT(14)
98#define FLEXCAN_ESR_ACK_ERR BIT(13)
99#define FLEXCAN_ESR_CRC_ERR BIT(12)
100#define FLEXCAN_ESR_FRM_ERR BIT(11)
101#define FLEXCAN_ESR_STF_ERR BIT(10)
102#define FLEXCAN_ESR_TX_WRN BIT(9)
103#define FLEXCAN_ESR_RX_WRN BIT(8)
104#define FLEXCAN_ESR_IDLE BIT(7)
105#define FLEXCAN_ESR_TXRX BIT(6)
106#define FLEXCAN_EST_FLT_CONF_SHIFT (4)
107#define FLEXCAN_ESR_FLT_CONF_MASK (0x3 << FLEXCAN_EST_FLT_CONF_SHIFT)
108#define FLEXCAN_ESR_FLT_CONF_ACTIVE (0x0 << FLEXCAN_EST_FLT_CONF_SHIFT)
109#define FLEXCAN_ESR_FLT_CONF_PASSIVE (0x1 << FLEXCAN_EST_FLT_CONF_SHIFT)
110#define FLEXCAN_ESR_BOFF_INT BIT(2)
111#define FLEXCAN_ESR_ERR_INT BIT(1)
112#define FLEXCAN_ESR_WAK_INT BIT(0)
113#define FLEXCAN_ESR_ERR_BUS \
114 (FLEXCAN_ESR_BIT1_ERR | FLEXCAN_ESR_BIT0_ERR | \
115 FLEXCAN_ESR_ACK_ERR | FLEXCAN_ESR_CRC_ERR | \
116 FLEXCAN_ESR_FRM_ERR | FLEXCAN_ESR_STF_ERR)
117#define FLEXCAN_ESR_ERR_STATE \
118 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | FLEXCAN_ESR_BOFF_INT)
119#define FLEXCAN_ESR_ERR_ALL \
120 (FLEXCAN_ESR_ERR_BUS | FLEXCAN_ESR_ERR_STATE)
6e9d554f
WG		 121#define FLEXCAN_ESR_ALL_INT \
122 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | \
123 FLEXCAN_ESR_BOFF_INT | FLEXCAN_ESR_ERR_INT)
e955cead
MKB		 124
125/* FLEXCAN interrupt flag register (IFLAG) bits */
126#define FLEXCAN_TX_BUF_ID 8
127#define FLEXCAN_IFLAG_BUF(x) BIT(x)
128#define FLEXCAN_IFLAG_RX_FIFO_OVERFLOW BIT(7)
129#define FLEXCAN_IFLAG_RX_FIFO_WARN BIT(6)
130#define FLEXCAN_IFLAG_RX_FIFO_AVAILABLE BIT(5)
131#define FLEXCAN_IFLAG_DEFAULT \
132 (FLEXCAN_IFLAG_RX_FIFO_OVERFLOW | FLEXCAN_IFLAG_RX_FIFO_AVAILABLE | \
133 FLEXCAN_IFLAG_BUF(FLEXCAN_TX_BUF_ID))
134
135/* FLEXCAN message buffers */
136#define FLEXCAN_MB_CNT_CODE(x) (((x) & 0xf) << 24)
137#define FLEXCAN_MB_CNT_SRR BIT(22)
138#define FLEXCAN_MB_CNT_IDE BIT(21)
139#define FLEXCAN_MB_CNT_RTR BIT(20)
140#define FLEXCAN_MB_CNT_LENGTH(x) (((x) & 0xf) << 16)
141#define FLEXCAN_MB_CNT_TIMESTAMP(x) ((x) & 0xffff)
142
143#define FLEXCAN_MB_CODE_MASK (0xf0ffffff)
144
145/* Structure of the message buffer */
146struct flexcan_mb {
147 u32 can_ctrl;
148 u32 can_id;
149 u32 data[2];
150};
151
152/* Structure of the hardware registers */
153struct flexcan_regs {
154 u32 mcr; /* 0x00 */
155 u32 ctrl; /* 0x04 */
156 u32 timer; /* 0x08 */
157 u32 _reserved1; /* 0x0c */
158 u32 rxgmask; /* 0x10 */
159 u32 rx14mask; /* 0x14 */
160 u32 rx15mask; /* 0x18 */
161 u32 ecr; /* 0x1c */
162 u32 esr; /* 0x20 */
163 u32 imask2; /* 0x24 */
164 u32 imask1; /* 0x28 */
165 u32 iflag2; /* 0x2c */
166 u32 iflag1; /* 0x30 */
167 u32 _reserved2[19];
168 struct flexcan_mb cantxfg[64];
169};
170
171struct flexcan_priv {
172 struct can_priv can;
173 struct net_device *dev;
174 struct napi_struct napi;
175
176 void __iomem *base;
177 u32 reg_esr;
178 u32 reg_ctrl_default;
179
180 struct clk *clk;
181 struct flexcan_platform_data *pdata;
182};
183
184static struct can_bittiming_const flexcan_bittiming_const = {
185 .name = DRV_NAME,
186 .tseg1_min = 4,
187 .tseg1_max = 16,
188 .tseg2_min = 2,
189 .tseg2_max = 8,
190 .sjw_max = 4,
191 .brp_min = 1,
192 .brp_max = 256,
193 .brp_inc = 1,
194};
195
61e271ee 196/*
197 * Abstract off the read/write for arm versus ppc.
198 */
199#if defined(__BIG_ENDIAN)
200static inline u32 flexcan_read(void __iomem *addr)
201{
202 return in_be32(addr);
203}
204
205static inline void flexcan_write(u32 val, void __iomem *addr)
206{
207 out_be32(addr, val);
208}
209#else
210static inline u32 flexcan_read(void __iomem *addr)
211{
212 return readl(addr);
213}
214
215static inline void flexcan_write(u32 val, void __iomem *addr)
216{
217 writel(val, addr);
218}
219#endif
220
e955cead
MKB		 221/*
222 * Swtich transceiver on or off
223 */
224static void flexcan_transceiver_switch(const struct flexcan_priv *priv, int on)
225{
226 if (priv->pdata && priv->pdata->transceiver_switch)
227 priv->pdata->transceiver_switch(on);
228}
229
230static inline int flexcan_has_and_handle_berr(const struct flexcan_priv *priv,
231 u32 reg_esr)
232{
233 return (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) &&
234 (reg_esr & FLEXCAN_ESR_ERR_BUS);
235}
236
237static inline void flexcan_chip_enable(struct flexcan_priv *priv)
238{
239 struct flexcan_regs __iomem *regs = priv->base;
240 u32 reg;
241
61e271ee 242 reg = flexcan_read(&regs->mcr);
e955cead 243 reg &= ~FLEXCAN_MCR_MDIS;
61e271ee 244 flexcan_write(reg, &regs->mcr);
e955cead
MKB		 245
246 udelay(10);
247}
248
249static inline void flexcan_chip_disable(struct flexcan_priv *priv)
250{
251 struct flexcan_regs __iomem *regs = priv->base;
252 u32 reg;
253
61e271ee 254 reg = flexcan_read(&regs->mcr);
e955cead 255 reg |= FLEXCAN_MCR_MDIS;
61e271ee 256 flexcan_write(reg, &regs->mcr);
e955cead
MKB		 257}
258
259static int flexcan_get_berr_counter(const struct net_device *dev,
260 struct can_berr_counter *bec)
261{
262 const struct flexcan_priv *priv = netdev_priv(dev);
263 struct flexcan_regs __iomem *regs = priv->base;
61e271ee 264 u32 reg = flexcan_read(&regs->ecr);
e955cead
MKB		 265
266 bec->txerr = (reg >> 0) & 0xff;
267 bec->rxerr = (reg >> 8) & 0xff;
268
269 return 0;
270}
271
272static int flexcan_start_xmit(struct sk_buff *skb, struct net_device *dev)
273{
274 const struct flexcan_priv *priv = netdev_priv(dev);
e955cead
MKB		 275 struct flexcan_regs __iomem *regs = priv->base;
276 struct can_frame *cf = (struct can_frame *)skb->data;
277 u32 can_id;
278 u32 ctrl = FLEXCAN_MB_CNT_CODE(0xc) | (cf->can_dlc << 16);
279
280 if (can_dropped_invalid_skb(dev, skb))
281 return NETDEV_TX_OK;
282
283 netif_stop_queue(dev);
284
285 if (cf->can_id & CAN_EFF_FLAG) {
286 can_id = cf->can_id & CAN_EFF_MASK;
287 ctrl |= FLEXCAN_MB_CNT_IDE | FLEXCAN_MB_CNT_SRR;
288 } else {
289 can_id = (cf->can_id & CAN_SFF_MASK) << 18;
290 }
291
292 if (cf->can_id & CAN_RTR_FLAG)
293 ctrl |= FLEXCAN_MB_CNT_RTR;
294
295 if (cf->can_dlc > 0) {
296 u32 data = be32_to_cpup((__be32 *)&cf->data[0]);
61e271ee 297 flexcan_write(data, &regs->cantxfg[FLEXCAN_TX_BUF_ID].data[0]);
e955cead
MKB		 298 }
299 if (cf->can_dlc > 3) {
300 u32 data = be32_to_cpup((__be32 *)&cf->data[4]);
61e271ee 301 flexcan_write(data, &regs->cantxfg[FLEXCAN_TX_BUF_ID].data[1]);
e955cead
MKB		 302 }
303
9a123496
RD		 304 can_put_echo_skb(skb, dev, 0);
305
61e271ee 306 flexcan_write(can_id, &regs->cantxfg[FLEXCAN_TX_BUF_ID].can_id);
307 flexcan_write(ctrl, &regs->cantxfg[FLEXCAN_TX_BUF_ID].can_ctrl);
e955cead 308
e955cead
MKB		 309 return NETDEV_TX_OK;
310}
311
312static void do_bus_err(struct net_device *dev,
313 struct can_frame *cf, u32 reg_esr)
314{
315 struct flexcan_priv *priv = netdev_priv(dev);
316 int rx_errors = 0, tx_errors = 0;
317
318 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
319
320 if (reg_esr & FLEXCAN_ESR_BIT1_ERR) {
aabdfd6a 321 netdev_dbg(dev, "BIT1_ERR irq\n");
e955cead
MKB		 322 cf->data[2] |= CAN_ERR_PROT_BIT1;
323 tx_errors = 1;
324 }
325 if (reg_esr & FLEXCAN_ESR_BIT0_ERR) {
aabdfd6a 326 netdev_dbg(dev, "BIT0_ERR irq\n");
e955cead
MKB		 327 cf->data[2] |= CAN_ERR_PROT_BIT0;
328 tx_errors = 1;
329 }
330 if (reg_esr & FLEXCAN_ESR_ACK_ERR) {
aabdfd6a 331 netdev_dbg(dev, "ACK_ERR irq\n");
e955cead
MKB		 332 cf->can_id |= CAN_ERR_ACK;
333 cf->data[3] |= CAN_ERR_PROT_LOC_ACK;
334 tx_errors = 1;
335 }
336 if (reg_esr & FLEXCAN_ESR_CRC_ERR) {
aabdfd6a 337 netdev_dbg(dev, "CRC_ERR irq\n");
e955cead
MKB		 338 cf->data[2] |= CAN_ERR_PROT_BIT;
339 cf->data[3] |= CAN_ERR_PROT_LOC_CRC_SEQ;
340 rx_errors = 1;
341 }
342 if (reg_esr & FLEXCAN_ESR_FRM_ERR) {
aabdfd6a 343 netdev_dbg(dev, "FRM_ERR irq\n");
e955cead
MKB		 344 cf->data[2] |= CAN_ERR_PROT_FORM;
345 rx_errors = 1;
346 }
347 if (reg_esr & FLEXCAN_ESR_STF_ERR) {
aabdfd6a 348 netdev_dbg(dev, "STF_ERR irq\n");
e955cead
MKB		 349 cf->data[2] |= CAN_ERR_PROT_STUFF;
350 rx_errors = 1;
351 }
352
353 priv->can.can_stats.bus_error++;
354 if (rx_errors)
355 dev->stats.rx_errors++;
356 if (tx_errors)
357 dev->stats.tx_errors++;
358}
359
360static int flexcan_poll_bus_err(struct net_device *dev, u32 reg_esr)
361{
362 struct sk_buff *skb;
363 struct can_frame *cf;
364
365 skb = alloc_can_err_skb(dev, &cf);
366 if (unlikely(!skb))
367 return 0;
368
369 do_bus_err(dev, cf, reg_esr);
370 netif_receive_skb(skb);
371
372 dev->stats.rx_packets++;
373 dev->stats.rx_bytes += cf->can_dlc;
374
375 return 1;
376}
377
378static void do_state(struct net_device *dev,
379 struct can_frame *cf, enum can_state new_state)
380{
381 struct flexcan_priv *priv = netdev_priv(dev);
382 struct can_berr_counter bec;
383
384 flexcan_get_berr_counter(dev, &bec);
385
386 switch (priv->can.state) {
387 case CAN_STATE_ERROR_ACTIVE:
388 /*
389 * from: ERROR_ACTIVE
390 * to : ERROR_WARNING, ERROR_PASSIVE, BUS_OFF
391 * => : there was a warning int
392 */
393 if (new_state >= CAN_STATE_ERROR_WARNING &&
394 new_state <= CAN_STATE_BUS_OFF) {
aabdfd6a 395 netdev_dbg(dev, "Error Warning IRQ\n");
e955cead
MKB		 396 priv->can.can_stats.error_warning++;
397
398 cf->can_id |= CAN_ERR_CRTL;
399 cf->data[1] = (bec.txerr > bec.rxerr) ?
400 CAN_ERR_CRTL_TX_WARNING :
401 CAN_ERR_CRTL_RX_WARNING;
402 }
403 case CAN_STATE_ERROR_WARNING: /* fallthrough */
404 /*
405 * from: ERROR_ACTIVE, ERROR_WARNING
406 * to : ERROR_PASSIVE, BUS_OFF
407 * => : error passive int
408 */
409 if (new_state >= CAN_STATE_ERROR_PASSIVE &&
410 new_state <= CAN_STATE_BUS_OFF) {
aabdfd6a 411 netdev_dbg(dev, "Error Passive IRQ\n");
e955cead
MKB		 412 priv->can.can_stats.error_passive++;
413
414 cf->can_id |= CAN_ERR_CRTL;
415 cf->data[1] = (bec.txerr > bec.rxerr) ?
416 CAN_ERR_CRTL_TX_PASSIVE :
417 CAN_ERR_CRTL_RX_PASSIVE;
418 }
419 break;
420 case CAN_STATE_BUS_OFF:
aabdfd6a
WG		 421 netdev_err(dev, "BUG! "
422 "hardware recovered automatically from BUS_OFF\n");
e955cead
MKB		 423 break;
424 default:
425 break;
426 }
427
428 /* process state changes depending on the new state */
429 switch (new_state) {
430 case CAN_STATE_ERROR_ACTIVE:
aabdfd6a 431 netdev_dbg(dev, "Error Active\n");
e955cead
MKB		 432 cf->can_id |= CAN_ERR_PROT;
433 cf->data[2] = CAN_ERR_PROT_ACTIVE;
434 break;
435 case CAN_STATE_BUS_OFF:
436 cf->can_id |= CAN_ERR_BUSOFF;
437 can_bus_off(dev);
438 break;
439 default:
440 break;
441 }
442}
443
444static int flexcan_poll_state(struct net_device *dev, u32 reg_esr)
445{
446 struct flexcan_priv *priv = netdev_priv(dev);
447 struct sk_buff *skb;
448 struct can_frame *cf;
449 enum can_state new_state;
450 int flt;
451
452 flt = reg_esr & FLEXCAN_ESR_FLT_CONF_MASK;
453 if (likely(flt == FLEXCAN_ESR_FLT_CONF_ACTIVE)) {
454 if (likely(!(reg_esr & (FLEXCAN_ESR_TX_WRN |
455 FLEXCAN_ESR_RX_WRN))))
456 new_state = CAN_STATE_ERROR_ACTIVE;
457 else
458 new_state = CAN_STATE_ERROR_WARNING;
459 } else if (unlikely(flt == FLEXCAN_ESR_FLT_CONF_PASSIVE))
460 new_state = CAN_STATE_ERROR_PASSIVE;
461 else
462 new_state = CAN_STATE_BUS_OFF;
463
464 /* state hasn't changed */
465 if (likely(new_state == priv->can.state))
466 return 0;
467
468 skb = alloc_can_err_skb(dev, &cf);
469 if (unlikely(!skb))
470 return 0;
471
472 do_state(dev, cf, new_state);
473 priv->can.state = new_state;
474 netif_receive_skb(skb);
475
476 dev->stats.rx_packets++;
477 dev->stats.rx_bytes += cf->can_dlc;
478
479 return 1;
480}
481
482static void flexcan_read_fifo(const struct net_device *dev,
483 struct can_frame *cf)
484{
485 const struct flexcan_priv *priv = netdev_priv(dev);
486 struct flexcan_regs __iomem *regs = priv->base;
487 struct flexcan_mb __iomem *mb = &regs->cantxfg[0];
488 u32 reg_ctrl, reg_id;
489
61e271ee 490 reg_ctrl = flexcan_read(&mb->can_ctrl);
491 reg_id = flexcan_read(&mb->can_id);
e955cead
MKB		 492 if (reg_ctrl & FLEXCAN_MB_CNT_IDE)
493 cf->can_id = ((reg_id >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG;
494 else
495 cf->can_id = (reg_id >> 18) & CAN_SFF_MASK;
496
497 if (reg_ctrl & FLEXCAN_MB_CNT_RTR)
498 cf->can_id |= CAN_RTR_FLAG;
499 cf->can_dlc = get_can_dlc((reg_ctrl >> 16) & 0xf);
500
61e271ee 501 *(__be32 *)(cf->data + 0) = cpu_to_be32(flexcan_read(&mb->data[0]));
502 *(__be32 *)(cf->data + 4) = cpu_to_be32(flexcan_read(&mb->data[1]));
e955cead
MKB		 503
504 /* mark as read */
61e271ee 505 flexcan_write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, &regs->iflag1);
506 flexcan_read(&regs->timer);
e955cead
MKB		 507}
508
509static int flexcan_read_frame(struct net_device *dev)
510{
511 struct net_device_stats *stats = &dev->stats;
512 struct can_frame *cf;
513 struct sk_buff *skb;
514
515 skb = alloc_can_skb(dev, &cf);
516 if (unlikely(!skb)) {
517 stats->rx_dropped++;
518 return 0;
519 }
520
521 flexcan_read_fifo(dev, cf);
522 netif_receive_skb(skb);
523
524 stats->rx_packets++;
525 stats->rx_bytes += cf->can_dlc;
526
527 return 1;
528}
529
530static int flexcan_poll(struct napi_struct *napi, int quota)
531{
532 struct net_device *dev = napi->dev;
533 const struct flexcan_priv *priv = netdev_priv(dev);
534 struct flexcan_regs __iomem *regs = priv->base;
535 u32 reg_iflag1, reg_esr;
536 int work_done = 0;
537
538 /*
539 * The error bits are cleared on read,
540 * use saved value from irq handler.
541 */
61e271ee 542 reg_esr = flexcan_read(&regs->esr) | priv->reg_esr;
e955cead
MKB		 543
544 /* handle state changes */
545 work_done += flexcan_poll_state(dev, reg_esr);
546
547 /* handle RX-FIFO */
61e271ee 548 reg_iflag1 = flexcan_read(&regs->iflag1);
e955cead
MKB		 549 while (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE &&
550 work_done < quota) {
551 work_done += flexcan_read_frame(dev);
61e271ee 552 reg_iflag1 = flexcan_read(&regs->iflag1);
e955cead
MKB		 553 }
554
555 /* report bus errors */
556 if (flexcan_has_and_handle_berr(priv, reg_esr) && work_done < quota)
557 work_done += flexcan_poll_bus_err(dev, reg_esr);
558
559 if (work_done < quota) {
560 napi_complete(napi);
561 /* enable IRQs */
61e271ee 562 flexcan_write(FLEXCAN_IFLAG_DEFAULT, &regs->imask1);
563 flexcan_write(priv->reg_ctrl_default, &regs->ctrl);
e955cead
MKB		 564 }
565
566 return work_done;
567}
568
569static irqreturn_t flexcan_irq(int irq, void *dev_id)
570{
571 struct net_device *dev = dev_id;
572 struct net_device_stats *stats = &dev->stats;
573 struct flexcan_priv *priv = netdev_priv(dev);
574 struct flexcan_regs __iomem *regs = priv->base;
575 u32 reg_iflag1, reg_esr;
576
61e271ee 577 reg_iflag1 = flexcan_read(&regs->iflag1);
578 reg_esr = flexcan_read(&regs->esr);
6e9d554f
WG		 579 /* ACK all bus error and state change IRQ sources */
580 if (reg_esr & FLEXCAN_ESR_ALL_INT)
581 flexcan_write(reg_esr & FLEXCAN_ESR_ALL_INT, &regs->esr);
e955cead
MKB		 582
583 /*
584 * schedule NAPI in case of:
585 * - rx IRQ
586 * - state change IRQ
587 * - bus error IRQ and bus error reporting is activated
588 */
589 if ((reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE) ||
590 (reg_esr & FLEXCAN_ESR_ERR_STATE) ||
591 flexcan_has_and_handle_berr(priv, reg_esr)) {
592 /*
593 * The error bits are cleared on read,
594 * save them for later use.
595 */
596 priv->reg_esr = reg_esr & FLEXCAN_ESR_ERR_BUS;
61e271ee 597 flexcan_write(FLEXCAN_IFLAG_DEFAULT &
598 ~FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, &regs->imask1);
599 flexcan_write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
e955cead
MKB		 600 &regs->ctrl);
601 napi_schedule(&priv->napi);
602 }
603
604 /* FIFO overflow */
605 if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_OVERFLOW) {
61e271ee 606 flexcan_write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW, &regs->iflag1);
e955cead
MKB		 607 dev->stats.rx_over_errors++;
608 dev->stats.rx_errors++;
609 }
610
611 /* transmission complete interrupt */
612 if (reg_iflag1 & (1 << FLEXCAN_TX_BUF_ID)) {
9a123496 613 stats->tx_bytes += can_get_echo_skb(dev, 0);
e955cead 614 stats->tx_packets++;
61e271ee 615 flexcan_write((1 << FLEXCAN_TX_BUF_ID), &regs->iflag1);
e955cead
MKB		 616 netif_wake_queue(dev);
617 }
618
619 return IRQ_HANDLED;
620}
621
622static void flexcan_set_bittiming(struct net_device *dev)
623{
624 const struct flexcan_priv *priv = netdev_priv(dev);
625 const struct can_bittiming *bt = &priv->can.bittiming;
626 struct flexcan_regs __iomem *regs = priv->base;
627 u32 reg;
628
61e271ee 629 reg = flexcan_read(&regs->ctrl);
e955cead
MKB		 630 reg &= ~(FLEXCAN_CTRL_PRESDIV(0xff) |
631 FLEXCAN_CTRL_RJW(0x3) |
632 FLEXCAN_CTRL_PSEG1(0x7) |
633 FLEXCAN_CTRL_PSEG2(0x7) |
634 FLEXCAN_CTRL_PROPSEG(0x7) |
635 FLEXCAN_CTRL_LPB |
636 FLEXCAN_CTRL_SMP |
637 FLEXCAN_CTRL_LOM);
638
639 reg |= FLEXCAN_CTRL_PRESDIV(bt->brp - 1) |
640 FLEXCAN_CTRL_PSEG1(bt->phase_seg1 - 1) |
641 FLEXCAN_CTRL_PSEG2(bt->phase_seg2 - 1) |
642 FLEXCAN_CTRL_RJW(bt->sjw - 1) |
643 FLEXCAN_CTRL_PROPSEG(bt->prop_seg - 1);
644
645 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
646 reg |= FLEXCAN_CTRL_LPB;
647 if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
648 reg |= FLEXCAN_CTRL_LOM;
649 if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES)
650 reg |= FLEXCAN_CTRL_SMP;
651
aabdfd6a 652 netdev_info(dev, "writing ctrl=0x%08x\n", reg);
61e271ee 653 flexcan_write(reg, &regs->ctrl);
e955cead
MKB		 654
655 /* print chip status */
aabdfd6a
WG		 656 netdev_dbg(dev, "%s: mcr=0x%08x ctrl=0x%08x\n", __func__,
657 flexcan_read(&regs->mcr), flexcan_read(&regs->ctrl));
e955cead
MKB		 658}
659
660/*
661 * flexcan_chip_start
662 *
663 * this functions is entered with clocks enabled
664 *
665 */
666static int flexcan_chip_start(struct net_device *dev)
667{
668 struct flexcan_priv *priv = netdev_priv(dev);
669 struct flexcan_regs __iomem *regs = priv->base;
670 unsigned int i;
671 int err;
672 u32 reg_mcr, reg_ctrl;
673
674 /* enable module */
675 flexcan_chip_enable(priv);
676
677 /* soft reset */
61e271ee 678 flexcan_write(FLEXCAN_MCR_SOFTRST, &regs->mcr);
e955cead
MKB		 679 udelay(10);
680
61e271ee 681 reg_mcr = flexcan_read(&regs->mcr);
e955cead 682 if (reg_mcr & FLEXCAN_MCR_SOFTRST) {
aabdfd6a
WG		 683 netdev_err(dev, "Failed to softreset can module (mcr=0x%08x)\n",
684 reg_mcr);
e955cead
MKB		 685 err = -ENODEV;
686 goto out;
687 }
688
689 flexcan_set_bittiming(dev);
690
691 /*
692 * MCR
693 *
694 * enable freeze
695 * enable fifo
696 * halt now
697 * only supervisor access
698 * enable warning int
699 * choose format C
9a123496 700 * disable local echo
e955cead
MKB		 701 *
702 */
61e271ee 703 reg_mcr = flexcan_read(&regs->mcr);
e955cead
MKB		 704 reg_mcr |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_FEN | FLEXCAN_MCR_HALT |
705 FLEXCAN_MCR_SUPV | FLEXCAN_MCR_WRN_EN |
9a123496 706 FLEXCAN_MCR_IDAM_C | FLEXCAN_MCR_SRX_DIS;
aabdfd6a 707 netdev_dbg(dev, "%s: writing mcr=0x%08x", __func__, reg_mcr);
61e271ee 708 flexcan_write(reg_mcr, &regs->mcr);
e955cead
MKB		 709
710 /*
711 * CTRL
712 *
713 * disable timer sync feature
714 *
715 * disable auto busoff recovery
716 * transmit lowest buffer first
717 *
718 * enable tx and rx warning interrupt
719 * enable bus off interrupt
720 * (== FLEXCAN_CTRL_ERR_STATE)
721 *
722 * _note_: we enable the "error interrupt"
723 * (FLEXCAN_CTRL_ERR_MSK), too. Otherwise we don't get any
724 * warning or bus passive interrupts.
725 */
61e271ee 726 reg_ctrl = flexcan_read(&regs->ctrl);
e955cead
MKB		 727 reg_ctrl &= ~FLEXCAN_CTRL_TSYN;
728 reg_ctrl |= FLEXCAN_CTRL_BOFF_REC | FLEXCAN_CTRL_LBUF |
729 FLEXCAN_CTRL_ERR_STATE | FLEXCAN_CTRL_ERR_MSK;
730
731 /* save for later use */
732 priv->reg_ctrl_default = reg_ctrl;
aabdfd6a 733 netdev_dbg(dev, "%s: writing ctrl=0x%08x", __func__, reg_ctrl);
61e271ee 734 flexcan_write(reg_ctrl, &regs->ctrl);
e955cead
MKB		 735
736 for (i = 0; i < ARRAY_SIZE(regs->cantxfg); i++) {
61e271ee 737 flexcan_write(0, &regs->cantxfg[i].can_ctrl);
738 flexcan_write(0, &regs->cantxfg[i].can_id);
739 flexcan_write(0, &regs->cantxfg[i].data[0]);
740 flexcan_write(0, &regs->cantxfg[i].data[1]);
e955cead
MKB		 741
742 /* put MB into rx queue */
61e271ee 743 flexcan_write(FLEXCAN_MB_CNT_CODE(0x4),
744 &regs->cantxfg[i].can_ctrl);
e955cead
MKB		 745 }
746
747 /* acceptance mask/acceptance code (accept everything) */
61e271ee 748 flexcan_write(0x0, &regs->rxgmask);
749 flexcan_write(0x0, &regs->rx14mask);
750 flexcan_write(0x0, &regs->rx15mask);
e955cead
MKB		 751
752 flexcan_transceiver_switch(priv, 1);
753
754 /* synchronize with the can bus */
61e271ee 755 reg_mcr = flexcan_read(&regs->mcr);
e955cead 756 reg_mcr &= ~FLEXCAN_MCR_HALT;
61e271ee 757 flexcan_write(reg_mcr, &regs->mcr);
e955cead
MKB		 758
759 priv->can.state = CAN_STATE_ERROR_ACTIVE;
760
761 /* enable FIFO interrupts */
61e271ee 762 flexcan_write(FLEXCAN_IFLAG_DEFAULT, &regs->imask1);
e955cead
MKB		 763
764 /* print chip status */
aabdfd6a
WG		 765 netdev_dbg(dev, "%s: reading mcr=0x%08x ctrl=0x%08x\n", __func__,
766 flexcan_read(&regs->mcr), flexcan_read(&regs->ctrl));
e955cead
MKB		 767
768 return 0;
769
770 out:
771 flexcan_chip_disable(priv);
772 return err;
773}
774
775/*
776 * flexcan_chip_stop
777 *
778 * this functions is entered with clocks enabled
779 *
780 */
781static void flexcan_chip_stop(struct net_device *dev)
782{
783 struct flexcan_priv *priv = netdev_priv(dev);
784 struct flexcan_regs __iomem *regs = priv->base;
785 u32 reg;
786
787 /* Disable all interrupts */
61e271ee 788 flexcan_write(0, &regs->imask1);
e955cead
MKB		 789
790 /* Disable + halt module */
61e271ee 791 reg = flexcan_read(&regs->mcr);
e955cead 792 reg |= FLEXCAN_MCR_MDIS | FLEXCAN_MCR_HALT;
61e271ee 793 flexcan_write(reg, &regs->mcr);
e955cead
MKB		 794
795 flexcan_transceiver_switch(priv, 0);
796 priv->can.state = CAN_STATE_STOPPED;
797
798 return;
799}
800
801static int flexcan_open(struct net_device *dev)
802{
803 struct flexcan_priv *priv = netdev_priv(dev);
804 int err;
805
e7354899 806 clk_prepare_enable(priv->clk);
e955cead
MKB		 807
808 err = open_candev(dev);
809 if (err)
810 goto out;
811
812 err = request_irq(dev->irq, flexcan_irq, IRQF_SHARED, dev->name, dev);
813 if (err)
814 goto out_close;
815
816 /* start chip and queuing */
817 err = flexcan_chip_start(dev);
818 if (err)
819 goto out_close;
820 napi_enable(&priv->napi);
821 netif_start_queue(dev);
822
823 return 0;
824
825 out_close:
826 close_candev(dev);
827 out:
e7354899 828 clk_disable_unprepare(priv->clk);
e955cead
MKB		 829
830 return err;
831}
832
833static int flexcan_close(struct net_device *dev)
834{
835 struct flexcan_priv *priv = netdev_priv(dev);
836
837 netif_stop_queue(dev);
838 napi_disable(&priv->napi);
839 flexcan_chip_stop(dev);
840
841 free_irq(dev->irq, dev);
e7354899 842 clk_disable_unprepare(priv->clk);
e955cead
MKB		 843
844 close_candev(dev);
845
846 return 0;
847}
848
849static int flexcan_set_mode(struct net_device *dev, enum can_mode mode)
850{
851 int err;
852
853 switch (mode) {
854 case CAN_MODE_START:
855 err = flexcan_chip_start(dev);
856 if (err)
857 return err;
858
859 netif_wake_queue(dev);
860 break;
861
862 default:
863 return -EOPNOTSUPP;
864 }
865
866 return 0;
867}
868
869static const struct net_device_ops flexcan_netdev_ops = {
870 .ndo_open = flexcan_open,
871 .ndo_stop = flexcan_close,
872 .ndo_start_xmit = flexcan_start_xmit,
873};
874
875static int __devinit register_flexcandev(struct net_device *dev)
876{
877 struct flexcan_priv *priv = netdev_priv(dev);
878 struct flexcan_regs __iomem *regs = priv->base;
879 u32 reg, err;
880
e7354899 881 clk_prepare_enable(priv->clk);
e955cead
MKB		 882
883 /* select "bus clock", chip must be disabled */
884 flexcan_chip_disable(priv);
61e271ee 885 reg = flexcan_read(&regs->ctrl);
e955cead 886 reg |= FLEXCAN_CTRL_CLK_SRC;
61e271ee 887 flexcan_write(reg, &regs->ctrl);
e955cead
MKB		 888
889 flexcan_chip_enable(priv);
890
891 /* set freeze, halt and activate FIFO, restrict register access */
61e271ee 892 reg = flexcan_read(&regs->mcr);
e955cead
MKB		 893 reg |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT |
894 FLEXCAN_MCR_FEN | FLEXCAN_MCR_SUPV;
61e271ee 895 flexcan_write(reg, &regs->mcr);
e955cead
MKB		 896
897 /*
898 * Currently we only support newer versions of this core
899 * featuring a RX FIFO. Older cores found on some Coldfire
900 * derivates are not yet supported.
901 */
61e271ee 902 reg = flexcan_read(&regs->mcr);
e955cead 903 if (!(reg & FLEXCAN_MCR_FEN)) {
aabdfd6a 904 netdev_err(dev, "Could not enable RX FIFO, unsupported core\n");
e955cead
MKB		 905 err = -ENODEV;
906 goto out;
907 }
908
909 err = register_candev(dev);
910
911 out:
912 /* disable core and turn off clocks */
913 flexcan_chip_disable(priv);
e7354899 914 clk_disable_unprepare(priv->clk);
e955cead
MKB		 915
916 return err;
917}
918
919static void __devexit unregister_flexcandev(struct net_device *dev)
920{
921 unregister_candev(dev);
922}
923
924static int __devinit flexcan_probe(struct platform_device *pdev)
925{
926 struct net_device *dev;
927 struct flexcan_priv *priv;
928 struct resource *mem;
97efe9ae 929 struct clk *clk = NULL;
e955cead
MKB		 930 void __iomem *base;
931 resource_size_t mem_size;
932 int err, irq;
97efe9ae 933 u32 clock_freq = 0;
934
935 if (pdev->dev.of_node) {
936 const u32 *clock_freq_p;
e955cead 937
97efe9ae 938 clock_freq_p = of_get_property(pdev->dev.of_node,
939 "clock-frequency", NULL);
940 if (clock_freq_p)
941 clock_freq = *clock_freq_p;
942 }
943
944 if (!clock_freq) {
945 clk = clk_get(&pdev->dev, NULL);
946 if (IS_ERR(clk)) {
947 dev_err(&pdev->dev, "no clock defined\n");
948 err = PTR_ERR(clk);
949 goto failed_clock;
950 }
951 clock_freq = clk_get_rate(clk);
e955cead
MKB		 952 }
953
954 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
955 irq = platform_get_irq(pdev, 0);
956 if (!mem || irq <= 0) {
957 err = -ENODEV;
958 goto failed_get;
959 }
960
961 mem_size = resource_size(mem);
962 if (!request_mem_region(mem->start, mem_size, pdev->name)) {
963 err = -EBUSY;
2e4ceec4 964 goto failed_get;
e955cead
MKB		 965 }
966
967 base = ioremap(mem->start, mem_size);
968 if (!base) {
969 err = -ENOMEM;
970 goto failed_map;
971 }
972
9a123496 973 dev = alloc_candev(sizeof(struct flexcan_priv), 1);
e955cead
MKB		 974 if (!dev) {
975 err = -ENOMEM;
976 goto failed_alloc;
977 }
978
979 dev->netdev_ops = &flexcan_netdev_ops;
980 dev->irq = irq;
9a123496 981 dev->flags |= IFF_ECHO;
e955cead
MKB		 982
983 priv = netdev_priv(dev);
97efe9ae 984 priv->can.clock.freq = clock_freq;
e955cead
MKB		 985 priv->can.bittiming_const = &flexcan_bittiming_const;
986 priv->can.do_set_mode = flexcan_set_mode;
987 priv->can.do_get_berr_counter = flexcan_get_berr_counter;
988 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
989 CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_3_SAMPLES |
990 CAN_CTRLMODE_BERR_REPORTING;
991 priv->base = base;
992 priv->dev = dev;
993 priv->clk = clk;
994 priv->pdata = pdev->dev.platform_data;
995
996 netif_napi_add(dev, &priv->napi, flexcan_poll, FLEXCAN_NAPI_WEIGHT);
997
998 dev_set_drvdata(&pdev->dev, dev);
999 SET_NETDEV_DEV(dev, &pdev->dev);
1000
1001 err = register_flexcandev(dev);
1002 if (err) {
1003 dev_err(&pdev->dev, "registering netdev failed\n");
1004 goto failed_register;
1005 }
1006
1007 dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%d)\n",
1008 priv->base, dev->irq);
1009
1010 return 0;
1011
1012 failed_register:
1013 free_candev(dev);
1014 failed_alloc:
1015 iounmap(base);
1016 failed_map:
1017 release_mem_region(mem->start, mem_size);
e955cead 1018 failed_get:
97efe9ae 1019 if (clk)
1020 clk_put(clk);
e955cead
MKB		 1021 failed_clock:
1022 return err;
1023}
1024
1025static int __devexit flexcan_remove(struct platform_device *pdev)
1026{
1027 struct net_device *dev = platform_get_drvdata(pdev);
1028 struct flexcan_priv *priv = netdev_priv(dev);
1029 struct resource *mem;
1030
1031 unregister_flexcandev(dev);
1032 platform_set_drvdata(pdev, NULL);
e955cead
MKB		 1033 iounmap(priv->base);
1034
1035 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1036 release_mem_region(mem->start, resource_size(mem));
1037
97efe9ae 1038 if (priv->clk)
1039 clk_put(priv->clk);
e955cead 1040
9a27586d
MKB		 1041 free_candev(dev);
1042
e955cead
MKB		 1043 return 0;
1044}
1045
c8aef4cb 1046static struct of_device_id flexcan_of_match[] = {
1047 {
1048 .compatible = "fsl,p1010-flexcan",
1049 },
1050 {},
1051};
1052
e955cead 1053static struct platform_driver flexcan_driver = {
c8aef4cb 1054 .driver = {
1055 .name = DRV_NAME,
1056 .owner = THIS_MODULE,
1057 .of_match_table = flexcan_of_match,
1058 },
e955cead
MKB		 1059 .probe = flexcan_probe,
1060 .remove = __devexit_p(flexcan_remove),
1061};
1062
871d3372 1063module_platform_driver(flexcan_driver);
e955cead
MKB		 1064
1065MODULE_AUTHOR("Sascha Hauer <kernel@pengutronix.de>, "
1066 "Marc Kleine-Budde <kernel@pengutronix.de>");
1067MODULE_LICENSE("GPL v2");
1068MODULE_DESCRIPTION("CAN port driver for flexcan based chip");
Linux kernel - Deliverables
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