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can: flexcan: mark TX mailbox as TX_INACTIVE
[deliverable/linux.git] / drivers / net / can / flexcan.c
CommitLineData
e955cead
MKB		 1/*
2 * flexcan.c - FLEXCAN CAN controller driver
3 *
4 * Copyright (c) 2005-2006 Varma Electronics Oy
5 * Copyright (c) 2009 Sascha Hauer, Pengutronix
6 * Copyright (c) 2010 Marc Kleine-Budde, Pengutronix
7 *
8 * Based on code originally by Andrey Volkov <avolkov@varma-el.com>
9 *
10 * LICENCE:
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation version 2.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 */
21
22#include <linux/netdevice.h>
23#include <linux/can.h>
24#include <linux/can/dev.h>
25#include <linux/can/error.h>
adccadb9 26#include <linux/can/led.h>
e955cead
MKB		 27#include <linux/clk.h>
28#include <linux/delay.h>
29#include <linux/if_arp.h>
30#include <linux/if_ether.h>
31#include <linux/interrupt.h>
32#include <linux/io.h>
33#include <linux/kernel.h>
34#include <linux/list.h>
35#include <linux/module.h>
97efe9ae 36#include <linux/of.h>
30c1e672 37#include <linux/of_device.h>
e955cead 38#include <linux/platform_device.h>
b7c4114b 39#include <linux/regulator/consumer.h>
e955cead 40
e955cead
MKB		 41#define DRV_NAME "flexcan"
42
43/* 8 for RX fifo and 2 error handling */
44#define FLEXCAN_NAPI_WEIGHT (8 + 2)
45
46/* FLEXCAN module configuration register (CANMCR) bits */
47#define FLEXCAN_MCR_MDIS BIT(31)
48#define FLEXCAN_MCR_FRZ BIT(30)
49#define FLEXCAN_MCR_FEN BIT(29)
50#define FLEXCAN_MCR_HALT BIT(28)
51#define FLEXCAN_MCR_NOT_RDY BIT(27)
52#define FLEXCAN_MCR_WAK_MSK BIT(26)
53#define FLEXCAN_MCR_SOFTRST BIT(25)
54#define FLEXCAN_MCR_FRZ_ACK BIT(24)
55#define FLEXCAN_MCR_SUPV BIT(23)
56#define FLEXCAN_MCR_SLF_WAK BIT(22)
57#define FLEXCAN_MCR_WRN_EN BIT(21)
58#define FLEXCAN_MCR_LPM_ACK BIT(20)
59#define FLEXCAN_MCR_WAK_SRC BIT(19)
60#define FLEXCAN_MCR_DOZE BIT(18)
61#define FLEXCAN_MCR_SRX_DIS BIT(17)
62#define FLEXCAN_MCR_BCC BIT(16)
63#define FLEXCAN_MCR_LPRIO_EN BIT(13)
64#define FLEXCAN_MCR_AEN BIT(12)
d5a7b406 65#define FLEXCAN_MCR_MAXMB(x) ((x) & 0x1f)
e955cead
MKB		 66#define FLEXCAN_MCR_IDAM_A (0 << 8)
67#define FLEXCAN_MCR_IDAM_B (1 << 8)
68#define FLEXCAN_MCR_IDAM_C (2 << 8)
69#define FLEXCAN_MCR_IDAM_D (3 << 8)
70
71/* FLEXCAN control register (CANCTRL) bits */
72#define FLEXCAN_CTRL_PRESDIV(x) (((x) & 0xff) << 24)
73#define FLEXCAN_CTRL_RJW(x) (((x) & 0x03) << 22)
74#define FLEXCAN_CTRL_PSEG1(x) (((x) & 0x07) << 19)
75#define FLEXCAN_CTRL_PSEG2(x) (((x) & 0x07) << 16)
76#define FLEXCAN_CTRL_BOFF_MSK BIT(15)
77#define FLEXCAN_CTRL_ERR_MSK BIT(14)
78#define FLEXCAN_CTRL_CLK_SRC BIT(13)
79#define FLEXCAN_CTRL_LPB BIT(12)
80#define FLEXCAN_CTRL_TWRN_MSK BIT(11)
81#define FLEXCAN_CTRL_RWRN_MSK BIT(10)
82#define FLEXCAN_CTRL_SMP BIT(7)
83#define FLEXCAN_CTRL_BOFF_REC BIT(6)
84#define FLEXCAN_CTRL_TSYN BIT(5)
85#define FLEXCAN_CTRL_LBUF BIT(4)
86#define FLEXCAN_CTRL_LOM BIT(3)
87#define FLEXCAN_CTRL_PROPSEG(x) ((x) & 0x07)
88#define FLEXCAN_CTRL_ERR_BUS (FLEXCAN_CTRL_ERR_MSK)
89#define FLEXCAN_CTRL_ERR_STATE \
90 (FLEXCAN_CTRL_TWRN_MSK | FLEXCAN_CTRL_RWRN_MSK | \
91 FLEXCAN_CTRL_BOFF_MSK)
92#define FLEXCAN_CTRL_ERR_ALL \
93 (FLEXCAN_CTRL_ERR_BUS | FLEXCAN_CTRL_ERR_STATE)
94
95/* FLEXCAN error and status register (ESR) bits */
96#define FLEXCAN_ESR_TWRN_INT BIT(17)
97#define FLEXCAN_ESR_RWRN_INT BIT(16)
98#define FLEXCAN_ESR_BIT1_ERR BIT(15)
99#define FLEXCAN_ESR_BIT0_ERR BIT(14)
100#define FLEXCAN_ESR_ACK_ERR BIT(13)
101#define FLEXCAN_ESR_CRC_ERR BIT(12)
102#define FLEXCAN_ESR_FRM_ERR BIT(11)
103#define FLEXCAN_ESR_STF_ERR BIT(10)
104#define FLEXCAN_ESR_TX_WRN BIT(9)
105#define FLEXCAN_ESR_RX_WRN BIT(8)
106#define FLEXCAN_ESR_IDLE BIT(7)
107#define FLEXCAN_ESR_TXRX BIT(6)
108#define FLEXCAN_EST_FLT_CONF_SHIFT (4)
109#define FLEXCAN_ESR_FLT_CONF_MASK (0x3 << FLEXCAN_EST_FLT_CONF_SHIFT)
110#define FLEXCAN_ESR_FLT_CONF_ACTIVE (0x0 << FLEXCAN_EST_FLT_CONF_SHIFT)
111#define FLEXCAN_ESR_FLT_CONF_PASSIVE (0x1 << FLEXCAN_EST_FLT_CONF_SHIFT)
112#define FLEXCAN_ESR_BOFF_INT BIT(2)
113#define FLEXCAN_ESR_ERR_INT BIT(1)
114#define FLEXCAN_ESR_WAK_INT BIT(0)
115#define FLEXCAN_ESR_ERR_BUS \
116 (FLEXCAN_ESR_BIT1_ERR | FLEXCAN_ESR_BIT0_ERR | \
117 FLEXCAN_ESR_ACK_ERR | FLEXCAN_ESR_CRC_ERR | \
118 FLEXCAN_ESR_FRM_ERR | FLEXCAN_ESR_STF_ERR)
119#define FLEXCAN_ESR_ERR_STATE \
120 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | FLEXCAN_ESR_BOFF_INT)
121#define FLEXCAN_ESR_ERR_ALL \
122 (FLEXCAN_ESR_ERR_BUS | FLEXCAN_ESR_ERR_STATE)
6e9d554f
WG		 123#define FLEXCAN_ESR_ALL_INT \
124 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | \
125 FLEXCAN_ESR_BOFF_INT | FLEXCAN_ESR_ERR_INT)
e955cead
MKB		 126
127/* FLEXCAN interrupt flag register (IFLAG) bits */
128#define FLEXCAN_TX_BUF_ID 8
129#define FLEXCAN_IFLAG_BUF(x) BIT(x)
130#define FLEXCAN_IFLAG_RX_FIFO_OVERFLOW BIT(7)
131#define FLEXCAN_IFLAG_RX_FIFO_WARN BIT(6)
132#define FLEXCAN_IFLAG_RX_FIFO_AVAILABLE BIT(5)
133#define FLEXCAN_IFLAG_DEFAULT \
134 (FLEXCAN_IFLAG_RX_FIFO_OVERFLOW | FLEXCAN_IFLAG_RX_FIFO_AVAILABLE | \
135 FLEXCAN_IFLAG_BUF(FLEXCAN_TX_BUF_ID))
136
137/* FLEXCAN message buffers */
138#define FLEXCAN_MB_CNT_CODE(x) (((x) & 0xf) << 24)
c32fe4ad
MKB		 139#define FLEXCAN_MB_CODE_RX_INACTIVE (0x0 << 24)
140#define FLEXCAN_MB_CODE_RX_EMPTY (0x4 << 24)
141#define FLEXCAN_MB_CODE_RX_FULL (0x2 << 24)
142#define FLEXCAN_MB_CODE_RX_OVERRRUN (0x6 << 24)
143#define FLEXCAN_MB_CODE_RX_RANSWER (0xa << 24)
144
145#define FLEXCAN_MB_CODE_TX_INACTIVE (0x8 << 24)
146#define FLEXCAN_MB_CODE_TX_ABORT (0x9 << 24)
147#define FLEXCAN_MB_CODE_TX_DATA (0xc << 24)
148#define FLEXCAN_MB_CODE_TX_TANSWER (0xe << 24)
149
e955cead
MKB		 150#define FLEXCAN_MB_CNT_SRR BIT(22)
151#define FLEXCAN_MB_CNT_IDE BIT(21)
152#define FLEXCAN_MB_CNT_RTR BIT(20)
153#define FLEXCAN_MB_CNT_LENGTH(x) (((x) & 0xf) << 16)
154#define FLEXCAN_MB_CNT_TIMESTAMP(x) ((x) & 0xffff)
155
156#define FLEXCAN_MB_CODE_MASK (0xf0ffffff)
157
9b00b300
MKB		 158#define FLEXCAN_TIMEOUT_US (50)
159
bb698ca4
WG		 160/*
161 * FLEXCAN hardware feature flags
162 *
163 * Below is some version info we got:
164 * SOC Version IP-Version Glitch- [TR]WRN_INT
165 * Filter? connected?
166 * MX25 FlexCAN2 03.00.00.00 no no
167 * MX28 FlexCAN2 03.00.04.00 yes yes
168 * MX35 FlexCAN2 03.00.00.00 no no
169 * MX53 FlexCAN2 03.00.00.00 yes no
170 * MX6s FlexCAN3 10.00.12.00 yes yes
171 *
172 * Some SOCs do not have the RX_WARN & TX_WARN interrupt line connected.
173 */
4f72e5f0 174#define FLEXCAN_HAS_V10_FEATURES BIT(1) /* For core version >= 10 */
bb698ca4 175#define FLEXCAN_HAS_BROKEN_ERR_STATE BIT(2) /* [TR]WRN_INT not connected */
4f72e5f0 176
e955cead
MKB		 177/* Structure of the message buffer */
178struct flexcan_mb {
179 u32 can_ctrl;
180 u32 can_id;
181 u32 data[2];
182};
183
184/* Structure of the hardware registers */
185struct flexcan_regs {
186 u32 mcr; /* 0x00 */
187 u32 ctrl; /* 0x04 */
188 u32 timer; /* 0x08 */
189 u32 _reserved1; /* 0x0c */
190 u32 rxgmask; /* 0x10 */
191 u32 rx14mask; /* 0x14 */
192 u32 rx15mask; /* 0x18 */
193 u32 ecr; /* 0x1c */
194 u32 esr; /* 0x20 */
195 u32 imask2; /* 0x24 */
196 u32 imask1; /* 0x28 */
197 u32 iflag2; /* 0x2c */
198 u32 iflag1; /* 0x30 */
30c1e672
HW		 199 u32 crl2; /* 0x34 */
200 u32 esr2; /* 0x38 */
201 u32 imeur; /* 0x3c */
202 u32 lrfr; /* 0x40 */
203 u32 crcr; /* 0x44 */
204 u32 rxfgmask; /* 0x48 */
205 u32 rxfir; /* 0x4c */
206 u32 _reserved3[12];
e955cead
MKB		 207 struct flexcan_mb cantxfg[64];
208};
209
30c1e672 210struct flexcan_devtype_data {
4f72e5f0 211 u32 features; /* hardware controller features */
30c1e672
HW		 212};
213
e955cead
MKB		 214struct flexcan_priv {
215 struct can_priv can;
216 struct net_device *dev;
217 struct napi_struct napi;
218
219 void __iomem *base;
220 u32 reg_esr;
221 u32 reg_ctrl_default;
222
3d42a379
ST		 223 struct clk *clk_ipg;
224 struct clk *clk_per;
e955cead 225 struct flexcan_platform_data *pdata;
dda0b3bd 226 const struct flexcan_devtype_data *devtype_data;
b7c4114b 227 struct regulator *reg_xceiver;
30c1e672
HW		 228};
229
230static struct flexcan_devtype_data fsl_p1010_devtype_data = {
4f72e5f0 231 .features = FLEXCAN_HAS_BROKEN_ERR_STATE,
30c1e672 232};
4f72e5f0 233static struct flexcan_devtype_data fsl_imx28_devtype_data;
30c1e672 234static struct flexcan_devtype_data fsl_imx6q_devtype_data = {
bb698ca4 235 .features = FLEXCAN_HAS_V10_FEATURES,
e955cead
MKB		 236};
237
194b9a4c 238static const struct can_bittiming_const flexcan_bittiming_const = {
e955cead
MKB		 239 .name = DRV_NAME,
240 .tseg1_min = 4,
241 .tseg1_max = 16,
242 .tseg2_min = 2,
243 .tseg2_max = 8,
244 .sjw_max = 4,
245 .brp_min = 1,
246 .brp_max = 256,
247 .brp_inc = 1,
248};
249
61e271ee 250/*
0e4b949e
AB		 251 * Abstract off the read/write for arm versus ppc. This
252 * assumes that PPC uses big-endian registers and everything
253 * else uses little-endian registers, independent of CPU
254 * endianess.
61e271ee 255 */
0e4b949e 256#if defined(CONFIG_PPC)
61e271ee 257static inline u32 flexcan_read(void __iomem *addr)
258{
259 return in_be32(addr);
260}
261
262static inline void flexcan_write(u32 val, void __iomem *addr)
263{
264 out_be32(addr, val);
265}
266#else
267static inline u32 flexcan_read(void __iomem *addr)
268{
269 return readl(addr);
270}
271
272static inline void flexcan_write(u32 val, void __iomem *addr)
273{
274 writel(val, addr);
275}
276#endif
277
f003698e
MKB		 278static inline int flexcan_transceiver_enable(const struct flexcan_priv *priv)
279{
280 if (!priv->reg_xceiver)
281 return 0;
282
283 return regulator_enable(priv->reg_xceiver);
284}
285
286static inline int flexcan_transceiver_disable(const struct flexcan_priv *priv)
287{
288 if (!priv->reg_xceiver)
289 return 0;
290
291 return regulator_disable(priv->reg_xceiver);
292}
293
e955cead
MKB		 294static inline int flexcan_has_and_handle_berr(const struct flexcan_priv *priv,
295 u32 reg_esr)
296{
297 return (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) &&
298 (reg_esr & FLEXCAN_ESR_ERR_BUS);
299}
300
9b00b300 301static int flexcan_chip_enable(struct flexcan_priv *priv)
e955cead
MKB		 302{
303 struct flexcan_regs __iomem *regs = priv->base;
9b00b300 304 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
e955cead
MKB		 305 u32 reg;
306
61e271ee 307 reg = flexcan_read(&regs->mcr);
e955cead 308 reg &= ~FLEXCAN_MCR_MDIS;
61e271ee 309 flexcan_write(reg, &regs->mcr);
e955cead 310
9b00b300 311 while (timeout-- && (flexcan_read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
8badd65e 312 udelay(10);
9b00b300
MKB		 313
314 if (flexcan_read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK)
315 return -ETIMEDOUT;
316
317 return 0;
e955cead
MKB		 318}
319
9b00b300 320static int flexcan_chip_disable(struct flexcan_priv *priv)
e955cead
MKB		 321{
322 struct flexcan_regs __iomem *regs = priv->base;
9b00b300 323 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
e955cead
MKB		 324 u32 reg;
325
61e271ee 326 reg = flexcan_read(&regs->mcr);
e955cead 327 reg |= FLEXCAN_MCR_MDIS;
61e271ee 328 flexcan_write(reg, &regs->mcr);
9b00b300
MKB		 329
330 while (timeout-- && !(flexcan_read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
8badd65e 331 udelay(10);
9b00b300
MKB		 332
333 if (!(flexcan_read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
334 return -ETIMEDOUT;
335
336 return 0;
e955cead
MKB		 337}
338
b1aa1c7a
MKB		 339static int flexcan_chip_freeze(struct flexcan_priv *priv)
340{
341 struct flexcan_regs __iomem *regs = priv->base;
342 unsigned int timeout = 1000 * 1000 * 10 / priv->can.bittiming.bitrate;
343 u32 reg;
344
345 reg = flexcan_read(&regs->mcr);
346 reg |= FLEXCAN_MCR_HALT;
347 flexcan_write(reg, &regs->mcr);
348
349 while (timeout-- && !(flexcan_read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
8badd65e 350 udelay(100);
b1aa1c7a
MKB		 351
352 if (!(flexcan_read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
353 return -ETIMEDOUT;
354
355 return 0;
356}
357
358static int flexcan_chip_unfreeze(struct flexcan_priv *priv)
359{
360 struct flexcan_regs __iomem *regs = priv->base;
361 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
362 u32 reg;
363
364 reg = flexcan_read(&regs->mcr);
365 reg &= ~FLEXCAN_MCR_HALT;
366 flexcan_write(reg, &regs->mcr);
367
368 while (timeout-- && (flexcan_read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
8badd65e 369 udelay(10);
b1aa1c7a
MKB		 370
371 if (flexcan_read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK)
372 return -ETIMEDOUT;
373
374 return 0;
375}
376
4b5b8227
MKB		 377static int flexcan_chip_softreset(struct flexcan_priv *priv)
378{
379 struct flexcan_regs __iomem *regs = priv->base;
380 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
381
382 flexcan_write(FLEXCAN_MCR_SOFTRST, &regs->mcr);
383 while (timeout-- && (flexcan_read(&regs->mcr) & FLEXCAN_MCR_SOFTRST))
8badd65e 384 udelay(10);
4b5b8227
MKB		 385
386 if (flexcan_read(&regs->mcr) & FLEXCAN_MCR_SOFTRST)
387 return -ETIMEDOUT;
388
389 return 0;
390}
391
e955cead
MKB		 392static int flexcan_get_berr_counter(const struct net_device *dev,
393 struct can_berr_counter *bec)
394{
395 const struct flexcan_priv *priv = netdev_priv(dev);
396 struct flexcan_regs __iomem *regs = priv->base;
61e271ee 397 u32 reg = flexcan_read(&regs->ecr);
e955cead
MKB		 398
399 bec->txerr = (reg >> 0) & 0xff;
400 bec->rxerr = (reg >> 8) & 0xff;
401
402 return 0;
403}
404
405static int flexcan_start_xmit(struct sk_buff *skb, struct net_device *dev)
406{
407 const struct flexcan_priv *priv = netdev_priv(dev);
e955cead
MKB		 408 struct flexcan_regs __iomem *regs = priv->base;
409 struct can_frame *cf = (struct can_frame *)skb->data;
410 u32 can_id;
411 u32 ctrl = FLEXCAN_MB_CNT_CODE(0xc) | (cf->can_dlc << 16);
412
413 if (can_dropped_invalid_skb(dev, skb))
414 return NETDEV_TX_OK;
415
416 netif_stop_queue(dev);
417
418 if (cf->can_id & CAN_EFF_FLAG) {
419 can_id = cf->can_id & CAN_EFF_MASK;
420 ctrl |= FLEXCAN_MB_CNT_IDE | FLEXCAN_MB_CNT_SRR;
421 } else {
422 can_id = (cf->can_id & CAN_SFF_MASK) << 18;
423 }
424
425 if (cf->can_id & CAN_RTR_FLAG)
426 ctrl |= FLEXCAN_MB_CNT_RTR;
427
428 if (cf->can_dlc > 0) {
429 u32 data = be32_to_cpup((__be32 *)&cf->data[0]);
61e271ee 430 flexcan_write(data, &regs->cantxfg[FLEXCAN_TX_BUF_ID].data[0]);
e955cead
MKB		 431 }
432 if (cf->can_dlc > 3) {
433 u32 data = be32_to_cpup((__be32 *)&cf->data[4]);
61e271ee 434 flexcan_write(data, &regs->cantxfg[FLEXCAN_TX_BUF_ID].data[1]);
e955cead
MKB		 435 }
436
9a123496
RD		 437 can_put_echo_skb(skb, dev, 0);
438
61e271ee 439 flexcan_write(can_id, &regs->cantxfg[FLEXCAN_TX_BUF_ID].can_id);
440 flexcan_write(ctrl, &regs->cantxfg[FLEXCAN_TX_BUF_ID].can_ctrl);
e955cead 441
e955cead
MKB		 442 return NETDEV_TX_OK;
443}
444
445static void do_bus_err(struct net_device *dev,
446 struct can_frame *cf, u32 reg_esr)
447{
448 struct flexcan_priv *priv = netdev_priv(dev);
449 int rx_errors = 0, tx_errors = 0;
450
451 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
452
453 if (reg_esr & FLEXCAN_ESR_BIT1_ERR) {
aabdfd6a 454 netdev_dbg(dev, "BIT1_ERR irq\n");
e955cead
MKB		 455 cf->data[2] |= CAN_ERR_PROT_BIT1;
456 tx_errors = 1;
457 }
458 if (reg_esr & FLEXCAN_ESR_BIT0_ERR) {
aabdfd6a 459 netdev_dbg(dev, "BIT0_ERR irq\n");
e955cead
MKB		 460 cf->data[2] |= CAN_ERR_PROT_BIT0;
461 tx_errors = 1;
462 }
463 if (reg_esr & FLEXCAN_ESR_ACK_ERR) {
aabdfd6a 464 netdev_dbg(dev, "ACK_ERR irq\n");
e955cead
MKB		 465 cf->can_id |= CAN_ERR_ACK;
466 cf->data[3] |= CAN_ERR_PROT_LOC_ACK;
467 tx_errors = 1;
468 }
469 if (reg_esr & FLEXCAN_ESR_CRC_ERR) {
aabdfd6a 470 netdev_dbg(dev, "CRC_ERR irq\n");
e955cead
MKB		 471 cf->data[2] |= CAN_ERR_PROT_BIT;
472 cf->data[3] |= CAN_ERR_PROT_LOC_CRC_SEQ;
473 rx_errors = 1;
474 }
475 if (reg_esr & FLEXCAN_ESR_FRM_ERR) {
aabdfd6a 476 netdev_dbg(dev, "FRM_ERR irq\n");
e955cead
MKB		 477 cf->data[2] |= CAN_ERR_PROT_FORM;
478 rx_errors = 1;
479 }
480 if (reg_esr & FLEXCAN_ESR_STF_ERR) {
aabdfd6a 481 netdev_dbg(dev, "STF_ERR irq\n");
e955cead
MKB		 482 cf->data[2] |= CAN_ERR_PROT_STUFF;
483 rx_errors = 1;
484 }
485
486 priv->can.can_stats.bus_error++;
487 if (rx_errors)
488 dev->stats.rx_errors++;
489 if (tx_errors)
490 dev->stats.tx_errors++;
491}
492
493static int flexcan_poll_bus_err(struct net_device *dev, u32 reg_esr)
494{
495 struct sk_buff *skb;
496 struct can_frame *cf;
497
498 skb = alloc_can_err_skb(dev, &cf);
499 if (unlikely(!skb))
500 return 0;
501
502 do_bus_err(dev, cf, reg_esr);
503 netif_receive_skb(skb);
504
505 dev->stats.rx_packets++;
506 dev->stats.rx_bytes += cf->can_dlc;
507
508 return 1;
509}
510
511static void do_state(struct net_device *dev,
512 struct can_frame *cf, enum can_state new_state)
513{
514 struct flexcan_priv *priv = netdev_priv(dev);
515 struct can_berr_counter bec;
516
517 flexcan_get_berr_counter(dev, &bec);
518
519 switch (priv->can.state) {
520 case CAN_STATE_ERROR_ACTIVE:
521 /*
522 * from: ERROR_ACTIVE
523 * to : ERROR_WARNING, ERROR_PASSIVE, BUS_OFF
524 * => : there was a warning int
525 */
526 if (new_state >= CAN_STATE_ERROR_WARNING &&
527 new_state <= CAN_STATE_BUS_OFF) {
aabdfd6a 528 netdev_dbg(dev, "Error Warning IRQ\n");
e955cead
MKB		 529 priv->can.can_stats.error_warning++;
530
531 cf->can_id |= CAN_ERR_CRTL;
532 cf->data[1] = (bec.txerr > bec.rxerr) ?
533 CAN_ERR_CRTL_TX_WARNING :
534 CAN_ERR_CRTL_RX_WARNING;
535 }
536 case CAN_STATE_ERROR_WARNING: /* fallthrough */
537 /*
538 * from: ERROR_ACTIVE, ERROR_WARNING
539 * to : ERROR_PASSIVE, BUS_OFF
540 * => : error passive int
541 */
542 if (new_state >= CAN_STATE_ERROR_PASSIVE &&
543 new_state <= CAN_STATE_BUS_OFF) {
aabdfd6a 544 netdev_dbg(dev, "Error Passive IRQ\n");
e955cead
MKB		 545 priv->can.can_stats.error_passive++;
546
547 cf->can_id |= CAN_ERR_CRTL;
548 cf->data[1] = (bec.txerr > bec.rxerr) ?
549 CAN_ERR_CRTL_TX_PASSIVE :
550 CAN_ERR_CRTL_RX_PASSIVE;
551 }
552 break;
553 case CAN_STATE_BUS_OFF:
aabdfd6a
WG		 554 netdev_err(dev, "BUG! "
555 "hardware recovered automatically from BUS_OFF\n");
e955cead
MKB		 556 break;
557 default:
558 break;
559 }
560
561 /* process state changes depending on the new state */
562 switch (new_state) {
8ce261d0
SAS		 563 case CAN_STATE_ERROR_WARNING:
564 netdev_dbg(dev, "Error Warning\n");
565 cf->can_id |= CAN_ERR_CRTL;
566 cf->data[1] = (bec.txerr > bec.rxerr) ?
567 CAN_ERR_CRTL_TX_WARNING :
568 CAN_ERR_CRTL_RX_WARNING;
569 break;
e955cead 570 case CAN_STATE_ERROR_ACTIVE:
aabdfd6a 571 netdev_dbg(dev, "Error Active\n");
e955cead
MKB		 572 cf->can_id |= CAN_ERR_PROT;
573 cf->data[2] = CAN_ERR_PROT_ACTIVE;
574 break;
575 case CAN_STATE_BUS_OFF:
576 cf->can_id |= CAN_ERR_BUSOFF;
577 can_bus_off(dev);
578 break;
579 default:
580 break;
581 }
582}
583
584static int flexcan_poll_state(struct net_device *dev, u32 reg_esr)
585{
586 struct flexcan_priv *priv = netdev_priv(dev);
587 struct sk_buff *skb;
588 struct can_frame *cf;
589 enum can_state new_state;
590 int flt;
591
592 flt = reg_esr & FLEXCAN_ESR_FLT_CONF_MASK;
593 if (likely(flt == FLEXCAN_ESR_FLT_CONF_ACTIVE)) {
594 if (likely(!(reg_esr & (FLEXCAN_ESR_TX_WRN |
595 FLEXCAN_ESR_RX_WRN))))
596 new_state = CAN_STATE_ERROR_ACTIVE;
597 else
598 new_state = CAN_STATE_ERROR_WARNING;
599 } else if (unlikely(flt == FLEXCAN_ESR_FLT_CONF_PASSIVE))
600 new_state = CAN_STATE_ERROR_PASSIVE;
601 else
602 new_state = CAN_STATE_BUS_OFF;
603
604 /* state hasn't changed */
605 if (likely(new_state == priv->can.state))
606 return 0;
607
608 skb = alloc_can_err_skb(dev, &cf);
609 if (unlikely(!skb))
610 return 0;
611
612 do_state(dev, cf, new_state);
613 priv->can.state = new_state;
614 netif_receive_skb(skb);
615
616 dev->stats.rx_packets++;
617 dev->stats.rx_bytes += cf->can_dlc;
618
619 return 1;
620}
621
622static void flexcan_read_fifo(const struct net_device *dev,
623 struct can_frame *cf)
624{
625 const struct flexcan_priv *priv = netdev_priv(dev);
626 struct flexcan_regs __iomem *regs = priv->base;
627 struct flexcan_mb __iomem *mb = &regs->cantxfg[0];
628 u32 reg_ctrl, reg_id;
629
61e271ee 630 reg_ctrl = flexcan_read(&mb->can_ctrl);
631 reg_id = flexcan_read(&mb->can_id);
e955cead
MKB		 632 if (reg_ctrl & FLEXCAN_MB_CNT_IDE)
633 cf->can_id = ((reg_id >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG;
634 else
635 cf->can_id = (reg_id >> 18) & CAN_SFF_MASK;
636
637 if (reg_ctrl & FLEXCAN_MB_CNT_RTR)
638 cf->can_id |= CAN_RTR_FLAG;
639 cf->can_dlc = get_can_dlc((reg_ctrl >> 16) & 0xf);
640
61e271ee 641 *(__be32 *)(cf->data + 0) = cpu_to_be32(flexcan_read(&mb->data[0]));
642 *(__be32 *)(cf->data + 4) = cpu_to_be32(flexcan_read(&mb->data[1]));
e955cead
MKB		 643
644 /* mark as read */
61e271ee 645 flexcan_write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, &regs->iflag1);
646 flexcan_read(&regs->timer);
e955cead
MKB		 647}
648
649static int flexcan_read_frame(struct net_device *dev)
650{
651 struct net_device_stats *stats = &dev->stats;
652 struct can_frame *cf;
653 struct sk_buff *skb;
654
655 skb = alloc_can_skb(dev, &cf);
656 if (unlikely(!skb)) {
657 stats->rx_dropped++;
658 return 0;
659 }
660
661 flexcan_read_fifo(dev, cf);
662 netif_receive_skb(skb);
663
664 stats->rx_packets++;
665 stats->rx_bytes += cf->can_dlc;
666
adccadb9
FB		 667 can_led_event(dev, CAN_LED_EVENT_RX);
668
e955cead
MKB		 669 return 1;
670}
671
672static int flexcan_poll(struct napi_struct *napi, int quota)
673{
674 struct net_device *dev = napi->dev;
675 const struct flexcan_priv *priv = netdev_priv(dev);
676 struct flexcan_regs __iomem *regs = priv->base;
677 u32 reg_iflag1, reg_esr;
678 int work_done = 0;
679
680 /*
681 * The error bits are cleared on read,
682 * use saved value from irq handler.
683 */
61e271ee 684 reg_esr = flexcan_read(&regs->esr) | priv->reg_esr;
e955cead
MKB		 685
686 /* handle state changes */
687 work_done += flexcan_poll_state(dev, reg_esr);
688
689 /* handle RX-FIFO */
61e271ee 690 reg_iflag1 = flexcan_read(&regs->iflag1);
e955cead
MKB		 691 while (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE &&
692 work_done < quota) {
693 work_done += flexcan_read_frame(dev);
61e271ee 694 reg_iflag1 = flexcan_read(&regs->iflag1);
e955cead
MKB		 695 }
696
697 /* report bus errors */
698 if (flexcan_has_and_handle_berr(priv, reg_esr) && work_done < quota)
699 work_done += flexcan_poll_bus_err(dev, reg_esr);
700
701 if (work_done < quota) {
702 napi_complete(napi);
703 /* enable IRQs */
61e271ee 704 flexcan_write(FLEXCAN_IFLAG_DEFAULT, &regs->imask1);
705 flexcan_write(priv->reg_ctrl_default, &regs->ctrl);
e955cead
MKB		 706 }
707
708 return work_done;
709}
710
711static irqreturn_t flexcan_irq(int irq, void *dev_id)
712{
713 struct net_device *dev = dev_id;
714 struct net_device_stats *stats = &dev->stats;
715 struct flexcan_priv *priv = netdev_priv(dev);
716 struct flexcan_regs __iomem *regs = priv->base;
717 u32 reg_iflag1, reg_esr;
718
61e271ee 719 reg_iflag1 = flexcan_read(&regs->iflag1);
720 reg_esr = flexcan_read(&regs->esr);
6e9d554f
WG		 721 /* ACK all bus error and state change IRQ sources */
722 if (reg_esr & FLEXCAN_ESR_ALL_INT)
723 flexcan_write(reg_esr & FLEXCAN_ESR_ALL_INT, &regs->esr);
e955cead
MKB		 724
725 /*
726 * schedule NAPI in case of:
727 * - rx IRQ
728 * - state change IRQ
729 * - bus error IRQ and bus error reporting is activated
730 */
731 if ((reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE) ||
732 (reg_esr & FLEXCAN_ESR_ERR_STATE) ||
733 flexcan_has_and_handle_berr(priv, reg_esr)) {
734 /*
735 * The error bits are cleared on read,
736 * save them for later use.
737 */
738 priv->reg_esr = reg_esr & FLEXCAN_ESR_ERR_BUS;
61e271ee 739 flexcan_write(FLEXCAN_IFLAG_DEFAULT &
740 ~FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, &regs->imask1);
741 flexcan_write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
e955cead
MKB		 742 &regs->ctrl);
743 napi_schedule(&priv->napi);
744 }
745
746 /* FIFO overflow */
747 if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_OVERFLOW) {
61e271ee 748 flexcan_write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW, &regs->iflag1);
e955cead
MKB		 749 dev->stats.rx_over_errors++;
750 dev->stats.rx_errors++;
751 }
752
753 /* transmission complete interrupt */
754 if (reg_iflag1 & (1 << FLEXCAN_TX_BUF_ID)) {
9a123496 755 stats->tx_bytes += can_get_echo_skb(dev, 0);
e955cead 756 stats->tx_packets++;
adccadb9 757 can_led_event(dev, CAN_LED_EVENT_TX);
61e271ee 758 flexcan_write((1 << FLEXCAN_TX_BUF_ID), &regs->iflag1);
e955cead
MKB		 759 netif_wake_queue(dev);
760 }
761
762 return IRQ_HANDLED;
763}
764
765static void flexcan_set_bittiming(struct net_device *dev)
766{
767 const struct flexcan_priv *priv = netdev_priv(dev);
768 const struct can_bittiming *bt = &priv->can.bittiming;
769 struct flexcan_regs __iomem *regs = priv->base;
770 u32 reg;
771
61e271ee 772 reg = flexcan_read(&regs->ctrl);
e955cead
MKB		 773 reg &= ~(FLEXCAN_CTRL_PRESDIV(0xff) |
774 FLEXCAN_CTRL_RJW(0x3) |
775 FLEXCAN_CTRL_PSEG1(0x7) |
776 FLEXCAN_CTRL_PSEG2(0x7) |
777 FLEXCAN_CTRL_PROPSEG(0x7) |
778 FLEXCAN_CTRL_LPB |
779 FLEXCAN_CTRL_SMP |
780 FLEXCAN_CTRL_LOM);
781
782 reg |= FLEXCAN_CTRL_PRESDIV(bt->brp - 1) |
783 FLEXCAN_CTRL_PSEG1(bt->phase_seg1 - 1) |
784 FLEXCAN_CTRL_PSEG2(bt->phase_seg2 - 1) |
785 FLEXCAN_CTRL_RJW(bt->sjw - 1) |
786 FLEXCAN_CTRL_PROPSEG(bt->prop_seg - 1);
787
788 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
789 reg |= FLEXCAN_CTRL_LPB;
790 if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
791 reg |= FLEXCAN_CTRL_LOM;
792 if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES)
793 reg |= FLEXCAN_CTRL_SMP;
794
aabdfd6a 795 netdev_info(dev, "writing ctrl=0x%08x\n", reg);
61e271ee 796 flexcan_write(reg, &regs->ctrl);
e955cead
MKB		 797
798 /* print chip status */
aabdfd6a
WG		 799 netdev_dbg(dev, "%s: mcr=0x%08x ctrl=0x%08x\n", __func__,
800 flexcan_read(&regs->mcr), flexcan_read(&regs->ctrl));
e955cead
MKB		 801}
802
803/*
804 * flexcan_chip_start
805 *
806 * this functions is entered with clocks enabled
807 *
808 */
809static int flexcan_chip_start(struct net_device *dev)
810{
811 struct flexcan_priv *priv = netdev_priv(dev);
812 struct flexcan_regs __iomem *regs = priv->base;
e955cead
MKB		 813 int err;
814 u32 reg_mcr, reg_ctrl;
815
816 /* enable module */
9b00b300
MKB		 817 err = flexcan_chip_enable(priv);
818 if (err)
819 return err;
e955cead
MKB		 820
821 /* soft reset */
4b5b8227
MKB		 822 err = flexcan_chip_softreset(priv);
823 if (err)
b1aa1c7a 824 goto out_chip_disable;
e955cead
MKB		 825
826 flexcan_set_bittiming(dev);
827
828 /*
829 * MCR
830 *
831 * enable freeze
832 * enable fifo
833 * halt now
834 * only supervisor access
835 * enable warning int
836 * choose format C
9a123496 837 * disable local echo
e955cead
MKB		 838 *
839 */
61e271ee 840 reg_mcr = flexcan_read(&regs->mcr);
d5a7b406 841 reg_mcr &= ~FLEXCAN_MCR_MAXMB(0xff);
e955cead
MKB		 842 reg_mcr |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_FEN | FLEXCAN_MCR_HALT |
843 FLEXCAN_MCR_SUPV | FLEXCAN_MCR_WRN_EN |
d5a7b406
MKB		 844 FLEXCAN_MCR_IDAM_C | FLEXCAN_MCR_SRX_DIS |
845 FLEXCAN_MCR_MAXMB(FLEXCAN_TX_BUF_ID);
aabdfd6a 846 netdev_dbg(dev, "%s: writing mcr=0x%08x", __func__, reg_mcr);
61e271ee 847 flexcan_write(reg_mcr, &regs->mcr);
e955cead
MKB		 848
849 /*
850 * CTRL
851 *
852 * disable timer sync feature
853 *
854 * disable auto busoff recovery
855 * transmit lowest buffer first
856 *
857 * enable tx and rx warning interrupt
858 * enable bus off interrupt
859 * (== FLEXCAN_CTRL_ERR_STATE)
e955cead 860 */
61e271ee 861 reg_ctrl = flexcan_read(&regs->ctrl);
e955cead
MKB		 862 reg_ctrl &= ~FLEXCAN_CTRL_TSYN;
863 reg_ctrl |= FLEXCAN_CTRL_BOFF_REC | FLEXCAN_CTRL_LBUF |
4f72e5f0
WG		 864 FLEXCAN_CTRL_ERR_STATE;
865 /*
866 * enable the "error interrupt" (FLEXCAN_CTRL_ERR_MSK),
867 * on most Flexcan cores, too. Otherwise we don't get
868 * any error warning or passive interrupts.
869 */
870 if (priv->devtype_data->features & FLEXCAN_HAS_BROKEN_ERR_STATE ||
871 priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)
872 reg_ctrl |= FLEXCAN_CTRL_ERR_MSK;
bc03a541
AS		 873 else
874 reg_ctrl &= ~FLEXCAN_CTRL_ERR_MSK;
e955cead
MKB		 875
876 /* save for later use */
877 priv->reg_ctrl_default = reg_ctrl;
aabdfd6a 878 netdev_dbg(dev, "%s: writing ctrl=0x%08x", __func__, reg_ctrl);
61e271ee 879 flexcan_write(reg_ctrl, &regs->ctrl);
e955cead 880
c32fe4ad
MKB		 881 /* mark TX mailbox as INACTIVE */
882 flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
d5a7b406
MKB		 883 &regs->cantxfg[FLEXCAN_TX_BUF_ID].can_ctrl);
884
e955cead 885 /* acceptance mask/acceptance code (accept everything) */
61e271ee 886 flexcan_write(0x0, &regs->rxgmask);
887 flexcan_write(0x0, &regs->rx14mask);
888 flexcan_write(0x0, &regs->rx15mask);
e955cead 889
4f72e5f0 890 if (priv->devtype_data->features & FLEXCAN_HAS_V10_FEATURES)
30c1e672
HW		 891 flexcan_write(0x0, &regs->rxfgmask);
892
f003698e
MKB		 893 err = flexcan_transceiver_enable(priv);
894 if (err)
b1aa1c7a 895 goto out_chip_disable;
e955cead
MKB		 896
897 /* synchronize with the can bus */
b1aa1c7a
MKB		 898 err = flexcan_chip_unfreeze(priv);
899 if (err)
900 goto out_transceiver_disable;
e955cead
MKB		 901
902 priv->can.state = CAN_STATE_ERROR_ACTIVE;
903
904 /* enable FIFO interrupts */
61e271ee 905 flexcan_write(FLEXCAN_IFLAG_DEFAULT, &regs->imask1);
e955cead
MKB		 906
907 /* print chip status */
aabdfd6a
WG		 908 netdev_dbg(dev, "%s: reading mcr=0x%08x ctrl=0x%08x\n", __func__,
909 flexcan_read(&regs->mcr), flexcan_read(&regs->ctrl));
e955cead
MKB		 910
911 return 0;
912
b1aa1c7a
MKB		 913 out_transceiver_disable:
914 flexcan_transceiver_disable(priv);
915 out_chip_disable:
e955cead
MKB		 916 flexcan_chip_disable(priv);
917 return err;
918}
919
920/*
921 * flexcan_chip_stop
922 *
923 * this functions is entered with clocks enabled
924 *
925 */
926static void flexcan_chip_stop(struct net_device *dev)
927{
928 struct flexcan_priv *priv = netdev_priv(dev);
929 struct flexcan_regs __iomem *regs = priv->base;
e955cead 930
b1aa1c7a
MKB		 931 /* freeze + disable module */
932 flexcan_chip_freeze(priv);
933 flexcan_chip_disable(priv);
e955cead 934
5be93bdd
MKB		 935 /* Disable all interrupts */
936 flexcan_write(0, &regs->imask1);
937 flexcan_write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
938 &regs->ctrl);
939
f003698e 940 flexcan_transceiver_disable(priv);
e955cead
MKB		 941 priv->can.state = CAN_STATE_STOPPED;
942
943 return;
944}
945
946static int flexcan_open(struct net_device *dev)
947{
948 struct flexcan_priv *priv = netdev_priv(dev);
949 int err;
950
aa10181b
FE		 951 err = clk_prepare_enable(priv->clk_ipg);
952 if (err)
953 return err;
954
955 err = clk_prepare_enable(priv->clk_per);
956 if (err)
957 goto out_disable_ipg;
e955cead
MKB		 958
959 err = open_candev(dev);
960 if (err)
aa10181b 961 goto out_disable_per;
e955cead
MKB		 962
963 err = request_irq(dev->irq, flexcan_irq, IRQF_SHARED, dev->name, dev);
964 if (err)
965 goto out_close;
966
967 /* start chip and queuing */
968 err = flexcan_chip_start(dev);
969 if (err)
7e9e148a 970 goto out_free_irq;
adccadb9
FB		 971
972 can_led_event(dev, CAN_LED_EVENT_OPEN);
973
e955cead
MKB		 974 napi_enable(&priv->napi);
975 netif_start_queue(dev);
976
977 return 0;
978
7e9e148a
MKB		 979 out_free_irq:
980 free_irq(dev->irq, dev);
e955cead
MKB		 981 out_close:
982 close_candev(dev);
aa10181b 983 out_disable_per:
3d42a379 984 clk_disable_unprepare(priv->clk_per);
aa10181b 985 out_disable_ipg:
3d42a379 986 clk_disable_unprepare(priv->clk_ipg);
e955cead
MKB		 987
988 return err;
989}
990
991static int flexcan_close(struct net_device *dev)
992{
993 struct flexcan_priv *priv = netdev_priv(dev);
994
995 netif_stop_queue(dev);
996 napi_disable(&priv->napi);
997 flexcan_chip_stop(dev);
998
999 free_irq(dev->irq, dev);
3d42a379
ST		 1000 clk_disable_unprepare(priv->clk_per);
1001 clk_disable_unprepare(priv->clk_ipg);
e955cead
MKB		 1002
1003 close_candev(dev);
1004
adccadb9
FB		 1005 can_led_event(dev, CAN_LED_EVENT_STOP);
1006
e955cead
MKB		 1007 return 0;
1008}
1009
1010static int flexcan_set_mode(struct net_device *dev, enum can_mode mode)
1011{
1012 int err;
1013
1014 switch (mode) {
1015 case CAN_MODE_START:
1016 err = flexcan_chip_start(dev);
1017 if (err)
1018 return err;
1019
1020 netif_wake_queue(dev);
1021 break;
1022
1023 default:
1024 return -EOPNOTSUPP;
1025 }
1026
1027 return 0;
1028}
1029
1030static const struct net_device_ops flexcan_netdev_ops = {
1031 .ndo_open = flexcan_open,
1032 .ndo_stop = flexcan_close,
1033 .ndo_start_xmit = flexcan_start_xmit,
c971fa2a 1034 .ndo_change_mtu = can_change_mtu,
e955cead
MKB		 1035};
1036
3c8ac0f2 1037static int register_flexcandev(struct net_device *dev)
e955cead
MKB		 1038{
1039 struct flexcan_priv *priv = netdev_priv(dev);
1040 struct flexcan_regs __iomem *regs = priv->base;
1041 u32 reg, err;
1042
aa10181b
FE		 1043 err = clk_prepare_enable(priv->clk_ipg);
1044 if (err)
1045 return err;
1046
1047 err = clk_prepare_enable(priv->clk_per);
1048 if (err)
1049 goto out_disable_ipg;
e955cead
MKB		 1050
1051 /* select "bus clock", chip must be disabled */
9b00b300
MKB		 1052 err = flexcan_chip_disable(priv);
1053 if (err)
1054 goto out_disable_per;
61e271ee 1055 reg = flexcan_read(&regs->ctrl);
e955cead 1056 reg |= FLEXCAN_CTRL_CLK_SRC;
61e271ee 1057 flexcan_write(reg, &regs->ctrl);
e955cead 1058
9b00b300
MKB		 1059 err = flexcan_chip_enable(priv);
1060 if (err)
1061 goto out_chip_disable;
e955cead
MKB		 1062
1063 /* set freeze, halt and activate FIFO, restrict register access */
61e271ee 1064 reg = flexcan_read(&regs->mcr);
e955cead
MKB		 1065 reg |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT |
1066 FLEXCAN_MCR_FEN | FLEXCAN_MCR_SUPV;
61e271ee 1067 flexcan_write(reg, &regs->mcr);
e955cead
MKB		 1068
1069 /*
1070 * Currently we only support newer versions of this core
1071 * featuring a RX FIFO. Older cores found on some Coldfire
1072 * derivates are not yet supported.
1073 */
61e271ee 1074 reg = flexcan_read(&regs->mcr);
e955cead 1075 if (!(reg & FLEXCAN_MCR_FEN)) {
aabdfd6a 1076 netdev_err(dev, "Could not enable RX FIFO, unsupported core\n");
e955cead 1077 err = -ENODEV;
9b00b300 1078 goto out_chip_disable;
e955cead
MKB		 1079 }
1080
1081 err = register_candev(dev);
1082
e955cead 1083 /* disable core and turn off clocks */
9b00b300 1084 out_chip_disable:
e955cead 1085 flexcan_chip_disable(priv);
9b00b300 1086 out_disable_per:
3d42a379 1087 clk_disable_unprepare(priv->clk_per);
aa10181b 1088 out_disable_ipg:
3d42a379 1089 clk_disable_unprepare(priv->clk_ipg);
e955cead
MKB		 1090
1091 return err;
1092}
1093
3c8ac0f2 1094static void unregister_flexcandev(struct net_device *dev)
e955cead
MKB		 1095{
1096 unregister_candev(dev);
1097}
1098
30c1e672 1099static const struct of_device_id flexcan_of_match[] = {
30c1e672 1100 { .compatible = "fsl,imx6q-flexcan", .data = &fsl_imx6q_devtype_data, },
e3587842
MKB		 1101 { .compatible = "fsl,imx28-flexcan", .data = &fsl_imx28_devtype_data, },
1102 { .compatible = "fsl,p1010-flexcan", .data = &fsl_p1010_devtype_data, },
30c1e672
HW		 1103 { /* sentinel */ },
1104};
4358a9dc 1105MODULE_DEVICE_TABLE(of, flexcan_of_match);
30c1e672
HW		 1106
1107static const struct platform_device_id flexcan_id_table[] = {
1108 { .name = "flexcan", .driver_data = (kernel_ulong_t)&fsl_p1010_devtype_data, },
1109 { /* sentinel */ },
1110};
4358a9dc 1111MODULE_DEVICE_TABLE(platform, flexcan_id_table);
30c1e672 1112
3c8ac0f2 1113static int flexcan_probe(struct platform_device *pdev)
e955cead 1114{
30c1e672 1115 const struct of_device_id *of_id;
dda0b3bd 1116 const struct flexcan_devtype_data *devtype_data;
e955cead
MKB		 1117 struct net_device *dev;
1118 struct flexcan_priv *priv;
1119 struct resource *mem;
3d42a379 1120 struct clk *clk_ipg = NULL, *clk_per = NULL;
e955cead 1121 void __iomem *base;
e955cead 1122 int err, irq;
97efe9ae 1123 u32 clock_freq = 0;
1124
afc016d8
HW		 1125 if (pdev->dev.of_node)
1126 of_property_read_u32(pdev->dev.of_node,
1127 "clock-frequency", &clock_freq);
97efe9ae 1128
1129 if (!clock_freq) {
3d42a379
ST		 1130 clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1131 if (IS_ERR(clk_ipg)) {
1132 dev_err(&pdev->dev, "no ipg clock defined\n");
933e4af4 1133 return PTR_ERR(clk_ipg);
3d42a379 1134 }
3d42a379
ST		 1135
1136 clk_per = devm_clk_get(&pdev->dev, "per");
1137 if (IS_ERR(clk_per)) {
1138 dev_err(&pdev->dev, "no per clock defined\n");
933e4af4 1139 return PTR_ERR(clk_per);
97efe9ae 1140 }
1a3e5173 1141 clock_freq = clk_get_rate(clk_per);
e955cead
MKB		 1142 }
1143
1144 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1145 irq = platform_get_irq(pdev, 0);
933e4af4
FE		 1146 if (irq <= 0)
1147 return -ENODEV;
e955cead 1148
933e4af4
FE		 1149 base = devm_ioremap_resource(&pdev->dev, mem);
1150 if (IS_ERR(base))
1151 return PTR_ERR(base);
e955cead 1152
30c1e672
HW		 1153 of_id = of_match_device(flexcan_of_match, &pdev->dev);
1154 if (of_id) {
1155 devtype_data = of_id->data;
d0873e6f 1156 } else if (platform_get_device_id(pdev)->driver_data) {
30c1e672 1157 devtype_data = (struct flexcan_devtype_data *)
d0873e6f 1158 platform_get_device_id(pdev)->driver_data;
30c1e672 1159 } else {
933e4af4 1160 return -ENODEV;
30c1e672
HW		 1161 }
1162
933e4af4
FE		 1163 dev = alloc_candev(sizeof(struct flexcan_priv), 1);
1164 if (!dev)
1165 return -ENOMEM;
1166
e955cead
MKB		 1167 dev->netdev_ops = &flexcan_netdev_ops;
1168 dev->irq = irq;
9a123496 1169 dev->flags |= IFF_ECHO;
e955cead
MKB		 1170
1171 priv = netdev_priv(dev);
97efe9ae 1172 priv->can.clock.freq = clock_freq;
e955cead
MKB		 1173 priv->can.bittiming_const = &flexcan_bittiming_const;
1174 priv->can.do_set_mode = flexcan_set_mode;
1175 priv->can.do_get_berr_counter = flexcan_get_berr_counter;
1176 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
1177 CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_3_SAMPLES |
1178 CAN_CTRLMODE_BERR_REPORTING;
1179 priv->base = base;
1180 priv->dev = dev;
3d42a379
ST		 1181 priv->clk_ipg = clk_ipg;
1182 priv->clk_per = clk_per;
84ae6643 1183 priv->pdata = dev_get_platdata(&pdev->dev);
30c1e672 1184 priv->devtype_data = devtype_data;
e955cead 1185
b7c4114b
FE		 1186 priv->reg_xceiver = devm_regulator_get(&pdev->dev, "xceiver");
1187 if (IS_ERR(priv->reg_xceiver))
1188 priv->reg_xceiver = NULL;
1189
e955cead
MKB		 1190 netif_napi_add(dev, &priv->napi, flexcan_poll, FLEXCAN_NAPI_WEIGHT);
1191
d75ea942 1192 platform_set_drvdata(pdev, dev);
e955cead
MKB		 1193 SET_NETDEV_DEV(dev, &pdev->dev);
1194
1195 err = register_flexcandev(dev);
1196 if (err) {
1197 dev_err(&pdev->dev, "registering netdev failed\n");
1198 goto failed_register;
1199 }
1200
adccadb9
FB		 1201 devm_can_led_init(dev);
1202
e955cead
MKB		 1203 dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%d)\n",
1204 priv->base, dev->irq);
1205
1206 return 0;
1207
1208 failed_register:
1209 free_candev(dev);
e955cead
MKB		 1210 return err;
1211}
1212
3c8ac0f2 1213static int flexcan_remove(struct platform_device *pdev)
e955cead
MKB		 1214{
1215 struct net_device *dev = platform_get_drvdata(pdev);
d96e43e8 1216 struct flexcan_priv *priv = netdev_priv(dev);
e955cead
MKB		 1217
1218 unregister_flexcandev(dev);
d96e43e8 1219 netif_napi_del(&priv->napi);
9a27586d
MKB		 1220 free_candev(dev);
1221
e955cead
MKB		 1222 return 0;
1223}
1224
08c6d351 1225static int __maybe_unused flexcan_suspend(struct device *device)
8b5e218d 1226{
588e7a8e 1227 struct net_device *dev = dev_get_drvdata(device);
8b5e218d 1228 struct flexcan_priv *priv = netdev_priv(dev);
9b00b300 1229 int err;
8b5e218d 1230
9b00b300
MKB		 1231 err = flexcan_chip_disable(priv);
1232 if (err)
1233 return err;
8b5e218d
EB		 1234
1235 if (netif_running(dev)) {
1236 netif_stop_queue(dev);
1237 netif_device_detach(dev);
1238 }
1239 priv->can.state = CAN_STATE_SLEEPING;
1240
1241 return 0;
1242}
1243
08c6d351 1244static int __maybe_unused flexcan_resume(struct device *device)
8b5e218d 1245{
588e7a8e 1246 struct net_device *dev = dev_get_drvdata(device);
8b5e218d
EB		 1247 struct flexcan_priv *priv = netdev_priv(dev);
1248
1249 priv->can.state = CAN_STATE_ERROR_ACTIVE;
1250 if (netif_running(dev)) {
1251 netif_device_attach(dev);
1252 netif_start_queue(dev);
1253 }
9b00b300 1254 return flexcan_chip_enable(priv);
8b5e218d 1255}
588e7a8e
FE		 1256
1257static SIMPLE_DEV_PM_OPS(flexcan_pm_ops, flexcan_suspend, flexcan_resume);
8b5e218d 1258
e955cead 1259static struct platform_driver flexcan_driver = {
c8aef4cb 1260 .driver = {
1261 .name = DRV_NAME,
1262 .owner = THIS_MODULE,
588e7a8e 1263 .pm = &flexcan_pm_ops,
c8aef4cb 1264 .of_match_table = flexcan_of_match,
1265 },
e955cead 1266 .probe = flexcan_probe,
3c8ac0f2 1267 .remove = flexcan_remove,
30c1e672 1268 .id_table = flexcan_id_table,
e955cead
MKB		 1269};
1270
871d3372 1271module_platform_driver(flexcan_driver);
e955cead
MKB		 1272
1273MODULE_AUTHOR("Sascha Hauer <kernel@pengutronix.de>, "
1274 "Marc Kleine-Budde <kernel@pengutronix.de>");
1275MODULE_LICENSE("GPL v2");
1276MODULE_DESCRIPTION("CAN port driver for flexcan based chip");
Linux kernel - Deliverables
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