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can: flexcan: flexcan_remove(): add missing netif_napi_del()
[deliverable/linux.git] / drivers / net / can / flexcan.c
CommitLineData
e955cead
MKB		 1/*
2 * flexcan.c - FLEXCAN CAN controller driver
3 *
4 * Copyright (c) 2005-2006 Varma Electronics Oy
5 * Copyright (c) 2009 Sascha Hauer, Pengutronix
6 * Copyright (c) 2010 Marc Kleine-Budde, Pengutronix
7 *
8 * Based on code originally by Andrey Volkov <avolkov@varma-el.com>
9 *
10 * LICENCE:
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation version 2.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 */
21
22#include <linux/netdevice.h>
23#include <linux/can.h>
24#include <linux/can/dev.h>
25#include <linux/can/error.h>
adccadb9 26#include <linux/can/led.h>
e955cead
MKB		 27#include <linux/clk.h>
28#include <linux/delay.h>
29#include <linux/if_arp.h>
30#include <linux/if_ether.h>
31#include <linux/interrupt.h>
32#include <linux/io.h>
33#include <linux/kernel.h>
34#include <linux/list.h>
35#include <linux/module.h>
97efe9ae 36#include <linux/of.h>
30c1e672 37#include <linux/of_device.h>
e955cead 38#include <linux/platform_device.h>
b7c4114b 39#include <linux/regulator/consumer.h>
e955cead 40
e955cead
MKB		 41#define DRV_NAME "flexcan"
42
43/* 8 for RX fifo and 2 error handling */
44#define FLEXCAN_NAPI_WEIGHT (8 + 2)
45
46/* FLEXCAN module configuration register (CANMCR) bits */
47#define FLEXCAN_MCR_MDIS BIT(31)
48#define FLEXCAN_MCR_FRZ BIT(30)
49#define FLEXCAN_MCR_FEN BIT(29)
50#define FLEXCAN_MCR_HALT BIT(28)
51#define FLEXCAN_MCR_NOT_RDY BIT(27)
52#define FLEXCAN_MCR_WAK_MSK BIT(26)
53#define FLEXCAN_MCR_SOFTRST BIT(25)
54#define FLEXCAN_MCR_FRZ_ACK BIT(24)
55#define FLEXCAN_MCR_SUPV BIT(23)
56#define FLEXCAN_MCR_SLF_WAK BIT(22)
57#define FLEXCAN_MCR_WRN_EN BIT(21)
58#define FLEXCAN_MCR_LPM_ACK BIT(20)
59#define FLEXCAN_MCR_WAK_SRC BIT(19)
60#define FLEXCAN_MCR_DOZE BIT(18)
61#define FLEXCAN_MCR_SRX_DIS BIT(17)
62#define FLEXCAN_MCR_BCC BIT(16)
63#define FLEXCAN_MCR_LPRIO_EN BIT(13)
64#define FLEXCAN_MCR_AEN BIT(12)
d5a7b406 65#define FLEXCAN_MCR_MAXMB(x) ((x) & 0x1f)
e955cead
MKB		 66#define FLEXCAN_MCR_IDAM_A (0 << 8)
67#define FLEXCAN_MCR_IDAM_B (1 << 8)
68#define FLEXCAN_MCR_IDAM_C (2 << 8)
69#define FLEXCAN_MCR_IDAM_D (3 << 8)
70
71/* FLEXCAN control register (CANCTRL) bits */
72#define FLEXCAN_CTRL_PRESDIV(x) (((x) & 0xff) << 24)
73#define FLEXCAN_CTRL_RJW(x) (((x) & 0x03) << 22)
74#define FLEXCAN_CTRL_PSEG1(x) (((x) & 0x07) << 19)
75#define FLEXCAN_CTRL_PSEG2(x) (((x) & 0x07) << 16)
76#define FLEXCAN_CTRL_BOFF_MSK BIT(15)
77#define FLEXCAN_CTRL_ERR_MSK BIT(14)
78#define FLEXCAN_CTRL_CLK_SRC BIT(13)
79#define FLEXCAN_CTRL_LPB BIT(12)
80#define FLEXCAN_CTRL_TWRN_MSK BIT(11)
81#define FLEXCAN_CTRL_RWRN_MSK BIT(10)
82#define FLEXCAN_CTRL_SMP BIT(7)
83#define FLEXCAN_CTRL_BOFF_REC BIT(6)
84#define FLEXCAN_CTRL_TSYN BIT(5)
85#define FLEXCAN_CTRL_LBUF BIT(4)
86#define FLEXCAN_CTRL_LOM BIT(3)
87#define FLEXCAN_CTRL_PROPSEG(x) ((x) & 0x07)
88#define FLEXCAN_CTRL_ERR_BUS (FLEXCAN_CTRL_ERR_MSK)
89#define FLEXCAN_CTRL_ERR_STATE \
90 (FLEXCAN_CTRL_TWRN_MSK | FLEXCAN_CTRL_RWRN_MSK | \
91 FLEXCAN_CTRL_BOFF_MSK)
92#define FLEXCAN_CTRL_ERR_ALL \
93 (FLEXCAN_CTRL_ERR_BUS | FLEXCAN_CTRL_ERR_STATE)
94
95/* FLEXCAN error and status register (ESR) bits */
96#define FLEXCAN_ESR_TWRN_INT BIT(17)
97#define FLEXCAN_ESR_RWRN_INT BIT(16)
98#define FLEXCAN_ESR_BIT1_ERR BIT(15)
99#define FLEXCAN_ESR_BIT0_ERR BIT(14)
100#define FLEXCAN_ESR_ACK_ERR BIT(13)
101#define FLEXCAN_ESR_CRC_ERR BIT(12)
102#define FLEXCAN_ESR_FRM_ERR BIT(11)
103#define FLEXCAN_ESR_STF_ERR BIT(10)
104#define FLEXCAN_ESR_TX_WRN BIT(9)
105#define FLEXCAN_ESR_RX_WRN BIT(8)
106#define FLEXCAN_ESR_IDLE BIT(7)
107#define FLEXCAN_ESR_TXRX BIT(6)
108#define FLEXCAN_EST_FLT_CONF_SHIFT (4)
109#define FLEXCAN_ESR_FLT_CONF_MASK (0x3 << FLEXCAN_EST_FLT_CONF_SHIFT)
110#define FLEXCAN_ESR_FLT_CONF_ACTIVE (0x0 << FLEXCAN_EST_FLT_CONF_SHIFT)
111#define FLEXCAN_ESR_FLT_CONF_PASSIVE (0x1 << FLEXCAN_EST_FLT_CONF_SHIFT)
112#define FLEXCAN_ESR_BOFF_INT BIT(2)
113#define FLEXCAN_ESR_ERR_INT BIT(1)
114#define FLEXCAN_ESR_WAK_INT BIT(0)
115#define FLEXCAN_ESR_ERR_BUS \
116 (FLEXCAN_ESR_BIT1_ERR | FLEXCAN_ESR_BIT0_ERR | \
117 FLEXCAN_ESR_ACK_ERR | FLEXCAN_ESR_CRC_ERR | \
118 FLEXCAN_ESR_FRM_ERR | FLEXCAN_ESR_STF_ERR)
119#define FLEXCAN_ESR_ERR_STATE \
120 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | FLEXCAN_ESR_BOFF_INT)
121#define FLEXCAN_ESR_ERR_ALL \
122 (FLEXCAN_ESR_ERR_BUS | FLEXCAN_ESR_ERR_STATE)
6e9d554f
WG		 123#define FLEXCAN_ESR_ALL_INT \
124 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | \
125 FLEXCAN_ESR_BOFF_INT | FLEXCAN_ESR_ERR_INT)
e955cead
MKB		 126
127/* FLEXCAN interrupt flag register (IFLAG) bits */
128#define FLEXCAN_TX_BUF_ID 8
129#define FLEXCAN_IFLAG_BUF(x) BIT(x)
130#define FLEXCAN_IFLAG_RX_FIFO_OVERFLOW BIT(7)
131#define FLEXCAN_IFLAG_RX_FIFO_WARN BIT(6)
132#define FLEXCAN_IFLAG_RX_FIFO_AVAILABLE BIT(5)
133#define FLEXCAN_IFLAG_DEFAULT \
134 (FLEXCAN_IFLAG_RX_FIFO_OVERFLOW | FLEXCAN_IFLAG_RX_FIFO_AVAILABLE | \
135 FLEXCAN_IFLAG_BUF(FLEXCAN_TX_BUF_ID))
136
137/* FLEXCAN message buffers */
138#define FLEXCAN_MB_CNT_CODE(x) (((x) & 0xf) << 24)
139#define FLEXCAN_MB_CNT_SRR BIT(22)
140#define FLEXCAN_MB_CNT_IDE BIT(21)
141#define FLEXCAN_MB_CNT_RTR BIT(20)
142#define FLEXCAN_MB_CNT_LENGTH(x) (((x) & 0xf) << 16)
143#define FLEXCAN_MB_CNT_TIMESTAMP(x) ((x) & 0xffff)
144
145#define FLEXCAN_MB_CODE_MASK (0xf0ffffff)
146
9b00b300
MKB		 147#define FLEXCAN_TIMEOUT_US (50)
148
bb698ca4
WG		 149/*
150 * FLEXCAN hardware feature flags
151 *
152 * Below is some version info we got:
153 * SOC Version IP-Version Glitch- [TR]WRN_INT
154 * Filter? connected?
155 * MX25 FlexCAN2 03.00.00.00 no no
156 * MX28 FlexCAN2 03.00.04.00 yes yes
157 * MX35 FlexCAN2 03.00.00.00 no no
158 * MX53 FlexCAN2 03.00.00.00 yes no
159 * MX6s FlexCAN3 10.00.12.00 yes yes
160 *
161 * Some SOCs do not have the RX_WARN & TX_WARN interrupt line connected.
162 */
4f72e5f0 163#define FLEXCAN_HAS_V10_FEATURES BIT(1) /* For core version >= 10 */
bb698ca4 164#define FLEXCAN_HAS_BROKEN_ERR_STATE BIT(2) /* [TR]WRN_INT not connected */
4f72e5f0 165
e955cead
MKB		 166/* Structure of the message buffer */
167struct flexcan_mb {
168 u32 can_ctrl;
169 u32 can_id;
170 u32 data[2];
171};
172
173/* Structure of the hardware registers */
174struct flexcan_regs {
175 u32 mcr; /* 0x00 */
176 u32 ctrl; /* 0x04 */
177 u32 timer; /* 0x08 */
178 u32 _reserved1; /* 0x0c */
179 u32 rxgmask; /* 0x10 */
180 u32 rx14mask; /* 0x14 */
181 u32 rx15mask; /* 0x18 */
182 u32 ecr; /* 0x1c */
183 u32 esr; /* 0x20 */
184 u32 imask2; /* 0x24 */
185 u32 imask1; /* 0x28 */
186 u32 iflag2; /* 0x2c */
187 u32 iflag1; /* 0x30 */
30c1e672
HW		 188 u32 crl2; /* 0x34 */
189 u32 esr2; /* 0x38 */
190 u32 imeur; /* 0x3c */
191 u32 lrfr; /* 0x40 */
192 u32 crcr; /* 0x44 */
193 u32 rxfgmask; /* 0x48 */
194 u32 rxfir; /* 0x4c */
195 u32 _reserved3[12];
e955cead
MKB		 196 struct flexcan_mb cantxfg[64];
197};
198
30c1e672 199struct flexcan_devtype_data {
4f72e5f0 200 u32 features; /* hardware controller features */
30c1e672
HW		 201};
202
e955cead
MKB		 203struct flexcan_priv {
204 struct can_priv can;
205 struct net_device *dev;
206 struct napi_struct napi;
207
208 void __iomem *base;
209 u32 reg_esr;
210 u32 reg_ctrl_default;
211
3d42a379
ST		 212 struct clk *clk_ipg;
213 struct clk *clk_per;
e955cead 214 struct flexcan_platform_data *pdata;
dda0b3bd 215 const struct flexcan_devtype_data *devtype_data;
b7c4114b 216 struct regulator *reg_xceiver;
30c1e672
HW		 217};
218
219static struct flexcan_devtype_data fsl_p1010_devtype_data = {
4f72e5f0 220 .features = FLEXCAN_HAS_BROKEN_ERR_STATE,
30c1e672 221};
4f72e5f0 222static struct flexcan_devtype_data fsl_imx28_devtype_data;
30c1e672 223static struct flexcan_devtype_data fsl_imx6q_devtype_data = {
bb698ca4 224 .features = FLEXCAN_HAS_V10_FEATURES,
e955cead
MKB		 225};
226
194b9a4c 227static const struct can_bittiming_const flexcan_bittiming_const = {
e955cead
MKB		 228 .name = DRV_NAME,
229 .tseg1_min = 4,
230 .tseg1_max = 16,
231 .tseg2_min = 2,
232 .tseg2_max = 8,
233 .sjw_max = 4,
234 .brp_min = 1,
235 .brp_max = 256,
236 .brp_inc = 1,
237};
238
61e271ee 239/*
0e4b949e
AB		 240 * Abstract off the read/write for arm versus ppc. This
241 * assumes that PPC uses big-endian registers and everything
242 * else uses little-endian registers, independent of CPU
243 * endianess.
61e271ee 244 */
0e4b949e 245#if defined(CONFIG_PPC)
61e271ee 246static inline u32 flexcan_read(void __iomem *addr)
247{
248 return in_be32(addr);
249}
250
251static inline void flexcan_write(u32 val, void __iomem *addr)
252{
253 out_be32(addr, val);
254}
255#else
256static inline u32 flexcan_read(void __iomem *addr)
257{
258 return readl(addr);
259}
260
261static inline void flexcan_write(u32 val, void __iomem *addr)
262{
263 writel(val, addr);
264}
265#endif
266
f003698e
MKB		 267static inline int flexcan_transceiver_enable(const struct flexcan_priv *priv)
268{
269 if (!priv->reg_xceiver)
270 return 0;
271
272 return regulator_enable(priv->reg_xceiver);
273}
274
275static inline int flexcan_transceiver_disable(const struct flexcan_priv *priv)
276{
277 if (!priv->reg_xceiver)
278 return 0;
279
280 return regulator_disable(priv->reg_xceiver);
281}
282
e955cead
MKB		 283static inline int flexcan_has_and_handle_berr(const struct flexcan_priv *priv,
284 u32 reg_esr)
285{
286 return (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) &&
287 (reg_esr & FLEXCAN_ESR_ERR_BUS);
288}
289
9b00b300 290static int flexcan_chip_enable(struct flexcan_priv *priv)
e955cead
MKB		 291{
292 struct flexcan_regs __iomem *regs = priv->base;
9b00b300 293 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
e955cead
MKB		 294 u32 reg;
295
61e271ee 296 reg = flexcan_read(&regs->mcr);
e955cead 297 reg &= ~FLEXCAN_MCR_MDIS;
61e271ee 298 flexcan_write(reg, &regs->mcr);
e955cead 299
9b00b300
MKB		 300 while (timeout-- && (flexcan_read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
301 usleep_range(10, 20);
302
303 if (flexcan_read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK)
304 return -ETIMEDOUT;
305
306 return 0;
e955cead
MKB		 307}
308
9b00b300 309static int flexcan_chip_disable(struct flexcan_priv *priv)
e955cead
MKB		 310{
311 struct flexcan_regs __iomem *regs = priv->base;
9b00b300 312 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
e955cead
MKB		 313 u32 reg;
314
61e271ee 315 reg = flexcan_read(&regs->mcr);
e955cead 316 reg |= FLEXCAN_MCR_MDIS;
61e271ee 317 flexcan_write(reg, &regs->mcr);
9b00b300
MKB		 318
319 while (timeout-- && !(flexcan_read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
320 usleep_range(10, 20);
321
322 if (!(flexcan_read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
323 return -ETIMEDOUT;
324
325 return 0;
e955cead
MKB		 326}
327
b1aa1c7a
MKB		 328static int flexcan_chip_freeze(struct flexcan_priv *priv)
329{
330 struct flexcan_regs __iomem *regs = priv->base;
331 unsigned int timeout = 1000 * 1000 * 10 / priv->can.bittiming.bitrate;
332 u32 reg;
333
334 reg = flexcan_read(&regs->mcr);
335 reg |= FLEXCAN_MCR_HALT;
336 flexcan_write(reg, &regs->mcr);
337
338 while (timeout-- && !(flexcan_read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
339 usleep_range(100, 200);
340
341 if (!(flexcan_read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
342 return -ETIMEDOUT;
343
344 return 0;
345}
346
347static int flexcan_chip_unfreeze(struct flexcan_priv *priv)
348{
349 struct flexcan_regs __iomem *regs = priv->base;
350 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
351 u32 reg;
352
353 reg = flexcan_read(&regs->mcr);
354 reg &= ~FLEXCAN_MCR_HALT;
355 flexcan_write(reg, &regs->mcr);
356
357 while (timeout-- && (flexcan_read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
358 usleep_range(10, 20);
359
360 if (flexcan_read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK)
361 return -ETIMEDOUT;
362
363 return 0;
364}
365
e955cead
MKB		 366static int flexcan_get_berr_counter(const struct net_device *dev,
367 struct can_berr_counter *bec)
368{
369 const struct flexcan_priv *priv = netdev_priv(dev);
370 struct flexcan_regs __iomem *regs = priv->base;
61e271ee 371 u32 reg = flexcan_read(&regs->ecr);
e955cead
MKB		 372
373 bec->txerr = (reg >> 0) & 0xff;
374 bec->rxerr = (reg >> 8) & 0xff;
375
376 return 0;
377}
378
379static int flexcan_start_xmit(struct sk_buff *skb, struct net_device *dev)
380{
381 const struct flexcan_priv *priv = netdev_priv(dev);
e955cead
MKB		 382 struct flexcan_regs __iomem *regs = priv->base;
383 struct can_frame *cf = (struct can_frame *)skb->data;
384 u32 can_id;
385 u32 ctrl = FLEXCAN_MB_CNT_CODE(0xc) | (cf->can_dlc << 16);
386
387 if (can_dropped_invalid_skb(dev, skb))
388 return NETDEV_TX_OK;
389
390 netif_stop_queue(dev);
391
392 if (cf->can_id & CAN_EFF_FLAG) {
393 can_id = cf->can_id & CAN_EFF_MASK;
394 ctrl |= FLEXCAN_MB_CNT_IDE | FLEXCAN_MB_CNT_SRR;
395 } else {
396 can_id = (cf->can_id & CAN_SFF_MASK) << 18;
397 }
398
399 if (cf->can_id & CAN_RTR_FLAG)
400 ctrl |= FLEXCAN_MB_CNT_RTR;
401
402 if (cf->can_dlc > 0) {
403 u32 data = be32_to_cpup((__be32 *)&cf->data[0]);
61e271ee 404 flexcan_write(data, &regs->cantxfg[FLEXCAN_TX_BUF_ID].data[0]);
e955cead
MKB		 405 }
406 if (cf->can_dlc > 3) {
407 u32 data = be32_to_cpup((__be32 *)&cf->data[4]);
61e271ee 408 flexcan_write(data, &regs->cantxfg[FLEXCAN_TX_BUF_ID].data[1]);
e955cead
MKB		 409 }
410
9a123496
RD		 411 can_put_echo_skb(skb, dev, 0);
412
61e271ee 413 flexcan_write(can_id, &regs->cantxfg[FLEXCAN_TX_BUF_ID].can_id);
414 flexcan_write(ctrl, &regs->cantxfg[FLEXCAN_TX_BUF_ID].can_ctrl);
e955cead 415
e955cead
MKB		 416 return NETDEV_TX_OK;
417}
418
419static void do_bus_err(struct net_device *dev,
420 struct can_frame *cf, u32 reg_esr)
421{
422 struct flexcan_priv *priv = netdev_priv(dev);
423 int rx_errors = 0, tx_errors = 0;
424
425 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
426
427 if (reg_esr & FLEXCAN_ESR_BIT1_ERR) {
aabdfd6a 428 netdev_dbg(dev, "BIT1_ERR irq\n");
e955cead
MKB		 429 cf->data[2] |= CAN_ERR_PROT_BIT1;
430 tx_errors = 1;
431 }
432 if (reg_esr & FLEXCAN_ESR_BIT0_ERR) {
aabdfd6a 433 netdev_dbg(dev, "BIT0_ERR irq\n");
e955cead
MKB		 434 cf->data[2] |= CAN_ERR_PROT_BIT0;
435 tx_errors = 1;
436 }
437 if (reg_esr & FLEXCAN_ESR_ACK_ERR) {
aabdfd6a 438 netdev_dbg(dev, "ACK_ERR irq\n");
e955cead
MKB		 439 cf->can_id |= CAN_ERR_ACK;
440 cf->data[3] |= CAN_ERR_PROT_LOC_ACK;
441 tx_errors = 1;
442 }
443 if (reg_esr & FLEXCAN_ESR_CRC_ERR) {
aabdfd6a 444 netdev_dbg(dev, "CRC_ERR irq\n");
e955cead
MKB		 445 cf->data[2] |= CAN_ERR_PROT_BIT;
446 cf->data[3] |= CAN_ERR_PROT_LOC_CRC_SEQ;
447 rx_errors = 1;
448 }
449 if (reg_esr & FLEXCAN_ESR_FRM_ERR) {
aabdfd6a 450 netdev_dbg(dev, "FRM_ERR irq\n");
e955cead
MKB		 451 cf->data[2] |= CAN_ERR_PROT_FORM;
452 rx_errors = 1;
453 }
454 if (reg_esr & FLEXCAN_ESR_STF_ERR) {
aabdfd6a 455 netdev_dbg(dev, "STF_ERR irq\n");
e955cead
MKB		 456 cf->data[2] |= CAN_ERR_PROT_STUFF;
457 rx_errors = 1;
458 }
459
460 priv->can.can_stats.bus_error++;
461 if (rx_errors)
462 dev->stats.rx_errors++;
463 if (tx_errors)
464 dev->stats.tx_errors++;
465}
466
467static int flexcan_poll_bus_err(struct net_device *dev, u32 reg_esr)
468{
469 struct sk_buff *skb;
470 struct can_frame *cf;
471
472 skb = alloc_can_err_skb(dev, &cf);
473 if (unlikely(!skb))
474 return 0;
475
476 do_bus_err(dev, cf, reg_esr);
477 netif_receive_skb(skb);
478
479 dev->stats.rx_packets++;
480 dev->stats.rx_bytes += cf->can_dlc;
481
482 return 1;
483}
484
485static void do_state(struct net_device *dev,
486 struct can_frame *cf, enum can_state new_state)
487{
488 struct flexcan_priv *priv = netdev_priv(dev);
489 struct can_berr_counter bec;
490
491 flexcan_get_berr_counter(dev, &bec);
492
493 switch (priv->can.state) {
494 case CAN_STATE_ERROR_ACTIVE:
495 /*
496 * from: ERROR_ACTIVE
497 * to : ERROR_WARNING, ERROR_PASSIVE, BUS_OFF
498 * => : there was a warning int
499 */
500 if (new_state >= CAN_STATE_ERROR_WARNING &&
501 new_state <= CAN_STATE_BUS_OFF) {
aabdfd6a 502 netdev_dbg(dev, "Error Warning IRQ\n");
e955cead
MKB		 503 priv->can.can_stats.error_warning++;
504
505 cf->can_id |= CAN_ERR_CRTL;
506 cf->data[1] = (bec.txerr > bec.rxerr) ?
507 CAN_ERR_CRTL_TX_WARNING :
508 CAN_ERR_CRTL_RX_WARNING;
509 }
510 case CAN_STATE_ERROR_WARNING: /* fallthrough */
511 /*
512 * from: ERROR_ACTIVE, ERROR_WARNING
513 * to : ERROR_PASSIVE, BUS_OFF
514 * => : error passive int
515 */
516 if (new_state >= CAN_STATE_ERROR_PASSIVE &&
517 new_state <= CAN_STATE_BUS_OFF) {
aabdfd6a 518 netdev_dbg(dev, "Error Passive IRQ\n");
e955cead
MKB		 519 priv->can.can_stats.error_passive++;
520
521 cf->can_id |= CAN_ERR_CRTL;
522 cf->data[1] = (bec.txerr > bec.rxerr) ?
523 CAN_ERR_CRTL_TX_PASSIVE :
524 CAN_ERR_CRTL_RX_PASSIVE;
525 }
526 break;
527 case CAN_STATE_BUS_OFF:
aabdfd6a
WG		 528 netdev_err(dev, "BUG! "
529 "hardware recovered automatically from BUS_OFF\n");
e955cead
MKB		 530 break;
531 default:
532 break;
533 }
534
535 /* process state changes depending on the new state */
536 switch (new_state) {
537 case CAN_STATE_ERROR_ACTIVE:
aabdfd6a 538 netdev_dbg(dev, "Error Active\n");
e955cead
MKB		 539 cf->can_id |= CAN_ERR_PROT;
540 cf->data[2] = CAN_ERR_PROT_ACTIVE;
541 break;
542 case CAN_STATE_BUS_OFF:
543 cf->can_id |= CAN_ERR_BUSOFF;
544 can_bus_off(dev);
545 break;
546 default:
547 break;
548 }
549}
550
551static int flexcan_poll_state(struct net_device *dev, u32 reg_esr)
552{
553 struct flexcan_priv *priv = netdev_priv(dev);
554 struct sk_buff *skb;
555 struct can_frame *cf;
556 enum can_state new_state;
557 int flt;
558
559 flt = reg_esr & FLEXCAN_ESR_FLT_CONF_MASK;
560 if (likely(flt == FLEXCAN_ESR_FLT_CONF_ACTIVE)) {
561 if (likely(!(reg_esr & (FLEXCAN_ESR_TX_WRN |
562 FLEXCAN_ESR_RX_WRN))))
563 new_state = CAN_STATE_ERROR_ACTIVE;
564 else
565 new_state = CAN_STATE_ERROR_WARNING;
566 } else if (unlikely(flt == FLEXCAN_ESR_FLT_CONF_PASSIVE))
567 new_state = CAN_STATE_ERROR_PASSIVE;
568 else
569 new_state = CAN_STATE_BUS_OFF;
570
571 /* state hasn't changed */
572 if (likely(new_state == priv->can.state))
573 return 0;
574
575 skb = alloc_can_err_skb(dev, &cf);
576 if (unlikely(!skb))
577 return 0;
578
579 do_state(dev, cf, new_state);
580 priv->can.state = new_state;
581 netif_receive_skb(skb);
582
583 dev->stats.rx_packets++;
584 dev->stats.rx_bytes += cf->can_dlc;
585
586 return 1;
587}
588
589static void flexcan_read_fifo(const struct net_device *dev,
590 struct can_frame *cf)
591{
592 const struct flexcan_priv *priv = netdev_priv(dev);
593 struct flexcan_regs __iomem *regs = priv->base;
594 struct flexcan_mb __iomem *mb = &regs->cantxfg[0];
595 u32 reg_ctrl, reg_id;
596
61e271ee 597 reg_ctrl = flexcan_read(&mb->can_ctrl);
598 reg_id = flexcan_read(&mb->can_id);
e955cead
MKB		 599 if (reg_ctrl & FLEXCAN_MB_CNT_IDE)
600 cf->can_id = ((reg_id >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG;
601 else
602 cf->can_id = (reg_id >> 18) & CAN_SFF_MASK;
603
604 if (reg_ctrl & FLEXCAN_MB_CNT_RTR)
605 cf->can_id |= CAN_RTR_FLAG;
606 cf->can_dlc = get_can_dlc((reg_ctrl >> 16) & 0xf);
607
61e271ee 608 *(__be32 *)(cf->data + 0) = cpu_to_be32(flexcan_read(&mb->data[0]));
609 *(__be32 *)(cf->data + 4) = cpu_to_be32(flexcan_read(&mb->data[1]));
e955cead
MKB		 610
611 /* mark as read */
61e271ee 612 flexcan_write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, &regs->iflag1);
613 flexcan_read(&regs->timer);
e955cead
MKB		 614}
615
616static int flexcan_read_frame(struct net_device *dev)
617{
618 struct net_device_stats *stats = &dev->stats;
619 struct can_frame *cf;
620 struct sk_buff *skb;
621
622 skb = alloc_can_skb(dev, &cf);
623 if (unlikely(!skb)) {
624 stats->rx_dropped++;
625 return 0;
626 }
627
628 flexcan_read_fifo(dev, cf);
629 netif_receive_skb(skb);
630
631 stats->rx_packets++;
632 stats->rx_bytes += cf->can_dlc;
633
adccadb9
FB		 634 can_led_event(dev, CAN_LED_EVENT_RX);
635
e955cead
MKB		 636 return 1;
637}
638
639static int flexcan_poll(struct napi_struct *napi, int quota)
640{
641 struct net_device *dev = napi->dev;
642 const struct flexcan_priv *priv = netdev_priv(dev);
643 struct flexcan_regs __iomem *regs = priv->base;
644 u32 reg_iflag1, reg_esr;
645 int work_done = 0;
646
647 /*
648 * The error bits are cleared on read,
649 * use saved value from irq handler.
650 */
61e271ee 651 reg_esr = flexcan_read(&regs->esr) | priv->reg_esr;
e955cead
MKB		 652
653 /* handle state changes */
654 work_done += flexcan_poll_state(dev, reg_esr);
655
656 /* handle RX-FIFO */
61e271ee 657 reg_iflag1 = flexcan_read(&regs->iflag1);
e955cead
MKB		 658 while (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE &&
659 work_done < quota) {
660 work_done += flexcan_read_frame(dev);
61e271ee 661 reg_iflag1 = flexcan_read(&regs->iflag1);
e955cead
MKB		 662 }
663
664 /* report bus errors */
665 if (flexcan_has_and_handle_berr(priv, reg_esr) && work_done < quota)
666 work_done += flexcan_poll_bus_err(dev, reg_esr);
667
668 if (work_done < quota) {
669 napi_complete(napi);
670 /* enable IRQs */
61e271ee 671 flexcan_write(FLEXCAN_IFLAG_DEFAULT, &regs->imask1);
672 flexcan_write(priv->reg_ctrl_default, &regs->ctrl);
e955cead
MKB		 673 }
674
675 return work_done;
676}
677
678static irqreturn_t flexcan_irq(int irq, void *dev_id)
679{
680 struct net_device *dev = dev_id;
681 struct net_device_stats *stats = &dev->stats;
682 struct flexcan_priv *priv = netdev_priv(dev);
683 struct flexcan_regs __iomem *regs = priv->base;
684 u32 reg_iflag1, reg_esr;
685
61e271ee 686 reg_iflag1 = flexcan_read(&regs->iflag1);
687 reg_esr = flexcan_read(&regs->esr);
6e9d554f
WG		 688 /* ACK all bus error and state change IRQ sources */
689 if (reg_esr & FLEXCAN_ESR_ALL_INT)
690 flexcan_write(reg_esr & FLEXCAN_ESR_ALL_INT, &regs->esr);
e955cead
MKB		 691
692 /*
693 * schedule NAPI in case of:
694 * - rx IRQ
695 * - state change IRQ
696 * - bus error IRQ and bus error reporting is activated
697 */
698 if ((reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE) ||
699 (reg_esr & FLEXCAN_ESR_ERR_STATE) ||
700 flexcan_has_and_handle_berr(priv, reg_esr)) {
701 /*
702 * The error bits are cleared on read,
703 * save them for later use.
704 */
705 priv->reg_esr = reg_esr & FLEXCAN_ESR_ERR_BUS;
61e271ee 706 flexcan_write(FLEXCAN_IFLAG_DEFAULT &
707 ~FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, &regs->imask1);
708 flexcan_write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
e955cead
MKB		 709 &regs->ctrl);
710 napi_schedule(&priv->napi);
711 }
712
713 /* FIFO overflow */
714 if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_OVERFLOW) {
61e271ee 715 flexcan_write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW, &regs->iflag1);
e955cead
MKB		 716 dev->stats.rx_over_errors++;
717 dev->stats.rx_errors++;
718 }
719
720 /* transmission complete interrupt */
721 if (reg_iflag1 & (1 << FLEXCAN_TX_BUF_ID)) {
9a123496 722 stats->tx_bytes += can_get_echo_skb(dev, 0);
e955cead 723 stats->tx_packets++;
adccadb9 724 can_led_event(dev, CAN_LED_EVENT_TX);
61e271ee 725 flexcan_write((1 << FLEXCAN_TX_BUF_ID), &regs->iflag1);
e955cead
MKB		 726 netif_wake_queue(dev);
727 }
728
729 return IRQ_HANDLED;
730}
731
732static void flexcan_set_bittiming(struct net_device *dev)
733{
734 const struct flexcan_priv *priv = netdev_priv(dev);
735 const struct can_bittiming *bt = &priv->can.bittiming;
736 struct flexcan_regs __iomem *regs = priv->base;
737 u32 reg;
738
61e271ee 739 reg = flexcan_read(&regs->ctrl);
e955cead
MKB		 740 reg &= ~(FLEXCAN_CTRL_PRESDIV(0xff) |
741 FLEXCAN_CTRL_RJW(0x3) |
742 FLEXCAN_CTRL_PSEG1(0x7) |
743 FLEXCAN_CTRL_PSEG2(0x7) |
744 FLEXCAN_CTRL_PROPSEG(0x7) |
745 FLEXCAN_CTRL_LPB |
746 FLEXCAN_CTRL_SMP |
747 FLEXCAN_CTRL_LOM);
748
749 reg |= FLEXCAN_CTRL_PRESDIV(bt->brp - 1) |
750 FLEXCAN_CTRL_PSEG1(bt->phase_seg1 - 1) |
751 FLEXCAN_CTRL_PSEG2(bt->phase_seg2 - 1) |
752 FLEXCAN_CTRL_RJW(bt->sjw - 1) |
753 FLEXCAN_CTRL_PROPSEG(bt->prop_seg - 1);
754
755 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
756 reg |= FLEXCAN_CTRL_LPB;
757 if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
758 reg |= FLEXCAN_CTRL_LOM;
759 if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES)
760 reg |= FLEXCAN_CTRL_SMP;
761
aabdfd6a 762 netdev_info(dev, "writing ctrl=0x%08x\n", reg);
61e271ee 763 flexcan_write(reg, &regs->ctrl);
e955cead
MKB		 764
765 /* print chip status */
aabdfd6a
WG		 766 netdev_dbg(dev, "%s: mcr=0x%08x ctrl=0x%08x\n", __func__,
767 flexcan_read(&regs->mcr), flexcan_read(&regs->ctrl));
e955cead
MKB		 768}
769
770/*
771 * flexcan_chip_start
772 *
773 * this functions is entered with clocks enabled
774 *
775 */
776static int flexcan_chip_start(struct net_device *dev)
777{
778 struct flexcan_priv *priv = netdev_priv(dev);
779 struct flexcan_regs __iomem *regs = priv->base;
e955cead
MKB		 780 int err;
781 u32 reg_mcr, reg_ctrl;
782
783 /* enable module */
9b00b300
MKB		 784 err = flexcan_chip_enable(priv);
785 if (err)
786 return err;
e955cead
MKB		 787
788 /* soft reset */
61e271ee 789 flexcan_write(FLEXCAN_MCR_SOFTRST, &regs->mcr);
e955cead
MKB		 790 udelay(10);
791
61e271ee 792 reg_mcr = flexcan_read(&regs->mcr);
e955cead 793 if (reg_mcr & FLEXCAN_MCR_SOFTRST) {
aabdfd6a
WG		 794 netdev_err(dev, "Failed to softreset can module (mcr=0x%08x)\n",
795 reg_mcr);
e955cead 796 err = -ENODEV;
b1aa1c7a 797 goto out_chip_disable;
e955cead
MKB		 798 }
799
800 flexcan_set_bittiming(dev);
801
802 /*
803 * MCR
804 *
805 * enable freeze
806 * enable fifo
807 * halt now
808 * only supervisor access
809 * enable warning int
810 * choose format C
9a123496 811 * disable local echo
e955cead
MKB		 812 *
813 */
61e271ee 814 reg_mcr = flexcan_read(&regs->mcr);
d5a7b406 815 reg_mcr &= ~FLEXCAN_MCR_MAXMB(0xff);
e955cead
MKB		 816 reg_mcr |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_FEN | FLEXCAN_MCR_HALT |
817 FLEXCAN_MCR_SUPV | FLEXCAN_MCR_WRN_EN |
d5a7b406
MKB		 818 FLEXCAN_MCR_IDAM_C | FLEXCAN_MCR_SRX_DIS |
819 FLEXCAN_MCR_MAXMB(FLEXCAN_TX_BUF_ID);
aabdfd6a 820 netdev_dbg(dev, "%s: writing mcr=0x%08x", __func__, reg_mcr);
61e271ee 821 flexcan_write(reg_mcr, &regs->mcr);
e955cead
MKB		 822
823 /*
824 * CTRL
825 *
826 * disable timer sync feature
827 *
828 * disable auto busoff recovery
829 * transmit lowest buffer first
830 *
831 * enable tx and rx warning interrupt
832 * enable bus off interrupt
833 * (== FLEXCAN_CTRL_ERR_STATE)
e955cead 834 */
61e271ee 835 reg_ctrl = flexcan_read(&regs->ctrl);
e955cead
MKB		 836 reg_ctrl &= ~FLEXCAN_CTRL_TSYN;
837 reg_ctrl |= FLEXCAN_CTRL_BOFF_REC | FLEXCAN_CTRL_LBUF |
4f72e5f0
WG		 838 FLEXCAN_CTRL_ERR_STATE;
839 /*
840 * enable the "error interrupt" (FLEXCAN_CTRL_ERR_MSK),
841 * on most Flexcan cores, too. Otherwise we don't get
842 * any error warning or passive interrupts.
843 */
844 if (priv->devtype_data->features & FLEXCAN_HAS_BROKEN_ERR_STATE ||
845 priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)
846 reg_ctrl |= FLEXCAN_CTRL_ERR_MSK;
e955cead
MKB		 847
848 /* save for later use */
849 priv->reg_ctrl_default = reg_ctrl;
aabdfd6a 850 netdev_dbg(dev, "%s: writing ctrl=0x%08x", __func__, reg_ctrl);
61e271ee 851 flexcan_write(reg_ctrl, &regs->ctrl);
e955cead 852
d5a7b406
MKB		 853 /* Abort any pending TX, mark Mailbox as INACTIVE */
854 flexcan_write(FLEXCAN_MB_CNT_CODE(0x4),
855 &regs->cantxfg[FLEXCAN_TX_BUF_ID].can_ctrl);
856
e955cead 857 /* acceptance mask/acceptance code (accept everything) */
61e271ee 858 flexcan_write(0x0, &regs->rxgmask);
859 flexcan_write(0x0, &regs->rx14mask);
860 flexcan_write(0x0, &regs->rx15mask);
e955cead 861
4f72e5f0 862 if (priv->devtype_data->features & FLEXCAN_HAS_V10_FEATURES)
30c1e672
HW		 863 flexcan_write(0x0, &regs->rxfgmask);
864
f003698e
MKB		 865 err = flexcan_transceiver_enable(priv);
866 if (err)
b1aa1c7a 867 goto out_chip_disable;
e955cead
MKB		 868
869 /* synchronize with the can bus */
b1aa1c7a
MKB		 870 err = flexcan_chip_unfreeze(priv);
871 if (err)
872 goto out_transceiver_disable;
e955cead
MKB		 873
874 priv->can.state = CAN_STATE_ERROR_ACTIVE;
875
876 /* enable FIFO interrupts */
61e271ee 877 flexcan_write(FLEXCAN_IFLAG_DEFAULT, &regs->imask1);
e955cead
MKB		 878
879 /* print chip status */
aabdfd6a
WG		 880 netdev_dbg(dev, "%s: reading mcr=0x%08x ctrl=0x%08x\n", __func__,
881 flexcan_read(&regs->mcr), flexcan_read(&regs->ctrl));
e955cead
MKB		 882
883 return 0;
884
b1aa1c7a
MKB		 885 out_transceiver_disable:
886 flexcan_transceiver_disable(priv);
887 out_chip_disable:
e955cead
MKB		 888 flexcan_chip_disable(priv);
889 return err;
890}
891
892/*
893 * flexcan_chip_stop
894 *
895 * this functions is entered with clocks enabled
896 *
897 */
898static void flexcan_chip_stop(struct net_device *dev)
899{
900 struct flexcan_priv *priv = netdev_priv(dev);
901 struct flexcan_regs __iomem *regs = priv->base;
e955cead 902
b1aa1c7a
MKB		 903 /* freeze + disable module */
904 flexcan_chip_freeze(priv);
905 flexcan_chip_disable(priv);
e955cead 906
5be93bdd
MKB		 907 /* Disable all interrupts */
908 flexcan_write(0, &regs->imask1);
909 flexcan_write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
910 &regs->ctrl);
911
f003698e 912 flexcan_transceiver_disable(priv);
e955cead
MKB		 913 priv->can.state = CAN_STATE_STOPPED;
914
915 return;
916}
917
918static int flexcan_open(struct net_device *dev)
919{
920 struct flexcan_priv *priv = netdev_priv(dev);
921 int err;
922
aa10181b
FE		 923 err = clk_prepare_enable(priv->clk_ipg);
924 if (err)
925 return err;
926
927 err = clk_prepare_enable(priv->clk_per);
928 if (err)
929 goto out_disable_ipg;
e955cead
MKB		 930
931 err = open_candev(dev);
932 if (err)
aa10181b 933 goto out_disable_per;
e955cead
MKB		 934
935 err = request_irq(dev->irq, flexcan_irq, IRQF_SHARED, dev->name, dev);
936 if (err)
937 goto out_close;
938
939 /* start chip and queuing */
940 err = flexcan_chip_start(dev);
941 if (err)
7e9e148a 942 goto out_free_irq;
adccadb9
FB		 943
944 can_led_event(dev, CAN_LED_EVENT_OPEN);
945
e955cead
MKB		 946 napi_enable(&priv->napi);
947 netif_start_queue(dev);
948
949 return 0;
950
7e9e148a
MKB		 951 out_free_irq:
952 free_irq(dev->irq, dev);
e955cead
MKB		 953 out_close:
954 close_candev(dev);
aa10181b 955 out_disable_per:
3d42a379 956 clk_disable_unprepare(priv->clk_per);
aa10181b 957 out_disable_ipg:
3d42a379 958 clk_disable_unprepare(priv->clk_ipg);
e955cead
MKB		 959
960 return err;
961}
962
963static int flexcan_close(struct net_device *dev)
964{
965 struct flexcan_priv *priv = netdev_priv(dev);
966
967 netif_stop_queue(dev);
968 napi_disable(&priv->napi);
969 flexcan_chip_stop(dev);
970
971 free_irq(dev->irq, dev);
3d42a379
ST		 972 clk_disable_unprepare(priv->clk_per);
973 clk_disable_unprepare(priv->clk_ipg);
e955cead
MKB		 974
975 close_candev(dev);
976
adccadb9
FB		 977 can_led_event(dev, CAN_LED_EVENT_STOP);
978
e955cead
MKB		 979 return 0;
980}
981
982static int flexcan_set_mode(struct net_device *dev, enum can_mode mode)
983{
984 int err;
985
986 switch (mode) {
987 case CAN_MODE_START:
988 err = flexcan_chip_start(dev);
989 if (err)
990 return err;
991
992 netif_wake_queue(dev);
993 break;
994
995 default:
996 return -EOPNOTSUPP;
997 }
998
999 return 0;
1000}
1001
1002static const struct net_device_ops flexcan_netdev_ops = {
1003 .ndo_open = flexcan_open,
1004 .ndo_stop = flexcan_close,
1005 .ndo_start_xmit = flexcan_start_xmit,
1006};
1007
3c8ac0f2 1008static int register_flexcandev(struct net_device *dev)
e955cead
MKB		 1009{
1010 struct flexcan_priv *priv = netdev_priv(dev);
1011 struct flexcan_regs __iomem *regs = priv->base;
1012 u32 reg, err;
1013
aa10181b
FE		 1014 err = clk_prepare_enable(priv->clk_ipg);
1015 if (err)
1016 return err;
1017
1018 err = clk_prepare_enable(priv->clk_per);
1019 if (err)
1020 goto out_disable_ipg;
e955cead
MKB		 1021
1022 /* select "bus clock", chip must be disabled */
9b00b300
MKB		 1023 err = flexcan_chip_disable(priv);
1024 if (err)
1025 goto out_disable_per;
61e271ee 1026 reg = flexcan_read(&regs->ctrl);
e955cead 1027 reg |= FLEXCAN_CTRL_CLK_SRC;
61e271ee 1028 flexcan_write(reg, &regs->ctrl);
e955cead 1029
9b00b300
MKB		 1030 err = flexcan_chip_enable(priv);
1031 if (err)
1032 goto out_chip_disable;
e955cead
MKB		 1033
1034 /* set freeze, halt and activate FIFO, restrict register access */
61e271ee 1035 reg = flexcan_read(&regs->mcr);
e955cead
MKB		 1036 reg |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT |
1037 FLEXCAN_MCR_FEN | FLEXCAN_MCR_SUPV;
61e271ee 1038 flexcan_write(reg, &regs->mcr);
e955cead
MKB		 1039
1040 /*
1041 * Currently we only support newer versions of this core
1042 * featuring a RX FIFO. Older cores found on some Coldfire
1043 * derivates are not yet supported.
1044 */
61e271ee 1045 reg = flexcan_read(&regs->mcr);
e955cead 1046 if (!(reg & FLEXCAN_MCR_FEN)) {
aabdfd6a 1047 netdev_err(dev, "Could not enable RX FIFO, unsupported core\n");
e955cead 1048 err = -ENODEV;
9b00b300 1049 goto out_chip_disable;
e955cead
MKB		 1050 }
1051
1052 err = register_candev(dev);
1053
e955cead 1054 /* disable core and turn off clocks */
9b00b300 1055 out_chip_disable:
e955cead 1056 flexcan_chip_disable(priv);
9b00b300 1057 out_disable_per:
3d42a379 1058 clk_disable_unprepare(priv->clk_per);
aa10181b 1059 out_disable_ipg:
3d42a379 1060 clk_disable_unprepare(priv->clk_ipg);
e955cead
MKB		 1061
1062 return err;
1063}
1064
3c8ac0f2 1065static void unregister_flexcandev(struct net_device *dev)
e955cead
MKB		 1066{
1067 unregister_candev(dev);
1068}
1069
30c1e672 1070static const struct of_device_id flexcan_of_match[] = {
30c1e672 1071 { .compatible = "fsl,imx6q-flexcan", .data = &fsl_imx6q_devtype_data, },
e3587842
MKB		 1072 { .compatible = "fsl,imx28-flexcan", .data = &fsl_imx28_devtype_data, },
1073 { .compatible = "fsl,p1010-flexcan", .data = &fsl_p1010_devtype_data, },
30c1e672
HW		 1074 { /* sentinel */ },
1075};
4358a9dc 1076MODULE_DEVICE_TABLE(of, flexcan_of_match);
30c1e672
HW		 1077
1078static const struct platform_device_id flexcan_id_table[] = {
1079 { .name = "flexcan", .driver_data = (kernel_ulong_t)&fsl_p1010_devtype_data, },
1080 { /* sentinel */ },
1081};
4358a9dc 1082MODULE_DEVICE_TABLE(platform, flexcan_id_table);
30c1e672 1083
3c8ac0f2 1084static int flexcan_probe(struct platform_device *pdev)
e955cead 1085{
30c1e672 1086 const struct of_device_id *of_id;
dda0b3bd 1087 const struct flexcan_devtype_data *devtype_data;
e955cead
MKB		 1088 struct net_device *dev;
1089 struct flexcan_priv *priv;
1090 struct resource *mem;
3d42a379 1091 struct clk *clk_ipg = NULL, *clk_per = NULL;
e955cead 1092 void __iomem *base;
e955cead 1093 int err, irq;
97efe9ae 1094 u32 clock_freq = 0;
1095
afc016d8
HW		 1096 if (pdev->dev.of_node)
1097 of_property_read_u32(pdev->dev.of_node,
1098 "clock-frequency", &clock_freq);
97efe9ae 1099
1100 if (!clock_freq) {
3d42a379
ST		 1101 clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1102 if (IS_ERR(clk_ipg)) {
1103 dev_err(&pdev->dev, "no ipg clock defined\n");
933e4af4 1104 return PTR_ERR(clk_ipg);
3d42a379 1105 }
3d42a379
ST		 1106
1107 clk_per = devm_clk_get(&pdev->dev, "per");
1108 if (IS_ERR(clk_per)) {
1109 dev_err(&pdev->dev, "no per clock defined\n");
933e4af4 1110 return PTR_ERR(clk_per);
97efe9ae 1111 }
1a3e5173 1112 clock_freq = clk_get_rate(clk_per);
e955cead
MKB		 1113 }
1114
1115 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1116 irq = platform_get_irq(pdev, 0);
933e4af4
FE		 1117 if (irq <= 0)
1118 return -ENODEV;
e955cead 1119
933e4af4
FE		 1120 base = devm_ioremap_resource(&pdev->dev, mem);
1121 if (IS_ERR(base))
1122 return PTR_ERR(base);
e955cead 1123
30c1e672
HW		 1124 of_id = of_match_device(flexcan_of_match, &pdev->dev);
1125 if (of_id) {
1126 devtype_data = of_id->data;
1127 } else if (pdev->id_entry->driver_data) {
1128 devtype_data = (struct flexcan_devtype_data *)
1129 pdev->id_entry->driver_data;
1130 } else {
933e4af4 1131 return -ENODEV;
30c1e672
HW		 1132 }
1133
933e4af4
FE		 1134 dev = alloc_candev(sizeof(struct flexcan_priv), 1);
1135 if (!dev)
1136 return -ENOMEM;
1137
e955cead
MKB		 1138 dev->netdev_ops = &flexcan_netdev_ops;
1139 dev->irq = irq;
9a123496 1140 dev->flags |= IFF_ECHO;
e955cead
MKB		 1141
1142 priv = netdev_priv(dev);
97efe9ae 1143 priv->can.clock.freq = clock_freq;
e955cead
MKB		 1144 priv->can.bittiming_const = &flexcan_bittiming_const;
1145 priv->can.do_set_mode = flexcan_set_mode;
1146 priv->can.do_get_berr_counter = flexcan_get_berr_counter;
1147 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
1148 CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_3_SAMPLES |
1149 CAN_CTRLMODE_BERR_REPORTING;
1150 priv->base = base;
1151 priv->dev = dev;
3d42a379
ST		 1152 priv->clk_ipg = clk_ipg;
1153 priv->clk_per = clk_per;
84ae6643 1154 priv->pdata = dev_get_platdata(&pdev->dev);
30c1e672 1155 priv->devtype_data = devtype_data;
e955cead 1156
b7c4114b
FE		 1157 priv->reg_xceiver = devm_regulator_get(&pdev->dev, "xceiver");
1158 if (IS_ERR(priv->reg_xceiver))
1159 priv->reg_xceiver = NULL;
1160
e955cead
MKB		 1161 netif_napi_add(dev, &priv->napi, flexcan_poll, FLEXCAN_NAPI_WEIGHT);
1162
d75ea942 1163 platform_set_drvdata(pdev, dev);
e955cead
MKB		 1164 SET_NETDEV_DEV(dev, &pdev->dev);
1165
1166 err = register_flexcandev(dev);
1167 if (err) {
1168 dev_err(&pdev->dev, "registering netdev failed\n");
1169 goto failed_register;
1170 }
1171
adccadb9
FB		 1172 devm_can_led_init(dev);
1173
e955cead
MKB		 1174 dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%d)\n",
1175 priv->base, dev->irq);
1176
1177 return 0;
1178
1179 failed_register:
1180 free_candev(dev);
e955cead
MKB		 1181 return err;
1182}
1183
3c8ac0f2 1184static int flexcan_remove(struct platform_device *pdev)
e955cead
MKB		 1185{
1186 struct net_device *dev = platform_get_drvdata(pdev);
d96e43e8 1187 struct flexcan_priv *priv = netdev_priv(dev);
e955cead
MKB		 1188
1189 unregister_flexcandev(dev);
d96e43e8 1190 netif_napi_del(&priv->napi);
9a27586d
MKB		 1191 free_candev(dev);
1192
e955cead
MKB		 1193 return 0;
1194}
1195
588e7a8e
FE		 1196#ifdef CONFIG_PM_SLEEP
1197static int flexcan_suspend(struct device *device)
8b5e218d 1198{
588e7a8e 1199 struct net_device *dev = dev_get_drvdata(device);
8b5e218d 1200 struct flexcan_priv *priv = netdev_priv(dev);
9b00b300 1201 int err;
8b5e218d 1202
9b00b300
MKB		 1203 err = flexcan_chip_disable(priv);
1204 if (err)
1205 return err;
8b5e218d
EB		 1206
1207 if (netif_running(dev)) {
1208 netif_stop_queue(dev);
1209 netif_device_detach(dev);
1210 }
1211 priv->can.state = CAN_STATE_SLEEPING;
1212
1213 return 0;
1214}
1215
588e7a8e 1216static int flexcan_resume(struct device *device)
8b5e218d 1217{
588e7a8e 1218 struct net_device *dev = dev_get_drvdata(device);
8b5e218d
EB		 1219 struct flexcan_priv *priv = netdev_priv(dev);
1220
1221 priv->can.state = CAN_STATE_ERROR_ACTIVE;
1222 if (netif_running(dev)) {
1223 netif_device_attach(dev);
1224 netif_start_queue(dev);
1225 }
9b00b300 1226 return flexcan_chip_enable(priv);
8b5e218d 1227}
588e7a8e
FE		 1228#endif /* CONFIG_PM_SLEEP */
1229
1230static SIMPLE_DEV_PM_OPS(flexcan_pm_ops, flexcan_suspend, flexcan_resume);
8b5e218d 1231
e955cead 1232static struct platform_driver flexcan_driver = {
c8aef4cb 1233 .driver = {
1234 .name = DRV_NAME,
1235 .owner = THIS_MODULE,
588e7a8e 1236 .pm = &flexcan_pm_ops,
c8aef4cb 1237 .of_match_table = flexcan_of_match,
1238 },
e955cead 1239 .probe = flexcan_probe,
3c8ac0f2 1240 .remove = flexcan_remove,
30c1e672 1241 .id_table = flexcan_id_table,
e955cead
MKB		 1242};
1243
871d3372 1244module_platform_driver(flexcan_driver);
e955cead
MKB		 1245
1246MODULE_AUTHOR("Sascha Hauer <kernel@pengutronix.de>, "
1247 "Marc Kleine-Budde <kernel@pengutronix.de>");
1248MODULE_LICENSE("GPL v2");
1249MODULE_DESCRIPTION("CAN port driver for flexcan based chip");
Linux kernel - Deliverables
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