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e0000163 CP |
1 | /* |
2 | * CAN bus driver for Microchip 251x CAN Controller with SPI Interface | |
3 | * | |
4 | * MCP2510 support and bug fixes by Christian Pellegrin | |
5 | * <chripell@evolware.org> | |
6 | * | |
7 | * Copyright 2009 Christian Pellegrin EVOL S.r.l. | |
8 | * | |
9 | * Copyright 2007 Raymarine UK, Ltd. All Rights Reserved. | |
10 | * Written under contract by: | |
11 | * Chris Elston, Katalix Systems, Ltd. | |
12 | * | |
13 | * Based on Microchip MCP251x CAN controller driver written by | |
14 | * David Vrabel, Copyright 2006 Arcom Control Systems Ltd. | |
15 | * | |
16 | * Based on CAN bus driver for the CCAN controller written by | |
17 | * - Sascha Hauer, Marc Kleine-Budde, Pengutronix | |
18 | * - Simon Kallweit, intefo AG | |
19 | * Copyright 2007 | |
20 | * | |
21 | * This program is free software; you can redistribute it and/or modify | |
22 | * it under the terms of the version 2 of the GNU General Public License | |
23 | * as published by the Free Software Foundation | |
24 | * | |
25 | * This program is distributed in the hope that it will be useful, | |
26 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
27 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
28 | * GNU General Public License for more details. | |
29 | * | |
30 | * You should have received a copy of the GNU General Public License | |
31 | * along with this program; if not, write to the Free Software | |
32 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
33 | * | |
34 | * | |
35 | * | |
36 | * Your platform definition file should specify something like: | |
37 | * | |
38 | * static struct mcp251x_platform_data mcp251x_info = { | |
39 | * .oscillator_frequency = 8000000, | |
40 | * .board_specific_setup = &mcp251x_setup, | |
e0000163 CP |
41 | * .power_enable = mcp251x_power_enable, |
42 | * .transceiver_enable = NULL, | |
43 | * }; | |
44 | * | |
45 | * static struct spi_board_info spi_board_info[] = { | |
46 | * { | |
f1f8c6cb MKB |
47 | * .modalias = "mcp2510", |
48 | * // or "mcp2515" depending on your controller | |
e0000163 CP |
49 | * .platform_data = &mcp251x_info, |
50 | * .irq = IRQ_EINT13, | |
51 | * .max_speed_hz = 2*1000*1000, | |
52 | * .chip_select = 2, | |
53 | * }, | |
54 | * }; | |
55 | * | |
56 | * Please see mcp251x.h for a description of the fields in | |
57 | * struct mcp251x_platform_data. | |
58 | * | |
59 | */ | |
60 | ||
e0000163 CP |
61 | #include <linux/can/core.h> |
62 | #include <linux/can/dev.h> | |
63 | #include <linux/can/platform/mcp251x.h> | |
64 | #include <linux/completion.h> | |
65 | #include <linux/delay.h> | |
66 | #include <linux/device.h> | |
67 | #include <linux/dma-mapping.h> | |
68 | #include <linux/freezer.h> | |
69 | #include <linux/interrupt.h> | |
70 | #include <linux/io.h> | |
71 | #include <linux/kernel.h> | |
72 | #include <linux/module.h> | |
73 | #include <linux/netdevice.h> | |
74 | #include <linux/platform_device.h> | |
5a0e3ad6 | 75 | #include <linux/slab.h> |
e0000163 CP |
76 | #include <linux/spi/spi.h> |
77 | #include <linux/uaccess.h> | |
78 | ||
79 | /* SPI interface instruction set */ | |
80 | #define INSTRUCTION_WRITE 0x02 | |
81 | #define INSTRUCTION_READ 0x03 | |
82 | #define INSTRUCTION_BIT_MODIFY 0x05 | |
83 | #define INSTRUCTION_LOAD_TXB(n) (0x40 + 2 * (n)) | |
84 | #define INSTRUCTION_READ_RXB(n) (((n) == 0) ? 0x90 : 0x94) | |
85 | #define INSTRUCTION_RESET 0xC0 | |
cab32f39 BL |
86 | #define RTS_TXB0 0x01 |
87 | #define RTS_TXB1 0x02 | |
88 | #define RTS_TXB2 0x04 | |
89 | #define INSTRUCTION_RTS(n) (0x80 | ((n) & 0x07)) | |
90 | ||
e0000163 CP |
91 | |
92 | /* MPC251x registers */ | |
93 | #define CANSTAT 0x0e | |
94 | #define CANCTRL 0x0f | |
95 | # define CANCTRL_REQOP_MASK 0xe0 | |
96 | # define CANCTRL_REQOP_CONF 0x80 | |
97 | # define CANCTRL_REQOP_LISTEN_ONLY 0x60 | |
98 | # define CANCTRL_REQOP_LOOPBACK 0x40 | |
99 | # define CANCTRL_REQOP_SLEEP 0x20 | |
100 | # define CANCTRL_REQOP_NORMAL 0x00 | |
101 | # define CANCTRL_OSM 0x08 | |
102 | # define CANCTRL_ABAT 0x10 | |
103 | #define TEC 0x1c | |
104 | #define REC 0x1d | |
105 | #define CNF1 0x2a | |
106 | # define CNF1_SJW_SHIFT 6 | |
107 | #define CNF2 0x29 | |
108 | # define CNF2_BTLMODE 0x80 | |
109 | # define CNF2_SAM 0x40 | |
110 | # define CNF2_PS1_SHIFT 3 | |
111 | #define CNF3 0x28 | |
112 | # define CNF3_SOF 0x08 | |
113 | # define CNF3_WAKFIL 0x04 | |
114 | # define CNF3_PHSEG2_MASK 0x07 | |
115 | #define CANINTE 0x2b | |
116 | # define CANINTE_MERRE 0x80 | |
117 | # define CANINTE_WAKIE 0x40 | |
118 | # define CANINTE_ERRIE 0x20 | |
119 | # define CANINTE_TX2IE 0x10 | |
120 | # define CANINTE_TX1IE 0x08 | |
121 | # define CANINTE_TX0IE 0x04 | |
122 | # define CANINTE_RX1IE 0x02 | |
123 | # define CANINTE_RX0IE 0x01 | |
124 | #define CANINTF 0x2c | |
125 | # define CANINTF_MERRF 0x80 | |
126 | # define CANINTF_WAKIF 0x40 | |
127 | # define CANINTF_ERRIF 0x20 | |
128 | # define CANINTF_TX2IF 0x10 | |
129 | # define CANINTF_TX1IF 0x08 | |
130 | # define CANINTF_TX0IF 0x04 | |
131 | # define CANINTF_RX1IF 0x02 | |
132 | # define CANINTF_RX0IF 0x01 | |
5601b2df MKB |
133 | # define CANINTF_RX (CANINTF_RX0IF | CANINTF_RX1IF) |
134 | # define CANINTF_TX (CANINTF_TX2IF | CANINTF_TX1IF | CANINTF_TX0IF) | |
135 | # define CANINTF_ERR (CANINTF_ERRIF) | |
e0000163 CP |
136 | #define EFLG 0x2d |
137 | # define EFLG_EWARN 0x01 | |
138 | # define EFLG_RXWAR 0x02 | |
139 | # define EFLG_TXWAR 0x04 | |
140 | # define EFLG_RXEP 0x08 | |
141 | # define EFLG_TXEP 0x10 | |
142 | # define EFLG_TXBO 0x20 | |
143 | # define EFLG_RX0OVR 0x40 | |
144 | # define EFLG_RX1OVR 0x80 | |
145 | #define TXBCTRL(n) (((n) * 0x10) + 0x30 + TXBCTRL_OFF) | |
146 | # define TXBCTRL_ABTF 0x40 | |
147 | # define TXBCTRL_MLOA 0x20 | |
148 | # define TXBCTRL_TXERR 0x10 | |
149 | # define TXBCTRL_TXREQ 0x08 | |
150 | #define TXBSIDH(n) (((n) * 0x10) + 0x30 + TXBSIDH_OFF) | |
151 | # define SIDH_SHIFT 3 | |
152 | #define TXBSIDL(n) (((n) * 0x10) + 0x30 + TXBSIDL_OFF) | |
153 | # define SIDL_SID_MASK 7 | |
154 | # define SIDL_SID_SHIFT 5 | |
155 | # define SIDL_EXIDE_SHIFT 3 | |
156 | # define SIDL_EID_SHIFT 16 | |
157 | # define SIDL_EID_MASK 3 | |
158 | #define TXBEID8(n) (((n) * 0x10) + 0x30 + TXBEID8_OFF) | |
159 | #define TXBEID0(n) (((n) * 0x10) + 0x30 + TXBEID0_OFF) | |
160 | #define TXBDLC(n) (((n) * 0x10) + 0x30 + TXBDLC_OFF) | |
161 | # define DLC_RTR_SHIFT 6 | |
162 | #define TXBCTRL_OFF 0 | |
163 | #define TXBSIDH_OFF 1 | |
164 | #define TXBSIDL_OFF 2 | |
165 | #define TXBEID8_OFF 3 | |
166 | #define TXBEID0_OFF 4 | |
167 | #define TXBDLC_OFF 5 | |
168 | #define TXBDAT_OFF 6 | |
169 | #define RXBCTRL(n) (((n) * 0x10) + 0x60 + RXBCTRL_OFF) | |
170 | # define RXBCTRL_BUKT 0x04 | |
171 | # define RXBCTRL_RXM0 0x20 | |
172 | # define RXBCTRL_RXM1 0x40 | |
173 | #define RXBSIDH(n) (((n) * 0x10) + 0x60 + RXBSIDH_OFF) | |
174 | # define RXBSIDH_SHIFT 3 | |
175 | #define RXBSIDL(n) (((n) * 0x10) + 0x60 + RXBSIDL_OFF) | |
176 | # define RXBSIDL_IDE 0x08 | |
b9958a95 | 177 | # define RXBSIDL_SRR 0x10 |
e0000163 CP |
178 | # define RXBSIDL_EID 3 |
179 | # define RXBSIDL_SHIFT 5 | |
180 | #define RXBEID8(n) (((n) * 0x10) + 0x60 + RXBEID8_OFF) | |
181 | #define RXBEID0(n) (((n) * 0x10) + 0x60 + RXBEID0_OFF) | |
182 | #define RXBDLC(n) (((n) * 0x10) + 0x60 + RXBDLC_OFF) | |
183 | # define RXBDLC_LEN_MASK 0x0f | |
184 | # define RXBDLC_RTR 0x40 | |
185 | #define RXBCTRL_OFF 0 | |
186 | #define RXBSIDH_OFF 1 | |
187 | #define RXBSIDL_OFF 2 | |
188 | #define RXBEID8_OFF 3 | |
189 | #define RXBEID0_OFF 4 | |
190 | #define RXBDLC_OFF 5 | |
191 | #define RXBDAT_OFF 6 | |
bf66f373 CP |
192 | #define RXFSIDH(n) ((n) * 4) |
193 | #define RXFSIDL(n) ((n) * 4 + 1) | |
194 | #define RXFEID8(n) ((n) * 4 + 2) | |
195 | #define RXFEID0(n) ((n) * 4 + 3) | |
196 | #define RXMSIDH(n) ((n) * 4 + 0x20) | |
197 | #define RXMSIDL(n) ((n) * 4 + 0x21) | |
198 | #define RXMEID8(n) ((n) * 4 + 0x22) | |
199 | #define RXMEID0(n) ((n) * 4 + 0x23) | |
e0000163 CP |
200 | |
201 | #define GET_BYTE(val, byte) \ | |
202 | (((val) >> ((byte) * 8)) & 0xff) | |
203 | #define SET_BYTE(val, byte) \ | |
204 | (((val) & 0xff) << ((byte) * 8)) | |
205 | ||
206 | /* | |
207 | * Buffer size required for the largest SPI transfer (i.e., reading a | |
208 | * frame) | |
209 | */ | |
210 | #define CAN_FRAME_MAX_DATA_LEN 8 | |
211 | #define SPI_TRANSFER_BUF_LEN (6 + CAN_FRAME_MAX_DATA_LEN) | |
212 | #define CAN_FRAME_MAX_BITS 128 | |
213 | ||
214 | #define TX_ECHO_SKB_MAX 1 | |
215 | ||
216 | #define DEVICE_NAME "mcp251x" | |
217 | ||
218 | static int mcp251x_enable_dma; /* Enable SPI DMA. Default: 0 (Off) */ | |
219 | module_param(mcp251x_enable_dma, int, S_IRUGO); | |
220 | MODULE_PARM_DESC(mcp251x_enable_dma, "Enable SPI DMA. Default: 0 (Off)"); | |
221 | ||
194b9a4c | 222 | static const struct can_bittiming_const mcp251x_bittiming_const = { |
e0000163 CP |
223 | .name = DEVICE_NAME, |
224 | .tseg1_min = 3, | |
225 | .tseg1_max = 16, | |
226 | .tseg2_min = 2, | |
227 | .tseg2_max = 8, | |
228 | .sjw_max = 4, | |
229 | .brp_min = 1, | |
230 | .brp_max = 64, | |
231 | .brp_inc = 1, | |
232 | }; | |
233 | ||
f1f8c6cb MKB |
234 | enum mcp251x_model { |
235 | CAN_MCP251X_MCP2510 = 0x2510, | |
236 | CAN_MCP251X_MCP2515 = 0x2515, | |
237 | }; | |
238 | ||
e0000163 CP |
239 | struct mcp251x_priv { |
240 | struct can_priv can; | |
241 | struct net_device *net; | |
242 | struct spi_device *spi; | |
f1f8c6cb | 243 | enum mcp251x_model model; |
e0000163 | 244 | |
bf66f373 CP |
245 | struct mutex mcp_lock; /* SPI device lock */ |
246 | ||
e0000163 CP |
247 | u8 *spi_tx_buf; |
248 | u8 *spi_rx_buf; | |
249 | dma_addr_t spi_tx_dma; | |
250 | dma_addr_t spi_rx_dma; | |
251 | ||
252 | struct sk_buff *tx_skb; | |
253 | int tx_len; | |
bf66f373 | 254 | |
e0000163 CP |
255 | struct workqueue_struct *wq; |
256 | struct work_struct tx_work; | |
bf66f373 CP |
257 | struct work_struct restart_work; |
258 | ||
e0000163 CP |
259 | int force_quit; |
260 | int after_suspend; | |
261 | #define AFTER_SUSPEND_UP 1 | |
262 | #define AFTER_SUSPEND_DOWN 2 | |
263 | #define AFTER_SUSPEND_POWER 4 | |
264 | #define AFTER_SUSPEND_RESTART 8 | |
265 | int restart_tx; | |
266 | }; | |
267 | ||
beab675c MKB |
268 | #define MCP251X_IS(_model) \ |
269 | static inline int mcp251x_is_##_model(struct spi_device *spi) \ | |
270 | { \ | |
271 | struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev); \ | |
272 | return priv->model == CAN_MCP251X_MCP##_model; \ | |
273 | } | |
274 | ||
275 | MCP251X_IS(2510); | |
276 | MCP251X_IS(2515); | |
277 | ||
e0000163 CP |
278 | static void mcp251x_clean(struct net_device *net) |
279 | { | |
280 | struct mcp251x_priv *priv = netdev_priv(net); | |
281 | ||
bf66f373 CP |
282 | if (priv->tx_skb || priv->tx_len) |
283 | net->stats.tx_errors++; | |
e0000163 CP |
284 | if (priv->tx_skb) |
285 | dev_kfree_skb(priv->tx_skb); | |
286 | if (priv->tx_len) | |
287 | can_free_echo_skb(priv->net, 0); | |
288 | priv->tx_skb = NULL; | |
289 | priv->tx_len = 0; | |
290 | } | |
291 | ||
292 | /* | |
293 | * Note about handling of error return of mcp251x_spi_trans: accessing | |
294 | * registers via SPI is not really different conceptually than using | |
295 | * normal I/O assembler instructions, although it's much more | |
296 | * complicated from a practical POV. So it's not advisable to always | |
297 | * check the return value of this function. Imagine that every | |
298 | * read{b,l}, write{b,l} and friends would be bracketed in "if ( < 0) | |
299 | * error();", it would be a great mess (well there are some situation | |
300 | * when exception handling C++ like could be useful after all). So we | |
301 | * just check that transfers are OK at the beginning of our | |
302 | * conversation with the chip and to avoid doing really nasty things | |
303 | * (like injecting bogus packets in the network stack). | |
304 | */ | |
305 | static int mcp251x_spi_trans(struct spi_device *spi, int len) | |
306 | { | |
307 | struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev); | |
308 | struct spi_transfer t = { | |
309 | .tx_buf = priv->spi_tx_buf, | |
310 | .rx_buf = priv->spi_rx_buf, | |
311 | .len = len, | |
312 | .cs_change = 0, | |
313 | }; | |
314 | struct spi_message m; | |
315 | int ret; | |
316 | ||
317 | spi_message_init(&m); | |
318 | ||
319 | if (mcp251x_enable_dma) { | |
320 | t.tx_dma = priv->spi_tx_dma; | |
321 | t.rx_dma = priv->spi_rx_dma; | |
322 | m.is_dma_mapped = 1; | |
323 | } | |
324 | ||
325 | spi_message_add_tail(&t, &m); | |
326 | ||
327 | ret = spi_sync(spi, &m); | |
328 | if (ret) | |
329 | dev_err(&spi->dev, "spi transfer failed: ret = %d\n", ret); | |
330 | return ret; | |
331 | } | |
332 | ||
333 | static u8 mcp251x_read_reg(struct spi_device *spi, uint8_t reg) | |
334 | { | |
335 | struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev); | |
336 | u8 val = 0; | |
337 | ||
e0000163 CP |
338 | priv->spi_tx_buf[0] = INSTRUCTION_READ; |
339 | priv->spi_tx_buf[1] = reg; | |
340 | ||
341 | mcp251x_spi_trans(spi, 3); | |
342 | val = priv->spi_rx_buf[2]; | |
343 | ||
e0000163 CP |
344 | return val; |
345 | } | |
346 | ||
f3a3ed31 SH |
347 | static void mcp251x_read_2regs(struct spi_device *spi, uint8_t reg, |
348 | uint8_t *v1, uint8_t *v2) | |
349 | { | |
350 | struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev); | |
351 | ||
352 | priv->spi_tx_buf[0] = INSTRUCTION_READ; | |
353 | priv->spi_tx_buf[1] = reg; | |
354 | ||
355 | mcp251x_spi_trans(spi, 4); | |
356 | ||
357 | *v1 = priv->spi_rx_buf[2]; | |
358 | *v2 = priv->spi_rx_buf[3]; | |
359 | } | |
360 | ||
e0000163 CP |
361 | static void mcp251x_write_reg(struct spi_device *spi, u8 reg, uint8_t val) |
362 | { | |
363 | struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev); | |
364 | ||
e0000163 CP |
365 | priv->spi_tx_buf[0] = INSTRUCTION_WRITE; |
366 | priv->spi_tx_buf[1] = reg; | |
367 | priv->spi_tx_buf[2] = val; | |
368 | ||
369 | mcp251x_spi_trans(spi, 3); | |
e0000163 CP |
370 | } |
371 | ||
372 | static void mcp251x_write_bits(struct spi_device *spi, u8 reg, | |
373 | u8 mask, uint8_t val) | |
374 | { | |
375 | struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev); | |
376 | ||
e0000163 CP |
377 | priv->spi_tx_buf[0] = INSTRUCTION_BIT_MODIFY; |
378 | priv->spi_tx_buf[1] = reg; | |
379 | priv->spi_tx_buf[2] = mask; | |
380 | priv->spi_tx_buf[3] = val; | |
381 | ||
382 | mcp251x_spi_trans(spi, 4); | |
e0000163 CP |
383 | } |
384 | ||
385 | static void mcp251x_hw_tx_frame(struct spi_device *spi, u8 *buf, | |
386 | int len, int tx_buf_idx) | |
387 | { | |
e0000163 CP |
388 | struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev); |
389 | ||
beab675c | 390 | if (mcp251x_is_2510(spi)) { |
e0000163 CP |
391 | int i; |
392 | ||
393 | for (i = 1; i < TXBDAT_OFF + len; i++) | |
394 | mcp251x_write_reg(spi, TXBCTRL(tx_buf_idx) + i, | |
395 | buf[i]); | |
396 | } else { | |
e0000163 CP |
397 | memcpy(priv->spi_tx_buf, buf, TXBDAT_OFF + len); |
398 | mcp251x_spi_trans(spi, TXBDAT_OFF + len); | |
e0000163 CP |
399 | } |
400 | } | |
401 | ||
402 | static void mcp251x_hw_tx(struct spi_device *spi, struct can_frame *frame, | |
403 | int tx_buf_idx) | |
404 | { | |
cab32f39 | 405 | struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev); |
e0000163 CP |
406 | u32 sid, eid, exide, rtr; |
407 | u8 buf[SPI_TRANSFER_BUF_LEN]; | |
408 | ||
409 | exide = (frame->can_id & CAN_EFF_FLAG) ? 1 : 0; /* Extended ID Enable */ | |
410 | if (exide) | |
411 | sid = (frame->can_id & CAN_EFF_MASK) >> 18; | |
412 | else | |
413 | sid = frame->can_id & CAN_SFF_MASK; /* Standard ID */ | |
414 | eid = frame->can_id & CAN_EFF_MASK; /* Extended ID */ | |
415 | rtr = (frame->can_id & CAN_RTR_FLAG) ? 1 : 0; /* Remote transmission */ | |
416 | ||
417 | buf[TXBCTRL_OFF] = INSTRUCTION_LOAD_TXB(tx_buf_idx); | |
418 | buf[TXBSIDH_OFF] = sid >> SIDH_SHIFT; | |
419 | buf[TXBSIDL_OFF] = ((sid & SIDL_SID_MASK) << SIDL_SID_SHIFT) | | |
420 | (exide << SIDL_EXIDE_SHIFT) | | |
421 | ((eid >> SIDL_EID_SHIFT) & SIDL_EID_MASK); | |
422 | buf[TXBEID8_OFF] = GET_BYTE(eid, 1); | |
423 | buf[TXBEID0_OFF] = GET_BYTE(eid, 0); | |
424 | buf[TXBDLC_OFF] = (rtr << DLC_RTR_SHIFT) | frame->can_dlc; | |
425 | memcpy(buf + TXBDAT_OFF, frame->data, frame->can_dlc); | |
426 | mcp251x_hw_tx_frame(spi, buf, frame->can_dlc, tx_buf_idx); | |
cab32f39 BL |
427 | |
428 | /* use INSTRUCTION_RTS, to avoid "repeated frame problem" */ | |
429 | priv->spi_tx_buf[0] = INSTRUCTION_RTS(1 << tx_buf_idx); | |
430 | mcp251x_spi_trans(priv->spi, 1); | |
e0000163 CP |
431 | } |
432 | ||
433 | static void mcp251x_hw_rx_frame(struct spi_device *spi, u8 *buf, | |
434 | int buf_idx) | |
435 | { | |
436 | struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev); | |
e0000163 | 437 | |
beab675c | 438 | if (mcp251x_is_2510(spi)) { |
e0000163 CP |
439 | int i, len; |
440 | ||
441 | for (i = 1; i < RXBDAT_OFF; i++) | |
442 | buf[i] = mcp251x_read_reg(spi, RXBCTRL(buf_idx) + i); | |
c7cd606f OH |
443 | |
444 | len = get_can_dlc(buf[RXBDLC_OFF] & RXBDLC_LEN_MASK); | |
e0000163 CP |
445 | for (; i < (RXBDAT_OFF + len); i++) |
446 | buf[i] = mcp251x_read_reg(spi, RXBCTRL(buf_idx) + i); | |
447 | } else { | |
e0000163 CP |
448 | priv->spi_tx_buf[RXBCTRL_OFF] = INSTRUCTION_READ_RXB(buf_idx); |
449 | mcp251x_spi_trans(spi, SPI_TRANSFER_BUF_LEN); | |
450 | memcpy(buf, priv->spi_rx_buf, SPI_TRANSFER_BUF_LEN); | |
e0000163 CP |
451 | } |
452 | } | |
453 | ||
454 | static void mcp251x_hw_rx(struct spi_device *spi, int buf_idx) | |
455 | { | |
456 | struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev); | |
457 | struct sk_buff *skb; | |
458 | struct can_frame *frame; | |
459 | u8 buf[SPI_TRANSFER_BUF_LEN]; | |
460 | ||
461 | skb = alloc_can_skb(priv->net, &frame); | |
462 | if (!skb) { | |
463 | dev_err(&spi->dev, "cannot allocate RX skb\n"); | |
464 | priv->net->stats.rx_dropped++; | |
465 | return; | |
466 | } | |
467 | ||
468 | mcp251x_hw_rx_frame(spi, buf, buf_idx); | |
469 | if (buf[RXBSIDL_OFF] & RXBSIDL_IDE) { | |
470 | /* Extended ID format */ | |
471 | frame->can_id = CAN_EFF_FLAG; | |
472 | frame->can_id |= | |
473 | /* Extended ID part */ | |
474 | SET_BYTE(buf[RXBSIDL_OFF] & RXBSIDL_EID, 2) | | |
475 | SET_BYTE(buf[RXBEID8_OFF], 1) | | |
476 | SET_BYTE(buf[RXBEID0_OFF], 0) | | |
477 | /* Standard ID part */ | |
478 | (((buf[RXBSIDH_OFF] << RXBSIDH_SHIFT) | | |
479 | (buf[RXBSIDL_OFF] >> RXBSIDL_SHIFT)) << 18); | |
480 | /* Remote transmission request */ | |
481 | if (buf[RXBDLC_OFF] & RXBDLC_RTR) | |
482 | frame->can_id |= CAN_RTR_FLAG; | |
483 | } else { | |
484 | /* Standard ID format */ | |
485 | frame->can_id = | |
486 | (buf[RXBSIDH_OFF] << RXBSIDH_SHIFT) | | |
487 | (buf[RXBSIDL_OFF] >> RXBSIDL_SHIFT); | |
b9958a95 MKB |
488 | if (buf[RXBSIDL_OFF] & RXBSIDL_SRR) |
489 | frame->can_id |= CAN_RTR_FLAG; | |
e0000163 CP |
490 | } |
491 | /* Data length */ | |
c7cd606f | 492 | frame->can_dlc = get_can_dlc(buf[RXBDLC_OFF] & RXBDLC_LEN_MASK); |
e0000163 CP |
493 | memcpy(frame->data, buf + RXBDAT_OFF, frame->can_dlc); |
494 | ||
495 | priv->net->stats.rx_packets++; | |
496 | priv->net->stats.rx_bytes += frame->can_dlc; | |
57d3c7b0 | 497 | netif_rx_ni(skb); |
e0000163 CP |
498 | } |
499 | ||
500 | static void mcp251x_hw_sleep(struct spi_device *spi) | |
501 | { | |
502 | mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_SLEEP); | |
503 | } | |
504 | ||
e0000163 CP |
505 | static netdev_tx_t mcp251x_hard_start_xmit(struct sk_buff *skb, |
506 | struct net_device *net) | |
507 | { | |
508 | struct mcp251x_priv *priv = netdev_priv(net); | |
509 | struct spi_device *spi = priv->spi; | |
510 | ||
511 | if (priv->tx_skb || priv->tx_len) { | |
512 | dev_warn(&spi->dev, "hard_xmit called while tx busy\n"); | |
e0000163 CP |
513 | return NETDEV_TX_BUSY; |
514 | } | |
515 | ||
3ccd4c61 | 516 | if (can_dropped_invalid_skb(net, skb)) |
e0000163 | 517 | return NETDEV_TX_OK; |
e0000163 CP |
518 | |
519 | netif_stop_queue(net); | |
520 | priv->tx_skb = skb; | |
e0000163 CP |
521 | queue_work(priv->wq, &priv->tx_work); |
522 | ||
523 | return NETDEV_TX_OK; | |
524 | } | |
525 | ||
526 | static int mcp251x_do_set_mode(struct net_device *net, enum can_mode mode) | |
527 | { | |
528 | struct mcp251x_priv *priv = netdev_priv(net); | |
529 | ||
530 | switch (mode) { | |
531 | case CAN_MODE_START: | |
bf66f373 | 532 | mcp251x_clean(net); |
e0000163 CP |
533 | /* We have to delay work since SPI I/O may sleep */ |
534 | priv->can.state = CAN_STATE_ERROR_ACTIVE; | |
535 | priv->restart_tx = 1; | |
536 | if (priv->can.restart_ms == 0) | |
537 | priv->after_suspend = AFTER_SUSPEND_RESTART; | |
bf66f373 | 538 | queue_work(priv->wq, &priv->restart_work); |
e0000163 CP |
539 | break; |
540 | default: | |
541 | return -EOPNOTSUPP; | |
542 | } | |
543 | ||
544 | return 0; | |
545 | } | |
546 | ||
bf66f373 | 547 | static int mcp251x_set_normal_mode(struct spi_device *spi) |
e0000163 CP |
548 | { |
549 | struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev); | |
550 | unsigned long timeout; | |
551 | ||
552 | /* Enable interrupts */ | |
553 | mcp251x_write_reg(spi, CANINTE, | |
554 | CANINTE_ERRIE | CANINTE_TX2IE | CANINTE_TX1IE | | |
bf66f373 | 555 | CANINTE_TX0IE | CANINTE_RX1IE | CANINTE_RX0IE); |
e0000163 CP |
556 | |
557 | if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) { | |
558 | /* Put device into loopback mode */ | |
559 | mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_LOOPBACK); | |
ad72c347 CP |
560 | } else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) { |
561 | /* Put device into listen-only mode */ | |
562 | mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_LISTEN_ONLY); | |
e0000163 CP |
563 | } else { |
564 | /* Put device into normal mode */ | |
bf66f373 | 565 | mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_NORMAL); |
e0000163 CP |
566 | |
567 | /* Wait for the device to enter normal mode */ | |
568 | timeout = jiffies + HZ; | |
569 | while (mcp251x_read_reg(spi, CANSTAT) & CANCTRL_REQOP_MASK) { | |
570 | schedule(); | |
571 | if (time_after(jiffies, timeout)) { | |
572 | dev_err(&spi->dev, "MCP251x didn't" | |
573 | " enter in normal mode\n"); | |
bf66f373 | 574 | return -EBUSY; |
e0000163 CP |
575 | } |
576 | } | |
577 | } | |
578 | priv->can.state = CAN_STATE_ERROR_ACTIVE; | |
bf66f373 | 579 | return 0; |
e0000163 CP |
580 | } |
581 | ||
582 | static int mcp251x_do_set_bittiming(struct net_device *net) | |
583 | { | |
584 | struct mcp251x_priv *priv = netdev_priv(net); | |
585 | struct can_bittiming *bt = &priv->can.bittiming; | |
586 | struct spi_device *spi = priv->spi; | |
587 | ||
588 | mcp251x_write_reg(spi, CNF1, ((bt->sjw - 1) << CNF1_SJW_SHIFT) | | |
589 | (bt->brp - 1)); | |
590 | mcp251x_write_reg(spi, CNF2, CNF2_BTLMODE | | |
591 | (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES ? | |
592 | CNF2_SAM : 0) | | |
593 | ((bt->phase_seg1 - 1) << CNF2_PS1_SHIFT) | | |
594 | (bt->prop_seg - 1)); | |
595 | mcp251x_write_bits(spi, CNF3, CNF3_PHSEG2_MASK, | |
596 | (bt->phase_seg2 - 1)); | |
597 | dev_info(&spi->dev, "CNF: 0x%02x 0x%02x 0x%02x\n", | |
598 | mcp251x_read_reg(spi, CNF1), | |
599 | mcp251x_read_reg(spi, CNF2), | |
600 | mcp251x_read_reg(spi, CNF3)); | |
601 | ||
602 | return 0; | |
603 | } | |
604 | ||
605 | static int mcp251x_setup(struct net_device *net, struct mcp251x_priv *priv, | |
606 | struct spi_device *spi) | |
607 | { | |
615534bc | 608 | mcp251x_do_set_bittiming(net); |
e0000163 | 609 | |
bf66f373 CP |
610 | mcp251x_write_reg(spi, RXBCTRL(0), |
611 | RXBCTRL_BUKT | RXBCTRL_RXM0 | RXBCTRL_RXM1); | |
612 | mcp251x_write_reg(spi, RXBCTRL(1), | |
613 | RXBCTRL_RXM0 | RXBCTRL_RXM1); | |
e0000163 CP |
614 | return 0; |
615 | } | |
616 | ||
bf66f373 | 617 | static int mcp251x_hw_reset(struct spi_device *spi) |
e0000163 CP |
618 | { |
619 | struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev); | |
620 | int ret; | |
bf66f373 | 621 | unsigned long timeout; |
e0000163 CP |
622 | |
623 | priv->spi_tx_buf[0] = INSTRUCTION_RESET; | |
e0000163 | 624 | ret = spi_write(spi, priv->spi_tx_buf, 1); |
bf66f373 | 625 | if (ret) { |
e0000163 | 626 | dev_err(&spi->dev, "reset failed: ret = %d\n", ret); |
bf66f373 CP |
627 | return -EIO; |
628 | } | |
629 | ||
e0000163 | 630 | /* Wait for reset to finish */ |
bf66f373 | 631 | timeout = jiffies + HZ; |
e0000163 | 632 | mdelay(10); |
bf66f373 CP |
633 | while ((mcp251x_read_reg(spi, CANSTAT) & CANCTRL_REQOP_MASK) |
634 | != CANCTRL_REQOP_CONF) { | |
635 | schedule(); | |
636 | if (time_after(jiffies, timeout)) { | |
637 | dev_err(&spi->dev, "MCP251x didn't" | |
638 | " enter in conf mode after reset\n"); | |
639 | return -EBUSY; | |
640 | } | |
641 | } | |
642 | return 0; | |
e0000163 CP |
643 | } |
644 | ||
645 | static int mcp251x_hw_probe(struct spi_device *spi) | |
646 | { | |
647 | int st1, st2; | |
648 | ||
649 | mcp251x_hw_reset(spi); | |
650 | ||
651 | /* | |
652 | * Please note that these are "magic values" based on after | |
653 | * reset defaults taken from data sheet which allows us to see | |
654 | * if we really have a chip on the bus (we avoid common all | |
655 | * zeroes or all ones situations) | |
656 | */ | |
657 | st1 = mcp251x_read_reg(spi, CANSTAT) & 0xEE; | |
658 | st2 = mcp251x_read_reg(spi, CANCTRL) & 0x17; | |
659 | ||
660 | dev_dbg(&spi->dev, "CANSTAT 0x%02x CANCTRL 0x%02x\n", st1, st2); | |
661 | ||
662 | /* Check for power up default values */ | |
663 | return (st1 == 0x80 && st2 == 0x07) ? 1 : 0; | |
664 | } | |
665 | ||
bf66f373 | 666 | static void mcp251x_open_clean(struct net_device *net) |
e0000163 CP |
667 | { |
668 | struct mcp251x_priv *priv = netdev_priv(net); | |
669 | struct spi_device *spi = priv->spi; | |
670 | struct mcp251x_platform_data *pdata = spi->dev.platform_data; | |
615534bc | 671 | |
bf66f373 CP |
672 | free_irq(spi->irq, priv); |
673 | mcp251x_hw_sleep(spi); | |
e0000163 | 674 | if (pdata->transceiver_enable) |
bf66f373 CP |
675 | pdata->transceiver_enable(0); |
676 | close_candev(net); | |
e0000163 CP |
677 | } |
678 | ||
679 | static int mcp251x_stop(struct net_device *net) | |
680 | { | |
681 | struct mcp251x_priv *priv = netdev_priv(net); | |
682 | struct spi_device *spi = priv->spi; | |
683 | struct mcp251x_platform_data *pdata = spi->dev.platform_data; | |
684 | ||
685 | close_candev(net); | |
686 | ||
bf66f373 CP |
687 | priv->force_quit = 1; |
688 | free_irq(spi->irq, priv); | |
689 | destroy_workqueue(priv->wq); | |
690 | priv->wq = NULL; | |
691 | ||
692 | mutex_lock(&priv->mcp_lock); | |
693 | ||
e0000163 CP |
694 | /* Disable and clear pending interrupts */ |
695 | mcp251x_write_reg(spi, CANINTE, 0x00); | |
696 | mcp251x_write_reg(spi, CANINTF, 0x00); | |
697 | ||
e0000163 | 698 | mcp251x_write_reg(spi, TXBCTRL(0), 0); |
bf66f373 | 699 | mcp251x_clean(net); |
e0000163 CP |
700 | |
701 | mcp251x_hw_sleep(spi); | |
702 | ||
703 | if (pdata->transceiver_enable) | |
704 | pdata->transceiver_enable(0); | |
705 | ||
706 | priv->can.state = CAN_STATE_STOPPED; | |
707 | ||
bf66f373 CP |
708 | mutex_unlock(&priv->mcp_lock); |
709 | ||
e0000163 CP |
710 | return 0; |
711 | } | |
712 | ||
bf66f373 CP |
713 | static void mcp251x_error_skb(struct net_device *net, int can_id, int data1) |
714 | { | |
715 | struct sk_buff *skb; | |
716 | struct can_frame *frame; | |
717 | ||
718 | skb = alloc_can_err_skb(net, &frame); | |
719 | if (skb) { | |
612eef4f | 720 | frame->can_id |= can_id; |
bf66f373 | 721 | frame->data[1] = data1; |
57d3c7b0 | 722 | netif_rx_ni(skb); |
bf66f373 | 723 | } else { |
aabdfd6a | 724 | netdev_err(net, "cannot allocate error skb\n"); |
bf66f373 CP |
725 | } |
726 | } | |
727 | ||
e0000163 CP |
728 | static void mcp251x_tx_work_handler(struct work_struct *ws) |
729 | { | |
730 | struct mcp251x_priv *priv = container_of(ws, struct mcp251x_priv, | |
731 | tx_work); | |
732 | struct spi_device *spi = priv->spi; | |
733 | struct net_device *net = priv->net; | |
734 | struct can_frame *frame; | |
735 | ||
bf66f373 | 736 | mutex_lock(&priv->mcp_lock); |
e0000163 | 737 | if (priv->tx_skb) { |
e0000163 CP |
738 | if (priv->can.state == CAN_STATE_BUS_OFF) { |
739 | mcp251x_clean(net); | |
bf66f373 CP |
740 | } else { |
741 | frame = (struct can_frame *)priv->tx_skb->data; | |
742 | ||
743 | if (frame->can_dlc > CAN_FRAME_MAX_DATA_LEN) | |
744 | frame->can_dlc = CAN_FRAME_MAX_DATA_LEN; | |
745 | mcp251x_hw_tx(spi, frame, 0); | |
746 | priv->tx_len = 1 + frame->can_dlc; | |
747 | can_put_echo_skb(priv->tx_skb, net, 0); | |
748 | priv->tx_skb = NULL; | |
e0000163 | 749 | } |
e0000163 | 750 | } |
bf66f373 | 751 | mutex_unlock(&priv->mcp_lock); |
e0000163 CP |
752 | } |
753 | ||
bf66f373 | 754 | static void mcp251x_restart_work_handler(struct work_struct *ws) |
e0000163 CP |
755 | { |
756 | struct mcp251x_priv *priv = container_of(ws, struct mcp251x_priv, | |
bf66f373 | 757 | restart_work); |
e0000163 CP |
758 | struct spi_device *spi = priv->spi; |
759 | struct net_device *net = priv->net; | |
e0000163 | 760 | |
bf66f373 | 761 | mutex_lock(&priv->mcp_lock); |
e0000163 CP |
762 | if (priv->after_suspend) { |
763 | mdelay(10); | |
764 | mcp251x_hw_reset(spi); | |
765 | mcp251x_setup(net, priv, spi); | |
766 | if (priv->after_suspend & AFTER_SUSPEND_RESTART) { | |
767 | mcp251x_set_normal_mode(spi); | |
768 | } else if (priv->after_suspend & AFTER_SUSPEND_UP) { | |
769 | netif_device_attach(net); | |
bf66f373 | 770 | mcp251x_clean(net); |
e0000163 | 771 | mcp251x_set_normal_mode(spi); |
bf66f373 | 772 | netif_wake_queue(net); |
e0000163 CP |
773 | } else { |
774 | mcp251x_hw_sleep(spi); | |
775 | } | |
776 | priv->after_suspend = 0; | |
bf66f373 | 777 | priv->force_quit = 0; |
e0000163 CP |
778 | } |
779 | ||
bf66f373 CP |
780 | if (priv->restart_tx) { |
781 | priv->restart_tx = 0; | |
782 | mcp251x_write_reg(spi, TXBCTRL(0), 0); | |
783 | mcp251x_clean(net); | |
784 | netif_wake_queue(net); | |
785 | mcp251x_error_skb(net, CAN_ERR_RESTARTED, 0); | |
786 | } | |
787 | mutex_unlock(&priv->mcp_lock); | |
788 | } | |
e0000163 | 789 | |
bf66f373 CP |
790 | static irqreturn_t mcp251x_can_ist(int irq, void *dev_id) |
791 | { | |
792 | struct mcp251x_priv *priv = dev_id; | |
793 | struct spi_device *spi = priv->spi; | |
794 | struct net_device *net = priv->net; | |
e0000163 | 795 | |
bf66f373 CP |
796 | mutex_lock(&priv->mcp_lock); |
797 | while (!priv->force_quit) { | |
798 | enum can_state new_state; | |
f3a3ed31 | 799 | u8 intf, eflag; |
d3cd1565 | 800 | u8 clear_intf = 0; |
bf66f373 | 801 | int can_id = 0, data1 = 0; |
e0000163 | 802 | |
f3a3ed31 SH |
803 | mcp251x_read_2regs(spi, CANINTF, &intf, &eflag); |
804 | ||
5601b2df MKB |
805 | /* mask out flags we don't care about */ |
806 | intf &= CANINTF_RX | CANINTF_TX | CANINTF_ERR; | |
807 | ||
d3cd1565 | 808 | /* receive buffer 0 */ |
bf66f373 CP |
809 | if (intf & CANINTF_RX0IF) { |
810 | mcp251x_hw_rx(spi, 0); | |
9c473fc3 MKB |
811 | /* |
812 | * Free one buffer ASAP | |
813 | * (The MCP2515 does this automatically.) | |
814 | */ | |
815 | if (mcp251x_is_2510(spi)) | |
816 | mcp251x_write_bits(spi, CANINTF, CANINTF_RX0IF, 0x00); | |
e0000163 CP |
817 | } |
818 | ||
d3cd1565 MKB |
819 | /* receive buffer 1 */ |
820 | if (intf & CANINTF_RX1IF) { | |
bf66f373 | 821 | mcp251x_hw_rx(spi, 1); |
9c473fc3 MKB |
822 | /* the MCP2515 does this automatically */ |
823 | if (mcp251x_is_2510(spi)) | |
824 | clear_intf |= CANINTF_RX1IF; | |
d3cd1565 | 825 | } |
e0000163 | 826 | |
d3cd1565 | 827 | /* any error or tx interrupt we need to clear? */ |
5601b2df MKB |
828 | if (intf & (CANINTF_ERR | CANINTF_TX)) |
829 | clear_intf |= intf & (CANINTF_ERR | CANINTF_TX); | |
d3cd1565 MKB |
830 | if (clear_intf) |
831 | mcp251x_write_bits(spi, CANINTF, clear_intf, 0x00); | |
e0000163 | 832 | |
7e15de3a SH |
833 | if (eflag) |
834 | mcp251x_write_bits(spi, EFLG, eflag, 0x00); | |
bf66f373 | 835 | |
e0000163 CP |
836 | /* Update can state */ |
837 | if (eflag & EFLG_TXBO) { | |
838 | new_state = CAN_STATE_BUS_OFF; | |
839 | can_id |= CAN_ERR_BUSOFF; | |
840 | } else if (eflag & EFLG_TXEP) { | |
841 | new_state = CAN_STATE_ERROR_PASSIVE; | |
842 | can_id |= CAN_ERR_CRTL; | |
843 | data1 |= CAN_ERR_CRTL_TX_PASSIVE; | |
844 | } else if (eflag & EFLG_RXEP) { | |
845 | new_state = CAN_STATE_ERROR_PASSIVE; | |
846 | can_id |= CAN_ERR_CRTL; | |
847 | data1 |= CAN_ERR_CRTL_RX_PASSIVE; | |
848 | } else if (eflag & EFLG_TXWAR) { | |
849 | new_state = CAN_STATE_ERROR_WARNING; | |
850 | can_id |= CAN_ERR_CRTL; | |
851 | data1 |= CAN_ERR_CRTL_TX_WARNING; | |
852 | } else if (eflag & EFLG_RXWAR) { | |
853 | new_state = CAN_STATE_ERROR_WARNING; | |
854 | can_id |= CAN_ERR_CRTL; | |
855 | data1 |= CAN_ERR_CRTL_RX_WARNING; | |
856 | } else { | |
857 | new_state = CAN_STATE_ERROR_ACTIVE; | |
858 | } | |
859 | ||
860 | /* Update can state statistics */ | |
861 | switch (priv->can.state) { | |
862 | case CAN_STATE_ERROR_ACTIVE: | |
863 | if (new_state >= CAN_STATE_ERROR_WARNING && | |
864 | new_state <= CAN_STATE_BUS_OFF) | |
865 | priv->can.can_stats.error_warning++; | |
866 | case CAN_STATE_ERROR_WARNING: /* fallthrough */ | |
867 | if (new_state >= CAN_STATE_ERROR_PASSIVE && | |
868 | new_state <= CAN_STATE_BUS_OFF) | |
869 | priv->can.can_stats.error_passive++; | |
870 | break; | |
871 | default: | |
872 | break; | |
873 | } | |
874 | priv->can.state = new_state; | |
875 | ||
bf66f373 CP |
876 | if (intf & CANINTF_ERRIF) { |
877 | /* Handle overflow counters */ | |
878 | if (eflag & (EFLG_RX0OVR | EFLG_RX1OVR)) { | |
711e4d6e | 879 | if (eflag & EFLG_RX0OVR) { |
bf66f373 | 880 | net->stats.rx_over_errors++; |
711e4d6e SH |
881 | net->stats.rx_errors++; |
882 | } | |
883 | if (eflag & EFLG_RX1OVR) { | |
bf66f373 | 884 | net->stats.rx_over_errors++; |
711e4d6e SH |
885 | net->stats.rx_errors++; |
886 | } | |
bf66f373 CP |
887 | can_id |= CAN_ERR_CRTL; |
888 | data1 |= CAN_ERR_CRTL_RX_OVERFLOW; | |
e0000163 | 889 | } |
bf66f373 | 890 | mcp251x_error_skb(net, can_id, data1); |
e0000163 CP |
891 | } |
892 | ||
893 | if (priv->can.state == CAN_STATE_BUS_OFF) { | |
894 | if (priv->can.restart_ms == 0) { | |
bf66f373 | 895 | priv->force_quit = 1; |
e0000163 CP |
896 | can_bus_off(net); |
897 | mcp251x_hw_sleep(spi); | |
bf66f373 | 898 | break; |
e0000163 CP |
899 | } |
900 | } | |
901 | ||
902 | if (intf == 0) | |
903 | break; | |
904 | ||
5601b2df | 905 | if (intf & CANINTF_TX) { |
e0000163 CP |
906 | net->stats.tx_packets++; |
907 | net->stats.tx_bytes += priv->tx_len - 1; | |
908 | if (priv->tx_len) { | |
909 | can_get_echo_skb(net, 0); | |
910 | priv->tx_len = 0; | |
911 | } | |
912 | netif_wake_queue(net); | |
913 | } | |
914 | ||
bf66f373 CP |
915 | } |
916 | mutex_unlock(&priv->mcp_lock); | |
917 | return IRQ_HANDLED; | |
918 | } | |
e0000163 | 919 | |
bf66f373 CP |
920 | static int mcp251x_open(struct net_device *net) |
921 | { | |
922 | struct mcp251x_priv *priv = netdev_priv(net); | |
923 | struct spi_device *spi = priv->spi; | |
924 | struct mcp251x_platform_data *pdata = spi->dev.platform_data; | |
925 | int ret; | |
926 | ||
927 | ret = open_candev(net); | |
928 | if (ret) { | |
929 | dev_err(&spi->dev, "unable to set initial baudrate!\n"); | |
930 | return ret; | |
931 | } | |
932 | ||
933 | mutex_lock(&priv->mcp_lock); | |
934 | if (pdata->transceiver_enable) | |
935 | pdata->transceiver_enable(1); | |
936 | ||
937 | priv->force_quit = 0; | |
938 | priv->tx_skb = NULL; | |
939 | priv->tx_len = 0; | |
940 | ||
941 | ret = request_threaded_irq(spi->irq, NULL, mcp251x_can_ist, | |
34206f26 EBS |
942 | pdata->irq_flags ? pdata->irq_flags : IRQF_TRIGGER_FALLING, |
943 | DEVICE_NAME, priv); | |
bf66f373 CP |
944 | if (ret) { |
945 | dev_err(&spi->dev, "failed to acquire irq %d\n", spi->irq); | |
946 | if (pdata->transceiver_enable) | |
947 | pdata->transceiver_enable(0); | |
948 | close_candev(net); | |
949 | goto open_unlock; | |
950 | } | |
951 | ||
58a69cb4 | 952 | priv->wq = create_freezable_workqueue("mcp251x_wq"); |
bf66f373 CP |
953 | INIT_WORK(&priv->tx_work, mcp251x_tx_work_handler); |
954 | INIT_WORK(&priv->restart_work, mcp251x_restart_work_handler); | |
955 | ||
956 | ret = mcp251x_hw_reset(spi); | |
957 | if (ret) { | |
958 | mcp251x_open_clean(net); | |
959 | goto open_unlock; | |
960 | } | |
961 | ret = mcp251x_setup(net, priv, spi); | |
962 | if (ret) { | |
963 | mcp251x_open_clean(net); | |
964 | goto open_unlock; | |
e0000163 | 965 | } |
bf66f373 CP |
966 | ret = mcp251x_set_normal_mode(spi); |
967 | if (ret) { | |
968 | mcp251x_open_clean(net); | |
969 | goto open_unlock; | |
970 | } | |
971 | netif_wake_queue(net); | |
972 | ||
973 | open_unlock: | |
974 | mutex_unlock(&priv->mcp_lock); | |
975 | return ret; | |
e0000163 CP |
976 | } |
977 | ||
978 | static const struct net_device_ops mcp251x_netdev_ops = { | |
979 | .ndo_open = mcp251x_open, | |
980 | .ndo_stop = mcp251x_stop, | |
981 | .ndo_start_xmit = mcp251x_hard_start_xmit, | |
982 | }; | |
983 | ||
984 | static int __devinit mcp251x_can_probe(struct spi_device *spi) | |
985 | { | |
986 | struct net_device *net; | |
987 | struct mcp251x_priv *priv; | |
988 | struct mcp251x_platform_data *pdata = spi->dev.platform_data; | |
989 | int ret = -ENODEV; | |
990 | ||
991 | if (!pdata) | |
992 | /* Platform data is required for osc freq */ | |
993 | goto error_out; | |
994 | ||
995 | /* Allocate can/net device */ | |
996 | net = alloc_candev(sizeof(struct mcp251x_priv), TX_ECHO_SKB_MAX); | |
997 | if (!net) { | |
998 | ret = -ENOMEM; | |
999 | goto error_alloc; | |
1000 | } | |
1001 | ||
1002 | net->netdev_ops = &mcp251x_netdev_ops; | |
1003 | net->flags |= IFF_ECHO; | |
1004 | ||
1005 | priv = netdev_priv(net); | |
1006 | priv->can.bittiming_const = &mcp251x_bittiming_const; | |
1007 | priv->can.do_set_mode = mcp251x_do_set_mode; | |
1008 | priv->can.clock.freq = pdata->oscillator_frequency / 2; | |
ad72c347 CP |
1009 | priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES | |
1010 | CAN_CTRLMODE_LOOPBACK | CAN_CTRLMODE_LISTENONLY; | |
f1f8c6cb | 1011 | priv->model = spi_get_device_id(spi)->driver_data; |
e0000163 CP |
1012 | priv->net = net; |
1013 | dev_set_drvdata(&spi->dev, priv); | |
1014 | ||
1015 | priv->spi = spi; | |
bf66f373 | 1016 | mutex_init(&priv->mcp_lock); |
e0000163 CP |
1017 | |
1018 | /* If requested, allocate DMA buffers */ | |
1019 | if (mcp251x_enable_dma) { | |
1020 | spi->dev.coherent_dma_mask = ~0; | |
1021 | ||
1022 | /* | |
1023 | * Minimum coherent DMA allocation is PAGE_SIZE, so allocate | |
1024 | * that much and share it between Tx and Rx DMA buffers. | |
1025 | */ | |
1026 | priv->spi_tx_buf = dma_alloc_coherent(&spi->dev, | |
1027 | PAGE_SIZE, | |
1028 | &priv->spi_tx_dma, | |
1029 | GFP_DMA); | |
1030 | ||
1031 | if (priv->spi_tx_buf) { | |
c2fd03a0 | 1032 | priv->spi_rx_buf = (priv->spi_tx_buf + (PAGE_SIZE / 2)); |
e0000163 CP |
1033 | priv->spi_rx_dma = (dma_addr_t)(priv->spi_tx_dma + |
1034 | (PAGE_SIZE / 2)); | |
1035 | } else { | |
1036 | /* Fall back to non-DMA */ | |
1037 | mcp251x_enable_dma = 0; | |
1038 | } | |
1039 | } | |
1040 | ||
1041 | /* Allocate non-DMA buffers */ | |
1042 | if (!mcp251x_enable_dma) { | |
1043 | priv->spi_tx_buf = kmalloc(SPI_TRANSFER_BUF_LEN, GFP_KERNEL); | |
1044 | if (!priv->spi_tx_buf) { | |
1045 | ret = -ENOMEM; | |
1046 | goto error_tx_buf; | |
1047 | } | |
1048 | priv->spi_rx_buf = kmalloc(SPI_TRANSFER_BUF_LEN, GFP_KERNEL); | |
ce739b47 | 1049 | if (!priv->spi_rx_buf) { |
e0000163 CP |
1050 | ret = -ENOMEM; |
1051 | goto error_rx_buf; | |
1052 | } | |
1053 | } | |
1054 | ||
1055 | if (pdata->power_enable) | |
1056 | pdata->power_enable(1); | |
1057 | ||
1058 | /* Call out to platform specific setup */ | |
1059 | if (pdata->board_specific_setup) | |
1060 | pdata->board_specific_setup(spi); | |
1061 | ||
1062 | SET_NETDEV_DEV(net, &spi->dev); | |
1063 | ||
e0000163 CP |
1064 | /* Configure the SPI bus */ |
1065 | spi->mode = SPI_MODE_0; | |
1066 | spi->bits_per_word = 8; | |
1067 | spi_setup(spi); | |
1068 | ||
bf66f373 | 1069 | /* Here is OK to not lock the MCP, no one knows about it yet */ |
e0000163 CP |
1070 | if (!mcp251x_hw_probe(spi)) { |
1071 | dev_info(&spi->dev, "Probe failed\n"); | |
1072 | goto error_probe; | |
1073 | } | |
1074 | mcp251x_hw_sleep(spi); | |
1075 | ||
1076 | if (pdata->transceiver_enable) | |
1077 | pdata->transceiver_enable(0); | |
1078 | ||
1079 | ret = register_candev(net); | |
1080 | if (!ret) { | |
1081 | dev_info(&spi->dev, "probed\n"); | |
1082 | return ret; | |
1083 | } | |
1084 | error_probe: | |
1085 | if (!mcp251x_enable_dma) | |
1086 | kfree(priv->spi_rx_buf); | |
1087 | error_rx_buf: | |
1088 | if (!mcp251x_enable_dma) | |
1089 | kfree(priv->spi_tx_buf); | |
1090 | error_tx_buf: | |
1091 | free_candev(net); | |
1092 | if (mcp251x_enable_dma) | |
1093 | dma_free_coherent(&spi->dev, PAGE_SIZE, | |
1094 | priv->spi_tx_buf, priv->spi_tx_dma); | |
1095 | error_alloc: | |
1096 | if (pdata->power_enable) | |
1097 | pdata->power_enable(0); | |
1098 | dev_err(&spi->dev, "probe failed\n"); | |
1099 | error_out: | |
1100 | return ret; | |
1101 | } | |
1102 | ||
1103 | static int __devexit mcp251x_can_remove(struct spi_device *spi) | |
1104 | { | |
1105 | struct mcp251x_platform_data *pdata = spi->dev.platform_data; | |
1106 | struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev); | |
1107 | struct net_device *net = priv->net; | |
1108 | ||
1109 | unregister_candev(net); | |
1110 | free_candev(net); | |
1111 | ||
e0000163 CP |
1112 | if (mcp251x_enable_dma) { |
1113 | dma_free_coherent(&spi->dev, PAGE_SIZE, | |
1114 | priv->spi_tx_buf, priv->spi_tx_dma); | |
1115 | } else { | |
1116 | kfree(priv->spi_tx_buf); | |
1117 | kfree(priv->spi_rx_buf); | |
1118 | } | |
1119 | ||
1120 | if (pdata->power_enable) | |
1121 | pdata->power_enable(0); | |
1122 | ||
1123 | return 0; | |
1124 | } | |
1125 | ||
1126 | #ifdef CONFIG_PM | |
1127 | static int mcp251x_can_suspend(struct spi_device *spi, pm_message_t state) | |
1128 | { | |
1129 | struct mcp251x_platform_data *pdata = spi->dev.platform_data; | |
1130 | struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev); | |
1131 | struct net_device *net = priv->net; | |
1132 | ||
bf66f373 CP |
1133 | priv->force_quit = 1; |
1134 | disable_irq(spi->irq); | |
1135 | /* | |
1136 | * Note: at this point neither IST nor workqueues are running. | |
1137 | * open/stop cannot be called anyway so locking is not needed | |
1138 | */ | |
e0000163 CP |
1139 | if (netif_running(net)) { |
1140 | netif_device_detach(net); | |
1141 | ||
1142 | mcp251x_hw_sleep(spi); | |
1143 | if (pdata->transceiver_enable) | |
1144 | pdata->transceiver_enable(0); | |
1145 | priv->after_suspend = AFTER_SUSPEND_UP; | |
1146 | } else { | |
1147 | priv->after_suspend = AFTER_SUSPEND_DOWN; | |
1148 | } | |
1149 | ||
1150 | if (pdata->power_enable) { | |
1151 | pdata->power_enable(0); | |
1152 | priv->after_suspend |= AFTER_SUSPEND_POWER; | |
1153 | } | |
1154 | ||
1155 | return 0; | |
1156 | } | |
1157 | ||
1158 | static int mcp251x_can_resume(struct spi_device *spi) | |
1159 | { | |
1160 | struct mcp251x_platform_data *pdata = spi->dev.platform_data; | |
1161 | struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev); | |
1162 | ||
1163 | if (priv->after_suspend & AFTER_SUSPEND_POWER) { | |
1164 | pdata->power_enable(1); | |
bf66f373 | 1165 | queue_work(priv->wq, &priv->restart_work); |
e0000163 CP |
1166 | } else { |
1167 | if (priv->after_suspend & AFTER_SUSPEND_UP) { | |
1168 | if (pdata->transceiver_enable) | |
1169 | pdata->transceiver_enable(1); | |
bf66f373 | 1170 | queue_work(priv->wq, &priv->restart_work); |
e0000163 CP |
1171 | } else { |
1172 | priv->after_suspend = 0; | |
1173 | } | |
1174 | } | |
bf66f373 CP |
1175 | priv->force_quit = 0; |
1176 | enable_irq(spi->irq); | |
e0000163 CP |
1177 | return 0; |
1178 | } | |
1179 | #else | |
1180 | #define mcp251x_can_suspend NULL | |
1181 | #define mcp251x_can_resume NULL | |
1182 | #endif | |
1183 | ||
f1f8c6cb | 1184 | static const struct spi_device_id mcp251x_id_table[] = { |
e446630c MZ |
1185 | { "mcp2510", CAN_MCP251X_MCP2510 }, |
1186 | { "mcp2515", CAN_MCP251X_MCP2515 }, | |
1187 | { }, | |
1188 | }; | |
1189 | ||
1190 | MODULE_DEVICE_TABLE(spi, mcp251x_id_table); | |
1191 | ||
e0000163 CP |
1192 | static struct spi_driver mcp251x_can_driver = { |
1193 | .driver = { | |
1194 | .name = DEVICE_NAME, | |
1195 | .bus = &spi_bus_type, | |
1196 | .owner = THIS_MODULE, | |
1197 | }, | |
1198 | ||
e446630c | 1199 | .id_table = mcp251x_id_table, |
e0000163 CP |
1200 | .probe = mcp251x_can_probe, |
1201 | .remove = __devexit_p(mcp251x_can_remove), | |
1202 | .suspend = mcp251x_can_suspend, | |
1203 | .resume = mcp251x_can_resume, | |
1204 | }; | |
1205 | ||
1206 | static int __init mcp251x_can_init(void) | |
1207 | { | |
1208 | return spi_register_driver(&mcp251x_can_driver); | |
1209 | } | |
1210 | ||
1211 | static void __exit mcp251x_can_exit(void) | |
1212 | { | |
1213 | spi_unregister_driver(&mcp251x_can_driver); | |
1214 | } | |
1215 | ||
1216 | module_init(mcp251x_can_init); | |
1217 | module_exit(mcp251x_can_exit); | |
1218 | ||
1219 | MODULE_AUTHOR("Chris Elston <celston@katalix.com>, " | |
1220 | "Christian Pellegrin <chripell@evolware.org>"); | |
1221 | MODULE_DESCRIPTION("Microchip 251x CAN driver"); | |
1222 | MODULE_LICENSE("GPL v2"); |