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afa17a50 WS |
1 | /* |
2 | * CAN bus driver for the Freescale MPC5xxx embedded CPU. | |
3 | * | |
4 | * Copyright (C) 2004-2005 Andrey Volkov <avolkov@varma-el.com>, | |
5 | * Varma Electronics Oy | |
6 | * Copyright (C) 2008-2009 Wolfgang Grandegger <wg@grandegger.com> | |
7 | * Copyright (C) 2009 Wolfram Sang, Pengutronix <w.sang@pengutronix.de> | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the version 2 of the GNU General Public License | |
11 | * as published by the Free Software Foundation | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but | |
14 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | */ | |
22 | ||
23 | #include <linux/kernel.h> | |
24 | #include <linux/module.h> | |
25 | #include <linux/interrupt.h> | |
26 | #include <linux/platform_device.h> | |
27 | #include <linux/netdevice.h> | |
afa17a50 WS |
28 | #include <linux/can/dev.h> |
29 | #include <linux/of_platform.h> | |
30 | #include <sysdev/fsl_soc.h> | |
bf3af547 | 31 | #include <linux/clk.h> |
afa17a50 WS |
32 | #include <linux/io.h> |
33 | #include <asm/mpc52xx.h> | |
34 | ||
35 | #include "mscan.h" | |
36 | ||
afa17a50 WS |
37 | #define DRV_NAME "mpc5xxx_can" |
38 | ||
bf3af547 WG |
39 | struct mpc5xxx_can_data { |
40 | unsigned int type; | |
2dc11581 | 41 | u32 (*get_clock)(struct platform_device *ofdev, const char *clock_name, |
bf3af547 WG |
42 | int *mscan_clksrc); |
43 | }; | |
44 | ||
c5bab5e9 | 45 | #ifdef CONFIG_PPC_MPC52xx |
bf3af547 | 46 | static struct of_device_id __devinitdata mpc52xx_cdm_ids[] = { |
afa17a50 | 47 | { .compatible = "fsl,mpc5200-cdm", }, |
afa17a50 WS |
48 | {} |
49 | }; | |
50 | ||
2dc11581 | 51 | static u32 __devinit mpc52xx_can_get_clock(struct platform_device *ofdev, |
bf3af547 WG |
52 | const char *clock_name, |
53 | int *mscan_clksrc) | |
afa17a50 | 54 | { |
3f158c25 | 55 | unsigned int pvr; |
afa17a50 WS |
56 | struct mpc52xx_cdm __iomem *cdm; |
57 | struct device_node *np_cdm; | |
58 | unsigned int freq; | |
59 | u32 val; | |
60 | ||
3f158c25 WS |
61 | pvr = mfspr(SPRN_PVR); |
62 | ||
bf3af547 WG |
63 | /* |
64 | * Either the oscillator clock (SYS_XTAL_IN) or the IP bus clock | |
65 | * (IP_CLK) can be selected as MSCAN clock source. According to | |
66 | * the MPC5200 user's manual, the oscillator clock is the better | |
67 | * choice as it has less jitter. For this reason, it is selected | |
68 | * by default. Unfortunately, it can not be selected for the old | |
69 | * MPC5200 Rev. A chips due to a hardware bug (check errata). | |
70 | */ | |
71 | if (clock_name && strcmp(clock_name, "ip") == 0) | |
72 | *mscan_clksrc = MSCAN_CLKSRC_BUS; | |
73 | else | |
74 | *mscan_clksrc = MSCAN_CLKSRC_XTAL; | |
75 | ||
6bd17eb9 | 76 | freq = mpc5xxx_get_bus_frequency(ofdev->dev.of_node); |
afa17a50 WS |
77 | if (!freq) |
78 | return 0; | |
79 | ||
bf3af547 | 80 | if (*mscan_clksrc == MSCAN_CLKSRC_BUS || pvr == 0x80822011) |
3f158c25 WS |
81 | return freq; |
82 | ||
83 | /* Determine SYS_XTAL_IN frequency from the clock domain settings */ | |
afa17a50 WS |
84 | np_cdm = of_find_matching_node(NULL, mpc52xx_cdm_ids); |
85 | if (!np_cdm) { | |
c5bab5e9 | 86 | dev_err(&ofdev->dev, "can't get clock node!\n"); |
afa17a50 WS |
87 | return 0; |
88 | } | |
89 | cdm = of_iomap(np_cdm, 0); | |
afa17a50 WS |
90 | |
91 | if (in_8(&cdm->ipb_clk_sel) & 0x1) | |
92 | freq *= 2; | |
0285e7ce WS |
93 | val = in_be32(&cdm->rstcfg); |
94 | ||
95 | freq *= (val & (1 << 5)) ? 8 : 4; | |
96 | freq /= (val & (1 << 6)) ? 12 : 16; | |
afa17a50 | 97 | |
bf3af547 | 98 | of_node_put(np_cdm); |
afa17a50 WS |
99 | iounmap(cdm); |
100 | ||
101 | return freq; | |
102 | } | |
c5bab5e9 | 103 | #else /* !CONFIG_PPC_MPC52xx */ |
2dc11581 | 104 | static u32 __devinit mpc52xx_can_get_clock(struct platform_device *ofdev, |
bf3af547 WG |
105 | const char *clock_name, |
106 | int *mscan_clksrc) | |
107 | { | |
108 | return 0; | |
109 | } | |
c5bab5e9 | 110 | #endif /* CONFIG_PPC_MPC52xx */ |
bf3af547 WG |
111 | |
112 | #ifdef CONFIG_PPC_MPC512x | |
113 | struct mpc512x_clockctl { | |
114 | u32 spmr; /* System PLL Mode Reg */ | |
115 | u32 sccr[2]; /* System Clk Ctrl Reg 1 & 2 */ | |
116 | u32 scfr1; /* System Clk Freq Reg 1 */ | |
117 | u32 scfr2; /* System Clk Freq Reg 2 */ | |
118 | u32 reserved; | |
119 | u32 bcr; /* Bread Crumb Reg */ | |
120 | u32 pccr[12]; /* PSC Clk Ctrl Reg 0-11 */ | |
121 | u32 spccr; /* SPDIF Clk Ctrl Reg */ | |
122 | u32 cccr; /* CFM Clk Ctrl Reg */ | |
123 | u32 dccr; /* DIU Clk Cnfg Reg */ | |
124 | u32 mccr[4]; /* MSCAN Clk Ctrl Reg 1-3 */ | |
125 | }; | |
126 | ||
127 | static struct of_device_id __devinitdata mpc512x_clock_ids[] = { | |
128 | { .compatible = "fsl,mpc5121-clock", }, | |
129 | {} | |
130 | }; | |
131 | ||
2dc11581 | 132 | static u32 __devinit mpc512x_can_get_clock(struct platform_device *ofdev, |
bf3af547 WG |
133 | const char *clock_name, |
134 | int *mscan_clksrc) | |
135 | { | |
136 | struct mpc512x_clockctl __iomem *clockctl; | |
137 | struct device_node *np_clock; | |
138 | struct clk *sys_clk, *ref_clk; | |
139 | int plen, clockidx, clocksrc = -1; | |
140 | u32 sys_freq, val, clockdiv = 1, freq = 0; | |
141 | const u32 *pval; | |
142 | ||
143 | np_clock = of_find_matching_node(NULL, mpc512x_clock_ids); | |
144 | if (!np_clock) { | |
145 | dev_err(&ofdev->dev, "couldn't find clock node\n"); | |
aed5029e | 146 | return 0; |
bf3af547 WG |
147 | } |
148 | clockctl = of_iomap(np_clock, 0); | |
149 | if (!clockctl) { | |
150 | dev_err(&ofdev->dev, "couldn't map clock registers\n"); | |
aed5029e | 151 | goto exit_put; |
bf3af547 WG |
152 | } |
153 | ||
154 | /* Determine the MSCAN device index from the physical address */ | |
6bd17eb9 | 155 | pval = of_get_property(ofdev->dev.of_node, "reg", &plen); |
bf3af547 WG |
156 | BUG_ON(!pval || plen < sizeof(*pval)); |
157 | clockidx = (*pval & 0x80) ? 1 : 0; | |
158 | if (*pval & 0x2000) | |
159 | clockidx += 2; | |
160 | ||
161 | /* | |
162 | * Clock source and divider selection: 3 different clock sources | |
163 | * can be selected: "ip", "ref" or "sys". For the latter two, a | |
164 | * clock divider can be defined as well. If the clock source is | |
165 | * not specified by the device tree, we first try to find an | |
166 | * optimal CAN source clock based on the system clock. If that | |
167 | * is not posslible, the reference clock will be used. | |
168 | */ | |
169 | if (clock_name && !strcmp(clock_name, "ip")) { | |
170 | *mscan_clksrc = MSCAN_CLKSRC_IPS; | |
6bd17eb9 | 171 | freq = mpc5xxx_get_bus_frequency(ofdev->dev.of_node); |
bf3af547 WG |
172 | } else { |
173 | *mscan_clksrc = MSCAN_CLKSRC_BUS; | |
174 | ||
6bd17eb9 | 175 | pval = of_get_property(ofdev->dev.of_node, |
bf3af547 WG |
176 | "fsl,mscan-clock-divider", &plen); |
177 | if (pval && plen == sizeof(*pval)) | |
178 | clockdiv = *pval; | |
179 | if (!clockdiv) | |
180 | clockdiv = 1; | |
181 | ||
182 | if (!clock_name || !strcmp(clock_name, "sys")) { | |
183 | sys_clk = clk_get(&ofdev->dev, "sys_clk"); | |
184 | if (!sys_clk) { | |
185 | dev_err(&ofdev->dev, "couldn't get sys_clk\n"); | |
186 | goto exit_unmap; | |
187 | } | |
188 | /* Get and round up/down sys clock rate */ | |
189 | sys_freq = 1000000 * | |
190 | ((clk_get_rate(sys_clk) + 499999) / 1000000); | |
191 | ||
192 | if (!clock_name) { | |
193 | /* A multiple of 16 MHz would be optimal */ | |
194 | if ((sys_freq % 16000000) == 0) { | |
195 | clocksrc = 0; | |
196 | clockdiv = sys_freq / 16000000; | |
197 | freq = sys_freq / clockdiv; | |
198 | } | |
199 | } else { | |
200 | clocksrc = 0; | |
201 | freq = sys_freq / clockdiv; | |
202 | } | |
203 | } | |
204 | ||
205 | if (clocksrc < 0) { | |
206 | ref_clk = clk_get(&ofdev->dev, "ref_clk"); | |
207 | if (!ref_clk) { | |
208 | dev_err(&ofdev->dev, "couldn't get ref_clk\n"); | |
209 | goto exit_unmap; | |
210 | } | |
211 | clocksrc = 1; | |
212 | freq = clk_get_rate(ref_clk) / clockdiv; | |
213 | } | |
214 | } | |
215 | ||
216 | /* Disable clock */ | |
217 | out_be32(&clockctl->mccr[clockidx], 0x0); | |
218 | if (clocksrc >= 0) { | |
219 | /* Set source and divider */ | |
220 | val = (clocksrc << 14) | ((clockdiv - 1) << 17); | |
221 | out_be32(&clockctl->mccr[clockidx], val); | |
222 | /* Enable clock */ | |
223 | out_be32(&clockctl->mccr[clockidx], val | 0x10000); | |
224 | } | |
225 | ||
226 | /* Enable MSCAN clock domain */ | |
227 | val = in_be32(&clockctl->sccr[1]); | |
228 | if (!(val & (1 << 25))) | |
229 | out_be32(&clockctl->sccr[1], val | (1 << 25)); | |
230 | ||
231 | dev_dbg(&ofdev->dev, "using '%s' with frequency divider %d\n", | |
232 | *mscan_clksrc == MSCAN_CLKSRC_IPS ? "ips_clk" : | |
233 | clocksrc == 1 ? "ref_clk" : "sys_clk", clockdiv); | |
234 | ||
235 | exit_unmap: | |
bf3af547 | 236 | iounmap(clockctl); |
aed5029e JL |
237 | exit_put: |
238 | of_node_put(np_clock); | |
bf3af547 WG |
239 | return freq; |
240 | } | |
241 | #else /* !CONFIG_PPC_MPC512x */ | |
2dc11581 | 242 | static u32 __devinit mpc512x_can_get_clock(struct platform_device *ofdev, |
bf3af547 WG |
243 | const char *clock_name, |
244 | int *mscan_clksrc) | |
245 | { | |
246 | return 0; | |
247 | } | |
248 | #endif /* CONFIG_PPC_MPC512x */ | |
afa17a50 | 249 | |
74888760 | 250 | static int __devinit mpc5xxx_can_probe(struct platform_device *ofdev) |
afa17a50 | 251 | { |
74888760 | 252 | struct mpc5xxx_can_data *data; |
6bd17eb9 | 253 | struct device_node *np = ofdev->dev.of_node; |
afa17a50 WS |
254 | struct net_device *dev; |
255 | struct mscan_priv *priv; | |
256 | void __iomem *base; | |
bf3af547 WG |
257 | const char *clock_name = NULL; |
258 | int irq, mscan_clksrc = 0; | |
259 | int err = -ENOMEM; | |
afa17a50 | 260 | |
74888760 GL |
261 | if (!ofdev->dev.of_match) |
262 | return -EINVAL; | |
263 | data = (struct mpc5xxx_can_data *)of_dev->dev.of_match->data; | |
264 | ||
bf3af547 | 265 | base = of_iomap(np, 0); |
afa17a50 WS |
266 | if (!base) { |
267 | dev_err(&ofdev->dev, "couldn't ioremap\n"); | |
bf3af547 | 268 | return err; |
afa17a50 WS |
269 | } |
270 | ||
271 | irq = irq_of_parse_and_map(np, 0); | |
272 | if (!irq) { | |
273 | dev_err(&ofdev->dev, "no irq found\n"); | |
274 | err = -ENODEV; | |
275 | goto exit_unmap_mem; | |
276 | } | |
277 | ||
278 | dev = alloc_mscandev(); | |
bf3af547 | 279 | if (!dev) |
afa17a50 | 280 | goto exit_dispose_irq; |
afa17a50 WS |
281 | |
282 | priv = netdev_priv(dev); | |
283 | priv->reg_base = base; | |
284 | dev->irq = irq; | |
285 | ||
bf3af547 WG |
286 | clock_name = of_get_property(np, "fsl,mscan-clock-source", NULL); |
287 | ||
288 | BUG_ON(!data); | |
289 | priv->type = data->type; | |
290 | priv->can.clock.freq = data->get_clock(ofdev, clock_name, | |
291 | &mscan_clksrc); | |
afa17a50 | 292 | if (!priv->can.clock.freq) { |
bf3af547 | 293 | dev_err(&ofdev->dev, "couldn't get MSCAN clock properties\n"); |
afa17a50 WS |
294 | goto exit_free_mscan; |
295 | } | |
296 | ||
297 | SET_NETDEV_DEV(dev, &ofdev->dev); | |
298 | ||
bf3af547 | 299 | err = register_mscandev(dev, mscan_clksrc); |
afa17a50 WS |
300 | if (err) { |
301 | dev_err(&ofdev->dev, "registering %s failed (err=%d)\n", | |
302 | DRV_NAME, err); | |
303 | goto exit_free_mscan; | |
304 | } | |
305 | ||
306 | dev_set_drvdata(&ofdev->dev, dev); | |
307 | ||
308 | dev_info(&ofdev->dev, "MSCAN at 0x%p, irq %d, clock %d Hz\n", | |
309 | priv->reg_base, dev->irq, priv->can.clock.freq); | |
310 | ||
311 | return 0; | |
312 | ||
313 | exit_free_mscan: | |
314 | free_candev(dev); | |
315 | exit_dispose_irq: | |
316 | irq_dispose_mapping(irq); | |
317 | exit_unmap_mem: | |
318 | iounmap(base); | |
bf3af547 | 319 | |
afa17a50 WS |
320 | return err; |
321 | } | |
322 | ||
2dc11581 | 323 | static int __devexit mpc5xxx_can_remove(struct platform_device *ofdev) |
afa17a50 WS |
324 | { |
325 | struct net_device *dev = dev_get_drvdata(&ofdev->dev); | |
326 | struct mscan_priv *priv = netdev_priv(dev); | |
327 | ||
328 | dev_set_drvdata(&ofdev->dev, NULL); | |
329 | ||
330 | unregister_mscandev(dev); | |
331 | iounmap(priv->reg_base); | |
332 | irq_dispose_mapping(dev->irq); | |
333 | free_candev(dev); | |
334 | ||
335 | return 0; | |
336 | } | |
337 | ||
338 | #ifdef CONFIG_PM | |
339 | static struct mscan_regs saved_regs; | |
2dc11581 | 340 | static int mpc5xxx_can_suspend(struct platform_device *ofdev, pm_message_t state) |
afa17a50 WS |
341 | { |
342 | struct net_device *dev = dev_get_drvdata(&ofdev->dev); | |
343 | struct mscan_priv *priv = netdev_priv(dev); | |
344 | struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base; | |
345 | ||
346 | _memcpy_fromio(&saved_regs, regs, sizeof(*regs)); | |
347 | ||
348 | return 0; | |
349 | } | |
350 | ||
2dc11581 | 351 | static int mpc5xxx_can_resume(struct platform_device *ofdev) |
afa17a50 WS |
352 | { |
353 | struct net_device *dev = dev_get_drvdata(&ofdev->dev); | |
354 | struct mscan_priv *priv = netdev_priv(dev); | |
355 | struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base; | |
356 | ||
357 | regs->canctl0 |= MSCAN_INITRQ; | |
0285e7ce | 358 | while (!(regs->canctl1 & MSCAN_INITAK)) |
afa17a50 WS |
359 | udelay(10); |
360 | ||
361 | regs->canctl1 = saved_regs.canctl1; | |
362 | regs->canbtr0 = saved_regs.canbtr0; | |
363 | regs->canbtr1 = saved_regs.canbtr1; | |
364 | regs->canidac = saved_regs.canidac; | |
365 | ||
366 | /* restore masks, buffers etc. */ | |
367 | _memcpy_toio(®s->canidar1_0, (void *)&saved_regs.canidar1_0, | |
368 | sizeof(*regs) - offsetof(struct mscan_regs, canidar1_0)); | |
369 | ||
370 | regs->canctl0 &= ~MSCAN_INITRQ; | |
371 | regs->cantbsel = saved_regs.cantbsel; | |
372 | regs->canrier = saved_regs.canrier; | |
373 | regs->cantier = saved_regs.cantier; | |
374 | regs->canctl0 = saved_regs.canctl0; | |
375 | ||
376 | return 0; | |
377 | } | |
378 | #endif | |
379 | ||
bf3af547 WG |
380 | static struct mpc5xxx_can_data __devinitdata mpc5200_can_data = { |
381 | .type = MSCAN_TYPE_MPC5200, | |
382 | .get_clock = mpc52xx_can_get_clock, | |
383 | }; | |
384 | ||
385 | static struct mpc5xxx_can_data __devinitdata mpc5121_can_data = { | |
386 | .type = MSCAN_TYPE_MPC5121, | |
387 | .get_clock = mpc512x_can_get_clock, | |
388 | }; | |
389 | ||
afa17a50 | 390 | static struct of_device_id __devinitdata mpc5xxx_can_table[] = { |
bf3af547 WG |
391 | { .compatible = "fsl,mpc5200-mscan", .data = &mpc5200_can_data, }, |
392 | /* Note that only MPC5121 Rev. 2 (and later) is supported */ | |
393 | { .compatible = "fsl,mpc5121-mscan", .data = &mpc5121_can_data, }, | |
afa17a50 WS |
394 | {}, |
395 | }; | |
396 | ||
74888760 | 397 | static struct platform_driver mpc5xxx_can_driver = { |
4018294b GL |
398 | .driver = { |
399 | .name = "mpc5xxx_can", | |
400 | .owner = THIS_MODULE, | |
401 | .of_match_table = mpc5xxx_can_table, | |
402 | }, | |
afa17a50 WS |
403 | .probe = mpc5xxx_can_probe, |
404 | .remove = __devexit_p(mpc5xxx_can_remove), | |
405 | #ifdef CONFIG_PM | |
406 | .suspend = mpc5xxx_can_suspend, | |
407 | .resume = mpc5xxx_can_resume, | |
408 | #endif | |
afa17a50 WS |
409 | }; |
410 | ||
411 | static int __init mpc5xxx_can_init(void) | |
412 | { | |
74888760 | 413 | return platform_driver_register(&mpc5xxx_can_driver); |
afa17a50 WS |
414 | } |
415 | module_init(mpc5xxx_can_init); | |
416 | ||
417 | static void __exit mpc5xxx_can_exit(void) | |
418 | { | |
74888760 | 419 | platform_driver_unregister(&mpc5xxx_can_driver); |
afa17a50 WS |
420 | }; |
421 | module_exit(mpc5xxx_can_exit); | |
422 | ||
423 | MODULE_AUTHOR("Wolfgang Grandegger <wg@grandegger.com>"); | |
bf3af547 | 424 | MODULE_DESCRIPTION("Freescale MPC5xxx CAN driver"); |
afa17a50 | 425 | MODULE_LICENSE("GPL v2"); |