projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
pch_can: Reduce register access
[deliverable/linux.git] / drivers / net / can / pch_can.c
CommitLineData
b21d18b5
MO		 1/*
2 * Copyright (C) 1999 - 2010 Intel Corporation.
3 * Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; version 2 of the License.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
17 */
18
19#include <linux/interrupt.h>
20#include <linux/delay.h>
21#include <linux/io.h>
22#include <linux/module.h>
23#include <linux/sched.h>
24#include <linux/pci.h>
25#include <linux/init.h>
26#include <linux/kernel.h>
27#include <linux/types.h>
28#include <linux/errno.h>
29#include <linux/netdevice.h>
30#include <linux/skbuff.h>
31#include <linux/can.h>
32#include <linux/can/dev.h>
33#include <linux/can/error.h>
34
0a80410d
T		 35#define PCH_CTRL_INIT BIT(0) /* The INIT bit of CANCONT register. */
36#define PCH_CTRL_IE BIT(1) /* The IE bit of CAN control register */
37#define PCH_CTRL_IE_SIE_EIE (BIT(3) | BIT(2) | BIT(1))
38#define PCH_CTRL_CCE BIT(6)
39#define PCH_CTRL_OPT BIT(7) /* The OPT bit of CANCONT register. */
40#define PCH_OPT_SILENT BIT(3) /* The Silent bit of CANOPT reg. */
41#define PCH_OPT_LBACK BIT(4) /* The LoopBack bit of CANOPT reg. */
42
086b5650
T		 43#define PCH_CMASK_RX_TX_SET 0x00f3
44#define PCH_CMASK_RX_TX_GET 0x0073
45#define PCH_CMASK_ALL 0xff
0a80410d
T		 46#define PCH_CMASK_NEWDAT BIT(2)
47#define PCH_CMASK_CLRINTPND BIT(3)
48#define PCH_CMASK_CTRL BIT(4)
49#define PCH_CMASK_ARB BIT(5)
50#define PCH_CMASK_MASK BIT(6)
51#define PCH_CMASK_RDWR BIT(7)
52#define PCH_IF_MCONT_NEWDAT BIT(15)
53#define PCH_IF_MCONT_MSGLOST BIT(14)
54#define PCH_IF_MCONT_INTPND BIT(13)
55#define PCH_IF_MCONT_UMASK BIT(12)
56#define PCH_IF_MCONT_TXIE BIT(11)
57#define PCH_IF_MCONT_RXIE BIT(10)
58#define PCH_IF_MCONT_RMTEN BIT(9)
59#define PCH_IF_MCONT_TXRQXT BIT(8)
60#define PCH_IF_MCONT_EOB BIT(7)
61#define PCH_IF_MCONT_DLC (BIT(0) | BIT(1) | BIT(2) | BIT(3))
62#define PCH_MASK2_MDIR_MXTD (BIT(14) | BIT(15))
63#define PCH_ID2_DIR BIT(13)
64#define PCH_ID2_XTD BIT(14)
65#define PCH_ID_MSGVAL BIT(15)
66#define PCH_IF_CREQ_BUSY BIT(15)
086b5650
T		 67
68#define PCH_STATUS_INT 0x8000
69#define PCH_REC 0x00007f00
70#define PCH_TEC 0x000000ff
b21d18b5 71
0a80410d
T		 72#define PCH_TX_OK BIT(3)
73#define PCH_RX_OK BIT(4)
74#define PCH_EPASSIV BIT(5)
75#define PCH_EWARN BIT(6)
76#define PCH_BUS_OFF BIT(7)
b21d18b5
MO		 77
78/* bit position of certain controller bits. */
bd58cbc3
T		 79#define PCH_BIT_BRP_SHIFT 0
80#define PCH_BIT_SJW_SHIFT 6
81#define PCH_BIT_TSEG1_SHIFT 8
82#define PCH_BIT_TSEG2_SHIFT 12
83#define PCH_BIT_BRPE_BRPE_SHIFT 6
84
086b5650
T		 85#define PCH_MSK_BITT_BRP 0x3f
86#define PCH_MSK_BRPE_BRPE 0x3c0
87#define PCH_MSK_CTRL_IE_SIE_EIE 0x07
88#define PCH_COUNTER_LIMIT 10
b21d18b5
MO		 89
90#define PCH_CAN_CLK 50000000 /* 50MHz */
91
92/* Define the number of message object.
93 * PCH CAN communications are done via Message RAM.
94 * The Message RAM consists of 32 message objects. */
15ffc8fd
T		 95#define PCH_RX_OBJ_NUM 26
96#define PCH_TX_OBJ_NUM 6
97#define PCH_RX_OBJ_START 1
98#define PCH_RX_OBJ_END PCH_RX_OBJ_NUM
99#define PCH_TX_OBJ_START (PCH_RX_OBJ_END + 1)
100#define PCH_TX_OBJ_END (PCH_RX_OBJ_NUM + PCH_TX_OBJ_NUM)
b21d18b5
MO		 101
102#define PCH_FIFO_THRESH 16
103
76d94b23
T		 104/* TxRqst2 show status of MsgObjNo.17~32 */
105#define PCH_TREQ2_TX_MASK (((1 << PCH_TX_OBJ_NUM) - 1) <<\
106 (PCH_RX_OBJ_END - 16))
107
8339a7ed
T		 108enum pch_ifreg {
109 PCH_RX_IFREG,
110 PCH_TX_IFREG,
111};
112
d68f6837
T		 113enum pch_can_err {
114 PCH_STUF_ERR = 1,
115 PCH_FORM_ERR,
116 PCH_ACK_ERR,
117 PCH_BIT1_ERR,
118 PCH_BIT0_ERR,
119 PCH_CRC_ERR,
120 PCH_LEC_ALL,
121};
122
b21d18b5
MO		 123enum pch_can_mode {
124 PCH_CAN_ENABLE,
125 PCH_CAN_DISABLE,
126 PCH_CAN_ALL,
127 PCH_CAN_NONE,
128 PCH_CAN_STOP,
129 PCH_CAN_RUN
130};
131
8339a7ed
T		 132struct pch_can_if_regs {
133 u32 creq;
134 u32 cmask;
135 u32 mask1;
136 u32 mask2;
137 u32 id1;
138 u32 id2;
139 u32 mcont;
8ac9702b 140 u32 data[4];
8339a7ed
T		 141 u32 rsv[13];
142};
143
b21d18b5
MO		 144struct pch_can_regs {
145 u32 cont;
146 u32 stat;
147 u32 errc;
148 u32 bitt;
149 u32 intr;
150 u32 opt;
151 u32 brpe;
8339a7ed
T		 152 u32 reserve;
153 struct pch_can_if_regs ifregs[2]; /* [0]=if1 [1]=if2 */
154 u32 reserve1[8];
b21d18b5
MO		 155 u32 treq1;
156 u32 treq2;
8339a7ed
T		 157 u32 reserve2[6];
158 u32 data1;
159 u32 data2;
160 u32 reserve3[6];
161 u32 canipend1;
162 u32 canipend2;
163 u32 reserve4[6];
164 u32 canmval1;
165 u32 canmval2;
166 u32 reserve5[37];
b21d18b5
MO		 167 u32 srst;
168};
169
170struct pch_can_priv {
171 struct can_priv can;
b21d18b5 172 struct pci_dev *dev;
bd58cbc3
T		 173 u32 tx_enable[PCH_TX_OBJ_END];
174 u32 rx_enable[PCH_TX_OBJ_END];
175 u32 rx_link[PCH_TX_OBJ_END];
176 u32 int_enables;
b21d18b5 177 struct net_device *ndev;
b21d18b5
MO		 178 struct pch_can_regs __iomem *regs;
179 struct napi_struct napi;
bd58cbc3
T		 180 int tx_obj; /* Point next Tx Obj index */
181 int use_msi;
b21d18b5
MO		 182};
183
184static struct can_bittiming_const pch_can_bittiming_const = {
185 .name = KBUILD_MODNAME,
186 .tseg1_min = 1,
187 .tseg1_max = 16,
188 .tseg2_min = 1,
189 .tseg2_max = 8,
190 .sjw_max = 4,
191 .brp_min = 1,
192 .brp_max = 1024, /* 6bit + extended 4bit */
193 .brp_inc = 1,
194};
195
196static DEFINE_PCI_DEVICE_TABLE(pch_pci_tbl) = {
197 {PCI_VENDOR_ID_INTEL, 0x8818, PCI_ANY_ID, PCI_ANY_ID,},
198 {0,}
199};
200MODULE_DEVICE_TABLE(pci, pch_pci_tbl);
201
526de53c 202static inline void pch_can_bit_set(void __iomem *addr, u32 mask)
b21d18b5
MO		 203{
204 iowrite32(ioread32(addr) | mask, addr);
205}
206
526de53c 207static inline void pch_can_bit_clear(void __iomem *addr, u32 mask)
b21d18b5
MO		 208{
209 iowrite32(ioread32(addr) & ~mask, addr);
210}
211
212static void pch_can_set_run_mode(struct pch_can_priv *priv,
213 enum pch_can_mode mode)
214{
215 switch (mode) {
216 case PCH_CAN_RUN:
086b5650 217 pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_INIT);
b21d18b5
MO		 218 break;
219
220 case PCH_CAN_STOP:
086b5650 221 pch_can_bit_set(&priv->regs->cont, PCH_CTRL_INIT);
b21d18b5
MO		 222 break;
223
224 default:
225 dev_err(&priv->ndev->dev, "%s -> Invalid Mode.\n", __func__);
226 break;
227 }
228}
229
230static void pch_can_set_optmode(struct pch_can_priv *priv)
231{
232 u32 reg_val = ioread32(&priv->regs->opt);
233
234 if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
086b5650 235 reg_val |= PCH_OPT_SILENT;
b21d18b5
MO		 236
237 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
086b5650 238 reg_val |= PCH_OPT_LBACK;
b21d18b5 239
086b5650 240 pch_can_bit_set(&priv->regs->cont, PCH_CTRL_OPT);
b21d18b5
MO		 241 iowrite32(reg_val, &priv->regs->opt);
242}
243
bd58cbc3
T		 244static void pch_can_rw_msg_obj(void __iomem *creq_addr, u32 num)
245{
246 int counter = PCH_COUNTER_LIMIT;
247 u32 ifx_creq;
248
249 iowrite32(num, creq_addr);
250 while (counter) {
251 ifx_creq = ioread32(creq_addr) & PCH_IF_CREQ_BUSY;
252 if (!ifx_creq)
253 break;
254 counter--;
255 udelay(1);
256 }
257 if (!counter)
258 pr_err("%s:IF1 BUSY Flag is set forever.\n", __func__);
259}
260
b21d18b5
MO		 261static void pch_can_set_int_enables(struct pch_can_priv *priv,
262 enum pch_can_mode interrupt_no)
263{
264 switch (interrupt_no) {
b21d18b5 265 case PCH_CAN_DISABLE:
086b5650 266 pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_IE);
b21d18b5
MO		 267 break;
268
269 case PCH_CAN_ALL:
086b5650 270 pch_can_bit_set(&priv->regs->cont, PCH_CTRL_IE_SIE_EIE);
b21d18b5
MO		 271 break;
272
273 case PCH_CAN_NONE:
086b5650 274 pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_IE_SIE_EIE);
b21d18b5
MO		 275 break;
276
277 default:
278 dev_err(&priv->ndev->dev, "Invalid interrupt number.\n");
279 break;
280 }
281}
282
8339a7ed 283static void pch_can_set_rxtx(struct pch_can_priv *priv, u32 buff_num,
bd58cbc3 284 int set, enum pch_ifreg dir)
b21d18b5 285{
8339a7ed
T		 286 u32 ie;
287
288 if (dir)
289 ie = PCH_IF_MCONT_TXIE;
290 else
291 ie = PCH_IF_MCONT_RXIE;
b21d18b5 292
b21d18b5 293 /* Reading the receive buffer data from RAM to Interface1 registers */
8339a7ed 294 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[dir].cmask);
bd58cbc3 295 pch_can_rw_msg_obj(&priv->regs->ifregs[dir].creq, buff_num);
b21d18b5
MO		 296
297 /* Setting the IF1MASK1 register to access MsgVal and RxIE bits */
086b5650 298 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_ARB | PCH_CMASK_CTRL,
8339a7ed 299 &priv->regs->ifregs[dir].cmask);
b21d18b5 300
bd58cbc3 301 if (set) {
b21d18b5 302 /* Setting the MsgVal and RxIE bits */
8339a7ed
T		 303 pch_can_bit_set(&priv->regs->ifregs[dir].mcont, ie);
304 pch_can_bit_set(&priv->regs->ifregs[dir].id2, PCH_ID_MSGVAL);
b21d18b5 305
bd58cbc3 306 } else {
b21d18b5 307 /* Resetting the MsgVal and RxIE bits */
8339a7ed
T		 308 pch_can_bit_clear(&priv->regs->ifregs[dir].mcont, ie);
309 pch_can_bit_clear(&priv->regs->ifregs[dir].id2, PCH_ID_MSGVAL);
b21d18b5
MO		 310 }
311
bd58cbc3 312 pch_can_rw_msg_obj(&priv->regs->ifregs[dir].creq, buff_num);
b21d18b5
MO		 313}
314
bd58cbc3 315static void pch_can_set_rx_all(struct pch_can_priv *priv, int set)
b21d18b5
MO		 316{
317 int i;
318
319 /* Traversing to obtain the object configured as receivers. */
15ffc8fd
T		 320 for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++)
321 pch_can_set_rxtx(priv, i, set, PCH_RX_IFREG);
b21d18b5
MO		 322}
323
bd58cbc3 324static void pch_can_set_tx_all(struct pch_can_priv *priv, int set)
b21d18b5
MO		 325{
326 int i;
327
328 /* Traversing to obtain the object configured as transmit object. */
15ffc8fd
T		 329 for (i = PCH_TX_OBJ_START; i <= PCH_TX_OBJ_END; i++)
330 pch_can_set_rxtx(priv, i, set, PCH_TX_IFREG);
b21d18b5
MO		 331}
332
bd58cbc3 333static u32 pch_can_int_pending(struct pch_can_priv *priv)
b21d18b5
MO		 334{
335 return ioread32(&priv->regs->intr) & 0xffff;
336}
337
bd58cbc3 338static void pch_can_clear_if_buffers(struct pch_can_priv *priv)
b21d18b5 339{
bd58cbc3 340 int i; /* Msg Obj ID (1~32) */
b21d18b5 341
bd58cbc3 342 for (i = PCH_RX_OBJ_START; i <= PCH_TX_OBJ_END; i++) {
8339a7ed
T		 343 iowrite32(PCH_CMASK_RX_TX_SET, &priv->regs->ifregs[0].cmask);
344 iowrite32(0xffff, &priv->regs->ifregs[0].mask1);
345 iowrite32(0xffff, &priv->regs->ifregs[0].mask2);
346 iowrite32(0x0, &priv->regs->ifregs[0].id1);
347 iowrite32(0x0, &priv->regs->ifregs[0].id2);
348 iowrite32(0x0, &priv->regs->ifregs[0].mcont);
8ac9702b
T		 349 iowrite32(0x0, &priv->regs->ifregs[0].data[0]);
350 iowrite32(0x0, &priv->regs->ifregs[0].data[1]);
351 iowrite32(0x0, &priv->regs->ifregs[0].data[2]);
352 iowrite32(0x0, &priv->regs->ifregs[0].data[3]);
086b5650
T		 353 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_MASK |
354 PCH_CMASK_ARB | PCH_CMASK_CTRL,
8339a7ed 355 &priv->regs->ifregs[0].cmask);
bd58cbc3 356 pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, i);
b21d18b5
MO		 357 }
358}
359
360static void pch_can_config_rx_tx_buffers(struct pch_can_priv *priv)
361{
362 int i;
b21d18b5 363
15ffc8fd
T		 364 for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++) {
365 iowrite32(PCH_CMASK_RX_TX_GET,
366 &priv->regs->ifregs[0].cmask);
bd58cbc3 367 pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, i);
b21d18b5 368
15ffc8fd
T		 369 iowrite32(0x0, &priv->regs->ifregs[0].id1);
370 iowrite32(0x0, &priv->regs->ifregs[0].id2);
b21d18b5 371
15ffc8fd
T		 372 pch_can_bit_set(&priv->regs->ifregs[0].mcont,
373 PCH_IF_MCONT_UMASK);
b21d18b5 374
15ffc8fd
T		 375 /* In case FIFO mode, Last EoB of Rx Obj must be 1 */
376 if (i == PCH_RX_OBJ_END)
377 pch_can_bit_set(&priv->regs->ifregs[0].mcont,
bd58cbc3
T		 378 PCH_IF_MCONT_EOB);
379 else
380 pch_can_bit_clear(&priv->regs->ifregs[0].mcont,
086b5650 381 PCH_IF_MCONT_EOB);
b21d18b5 382
15ffc8fd
T		 383 iowrite32(0, &priv->regs->ifregs[0].mask1);
384 pch_can_bit_clear(&priv->regs->ifregs[0].mask2,
385 0x1fff | PCH_MASK2_MDIR_MXTD);
b21d18b5 386
15ffc8fd
T		 387 /* Setting CMASK for writing */
388 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_MASK |
389 PCH_CMASK_ARB | PCH_CMASK_CTRL,
390 &priv->regs->ifregs[0].cmask);
b21d18b5 391
bd58cbc3 392 pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, i);
15ffc8fd 393 }
b21d18b5 394
15ffc8fd
T		 395 for (i = PCH_TX_OBJ_START; i <= PCH_TX_OBJ_END; i++) {
396 iowrite32(PCH_CMASK_RX_TX_GET,
397 &priv->regs->ifregs[1].cmask);
bd58cbc3 398 pch_can_rw_msg_obj(&priv->regs->ifregs[1].creq, i);
b21d18b5 399
15ffc8fd
T		 400 /* Resetting DIR bit for reception */
401 iowrite32(0x0, &priv->regs->ifregs[1].id1);
44c9aa89 402 iowrite32(PCH_ID2_DIR, &priv->regs->ifregs[1].id2);
b21d18b5 403
15ffc8fd 404 /* Setting EOB bit for transmitter */
44c9aa89
T		 405 iowrite32(PCH_IF_MCONT_EOB | PCH_IF_MCONT_UMASK,
406 &priv->regs->ifregs[1].mcont);
15ffc8fd
T		 407
408 iowrite32(0, &priv->regs->ifregs[1].mask1);
409 pch_can_bit_clear(&priv->regs->ifregs[1].mask2, 0x1fff);
410
411 /* Setting CMASK for writing */
412 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_MASK |
413 PCH_CMASK_ARB | PCH_CMASK_CTRL,
414 &priv->regs->ifregs[1].cmask);
415
bd58cbc3 416 pch_can_rw_msg_obj(&priv->regs->ifregs[1].creq, i);
b21d18b5 417 }
b21d18b5
MO		 418}
419
420static void pch_can_init(struct pch_can_priv *priv)
421{
422 /* Stopping the Can device. */
423 pch_can_set_run_mode(priv, PCH_CAN_STOP);
424
425 /* Clearing all the message object buffers. */
bd58cbc3 426 pch_can_clear_if_buffers(priv);
b21d18b5
MO		 427
428 /* Configuring the respective message object as either rx/tx object. */
429 pch_can_config_rx_tx_buffers(priv);
430
431 /* Enabling the interrupts. */
432 pch_can_set_int_enables(priv, PCH_CAN_ALL);
433}
434
435static void pch_can_release(struct pch_can_priv *priv)
436{
437 /* Stooping the CAN device. */
438 pch_can_set_run_mode(priv, PCH_CAN_STOP);
439
440 /* Disabling the interrupts. */
441 pch_can_set_int_enables(priv, PCH_CAN_NONE);
442
443 /* Disabling all the receive object. */
8339a7ed 444 pch_can_set_rx_all(priv, 0);
b21d18b5
MO		 445
446 /* Disabling all the transmit object. */
8339a7ed 447 pch_can_set_tx_all(priv, 0);
b21d18b5
MO		 448}
449
450/* This function clears interrupt(s) from the CAN device. */
451static void pch_can_int_clr(struct pch_can_priv *priv, u32 mask)
452{
086b5650 453 if (mask == PCH_STATUS_INT) {
b21d18b5
MO		 454 ioread32(&priv->regs->stat);
455 return;
456 }
457
458 /* Clear interrupt for transmit object */
15ffc8fd
T		 459 if ((mask >= PCH_RX_OBJ_START) && (mask <= PCH_RX_OBJ_END)) {
460 /* Setting CMASK for clearing the reception interrupts. */
461 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL | PCH_CMASK_ARB,
462 &priv->regs->ifregs[0].cmask);
463
464 /* Clearing the Dir bit. */
465 pch_can_bit_clear(&priv->regs->ifregs[0].id2, PCH_ID2_DIR);
466
467 /* Clearing NewDat & IntPnd */
468 pch_can_bit_clear(&priv->regs->ifregs[0].mcont,
469 PCH_IF_MCONT_NEWDAT | PCH_IF_MCONT_INTPND);
470
bd58cbc3 471 pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, mask);
15ffc8fd 472 } else if ((mask >= PCH_TX_OBJ_START) && (mask <= PCH_TX_OBJ_END)) {
b21d18b5
MO		 473 /* Setting CMASK for clearing interrupts for
474 frame transmission. */
086b5650 475 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL | PCH_CMASK_ARB,
8339a7ed 476 &priv->regs->ifregs[1].cmask);
b21d18b5
MO		 477
478 /* Resetting the ID registers. */
8339a7ed 479 pch_can_bit_set(&priv->regs->ifregs[1].id2,
086b5650 480 PCH_ID2_DIR | (0x7ff << 2));
8339a7ed 481 iowrite32(0x0, &priv->regs->ifregs[1].id1);
b21d18b5
MO		 482
483 /* Claring NewDat, TxRqst & IntPnd */
8339a7ed 484 pch_can_bit_clear(&priv->regs->ifregs[1].mcont,
086b5650
T		 485 PCH_IF_MCONT_NEWDAT | PCH_IF_MCONT_INTPND |
486 PCH_IF_MCONT_TXRQXT);
bd58cbc3 487 pch_can_rw_msg_obj(&priv->regs->ifregs[1].creq, mask);
b21d18b5
MO		 488 }
489}
490
b21d18b5
MO		 491static void pch_can_reset(struct pch_can_priv *priv)
492{
493 /* write to sw reset register */
494 iowrite32(1, &priv->regs->srst);
495 iowrite32(0, &priv->regs->srst);
496}
497
498static void pch_can_error(struct net_device *ndev, u32 status)
499{
500 struct sk_buff *skb;
501 struct pch_can_priv *priv = netdev_priv(ndev);
502 struct can_frame *cf;
d68f6837 503 u32 errc, lec;
b21d18b5
MO		 504 struct net_device_stats *stats = &(priv->ndev->stats);
505 enum can_state state = priv->can.state;
506
507 skb = alloc_can_err_skb(ndev, &cf);
508 if (!skb)
509 return;
510
511 if (status & PCH_BUS_OFF) {
8339a7ed
T		 512 pch_can_set_tx_all(priv, 0);
513 pch_can_set_rx_all(priv, 0);
b21d18b5
MO		 514 state = CAN_STATE_BUS_OFF;
515 cf->can_id |= CAN_ERR_BUSOFF;
516 can_bus_off(ndev);
517 pch_can_set_run_mode(priv, PCH_CAN_RUN);
518 dev_err(&ndev->dev, "%s -> Bus Off occurres.\n", __func__);
519 }
520
44c9aa89 521 errc = ioread32(&priv->regs->errc);
b21d18b5
MO		 522 /* Warning interrupt. */
523 if (status & PCH_EWARN) {
524 state = CAN_STATE_ERROR_WARNING;
525 priv->can.can_stats.error_warning++;
526 cf->can_id |= CAN_ERR_CRTL;
086b5650 527 if (((errc & PCH_REC) >> 8) > 96)
b21d18b5 528 cf->data[1] |= CAN_ERR_CRTL_RX_WARNING;
086b5650 529 if ((errc & PCH_TEC) > 96)
b21d18b5
MO		 530 cf->data[1] |= CAN_ERR_CRTL_TX_WARNING;
531 dev_warn(&ndev->dev,
532 "%s -> Error Counter is more than 96.\n", __func__);
533 }
534 /* Error passive interrupt. */
535 if (status & PCH_EPASSIV) {
536 priv->can.can_stats.error_passive++;
537 state = CAN_STATE_ERROR_PASSIVE;
538 cf->can_id |= CAN_ERR_CRTL;
086b5650 539 if (((errc & PCH_REC) >> 8) > 127)
b21d18b5 540 cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE;
086b5650 541 if ((errc & PCH_TEC) > 127)
b21d18b5
MO		 542 cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE;
543 dev_err(&ndev->dev,
544 "%s -> CAN controller is ERROR PASSIVE .\n", __func__);
545 }
546
d68f6837
T		 547 lec = status & PCH_LEC_ALL;
548 switch (lec) {
549 case PCH_STUF_ERR:
550 cf->data[2] |= CAN_ERR_PROT_STUFF;
b21d18b5
MO		 551 priv->can.can_stats.bus_error++;
552 stats->rx_errors++;
d68f6837
T		 553 break;
554 case PCH_FORM_ERR:
555 cf->data[2] |= CAN_ERR_PROT_FORM;
556 priv->can.can_stats.bus_error++;
557 stats->rx_errors++;
558 break;
559 case PCH_ACK_ERR:
560 cf->can_id |= CAN_ERR_ACK;
561 priv->can.can_stats.bus_error++;
562 stats->rx_errors++;
563 break;
564 case PCH_BIT1_ERR:
565 case PCH_BIT0_ERR:
566 cf->data[2] |= CAN_ERR_PROT_BIT;
567 priv->can.can_stats.bus_error++;
568 stats->rx_errors++;
569 break;
570 case PCH_CRC_ERR:
571 cf->data[2] |= CAN_ERR_PROT_LOC_CRC_SEQ |
572 CAN_ERR_PROT_LOC_CRC_DEL;
573 priv->can.can_stats.bus_error++;
574 stats->rx_errors++;
575 break;
576 case PCH_LEC_ALL: /* Written by CPU. No error status */
577 break;
b21d18b5
MO		 578 }
579
580 priv->can.state = state;
581 netif_rx(skb);
582
583 stats->rx_packets++;
584 stats->rx_bytes += cf->can_dlc;
585}
586
587static irqreturn_t pch_can_interrupt(int irq, void *dev_id)
588{
589 struct net_device *ndev = (struct net_device *)dev_id;
590 struct pch_can_priv *priv = netdev_priv(ndev);
591
592 pch_can_set_int_enables(priv, PCH_CAN_NONE);
593
594 napi_schedule(&priv->napi);
595
596 return IRQ_HANDLED;
597}
598
1d5b4b27
T		 599static void pch_fifo_thresh(struct pch_can_priv *priv, int obj_id)
600{
601 if (obj_id < PCH_FIFO_THRESH) {
602 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL |
603 PCH_CMASK_ARB, &priv->regs->ifregs[0].cmask);
604
605 /* Clearing the Dir bit. */
606 pch_can_bit_clear(&priv->regs->ifregs[0].id2, PCH_ID2_DIR);
607
608 /* Clearing NewDat & IntPnd */
609 pch_can_bit_clear(&priv->regs->ifregs[0].mcont,
610 PCH_IF_MCONT_INTPND);
bd58cbc3 611 pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, obj_id);
1d5b4b27
T		 612 } else if (obj_id > PCH_FIFO_THRESH) {
613 pch_can_int_clr(priv, obj_id);
614 } else if (obj_id == PCH_FIFO_THRESH) {
615 int cnt;
616 for (cnt = 0; cnt < PCH_FIFO_THRESH; cnt++)
617 pch_can_int_clr(priv, cnt + 1);
618 }
619}
620
621static void pch_can_rx_msg_lost(struct net_device *ndev, int obj_id)
622{
623 struct pch_can_priv *priv = netdev_priv(ndev);
624 struct net_device_stats *stats = &(priv->ndev->stats);
625 struct sk_buff *skb;
626 struct can_frame *cf;
627
628 netdev_dbg(priv->ndev, "Msg Obj is overwritten.\n");
629 pch_can_bit_clear(&priv->regs->ifregs[0].mcont,
630 PCH_IF_MCONT_MSGLOST);
631 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL,
632 &priv->regs->ifregs[0].cmask);
bd58cbc3 633 pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, obj_id);
1d5b4b27
T		 634
635 skb = alloc_can_err_skb(ndev, &cf);
636 if (!skb)
637 return;
638
639 cf->can_id |= CAN_ERR_CRTL;
640 cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
641 stats->rx_over_errors++;
642 stats->rx_errors++;
643
644 netif_receive_skb(skb);
645}
646
647static int pch_can_rx_normal(struct net_device *ndev, u32 obj_num, int quota)
b21d18b5
MO		 648{
649 u32 reg;
650 canid_t id;
b21d18b5
MO		 651 int rcv_pkts = 0;
652 struct sk_buff *skb;
653 struct can_frame *cf;
654 struct pch_can_priv *priv = netdev_priv(ndev);
655 struct net_device_stats *stats = &(priv->ndev->stats);
1d5b4b27
T		 656 int i;
657 u32 id2;
8ac9702b 658 u16 data_reg;
b21d18b5 659
1d5b4b27
T		 660 do {
661 /* Reading the messsage object from the Message RAM */
662 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask);
bd58cbc3 663 pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, obj_num);
b21d18b5 664
1d5b4b27
T		 665 /* Reading the MCONT register. */
666 reg = ioread32(&priv->regs->ifregs[0].mcont);
667
668 if (reg & PCH_IF_MCONT_EOB)
669 break;
b21d18b5 670
b21d18b5 671 /* If MsgLost bit set. */
086b5650 672 if (reg & PCH_IF_MCONT_MSGLOST) {
1d5b4b27 673 pch_can_rx_msg_lost(ndev, obj_num);
b21d18b5 674 rcv_pkts++;
1d5b4b27
T		 675 quota--;
676 obj_num++;
677 continue;
678 } else if (!(reg & PCH_IF_MCONT_NEWDAT)) {
679 obj_num++;
680 continue;
b21d18b5 681 }
b21d18b5
MO		 682
683 skb = alloc_can_skb(priv->ndev, &cf);
684 if (!skb)
685 return -ENOMEM;
686
687 /* Get Received data */
1d5b4b27
T		 688 id2 = ioread32(&priv->regs->ifregs[0].id2);
689 if (id2 & PCH_ID2_XTD) {
8339a7ed 690 id = (ioread32(&priv->regs->ifregs[0].id1) & 0xffff);
1d5b4b27
T		 691 id |= (((id2) & 0x1fff) << 16);
692 cf->can_id = id | CAN_EFF_FLAG;
b21d18b5 693 } else {
1d5b4b27
T		 694 id = (id2 >> 2) & CAN_SFF_MASK;
695 cf->can_id = id;
b21d18b5
MO		 696 }
697
1d5b4b27 698 if (id2 & PCH_ID2_DIR)
b21d18b5 699 cf->can_id |= CAN_RTR_FLAG;
1d5b4b27
T		 700
701 cf->can_dlc = get_can_dlc((ioread32(&priv->regs->
702 ifregs[0].mcont)) & 0xF);
b21d18b5 703
8ac9702b
T		 704 for (i = 0; i < cf->can_dlc; i += 2) {
705 data_reg = ioread16(&priv->regs->ifregs[0].data[i / 2]);
706 cf->data[i] = data_reg;
707 cf->data[i + 1] = data_reg >> 8;
b21d18b5
MO		 708 }
709
710 netif_receive_skb(skb);
711 rcv_pkts++;
712 stats->rx_packets++;
1d5b4b27 713 quota--;
b21d18b5
MO		 714 stats->rx_bytes += cf->can_dlc;
715
1d5b4b27
T		 716 pch_fifo_thresh(priv, obj_num);
717 obj_num++;
718 } while (quota > 0);
b21d18b5
MO		 719
720 return rcv_pkts;
721}
e489cceb
T		 722
723static void pch_can_tx_complete(struct net_device *ndev, u32 int_stat)
b21d18b5 724{
b21d18b5
MO		 725 struct pch_can_priv *priv = netdev_priv(ndev);
726 struct net_device_stats *stats = &(priv->ndev->stats);
727 u32 dlc;
e489cceb
T		 728
729 can_get_echo_skb(ndev, int_stat - PCH_RX_OBJ_END - 1);
730 iowrite32(PCH_CMASK_RX_TX_GET | PCH_CMASK_CLRINTPND,
731 &priv->regs->ifregs[1].cmask);
bd58cbc3 732 pch_can_rw_msg_obj(&priv->regs->ifregs[1].creq, int_stat);
e489cceb
T		 733 dlc = get_can_dlc(ioread32(&priv->regs->ifregs[1].mcont) &
734 PCH_IF_MCONT_DLC);
735 stats->tx_bytes += dlc;
736 stats->tx_packets++;
737 if (int_stat == PCH_TX_OBJ_END)
738 netif_wake_queue(ndev);
739}
740
bd58cbc3 741static int pch_can_poll(struct napi_struct *napi, int quota)
e489cceb
T		 742{
743 struct net_device *ndev = napi->dev;
744 struct pch_can_priv *priv = netdev_priv(ndev);
b21d18b5
MO		 745 u32 int_stat;
746 int rcv_pkts = 0;
747 u32 reg_stat;
b21d18b5
MO		 748
749 int_stat = pch_can_int_pending(priv);
750 if (!int_stat)
e489cceb 751 goto end;
b21d18b5 752
e489cceb 753 if ((int_stat == PCH_STATUS_INT) && (quota > 0)) {
b21d18b5
MO		 754 reg_stat = ioread32(&priv->regs->stat);
755 if (reg_stat & (PCH_BUS_OFF | PCH_LEC_ALL)) {
e489cceb
T		 756 if (reg_stat & PCH_BUS_OFF ||
757 (reg_stat & PCH_LEC_ALL) != PCH_LEC_ALL) {
b21d18b5 758 pch_can_error(ndev, reg_stat);
e489cceb
T		 759 quota--;
760 }
b21d18b5
MO		 761 }
762
e489cceb 763 if (reg_stat & PCH_TX_OK)
b21d18b5 764 pch_can_bit_clear(&priv->regs->stat, PCH_TX_OK);
b21d18b5
MO		 765
766 if (reg_stat & PCH_RX_OK)
767 pch_can_bit_clear(&priv->regs->stat, PCH_RX_OK);
768
769 int_stat = pch_can_int_pending(priv);
b21d18b5
MO		 770 }
771
e489cceb
T		 772 if (quota == 0)
773 goto end;
774
15ffc8fd 775 if ((int_stat >= PCH_RX_OBJ_START) && (int_stat <= PCH_RX_OBJ_END)) {
1d5b4b27 776 rcv_pkts += pch_can_rx_normal(ndev, int_stat, quota);
e489cceb
T		 777 quota -= rcv_pkts;
778 if (quota < 0)
779 goto end;
15ffc8fd
T		 780 } else if ((int_stat >= PCH_TX_OBJ_START) &&
781 (int_stat <= PCH_TX_OBJ_END)) {
782 /* Handle transmission interrupt */
e489cceb 783 pch_can_tx_complete(ndev, int_stat);
b21d18b5
MO		 784 }
785
e489cceb 786end:
b21d18b5
MO		 787 napi_complete(napi);
788 pch_can_set_int_enables(priv, PCH_CAN_ALL);
789
790 return rcv_pkts;
791}
792
793static int pch_set_bittiming(struct net_device *ndev)
794{
795 struct pch_can_priv *priv = netdev_priv(ndev);
796 const struct can_bittiming *bt = &priv->can.bittiming;
797 u32 canbit;
798 u32 bepe;
799 u32 brp;
800
801 /* Setting the CCE bit for accessing the Can Timing register. */
086b5650 802 pch_can_bit_set(&priv->regs->cont, PCH_CTRL_CCE);
b21d18b5
MO		 803
804 brp = (bt->tq) / (1000000000/PCH_CAN_CLK) - 1;
086b5650 805 canbit = brp & PCH_MSK_BITT_BRP;
bd58cbc3
T		 806 canbit |= (bt->sjw - 1) << PCH_BIT_SJW_SHIFT;
807 canbit |= (bt->phase_seg1 + bt->prop_seg - 1) << PCH_BIT_TSEG1_SHIFT;
808 canbit |= (bt->phase_seg2 - 1) << PCH_BIT_TSEG2_SHIFT;
809 bepe = (brp & PCH_MSK_BRPE_BRPE) >> PCH_BIT_BRPE_BRPE_SHIFT;
b21d18b5
MO		 810 iowrite32(canbit, &priv->regs->bitt);
811 iowrite32(bepe, &priv->regs->brpe);
086b5650 812 pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_CCE);
b21d18b5
MO		 813
814 return 0;
815}
816
817static void pch_can_start(struct net_device *ndev)
818{
819 struct pch_can_priv *priv = netdev_priv(ndev);
820
821 if (priv->can.state != CAN_STATE_STOPPED)
822 pch_can_reset(priv);
823
824 pch_set_bittiming(ndev);
825 pch_can_set_optmode(priv);
826
8339a7ed
T		 827 pch_can_set_tx_all(priv, 1);
828 pch_can_set_rx_all(priv, 1);
b21d18b5
MO		 829
830 /* Setting the CAN to run mode. */
831 pch_can_set_run_mode(priv, PCH_CAN_RUN);
832
833 priv->can.state = CAN_STATE_ERROR_ACTIVE;
834
835 return;
836}
837
838static int pch_can_do_set_mode(struct net_device *ndev, enum can_mode mode)
839{
840 int ret = 0;
841
842 switch (mode) {
843 case CAN_MODE_START:
844 pch_can_start(ndev);
845 netif_wake_queue(ndev);
846 break;
847 default:
848 ret = -EOPNOTSUPP;
849 break;
850 }
851
852 return ret;
853}
854
855static int pch_can_open(struct net_device *ndev)
856{
857 struct pch_can_priv *priv = netdev_priv(ndev);
858 int retval;
859
860 retval = pci_enable_msi(priv->dev);
861 if (retval) {
862 dev_info(&ndev->dev, "PCH CAN opened without MSI\n");
863 priv->use_msi = 0;
864 } else {
865 dev_info(&ndev->dev, "PCH CAN opened with MSI\n");
866 priv->use_msi = 1;
867 }
868
869 /* Regsitering the interrupt. */
870 retval = request_irq(priv->dev->irq, pch_can_interrupt, IRQF_SHARED,
871 ndev->name, ndev);
872 if (retval) {
873 dev_err(&ndev->dev, "request_irq failed.\n");
874 goto req_irq_err;
875 }
876
877 /* Open common can device */
878 retval = open_candev(ndev);
879 if (retval) {
880 dev_err(ndev->dev.parent, "open_candev() failed %d\n", retval);
881 goto err_open_candev;
882 }
883
884 pch_can_init(priv);
885 pch_can_start(ndev);
886 napi_enable(&priv->napi);
887 netif_start_queue(ndev);
888
889 return 0;
890
891err_open_candev:
892 free_irq(priv->dev->irq, ndev);
893req_irq_err:
894 if (priv->use_msi)
895 pci_disable_msi(priv->dev);
896
897 pch_can_release(priv);
898
899 return retval;
900}
901
902static int pch_close(struct net_device *ndev)
903{
904 struct pch_can_priv *priv = netdev_priv(ndev);
905
906 netif_stop_queue(ndev);
907 napi_disable(&priv->napi);
908 pch_can_release(priv);
909 free_irq(priv->dev->irq, ndev);
910 if (priv->use_msi)
911 pci_disable_msi(priv->dev);
912 close_candev(ndev);
913 priv->can.state = CAN_STATE_STOPPED;
914 return 0;
915}
916
b21d18b5
MO		 917static netdev_tx_t pch_xmit(struct sk_buff *skb, struct net_device *ndev)
918{
b21d18b5
MO		 919 struct pch_can_priv *priv = netdev_priv(ndev);
920 struct can_frame *cf = (struct can_frame *)skb->data;
bd58cbc3 921 int tx_obj_no;
8ac9702b 922 int i;
44c9aa89 923 u32 id2;
b21d18b5
MO		 924
925 if (can_dropped_invalid_skb(ndev, skb))
926 return NETDEV_TX_OK;
927
76d94b23
T		 928 if (priv->tx_obj == PCH_TX_OBJ_END) {
929 if (ioread32(&priv->regs->treq2) & PCH_TREQ2_TX_MASK)
930 netif_stop_queue(ndev);
b21d18b5 931
bd58cbc3 932 tx_obj_no = priv->tx_obj;
76d94b23 933 priv->tx_obj = PCH_TX_OBJ_START;
b21d18b5 934 } else {
bd58cbc3 935 tx_obj_no = priv->tx_obj;
76d94b23 936 priv->tx_obj++;
b21d18b5 937 }
b21d18b5 938
b21d18b5 939 /* Reading the Msg Obj from the Msg RAM to the Interface register. */
8339a7ed 940 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[1].cmask);
bd58cbc3 941 pch_can_rw_msg_obj(&priv->regs->ifregs[1].creq, tx_obj_no);
b21d18b5
MO		 942
943 /* Setting the CMASK register. */
8339a7ed 944 pch_can_bit_set(&priv->regs->ifregs[1].cmask, PCH_CMASK_ALL);
b21d18b5
MO		 945
946 /* If ID extended is set. */
b21d18b5 947 if (cf->can_id & CAN_EFF_FLAG) {
44c9aa89
T		 948 iowrite32(cf->can_id & 0xffff, &priv->regs->ifregs[1].id1);
949 id2 = ((cf->can_id >> 16) & 0x1fff) | PCH_ID2_XTD;
b21d18b5 950 } else {
44c9aa89
T		 951 iowrite32(0, &priv->regs->ifregs[1].id1);
952 id2 = (cf->can_id & CAN_SFF_MASK) << 2;
b21d18b5
MO		 953 }
954
44c9aa89
T		 955 id2 |= PCH_ID_MSGVAL;
956
b21d18b5
MO		 957 /* If remote frame has to be transmitted.. */
958 if (cf->can_id & CAN_RTR_FLAG)
44c9aa89
T		 959 id2 &= ~PCH_ID2_DIR;
960 else
961 id2 |= PCH_ID2_DIR;
962
963 iowrite32(id2, &priv->regs->ifregs[1].id2);
b21d18b5 964
8ac9702b
T		 965 /* Copy data to register */
966 for (i = 0; i < cf->can_dlc; i += 2) {
967 iowrite16(cf->data[i] | (cf->data[i + 1] << 8),
968 &priv->regs->ifregs[1].data[i / 2]);
b21d18b5
MO		 969 }
970
bd58cbc3 971 can_put_echo_skb(skb, ndev, tx_obj_no - PCH_RX_OBJ_END - 1);
b21d18b5
MO		 972
973 /* Updating the size of the data. */
44c9aa89
T		 974 iowrite32(cf->can_dlc | PCH_IF_MCONT_NEWDAT | PCH_IF_MCONT_TXRQXT |
975 PCH_IF_MCONT_TXIE, &priv->regs->ifregs[1].mcont);
b21d18b5 976
bd58cbc3 977 pch_can_rw_msg_obj(&priv->regs->ifregs[1].creq, tx_obj_no);
b21d18b5 978
b21d18b5
MO		 979 return NETDEV_TX_OK;
980}
981
982static const struct net_device_ops pch_can_netdev_ops = {
983 .ndo_open = pch_can_open,
984 .ndo_stop = pch_close,
985 .ndo_start_xmit = pch_xmit,
986};
987
988static void __devexit pch_can_remove(struct pci_dev *pdev)
989{
990 struct net_device *ndev = pci_get_drvdata(pdev);
991 struct pch_can_priv *priv = netdev_priv(ndev);
992
993 unregister_candev(priv->ndev);
994 free_candev(priv->ndev);
995 pci_iounmap(pdev, priv->regs);
996 pci_release_regions(pdev);
997 pci_disable_device(pdev);
998 pci_set_drvdata(pdev, NULL);
999 pch_can_reset(priv);
1000}
1001
1002#ifdef CONFIG_PM
7f2bc50e
T		 1003static void pch_can_set_int_custom(struct pch_can_priv *priv)
1004{
1005 /* Clearing the IE, SIE and EIE bits of Can control register. */
1006 pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_IE_SIE_EIE);
1007
1008 /* Appropriately setting them. */
1009 pch_can_bit_set(&priv->regs->cont,
1010 ((priv->int_enables & PCH_MSK_CTRL_IE_SIE_EIE) << 1));
1011}
1012
1013/* This function retrieves interrupt enabled for the CAN device. */
ca2b004e 1014static u32 pch_can_get_int_enables(struct pch_can_priv *priv)
7f2bc50e
T		 1015{
1016 /* Obtaining the status of IE, SIE and EIE interrupt bits. */
ca2b004e 1017 return (ioread32(&priv->regs->cont) & PCH_CTRL_IE_SIE_EIE) >> 1;
7f2bc50e
T		 1018}
1019
1020static u32 pch_can_get_rxtx_ir(struct pch_can_priv *priv, u32 buff_num,
1021 enum pch_ifreg dir)
1022{
1023 u32 ie, enable;
1024
1025 if (dir)
1026 ie = PCH_IF_MCONT_RXIE;
1027 else
1028 ie = PCH_IF_MCONT_TXIE;
1029
1030 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[dir].cmask);
bd58cbc3 1031 pch_can_rw_msg_obj(&priv->regs->ifregs[dir].creq, buff_num);
7f2bc50e
T		 1032
1033 if (((ioread32(&priv->regs->ifregs[dir].id2)) & PCH_ID_MSGVAL) &&
1034 ((ioread32(&priv->regs->ifregs[dir].mcont)) & ie)) {
1035 enable = 1;
1036 } else {
1037 enable = 0;
1038 }
1039 return enable;
1040}
1041
1042static void pch_can_set_rx_buffer_link(struct pch_can_priv *priv,
bd58cbc3 1043 u32 buffer_num, int set)
7f2bc50e
T		 1044{
1045 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask);
bd58cbc3 1046 pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, buffer_num);
7f2bc50e
T		 1047 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL,
1048 &priv->regs->ifregs[0].cmask);
bd58cbc3 1049 if (set)
7f2bc50e
T		 1050 pch_can_bit_clear(&priv->regs->ifregs[0].mcont,
1051 PCH_IF_MCONT_EOB);
1052 else
1053 pch_can_bit_set(&priv->regs->ifregs[0].mcont, PCH_IF_MCONT_EOB);
1054
bd58cbc3 1055 pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, buffer_num);
7f2bc50e
T		 1056}
1057
ca2b004e 1058static u32 pch_can_get_rx_buffer_link(struct pch_can_priv *priv, u32 buffer_num)
7f2bc50e 1059{
ca2b004e
T		 1060 u32 link;
1061
7f2bc50e 1062 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask);
bd58cbc3 1063 pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, buffer_num);
7f2bc50e
T		 1064
1065 if (ioread32(&priv->regs->ifregs[0].mcont) & PCH_IF_MCONT_EOB)
ca2b004e 1066 link = 0;
7f2bc50e 1067 else
ca2b004e
T		 1068 link = 1;
1069 return link;
7f2bc50e
T		 1070}
1071
1072static int pch_can_get_buffer_status(struct pch_can_priv *priv)
1073{
1074 return (ioread32(&priv->regs->treq1) & 0xffff) |
bd58cbc3 1075 (ioread32(&priv->regs->treq2) << 16);
7f2bc50e
T		 1076}
1077
b21d18b5
MO		 1078static int pch_can_suspend(struct pci_dev *pdev, pm_message_t state)
1079{
1080 int i; /* Counter variable. */
1081 int retval; /* Return value. */
1082 u32 buf_stat; /* Variable for reading the transmit buffer status. */
bd58cbc3 1083 int counter = PCH_COUNTER_LIMIT;
b21d18b5
MO		 1084
1085 struct net_device *dev = pci_get_drvdata(pdev);
1086 struct pch_can_priv *priv = netdev_priv(dev);
1087
1088 /* Stop the CAN controller */
1089 pch_can_set_run_mode(priv, PCH_CAN_STOP);
1090
1091 /* Indicate that we are aboutto/in suspend */
1092 priv->can.state = CAN_STATE_SLEEPING;
1093
1094 /* Waiting for all transmission to complete. */
1095 while (counter) {
1096 buf_stat = pch_can_get_buffer_status(priv);
1097 if (!buf_stat)
1098 break;
1099 counter--;
1100 udelay(1);
1101 }
1102 if (!counter)
1103 dev_err(&pdev->dev, "%s -> Transmission time out.\n", __func__);
1104
1105 /* Save interrupt configuration and then disable them */
ca2b004e 1106 priv->int_enables = pch_can_get_int_enables(priv);
b21d18b5
MO		 1107 pch_can_set_int_enables(priv, PCH_CAN_DISABLE);
1108
1109 /* Save Tx buffer enable state */
15ffc8fd
T		 1110 for (i = PCH_TX_OBJ_START; i <= PCH_TX_OBJ_END; i++)
1111 priv->tx_enable[i] = pch_can_get_rxtx_ir(priv, i, PCH_TX_IFREG);
b21d18b5
MO		 1112
1113 /* Disable all Transmit buffers */
8339a7ed 1114 pch_can_set_tx_all(priv, 0);
b21d18b5
MO		 1115
1116 /* Save Rx buffer enable state */
15ffc8fd
T		 1117 for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++) {
1118 priv->rx_enable[i] = pch_can_get_rxtx_ir(priv, i, PCH_RX_IFREG);
ca2b004e 1119 priv->rx_link[i] = pch_can_get_rx_buffer_link(priv, i);
b21d18b5
MO		 1120 }
1121
1122 /* Disable all Receive buffers */
8339a7ed 1123 pch_can_set_rx_all(priv, 0);
b21d18b5
MO		 1124 retval = pci_save_state(pdev);
1125 if (retval) {
1126 dev_err(&pdev->dev, "pci_save_state failed.\n");
1127 } else {
1128 pci_enable_wake(pdev, PCI_D3hot, 0);
1129 pci_disable_device(pdev);
1130 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1131 }
1132
1133 return retval;
1134}
1135
1136static int pch_can_resume(struct pci_dev *pdev)
1137{
1138 int i; /* Counter variable. */
1139 int retval; /* Return variable. */
1140 struct net_device *dev = pci_get_drvdata(pdev);
1141 struct pch_can_priv *priv = netdev_priv(dev);
1142
1143 pci_set_power_state(pdev, PCI_D0);
1144 pci_restore_state(pdev);
1145 retval = pci_enable_device(pdev);
1146 if (retval) {
1147 dev_err(&pdev->dev, "pci_enable_device failed.\n");
1148 return retval;
1149 }
1150
1151 pci_enable_wake(pdev, PCI_D3hot, 0);
1152
1153 priv->can.state = CAN_STATE_ERROR_ACTIVE;
1154
1155 /* Disabling all interrupts. */
1156 pch_can_set_int_enables(priv, PCH_CAN_DISABLE);
1157
1158 /* Setting the CAN device in Stop Mode. */
1159 pch_can_set_run_mode(priv, PCH_CAN_STOP);
1160
1161 /* Configuring the transmit and receive buffers. */
1162 pch_can_config_rx_tx_buffers(priv);
1163
1164 /* Restore the CAN state */
1165 pch_set_bittiming(dev);
1166
1167 /* Listen/Active */
1168 pch_can_set_optmode(priv);
1169
1170 /* Enabling the transmit buffer. */
15ffc8fd
T		 1171 for (i = PCH_TX_OBJ_START; i <= PCH_TX_OBJ_END; i++)
1172 pch_can_set_rxtx(priv, i, priv->tx_enable[i], PCH_TX_IFREG);
b21d18b5
MO		 1173
1174 /* Configuring the receive buffer and enabling them. */
15ffc8fd
T		 1175 for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++) {
1176 /* Restore buffer link */
1177 pch_can_set_rx_buffer_link(priv, i, priv->rx_link[i]);
b21d18b5 1178
15ffc8fd
T		 1179 /* Restore buffer enables */
1180 pch_can_set_rxtx(priv, i, priv->rx_enable[i], PCH_RX_IFREG);
b21d18b5
MO		 1181 }
1182
1183 /* Enable CAN Interrupts */
1184 pch_can_set_int_custom(priv);
1185
1186 /* Restore Run Mode */
1187 pch_can_set_run_mode(priv, PCH_CAN_RUN);
1188
1189 return retval;
1190}
1191#else
1192#define pch_can_suspend NULL
1193#define pch_can_resume NULL
1194#endif
1195
1196static int pch_can_get_berr_counter(const struct net_device *dev,
1197 struct can_berr_counter *bec)
1198{
1199 struct pch_can_priv *priv = netdev_priv(dev);
44c9aa89 1200 u32 errc = ioread32(&priv->regs->errc);
b21d18b5 1201
44c9aa89
T		 1202 bec->txerr = errc & PCH_TEC;
1203 bec->rxerr = (errc & PCH_REC) >> 8;
b21d18b5
MO		 1204
1205 return 0;
1206}
1207
1208static int __devinit pch_can_probe(struct pci_dev *pdev,
1209 const struct pci_device_id *id)
1210{
1211 struct net_device *ndev;
1212 struct pch_can_priv *priv;
1213 int rc;
b21d18b5
MO		 1214 void __iomem *addr;
1215
1216 rc = pci_enable_device(pdev);
1217 if (rc) {
1218 dev_err(&pdev->dev, "Failed pci_enable_device %d\n", rc);
1219 goto probe_exit_endev;
1220 }
1221
1222 rc = pci_request_regions(pdev, KBUILD_MODNAME);
1223 if (rc) {
1224 dev_err(&pdev->dev, "Failed pci_request_regions %d\n", rc);
1225 goto probe_exit_pcireq;
1226 }
1227
1228 addr = pci_iomap(pdev, 1, 0);
1229 if (!addr) {
1230 rc = -EIO;
1231 dev_err(&pdev->dev, "Failed pci_iomap\n");
1232 goto probe_exit_ipmap;
1233 }
1234
15ffc8fd 1235 ndev = alloc_candev(sizeof(struct pch_can_priv), PCH_TX_OBJ_END);
b21d18b5
MO		 1236 if (!ndev) {
1237 rc = -ENOMEM;
1238 dev_err(&pdev->dev, "Failed alloc_candev\n");
1239 goto probe_exit_alloc_candev;
1240 }
1241
1242 priv = netdev_priv(ndev);
1243 priv->ndev = ndev;
1244 priv->regs = addr;
1245 priv->dev = pdev;
1246 priv->can.bittiming_const = &pch_can_bittiming_const;
1247 priv->can.do_set_mode = pch_can_do_set_mode;
1248 priv->can.do_get_berr_counter = pch_can_get_berr_counter;
1249 priv->can.ctrlmode_supported = CAN_CTRLMODE_LISTENONLY |
1250 CAN_CTRLMODE_LOOPBACK;
15ffc8fd 1251 priv->tx_obj = PCH_TX_OBJ_START; /* Point head of Tx Obj */
b21d18b5
MO		 1252
1253 ndev->irq = pdev->irq;
1254 ndev->flags |= IFF_ECHO;
1255
1256 pci_set_drvdata(pdev, ndev);
1257 SET_NETDEV_DEV(ndev, &pdev->dev);
1258 ndev->netdev_ops = &pch_can_netdev_ops;
b21d18b5 1259 priv->can.clock.freq = PCH_CAN_CLK; /* Hz */
b21d18b5 1260
bd58cbc3 1261 netif_napi_add(ndev, &priv->napi, pch_can_poll, PCH_RX_OBJ_END);
b21d18b5
MO		 1262
1263 rc = register_candev(ndev);
1264 if (rc) {
1265 dev_err(&pdev->dev, "Failed register_candev %d\n", rc);
1266 goto probe_exit_reg_candev;
1267 }
1268
1269 return 0;
1270
1271probe_exit_reg_candev:
1272 free_candev(ndev);
1273probe_exit_alloc_candev:
1274 pci_iounmap(pdev, addr);
1275probe_exit_ipmap:
1276 pci_release_regions(pdev);
1277probe_exit_pcireq:
1278 pci_disable_device(pdev);
1279probe_exit_endev:
1280 return rc;
1281}
1282
bdfa3d8f 1283static struct pci_driver pch_can_pci_driver = {
b21d18b5
MO		 1284 .name = "pch_can",
1285 .id_table = pch_pci_tbl,
1286 .probe = pch_can_probe,
1287 .remove = __devexit_p(pch_can_remove),
1288 .suspend = pch_can_suspend,
1289 .resume = pch_can_resume,
1290};
1291
1292static int __init pch_can_pci_init(void)
1293{
bdfa3d8f 1294 return pci_register_driver(&pch_can_pci_driver);
b21d18b5
MO		 1295}
1296module_init(pch_can_pci_init);
1297
1298static void __exit pch_can_pci_exit(void)
1299{
bdfa3d8f 1300 pci_unregister_driver(&pch_can_pci_driver);
b21d18b5
MO		 1301}
1302module_exit(pch_can_pci_exit);
1303
1304MODULE_DESCRIPTION("Controller Area Network Driver");
1305MODULE_LICENSE("GPL v2");
1306MODULE_VERSION("0.94");
Linux kernel - Deliverables
This page took 0.098599 seconds and 5 git commands to generate.