Commit | Line | Data |
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b21d18b5 MO |
1 | /* |
2 | * Copyright (C) 1999 - 2010 Intel Corporation. | |
3 | * Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation; version 2 of the License. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. | |
17 | */ | |
18 | ||
19 | #include <linux/interrupt.h> | |
20 | #include <linux/delay.h> | |
21 | #include <linux/io.h> | |
22 | #include <linux/module.h> | |
23 | #include <linux/sched.h> | |
24 | #include <linux/pci.h> | |
25 | #include <linux/init.h> | |
26 | #include <linux/kernel.h> | |
27 | #include <linux/types.h> | |
28 | #include <linux/errno.h> | |
29 | #include <linux/netdevice.h> | |
30 | #include <linux/skbuff.h> | |
31 | #include <linux/can.h> | |
32 | #include <linux/can/dev.h> | |
33 | #include <linux/can/error.h> | |
34 | ||
086b5650 T |
35 | #define PCH_ENABLE 1 /* The enable flag */ |
36 | #define PCH_DISABLE 0 /* The disable flag */ | |
0a80410d T |
37 | #define PCH_CTRL_INIT BIT(0) /* The INIT bit of CANCONT register. */ |
38 | #define PCH_CTRL_IE BIT(1) /* The IE bit of CAN control register */ | |
39 | #define PCH_CTRL_IE_SIE_EIE (BIT(3) | BIT(2) | BIT(1)) | |
40 | #define PCH_CTRL_CCE BIT(6) | |
41 | #define PCH_CTRL_OPT BIT(7) /* The OPT bit of CANCONT register. */ | |
42 | #define PCH_OPT_SILENT BIT(3) /* The Silent bit of CANOPT reg. */ | |
43 | #define PCH_OPT_LBACK BIT(4) /* The LoopBack bit of CANOPT reg. */ | |
44 | ||
086b5650 T |
45 | #define PCH_CMASK_RX_TX_SET 0x00f3 |
46 | #define PCH_CMASK_RX_TX_GET 0x0073 | |
47 | #define PCH_CMASK_ALL 0xff | |
0a80410d T |
48 | #define PCH_CMASK_NEWDAT BIT(2) |
49 | #define PCH_CMASK_CLRINTPND BIT(3) | |
50 | #define PCH_CMASK_CTRL BIT(4) | |
51 | #define PCH_CMASK_ARB BIT(5) | |
52 | #define PCH_CMASK_MASK BIT(6) | |
53 | #define PCH_CMASK_RDWR BIT(7) | |
54 | #define PCH_IF_MCONT_NEWDAT BIT(15) | |
55 | #define PCH_IF_MCONT_MSGLOST BIT(14) | |
56 | #define PCH_IF_MCONT_INTPND BIT(13) | |
57 | #define PCH_IF_MCONT_UMASK BIT(12) | |
58 | #define PCH_IF_MCONT_TXIE BIT(11) | |
59 | #define PCH_IF_MCONT_RXIE BIT(10) | |
60 | #define PCH_IF_MCONT_RMTEN BIT(9) | |
61 | #define PCH_IF_MCONT_TXRQXT BIT(8) | |
62 | #define PCH_IF_MCONT_EOB BIT(7) | |
63 | #define PCH_IF_MCONT_DLC (BIT(0) | BIT(1) | BIT(2) | BIT(3)) | |
64 | #define PCH_MASK2_MDIR_MXTD (BIT(14) | BIT(15)) | |
65 | #define PCH_ID2_DIR BIT(13) | |
66 | #define PCH_ID2_XTD BIT(14) | |
67 | #define PCH_ID_MSGVAL BIT(15) | |
68 | #define PCH_IF_CREQ_BUSY BIT(15) | |
086b5650 T |
69 | |
70 | #define PCH_STATUS_INT 0x8000 | |
71 | #define PCH_REC 0x00007f00 | |
72 | #define PCH_TEC 0x000000ff | |
b21d18b5 | 73 | |
0a80410d T |
74 | #define PCH_TX_OK BIT(3) |
75 | #define PCH_RX_OK BIT(4) | |
76 | #define PCH_EPASSIV BIT(5) | |
77 | #define PCH_EWARN BIT(6) | |
78 | #define PCH_BUS_OFF BIT(7) | |
b21d18b5 MO |
79 | |
80 | /* bit position of certain controller bits. */ | |
086b5650 T |
81 | #define PCH_BIT_BRP 0 |
82 | #define PCH_BIT_SJW 6 | |
83 | #define PCH_BIT_TSEG1 8 | |
84 | #define PCH_BIT_TSEG2 12 | |
85 | #define PCH_BIT_BRPE_BRPE 6 | |
86 | #define PCH_MSK_BITT_BRP 0x3f | |
87 | #define PCH_MSK_BRPE_BRPE 0x3c0 | |
88 | #define PCH_MSK_CTRL_IE_SIE_EIE 0x07 | |
89 | #define PCH_COUNTER_LIMIT 10 | |
b21d18b5 MO |
90 | |
91 | #define PCH_CAN_CLK 50000000 /* 50MHz */ | |
92 | ||
93 | /* Define the number of message object. | |
94 | * PCH CAN communications are done via Message RAM. | |
95 | * The Message RAM consists of 32 message objects. */ | |
15ffc8fd T |
96 | #define PCH_RX_OBJ_NUM 26 |
97 | #define PCH_TX_OBJ_NUM 6 | |
98 | #define PCH_RX_OBJ_START 1 | |
99 | #define PCH_RX_OBJ_END PCH_RX_OBJ_NUM | |
100 | #define PCH_TX_OBJ_START (PCH_RX_OBJ_END + 1) | |
101 | #define PCH_TX_OBJ_END (PCH_RX_OBJ_NUM + PCH_TX_OBJ_NUM) | |
b21d18b5 MO |
102 | |
103 | #define PCH_FIFO_THRESH 16 | |
104 | ||
76d94b23 T |
105 | /* TxRqst2 show status of MsgObjNo.17~32 */ |
106 | #define PCH_TREQ2_TX_MASK (((1 << PCH_TX_OBJ_NUM) - 1) <<\ | |
107 | (PCH_RX_OBJ_END - 16)) | |
108 | ||
8339a7ed T |
109 | enum pch_ifreg { |
110 | PCH_RX_IFREG, | |
111 | PCH_TX_IFREG, | |
112 | }; | |
113 | ||
d68f6837 T |
114 | enum pch_can_err { |
115 | PCH_STUF_ERR = 1, | |
116 | PCH_FORM_ERR, | |
117 | PCH_ACK_ERR, | |
118 | PCH_BIT1_ERR, | |
119 | PCH_BIT0_ERR, | |
120 | PCH_CRC_ERR, | |
121 | PCH_LEC_ALL, | |
122 | }; | |
123 | ||
b21d18b5 MO |
124 | enum pch_can_mode { |
125 | PCH_CAN_ENABLE, | |
126 | PCH_CAN_DISABLE, | |
127 | PCH_CAN_ALL, | |
128 | PCH_CAN_NONE, | |
129 | PCH_CAN_STOP, | |
130 | PCH_CAN_RUN | |
131 | }; | |
132 | ||
8339a7ed T |
133 | struct pch_can_if_regs { |
134 | u32 creq; | |
135 | u32 cmask; | |
136 | u32 mask1; | |
137 | u32 mask2; | |
138 | u32 id1; | |
139 | u32 id2; | |
140 | u32 mcont; | |
141 | u32 dataa1; | |
142 | u32 dataa2; | |
143 | u32 datab1; | |
144 | u32 datab2; | |
145 | u32 rsv[13]; | |
146 | }; | |
147 | ||
b21d18b5 MO |
148 | struct pch_can_regs { |
149 | u32 cont; | |
150 | u32 stat; | |
151 | u32 errc; | |
152 | u32 bitt; | |
153 | u32 intr; | |
154 | u32 opt; | |
155 | u32 brpe; | |
8339a7ed T |
156 | u32 reserve; |
157 | struct pch_can_if_regs ifregs[2]; /* [0]=if1 [1]=if2 */ | |
158 | u32 reserve1[8]; | |
b21d18b5 MO |
159 | u32 treq1; |
160 | u32 treq2; | |
8339a7ed T |
161 | u32 reserve2[6]; |
162 | u32 data1; | |
163 | u32 data2; | |
164 | u32 reserve3[6]; | |
165 | u32 canipend1; | |
166 | u32 canipend2; | |
167 | u32 reserve4[6]; | |
168 | u32 canmval1; | |
169 | u32 canmval2; | |
170 | u32 reserve5[37]; | |
b21d18b5 MO |
171 | u32 srst; |
172 | }; | |
173 | ||
174 | struct pch_can_priv { | |
175 | struct can_priv can; | |
176 | unsigned int can_num; | |
177 | struct pci_dev *dev; | |
15ffc8fd T |
178 | int tx_enable[PCH_TX_OBJ_END]; |
179 | int rx_enable[PCH_TX_OBJ_END]; | |
180 | int rx_link[PCH_TX_OBJ_END]; | |
b21d18b5 MO |
181 | unsigned int int_enables; |
182 | unsigned int int_stat; | |
183 | struct net_device *ndev; | |
15ffc8fd | 184 | unsigned int msg_obj[PCH_TX_OBJ_END]; |
b21d18b5 MO |
185 | struct pch_can_regs __iomem *regs; |
186 | struct napi_struct napi; | |
187 | unsigned int tx_obj; /* Point next Tx Obj index */ | |
188 | unsigned int use_msi; | |
189 | }; | |
190 | ||
191 | static struct can_bittiming_const pch_can_bittiming_const = { | |
192 | .name = KBUILD_MODNAME, | |
193 | .tseg1_min = 1, | |
194 | .tseg1_max = 16, | |
195 | .tseg2_min = 1, | |
196 | .tseg2_max = 8, | |
197 | .sjw_max = 4, | |
198 | .brp_min = 1, | |
199 | .brp_max = 1024, /* 6bit + extended 4bit */ | |
200 | .brp_inc = 1, | |
201 | }; | |
202 | ||
203 | static DEFINE_PCI_DEVICE_TABLE(pch_pci_tbl) = { | |
204 | {PCI_VENDOR_ID_INTEL, 0x8818, PCI_ANY_ID, PCI_ANY_ID,}, | |
205 | {0,} | |
206 | }; | |
207 | MODULE_DEVICE_TABLE(pci, pch_pci_tbl); | |
208 | ||
526de53c | 209 | static inline void pch_can_bit_set(void __iomem *addr, u32 mask) |
b21d18b5 MO |
210 | { |
211 | iowrite32(ioread32(addr) | mask, addr); | |
212 | } | |
213 | ||
526de53c | 214 | static inline void pch_can_bit_clear(void __iomem *addr, u32 mask) |
b21d18b5 MO |
215 | { |
216 | iowrite32(ioread32(addr) & ~mask, addr); | |
217 | } | |
218 | ||
219 | static void pch_can_set_run_mode(struct pch_can_priv *priv, | |
220 | enum pch_can_mode mode) | |
221 | { | |
222 | switch (mode) { | |
223 | case PCH_CAN_RUN: | |
086b5650 | 224 | pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_INIT); |
b21d18b5 MO |
225 | break; |
226 | ||
227 | case PCH_CAN_STOP: | |
086b5650 | 228 | pch_can_bit_set(&priv->regs->cont, PCH_CTRL_INIT); |
b21d18b5 MO |
229 | break; |
230 | ||
231 | default: | |
232 | dev_err(&priv->ndev->dev, "%s -> Invalid Mode.\n", __func__); | |
233 | break; | |
234 | } | |
235 | } | |
236 | ||
237 | static void pch_can_set_optmode(struct pch_can_priv *priv) | |
238 | { | |
239 | u32 reg_val = ioread32(&priv->regs->opt); | |
240 | ||
241 | if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) | |
086b5650 | 242 | reg_val |= PCH_OPT_SILENT; |
b21d18b5 MO |
243 | |
244 | if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) | |
086b5650 | 245 | reg_val |= PCH_OPT_LBACK; |
b21d18b5 | 246 | |
086b5650 | 247 | pch_can_bit_set(&priv->regs->cont, PCH_CTRL_OPT); |
b21d18b5 MO |
248 | iowrite32(reg_val, &priv->regs->opt); |
249 | } | |
250 | ||
251 | static void pch_can_set_int_custom(struct pch_can_priv *priv) | |
252 | { | |
253 | /* Clearing the IE, SIE and EIE bits of Can control register. */ | |
086b5650 | 254 | pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_IE_SIE_EIE); |
b21d18b5 MO |
255 | |
256 | /* Appropriately setting them. */ | |
257 | pch_can_bit_set(&priv->regs->cont, | |
086b5650 | 258 | ((priv->int_enables & PCH_MSK_CTRL_IE_SIE_EIE) << 1)); |
b21d18b5 MO |
259 | } |
260 | ||
261 | /* This function retrieves interrupt enabled for the CAN device. */ | |
262 | static void pch_can_get_int_enables(struct pch_can_priv *priv, u32 *enables) | |
263 | { | |
264 | /* Obtaining the status of IE, SIE and EIE interrupt bits. */ | |
086b5650 | 265 | *enables = ((ioread32(&priv->regs->cont) & PCH_CTRL_IE_SIE_EIE) >> 1); |
b21d18b5 MO |
266 | } |
267 | ||
268 | static void pch_can_set_int_enables(struct pch_can_priv *priv, | |
269 | enum pch_can_mode interrupt_no) | |
270 | { | |
271 | switch (interrupt_no) { | |
272 | case PCH_CAN_ENABLE: | |
086b5650 | 273 | pch_can_bit_set(&priv->regs->cont, PCH_CTRL_IE); |
b21d18b5 MO |
274 | break; |
275 | ||
276 | case PCH_CAN_DISABLE: | |
086b5650 | 277 | pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_IE); |
b21d18b5 MO |
278 | break; |
279 | ||
280 | case PCH_CAN_ALL: | |
086b5650 | 281 | pch_can_bit_set(&priv->regs->cont, PCH_CTRL_IE_SIE_EIE); |
b21d18b5 MO |
282 | break; |
283 | ||
284 | case PCH_CAN_NONE: | |
086b5650 | 285 | pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_IE_SIE_EIE); |
b21d18b5 MO |
286 | break; |
287 | ||
288 | default: | |
289 | dev_err(&priv->ndev->dev, "Invalid interrupt number.\n"); | |
290 | break; | |
291 | } | |
292 | } | |
293 | ||
294 | static void pch_can_check_if_busy(u32 __iomem *creq_addr, u32 num) | |
295 | { | |
086b5650 | 296 | u32 counter = PCH_COUNTER_LIMIT; |
b21d18b5 MO |
297 | u32 ifx_creq; |
298 | ||
299 | iowrite32(num, creq_addr); | |
300 | while (counter) { | |
086b5650 | 301 | ifx_creq = ioread32(creq_addr) & PCH_IF_CREQ_BUSY; |
b21d18b5 MO |
302 | if (!ifx_creq) |
303 | break; | |
304 | counter--; | |
305 | udelay(1); | |
306 | } | |
307 | if (!counter) | |
308 | pr_err("%s:IF1 BUSY Flag is set forever.\n", __func__); | |
309 | } | |
310 | ||
8339a7ed T |
311 | static void pch_can_set_rxtx(struct pch_can_priv *priv, u32 buff_num, |
312 | u32 set, enum pch_ifreg dir) | |
b21d18b5 | 313 | { |
8339a7ed T |
314 | u32 ie; |
315 | ||
316 | if (dir) | |
317 | ie = PCH_IF_MCONT_TXIE; | |
318 | else | |
319 | ie = PCH_IF_MCONT_RXIE; | |
b21d18b5 | 320 | |
b21d18b5 | 321 | /* Reading the receive buffer data from RAM to Interface1 registers */ |
8339a7ed T |
322 | iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[dir].cmask); |
323 | pch_can_check_if_busy(&priv->regs->ifregs[dir].creq, buff_num); | |
b21d18b5 MO |
324 | |
325 | /* Setting the IF1MASK1 register to access MsgVal and RxIE bits */ | |
086b5650 | 326 | iowrite32(PCH_CMASK_RDWR | PCH_CMASK_ARB | PCH_CMASK_CTRL, |
8339a7ed | 327 | &priv->regs->ifregs[dir].cmask); |
b21d18b5 | 328 | |
086b5650 | 329 | if (set == PCH_ENABLE) { |
b21d18b5 | 330 | /* Setting the MsgVal and RxIE bits */ |
8339a7ed T |
331 | pch_can_bit_set(&priv->regs->ifregs[dir].mcont, ie); |
332 | pch_can_bit_set(&priv->regs->ifregs[dir].id2, PCH_ID_MSGVAL); | |
b21d18b5 | 333 | |
086b5650 | 334 | } else if (set == PCH_DISABLE) { |
b21d18b5 | 335 | /* Resetting the MsgVal and RxIE bits */ |
8339a7ed T |
336 | pch_can_bit_clear(&priv->regs->ifregs[dir].mcont, ie); |
337 | pch_can_bit_clear(&priv->regs->ifregs[dir].id2, PCH_ID_MSGVAL); | |
b21d18b5 MO |
338 | } |
339 | ||
8339a7ed | 340 | pch_can_check_if_busy(&priv->regs->ifregs[dir].creq, buff_num); |
b21d18b5 MO |
341 | } |
342 | ||
8339a7ed | 343 | static void pch_can_set_rx_all(struct pch_can_priv *priv, u32 set) |
b21d18b5 MO |
344 | { |
345 | int i; | |
346 | ||
347 | /* Traversing to obtain the object configured as receivers. */ | |
15ffc8fd T |
348 | for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++) |
349 | pch_can_set_rxtx(priv, i, set, PCH_RX_IFREG); | |
b21d18b5 MO |
350 | } |
351 | ||
8339a7ed | 352 | static void pch_can_set_tx_all(struct pch_can_priv *priv, u32 set) |
b21d18b5 MO |
353 | { |
354 | int i; | |
355 | ||
356 | /* Traversing to obtain the object configured as transmit object. */ | |
15ffc8fd T |
357 | for (i = PCH_TX_OBJ_START; i <= PCH_TX_OBJ_END; i++) |
358 | pch_can_set_rxtx(priv, i, set, PCH_TX_IFREG); | |
b21d18b5 MO |
359 | } |
360 | ||
8339a7ed T |
361 | static u32 pch_can_get_rxtx_ir(struct pch_can_priv *priv, u32 buff_num, |
362 | enum pch_ifreg dir) | |
b21d18b5 | 363 | { |
8339a7ed | 364 | u32 ie, enable; |
b21d18b5 | 365 | |
8339a7ed T |
366 | if (dir) |
367 | ie = PCH_IF_MCONT_RXIE; | |
b21d18b5 | 368 | else |
8339a7ed | 369 | ie = PCH_IF_MCONT_TXIE; |
b21d18b5 | 370 | |
8339a7ed T |
371 | iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[dir].cmask); |
372 | pch_can_check_if_busy(&priv->regs->ifregs[dir].creq, buff_num); | |
b21d18b5 | 373 | |
8339a7ed T |
374 | if (((ioread32(&priv->regs->ifregs[dir].id2)) & PCH_ID_MSGVAL) && |
375 | ((ioread32(&priv->regs->ifregs[dir].mcont)) & ie)) { | |
15ffc8fd | 376 | enable = 1; |
b21d18b5 | 377 | } else { |
15ffc8fd | 378 | enable = 0; |
b21d18b5 | 379 | } |
8339a7ed | 380 | return enable; |
b21d18b5 MO |
381 | } |
382 | ||
383 | static int pch_can_int_pending(struct pch_can_priv *priv) | |
384 | { | |
385 | return ioread32(&priv->regs->intr) & 0xffff; | |
386 | } | |
387 | ||
388 | static void pch_can_set_rx_buffer_link(struct pch_can_priv *priv, | |
389 | u32 buffer_num, u32 set) | |
390 | { | |
8339a7ed T |
391 | iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask); |
392 | pch_can_check_if_busy(&priv->regs->ifregs[0].creq, buffer_num); | |
393 | iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL, | |
394 | &priv->regs->ifregs[0].cmask); | |
086b5650 | 395 | if (set == PCH_ENABLE) |
8339a7ed T |
396 | pch_can_bit_clear(&priv->regs->ifregs[0].mcont, |
397 | PCH_IF_MCONT_EOB); | |
b21d18b5 | 398 | else |
8339a7ed | 399 | pch_can_bit_set(&priv->regs->ifregs[0].mcont, PCH_IF_MCONT_EOB); |
b21d18b5 | 400 | |
8339a7ed | 401 | pch_can_check_if_busy(&priv->regs->ifregs[0].creq, buffer_num); |
b21d18b5 MO |
402 | } |
403 | ||
404 | static void pch_can_get_rx_buffer_link(struct pch_can_priv *priv, | |
405 | u32 buffer_num, u32 *link) | |
406 | { | |
8339a7ed T |
407 | iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask); |
408 | pch_can_check_if_busy(&priv->regs->ifregs[0].creq, buffer_num); | |
b21d18b5 | 409 | |
8339a7ed | 410 | if (ioread32(&priv->regs->ifregs[0].mcont) & PCH_IF_MCONT_EOB) |
086b5650 | 411 | *link = PCH_DISABLE; |
b21d18b5 | 412 | else |
086b5650 | 413 | *link = PCH_ENABLE; |
b21d18b5 MO |
414 | } |
415 | ||
416 | static void pch_can_clear_buffers(struct pch_can_priv *priv) | |
417 | { | |
418 | int i; | |
419 | ||
15ffc8fd | 420 | for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++) { |
8339a7ed T |
421 | iowrite32(PCH_CMASK_RX_TX_SET, &priv->regs->ifregs[0].cmask); |
422 | iowrite32(0xffff, &priv->regs->ifregs[0].mask1); | |
423 | iowrite32(0xffff, &priv->regs->ifregs[0].mask2); | |
424 | iowrite32(0x0, &priv->regs->ifregs[0].id1); | |
425 | iowrite32(0x0, &priv->regs->ifregs[0].id2); | |
426 | iowrite32(0x0, &priv->regs->ifregs[0].mcont); | |
427 | iowrite32(0x0, &priv->regs->ifregs[0].dataa1); | |
428 | iowrite32(0x0, &priv->regs->ifregs[0].dataa2); | |
429 | iowrite32(0x0, &priv->regs->ifregs[0].datab1); | |
430 | iowrite32(0x0, &priv->regs->ifregs[0].datab2); | |
086b5650 T |
431 | iowrite32(PCH_CMASK_RDWR | PCH_CMASK_MASK | |
432 | PCH_CMASK_ARB | PCH_CMASK_CTRL, | |
8339a7ed | 433 | &priv->regs->ifregs[0].cmask); |
15ffc8fd | 434 | pch_can_check_if_busy(&priv->regs->ifregs[0].creq, i); |
b21d18b5 MO |
435 | } |
436 | ||
15ffc8fd | 437 | for (i = PCH_TX_OBJ_START; i <= PCH_TX_OBJ_END; i++) { |
8339a7ed T |
438 | iowrite32(PCH_CMASK_RX_TX_SET, &priv->regs->ifregs[1].cmask); |
439 | iowrite32(0xffff, &priv->regs->ifregs[1].mask1); | |
440 | iowrite32(0xffff, &priv->regs->ifregs[1].mask2); | |
441 | iowrite32(0x0, &priv->regs->ifregs[1].id1); | |
442 | iowrite32(0x0, &priv->regs->ifregs[1].id2); | |
443 | iowrite32(0x0, &priv->regs->ifregs[1].mcont); | |
444 | iowrite32(0x0, &priv->regs->ifregs[1].dataa1); | |
445 | iowrite32(0x0, &priv->regs->ifregs[1].dataa2); | |
446 | iowrite32(0x0, &priv->regs->ifregs[1].datab1); | |
447 | iowrite32(0x0, &priv->regs->ifregs[1].datab2); | |
086b5650 T |
448 | iowrite32(PCH_CMASK_RDWR | PCH_CMASK_MASK | |
449 | PCH_CMASK_ARB | PCH_CMASK_CTRL, | |
8339a7ed | 450 | &priv->regs->ifregs[1].cmask); |
15ffc8fd | 451 | pch_can_check_if_busy(&priv->regs->ifregs[1].creq, i); |
b21d18b5 MO |
452 | } |
453 | } | |
454 | ||
455 | static void pch_can_config_rx_tx_buffers(struct pch_can_priv *priv) | |
456 | { | |
457 | int i; | |
b21d18b5 | 458 | |
15ffc8fd T |
459 | for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++) { |
460 | iowrite32(PCH_CMASK_RX_TX_GET, | |
461 | &priv->regs->ifregs[0].cmask); | |
462 | pch_can_check_if_busy(&priv->regs->ifregs[0].creq, i); | |
b21d18b5 | 463 | |
15ffc8fd T |
464 | iowrite32(0x0, &priv->regs->ifregs[0].id1); |
465 | iowrite32(0x0, &priv->regs->ifregs[0].id2); | |
b21d18b5 | 466 | |
15ffc8fd T |
467 | pch_can_bit_set(&priv->regs->ifregs[0].mcont, |
468 | PCH_IF_MCONT_UMASK); | |
b21d18b5 | 469 | |
15ffc8fd T |
470 | /* Set FIFO mode set to 0 except last Rx Obj*/ |
471 | pch_can_bit_clear(&priv->regs->ifregs[0].mcont, | |
472 | PCH_IF_MCONT_EOB); | |
473 | /* In case FIFO mode, Last EoB of Rx Obj must be 1 */ | |
474 | if (i == PCH_RX_OBJ_END) | |
475 | pch_can_bit_set(&priv->regs->ifregs[0].mcont, | |
086b5650 | 476 | PCH_IF_MCONT_EOB); |
b21d18b5 | 477 | |
15ffc8fd T |
478 | iowrite32(0, &priv->regs->ifregs[0].mask1); |
479 | pch_can_bit_clear(&priv->regs->ifregs[0].mask2, | |
480 | 0x1fff | PCH_MASK2_MDIR_MXTD); | |
b21d18b5 | 481 | |
15ffc8fd T |
482 | /* Setting CMASK for writing */ |
483 | iowrite32(PCH_CMASK_RDWR | PCH_CMASK_MASK | | |
484 | PCH_CMASK_ARB | PCH_CMASK_CTRL, | |
485 | &priv->regs->ifregs[0].cmask); | |
b21d18b5 | 486 | |
15ffc8fd T |
487 | pch_can_check_if_busy(&priv->regs->ifregs[0].creq, i); |
488 | } | |
b21d18b5 | 489 | |
15ffc8fd T |
490 | for (i = PCH_TX_OBJ_START; i <= PCH_TX_OBJ_END; i++) { |
491 | iowrite32(PCH_CMASK_RX_TX_GET, | |
492 | &priv->regs->ifregs[1].cmask); | |
493 | pch_can_check_if_busy(&priv->regs->ifregs[1].creq, i); | |
b21d18b5 | 494 | |
15ffc8fd T |
495 | /* Resetting DIR bit for reception */ |
496 | iowrite32(0x0, &priv->regs->ifregs[1].id1); | |
497 | iowrite32(0x0, &priv->regs->ifregs[1].id2); | |
498 | pch_can_bit_set(&priv->regs->ifregs[1].id2, PCH_ID2_DIR); | |
b21d18b5 | 499 | |
15ffc8fd T |
500 | /* Setting EOB bit for transmitter */ |
501 | iowrite32(PCH_IF_MCONT_EOB, &priv->regs->ifregs[1].mcont); | |
b21d18b5 | 502 | |
15ffc8fd T |
503 | pch_can_bit_set(&priv->regs->ifregs[1].mcont, |
504 | PCH_IF_MCONT_UMASK); | |
505 | ||
506 | iowrite32(0, &priv->regs->ifregs[1].mask1); | |
507 | pch_can_bit_clear(&priv->regs->ifregs[1].mask2, 0x1fff); | |
508 | ||
509 | /* Setting CMASK for writing */ | |
510 | iowrite32(PCH_CMASK_RDWR | PCH_CMASK_MASK | | |
511 | PCH_CMASK_ARB | PCH_CMASK_CTRL, | |
512 | &priv->regs->ifregs[1].cmask); | |
513 | ||
514 | pch_can_check_if_busy(&priv->regs->ifregs[1].creq, i); | |
b21d18b5 | 515 | } |
b21d18b5 MO |
516 | } |
517 | ||
518 | static void pch_can_init(struct pch_can_priv *priv) | |
519 | { | |
520 | /* Stopping the Can device. */ | |
521 | pch_can_set_run_mode(priv, PCH_CAN_STOP); | |
522 | ||
523 | /* Clearing all the message object buffers. */ | |
524 | pch_can_clear_buffers(priv); | |
525 | ||
526 | /* Configuring the respective message object as either rx/tx object. */ | |
527 | pch_can_config_rx_tx_buffers(priv); | |
528 | ||
529 | /* Enabling the interrupts. */ | |
530 | pch_can_set_int_enables(priv, PCH_CAN_ALL); | |
531 | } | |
532 | ||
533 | static void pch_can_release(struct pch_can_priv *priv) | |
534 | { | |
535 | /* Stooping the CAN device. */ | |
536 | pch_can_set_run_mode(priv, PCH_CAN_STOP); | |
537 | ||
538 | /* Disabling the interrupts. */ | |
539 | pch_can_set_int_enables(priv, PCH_CAN_NONE); | |
540 | ||
541 | /* Disabling all the receive object. */ | |
8339a7ed | 542 | pch_can_set_rx_all(priv, 0); |
b21d18b5 MO |
543 | |
544 | /* Disabling all the transmit object. */ | |
8339a7ed | 545 | pch_can_set_tx_all(priv, 0); |
b21d18b5 MO |
546 | } |
547 | ||
548 | /* This function clears interrupt(s) from the CAN device. */ | |
549 | static void pch_can_int_clr(struct pch_can_priv *priv, u32 mask) | |
550 | { | |
086b5650 | 551 | if (mask == PCH_STATUS_INT) { |
b21d18b5 MO |
552 | ioread32(&priv->regs->stat); |
553 | return; | |
554 | } | |
555 | ||
556 | /* Clear interrupt for transmit object */ | |
15ffc8fd T |
557 | if ((mask >= PCH_RX_OBJ_START) && (mask <= PCH_RX_OBJ_END)) { |
558 | /* Setting CMASK for clearing the reception interrupts. */ | |
559 | iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL | PCH_CMASK_ARB, | |
560 | &priv->regs->ifregs[0].cmask); | |
561 | ||
562 | /* Clearing the Dir bit. */ | |
563 | pch_can_bit_clear(&priv->regs->ifregs[0].id2, PCH_ID2_DIR); | |
564 | ||
565 | /* Clearing NewDat & IntPnd */ | |
566 | pch_can_bit_clear(&priv->regs->ifregs[0].mcont, | |
567 | PCH_IF_MCONT_NEWDAT | PCH_IF_MCONT_INTPND); | |
568 | ||
569 | pch_can_check_if_busy(&priv->regs->ifregs[0].creq, mask); | |
570 | } else if ((mask >= PCH_TX_OBJ_START) && (mask <= PCH_TX_OBJ_END)) { | |
b21d18b5 MO |
571 | /* Setting CMASK for clearing interrupts for |
572 | frame transmission. */ | |
086b5650 | 573 | iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL | PCH_CMASK_ARB, |
8339a7ed | 574 | &priv->regs->ifregs[1].cmask); |
b21d18b5 MO |
575 | |
576 | /* Resetting the ID registers. */ | |
8339a7ed | 577 | pch_can_bit_set(&priv->regs->ifregs[1].id2, |
086b5650 | 578 | PCH_ID2_DIR | (0x7ff << 2)); |
8339a7ed | 579 | iowrite32(0x0, &priv->regs->ifregs[1].id1); |
b21d18b5 MO |
580 | |
581 | /* Claring NewDat, TxRqst & IntPnd */ | |
8339a7ed | 582 | pch_can_bit_clear(&priv->regs->ifregs[1].mcont, |
086b5650 T |
583 | PCH_IF_MCONT_NEWDAT | PCH_IF_MCONT_INTPND | |
584 | PCH_IF_MCONT_TXRQXT); | |
8339a7ed | 585 | pch_can_check_if_busy(&priv->regs->ifregs[1].creq, mask); |
b21d18b5 MO |
586 | } |
587 | } | |
588 | ||
589 | static int pch_can_get_buffer_status(struct pch_can_priv *priv) | |
590 | { | |
591 | return (ioread32(&priv->regs->treq1) & 0xffff) | | |
592 | ((ioread32(&priv->regs->treq2) & 0xffff) << 16); | |
593 | } | |
594 | ||
595 | static void pch_can_reset(struct pch_can_priv *priv) | |
596 | { | |
597 | /* write to sw reset register */ | |
598 | iowrite32(1, &priv->regs->srst); | |
599 | iowrite32(0, &priv->regs->srst); | |
600 | } | |
601 | ||
602 | static void pch_can_error(struct net_device *ndev, u32 status) | |
603 | { | |
604 | struct sk_buff *skb; | |
605 | struct pch_can_priv *priv = netdev_priv(ndev); | |
606 | struct can_frame *cf; | |
d68f6837 | 607 | u32 errc, lec; |
b21d18b5 MO |
608 | struct net_device_stats *stats = &(priv->ndev->stats); |
609 | enum can_state state = priv->can.state; | |
610 | ||
611 | skb = alloc_can_err_skb(ndev, &cf); | |
612 | if (!skb) | |
613 | return; | |
614 | ||
615 | if (status & PCH_BUS_OFF) { | |
8339a7ed T |
616 | pch_can_set_tx_all(priv, 0); |
617 | pch_can_set_rx_all(priv, 0); | |
b21d18b5 MO |
618 | state = CAN_STATE_BUS_OFF; |
619 | cf->can_id |= CAN_ERR_BUSOFF; | |
620 | can_bus_off(ndev); | |
621 | pch_can_set_run_mode(priv, PCH_CAN_RUN); | |
622 | dev_err(&ndev->dev, "%s -> Bus Off occurres.\n", __func__); | |
623 | } | |
624 | ||
625 | /* Warning interrupt. */ | |
626 | if (status & PCH_EWARN) { | |
627 | state = CAN_STATE_ERROR_WARNING; | |
628 | priv->can.can_stats.error_warning++; | |
629 | cf->can_id |= CAN_ERR_CRTL; | |
630 | errc = ioread32(&priv->regs->errc); | |
086b5650 | 631 | if (((errc & PCH_REC) >> 8) > 96) |
b21d18b5 | 632 | cf->data[1] |= CAN_ERR_CRTL_RX_WARNING; |
086b5650 | 633 | if ((errc & PCH_TEC) > 96) |
b21d18b5 MO |
634 | cf->data[1] |= CAN_ERR_CRTL_TX_WARNING; |
635 | dev_warn(&ndev->dev, | |
636 | "%s -> Error Counter is more than 96.\n", __func__); | |
637 | } | |
638 | /* Error passive interrupt. */ | |
639 | if (status & PCH_EPASSIV) { | |
640 | priv->can.can_stats.error_passive++; | |
641 | state = CAN_STATE_ERROR_PASSIVE; | |
642 | cf->can_id |= CAN_ERR_CRTL; | |
643 | errc = ioread32(&priv->regs->errc); | |
086b5650 | 644 | if (((errc & PCH_REC) >> 8) > 127) |
b21d18b5 | 645 | cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE; |
086b5650 | 646 | if ((errc & PCH_TEC) > 127) |
b21d18b5 MO |
647 | cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE; |
648 | dev_err(&ndev->dev, | |
649 | "%s -> CAN controller is ERROR PASSIVE .\n", __func__); | |
650 | } | |
651 | ||
d68f6837 T |
652 | lec = status & PCH_LEC_ALL; |
653 | switch (lec) { | |
654 | case PCH_STUF_ERR: | |
655 | cf->data[2] |= CAN_ERR_PROT_STUFF; | |
b21d18b5 MO |
656 | priv->can.can_stats.bus_error++; |
657 | stats->rx_errors++; | |
d68f6837 T |
658 | break; |
659 | case PCH_FORM_ERR: | |
660 | cf->data[2] |= CAN_ERR_PROT_FORM; | |
661 | priv->can.can_stats.bus_error++; | |
662 | stats->rx_errors++; | |
663 | break; | |
664 | case PCH_ACK_ERR: | |
665 | cf->can_id |= CAN_ERR_ACK; | |
666 | priv->can.can_stats.bus_error++; | |
667 | stats->rx_errors++; | |
668 | break; | |
669 | case PCH_BIT1_ERR: | |
670 | case PCH_BIT0_ERR: | |
671 | cf->data[2] |= CAN_ERR_PROT_BIT; | |
672 | priv->can.can_stats.bus_error++; | |
673 | stats->rx_errors++; | |
674 | break; | |
675 | case PCH_CRC_ERR: | |
676 | cf->data[2] |= CAN_ERR_PROT_LOC_CRC_SEQ | | |
677 | CAN_ERR_PROT_LOC_CRC_DEL; | |
678 | priv->can.can_stats.bus_error++; | |
679 | stats->rx_errors++; | |
680 | break; | |
681 | case PCH_LEC_ALL: /* Written by CPU. No error status */ | |
682 | break; | |
b21d18b5 MO |
683 | } |
684 | ||
685 | priv->can.state = state; | |
686 | netif_rx(skb); | |
687 | ||
688 | stats->rx_packets++; | |
689 | stats->rx_bytes += cf->can_dlc; | |
690 | } | |
691 | ||
692 | static irqreturn_t pch_can_interrupt(int irq, void *dev_id) | |
693 | { | |
694 | struct net_device *ndev = (struct net_device *)dev_id; | |
695 | struct pch_can_priv *priv = netdev_priv(ndev); | |
696 | ||
697 | pch_can_set_int_enables(priv, PCH_CAN_NONE); | |
698 | ||
699 | napi_schedule(&priv->napi); | |
700 | ||
701 | return IRQ_HANDLED; | |
702 | } | |
703 | ||
704 | static int pch_can_rx_normal(struct net_device *ndev, u32 int_stat) | |
705 | { | |
706 | u32 reg; | |
707 | canid_t id; | |
708 | u32 ide; | |
709 | u32 rtr; | |
710 | int i, j, k; | |
711 | int rcv_pkts = 0; | |
712 | struct sk_buff *skb; | |
713 | struct can_frame *cf; | |
714 | struct pch_can_priv *priv = netdev_priv(ndev); | |
715 | struct net_device_stats *stats = &(priv->ndev->stats); | |
716 | ||
717 | /* Reading the messsage object from the Message RAM */ | |
8339a7ed T |
718 | iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask); |
719 | pch_can_check_if_busy(&priv->regs->ifregs[0].creq, int_stat); | |
b21d18b5 MO |
720 | |
721 | /* Reading the MCONT register. */ | |
8339a7ed | 722 | reg = ioread32(&priv->regs->ifregs[0].mcont); |
b21d18b5 MO |
723 | reg &= 0xffff; |
724 | ||
086b5650 | 725 | for (k = int_stat; !(reg & PCH_IF_MCONT_EOB); k++) { |
b21d18b5 | 726 | /* If MsgLost bit set. */ |
086b5650 | 727 | if (reg & PCH_IF_MCONT_MSGLOST) { |
b21d18b5 | 728 | dev_err(&priv->ndev->dev, "Msg Obj is overwritten.\n"); |
8339a7ed | 729 | pch_can_bit_clear(&priv->regs->ifregs[0].mcont, |
086b5650 T |
730 | PCH_IF_MCONT_MSGLOST); |
731 | iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL, | |
8339a7ed T |
732 | &priv->regs->ifregs[0].cmask); |
733 | pch_can_check_if_busy(&priv->regs->ifregs[0].creq, k); | |
b21d18b5 MO |
734 | |
735 | skb = alloc_can_err_skb(ndev, &cf); | |
736 | if (!skb) | |
737 | return -ENOMEM; | |
738 | ||
739 | priv->can.can_stats.error_passive++; | |
740 | priv->can.state = CAN_STATE_ERROR_PASSIVE; | |
741 | cf->can_id |= CAN_ERR_CRTL; | |
742 | cf->data[1] |= CAN_ERR_CRTL_RX_OVERFLOW; | |
743 | cf->data[2] |= CAN_ERR_PROT_OVERLOAD; | |
744 | stats->rx_packets++; | |
745 | stats->rx_bytes += cf->can_dlc; | |
746 | ||
747 | netif_receive_skb(skb); | |
748 | rcv_pkts++; | |
749 | goto RX_NEXT; | |
750 | } | |
086b5650 | 751 | if (!(reg & PCH_IF_MCONT_NEWDAT)) |
b21d18b5 MO |
752 | goto RX_NEXT; |
753 | ||
754 | skb = alloc_can_skb(priv->ndev, &cf); | |
755 | if (!skb) | |
756 | return -ENOMEM; | |
757 | ||
758 | /* Get Received data */ | |
8339a7ed T |
759 | ide = ((ioread32(&priv->regs->ifregs[0].id2)) & PCH_ID2_XTD) >> |
760 | 14; | |
b21d18b5 | 761 | if (ide) { |
8339a7ed T |
762 | id = (ioread32(&priv->regs->ifregs[0].id1) & 0xffff); |
763 | id |= (((ioread32(&priv->regs->ifregs[0].id2)) & | |
b21d18b5 MO |
764 | 0x1fff) << 16); |
765 | cf->can_id = (id & CAN_EFF_MASK) | CAN_EFF_FLAG; | |
766 | } else { | |
8339a7ed T |
767 | id = (((ioread32(&priv->regs->ifregs[0].id2)) & |
768 | (CAN_SFF_MASK << 2)) >> 2); | |
b21d18b5 MO |
769 | cf->can_id = (id & CAN_SFF_MASK); |
770 | } | |
771 | ||
8339a7ed | 772 | rtr = (ioread32(&priv->regs->ifregs[0].id2) & PCH_ID2_DIR); |
b21d18b5 MO |
773 | if (rtr) { |
774 | cf->can_dlc = 0; | |
775 | cf->can_id |= CAN_RTR_FLAG; | |
776 | } else { | |
15ffc8fd T |
777 | cf->can_dlc = |
778 | ((ioread32(&priv->regs->ifregs[0].mcont)) & 0x0f); | |
b21d18b5 MO |
779 | } |
780 | ||
781 | for (i = 0, j = 0; i < cf->can_dlc; j++) { | |
8339a7ed | 782 | reg = ioread32(&priv->regs->ifregs[0].dataa1 + j*4); |
b21d18b5 MO |
783 | cf->data[i++] = cpu_to_le32(reg & 0xff); |
784 | if (i == cf->can_dlc) | |
785 | break; | |
786 | cf->data[i++] = cpu_to_le32((reg >> 8) & 0xff); | |
787 | } | |
788 | ||
789 | netif_receive_skb(skb); | |
790 | rcv_pkts++; | |
791 | stats->rx_packets++; | |
792 | stats->rx_bytes += cf->can_dlc; | |
793 | ||
794 | if (k < PCH_FIFO_THRESH) { | |
086b5650 | 795 | iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL | |
8339a7ed | 796 | PCH_CMASK_ARB, &priv->regs->ifregs[0].cmask); |
b21d18b5 MO |
797 | |
798 | /* Clearing the Dir bit. */ | |
8339a7ed T |
799 | pch_can_bit_clear(&priv->regs->ifregs[0].id2, |
800 | PCH_ID2_DIR); | |
b21d18b5 MO |
801 | |
802 | /* Clearing NewDat & IntPnd */ | |
8339a7ed | 803 | pch_can_bit_clear(&priv->regs->ifregs[0].mcont, |
086b5650 | 804 | PCH_IF_MCONT_INTPND); |
8339a7ed | 805 | pch_can_check_if_busy(&priv->regs->ifregs[0].creq, k); |
b21d18b5 MO |
806 | } else if (k > PCH_FIFO_THRESH) { |
807 | pch_can_int_clr(priv, k); | |
808 | } else if (k == PCH_FIFO_THRESH) { | |
809 | int cnt; | |
810 | for (cnt = 0; cnt < PCH_FIFO_THRESH; cnt++) | |
811 | pch_can_int_clr(priv, cnt+1); | |
812 | } | |
813 | RX_NEXT: | |
814 | /* Reading the messsage object from the Message RAM */ | |
8339a7ed | 815 | iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask); |
15ffc8fd | 816 | pch_can_check_if_busy(&priv->regs->ifregs[0].creq, k); |
8339a7ed | 817 | reg = ioread32(&priv->regs->ifregs[0].mcont); |
b21d18b5 MO |
818 | } |
819 | ||
820 | return rcv_pkts; | |
821 | } | |
822 | static int pch_can_rx_poll(struct napi_struct *napi, int quota) | |
823 | { | |
824 | struct net_device *ndev = napi->dev; | |
825 | struct pch_can_priv *priv = netdev_priv(ndev); | |
826 | struct net_device_stats *stats = &(priv->ndev->stats); | |
827 | u32 dlc; | |
828 | u32 int_stat; | |
829 | int rcv_pkts = 0; | |
830 | u32 reg_stat; | |
b21d18b5 MO |
831 | |
832 | int_stat = pch_can_int_pending(priv); | |
833 | if (!int_stat) | |
834 | return 0; | |
835 | ||
836 | INT_STAT: | |
086b5650 | 837 | if (int_stat == PCH_STATUS_INT) { |
b21d18b5 MO |
838 | reg_stat = ioread32(&priv->regs->stat); |
839 | if (reg_stat & (PCH_BUS_OFF | PCH_LEC_ALL)) { | |
840 | if ((reg_stat & PCH_LEC_ALL) != PCH_LEC_ALL) | |
841 | pch_can_error(ndev, reg_stat); | |
842 | } | |
843 | ||
844 | if (reg_stat & PCH_TX_OK) { | |
8339a7ed T |
845 | iowrite32(PCH_CMASK_RX_TX_GET, |
846 | &priv->regs->ifregs[1].cmask); | |
847 | pch_can_check_if_busy(&priv->regs->ifregs[1].creq, | |
b21d18b5 | 848 | ioread32(&priv->regs->intr)); |
b21d18b5 MO |
849 | pch_can_bit_clear(&priv->regs->stat, PCH_TX_OK); |
850 | } | |
851 | ||
852 | if (reg_stat & PCH_RX_OK) | |
853 | pch_can_bit_clear(&priv->regs->stat, PCH_RX_OK); | |
854 | ||
855 | int_stat = pch_can_int_pending(priv); | |
086b5650 | 856 | if (int_stat == PCH_STATUS_INT) |
b21d18b5 MO |
857 | goto INT_STAT; |
858 | } | |
859 | ||
860 | MSG_OBJ: | |
15ffc8fd | 861 | if ((int_stat >= PCH_RX_OBJ_START) && (int_stat <= PCH_RX_OBJ_END)) { |
b21d18b5 | 862 | rcv_pkts = pch_can_rx_normal(ndev, int_stat); |
b21d18b5 MO |
863 | if (rcv_pkts < 0) |
864 | return 0; | |
15ffc8fd T |
865 | } else if ((int_stat >= PCH_TX_OBJ_START) && |
866 | (int_stat <= PCH_TX_OBJ_END)) { | |
867 | /* Handle transmission interrupt */ | |
868 | can_get_echo_skb(ndev, int_stat - PCH_RX_OBJ_END - 1); | |
15ffc8fd T |
869 | iowrite32(PCH_CMASK_RX_TX_GET | PCH_CMASK_CLRINTPND, |
870 | &priv->regs->ifregs[1].cmask); | |
871 | dlc = ioread32(&priv->regs->ifregs[1].mcont) & | |
872 | PCH_IF_MCONT_DLC; | |
873 | pch_can_check_if_busy(&priv->regs->ifregs[1].creq, int_stat); | |
15ffc8fd T |
874 | if (dlc > 8) |
875 | dlc = 8; | |
876 | stats->tx_bytes += dlc; | |
877 | stats->tx_packets++; | |
76d94b23 T |
878 | if (int_stat == PCH_TX_OBJ_END) |
879 | netif_wake_queue(ndev); | |
b21d18b5 MO |
880 | } |
881 | ||
882 | int_stat = pch_can_int_pending(priv); | |
086b5650 | 883 | if (int_stat == PCH_STATUS_INT) |
b21d18b5 MO |
884 | goto INT_STAT; |
885 | else if (int_stat >= 1 && int_stat <= 32) | |
886 | goto MSG_OBJ; | |
887 | ||
888 | napi_complete(napi); | |
889 | pch_can_set_int_enables(priv, PCH_CAN_ALL); | |
890 | ||
891 | return rcv_pkts; | |
892 | } | |
893 | ||
894 | static int pch_set_bittiming(struct net_device *ndev) | |
895 | { | |
896 | struct pch_can_priv *priv = netdev_priv(ndev); | |
897 | const struct can_bittiming *bt = &priv->can.bittiming; | |
898 | u32 canbit; | |
899 | u32 bepe; | |
900 | u32 brp; | |
901 | ||
902 | /* Setting the CCE bit for accessing the Can Timing register. */ | |
086b5650 | 903 | pch_can_bit_set(&priv->regs->cont, PCH_CTRL_CCE); |
b21d18b5 MO |
904 | |
905 | brp = (bt->tq) / (1000000000/PCH_CAN_CLK) - 1; | |
086b5650 T |
906 | canbit = brp & PCH_MSK_BITT_BRP; |
907 | canbit |= (bt->sjw - 1) << PCH_BIT_SJW; | |
908 | canbit |= (bt->phase_seg1 + bt->prop_seg - 1) << PCH_BIT_TSEG1; | |
909 | canbit |= (bt->phase_seg2 - 1) << PCH_BIT_TSEG2; | |
910 | bepe = (brp & PCH_MSK_BRPE_BRPE) >> PCH_BIT_BRPE_BRPE; | |
b21d18b5 MO |
911 | iowrite32(canbit, &priv->regs->bitt); |
912 | iowrite32(bepe, &priv->regs->brpe); | |
086b5650 | 913 | pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_CCE); |
b21d18b5 MO |
914 | |
915 | return 0; | |
916 | } | |
917 | ||
918 | static void pch_can_start(struct net_device *ndev) | |
919 | { | |
920 | struct pch_can_priv *priv = netdev_priv(ndev); | |
921 | ||
922 | if (priv->can.state != CAN_STATE_STOPPED) | |
923 | pch_can_reset(priv); | |
924 | ||
925 | pch_set_bittiming(ndev); | |
926 | pch_can_set_optmode(priv); | |
927 | ||
8339a7ed T |
928 | pch_can_set_tx_all(priv, 1); |
929 | pch_can_set_rx_all(priv, 1); | |
b21d18b5 MO |
930 | |
931 | /* Setting the CAN to run mode. */ | |
932 | pch_can_set_run_mode(priv, PCH_CAN_RUN); | |
933 | ||
934 | priv->can.state = CAN_STATE_ERROR_ACTIVE; | |
935 | ||
936 | return; | |
937 | } | |
938 | ||
939 | static int pch_can_do_set_mode(struct net_device *ndev, enum can_mode mode) | |
940 | { | |
941 | int ret = 0; | |
942 | ||
943 | switch (mode) { | |
944 | case CAN_MODE_START: | |
945 | pch_can_start(ndev); | |
946 | netif_wake_queue(ndev); | |
947 | break; | |
948 | default: | |
949 | ret = -EOPNOTSUPP; | |
950 | break; | |
951 | } | |
952 | ||
953 | return ret; | |
954 | } | |
955 | ||
956 | static int pch_can_open(struct net_device *ndev) | |
957 | { | |
958 | struct pch_can_priv *priv = netdev_priv(ndev); | |
959 | int retval; | |
960 | ||
961 | retval = pci_enable_msi(priv->dev); | |
962 | if (retval) { | |
963 | dev_info(&ndev->dev, "PCH CAN opened without MSI\n"); | |
964 | priv->use_msi = 0; | |
965 | } else { | |
966 | dev_info(&ndev->dev, "PCH CAN opened with MSI\n"); | |
967 | priv->use_msi = 1; | |
968 | } | |
969 | ||
970 | /* Regsitering the interrupt. */ | |
971 | retval = request_irq(priv->dev->irq, pch_can_interrupt, IRQF_SHARED, | |
972 | ndev->name, ndev); | |
973 | if (retval) { | |
974 | dev_err(&ndev->dev, "request_irq failed.\n"); | |
975 | goto req_irq_err; | |
976 | } | |
977 | ||
978 | /* Open common can device */ | |
979 | retval = open_candev(ndev); | |
980 | if (retval) { | |
981 | dev_err(ndev->dev.parent, "open_candev() failed %d\n", retval); | |
982 | goto err_open_candev; | |
983 | } | |
984 | ||
985 | pch_can_init(priv); | |
986 | pch_can_start(ndev); | |
987 | napi_enable(&priv->napi); | |
988 | netif_start_queue(ndev); | |
989 | ||
990 | return 0; | |
991 | ||
992 | err_open_candev: | |
993 | free_irq(priv->dev->irq, ndev); | |
994 | req_irq_err: | |
995 | if (priv->use_msi) | |
996 | pci_disable_msi(priv->dev); | |
997 | ||
998 | pch_can_release(priv); | |
999 | ||
1000 | return retval; | |
1001 | } | |
1002 | ||
1003 | static int pch_close(struct net_device *ndev) | |
1004 | { | |
1005 | struct pch_can_priv *priv = netdev_priv(ndev); | |
1006 | ||
1007 | netif_stop_queue(ndev); | |
1008 | napi_disable(&priv->napi); | |
1009 | pch_can_release(priv); | |
1010 | free_irq(priv->dev->irq, ndev); | |
1011 | if (priv->use_msi) | |
1012 | pci_disable_msi(priv->dev); | |
1013 | close_candev(ndev); | |
1014 | priv->can.state = CAN_STATE_STOPPED; | |
1015 | return 0; | |
1016 | } | |
1017 | ||
b21d18b5 MO |
1018 | static netdev_tx_t pch_xmit(struct sk_buff *skb, struct net_device *ndev) |
1019 | { | |
1020 | int i, j; | |
b21d18b5 MO |
1021 | struct pch_can_priv *priv = netdev_priv(ndev); |
1022 | struct can_frame *cf = (struct can_frame *)skb->data; | |
1023 | int tx_buffer_avail = 0; | |
1024 | ||
1025 | if (can_dropped_invalid_skb(ndev, skb)) | |
1026 | return NETDEV_TX_OK; | |
1027 | ||
76d94b23 T |
1028 | if (priv->tx_obj == PCH_TX_OBJ_END) { |
1029 | if (ioread32(&priv->regs->treq2) & PCH_TREQ2_TX_MASK) | |
1030 | netif_stop_queue(ndev); | |
b21d18b5 | 1031 | |
76d94b23 T |
1032 | tx_buffer_avail = priv->tx_obj; |
1033 | priv->tx_obj = PCH_TX_OBJ_START; | |
b21d18b5 MO |
1034 | } else { |
1035 | tx_buffer_avail = priv->tx_obj; | |
76d94b23 | 1036 | priv->tx_obj++; |
b21d18b5 | 1037 | } |
b21d18b5 | 1038 | |
b21d18b5 | 1039 | /* Reading the Msg Obj from the Msg RAM to the Interface register. */ |
8339a7ed T |
1040 | iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[1].cmask); |
1041 | pch_can_check_if_busy(&priv->regs->ifregs[1].creq, tx_buffer_avail); | |
b21d18b5 MO |
1042 | |
1043 | /* Setting the CMASK register. */ | |
8339a7ed | 1044 | pch_can_bit_set(&priv->regs->ifregs[1].cmask, PCH_CMASK_ALL); |
b21d18b5 MO |
1045 | |
1046 | /* If ID extended is set. */ | |
8339a7ed T |
1047 | pch_can_bit_clear(&priv->regs->ifregs[1].id1, 0xffff); |
1048 | pch_can_bit_clear(&priv->regs->ifregs[1].id2, 0x1fff | PCH_ID2_XTD); | |
b21d18b5 | 1049 | if (cf->can_id & CAN_EFF_FLAG) { |
8339a7ed T |
1050 | pch_can_bit_set(&priv->regs->ifregs[1].id1, |
1051 | cf->can_id & 0xffff); | |
1052 | pch_can_bit_set(&priv->regs->ifregs[1].id2, | |
086b5650 | 1053 | ((cf->can_id >> 16) & 0x1fff) | PCH_ID2_XTD); |
b21d18b5 | 1054 | } else { |
8339a7ed T |
1055 | pch_can_bit_set(&priv->regs->ifregs[1].id1, 0); |
1056 | pch_can_bit_set(&priv->regs->ifregs[1].id2, | |
b21d18b5 MO |
1057 | (cf->can_id & CAN_SFF_MASK) << 2); |
1058 | } | |
1059 | ||
1060 | /* If remote frame has to be transmitted.. */ | |
1061 | if (cf->can_id & CAN_RTR_FLAG) | |
8339a7ed | 1062 | pch_can_bit_clear(&priv->regs->ifregs[1].id2, PCH_ID2_DIR); |
b21d18b5 MO |
1063 | |
1064 | for (i = 0, j = 0; i < cf->can_dlc; j++) { | |
1065 | iowrite32(le32_to_cpu(cf->data[i++]), | |
8339a7ed | 1066 | (&priv->regs->ifregs[1].dataa1) + j*4); |
b21d18b5 MO |
1067 | if (i == cf->can_dlc) |
1068 | break; | |
1069 | iowrite32(le32_to_cpu(cf->data[i++] << 8), | |
8339a7ed | 1070 | (&priv->regs->ifregs[1].dataa1) + j*4); |
b21d18b5 MO |
1071 | } |
1072 | ||
15ffc8fd | 1073 | can_put_echo_skb(skb, ndev, tx_buffer_avail - PCH_RX_OBJ_END - 1); |
b21d18b5 MO |
1074 | |
1075 | /* Updating the size of the data. */ | |
8339a7ed T |
1076 | pch_can_bit_clear(&priv->regs->ifregs[1].mcont, 0x0f); |
1077 | pch_can_bit_set(&priv->regs->ifregs[1].mcont, cf->can_dlc); | |
b21d18b5 MO |
1078 | |
1079 | /* Clearing IntPend, NewDat & TxRqst */ | |
8339a7ed | 1080 | pch_can_bit_clear(&priv->regs->ifregs[1].mcont, |
086b5650 T |
1081 | PCH_IF_MCONT_NEWDAT | PCH_IF_MCONT_INTPND | |
1082 | PCH_IF_MCONT_TXRQXT); | |
b21d18b5 MO |
1083 | |
1084 | /* Setting NewDat, TxRqst bits */ | |
8339a7ed | 1085 | pch_can_bit_set(&priv->regs->ifregs[1].mcont, |
086b5650 | 1086 | PCH_IF_MCONT_NEWDAT | PCH_IF_MCONT_TXRQXT); |
b21d18b5 | 1087 | |
8339a7ed | 1088 | pch_can_check_if_busy(&priv->regs->ifregs[1].creq, tx_buffer_avail); |
b21d18b5 | 1089 | |
b21d18b5 MO |
1090 | return NETDEV_TX_OK; |
1091 | } | |
1092 | ||
1093 | static const struct net_device_ops pch_can_netdev_ops = { | |
1094 | .ndo_open = pch_can_open, | |
1095 | .ndo_stop = pch_close, | |
1096 | .ndo_start_xmit = pch_xmit, | |
1097 | }; | |
1098 | ||
1099 | static void __devexit pch_can_remove(struct pci_dev *pdev) | |
1100 | { | |
1101 | struct net_device *ndev = pci_get_drvdata(pdev); | |
1102 | struct pch_can_priv *priv = netdev_priv(ndev); | |
1103 | ||
1104 | unregister_candev(priv->ndev); | |
1105 | free_candev(priv->ndev); | |
1106 | pci_iounmap(pdev, priv->regs); | |
1107 | pci_release_regions(pdev); | |
1108 | pci_disable_device(pdev); | |
1109 | pci_set_drvdata(pdev, NULL); | |
1110 | pch_can_reset(priv); | |
1111 | } | |
1112 | ||
1113 | #ifdef CONFIG_PM | |
1114 | static int pch_can_suspend(struct pci_dev *pdev, pm_message_t state) | |
1115 | { | |
1116 | int i; /* Counter variable. */ | |
1117 | int retval; /* Return value. */ | |
1118 | u32 buf_stat; /* Variable for reading the transmit buffer status. */ | |
1119 | u32 counter = 0xFFFFFF; | |
1120 | ||
1121 | struct net_device *dev = pci_get_drvdata(pdev); | |
1122 | struct pch_can_priv *priv = netdev_priv(dev); | |
1123 | ||
1124 | /* Stop the CAN controller */ | |
1125 | pch_can_set_run_mode(priv, PCH_CAN_STOP); | |
1126 | ||
1127 | /* Indicate that we are aboutto/in suspend */ | |
1128 | priv->can.state = CAN_STATE_SLEEPING; | |
1129 | ||
1130 | /* Waiting for all transmission to complete. */ | |
1131 | while (counter) { | |
1132 | buf_stat = pch_can_get_buffer_status(priv); | |
1133 | if (!buf_stat) | |
1134 | break; | |
1135 | counter--; | |
1136 | udelay(1); | |
1137 | } | |
1138 | if (!counter) | |
1139 | dev_err(&pdev->dev, "%s -> Transmission time out.\n", __func__); | |
1140 | ||
1141 | /* Save interrupt configuration and then disable them */ | |
1142 | pch_can_get_int_enables(priv, &(priv->int_enables)); | |
1143 | pch_can_set_int_enables(priv, PCH_CAN_DISABLE); | |
1144 | ||
1145 | /* Save Tx buffer enable state */ | |
15ffc8fd T |
1146 | for (i = PCH_TX_OBJ_START; i <= PCH_TX_OBJ_END; i++) |
1147 | priv->tx_enable[i] = pch_can_get_rxtx_ir(priv, i, PCH_TX_IFREG); | |
b21d18b5 MO |
1148 | |
1149 | /* Disable all Transmit buffers */ | |
8339a7ed | 1150 | pch_can_set_tx_all(priv, 0); |
b21d18b5 MO |
1151 | |
1152 | /* Save Rx buffer enable state */ | |
15ffc8fd T |
1153 | for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++) { |
1154 | priv->rx_enable[i] = pch_can_get_rxtx_ir(priv, i, PCH_RX_IFREG); | |
1155 | pch_can_get_rx_buffer_link(priv, i, &priv->rx_link[i]); | |
b21d18b5 MO |
1156 | } |
1157 | ||
1158 | /* Disable all Receive buffers */ | |
8339a7ed | 1159 | pch_can_set_rx_all(priv, 0); |
b21d18b5 MO |
1160 | retval = pci_save_state(pdev); |
1161 | if (retval) { | |
1162 | dev_err(&pdev->dev, "pci_save_state failed.\n"); | |
1163 | } else { | |
1164 | pci_enable_wake(pdev, PCI_D3hot, 0); | |
1165 | pci_disable_device(pdev); | |
1166 | pci_set_power_state(pdev, pci_choose_state(pdev, state)); | |
1167 | } | |
1168 | ||
1169 | return retval; | |
1170 | } | |
1171 | ||
1172 | static int pch_can_resume(struct pci_dev *pdev) | |
1173 | { | |
1174 | int i; /* Counter variable. */ | |
1175 | int retval; /* Return variable. */ | |
1176 | struct net_device *dev = pci_get_drvdata(pdev); | |
1177 | struct pch_can_priv *priv = netdev_priv(dev); | |
1178 | ||
1179 | pci_set_power_state(pdev, PCI_D0); | |
1180 | pci_restore_state(pdev); | |
1181 | retval = pci_enable_device(pdev); | |
1182 | if (retval) { | |
1183 | dev_err(&pdev->dev, "pci_enable_device failed.\n"); | |
1184 | return retval; | |
1185 | } | |
1186 | ||
1187 | pci_enable_wake(pdev, PCI_D3hot, 0); | |
1188 | ||
1189 | priv->can.state = CAN_STATE_ERROR_ACTIVE; | |
1190 | ||
1191 | /* Disabling all interrupts. */ | |
1192 | pch_can_set_int_enables(priv, PCH_CAN_DISABLE); | |
1193 | ||
1194 | /* Setting the CAN device in Stop Mode. */ | |
1195 | pch_can_set_run_mode(priv, PCH_CAN_STOP); | |
1196 | ||
1197 | /* Configuring the transmit and receive buffers. */ | |
1198 | pch_can_config_rx_tx_buffers(priv); | |
1199 | ||
1200 | /* Restore the CAN state */ | |
1201 | pch_set_bittiming(dev); | |
1202 | ||
1203 | /* Listen/Active */ | |
1204 | pch_can_set_optmode(priv); | |
1205 | ||
1206 | /* Enabling the transmit buffer. */ | |
15ffc8fd T |
1207 | for (i = PCH_TX_OBJ_START; i <= PCH_TX_OBJ_END; i++) |
1208 | pch_can_set_rxtx(priv, i, priv->tx_enable[i], PCH_TX_IFREG); | |
b21d18b5 MO |
1209 | |
1210 | /* Configuring the receive buffer and enabling them. */ | |
15ffc8fd T |
1211 | for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++) { |
1212 | /* Restore buffer link */ | |
1213 | pch_can_set_rx_buffer_link(priv, i, priv->rx_link[i]); | |
b21d18b5 | 1214 | |
15ffc8fd T |
1215 | /* Restore buffer enables */ |
1216 | pch_can_set_rxtx(priv, i, priv->rx_enable[i], PCH_RX_IFREG); | |
b21d18b5 MO |
1217 | } |
1218 | ||
1219 | /* Enable CAN Interrupts */ | |
1220 | pch_can_set_int_custom(priv); | |
1221 | ||
1222 | /* Restore Run Mode */ | |
1223 | pch_can_set_run_mode(priv, PCH_CAN_RUN); | |
1224 | ||
1225 | return retval; | |
1226 | } | |
1227 | #else | |
1228 | #define pch_can_suspend NULL | |
1229 | #define pch_can_resume NULL | |
1230 | #endif | |
1231 | ||
1232 | static int pch_can_get_berr_counter(const struct net_device *dev, | |
1233 | struct can_berr_counter *bec) | |
1234 | { | |
1235 | struct pch_can_priv *priv = netdev_priv(dev); | |
1236 | ||
086b5650 T |
1237 | bec->txerr = ioread32(&priv->regs->errc) & PCH_TEC; |
1238 | bec->rxerr = (ioread32(&priv->regs->errc) & PCH_REC) >> 8; | |
b21d18b5 MO |
1239 | |
1240 | return 0; | |
1241 | } | |
1242 | ||
1243 | static int __devinit pch_can_probe(struct pci_dev *pdev, | |
1244 | const struct pci_device_id *id) | |
1245 | { | |
1246 | struct net_device *ndev; | |
1247 | struct pch_can_priv *priv; | |
1248 | int rc; | |
b21d18b5 MO |
1249 | void __iomem *addr; |
1250 | ||
1251 | rc = pci_enable_device(pdev); | |
1252 | if (rc) { | |
1253 | dev_err(&pdev->dev, "Failed pci_enable_device %d\n", rc); | |
1254 | goto probe_exit_endev; | |
1255 | } | |
1256 | ||
1257 | rc = pci_request_regions(pdev, KBUILD_MODNAME); | |
1258 | if (rc) { | |
1259 | dev_err(&pdev->dev, "Failed pci_request_regions %d\n", rc); | |
1260 | goto probe_exit_pcireq; | |
1261 | } | |
1262 | ||
1263 | addr = pci_iomap(pdev, 1, 0); | |
1264 | if (!addr) { | |
1265 | rc = -EIO; | |
1266 | dev_err(&pdev->dev, "Failed pci_iomap\n"); | |
1267 | goto probe_exit_ipmap; | |
1268 | } | |
1269 | ||
15ffc8fd | 1270 | ndev = alloc_candev(sizeof(struct pch_can_priv), PCH_TX_OBJ_END); |
b21d18b5 MO |
1271 | if (!ndev) { |
1272 | rc = -ENOMEM; | |
1273 | dev_err(&pdev->dev, "Failed alloc_candev\n"); | |
1274 | goto probe_exit_alloc_candev; | |
1275 | } | |
1276 | ||
1277 | priv = netdev_priv(ndev); | |
1278 | priv->ndev = ndev; | |
1279 | priv->regs = addr; | |
1280 | priv->dev = pdev; | |
1281 | priv->can.bittiming_const = &pch_can_bittiming_const; | |
1282 | priv->can.do_set_mode = pch_can_do_set_mode; | |
1283 | priv->can.do_get_berr_counter = pch_can_get_berr_counter; | |
1284 | priv->can.ctrlmode_supported = CAN_CTRLMODE_LISTENONLY | | |
1285 | CAN_CTRLMODE_LOOPBACK; | |
15ffc8fd | 1286 | priv->tx_obj = PCH_TX_OBJ_START; /* Point head of Tx Obj */ |
b21d18b5 MO |
1287 | |
1288 | ndev->irq = pdev->irq; | |
1289 | ndev->flags |= IFF_ECHO; | |
1290 | ||
1291 | pci_set_drvdata(pdev, ndev); | |
1292 | SET_NETDEV_DEV(ndev, &pdev->dev); | |
1293 | ndev->netdev_ops = &pch_can_netdev_ops; | |
b21d18b5 | 1294 | priv->can.clock.freq = PCH_CAN_CLK; /* Hz */ |
b21d18b5 | 1295 | |
15ffc8fd | 1296 | netif_napi_add(ndev, &priv->napi, pch_can_rx_poll, PCH_RX_OBJ_END); |
b21d18b5 MO |
1297 | |
1298 | rc = register_candev(ndev); | |
1299 | if (rc) { | |
1300 | dev_err(&pdev->dev, "Failed register_candev %d\n", rc); | |
1301 | goto probe_exit_reg_candev; | |
1302 | } | |
1303 | ||
1304 | return 0; | |
1305 | ||
1306 | probe_exit_reg_candev: | |
1307 | free_candev(ndev); | |
1308 | probe_exit_alloc_candev: | |
1309 | pci_iounmap(pdev, addr); | |
1310 | probe_exit_ipmap: | |
1311 | pci_release_regions(pdev); | |
1312 | probe_exit_pcireq: | |
1313 | pci_disable_device(pdev); | |
1314 | probe_exit_endev: | |
1315 | return rc; | |
1316 | } | |
1317 | ||
bdfa3d8f | 1318 | static struct pci_driver pch_can_pci_driver = { |
b21d18b5 MO |
1319 | .name = "pch_can", |
1320 | .id_table = pch_pci_tbl, | |
1321 | .probe = pch_can_probe, | |
1322 | .remove = __devexit_p(pch_can_remove), | |
1323 | .suspend = pch_can_suspend, | |
1324 | .resume = pch_can_resume, | |
1325 | }; | |
1326 | ||
1327 | static int __init pch_can_pci_init(void) | |
1328 | { | |
bdfa3d8f | 1329 | return pci_register_driver(&pch_can_pci_driver); |
b21d18b5 MO |
1330 | } |
1331 | module_init(pch_can_pci_init); | |
1332 | ||
1333 | static void __exit pch_can_pci_exit(void) | |
1334 | { | |
bdfa3d8f | 1335 | pci_unregister_driver(&pch_can_pci_driver); |
b21d18b5 MO |
1336 | } |
1337 | module_exit(pch_can_pci_exit); | |
1338 | ||
1339 | MODULE_DESCRIPTION("Controller Area Network Driver"); | |
1340 | MODULE_LICENSE("GPL v2"); | |
1341 | MODULE_VERSION("0.94"); |