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pch_can: Fix coding rule violation
[deliverable/linux.git] / drivers / net / can / pch_can.c
CommitLineData
b21d18b5
MO		 1/*
2 * Copyright (C) 1999 - 2010 Intel Corporation.
e91530ea 3 * Copyright (C) 2010 OKI SEMICONDUCTOR CO., LTD.
b21d18b5
MO		 4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; version 2 of the License.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
17 */
18
19#include <linux/interrupt.h>
20#include <linux/delay.h>
21#include <linux/io.h>
22#include <linux/module.h>
23#include <linux/sched.h>
24#include <linux/pci.h>
25#include <linux/init.h>
26#include <linux/kernel.h>
27#include <linux/types.h>
28#include <linux/errno.h>
29#include <linux/netdevice.h>
30#include <linux/skbuff.h>
31#include <linux/can.h>
32#include <linux/can/dev.h>
33#include <linux/can/error.h>
34
0a80410d
T		 35#define PCH_CTRL_INIT BIT(0) /* The INIT bit of CANCONT register. */
36#define PCH_CTRL_IE BIT(1) /* The IE bit of CAN control register */
37#define PCH_CTRL_IE_SIE_EIE (BIT(3) | BIT(2) | BIT(1))
38#define PCH_CTRL_CCE BIT(6)
39#define PCH_CTRL_OPT BIT(7) /* The OPT bit of CANCONT register. */
40#define PCH_OPT_SILENT BIT(3) /* The Silent bit of CANOPT reg. */
41#define PCH_OPT_LBACK BIT(4) /* The LoopBack bit of CANOPT reg. */
42
086b5650
T		 43#define PCH_CMASK_RX_TX_SET 0x00f3
44#define PCH_CMASK_RX_TX_GET 0x0073
45#define PCH_CMASK_ALL 0xff
0a80410d
T		 46#define PCH_CMASK_NEWDAT BIT(2)
47#define PCH_CMASK_CLRINTPND BIT(3)
48#define PCH_CMASK_CTRL BIT(4)
49#define PCH_CMASK_ARB BIT(5)
50#define PCH_CMASK_MASK BIT(6)
51#define PCH_CMASK_RDWR BIT(7)
52#define PCH_IF_MCONT_NEWDAT BIT(15)
53#define PCH_IF_MCONT_MSGLOST BIT(14)
54#define PCH_IF_MCONT_INTPND BIT(13)
55#define PCH_IF_MCONT_UMASK BIT(12)
56#define PCH_IF_MCONT_TXIE BIT(11)
57#define PCH_IF_MCONT_RXIE BIT(10)
58#define PCH_IF_MCONT_RMTEN BIT(9)
59#define PCH_IF_MCONT_TXRQXT BIT(8)
60#define PCH_IF_MCONT_EOB BIT(7)
61#define PCH_IF_MCONT_DLC (BIT(0) | BIT(1) | BIT(2) | BIT(3))
62#define PCH_MASK2_MDIR_MXTD (BIT(14) | BIT(15))
63#define PCH_ID2_DIR BIT(13)
64#define PCH_ID2_XTD BIT(14)
65#define PCH_ID_MSGVAL BIT(15)
66#define PCH_IF_CREQ_BUSY BIT(15)
086b5650
T		 67
68#define PCH_STATUS_INT 0x8000
69#define PCH_REC 0x00007f00
70#define PCH_TEC 0x000000ff
b21d18b5 71
0a80410d
T		 72#define PCH_TX_OK BIT(3)
73#define PCH_RX_OK BIT(4)
74#define PCH_EPASSIV BIT(5)
75#define PCH_EWARN BIT(6)
76#define PCH_BUS_OFF BIT(7)
b21d18b5
MO		 77
78/* bit position of certain controller bits. */
bd58cbc3
T		 79#define PCH_BIT_BRP_SHIFT 0
80#define PCH_BIT_SJW_SHIFT 6
81#define PCH_BIT_TSEG1_SHIFT 8
82#define PCH_BIT_TSEG2_SHIFT 12
83#define PCH_BIT_BRPE_BRPE_SHIFT 6
84
086b5650
T		 85#define PCH_MSK_BITT_BRP 0x3f
86#define PCH_MSK_BRPE_BRPE 0x3c0
87#define PCH_MSK_CTRL_IE_SIE_EIE 0x07
88#define PCH_COUNTER_LIMIT 10
b21d18b5
MO		 89
90#define PCH_CAN_CLK 50000000 /* 50MHz */
91
9388b166
T		 92/*
93 * Define the number of message object.
b21d18b5 94 * PCH CAN communications are done via Message RAM.
9388b166
T		 95 * The Message RAM consists of 32 message objects.
96 */
15ffc8fd
T		 97#define PCH_RX_OBJ_NUM 26
98#define PCH_TX_OBJ_NUM 6
99#define PCH_RX_OBJ_START 1
100#define PCH_RX_OBJ_END PCH_RX_OBJ_NUM
101#define PCH_TX_OBJ_START (PCH_RX_OBJ_END + 1)
102#define PCH_TX_OBJ_END (PCH_RX_OBJ_NUM + PCH_TX_OBJ_NUM)
b21d18b5
MO		 103
104#define PCH_FIFO_THRESH 16
105
76d94b23
T		 106/* TxRqst2 show status of MsgObjNo.17~32 */
107#define PCH_TREQ2_TX_MASK (((1 << PCH_TX_OBJ_NUM) - 1) <<\
108 (PCH_RX_OBJ_END - 16))
109
8339a7ed
T		 110enum pch_ifreg {
111 PCH_RX_IFREG,
112 PCH_TX_IFREG,
113};
114
d68f6837
T		 115enum pch_can_err {
116 PCH_STUF_ERR = 1,
117 PCH_FORM_ERR,
118 PCH_ACK_ERR,
119 PCH_BIT1_ERR,
120 PCH_BIT0_ERR,
121 PCH_CRC_ERR,
122 PCH_LEC_ALL,
123};
124
b21d18b5
MO		 125enum pch_can_mode {
126 PCH_CAN_ENABLE,
127 PCH_CAN_DISABLE,
128 PCH_CAN_ALL,
129 PCH_CAN_NONE,
130 PCH_CAN_STOP,
9388b166 131 PCH_CAN_RUN,
b21d18b5
MO		 132};
133
8339a7ed
T		 134struct pch_can_if_regs {
135 u32 creq;
136 u32 cmask;
137 u32 mask1;
138 u32 mask2;
139 u32 id1;
140 u32 id2;
141 u32 mcont;
8ac9702b 142 u32 data[4];
8339a7ed
T		 143 u32 rsv[13];
144};
145
b21d18b5
MO		 146struct pch_can_regs {
147 u32 cont;
148 u32 stat;
149 u32 errc;
150 u32 bitt;
151 u32 intr;
152 u32 opt;
153 u32 brpe;
8339a7ed
T		 154 u32 reserve;
155 struct pch_can_if_regs ifregs[2]; /* [0]=if1 [1]=if2 */
156 u32 reserve1[8];
b21d18b5
MO		 157 u32 treq1;
158 u32 treq2;
8339a7ed
T		 159 u32 reserve2[6];
160 u32 data1;
161 u32 data2;
162 u32 reserve3[6];
163 u32 canipend1;
164 u32 canipend2;
165 u32 reserve4[6];
166 u32 canmval1;
167 u32 canmval2;
168 u32 reserve5[37];
b21d18b5
MO		 169 u32 srst;
170};
171
172struct pch_can_priv {
173 struct can_priv can;
b21d18b5 174 struct pci_dev *dev;
bd58cbc3
T		 175 u32 tx_enable[PCH_TX_OBJ_END];
176 u32 rx_enable[PCH_TX_OBJ_END];
177 u32 rx_link[PCH_TX_OBJ_END];
178 u32 int_enables;
b21d18b5 179 struct net_device *ndev;
b21d18b5
MO		 180 struct pch_can_regs __iomem *regs;
181 struct napi_struct napi;
bd58cbc3
T		 182 int tx_obj; /* Point next Tx Obj index */
183 int use_msi;
b21d18b5
MO		 184};
185
186static struct can_bittiming_const pch_can_bittiming_const = {
187 .name = KBUILD_MODNAME,
188 .tseg1_min = 1,
189 .tseg1_max = 16,
190 .tseg2_min = 1,
191 .tseg2_max = 8,
192 .sjw_max = 4,
193 .brp_min = 1,
194 .brp_max = 1024, /* 6bit + extended 4bit */
195 .brp_inc = 1,
196};
197
198static DEFINE_PCI_DEVICE_TABLE(pch_pci_tbl) = {
199 {PCI_VENDOR_ID_INTEL, 0x8818, PCI_ANY_ID, PCI_ANY_ID,},
200 {0,}
201};
202MODULE_DEVICE_TABLE(pci, pch_pci_tbl);
203
526de53c 204static inline void pch_can_bit_set(void __iomem *addr, u32 mask)
b21d18b5
MO		 205{
206 iowrite32(ioread32(addr) | mask, addr);
207}
208
526de53c 209static inline void pch_can_bit_clear(void __iomem *addr, u32 mask)
b21d18b5
MO		 210{
211 iowrite32(ioread32(addr) & ~mask, addr);
212}
213
214static void pch_can_set_run_mode(struct pch_can_priv *priv,
215 enum pch_can_mode mode)
216{
217 switch (mode) {
218 case PCH_CAN_RUN:
086b5650 219 pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_INIT);
b21d18b5
MO		 220 break;
221
222 case PCH_CAN_STOP:
086b5650 223 pch_can_bit_set(&priv->regs->cont, PCH_CTRL_INIT);
b21d18b5
MO		 224 break;
225
226 default:
435b4efe 227 netdev_err(priv->ndev, "%s -> Invalid Mode.\n", __func__);
b21d18b5
MO		 228 break;
229 }
230}
231
232static void pch_can_set_optmode(struct pch_can_priv *priv)
233{
234 u32 reg_val = ioread32(&priv->regs->opt);
235
236 if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
086b5650 237 reg_val |= PCH_OPT_SILENT;
b21d18b5
MO		 238
239 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
086b5650 240 reg_val |= PCH_OPT_LBACK;
b21d18b5 241
086b5650 242 pch_can_bit_set(&priv->regs->cont, PCH_CTRL_OPT);
b21d18b5
MO		 243 iowrite32(reg_val, &priv->regs->opt);
244}
245
bd58cbc3
T		 246static void pch_can_rw_msg_obj(void __iomem *creq_addr, u32 num)
247{
248 int counter = PCH_COUNTER_LIMIT;
249 u32 ifx_creq;
250
251 iowrite32(num, creq_addr);
252 while (counter) {
253 ifx_creq = ioread32(creq_addr) & PCH_IF_CREQ_BUSY;
254 if (!ifx_creq)
255 break;
256 counter--;
257 udelay(1);
258 }
259 if (!counter)
260 pr_err("%s:IF1 BUSY Flag is set forever.\n", __func__);
261}
262
b21d18b5
MO		 263static void pch_can_set_int_enables(struct pch_can_priv *priv,
264 enum pch_can_mode interrupt_no)
265{
266 switch (interrupt_no) {
b21d18b5 267 case PCH_CAN_DISABLE:
086b5650 268 pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_IE);
b21d18b5
MO		 269 break;
270
271 case PCH_CAN_ALL:
086b5650 272 pch_can_bit_set(&priv->regs->cont, PCH_CTRL_IE_SIE_EIE);
b21d18b5
MO		 273 break;
274
275 case PCH_CAN_NONE:
086b5650 276 pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_IE_SIE_EIE);
b21d18b5
MO		 277 break;
278
279 default:
435b4efe 280 netdev_err(priv->ndev, "Invalid interrupt number.\n");
b21d18b5
MO		 281 break;
282 }
283}
284
8339a7ed 285static void pch_can_set_rxtx(struct pch_can_priv *priv, u32 buff_num,
bd58cbc3 286 int set, enum pch_ifreg dir)
b21d18b5 287{
8339a7ed
T		 288 u32 ie;
289
290 if (dir)
291 ie = PCH_IF_MCONT_TXIE;
292 else
293 ie = PCH_IF_MCONT_RXIE;
b21d18b5 294
9388b166 295 /* Reading the receive buffer data from RAM to Interface1/2 registers */
8339a7ed 296 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[dir].cmask);
bd58cbc3 297 pch_can_rw_msg_obj(&priv->regs->ifregs[dir].creq, buff_num);
b21d18b5 298
9388b166 299 /* Setting the IF1/2MASK1 register to access MsgVal and RxIE bits */
086b5650 300 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_ARB | PCH_CMASK_CTRL,
8339a7ed 301 &priv->regs->ifregs[dir].cmask);
b21d18b5 302
bd58cbc3 303 if (set) {
9388b166 304 /* Setting the MsgVal and RxIE/TxIE bits */
8339a7ed
T		 305 pch_can_bit_set(&priv->regs->ifregs[dir].mcont, ie);
306 pch_can_bit_set(&priv->regs->ifregs[dir].id2, PCH_ID_MSGVAL);
bd58cbc3 307 } else {
9388b166 308 /* Clearing the MsgVal and RxIE/TxIE bits */
8339a7ed
T		 309 pch_can_bit_clear(&priv->regs->ifregs[dir].mcont, ie);
310 pch_can_bit_clear(&priv->regs->ifregs[dir].id2, PCH_ID_MSGVAL);
b21d18b5
MO		 311 }
312
bd58cbc3 313 pch_can_rw_msg_obj(&priv->regs->ifregs[dir].creq, buff_num);
b21d18b5
MO		 314}
315
bd58cbc3 316static void pch_can_set_rx_all(struct pch_can_priv *priv, int set)
b21d18b5
MO		 317{
318 int i;
319
320 /* Traversing to obtain the object configured as receivers. */
15ffc8fd
T		 321 for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++)
322 pch_can_set_rxtx(priv, i, set, PCH_RX_IFREG);
b21d18b5
MO		 323}
324
bd58cbc3 325static void pch_can_set_tx_all(struct pch_can_priv *priv, int set)
b21d18b5
MO		 326{
327 int i;
328
329 /* Traversing to obtain the object configured as transmit object. */
15ffc8fd
T		 330 for (i = PCH_TX_OBJ_START; i <= PCH_TX_OBJ_END; i++)
331 pch_can_set_rxtx(priv, i, set, PCH_TX_IFREG);
b21d18b5
MO		 332}
333
bd58cbc3 334static u32 pch_can_int_pending(struct pch_can_priv *priv)
b21d18b5
MO		 335{
336 return ioread32(&priv->regs->intr) & 0xffff;
337}
338
bd58cbc3 339static void pch_can_clear_if_buffers(struct pch_can_priv *priv)
b21d18b5 340{
bd58cbc3 341 int i; /* Msg Obj ID (1~32) */
b21d18b5 342
bd58cbc3 343 for (i = PCH_RX_OBJ_START; i <= PCH_TX_OBJ_END; i++) {
8339a7ed
T		 344 iowrite32(PCH_CMASK_RX_TX_SET, &priv->regs->ifregs[0].cmask);
345 iowrite32(0xffff, &priv->regs->ifregs[0].mask1);
346 iowrite32(0xffff, &priv->regs->ifregs[0].mask2);
347 iowrite32(0x0, &priv->regs->ifregs[0].id1);
348 iowrite32(0x0, &priv->regs->ifregs[0].id2);
349 iowrite32(0x0, &priv->regs->ifregs[0].mcont);
8ac9702b
T		 350 iowrite32(0x0, &priv->regs->ifregs[0].data[0]);
351 iowrite32(0x0, &priv->regs->ifregs[0].data[1]);
352 iowrite32(0x0, &priv->regs->ifregs[0].data[2]);
353 iowrite32(0x0, &priv->regs->ifregs[0].data[3]);
086b5650
T		 354 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_MASK |
355 PCH_CMASK_ARB | PCH_CMASK_CTRL,
8339a7ed 356 &priv->regs->ifregs[0].cmask);
bd58cbc3 357 pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, i);
b21d18b5
MO		 358 }
359}
360
361static void pch_can_config_rx_tx_buffers(struct pch_can_priv *priv)
362{
363 int i;
b21d18b5 364
15ffc8fd 365 for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++) {
9388b166 366 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask);
bd58cbc3 367 pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, i);
b21d18b5 368
15ffc8fd
T		 369 iowrite32(0x0, &priv->regs->ifregs[0].id1);
370 iowrite32(0x0, &priv->regs->ifregs[0].id2);
b21d18b5 371
15ffc8fd
T		 372 pch_can_bit_set(&priv->regs->ifregs[0].mcont,
373 PCH_IF_MCONT_UMASK);
b21d18b5 374
15ffc8fd
T		 375 /* In case FIFO mode, Last EoB of Rx Obj must be 1 */
376 if (i == PCH_RX_OBJ_END)
377 pch_can_bit_set(&priv->regs->ifregs[0].mcont,
bd58cbc3
T		 378 PCH_IF_MCONT_EOB);
379 else
380 pch_can_bit_clear(&priv->regs->ifregs[0].mcont,
086b5650 381 PCH_IF_MCONT_EOB);
b21d18b5 382
15ffc8fd
T		 383 iowrite32(0, &priv->regs->ifregs[0].mask1);
384 pch_can_bit_clear(&priv->regs->ifregs[0].mask2,
385 0x1fff | PCH_MASK2_MDIR_MXTD);
b21d18b5 386
15ffc8fd 387 /* Setting CMASK for writing */
9388b166
T		 388 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_MASK | PCH_CMASK_ARB |
389 PCH_CMASK_CTRL, &priv->regs->ifregs[0].cmask);
b21d18b5 390
bd58cbc3 391 pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, i);
15ffc8fd 392 }
b21d18b5 393
15ffc8fd 394 for (i = PCH_TX_OBJ_START; i <= PCH_TX_OBJ_END; i++) {
9388b166 395 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[1].cmask);
bd58cbc3 396 pch_can_rw_msg_obj(&priv->regs->ifregs[1].creq, i);
b21d18b5 397
15ffc8fd
T		 398 /* Resetting DIR bit for reception */
399 iowrite32(0x0, &priv->regs->ifregs[1].id1);
44c9aa89 400 iowrite32(PCH_ID2_DIR, &priv->regs->ifregs[1].id2);
b21d18b5 401
15ffc8fd 402 /* Setting EOB bit for transmitter */
44c9aa89
T		 403 iowrite32(PCH_IF_MCONT_EOB | PCH_IF_MCONT_UMASK,
404 &priv->regs->ifregs[1].mcont);
15ffc8fd
T		 405
406 iowrite32(0, &priv->regs->ifregs[1].mask1);
407 pch_can_bit_clear(&priv->regs->ifregs[1].mask2, 0x1fff);
408
409 /* Setting CMASK for writing */
9388b166
T		 410 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_MASK | PCH_CMASK_ARB |
411 PCH_CMASK_CTRL, &priv->regs->ifregs[1].cmask);
15ffc8fd 412
bd58cbc3 413 pch_can_rw_msg_obj(&priv->regs->ifregs[1].creq, i);
b21d18b5 414 }
b21d18b5
MO		 415}
416
417static void pch_can_init(struct pch_can_priv *priv)
418{
419 /* Stopping the Can device. */
420 pch_can_set_run_mode(priv, PCH_CAN_STOP);
421
422 /* Clearing all the message object buffers. */
bd58cbc3 423 pch_can_clear_if_buffers(priv);
b21d18b5
MO		 424
425 /* Configuring the respective message object as either rx/tx object. */
426 pch_can_config_rx_tx_buffers(priv);
427
428 /* Enabling the interrupts. */
429 pch_can_set_int_enables(priv, PCH_CAN_ALL);
430}
431
432static void pch_can_release(struct pch_can_priv *priv)
433{
434 /* Stooping the CAN device. */
435 pch_can_set_run_mode(priv, PCH_CAN_STOP);
436
437 /* Disabling the interrupts. */
438 pch_can_set_int_enables(priv, PCH_CAN_NONE);
439
440 /* Disabling all the receive object. */
8339a7ed 441 pch_can_set_rx_all(priv, 0);
b21d18b5
MO		 442
443 /* Disabling all the transmit object. */
8339a7ed 444 pch_can_set_tx_all(priv, 0);
b21d18b5
MO		 445}
446
447/* This function clears interrupt(s) from the CAN device. */
448static void pch_can_int_clr(struct pch_can_priv *priv, u32 mask)
449{
086b5650 450 if (mask == PCH_STATUS_INT) {
b21d18b5
MO		 451 ioread32(&priv->regs->stat);
452 return;
453 }
454
455 /* Clear interrupt for transmit object */
15ffc8fd
T		 456 if ((mask >= PCH_RX_OBJ_START) && (mask <= PCH_RX_OBJ_END)) {
457 /* Setting CMASK for clearing the reception interrupts. */
458 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL | PCH_CMASK_ARB,
459 &priv->regs->ifregs[0].cmask);
460
461 /* Clearing the Dir bit. */
462 pch_can_bit_clear(&priv->regs->ifregs[0].id2, PCH_ID2_DIR);
463
464 /* Clearing NewDat & IntPnd */
465 pch_can_bit_clear(&priv->regs->ifregs[0].mcont,
466 PCH_IF_MCONT_NEWDAT | PCH_IF_MCONT_INTPND);
467
bd58cbc3 468 pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, mask);
15ffc8fd 469 } else if ((mask >= PCH_TX_OBJ_START) && (mask <= PCH_TX_OBJ_END)) {
9388b166
T		 470 /*
471 * Setting CMASK for clearing interrupts for frame transmission.
472 */
086b5650 473 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL | PCH_CMASK_ARB,
8339a7ed 474 &priv->regs->ifregs[1].cmask);
b21d18b5
MO		 475
476 /* Resetting the ID registers. */
8339a7ed 477 pch_can_bit_set(&priv->regs->ifregs[1].id2,
086b5650 478 PCH_ID2_DIR | (0x7ff << 2));
8339a7ed 479 iowrite32(0x0, &priv->regs->ifregs[1].id1);
b21d18b5
MO		 480
481 /* Claring NewDat, TxRqst & IntPnd */
8339a7ed 482 pch_can_bit_clear(&priv->regs->ifregs[1].mcont,
086b5650
T		 483 PCH_IF_MCONT_NEWDAT | PCH_IF_MCONT_INTPND |
484 PCH_IF_MCONT_TXRQXT);
bd58cbc3 485 pch_can_rw_msg_obj(&priv->regs->ifregs[1].creq, mask);
b21d18b5
MO		 486 }
487}
488
b21d18b5
MO		 489static void pch_can_reset(struct pch_can_priv *priv)
490{
491 /* write to sw reset register */
492 iowrite32(1, &priv->regs->srst);
493 iowrite32(0, &priv->regs->srst);
494}
495
496static void pch_can_error(struct net_device *ndev, u32 status)
497{
498 struct sk_buff *skb;
499 struct pch_can_priv *priv = netdev_priv(ndev);
500 struct can_frame *cf;
d68f6837 501 u32 errc, lec;
b21d18b5
MO		 502 struct net_device_stats *stats = &(priv->ndev->stats);
503 enum can_state state = priv->can.state;
504
505 skb = alloc_can_err_skb(ndev, &cf);
506 if (!skb)
507 return;
508
509 if (status & PCH_BUS_OFF) {
8339a7ed
T		 510 pch_can_set_tx_all(priv, 0);
511 pch_can_set_rx_all(priv, 0);
b21d18b5
MO		 512 state = CAN_STATE_BUS_OFF;
513 cf->can_id |= CAN_ERR_BUSOFF;
514 can_bus_off(ndev);
515 pch_can_set_run_mode(priv, PCH_CAN_RUN);
516 dev_err(&ndev->dev, "%s -> Bus Off occurres.\n", __func__);
517 }
518
44c9aa89 519 errc = ioread32(&priv->regs->errc);
b21d18b5
MO		 520 /* Warning interrupt. */
521 if (status & PCH_EWARN) {
522 state = CAN_STATE_ERROR_WARNING;
523 priv->can.can_stats.error_warning++;
524 cf->can_id |= CAN_ERR_CRTL;
086b5650 525 if (((errc & PCH_REC) >> 8) > 96)
b21d18b5 526 cf->data[1] |= CAN_ERR_CRTL_RX_WARNING;
086b5650 527 if ((errc & PCH_TEC) > 96)
b21d18b5 528 cf->data[1] |= CAN_ERR_CRTL_TX_WARNING;
435b4efe 529 netdev_dbg(ndev,
b21d18b5
MO		 530 "%s -> Error Counter is more than 96.\n", __func__);
531 }
532 /* Error passive interrupt. */
533 if (status & PCH_EPASSIV) {
534 priv->can.can_stats.error_passive++;
535 state = CAN_STATE_ERROR_PASSIVE;
536 cf->can_id |= CAN_ERR_CRTL;
086b5650 537 if (((errc & PCH_REC) >> 8) > 127)
b21d18b5 538 cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE;
086b5650 539 if ((errc & PCH_TEC) > 127)
b21d18b5 540 cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE;
435b4efe 541 netdev_dbg(ndev,
b21d18b5
MO		 542 "%s -> CAN controller is ERROR PASSIVE .\n", __func__);
543 }
544
d68f6837
T		 545 lec = status & PCH_LEC_ALL;
546 switch (lec) {
547 case PCH_STUF_ERR:
548 cf->data[2] |= CAN_ERR_PROT_STUFF;
b21d18b5
MO		 549 priv->can.can_stats.bus_error++;
550 stats->rx_errors++;
d68f6837
T		 551 break;
552 case PCH_FORM_ERR:
553 cf->data[2] |= CAN_ERR_PROT_FORM;
554 priv->can.can_stats.bus_error++;
555 stats->rx_errors++;
556 break;
557 case PCH_ACK_ERR:
558 cf->can_id |= CAN_ERR_ACK;
559 priv->can.can_stats.bus_error++;
560 stats->rx_errors++;
561 break;
562 case PCH_BIT1_ERR:
563 case PCH_BIT0_ERR:
564 cf->data[2] |= CAN_ERR_PROT_BIT;
565 priv->can.can_stats.bus_error++;
566 stats->rx_errors++;
567 break;
568 case PCH_CRC_ERR:
569 cf->data[2] |= CAN_ERR_PROT_LOC_CRC_SEQ |
570 CAN_ERR_PROT_LOC_CRC_DEL;
571 priv->can.can_stats.bus_error++;
572 stats->rx_errors++;
573 break;
574 case PCH_LEC_ALL: /* Written by CPU. No error status */
575 break;
b21d18b5
MO		 576 }
577
578 priv->can.state = state;
579 netif_rx(skb);
580
581 stats->rx_packets++;
582 stats->rx_bytes += cf->can_dlc;
583}
584
585static irqreturn_t pch_can_interrupt(int irq, void *dev_id)
586{
587 struct net_device *ndev = (struct net_device *)dev_id;
588 struct pch_can_priv *priv = netdev_priv(ndev);
589
590 pch_can_set_int_enables(priv, PCH_CAN_NONE);
b21d18b5
MO		 591 napi_schedule(&priv->napi);
592
593 return IRQ_HANDLED;
594}
595
1d5b4b27
T		 596static void pch_fifo_thresh(struct pch_can_priv *priv, int obj_id)
597{
598 if (obj_id < PCH_FIFO_THRESH) {
599 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL |
600 PCH_CMASK_ARB, &priv->regs->ifregs[0].cmask);
601
602 /* Clearing the Dir bit. */
603 pch_can_bit_clear(&priv->regs->ifregs[0].id2, PCH_ID2_DIR);
604
605 /* Clearing NewDat & IntPnd */
606 pch_can_bit_clear(&priv->regs->ifregs[0].mcont,
607 PCH_IF_MCONT_INTPND);
bd58cbc3 608 pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, obj_id);
1d5b4b27
T		 609 } else if (obj_id > PCH_FIFO_THRESH) {
610 pch_can_int_clr(priv, obj_id);
611 } else if (obj_id == PCH_FIFO_THRESH) {
612 int cnt;
613 for (cnt = 0; cnt < PCH_FIFO_THRESH; cnt++)
614 pch_can_int_clr(priv, cnt + 1);
615 }
616}
617
618static void pch_can_rx_msg_lost(struct net_device *ndev, int obj_id)
619{
620 struct pch_can_priv *priv = netdev_priv(ndev);
621 struct net_device_stats *stats = &(priv->ndev->stats);
622 struct sk_buff *skb;
623 struct can_frame *cf;
624
625 netdev_dbg(priv->ndev, "Msg Obj is overwritten.\n");
626 pch_can_bit_clear(&priv->regs->ifregs[0].mcont,
627 PCH_IF_MCONT_MSGLOST);
628 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL,
629 &priv->regs->ifregs[0].cmask);
bd58cbc3 630 pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, obj_id);
1d5b4b27
T		 631
632 skb = alloc_can_err_skb(ndev, &cf);
633 if (!skb)
634 return;
635
636 cf->can_id |= CAN_ERR_CRTL;
637 cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
638 stats->rx_over_errors++;
639 stats->rx_errors++;
640
641 netif_receive_skb(skb);
642}
643
644static int pch_can_rx_normal(struct net_device *ndev, u32 obj_num, int quota)
b21d18b5
MO		 645{
646 u32 reg;
647 canid_t id;
b21d18b5
MO		 648 int rcv_pkts = 0;
649 struct sk_buff *skb;
650 struct can_frame *cf;
651 struct pch_can_priv *priv = netdev_priv(ndev);
652 struct net_device_stats *stats = &(priv->ndev->stats);
1d5b4b27
T		 653 int i;
654 u32 id2;
8ac9702b 655 u16 data_reg;
b21d18b5 656
1d5b4b27
T		 657 do {
658 /* Reading the messsage object from the Message RAM */
659 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask);
bd58cbc3 660 pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, obj_num);
b21d18b5 661
1d5b4b27
T		 662 /* Reading the MCONT register. */
663 reg = ioread32(&priv->regs->ifregs[0].mcont);
664
665 if (reg & PCH_IF_MCONT_EOB)
666 break;
b21d18b5 667
b21d18b5 668 /* If MsgLost bit set. */
086b5650 669 if (reg & PCH_IF_MCONT_MSGLOST) {
1d5b4b27 670 pch_can_rx_msg_lost(ndev, obj_num);
b21d18b5 671 rcv_pkts++;
1d5b4b27
T		 672 quota--;
673 obj_num++;
674 continue;
675 } else if (!(reg & PCH_IF_MCONT_NEWDAT)) {
676 obj_num++;
677 continue;
b21d18b5 678 }
b21d18b5
MO		 679
680 skb = alloc_can_skb(priv->ndev, &cf);
681 if (!skb)
682 return -ENOMEM;
683
684 /* Get Received data */
1d5b4b27
T		 685 id2 = ioread32(&priv->regs->ifregs[0].id2);
686 if (id2 & PCH_ID2_XTD) {
8339a7ed 687 id = (ioread32(&priv->regs->ifregs[0].id1) & 0xffff);
1d5b4b27
T		 688 id |= (((id2) & 0x1fff) << 16);
689 cf->can_id = id | CAN_EFF_FLAG;
b21d18b5 690 } else {
1d5b4b27
T		 691 id = (id2 >> 2) & CAN_SFF_MASK;
692 cf->can_id = id;
b21d18b5
MO		 693 }
694
1d5b4b27 695 if (id2 & PCH_ID2_DIR)
b21d18b5 696 cf->can_id |= CAN_RTR_FLAG;
1d5b4b27
T		 697
698 cf->can_dlc = get_can_dlc((ioread32(&priv->regs->
699 ifregs[0].mcont)) & 0xF);
b21d18b5 700
8ac9702b
T		 701 for (i = 0; i < cf->can_dlc; i += 2) {
702 data_reg = ioread16(&priv->regs->ifregs[0].data[i / 2]);
703 cf->data[i] = data_reg;
704 cf->data[i + 1] = data_reg >> 8;
b21d18b5
MO		 705 }
706
707 netif_receive_skb(skb);
708 rcv_pkts++;
709 stats->rx_packets++;
1d5b4b27 710 quota--;
b21d18b5
MO		 711 stats->rx_bytes += cf->can_dlc;
712
1d5b4b27
T		 713 pch_fifo_thresh(priv, obj_num);
714 obj_num++;
715 } while (quota > 0);
b21d18b5
MO		 716
717 return rcv_pkts;
718}
e489cceb
T		 719
720static void pch_can_tx_complete(struct net_device *ndev, u32 int_stat)
b21d18b5 721{
b21d18b5
MO		 722 struct pch_can_priv *priv = netdev_priv(ndev);
723 struct net_device_stats *stats = &(priv->ndev->stats);
724 u32 dlc;
e489cceb
T		 725
726 can_get_echo_skb(ndev, int_stat - PCH_RX_OBJ_END - 1);
727 iowrite32(PCH_CMASK_RX_TX_GET | PCH_CMASK_CLRINTPND,
728 &priv->regs->ifregs[1].cmask);
bd58cbc3 729 pch_can_rw_msg_obj(&priv->regs->ifregs[1].creq, int_stat);
e489cceb
T		 730 dlc = get_can_dlc(ioread32(&priv->regs->ifregs[1].mcont) &
731 PCH_IF_MCONT_DLC);
732 stats->tx_bytes += dlc;
733 stats->tx_packets++;
734 if (int_stat == PCH_TX_OBJ_END)
735 netif_wake_queue(ndev);
736}
737
bd58cbc3 738static int pch_can_poll(struct napi_struct *napi, int quota)
e489cceb
T		 739{
740 struct net_device *ndev = napi->dev;
741 struct pch_can_priv *priv = netdev_priv(ndev);
b21d18b5
MO		 742 u32 int_stat;
743 int rcv_pkts = 0;
744 u32 reg_stat;
b21d18b5
MO		 745
746 int_stat = pch_can_int_pending(priv);
747 if (!int_stat)
e489cceb 748 goto end;
b21d18b5 749
e489cceb 750 if ((int_stat == PCH_STATUS_INT) && (quota > 0)) {
b21d18b5
MO		 751 reg_stat = ioread32(&priv->regs->stat);
752 if (reg_stat & (PCH_BUS_OFF | PCH_LEC_ALL)) {
e489cceb
T		 753 if (reg_stat & PCH_BUS_OFF ||
754 (reg_stat & PCH_LEC_ALL) != PCH_LEC_ALL) {
b21d18b5 755 pch_can_error(ndev, reg_stat);
e489cceb
T		 756 quota--;
757 }
b21d18b5
MO		 758 }
759
e489cceb 760 if (reg_stat & PCH_TX_OK)
b21d18b5 761 pch_can_bit_clear(&priv->regs->stat, PCH_TX_OK);
b21d18b5
MO		 762
763 if (reg_stat & PCH_RX_OK)
764 pch_can_bit_clear(&priv->regs->stat, PCH_RX_OK);
765
766 int_stat = pch_can_int_pending(priv);
b21d18b5
MO		 767 }
768
e489cceb
T		 769 if (quota == 0)
770 goto end;
771
15ffc8fd 772 if ((int_stat >= PCH_RX_OBJ_START) && (int_stat <= PCH_RX_OBJ_END)) {
1d5b4b27 773 rcv_pkts += pch_can_rx_normal(ndev, int_stat, quota);
e489cceb
T		 774 quota -= rcv_pkts;
775 if (quota < 0)
776 goto end;
15ffc8fd
T		 777 } else if ((int_stat >= PCH_TX_OBJ_START) &&
778 (int_stat <= PCH_TX_OBJ_END)) {
779 /* Handle transmission interrupt */
e489cceb 780 pch_can_tx_complete(ndev, int_stat);
b21d18b5
MO		 781 }
782
e489cceb 783end:
b21d18b5
MO		 784 napi_complete(napi);
785 pch_can_set_int_enables(priv, PCH_CAN_ALL);
786
787 return rcv_pkts;
788}
789
790static int pch_set_bittiming(struct net_device *ndev)
791{
792 struct pch_can_priv *priv = netdev_priv(ndev);
793 const struct can_bittiming *bt = &priv->can.bittiming;
794 u32 canbit;
795 u32 bepe;
796 u32 brp;
797
798 /* Setting the CCE bit for accessing the Can Timing register. */
086b5650 799 pch_can_bit_set(&priv->regs->cont, PCH_CTRL_CCE);
b21d18b5
MO		 800
801 brp = (bt->tq) / (1000000000/PCH_CAN_CLK) - 1;
086b5650 802 canbit = brp & PCH_MSK_BITT_BRP;
bd58cbc3
T		 803 canbit |= (bt->sjw - 1) << PCH_BIT_SJW_SHIFT;
804 canbit |= (bt->phase_seg1 + bt->prop_seg - 1) << PCH_BIT_TSEG1_SHIFT;
805 canbit |= (bt->phase_seg2 - 1) << PCH_BIT_TSEG2_SHIFT;
806 bepe = (brp & PCH_MSK_BRPE_BRPE) >> PCH_BIT_BRPE_BRPE_SHIFT;
b21d18b5
MO		 807 iowrite32(canbit, &priv->regs->bitt);
808 iowrite32(bepe, &priv->regs->brpe);
086b5650 809 pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_CCE);
b21d18b5
MO		 810
811 return 0;
812}
813
814static void pch_can_start(struct net_device *ndev)
815{
816 struct pch_can_priv *priv = netdev_priv(ndev);
817
818 if (priv->can.state != CAN_STATE_STOPPED)
819 pch_can_reset(priv);
820
821 pch_set_bittiming(ndev);
822 pch_can_set_optmode(priv);
823
8339a7ed
T		 824 pch_can_set_tx_all(priv, 1);
825 pch_can_set_rx_all(priv, 1);
b21d18b5
MO		 826
827 /* Setting the CAN to run mode. */
828 pch_can_set_run_mode(priv, PCH_CAN_RUN);
829
830 priv->can.state = CAN_STATE_ERROR_ACTIVE;
831
832 return;
833}
834
835static int pch_can_do_set_mode(struct net_device *ndev, enum can_mode mode)
836{
837 int ret = 0;
838
839 switch (mode) {
840 case CAN_MODE_START:
841 pch_can_start(ndev);
842 netif_wake_queue(ndev);
843 break;
844 default:
845 ret = -EOPNOTSUPP;
846 break;
847 }
848
849 return ret;
850}
851
852static int pch_can_open(struct net_device *ndev)
853{
854 struct pch_can_priv *priv = netdev_priv(ndev);
855 int retval;
856
857 retval = pci_enable_msi(priv->dev);
858 if (retval) {
435b4efe 859 netdev_err(ndev, "PCH CAN opened without MSI\n");
b21d18b5
MO		 860 priv->use_msi = 0;
861 } else {
435b4efe 862 netdev_err(ndev, "PCH CAN opened with MSI\n");
b21d18b5
MO		 863 priv->use_msi = 1;
864 }
865
866 /* Regsitering the interrupt. */
867 retval = request_irq(priv->dev->irq, pch_can_interrupt, IRQF_SHARED,
868 ndev->name, ndev);
869 if (retval) {
435b4efe 870 netdev_err(ndev, "request_irq failed.\n");
b21d18b5
MO		 871 goto req_irq_err;
872 }
873
874 /* Open common can device */
875 retval = open_candev(ndev);
876 if (retval) {
435b4efe 877 netdev_err(ndev, "open_candev() failed %d\n", retval);
b21d18b5
MO		 878 goto err_open_candev;
879 }
880
881 pch_can_init(priv);
882 pch_can_start(ndev);
883 napi_enable(&priv->napi);
884 netif_start_queue(ndev);
885
886 return 0;
887
888err_open_candev:
889 free_irq(priv->dev->irq, ndev);
890req_irq_err:
891 if (priv->use_msi)
892 pci_disable_msi(priv->dev);
893
894 pch_can_release(priv);
895
896 return retval;
897}
898
899static int pch_close(struct net_device *ndev)
900{
901 struct pch_can_priv *priv = netdev_priv(ndev);
902
903 netif_stop_queue(ndev);
904 napi_disable(&priv->napi);
905 pch_can_release(priv);
906 free_irq(priv->dev->irq, ndev);
907 if (priv->use_msi)
908 pci_disable_msi(priv->dev);
909 close_candev(ndev);
910 priv->can.state = CAN_STATE_STOPPED;
911 return 0;
912}
913
b21d18b5
MO		 914static netdev_tx_t pch_xmit(struct sk_buff *skb, struct net_device *ndev)
915{
b21d18b5
MO		 916 struct pch_can_priv *priv = netdev_priv(ndev);
917 struct can_frame *cf = (struct can_frame *)skb->data;
bd58cbc3 918 int tx_obj_no;
8ac9702b 919 int i;
44c9aa89 920 u32 id2;
b21d18b5
MO		 921
922 if (can_dropped_invalid_skb(ndev, skb))
923 return NETDEV_TX_OK;
924
76d94b23
T		 925 if (priv->tx_obj == PCH_TX_OBJ_END) {
926 if (ioread32(&priv->regs->treq2) & PCH_TREQ2_TX_MASK)
927 netif_stop_queue(ndev);
b21d18b5 928
bd58cbc3 929 tx_obj_no = priv->tx_obj;
76d94b23 930 priv->tx_obj = PCH_TX_OBJ_START;
b21d18b5 931 } else {
bd58cbc3 932 tx_obj_no = priv->tx_obj;
76d94b23 933 priv->tx_obj++;
b21d18b5 934 }
b21d18b5 935
b21d18b5 936 /* Reading the Msg Obj from the Msg RAM to the Interface register. */
8339a7ed 937 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[1].cmask);
bd58cbc3 938 pch_can_rw_msg_obj(&priv->regs->ifregs[1].creq, tx_obj_no);
b21d18b5
MO		 939
940 /* Setting the CMASK register. */
8339a7ed 941 pch_can_bit_set(&priv->regs->ifregs[1].cmask, PCH_CMASK_ALL);
b21d18b5
MO		 942
943 /* If ID extended is set. */
b21d18b5 944 if (cf->can_id & CAN_EFF_FLAG) {
44c9aa89
T		 945 iowrite32(cf->can_id & 0xffff, &priv->regs->ifregs[1].id1);
946 id2 = ((cf->can_id >> 16) & 0x1fff) | PCH_ID2_XTD;
b21d18b5 947 } else {
44c9aa89
T		 948 iowrite32(0, &priv->regs->ifregs[1].id1);
949 id2 = (cf->can_id & CAN_SFF_MASK) << 2;
b21d18b5
MO		 950 }
951
44c9aa89
T		 952 id2 |= PCH_ID_MSGVAL;
953
b21d18b5
MO		 954 /* If remote frame has to be transmitted.. */
955 if (cf->can_id & CAN_RTR_FLAG)
44c9aa89
T		 956 id2 &= ~PCH_ID2_DIR;
957 else
958 id2 |= PCH_ID2_DIR;
959
960 iowrite32(id2, &priv->regs->ifregs[1].id2);
b21d18b5 961
8ac9702b
T		 962 /* Copy data to register */
963 for (i = 0; i < cf->can_dlc; i += 2) {
964 iowrite16(cf->data[i] | (cf->data[i + 1] << 8),
965 &priv->regs->ifregs[1].data[i / 2]);
b21d18b5
MO		 966 }
967
bd58cbc3 968 can_put_echo_skb(skb, ndev, tx_obj_no - PCH_RX_OBJ_END - 1);
b21d18b5
MO		 969
970 /* Updating the size of the data. */
44c9aa89
T		 971 iowrite32(cf->can_dlc | PCH_IF_MCONT_NEWDAT | PCH_IF_MCONT_TXRQXT |
972 PCH_IF_MCONT_TXIE, &priv->regs->ifregs[1].mcont);
b21d18b5 973
bd58cbc3 974 pch_can_rw_msg_obj(&priv->regs->ifregs[1].creq, tx_obj_no);
b21d18b5 975
b21d18b5
MO		 976 return NETDEV_TX_OK;
977}
978
979static const struct net_device_ops pch_can_netdev_ops = {
980 .ndo_open = pch_can_open,
981 .ndo_stop = pch_close,
982 .ndo_start_xmit = pch_xmit,
983};
984
985static void __devexit pch_can_remove(struct pci_dev *pdev)
986{
987 struct net_device *ndev = pci_get_drvdata(pdev);
988 struct pch_can_priv *priv = netdev_priv(ndev);
989
990 unregister_candev(priv->ndev);
991 free_candev(priv->ndev);
992 pci_iounmap(pdev, priv->regs);
993 pci_release_regions(pdev);
994 pci_disable_device(pdev);
995 pci_set_drvdata(pdev, NULL);
996 pch_can_reset(priv);
997}
998
999#ifdef CONFIG_PM
7f2bc50e
T		 1000static void pch_can_set_int_custom(struct pch_can_priv *priv)
1001{
1002 /* Clearing the IE, SIE and EIE bits of Can control register. */
1003 pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_IE_SIE_EIE);
1004
1005 /* Appropriately setting them. */
1006 pch_can_bit_set(&priv->regs->cont,
1007 ((priv->int_enables & PCH_MSK_CTRL_IE_SIE_EIE) << 1));
1008}
1009
1010/* This function retrieves interrupt enabled for the CAN device. */
ca2b004e 1011static u32 pch_can_get_int_enables(struct pch_can_priv *priv)
7f2bc50e
T		 1012{
1013 /* Obtaining the status of IE, SIE and EIE interrupt bits. */
ca2b004e 1014 return (ioread32(&priv->regs->cont) & PCH_CTRL_IE_SIE_EIE) >> 1;
7f2bc50e
T		 1015}
1016
1017static u32 pch_can_get_rxtx_ir(struct pch_can_priv *priv, u32 buff_num,
1018 enum pch_ifreg dir)
1019{
1020 u32 ie, enable;
1021
1022 if (dir)
1023 ie = PCH_IF_MCONT_RXIE;
1024 else
1025 ie = PCH_IF_MCONT_TXIE;
1026
1027 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[dir].cmask);
bd58cbc3 1028 pch_can_rw_msg_obj(&priv->regs->ifregs[dir].creq, buff_num);
7f2bc50e
T		 1029
1030 if (((ioread32(&priv->regs->ifregs[dir].id2)) & PCH_ID_MSGVAL) &&
9388b166 1031 ((ioread32(&priv->regs->ifregs[dir].mcont)) & ie))
7f2bc50e 1032 enable = 1;
9388b166 1033 else
7f2bc50e 1034 enable = 0;
9388b166 1035
7f2bc50e
T		 1036 return enable;
1037}
1038
1039static void pch_can_set_rx_buffer_link(struct pch_can_priv *priv,
bd58cbc3 1040 u32 buffer_num, int set)
7f2bc50e
T		 1041{
1042 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask);
bd58cbc3 1043 pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, buffer_num);
7f2bc50e
T		 1044 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL,
1045 &priv->regs->ifregs[0].cmask);
bd58cbc3 1046 if (set)
7f2bc50e
T		 1047 pch_can_bit_clear(&priv->regs->ifregs[0].mcont,
1048 PCH_IF_MCONT_EOB);
1049 else
1050 pch_can_bit_set(&priv->regs->ifregs[0].mcont, PCH_IF_MCONT_EOB);
1051
bd58cbc3 1052 pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, buffer_num);
7f2bc50e
T		 1053}
1054
ca2b004e 1055static u32 pch_can_get_rx_buffer_link(struct pch_can_priv *priv, u32 buffer_num)
7f2bc50e 1056{
ca2b004e
T		 1057 u32 link;
1058
7f2bc50e 1059 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask);
bd58cbc3 1060 pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, buffer_num);
7f2bc50e
T		 1061
1062 if (ioread32(&priv->regs->ifregs[0].mcont) & PCH_IF_MCONT_EOB)
ca2b004e 1063 link = 0;
7f2bc50e 1064 else
ca2b004e
T		 1065 link = 1;
1066 return link;
7f2bc50e
T		 1067}
1068
1069static int pch_can_get_buffer_status(struct pch_can_priv *priv)
1070{
1071 return (ioread32(&priv->regs->treq1) & 0xffff) |
bd58cbc3 1072 (ioread32(&priv->regs->treq2) << 16);
7f2bc50e
T		 1073}
1074
b21d18b5
MO		 1075static int pch_can_suspend(struct pci_dev *pdev, pm_message_t state)
1076{
1077 int i; /* Counter variable. */
1078 int retval; /* Return value. */
1079 u32 buf_stat; /* Variable for reading the transmit buffer status. */
bd58cbc3 1080 int counter = PCH_COUNTER_LIMIT;
b21d18b5
MO		 1081
1082 struct net_device *dev = pci_get_drvdata(pdev);
1083 struct pch_can_priv *priv = netdev_priv(dev);
1084
1085 /* Stop the CAN controller */
1086 pch_can_set_run_mode(priv, PCH_CAN_STOP);
1087
1088 /* Indicate that we are aboutto/in suspend */
1089 priv->can.state = CAN_STATE_SLEEPING;
1090
1091 /* Waiting for all transmission to complete. */
1092 while (counter) {
1093 buf_stat = pch_can_get_buffer_status(priv);
1094 if (!buf_stat)
1095 break;
1096 counter--;
1097 udelay(1);
1098 }
1099 if (!counter)
1100 dev_err(&pdev->dev, "%s -> Transmission time out.\n", __func__);
1101
1102 /* Save interrupt configuration and then disable them */
ca2b004e 1103 priv->int_enables = pch_can_get_int_enables(priv);
b21d18b5
MO		 1104 pch_can_set_int_enables(priv, PCH_CAN_DISABLE);
1105
1106 /* Save Tx buffer enable state */
15ffc8fd
T		 1107 for (i = PCH_TX_OBJ_START; i <= PCH_TX_OBJ_END; i++)
1108 priv->tx_enable[i] = pch_can_get_rxtx_ir(priv, i, PCH_TX_IFREG);
b21d18b5
MO		 1109
1110 /* Disable all Transmit buffers */
8339a7ed 1111 pch_can_set_tx_all(priv, 0);
b21d18b5
MO		 1112
1113 /* Save Rx buffer enable state */
15ffc8fd
T		 1114 for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++) {
1115 priv->rx_enable[i] = pch_can_get_rxtx_ir(priv, i, PCH_RX_IFREG);
ca2b004e 1116 priv->rx_link[i] = pch_can_get_rx_buffer_link(priv, i);
b21d18b5
MO		 1117 }
1118
1119 /* Disable all Receive buffers */
8339a7ed 1120 pch_can_set_rx_all(priv, 0);
b21d18b5
MO		 1121 retval = pci_save_state(pdev);
1122 if (retval) {
1123 dev_err(&pdev->dev, "pci_save_state failed.\n");
1124 } else {
1125 pci_enable_wake(pdev, PCI_D3hot, 0);
1126 pci_disable_device(pdev);
1127 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1128 }
1129
1130 return retval;
1131}
1132
1133static int pch_can_resume(struct pci_dev *pdev)
1134{
1135 int i; /* Counter variable. */
1136 int retval; /* Return variable. */
1137 struct net_device *dev = pci_get_drvdata(pdev);
1138 struct pch_can_priv *priv = netdev_priv(dev);
1139
1140 pci_set_power_state(pdev, PCI_D0);
1141 pci_restore_state(pdev);
1142 retval = pci_enable_device(pdev);
1143 if (retval) {
1144 dev_err(&pdev->dev, "pci_enable_device failed.\n");
1145 return retval;
1146 }
1147
1148 pci_enable_wake(pdev, PCI_D3hot, 0);
1149
1150 priv->can.state = CAN_STATE_ERROR_ACTIVE;
1151
1152 /* Disabling all interrupts. */
1153 pch_can_set_int_enables(priv, PCH_CAN_DISABLE);
1154
1155 /* Setting the CAN device in Stop Mode. */
1156 pch_can_set_run_mode(priv, PCH_CAN_STOP);
1157
1158 /* Configuring the transmit and receive buffers. */
1159 pch_can_config_rx_tx_buffers(priv);
1160
1161 /* Restore the CAN state */
1162 pch_set_bittiming(dev);
1163
1164 /* Listen/Active */
1165 pch_can_set_optmode(priv);
1166
1167 /* Enabling the transmit buffer. */
15ffc8fd
T		 1168 for (i = PCH_TX_OBJ_START; i <= PCH_TX_OBJ_END; i++)
1169 pch_can_set_rxtx(priv, i, priv->tx_enable[i], PCH_TX_IFREG);
b21d18b5
MO		 1170
1171 /* Configuring the receive buffer and enabling them. */
15ffc8fd
T		 1172 for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++) {
1173 /* Restore buffer link */
1174 pch_can_set_rx_buffer_link(priv, i, priv->rx_link[i]);
b21d18b5 1175
15ffc8fd
T		 1176 /* Restore buffer enables */
1177 pch_can_set_rxtx(priv, i, priv->rx_enable[i], PCH_RX_IFREG);
b21d18b5
MO		 1178 }
1179
1180 /* Enable CAN Interrupts */
1181 pch_can_set_int_custom(priv);
1182
1183 /* Restore Run Mode */
1184 pch_can_set_run_mode(priv, PCH_CAN_RUN);
1185
1186 return retval;
1187}
1188#else
1189#define pch_can_suspend NULL
1190#define pch_can_resume NULL
1191#endif
1192
1193static int pch_can_get_berr_counter(const struct net_device *dev,
1194 struct can_berr_counter *bec)
1195{
1196 struct pch_can_priv *priv = netdev_priv(dev);
44c9aa89 1197 u32 errc = ioread32(&priv->regs->errc);
b21d18b5 1198
44c9aa89
T		 1199 bec->txerr = errc & PCH_TEC;
1200 bec->rxerr = (errc & PCH_REC) >> 8;
b21d18b5
MO		 1201
1202 return 0;
1203}
1204
1205static int __devinit pch_can_probe(struct pci_dev *pdev,
1206 const struct pci_device_id *id)
1207{
1208 struct net_device *ndev;
1209 struct pch_can_priv *priv;
1210 int rc;
b21d18b5
MO		 1211 void __iomem *addr;
1212
1213 rc = pci_enable_device(pdev);
1214 if (rc) {
1215 dev_err(&pdev->dev, "Failed pci_enable_device %d\n", rc);
1216 goto probe_exit_endev;
1217 }
1218
1219 rc = pci_request_regions(pdev, KBUILD_MODNAME);
1220 if (rc) {
1221 dev_err(&pdev->dev, "Failed pci_request_regions %d\n", rc);
1222 goto probe_exit_pcireq;
1223 }
1224
1225 addr = pci_iomap(pdev, 1, 0);
1226 if (!addr) {
1227 rc = -EIO;
1228 dev_err(&pdev->dev, "Failed pci_iomap\n");
1229 goto probe_exit_ipmap;
1230 }
1231
15ffc8fd 1232 ndev = alloc_candev(sizeof(struct pch_can_priv), PCH_TX_OBJ_END);
b21d18b5
MO		 1233 if (!ndev) {
1234 rc = -ENOMEM;
1235 dev_err(&pdev->dev, "Failed alloc_candev\n");
1236 goto probe_exit_alloc_candev;
1237 }
1238
1239 priv = netdev_priv(ndev);
1240 priv->ndev = ndev;
1241 priv->regs = addr;
1242 priv->dev = pdev;
1243 priv->can.bittiming_const = &pch_can_bittiming_const;
1244 priv->can.do_set_mode = pch_can_do_set_mode;
1245 priv->can.do_get_berr_counter = pch_can_get_berr_counter;
1246 priv->can.ctrlmode_supported = CAN_CTRLMODE_LISTENONLY |
1247 CAN_CTRLMODE_LOOPBACK;
15ffc8fd 1248 priv->tx_obj = PCH_TX_OBJ_START; /* Point head of Tx Obj */
b21d18b5
MO		 1249
1250 ndev->irq = pdev->irq;
1251 ndev->flags |= IFF_ECHO;
1252
1253 pci_set_drvdata(pdev, ndev);
1254 SET_NETDEV_DEV(ndev, &pdev->dev);
1255 ndev->netdev_ops = &pch_can_netdev_ops;
b21d18b5 1256 priv->can.clock.freq = PCH_CAN_CLK; /* Hz */
b21d18b5 1257
bd58cbc3 1258 netif_napi_add(ndev, &priv->napi, pch_can_poll, PCH_RX_OBJ_END);
b21d18b5
MO		 1259
1260 rc = register_candev(ndev);
1261 if (rc) {
1262 dev_err(&pdev->dev, "Failed register_candev %d\n", rc);
1263 goto probe_exit_reg_candev;
1264 }
1265
1266 return 0;
1267
1268probe_exit_reg_candev:
1269 free_candev(ndev);
1270probe_exit_alloc_candev:
1271 pci_iounmap(pdev, addr);
1272probe_exit_ipmap:
1273 pci_release_regions(pdev);
1274probe_exit_pcireq:
1275 pci_disable_device(pdev);
1276probe_exit_endev:
1277 return rc;
1278}
1279
bdfa3d8f 1280static struct pci_driver pch_can_pci_driver = {
b21d18b5
MO		 1281 .name = "pch_can",
1282 .id_table = pch_pci_tbl,
1283 .probe = pch_can_probe,
1284 .remove = __devexit_p(pch_can_remove),
1285 .suspend = pch_can_suspend,
1286 .resume = pch_can_resume,
1287};
1288
1289static int __init pch_can_pci_init(void)
1290{
bdfa3d8f 1291 return pci_register_driver(&pch_can_pci_driver);
b21d18b5
MO		 1292}
1293module_init(pch_can_pci_init);
1294
1295static void __exit pch_can_pci_exit(void)
1296{
bdfa3d8f 1297 pci_unregister_driver(&pch_can_pci_driver);
b21d18b5
MO		 1298}
1299module_exit(pch_can_pci_exit);
1300
e91530ea 1301MODULE_DESCRIPTION("Intel EG20T PCH CAN(Controller Area Network) Driver");
b21d18b5
MO		 1302MODULE_LICENSE("GPL v2");
1303MODULE_VERSION("0.94");
Linux kernel - Deliverables
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