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8199d3a7 CL |
1 | /***************************************************************************** |
2 | * * | |
3 | * File: sge.c * | |
559fb51b SB |
4 | * $Revision: 1.26 $ * |
5 | * $Date: 2005/06/21 18:29:48 $ * | |
8199d3a7 CL |
6 | * Description: * |
7 | * DMA engine. * | |
8 | * part of the Chelsio 10Gb Ethernet Driver. * | |
9 | * * | |
10 | * This program is free software; you can redistribute it and/or modify * | |
11 | * it under the terms of the GNU General Public License, version 2, as * | |
12 | * published by the Free Software Foundation. * | |
13 | * * | |
14 | * You should have received a copy of the GNU General Public License along * | |
15 | * with this program; if not, write to the Free Software Foundation, Inc., * | |
16 | * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * | |
17 | * * | |
18 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED * | |
19 | * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF * | |
20 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. * | |
21 | * * | |
22 | * http://www.chelsio.com * | |
23 | * * | |
24 | * Copyright (c) 2003 - 2005 Chelsio Communications, Inc. * | |
25 | * All rights reserved. * | |
26 | * * | |
27 | * Maintainers: maintainers@chelsio.com * | |
28 | * * | |
29 | * Authors: Dimitrios Michailidis <dm@chelsio.com> * | |
30 | * Tina Yang <tainay@chelsio.com> * | |
31 | * Felix Marti <felix@chelsio.com> * | |
32 | * Scott Bardone <sbardone@chelsio.com> * | |
33 | * Kurt Ottaway <kottaway@chelsio.com> * | |
34 | * Frank DiMambro <frank@chelsio.com> * | |
35 | * * | |
36 | * History: * | |
37 | * * | |
38 | ****************************************************************************/ | |
39 | ||
40 | #include "common.h" | |
41 | ||
8199d3a7 CL |
42 | #include <linux/types.h> |
43 | #include <linux/errno.h> | |
44 | #include <linux/pci.h> | |
f1d3d38a | 45 | #include <linux/ktime.h> |
8199d3a7 CL |
46 | #include <linux/netdevice.h> |
47 | #include <linux/etherdevice.h> | |
48 | #include <linux/if_vlan.h> | |
49 | #include <linux/skbuff.h> | |
50 | #include <linux/init.h> | |
51 | #include <linux/mm.h> | |
f1d3d38a | 52 | #include <linux/tcp.h> |
8199d3a7 CL |
53 | #include <linux/ip.h> |
54 | #include <linux/in.h> | |
55 | #include <linux/if_arp.h> | |
56 | ||
57 | #include "cpl5_cmd.h" | |
58 | #include "sge.h" | |
59 | #include "regs.h" | |
60 | #include "espi.h" | |
61 | ||
f1d3d38a SH |
62 | /* This belongs in if_ether.h */ |
63 | #define ETH_P_CPL5 0xf | |
8199d3a7 CL |
64 | |
65 | #define SGE_CMDQ_N 2 | |
66 | #define SGE_FREELQ_N 2 | |
559fb51b | 67 | #define SGE_CMDQ0_E_N 1024 |
8199d3a7 CL |
68 | #define SGE_CMDQ1_E_N 128 |
69 | #define SGE_FREEL_SIZE 4096 | |
70 | #define SGE_JUMBO_FREEL_SIZE 512 | |
71 | #define SGE_FREEL_REFILL_THRESH 16 | |
72 | #define SGE_RESPQ_E_N 1024 | |
559fb51b SB |
73 | #define SGE_INTRTIMER_NRES 1000 |
74 | #define SGE_RX_COPY_THRES 256 | |
8199d3a7 | 75 | #define SGE_RX_SM_BUF_SIZE 1536 |
f1d3d38a | 76 | #define SGE_TX_DESC_MAX_PLEN 16384 |
8199d3a7 | 77 | |
559fb51b SB |
78 | # define SGE_RX_DROP_THRES 2 |
79 | ||
80 | #define SGE_RESPQ_REPLENISH_THRES (SGE_RESPQ_E_N / 4) | |
81 | ||
82 | /* | |
83 | * Period of the TX buffer reclaim timer. This timer does not need to run | |
84 | * frequently as TX buffers are usually reclaimed by new TX packets. | |
85 | */ | |
86 | #define TX_RECLAIM_PERIOD (HZ / 4) | |
8199d3a7 | 87 | |
559fb51b SB |
88 | #define M_CMD_LEN 0x7fffffff |
89 | #define V_CMD_LEN(v) (v) | |
90 | #define G_CMD_LEN(v) ((v) & M_CMD_LEN) | |
91 | #define V_CMD_GEN1(v) ((v) << 31) | |
92 | #define V_CMD_GEN2(v) (v) | |
93 | #define F_CMD_DATAVALID (1 << 1) | |
94 | #define F_CMD_SOP (1 << 2) | |
95 | #define V_CMD_EOP(v) ((v) << 3) | |
96 | ||
8199d3a7 | 97 | /* |
559fb51b | 98 | * Command queue, receive buffer list, and response queue descriptors. |
8199d3a7 CL |
99 | */ |
100 | #if defined(__BIG_ENDIAN_BITFIELD) | |
101 | struct cmdQ_e { | |
559fb51b SB |
102 | u32 addr_lo; |
103 | u32 len_gen; | |
104 | u32 flags; | |
105 | u32 addr_hi; | |
8199d3a7 CL |
106 | }; |
107 | ||
108 | struct freelQ_e { | |
559fb51b SB |
109 | u32 addr_lo; |
110 | u32 len_gen; | |
111 | u32 gen2; | |
112 | u32 addr_hi; | |
8199d3a7 CL |
113 | }; |
114 | ||
115 | struct respQ_e { | |
116 | u32 Qsleeping : 4; | |
117 | u32 Cmdq1CreditReturn : 5; | |
118 | u32 Cmdq1DmaComplete : 5; | |
119 | u32 Cmdq0CreditReturn : 5; | |
120 | u32 Cmdq0DmaComplete : 5; | |
121 | u32 FreelistQid : 2; | |
122 | u32 CreditValid : 1; | |
123 | u32 DataValid : 1; | |
124 | u32 Offload : 1; | |
125 | u32 Eop : 1; | |
126 | u32 Sop : 1; | |
127 | u32 GenerationBit : 1; | |
128 | u32 BufferLength; | |
129 | }; | |
8199d3a7 CL |
130 | #elif defined(__LITTLE_ENDIAN_BITFIELD) |
131 | struct cmdQ_e { | |
559fb51b SB |
132 | u32 len_gen; |
133 | u32 addr_lo; | |
134 | u32 addr_hi; | |
135 | u32 flags; | |
8199d3a7 CL |
136 | }; |
137 | ||
138 | struct freelQ_e { | |
559fb51b SB |
139 | u32 len_gen; |
140 | u32 addr_lo; | |
141 | u32 addr_hi; | |
142 | u32 gen2; | |
8199d3a7 CL |
143 | }; |
144 | ||
145 | struct respQ_e { | |
146 | u32 BufferLength; | |
147 | u32 GenerationBit : 1; | |
148 | u32 Sop : 1; | |
149 | u32 Eop : 1; | |
150 | u32 Offload : 1; | |
151 | u32 DataValid : 1; | |
152 | u32 CreditValid : 1; | |
153 | u32 FreelistQid : 2; | |
154 | u32 Cmdq0DmaComplete : 5; | |
155 | u32 Cmdq0CreditReturn : 5; | |
156 | u32 Cmdq1DmaComplete : 5; | |
157 | u32 Cmdq1CreditReturn : 5; | |
158 | u32 Qsleeping : 4; | |
159 | } ; | |
160 | #endif | |
161 | ||
162 | /* | |
163 | * SW Context Command and Freelist Queue Descriptors | |
164 | */ | |
165 | struct cmdQ_ce { | |
166 | struct sk_buff *skb; | |
167 | DECLARE_PCI_UNMAP_ADDR(dma_addr); | |
168 | DECLARE_PCI_UNMAP_LEN(dma_len); | |
8199d3a7 CL |
169 | }; |
170 | ||
171 | struct freelQ_ce { | |
172 | struct sk_buff *skb; | |
173 | DECLARE_PCI_UNMAP_ADDR(dma_addr); | |
174 | DECLARE_PCI_UNMAP_LEN(dma_len); | |
175 | }; | |
176 | ||
177 | /* | |
559fb51b | 178 | * SW command, freelist and response rings |
8199d3a7 CL |
179 | */ |
180 | struct cmdQ { | |
559fb51b SB |
181 | unsigned long status; /* HW DMA fetch status */ |
182 | unsigned int in_use; /* # of in-use command descriptors */ | |
183 | unsigned int size; /* # of descriptors */ | |
f1d3d38a SH |
184 | unsigned int processed; /* total # of descs HW has processed */ |
185 | unsigned int cleaned; /* total # of descs SW has reclaimed */ | |
186 | unsigned int stop_thres; /* SW TX queue suspend threshold */ | |
559fb51b SB |
187 | u16 pidx; /* producer index (SW) */ |
188 | u16 cidx; /* consumer index (HW) */ | |
189 | u8 genbit; /* current generation (=valid) bit */ | |
f1d3d38a | 190 | u8 sop; /* is next entry start of packet? */ |
559fb51b SB |
191 | struct cmdQ_e *entries; /* HW command descriptor Q */ |
192 | struct cmdQ_ce *centries; /* SW command context descriptor Q */ | |
559fb51b | 193 | dma_addr_t dma_addr; /* DMA addr HW command descriptor Q */ |
356bd146 | 194 | spinlock_t lock; /* Lock to protect cmdQ enqueuing */ |
8199d3a7 CL |
195 | }; |
196 | ||
197 | struct freelQ { | |
559fb51b SB |
198 | unsigned int credits; /* # of available RX buffers */ |
199 | unsigned int size; /* free list capacity */ | |
200 | u16 pidx; /* producer index (SW) */ | |
201 | u16 cidx; /* consumer index (HW) */ | |
8199d3a7 | 202 | u16 rx_buffer_size; /* Buffer size on this free list */ |
f1d3d38a SH |
203 | u16 dma_offset; /* DMA offset to align IP headers */ |
204 | u16 recycleq_idx; /* skb recycle q to use */ | |
559fb51b SB |
205 | u8 genbit; /* current generation (=valid) bit */ |
206 | struct freelQ_e *entries; /* HW freelist descriptor Q */ | |
207 | struct freelQ_ce *centries; /* SW freelist context descriptor Q */ | |
208 | dma_addr_t dma_addr; /* DMA addr HW freelist descriptor Q */ | |
8199d3a7 CL |
209 | }; |
210 | ||
211 | struct respQ { | |
559fb51b SB |
212 | unsigned int credits; /* credits to be returned to SGE */ |
213 | unsigned int size; /* # of response Q descriptors */ | |
214 | u16 cidx; /* consumer index (SW) */ | |
215 | u8 genbit; /* current generation(=valid) bit */ | |
8199d3a7 | 216 | struct respQ_e *entries; /* HW response descriptor Q */ |
559fb51b SB |
217 | dma_addr_t dma_addr; /* DMA addr HW response descriptor Q */ |
218 | }; | |
219 | ||
220 | /* Bit flags for cmdQ.status */ | |
221 | enum { | |
222 | CMDQ_STAT_RUNNING = 1, /* fetch engine is running */ | |
223 | CMDQ_STAT_LAST_PKT_DB = 2 /* last packet rung the doorbell */ | |
8199d3a7 CL |
224 | }; |
225 | ||
f1d3d38a SH |
226 | /* T204 TX SW scheduler */ |
227 | ||
228 | /* Per T204 TX port */ | |
229 | struct sched_port { | |
230 | unsigned int avail; /* available bits - quota */ | |
231 | unsigned int drain_bits_per_1024ns; /* drain rate */ | |
232 | unsigned int speed; /* drain rate, mbps */ | |
233 | unsigned int mtu; /* mtu size */ | |
234 | struct sk_buff_head skbq; /* pending skbs */ | |
235 | }; | |
236 | ||
237 | /* Per T204 device */ | |
238 | struct sched { | |
239 | ktime_t last_updated; /* last time quotas were computed */ | |
356bd146 FR |
240 | unsigned int max_avail; /* max bits to be sent to any port */ |
241 | unsigned int port; /* port index (round robin ports) */ | |
242 | unsigned int num; /* num skbs in per port queues */ | |
f1d3d38a SH |
243 | struct sched_port p[MAX_NPORTS]; |
244 | struct tasklet_struct sched_tsk;/* tasklet used to run scheduler */ | |
245 | }; | |
246 | static void restart_sched(unsigned long); | |
247 | ||
248 | ||
8199d3a7 CL |
249 | /* |
250 | * Main SGE data structure | |
251 | * | |
252 | * Interrupts are handled by a single CPU and it is likely that on a MP system | |
253 | * the application is migrated to another CPU. In that scenario, we try to | |
254 | * seperate the RX(in irq context) and TX state in order to decrease memory | |
255 | * contention. | |
256 | */ | |
257 | struct sge { | |
356bd146 | 258 | struct adapter *adapter; /* adapter backpointer */ |
559fb51b | 259 | struct net_device *netdev; /* netdevice backpointer */ |
356bd146 FR |
260 | struct freelQ freelQ[SGE_FREELQ_N]; /* buffer free lists */ |
261 | struct respQ respQ; /* response Q */ | |
559fb51b | 262 | unsigned long stopped_tx_queues; /* bitmap of suspended Tx queues */ |
8199d3a7 CL |
263 | unsigned int rx_pkt_pad; /* RX padding for L2 packets */ |
264 | unsigned int jumbo_fl; /* jumbo freelist Q index */ | |
559fb51b | 265 | unsigned int intrtimer_nres; /* no-resource interrupt timer */ |
f1d3d38a | 266 | unsigned int fixed_intrtimer;/* non-adaptive interrupt timer */ |
559fb51b SB |
267 | struct timer_list tx_reclaim_timer; /* reclaims TX buffers */ |
268 | struct timer_list espibug_timer; | |
f1d3d38a SH |
269 | unsigned long espibug_timeout; |
270 | struct sk_buff *espibug_skb[MAX_NPORTS]; | |
559fb51b SB |
271 | u32 sge_control; /* shadow value of sge control reg */ |
272 | struct sge_intr_counts stats; | |
56f643c2 | 273 | struct sge_port_stats *port_stats[MAX_NPORTS]; |
f1d3d38a | 274 | struct sched *tx_sched; |
559fb51b | 275 | struct cmdQ cmdQ[SGE_CMDQ_N] ____cacheline_aligned_in_smp; |
8199d3a7 CL |
276 | }; |
277 | ||
f1d3d38a SH |
278 | /* |
279 | * stop tasklet and free all pending skb's | |
280 | */ | |
281 | static void tx_sched_stop(struct sge *sge) | |
282 | { | |
283 | struct sched *s = sge->tx_sched; | |
284 | int i; | |
285 | ||
286 | tasklet_kill(&s->sched_tsk); | |
287 | ||
288 | for (i = 0; i < MAX_NPORTS; i++) | |
289 | __skb_queue_purge(&s->p[s->port].skbq); | |
290 | } | |
291 | ||
292 | /* | |
293 | * t1_sched_update_parms() is called when the MTU or link speed changes. It | |
294 | * re-computes scheduler parameters to scope with the change. | |
295 | */ | |
296 | unsigned int t1_sched_update_parms(struct sge *sge, unsigned int port, | |
297 | unsigned int mtu, unsigned int speed) | |
298 | { | |
299 | struct sched *s = sge->tx_sched; | |
300 | struct sched_port *p = &s->p[port]; | |
301 | unsigned int max_avail_segs; | |
302 | ||
303 | pr_debug("t1_sched_update_params mtu=%d speed=%d\n", mtu, speed); | |
304 | if (speed) | |
305 | p->speed = speed; | |
306 | if (mtu) | |
307 | p->mtu = mtu; | |
308 | ||
309 | if (speed || mtu) { | |
310 | unsigned long long drain = 1024ULL * p->speed * (p->mtu - 40); | |
311 | do_div(drain, (p->mtu + 50) * 1000); | |
312 | p->drain_bits_per_1024ns = (unsigned int) drain; | |
313 | ||
314 | if (p->speed < 1000) | |
315 | p->drain_bits_per_1024ns = | |
316 | 90 * p->drain_bits_per_1024ns / 100; | |
317 | } | |
318 | ||
319 | if (board_info(sge->adapter)->board == CHBT_BOARD_CHT204) { | |
320 | p->drain_bits_per_1024ns -= 16; | |
321 | s->max_avail = max(4096U, p->mtu + 16 + 14 + 4); | |
322 | max_avail_segs = max(1U, 4096 / (p->mtu - 40)); | |
323 | } else { | |
324 | s->max_avail = 16384; | |
325 | max_avail_segs = max(1U, 9000 / (p->mtu - 40)); | |
326 | } | |
327 | ||
328 | pr_debug("t1_sched_update_parms: mtu %u speed %u max_avail %u " | |
329 | "max_avail_segs %u drain_bits_per_1024ns %u\n", p->mtu, | |
330 | p->speed, s->max_avail, max_avail_segs, | |
331 | p->drain_bits_per_1024ns); | |
332 | ||
333 | return max_avail_segs * (p->mtu - 40); | |
334 | } | |
335 | ||
336 | /* | |
337 | * t1_sched_max_avail_bytes() tells the scheduler the maximum amount of | |
338 | * data that can be pushed per port. | |
339 | */ | |
340 | void t1_sched_set_max_avail_bytes(struct sge *sge, unsigned int val) | |
341 | { | |
342 | struct sched *s = sge->tx_sched; | |
343 | unsigned int i; | |
344 | ||
345 | s->max_avail = val; | |
346 | for (i = 0; i < MAX_NPORTS; i++) | |
347 | t1_sched_update_parms(sge, i, 0, 0); | |
348 | } | |
349 | ||
350 | /* | |
351 | * t1_sched_set_drain_bits_per_us() tells the scheduler at which rate a port | |
352 | * is draining. | |
353 | */ | |
354 | void t1_sched_set_drain_bits_per_us(struct sge *sge, unsigned int port, | |
355 | unsigned int val) | |
356 | { | |
357 | struct sched *s = sge->tx_sched; | |
358 | struct sched_port *p = &s->p[port]; | |
359 | p->drain_bits_per_1024ns = val * 1024 / 1000; | |
360 | t1_sched_update_parms(sge, port, 0, 0); | |
361 | } | |
362 | ||
363 | ||
364 | /* | |
365 | * get_clock() implements a ns clock (see ktime_get) | |
366 | */ | |
367 | static inline ktime_t get_clock(void) | |
368 | { | |
369 | struct timespec ts; | |
370 | ||
371 | ktime_get_ts(&ts); | |
372 | return timespec_to_ktime(ts); | |
373 | } | |
374 | ||
375 | /* | |
376 | * tx_sched_init() allocates resources and does basic initialization. | |
377 | */ | |
378 | static int tx_sched_init(struct sge *sge) | |
379 | { | |
380 | struct sched *s; | |
381 | int i; | |
382 | ||
383 | s = kzalloc(sizeof (struct sched), GFP_KERNEL); | |
384 | if (!s) | |
385 | return -ENOMEM; | |
386 | ||
387 | pr_debug("tx_sched_init\n"); | |
388 | tasklet_init(&s->sched_tsk, restart_sched, (unsigned long) sge); | |
389 | sge->tx_sched = s; | |
390 | ||
391 | for (i = 0; i < MAX_NPORTS; i++) { | |
392 | skb_queue_head_init(&s->p[i].skbq); | |
393 | t1_sched_update_parms(sge, i, 1500, 1000); | |
394 | } | |
395 | ||
396 | return 0; | |
397 | } | |
398 | ||
399 | /* | |
400 | * sched_update_avail() computes the delta since the last time it was called | |
401 | * and updates the per port quota (number of bits that can be sent to the any | |
402 | * port). | |
403 | */ | |
404 | static inline int sched_update_avail(struct sge *sge) | |
405 | { | |
406 | struct sched *s = sge->tx_sched; | |
407 | ktime_t now = get_clock(); | |
408 | unsigned int i; | |
409 | long long delta_time_ns; | |
410 | ||
411 | delta_time_ns = ktime_to_ns(ktime_sub(now, s->last_updated)); | |
412 | ||
413 | pr_debug("sched_update_avail delta=%lld\n", delta_time_ns); | |
414 | if (delta_time_ns < 15000) | |
415 | return 0; | |
416 | ||
417 | for (i = 0; i < MAX_NPORTS; i++) { | |
418 | struct sched_port *p = &s->p[i]; | |
419 | unsigned int delta_avail; | |
420 | ||
421 | delta_avail = (p->drain_bits_per_1024ns * delta_time_ns) >> 13; | |
422 | p->avail = min(p->avail + delta_avail, s->max_avail); | |
423 | } | |
424 | ||
425 | s->last_updated = now; | |
426 | ||
427 | return 1; | |
428 | } | |
429 | ||
430 | /* | |
431 | * sched_skb() is called from two different places. In the tx path, any | |
432 | * packet generating load on an output port will call sched_skb() | |
433 | * (skb != NULL). In addition, sched_skb() is called from the irq/soft irq | |
434 | * context (skb == NULL). | |
435 | * The scheduler only returns a skb (which will then be sent) if the | |
436 | * length of the skb is <= the current quota of the output port. | |
437 | */ | |
438 | static struct sk_buff *sched_skb(struct sge *sge, struct sk_buff *skb, | |
439 | unsigned int credits) | |
440 | { | |
441 | struct sched *s = sge->tx_sched; | |
442 | struct sk_buff_head *skbq; | |
443 | unsigned int i, len, update = 1; | |
444 | ||
445 | pr_debug("sched_skb %p\n", skb); | |
446 | if (!skb) { | |
447 | if (!s->num) | |
448 | return NULL; | |
449 | } else { | |
450 | skbq = &s->p[skb->dev->if_port].skbq; | |
451 | __skb_queue_tail(skbq, skb); | |
452 | s->num++; | |
453 | skb = NULL; | |
454 | } | |
455 | ||
456 | if (credits < MAX_SKB_FRAGS + 1) | |
457 | goto out; | |
458 | ||
356bd146 | 459 | again: |
f1d3d38a SH |
460 | for (i = 0; i < MAX_NPORTS; i++) { |
461 | s->port = ++s->port & (MAX_NPORTS - 1); | |
462 | skbq = &s->p[s->port].skbq; | |
463 | ||
464 | skb = skb_peek(skbq); | |
465 | ||
466 | if (!skb) | |
467 | continue; | |
468 | ||
469 | len = skb->len; | |
470 | if (len <= s->p[s->port].avail) { | |
471 | s->p[s->port].avail -= len; | |
472 | s->num--; | |
473 | __skb_unlink(skb, skbq); | |
474 | goto out; | |
475 | } | |
476 | skb = NULL; | |
477 | } | |
478 | ||
479 | if (update-- && sched_update_avail(sge)) | |
480 | goto again; | |
481 | ||
356bd146 FR |
482 | out: |
483 | /* If there are more pending skbs, we use the hardware to schedule us | |
f1d3d38a SH |
484 | * again. |
485 | */ | |
486 | if (s->num && !skb) { | |
487 | struct cmdQ *q = &sge->cmdQ[0]; | |
488 | clear_bit(CMDQ_STAT_LAST_PKT_DB, &q->status); | |
489 | if (test_and_set_bit(CMDQ_STAT_RUNNING, &q->status) == 0) { | |
490 | set_bit(CMDQ_STAT_LAST_PKT_DB, &q->status); | |
491 | writel(F_CMDQ0_ENABLE, sge->adapter->regs + A_SG_DOORBELL); | |
492 | } | |
493 | } | |
494 | pr_debug("sched_skb ret %p\n", skb); | |
495 | ||
496 | return skb; | |
497 | } | |
498 | ||
8199d3a7 CL |
499 | /* |
500 | * PIO to indicate that memory mapped Q contains valid descriptor(s). | |
501 | */ | |
559fb51b | 502 | static inline void doorbell_pio(struct adapter *adapter, u32 val) |
8199d3a7 CL |
503 | { |
504 | wmb(); | |
559fb51b | 505 | writel(val, adapter->regs + A_SG_DOORBELL); |
8199d3a7 CL |
506 | } |
507 | ||
508 | /* | |
509 | * Frees all RX buffers on the freelist Q. The caller must make sure that | |
510 | * the SGE is turned off before calling this function. | |
511 | */ | |
559fb51b | 512 | static void free_freelQ_buffers(struct pci_dev *pdev, struct freelQ *q) |
8199d3a7 | 513 | { |
559fb51b | 514 | unsigned int cidx = q->cidx; |
8199d3a7 | 515 | |
559fb51b SB |
516 | while (q->credits--) { |
517 | struct freelQ_ce *ce = &q->centries[cidx]; | |
8199d3a7 CL |
518 | |
519 | pci_unmap_single(pdev, pci_unmap_addr(ce, dma_addr), | |
520 | pci_unmap_len(ce, dma_len), | |
521 | PCI_DMA_FROMDEVICE); | |
522 | dev_kfree_skb(ce->skb); | |
523 | ce->skb = NULL; | |
559fb51b | 524 | if (++cidx == q->size) |
8199d3a7 CL |
525 | cidx = 0; |
526 | } | |
527 | } | |
528 | ||
529 | /* | |
530 | * Free RX free list and response queue resources. | |
531 | */ | |
532 | static void free_rx_resources(struct sge *sge) | |
533 | { | |
534 | struct pci_dev *pdev = sge->adapter->pdev; | |
535 | unsigned int size, i; | |
536 | ||
537 | if (sge->respQ.entries) { | |
559fb51b | 538 | size = sizeof(struct respQ_e) * sge->respQ.size; |
8199d3a7 CL |
539 | pci_free_consistent(pdev, size, sge->respQ.entries, |
540 | sge->respQ.dma_addr); | |
541 | } | |
542 | ||
543 | for (i = 0; i < SGE_FREELQ_N; i++) { | |
559fb51b | 544 | struct freelQ *q = &sge->freelQ[i]; |
8199d3a7 | 545 | |
559fb51b SB |
546 | if (q->centries) { |
547 | free_freelQ_buffers(pdev, q); | |
548 | kfree(q->centries); | |
8199d3a7 | 549 | } |
559fb51b SB |
550 | if (q->entries) { |
551 | size = sizeof(struct freelQ_e) * q->size; | |
552 | pci_free_consistent(pdev, size, q->entries, | |
553 | q->dma_addr); | |
8199d3a7 CL |
554 | } |
555 | } | |
556 | } | |
557 | ||
558 | /* | |
559 | * Allocates basic RX resources, consisting of memory mapped freelist Qs and a | |
559fb51b | 560 | * response queue. |
8199d3a7 CL |
561 | */ |
562 | static int alloc_rx_resources(struct sge *sge, struct sge_params *p) | |
563 | { | |
564 | struct pci_dev *pdev = sge->adapter->pdev; | |
565 | unsigned int size, i; | |
566 | ||
567 | for (i = 0; i < SGE_FREELQ_N; i++) { | |
559fb51b SB |
568 | struct freelQ *q = &sge->freelQ[i]; |
569 | ||
570 | q->genbit = 1; | |
571 | q->size = p->freelQ_size[i]; | |
572 | q->dma_offset = sge->rx_pkt_pad ? 0 : NET_IP_ALIGN; | |
573 | size = sizeof(struct freelQ_e) * q->size; | |
3e0f75be | 574 | q->entries = pci_alloc_consistent(pdev, size, &q->dma_addr); |
559fb51b | 575 | if (!q->entries) |
8199d3a7 | 576 | goto err_no_mem; |
3e0f75be | 577 | |
559fb51b | 578 | size = sizeof(struct freelQ_ce) * q->size; |
cbee9f91 | 579 | q->centries = kzalloc(size, GFP_KERNEL); |
559fb51b | 580 | if (!q->centries) |
8199d3a7 CL |
581 | goto err_no_mem; |
582 | } | |
583 | ||
584 | /* | |
585 | * Calculate the buffer sizes for the two free lists. FL0 accommodates | |
586 | * regular sized Ethernet frames, FL1 is sized not to exceed 16K, | |
587 | * including all the sk_buff overhead. | |
588 | * | |
589 | * Note: For T2 FL0 and FL1 are reversed. | |
590 | */ | |
591 | sge->freelQ[!sge->jumbo_fl].rx_buffer_size = SGE_RX_SM_BUF_SIZE + | |
592 | sizeof(struct cpl_rx_data) + | |
593 | sge->freelQ[!sge->jumbo_fl].dma_offset; | |
f1d3d38a SH |
594 | |
595 | size = (16 * 1024) - | |
596 | SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); | |
597 | ||
598 | sge->freelQ[sge->jumbo_fl].rx_buffer_size = size; | |
8199d3a7 | 599 | |
559fb51b SB |
600 | /* |
601 | * Setup which skb recycle Q should be used when recycling buffers from | |
602 | * each free list. | |
603 | */ | |
604 | sge->freelQ[!sge->jumbo_fl].recycleq_idx = 0; | |
605 | sge->freelQ[sge->jumbo_fl].recycleq_idx = 1; | |
606 | ||
8199d3a7 | 607 | sge->respQ.genbit = 1; |
559fb51b SB |
608 | sge->respQ.size = SGE_RESPQ_E_N; |
609 | sge->respQ.credits = 0; | |
610 | size = sizeof(struct respQ_e) * sge->respQ.size; | |
3e0f75be | 611 | sge->respQ.entries = |
8199d3a7 CL |
612 | pci_alloc_consistent(pdev, size, &sge->respQ.dma_addr); |
613 | if (!sge->respQ.entries) | |
614 | goto err_no_mem; | |
8199d3a7 CL |
615 | return 0; |
616 | ||
617 | err_no_mem: | |
618 | free_rx_resources(sge); | |
619 | return -ENOMEM; | |
620 | } | |
621 | ||
622 | /* | |
559fb51b | 623 | * Reclaims n TX descriptors and frees the buffers associated with them. |
8199d3a7 | 624 | */ |
559fb51b | 625 | static void free_cmdQ_buffers(struct sge *sge, struct cmdQ *q, unsigned int n) |
8199d3a7 | 626 | { |
559fb51b | 627 | struct cmdQ_ce *ce; |
8199d3a7 | 628 | struct pci_dev *pdev = sge->adapter->pdev; |
559fb51b | 629 | unsigned int cidx = q->cidx; |
8199d3a7 | 630 | |
559fb51b SB |
631 | q->in_use -= n; |
632 | ce = &q->centries[cidx]; | |
633 | while (n--) { | |
3e0f75be FR |
634 | if (likely(pci_unmap_len(ce, dma_len))) { |
635 | pci_unmap_single(pdev, pci_unmap_addr(ce, dma_addr), | |
636 | pci_unmap_len(ce, dma_len), | |
637 | PCI_DMA_TODEVICE); | |
638 | if (q->sop) | |
f1d3d38a | 639 | q->sop = 0; |
f1d3d38a | 640 | } |
559fb51b | 641 | if (ce->skb) { |
f1d3d38a | 642 | dev_kfree_skb_any(ce->skb); |
559fb51b SB |
643 | q->sop = 1; |
644 | } | |
8199d3a7 | 645 | ce++; |
559fb51b | 646 | if (++cidx == q->size) { |
8199d3a7 | 647 | cidx = 0; |
559fb51b | 648 | ce = q->centries; |
8199d3a7 CL |
649 | } |
650 | } | |
559fb51b | 651 | q->cidx = cidx; |
8199d3a7 CL |
652 | } |
653 | ||
654 | /* | |
655 | * Free TX resources. | |
656 | * | |
657 | * Assumes that SGE is stopped and all interrupts are disabled. | |
658 | */ | |
659 | static void free_tx_resources(struct sge *sge) | |
660 | { | |
661 | struct pci_dev *pdev = sge->adapter->pdev; | |
662 | unsigned int size, i; | |
663 | ||
664 | for (i = 0; i < SGE_CMDQ_N; i++) { | |
559fb51b | 665 | struct cmdQ *q = &sge->cmdQ[i]; |
8199d3a7 | 666 | |
559fb51b SB |
667 | if (q->centries) { |
668 | if (q->in_use) | |
669 | free_cmdQ_buffers(sge, q, q->in_use); | |
670 | kfree(q->centries); | |
8199d3a7 | 671 | } |
559fb51b SB |
672 | if (q->entries) { |
673 | size = sizeof(struct cmdQ_e) * q->size; | |
674 | pci_free_consistent(pdev, size, q->entries, | |
675 | q->dma_addr); | |
8199d3a7 CL |
676 | } |
677 | } | |
678 | } | |
679 | ||
680 | /* | |
681 | * Allocates basic TX resources, consisting of memory mapped command Qs. | |
682 | */ | |
683 | static int alloc_tx_resources(struct sge *sge, struct sge_params *p) | |
684 | { | |
685 | struct pci_dev *pdev = sge->adapter->pdev; | |
686 | unsigned int size, i; | |
687 | ||
688 | for (i = 0; i < SGE_CMDQ_N; i++) { | |
559fb51b SB |
689 | struct cmdQ *q = &sge->cmdQ[i]; |
690 | ||
691 | q->genbit = 1; | |
692 | q->sop = 1; | |
693 | q->size = p->cmdQ_size[i]; | |
694 | q->in_use = 0; | |
695 | q->status = 0; | |
696 | q->processed = q->cleaned = 0; | |
697 | q->stop_thres = 0; | |
698 | spin_lock_init(&q->lock); | |
699 | size = sizeof(struct cmdQ_e) * q->size; | |
3e0f75be | 700 | q->entries = pci_alloc_consistent(pdev, size, &q->dma_addr); |
559fb51b | 701 | if (!q->entries) |
8199d3a7 | 702 | goto err_no_mem; |
3e0f75be | 703 | |
559fb51b | 704 | size = sizeof(struct cmdQ_ce) * q->size; |
cbee9f91 | 705 | q->centries = kzalloc(size, GFP_KERNEL); |
559fb51b | 706 | if (!q->centries) |
8199d3a7 CL |
707 | goto err_no_mem; |
708 | } | |
709 | ||
559fb51b SB |
710 | /* |
711 | * CommandQ 0 handles Ethernet and TOE packets, while queue 1 is TOE | |
712 | * only. For queue 0 set the stop threshold so we can handle one more | |
713 | * packet from each port, plus reserve an additional 24 entries for | |
714 | * Ethernet packets only. Queue 1 never suspends nor do we reserve | |
715 | * space for Ethernet packets. | |
716 | */ | |
717 | sge->cmdQ[0].stop_thres = sge->adapter->params.nports * | |
718 | (MAX_SKB_FRAGS + 1); | |
8199d3a7 CL |
719 | return 0; |
720 | ||
721 | err_no_mem: | |
722 | free_tx_resources(sge); | |
723 | return -ENOMEM; | |
724 | } | |
725 | ||
726 | static inline void setup_ring_params(struct adapter *adapter, u64 addr, | |
727 | u32 size, int base_reg_lo, | |
728 | int base_reg_hi, int size_reg) | |
729 | { | |
559fb51b SB |
730 | writel((u32)addr, adapter->regs + base_reg_lo); |
731 | writel(addr >> 32, adapter->regs + base_reg_hi); | |
732 | writel(size, adapter->regs + size_reg); | |
8199d3a7 CL |
733 | } |
734 | ||
735 | /* | |
736 | * Enable/disable VLAN acceleration. | |
737 | */ | |
738 | void t1_set_vlan_accel(struct adapter *adapter, int on_off) | |
739 | { | |
740 | struct sge *sge = adapter->sge; | |
741 | ||
742 | sge->sge_control &= ~F_VLAN_XTRACT; | |
743 | if (on_off) | |
744 | sge->sge_control |= F_VLAN_XTRACT; | |
745 | if (adapter->open_device_map) { | |
559fb51b | 746 | writel(sge->sge_control, adapter->regs + A_SG_CONTROL); |
f1d3d38a | 747 | readl(adapter->regs + A_SG_CONTROL); /* flush */ |
8199d3a7 CL |
748 | } |
749 | } | |
750 | ||
8199d3a7 CL |
751 | /* |
752 | * Programs the various SGE registers. However, the engine is not yet enabled, | |
753 | * but sge->sge_control is setup and ready to go. | |
754 | */ | |
755 | static void configure_sge(struct sge *sge, struct sge_params *p) | |
756 | { | |
757 | struct adapter *ap = sge->adapter; | |
356bd146 | 758 | |
559fb51b SB |
759 | writel(0, ap->regs + A_SG_CONTROL); |
760 | setup_ring_params(ap, sge->cmdQ[0].dma_addr, sge->cmdQ[0].size, | |
8199d3a7 | 761 | A_SG_CMD0BASELWR, A_SG_CMD0BASEUPR, A_SG_CMD0SIZE); |
559fb51b | 762 | setup_ring_params(ap, sge->cmdQ[1].dma_addr, sge->cmdQ[1].size, |
8199d3a7 CL |
763 | A_SG_CMD1BASELWR, A_SG_CMD1BASEUPR, A_SG_CMD1SIZE); |
764 | setup_ring_params(ap, sge->freelQ[0].dma_addr, | |
559fb51b | 765 | sge->freelQ[0].size, A_SG_FL0BASELWR, |
8199d3a7 CL |
766 | A_SG_FL0BASEUPR, A_SG_FL0SIZE); |
767 | setup_ring_params(ap, sge->freelQ[1].dma_addr, | |
559fb51b | 768 | sge->freelQ[1].size, A_SG_FL1BASELWR, |
8199d3a7 CL |
769 | A_SG_FL1BASEUPR, A_SG_FL1SIZE); |
770 | ||
771 | /* The threshold comparison uses <. */ | |
559fb51b | 772 | writel(SGE_RX_SM_BUF_SIZE + 1, ap->regs + A_SG_FLTHRESHOLD); |
8199d3a7 | 773 | |
559fb51b SB |
774 | setup_ring_params(ap, sge->respQ.dma_addr, sge->respQ.size, |
775 | A_SG_RSPBASELWR, A_SG_RSPBASEUPR, A_SG_RSPSIZE); | |
776 | writel((u32)sge->respQ.size - 1, ap->regs + A_SG_RSPQUEUECREDIT); | |
8199d3a7 CL |
777 | |
778 | sge->sge_control = F_CMDQ0_ENABLE | F_CMDQ1_ENABLE | F_FL0_ENABLE | | |
779 | F_FL1_ENABLE | F_CPL_ENABLE | F_RESPONSE_QUEUE_ENABLE | | |
780 | V_CMDQ_PRIORITY(2) | F_DISABLE_CMDQ1_GTS | F_ISCSI_COALESCE | | |
781 | V_RX_PKT_OFFSET(sge->rx_pkt_pad); | |
782 | ||
783 | #if defined(__BIG_ENDIAN_BITFIELD) | |
784 | sge->sge_control |= F_ENABLE_BIG_ENDIAN; | |
785 | #endif | |
786 | ||
559fb51b SB |
787 | /* Initialize no-resource timer */ |
788 | sge->intrtimer_nres = SGE_INTRTIMER_NRES * core_ticks_per_usec(ap); | |
789 | ||
790 | t1_sge_set_coalesce_params(sge, p); | |
8199d3a7 CL |
791 | } |
792 | ||
793 | /* | |
794 | * Return the payload capacity of the jumbo free-list buffers. | |
795 | */ | |
796 | static inline unsigned int jumbo_payload_capacity(const struct sge *sge) | |
797 | { | |
798 | return sge->freelQ[sge->jumbo_fl].rx_buffer_size - | |
559fb51b SB |
799 | sge->freelQ[sge->jumbo_fl].dma_offset - |
800 | sizeof(struct cpl_rx_data); | |
8199d3a7 CL |
801 | } |
802 | ||
803 | /* | |
804 | * Frees all SGE related resources and the sge structure itself | |
805 | */ | |
806 | void t1_sge_destroy(struct sge *sge) | |
807 | { | |
56f643c2 SH |
808 | int i; |
809 | ||
810 | for_each_port(sge->adapter, i) | |
811 | free_percpu(sge->port_stats[i]); | |
812 | ||
f1d3d38a | 813 | kfree(sge->tx_sched); |
8199d3a7 CL |
814 | free_tx_resources(sge); |
815 | free_rx_resources(sge); | |
816 | kfree(sge); | |
817 | } | |
818 | ||
819 | /* | |
820 | * Allocates new RX buffers on the freelist Q (and tracks them on the freelist | |
821 | * context Q) until the Q is full or alloc_skb fails. | |
822 | * | |
823 | * It is possible that the generation bits already match, indicating that the | |
824 | * buffer is already valid and nothing needs to be done. This happens when we | |
825 | * copied a received buffer into a new sk_buff during the interrupt processing. | |
826 | * | |
827 | * If the SGE doesn't automatically align packets properly (!sge->rx_pkt_pad), | |
828 | * we specify a RX_OFFSET in order to make sure that the IP header is 4B | |
829 | * aligned. | |
830 | */ | |
559fb51b | 831 | static void refill_free_list(struct sge *sge, struct freelQ *q) |
8199d3a7 CL |
832 | { |
833 | struct pci_dev *pdev = sge->adapter->pdev; | |
559fb51b SB |
834 | struct freelQ_ce *ce = &q->centries[q->pidx]; |
835 | struct freelQ_e *e = &q->entries[q->pidx]; | |
836 | unsigned int dma_len = q->rx_buffer_size - q->dma_offset; | |
8199d3a7 | 837 | |
559fb51b SB |
838 | while (q->credits < q->size) { |
839 | struct sk_buff *skb; | |
840 | dma_addr_t mapping; | |
8199d3a7 | 841 | |
559fb51b SB |
842 | skb = alloc_skb(q->rx_buffer_size, GFP_ATOMIC); |
843 | if (!skb) | |
844 | break; | |
845 | ||
846 | skb_reserve(skb, q->dma_offset); | |
847 | mapping = pci_map_single(pdev, skb->data, dma_len, | |
848 | PCI_DMA_FROMDEVICE); | |
849 | ce->skb = skb; | |
850 | pci_unmap_addr_set(ce, dma_addr, mapping); | |
851 | pci_unmap_len_set(ce, dma_len, dma_len); | |
852 | e->addr_lo = (u32)mapping; | |
853 | e->addr_hi = (u64)mapping >> 32; | |
854 | e->len_gen = V_CMD_LEN(dma_len) | V_CMD_GEN1(q->genbit); | |
855 | wmb(); | |
856 | e->gen2 = V_CMD_GEN2(q->genbit); | |
8199d3a7 CL |
857 | |
858 | e++; | |
859 | ce++; | |
559fb51b SB |
860 | if (++q->pidx == q->size) { |
861 | q->pidx = 0; | |
862 | q->genbit ^= 1; | |
863 | ce = q->centries; | |
864 | e = q->entries; | |
8199d3a7 | 865 | } |
559fb51b | 866 | q->credits++; |
8199d3a7 | 867 | } |
8199d3a7 CL |
868 | } |
869 | ||
870 | /* | |
559fb51b SB |
871 | * Calls refill_free_list for both free lists. If we cannot fill at least 1/4 |
872 | * of both rings, we go into 'few interrupt mode' in order to give the system | |
873 | * time to free up resources. | |
8199d3a7 CL |
874 | */ |
875 | static void freelQs_empty(struct sge *sge) | |
876 | { | |
559fb51b SB |
877 | struct adapter *adapter = sge->adapter; |
878 | u32 irq_reg = readl(adapter->regs + A_SG_INT_ENABLE); | |
8199d3a7 CL |
879 | u32 irqholdoff_reg; |
880 | ||
881 | refill_free_list(sge, &sge->freelQ[0]); | |
882 | refill_free_list(sge, &sge->freelQ[1]); | |
883 | ||
559fb51b SB |
884 | if (sge->freelQ[0].credits > (sge->freelQ[0].size >> 2) && |
885 | sge->freelQ[1].credits > (sge->freelQ[1].size >> 2)) { | |
8199d3a7 | 886 | irq_reg |= F_FL_EXHAUSTED; |
559fb51b | 887 | irqholdoff_reg = sge->fixed_intrtimer; |
8199d3a7 CL |
888 | } else { |
889 | /* Clear the F_FL_EXHAUSTED interrupts for now */ | |
890 | irq_reg &= ~F_FL_EXHAUSTED; | |
891 | irqholdoff_reg = sge->intrtimer_nres; | |
892 | } | |
559fb51b SB |
893 | writel(irqholdoff_reg, adapter->regs + A_SG_INTRTIMER); |
894 | writel(irq_reg, adapter->regs + A_SG_INT_ENABLE); | |
8199d3a7 CL |
895 | |
896 | /* We reenable the Qs to force a freelist GTS interrupt later */ | |
559fb51b | 897 | doorbell_pio(adapter, F_FL0_ENABLE | F_FL1_ENABLE); |
8199d3a7 CL |
898 | } |
899 | ||
900 | #define SGE_PL_INTR_MASK (F_PL_INTR_SGE_ERR | F_PL_INTR_SGE_DATA) | |
901 | #define SGE_INT_FATAL (F_RESPQ_OVERFLOW | F_PACKET_TOO_BIG | F_PACKET_MISMATCH) | |
902 | #define SGE_INT_ENABLE (F_RESPQ_EXHAUSTED | F_RESPQ_OVERFLOW | \ | |
903 | F_FL_EXHAUSTED | F_PACKET_TOO_BIG | F_PACKET_MISMATCH) | |
904 | ||
905 | /* | |
906 | * Disable SGE Interrupts | |
907 | */ | |
908 | void t1_sge_intr_disable(struct sge *sge) | |
909 | { | |
559fb51b | 910 | u32 val = readl(sge->adapter->regs + A_PL_ENABLE); |
8199d3a7 | 911 | |
559fb51b SB |
912 | writel(val & ~SGE_PL_INTR_MASK, sge->adapter->regs + A_PL_ENABLE); |
913 | writel(0, sge->adapter->regs + A_SG_INT_ENABLE); | |
8199d3a7 CL |
914 | } |
915 | ||
916 | /* | |
917 | * Enable SGE interrupts. | |
918 | */ | |
919 | void t1_sge_intr_enable(struct sge *sge) | |
920 | { | |
921 | u32 en = SGE_INT_ENABLE; | |
559fb51b | 922 | u32 val = readl(sge->adapter->regs + A_PL_ENABLE); |
8199d3a7 CL |
923 | |
924 | if (sge->adapter->flags & TSO_CAPABLE) | |
925 | en &= ~F_PACKET_TOO_BIG; | |
559fb51b SB |
926 | writel(en, sge->adapter->regs + A_SG_INT_ENABLE); |
927 | writel(val | SGE_PL_INTR_MASK, sge->adapter->regs + A_PL_ENABLE); | |
8199d3a7 CL |
928 | } |
929 | ||
930 | /* | |
931 | * Clear SGE interrupts. | |
932 | */ | |
933 | void t1_sge_intr_clear(struct sge *sge) | |
934 | { | |
559fb51b SB |
935 | writel(SGE_PL_INTR_MASK, sge->adapter->regs + A_PL_CAUSE); |
936 | writel(0xffffffff, sge->adapter->regs + A_SG_INT_CAUSE); | |
8199d3a7 CL |
937 | } |
938 | ||
939 | /* | |
940 | * SGE 'Error' interrupt handler | |
941 | */ | |
942 | int t1_sge_intr_error_handler(struct sge *sge) | |
943 | { | |
944 | struct adapter *adapter = sge->adapter; | |
559fb51b | 945 | u32 cause = readl(adapter->regs + A_SG_INT_CAUSE); |
8199d3a7 CL |
946 | |
947 | if (adapter->flags & TSO_CAPABLE) | |
948 | cause &= ~F_PACKET_TOO_BIG; | |
949 | if (cause & F_RESPQ_EXHAUSTED) | |
559fb51b | 950 | sge->stats.respQ_empty++; |
8199d3a7 | 951 | if (cause & F_RESPQ_OVERFLOW) { |
559fb51b | 952 | sge->stats.respQ_overflow++; |
8199d3a7 CL |
953 | CH_ALERT("%s: SGE response queue overflow\n", |
954 | adapter->name); | |
955 | } | |
956 | if (cause & F_FL_EXHAUSTED) { | |
559fb51b | 957 | sge->stats.freelistQ_empty++; |
8199d3a7 CL |
958 | freelQs_empty(sge); |
959 | } | |
960 | if (cause & F_PACKET_TOO_BIG) { | |
559fb51b | 961 | sge->stats.pkt_too_big++; |
8199d3a7 CL |
962 | CH_ALERT("%s: SGE max packet size exceeded\n", |
963 | adapter->name); | |
964 | } | |
965 | if (cause & F_PACKET_MISMATCH) { | |
559fb51b | 966 | sge->stats.pkt_mismatch++; |
8199d3a7 CL |
967 | CH_ALERT("%s: SGE packet mismatch\n", adapter->name); |
968 | } | |
969 | if (cause & SGE_INT_FATAL) | |
970 | t1_fatal_err(adapter); | |
971 | ||
559fb51b | 972 | writel(cause, adapter->regs + A_SG_INT_CAUSE); |
8199d3a7 CL |
973 | return 0; |
974 | } | |
975 | ||
56f643c2 | 976 | const struct sge_intr_counts *t1_sge_get_intr_counts(const struct sge *sge) |
559fb51b SB |
977 | { |
978 | return &sge->stats; | |
979 | } | |
980 | ||
56f643c2 SH |
981 | void t1_sge_get_port_stats(const struct sge *sge, int port, |
982 | struct sge_port_stats *ss) | |
559fb51b | 983 | { |
56f643c2 SH |
984 | int cpu; |
985 | ||
986 | memset(ss, 0, sizeof(*ss)); | |
987 | for_each_possible_cpu(cpu) { | |
988 | struct sge_port_stats *st = per_cpu_ptr(sge->port_stats[port], cpu); | |
989 | ||
990 | ss->rx_packets += st->rx_packets; | |
991 | ss->rx_cso_good += st->rx_cso_good; | |
992 | ss->tx_packets += st->tx_packets; | |
993 | ss->tx_cso += st->tx_cso; | |
994 | ss->tx_tso += st->tx_tso; | |
995 | ss->vlan_xtract += st->vlan_xtract; | |
996 | ss->vlan_insert += st->vlan_insert; | |
997 | } | |
559fb51b SB |
998 | } |
999 | ||
1000 | /** | |
1001 | * recycle_fl_buf - recycle a free list buffer | |
1002 | * @fl: the free list | |
1003 | * @idx: index of buffer to recycle | |
8199d3a7 | 1004 | * |
559fb51b SB |
1005 | * Recycles the specified buffer on the given free list by adding it at |
1006 | * the next available slot on the list. | |
8199d3a7 | 1007 | */ |
559fb51b | 1008 | static void recycle_fl_buf(struct freelQ *fl, int idx) |
8199d3a7 | 1009 | { |
559fb51b SB |
1010 | struct freelQ_e *from = &fl->entries[idx]; |
1011 | struct freelQ_e *to = &fl->entries[fl->pidx]; | |
8199d3a7 | 1012 | |
559fb51b SB |
1013 | fl->centries[fl->pidx] = fl->centries[idx]; |
1014 | to->addr_lo = from->addr_lo; | |
1015 | to->addr_hi = from->addr_hi; | |
1016 | to->len_gen = G_CMD_LEN(from->len_gen) | V_CMD_GEN1(fl->genbit); | |
1017 | wmb(); | |
1018 | to->gen2 = V_CMD_GEN2(fl->genbit); | |
1019 | fl->credits++; | |
8199d3a7 | 1020 | |
559fb51b SB |
1021 | if (++fl->pidx == fl->size) { |
1022 | fl->pidx = 0; | |
1023 | fl->genbit ^= 1; | |
8199d3a7 | 1024 | } |
559fb51b | 1025 | } |
8199d3a7 | 1026 | |
559fb51b SB |
1027 | /** |
1028 | * get_packet - return the next ingress packet buffer | |
1029 | * @pdev: the PCI device that received the packet | |
1030 | * @fl: the SGE free list holding the packet | |
1031 | * @len: the actual packet length, excluding any SGE padding | |
1032 | * @dma_pad: padding at beginning of buffer left by SGE DMA | |
1033 | * @skb_pad: padding to be used if the packet is copied | |
1034 | * @copy_thres: length threshold under which a packet should be copied | |
1035 | * @drop_thres: # of remaining buffers before we start dropping packets | |
1036 | * | |
1037 | * Get the next packet from a free list and complete setup of the | |
1038 | * sk_buff. If the packet is small we make a copy and recycle the | |
1039 | * original buffer, otherwise we use the original buffer itself. If a | |
1040 | * positive drop threshold is supplied packets are dropped and their | |
1041 | * buffers recycled if (a) the number of remaining buffers is under the | |
1042 | * threshold and the packet is too big to copy, or (b) the packet should | |
1043 | * be copied but there is no memory for the copy. | |
1044 | */ | |
1045 | static inline struct sk_buff *get_packet(struct pci_dev *pdev, | |
1046 | struct freelQ *fl, unsigned int len, | |
1047 | int dma_pad, int skb_pad, | |
1048 | unsigned int copy_thres, | |
1049 | unsigned int drop_thres) | |
1050 | { | |
1051 | struct sk_buff *skb; | |
1052 | struct freelQ_ce *ce = &fl->centries[fl->cidx]; | |
1053 | ||
1054 | if (len < copy_thres) { | |
1055 | skb = alloc_skb(len + skb_pad, GFP_ATOMIC); | |
1056 | if (likely(skb != NULL)) { | |
1057 | skb_reserve(skb, skb_pad); | |
1058 | skb_put(skb, len); | |
1059 | pci_dma_sync_single_for_cpu(pdev, | |
1060 | pci_unmap_addr(ce, dma_addr), | |
356bd146 | 1061 | pci_unmap_len(ce, dma_len), |
559fb51b SB |
1062 | PCI_DMA_FROMDEVICE); |
1063 | memcpy(skb->data, ce->skb->data + dma_pad, len); | |
1064 | pci_dma_sync_single_for_device(pdev, | |
1065 | pci_unmap_addr(ce, dma_addr), | |
356bd146 | 1066 | pci_unmap_len(ce, dma_len), |
559fb51b SB |
1067 | PCI_DMA_FROMDEVICE); |
1068 | } else if (!drop_thres) | |
1069 | goto use_orig_buf; | |
8199d3a7 | 1070 | |
559fb51b SB |
1071 | recycle_fl_buf(fl, fl->cidx); |
1072 | return skb; | |
8199d3a7 CL |
1073 | } |
1074 | ||
559fb51b SB |
1075 | if (fl->credits < drop_thres) { |
1076 | recycle_fl_buf(fl, fl->cidx); | |
1077 | return NULL; | |
1078 | } | |
8199d3a7 | 1079 | |
559fb51b SB |
1080 | use_orig_buf: |
1081 | pci_unmap_single(pdev, pci_unmap_addr(ce, dma_addr), | |
1082 | pci_unmap_len(ce, dma_len), PCI_DMA_FROMDEVICE); | |
1083 | skb = ce->skb; | |
1084 | skb_reserve(skb, dma_pad); | |
1085 | skb_put(skb, len); | |
1086 | return skb; | |
1087 | } | |
8199d3a7 | 1088 | |
559fb51b SB |
1089 | /** |
1090 | * unexpected_offload - handle an unexpected offload packet | |
1091 | * @adapter: the adapter | |
1092 | * @fl: the free list that received the packet | |
1093 | * | |
1094 | * Called when we receive an unexpected offload packet (e.g., the TOE | |
1095 | * function is disabled or the card is a NIC). Prints a message and | |
1096 | * recycles the buffer. | |
1097 | */ | |
1098 | static void unexpected_offload(struct adapter *adapter, struct freelQ *fl) | |
1099 | { | |
1100 | struct freelQ_ce *ce = &fl->centries[fl->cidx]; | |
1101 | struct sk_buff *skb = ce->skb; | |
1102 | ||
1103 | pci_dma_sync_single_for_cpu(adapter->pdev, pci_unmap_addr(ce, dma_addr), | |
1104 | pci_unmap_len(ce, dma_len), PCI_DMA_FROMDEVICE); | |
1105 | CH_ERR("%s: unexpected offload packet, cmd %u\n", | |
1106 | adapter->name, *skb->data); | |
1107 | recycle_fl_buf(fl, fl->cidx); | |
8199d3a7 CL |
1108 | } |
1109 | ||
f1d3d38a SH |
1110 | /* |
1111 | * T1/T2 SGE limits the maximum DMA size per TX descriptor to | |
1112 | * SGE_TX_DESC_MAX_PLEN (16KB). If the PAGE_SIZE is larger than 16KB, the | |
1113 | * stack might send more than SGE_TX_DESC_MAX_PLEN in a contiguous manner. | |
1114 | * Note that the *_large_page_tx_descs stuff will be optimized out when | |
1115 | * PAGE_SIZE <= SGE_TX_DESC_MAX_PLEN. | |
1116 | * | |
1117 | * compute_large_page_descs() computes how many additional descriptors are | |
1118 | * required to break down the stack's request. | |
1119 | */ | |
1120 | static inline unsigned int compute_large_page_tx_descs(struct sk_buff *skb) | |
1121 | { | |
1122 | unsigned int count = 0; | |
356bd146 | 1123 | |
f1d3d38a SH |
1124 | if (PAGE_SIZE > SGE_TX_DESC_MAX_PLEN) { |
1125 | unsigned int nfrags = skb_shinfo(skb)->nr_frags; | |
1126 | unsigned int i, len = skb->len - skb->data_len; | |
1127 | while (len > SGE_TX_DESC_MAX_PLEN) { | |
1128 | count++; | |
1129 | len -= SGE_TX_DESC_MAX_PLEN; | |
1130 | } | |
1131 | for (i = 0; nfrags--; i++) { | |
1132 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | |
1133 | len = frag->size; | |
1134 | while (len > SGE_TX_DESC_MAX_PLEN) { | |
1135 | count++; | |
1136 | len -= SGE_TX_DESC_MAX_PLEN; | |
1137 | } | |
1138 | } | |
1139 | } | |
1140 | return count; | |
1141 | } | |
1142 | ||
1143 | /* | |
1144 | * Write a cmdQ entry. | |
1145 | * | |
1146 | * Since this function writes the 'flags' field, it must not be used to | |
1147 | * write the first cmdQ entry. | |
1148 | */ | |
1149 | static inline void write_tx_desc(struct cmdQ_e *e, dma_addr_t mapping, | |
1150 | unsigned int len, unsigned int gen, | |
1151 | unsigned int eop) | |
1152 | { | |
1153 | if (unlikely(len > SGE_TX_DESC_MAX_PLEN)) | |
1154 | BUG(); | |
1155 | e->addr_lo = (u32)mapping; | |
1156 | e->addr_hi = (u64)mapping >> 32; | |
1157 | e->len_gen = V_CMD_LEN(len) | V_CMD_GEN1(gen); | |
1158 | e->flags = F_CMD_DATAVALID | V_CMD_EOP(eop) | V_CMD_GEN2(gen); | |
1159 | } | |
1160 | ||
1161 | /* | |
1162 | * See comment for previous function. | |
1163 | * | |
1164 | * write_tx_descs_large_page() writes additional SGE tx descriptors if | |
1165 | * *desc_len exceeds HW's capability. | |
1166 | */ | |
1167 | static inline unsigned int write_large_page_tx_descs(unsigned int pidx, | |
1168 | struct cmdQ_e **e, | |
1169 | struct cmdQ_ce **ce, | |
1170 | unsigned int *gen, | |
1171 | dma_addr_t *desc_mapping, | |
1172 | unsigned int *desc_len, | |
1173 | unsigned int nfrags, | |
1174 | struct cmdQ *q) | |
1175 | { | |
1176 | if (PAGE_SIZE > SGE_TX_DESC_MAX_PLEN) { | |
1177 | struct cmdQ_e *e1 = *e; | |
1178 | struct cmdQ_ce *ce1 = *ce; | |
1179 | ||
1180 | while (*desc_len > SGE_TX_DESC_MAX_PLEN) { | |
1181 | *desc_len -= SGE_TX_DESC_MAX_PLEN; | |
1182 | write_tx_desc(e1, *desc_mapping, SGE_TX_DESC_MAX_PLEN, | |
1183 | *gen, nfrags == 0 && *desc_len == 0); | |
1184 | ce1->skb = NULL; | |
1185 | pci_unmap_len_set(ce1, dma_len, 0); | |
1186 | *desc_mapping += SGE_TX_DESC_MAX_PLEN; | |
1187 | if (*desc_len) { | |
1188 | ce1++; | |
1189 | e1++; | |
1190 | if (++pidx == q->size) { | |
1191 | pidx = 0; | |
1192 | *gen ^= 1; | |
1193 | ce1 = q->centries; | |
1194 | e1 = q->entries; | |
1195 | } | |
1196 | } | |
1197 | } | |
1198 | *e = e1; | |
1199 | *ce = ce1; | |
1200 | } | |
1201 | return pidx; | |
1202 | } | |
1203 | ||
8199d3a7 | 1204 | /* |
559fb51b SB |
1205 | * Write the command descriptors to transmit the given skb starting at |
1206 | * descriptor pidx with the given generation. | |
8199d3a7 | 1207 | */ |
559fb51b SB |
1208 | static inline void write_tx_descs(struct adapter *adapter, struct sk_buff *skb, |
1209 | unsigned int pidx, unsigned int gen, | |
1210 | struct cmdQ *q) | |
8199d3a7 | 1211 | { |
f1d3d38a | 1212 | dma_addr_t mapping, desc_mapping; |
559fb51b SB |
1213 | struct cmdQ_e *e, *e1; |
1214 | struct cmdQ_ce *ce; | |
f1d3d38a SH |
1215 | unsigned int i, flags, first_desc_len, desc_len, |
1216 | nfrags = skb_shinfo(skb)->nr_frags; | |
559fb51b | 1217 | |
f1d3d38a | 1218 | e = e1 = &q->entries[pidx]; |
559fb51b | 1219 | ce = &q->centries[pidx]; |
f1d3d38a SH |
1220 | |
1221 | mapping = pci_map_single(adapter->pdev, skb->data, | |
1222 | skb->len - skb->data_len, PCI_DMA_TODEVICE); | |
1223 | ||
1224 | desc_mapping = mapping; | |
1225 | desc_len = skb->len - skb->data_len; | |
1226 | ||
1227 | flags = F_CMD_DATAVALID | F_CMD_SOP | | |
1228 | V_CMD_EOP(nfrags == 0 && desc_len <= SGE_TX_DESC_MAX_PLEN) | | |
1229 | V_CMD_GEN2(gen); | |
1230 | first_desc_len = (desc_len <= SGE_TX_DESC_MAX_PLEN) ? | |
1231 | desc_len : SGE_TX_DESC_MAX_PLEN; | |
1232 | e->addr_lo = (u32)desc_mapping; | |
1233 | e->addr_hi = (u64)desc_mapping >> 32; | |
1234 | e->len_gen = V_CMD_LEN(first_desc_len) | V_CMD_GEN1(gen); | |
1235 | ce->skb = NULL; | |
1236 | pci_unmap_len_set(ce, dma_len, 0); | |
1237 | ||
1238 | if (PAGE_SIZE > SGE_TX_DESC_MAX_PLEN && | |
1239 | desc_len > SGE_TX_DESC_MAX_PLEN) { | |
1240 | desc_mapping += first_desc_len; | |
1241 | desc_len -= first_desc_len; | |
1242 | e1++; | |
1243 | ce++; | |
1244 | if (++pidx == q->size) { | |
1245 | pidx = 0; | |
1246 | gen ^= 1; | |
1247 | e1 = q->entries; | |
1248 | ce = q->centries; | |
1249 | } | |
1250 | pidx = write_large_page_tx_descs(pidx, &e1, &ce, &gen, | |
1251 | &desc_mapping, &desc_len, | |
1252 | nfrags, q); | |
1253 | ||
1254 | if (likely(desc_len)) | |
1255 | write_tx_desc(e1, desc_mapping, desc_len, gen, | |
1256 | nfrags == 0); | |
1257 | } | |
1258 | ||
559fb51b SB |
1259 | ce->skb = NULL; |
1260 | pci_unmap_addr_set(ce, dma_addr, mapping); | |
1261 | pci_unmap_len_set(ce, dma_len, skb->len - skb->data_len); | |
8199d3a7 | 1262 | |
f1d3d38a | 1263 | for (i = 0; nfrags--; i++) { |
559fb51b | 1264 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; |
559fb51b | 1265 | e1++; |
f1d3d38a | 1266 | ce++; |
559fb51b SB |
1267 | if (++pidx == q->size) { |
1268 | pidx = 0; | |
1269 | gen ^= 1; | |
559fb51b | 1270 | e1 = q->entries; |
f1d3d38a | 1271 | ce = q->centries; |
8199d3a7 | 1272 | } |
8199d3a7 | 1273 | |
559fb51b SB |
1274 | mapping = pci_map_page(adapter->pdev, frag->page, |
1275 | frag->page_offset, frag->size, | |
1276 | PCI_DMA_TODEVICE); | |
f1d3d38a SH |
1277 | desc_mapping = mapping; |
1278 | desc_len = frag->size; | |
1279 | ||
1280 | pidx = write_large_page_tx_descs(pidx, &e1, &ce, &gen, | |
1281 | &desc_mapping, &desc_len, | |
1282 | nfrags, q); | |
1283 | if (likely(desc_len)) | |
1284 | write_tx_desc(e1, desc_mapping, desc_len, gen, | |
1285 | nfrags == 0); | |
559fb51b SB |
1286 | ce->skb = NULL; |
1287 | pci_unmap_addr_set(ce, dma_addr, mapping); | |
1288 | pci_unmap_len_set(ce, dma_len, frag->size); | |
8199d3a7 | 1289 | } |
559fb51b SB |
1290 | ce->skb = skb; |
1291 | wmb(); | |
1292 | e->flags = flags; | |
1293 | } | |
8199d3a7 | 1294 | |
559fb51b SB |
1295 | /* |
1296 | * Clean up completed Tx buffers. | |
1297 | */ | |
1298 | static inline void reclaim_completed_tx(struct sge *sge, struct cmdQ *q) | |
1299 | { | |
1300 | unsigned int reclaim = q->processed - q->cleaned; | |
8199d3a7 | 1301 | |
559fb51b | 1302 | if (reclaim) { |
f1d3d38a SH |
1303 | pr_debug("reclaim_completed_tx processed:%d cleaned:%d\n", |
1304 | q->processed, q->cleaned); | |
559fb51b SB |
1305 | free_cmdQ_buffers(sge, q, reclaim); |
1306 | q->cleaned += reclaim; | |
8199d3a7 | 1307 | } |
559fb51b | 1308 | } |
8199d3a7 | 1309 | |
f1d3d38a SH |
1310 | /* |
1311 | * Called from tasklet. Checks the scheduler for any | |
1312 | * pending skbs that can be sent. | |
1313 | */ | |
1314 | static void restart_sched(unsigned long arg) | |
1315 | { | |
1316 | struct sge *sge = (struct sge *) arg; | |
1317 | struct adapter *adapter = sge->adapter; | |
1318 | struct cmdQ *q = &sge->cmdQ[0]; | |
1319 | struct sk_buff *skb; | |
1320 | unsigned int credits, queued_skb = 0; | |
1321 | ||
1322 | spin_lock(&q->lock); | |
1323 | reclaim_completed_tx(sge, q); | |
1324 | ||
1325 | credits = q->size - q->in_use; | |
1326 | pr_debug("restart_sched credits=%d\n", credits); | |
1327 | while ((skb = sched_skb(sge, NULL, credits)) != NULL) { | |
1328 | unsigned int genbit, pidx, count; | |
1329 | count = 1 + skb_shinfo(skb)->nr_frags; | |
356bd146 | 1330 | count += compute_large_page_tx_descs(skb); |
f1d3d38a SH |
1331 | q->in_use += count; |
1332 | genbit = q->genbit; | |
1333 | pidx = q->pidx; | |
1334 | q->pidx += count; | |
1335 | if (q->pidx >= q->size) { | |
1336 | q->pidx -= q->size; | |
1337 | q->genbit ^= 1; | |
1338 | } | |
1339 | write_tx_descs(adapter, skb, pidx, genbit, q); | |
1340 | credits = q->size - q->in_use; | |
1341 | queued_skb = 1; | |
1342 | } | |
1343 | ||
1344 | if (queued_skb) { | |
1345 | clear_bit(CMDQ_STAT_LAST_PKT_DB, &q->status); | |
1346 | if (test_and_set_bit(CMDQ_STAT_RUNNING, &q->status) == 0) { | |
1347 | set_bit(CMDQ_STAT_LAST_PKT_DB, &q->status); | |
1348 | writel(F_CMDQ0_ENABLE, adapter->regs + A_SG_DOORBELL); | |
1349 | } | |
1350 | } | |
1351 | spin_unlock(&q->lock); | |
1352 | } | |
8199d3a7 | 1353 | |
559fb51b SB |
1354 | /** |
1355 | * sge_rx - process an ingress ethernet packet | |
1356 | * @sge: the sge structure | |
1357 | * @fl: the free list that contains the packet buffer | |
1358 | * @len: the packet length | |
8199d3a7 | 1359 | * |
559fb51b | 1360 | * Process an ingress ethernet pakcet and deliver it to the stack. |
8199d3a7 | 1361 | */ |
559fb51b | 1362 | static int sge_rx(struct sge *sge, struct freelQ *fl, unsigned int len) |
8199d3a7 | 1363 | { |
559fb51b SB |
1364 | struct sk_buff *skb; |
1365 | struct cpl_rx_pkt *p; | |
1366 | struct adapter *adapter = sge->adapter; | |
56f643c2 | 1367 | struct sge_port_stats *st; |
8199d3a7 | 1368 | |
559fb51b SB |
1369 | skb = get_packet(adapter->pdev, fl, len - sge->rx_pkt_pad, |
1370 | sge->rx_pkt_pad, 2, SGE_RX_COPY_THRES, | |
1371 | SGE_RX_DROP_THRES); | |
56f643c2 SH |
1372 | if (unlikely(!skb)) { |
1373 | sge->stats.rx_drops++; | |
559fb51b | 1374 | return 0; |
8199d3a7 | 1375 | } |
559fb51b SB |
1376 | |
1377 | p = (struct cpl_rx_pkt *)skb->data; | |
1378 | skb_pull(skb, sizeof(*p)); | |
f1d3d38a SH |
1379 | if (p->iff >= adapter->params.nports) { |
1380 | kfree_skb(skb); | |
1381 | return 0; | |
1382 | } | |
1383 | ||
56f643c2 | 1384 | skb->dev = adapter->port[p->iff].dev; |
559fb51b | 1385 | skb->dev->last_rx = jiffies; |
56f643c2 SH |
1386 | st = per_cpu_ptr(sge->port_stats[p->iff], smp_processor_id()); |
1387 | st->rx_packets++; | |
1388 | ||
559fb51b SB |
1389 | skb->protocol = eth_type_trans(skb, skb->dev); |
1390 | if ((adapter->flags & RX_CSUM_ENABLED) && p->csum == 0xffff && | |
1391 | skb->protocol == htons(ETH_P_IP) && | |
1392 | (skb->data[9] == IPPROTO_TCP || skb->data[9] == IPPROTO_UDP)) { | |
56f643c2 | 1393 | ++st->rx_cso_good; |
559fb51b SB |
1394 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
1395 | } else | |
1396 | skb->ip_summed = CHECKSUM_NONE; | |
1397 | ||
1398 | if (unlikely(adapter->vlan_grp && p->vlan_valid)) { | |
56f643c2 | 1399 | st->vlan_xtract++; |
7fe26a60 | 1400 | #ifdef CONFIG_CHELSIO_T1_NAPI |
559fb51b SB |
1401 | vlan_hwaccel_receive_skb(skb, adapter->vlan_grp, |
1402 | ntohs(p->vlan)); | |
7fe26a60 | 1403 | #else |
559fb51b SB |
1404 | vlan_hwaccel_rx(skb, adapter->vlan_grp, |
1405 | ntohs(p->vlan)); | |
7fe26a60 SH |
1406 | #endif |
1407 | } else { | |
1408 | #ifdef CONFIG_CHELSIO_T1_NAPI | |
559fb51b | 1409 | netif_receive_skb(skb); |
7fe26a60 | 1410 | #else |
559fb51b | 1411 | netif_rx(skb); |
7fe26a60 SH |
1412 | #endif |
1413 | } | |
559fb51b | 1414 | return 0; |
8199d3a7 CL |
1415 | } |
1416 | ||
1417 | /* | |
559fb51b | 1418 | * Returns true if a command queue has enough available descriptors that |
8199d3a7 CL |
1419 | * we can resume Tx operation after temporarily disabling its packet queue. |
1420 | */ | |
559fb51b | 1421 | static inline int enough_free_Tx_descs(const struct cmdQ *q) |
8199d3a7 | 1422 | { |
559fb51b SB |
1423 | unsigned int r = q->processed - q->cleaned; |
1424 | ||
1425 | return q->in_use - r < (q->size >> 1); | |
8199d3a7 CL |
1426 | } |
1427 | ||
1428 | /* | |
559fb51b SB |
1429 | * Called when sufficient space has become available in the SGE command queues |
1430 | * after the Tx packet schedulers have been suspended to restart the Tx path. | |
8199d3a7 | 1431 | */ |
559fb51b | 1432 | static void restart_tx_queues(struct sge *sge) |
8199d3a7 | 1433 | { |
559fb51b | 1434 | struct adapter *adap = sge->adapter; |
3e0f75be | 1435 | int i; |
8199d3a7 | 1436 | |
3e0f75be FR |
1437 | if (!enough_free_Tx_descs(&sge->cmdQ[0])) |
1438 | return; | |
559fb51b | 1439 | |
3e0f75be FR |
1440 | for_each_port(adap, i) { |
1441 | struct net_device *nd = adap->port[i].dev; | |
559fb51b | 1442 | |
3e0f75be FR |
1443 | if (test_and_clear_bit(nd->if_port, &sge->stopped_tx_queues) && |
1444 | netif_running(nd)) { | |
1445 | sge->stats.cmdQ_restarted[2]++; | |
1446 | netif_wake_queue(nd); | |
559fb51b SB |
1447 | } |
1448 | } | |
1449 | } | |
1450 | ||
1451 | /* | |
356bd146 | 1452 | * update_tx_info is called from the interrupt handler/NAPI to return cmdQ0 |
559fb51b SB |
1453 | * information. |
1454 | */ | |
356bd146 FR |
1455 | static unsigned int update_tx_info(struct adapter *adapter, |
1456 | unsigned int flags, | |
559fb51b SB |
1457 | unsigned int pr0) |
1458 | { | |
1459 | struct sge *sge = adapter->sge; | |
1460 | struct cmdQ *cmdq = &sge->cmdQ[0]; | |
8199d3a7 | 1461 | |
559fb51b | 1462 | cmdq->processed += pr0; |
f1d3d38a SH |
1463 | if (flags & (F_FL0_ENABLE | F_FL1_ENABLE)) { |
1464 | freelQs_empty(sge); | |
1465 | flags &= ~(F_FL0_ENABLE | F_FL1_ENABLE); | |
1466 | } | |
559fb51b SB |
1467 | if (flags & F_CMDQ0_ENABLE) { |
1468 | clear_bit(CMDQ_STAT_RUNNING, &cmdq->status); | |
f1d3d38a | 1469 | |
559fb51b SB |
1470 | if (cmdq->cleaned + cmdq->in_use != cmdq->processed && |
1471 | !test_and_set_bit(CMDQ_STAT_LAST_PKT_DB, &cmdq->status)) { | |
1472 | set_bit(CMDQ_STAT_RUNNING, &cmdq->status); | |
1473 | writel(F_CMDQ0_ENABLE, adapter->regs + A_SG_DOORBELL); | |
1474 | } | |
f1d3d38a SH |
1475 | if (sge->tx_sched) |
1476 | tasklet_hi_schedule(&sge->tx_sched->sched_tsk); | |
1477 | ||
1478 | flags &= ~F_CMDQ0_ENABLE; | |
559fb51b | 1479 | } |
f1d3d38a | 1480 | |
559fb51b SB |
1481 | if (unlikely(sge->stopped_tx_queues != 0)) |
1482 | restart_tx_queues(sge); | |
8199d3a7 | 1483 | |
559fb51b SB |
1484 | return flags; |
1485 | } | |
8199d3a7 | 1486 | |
559fb51b SB |
1487 | /* |
1488 | * Process SGE responses, up to the supplied budget. Returns the number of | |
1489 | * responses processed. A negative budget is effectively unlimited. | |
1490 | */ | |
1491 | static int process_responses(struct adapter *adapter, int budget) | |
1492 | { | |
1493 | struct sge *sge = adapter->sge; | |
1494 | struct respQ *q = &sge->respQ; | |
1495 | struct respQ_e *e = &q->entries[q->cidx]; | |
1496 | int budget_left = budget; | |
1497 | unsigned int flags = 0; | |
1498 | unsigned int cmdq_processed[SGE_CMDQ_N] = {0, 0}; | |
356bd146 | 1499 | |
559fb51b SB |
1500 | |
1501 | while (likely(budget_left && e->GenerationBit == q->genbit)) { | |
1502 | flags |= e->Qsleeping; | |
356bd146 | 1503 | |
559fb51b SB |
1504 | cmdq_processed[0] += e->Cmdq0CreditReturn; |
1505 | cmdq_processed[1] += e->Cmdq1CreditReturn; | |
356bd146 | 1506 | |
559fb51b SB |
1507 | /* We batch updates to the TX side to avoid cacheline |
1508 | * ping-pong of TX state information on MP where the sender | |
1509 | * might run on a different CPU than this function... | |
1510 | */ | |
1511 | if (unlikely(flags & F_CMDQ0_ENABLE || cmdq_processed[0] > 64)) { | |
1512 | flags = update_tx_info(adapter, flags, cmdq_processed[0]); | |
1513 | cmdq_processed[0] = 0; | |
1514 | } | |
1515 | if (unlikely(cmdq_processed[1] > 16)) { | |
1516 | sge->cmdQ[1].processed += cmdq_processed[1]; | |
1517 | cmdq_processed[1] = 0; | |
8199d3a7 CL |
1518 | } |
1519 | if (likely(e->DataValid)) { | |
559fb51b SB |
1520 | struct freelQ *fl = &sge->freelQ[e->FreelistQid]; |
1521 | ||
5d9428de | 1522 | BUG_ON(!e->Sop || !e->Eop); |
559fb51b SB |
1523 | if (unlikely(e->Offload)) |
1524 | unexpected_offload(adapter, fl); | |
1525 | else | |
1526 | sge_rx(sge, fl, e->BufferLength); | |
1527 | ||
1528 | /* | |
1529 | * Note: this depends on each packet consuming a | |
1530 | * single free-list buffer; cf. the BUG above. | |
1531 | */ | |
1532 | if (++fl->cidx == fl->size) | |
1533 | fl->cidx = 0; | |
1534 | if (unlikely(--fl->credits < | |
1535 | fl->size - SGE_FREEL_REFILL_THRESH)) | |
1536 | refill_free_list(sge, fl); | |
1537 | } else | |
1538 | sge->stats.pure_rsps++; | |
8199d3a7 | 1539 | |
8199d3a7 | 1540 | e++; |
559fb51b SB |
1541 | if (unlikely(++q->cidx == q->size)) { |
1542 | q->cidx = 0; | |
1543 | q->genbit ^= 1; | |
1544 | e = q->entries; | |
1545 | } | |
1546 | prefetch(e); | |
1547 | ||
1548 | if (++q->credits > SGE_RESPQ_REPLENISH_THRES) { | |
1549 | writel(q->credits, adapter->regs + A_SG_RSPQUEUECREDIT); | |
1550 | q->credits = 0; | |
8199d3a7 | 1551 | } |
559fb51b | 1552 | --budget_left; |
8199d3a7 CL |
1553 | } |
1554 | ||
356bd146 | 1555 | flags = update_tx_info(adapter, flags, cmdq_processed[0]); |
559fb51b | 1556 | sge->cmdQ[1].processed += cmdq_processed[1]; |
8199d3a7 | 1557 | |
559fb51b SB |
1558 | budget -= budget_left; |
1559 | return budget; | |
1560 | } | |
8199d3a7 | 1561 | |
7fe26a60 | 1562 | #ifdef CONFIG_CHELSIO_T1_NAPI |
559fb51b SB |
1563 | /* |
1564 | * A simpler version of process_responses() that handles only pure (i.e., | |
1565 | * non data-carrying) responses. Such respones are too light-weight to justify | |
1566 | * calling a softirq when using NAPI, so we handle them specially in hard | |
1567 | * interrupt context. The function is called with a pointer to a response, | |
1568 | * which the caller must ensure is a valid pure response. Returns 1 if it | |
1569 | * encounters a valid data-carrying response, 0 otherwise. | |
1570 | */ | |
1571 | static int process_pure_responses(struct adapter *adapter, struct respQ_e *e) | |
1572 | { | |
1573 | struct sge *sge = adapter->sge; | |
1574 | struct respQ *q = &sge->respQ; | |
1575 | unsigned int flags = 0; | |
1576 | unsigned int cmdq_processed[SGE_CMDQ_N] = {0, 0}; | |
8199d3a7 | 1577 | |
559fb51b SB |
1578 | do { |
1579 | flags |= e->Qsleeping; | |
8199d3a7 | 1580 | |
559fb51b SB |
1581 | cmdq_processed[0] += e->Cmdq0CreditReturn; |
1582 | cmdq_processed[1] += e->Cmdq1CreditReturn; | |
356bd146 | 1583 | |
559fb51b SB |
1584 | e++; |
1585 | if (unlikely(++q->cidx == q->size)) { | |
1586 | q->cidx = 0; | |
1587 | q->genbit ^= 1; | |
1588 | e = q->entries; | |
8199d3a7 | 1589 | } |
559fb51b | 1590 | prefetch(e); |
8199d3a7 | 1591 | |
559fb51b SB |
1592 | if (++q->credits > SGE_RESPQ_REPLENISH_THRES) { |
1593 | writel(q->credits, adapter->regs + A_SG_RSPQUEUECREDIT); | |
1594 | q->credits = 0; | |
8199d3a7 | 1595 | } |
559fb51b SB |
1596 | sge->stats.pure_rsps++; |
1597 | } while (e->GenerationBit == q->genbit && !e->DataValid); | |
8199d3a7 | 1598 | |
356bd146 | 1599 | flags = update_tx_info(adapter, flags, cmdq_processed[0]); |
559fb51b | 1600 | sge->cmdQ[1].processed += cmdq_processed[1]; |
8199d3a7 | 1601 | |
559fb51b | 1602 | return e->GenerationBit == q->genbit; |
8199d3a7 CL |
1603 | } |
1604 | ||
1605 | /* | |
559fb51b SB |
1606 | * Handler for new data events when using NAPI. This does not need any locking |
1607 | * or protection from interrupts as data interrupts are off at this point and | |
1608 | * other adapter interrupts do not interfere. | |
8199d3a7 | 1609 | */ |
7fe26a60 | 1610 | int t1_poll(struct net_device *dev, int *budget) |
8199d3a7 | 1611 | { |
559fb51b SB |
1612 | struct adapter *adapter = dev->priv; |
1613 | int effective_budget = min(*budget, dev->quota); | |
559fb51b | 1614 | int work_done = process_responses(adapter, effective_budget); |
7fe26a60 | 1615 | |
559fb51b SB |
1616 | *budget -= work_done; |
1617 | dev->quota -= work_done; | |
8199d3a7 | 1618 | |
559fb51b SB |
1619 | if (work_done >= effective_budget) |
1620 | return 1; | |
1621 | ||
356bd146 | 1622 | spin_lock_irq(&adapter->async_lock); |
559fb51b | 1623 | __netif_rx_complete(dev); |
559fb51b | 1624 | writel(adapter->sge->respQ.cidx, adapter->regs + A_SG_SLEEPING); |
7fe26a60 SH |
1625 | writel(adapter->slow_intr_mask | F_PL_INTR_SGE_DATA, |
1626 | adapter->regs + A_PL_ENABLE); | |
356bd146 | 1627 | spin_unlock_irq(&adapter->async_lock); |
8199d3a7 | 1628 | |
7fe26a60 | 1629 | return 0; |
559fb51b | 1630 | } |
8199d3a7 | 1631 | |
559fb51b SB |
1632 | /* |
1633 | * NAPI version of the main interrupt handler. | |
1634 | */ | |
7fe26a60 | 1635 | irqreturn_t t1_interrupt(int irq, void *data) |
559fb51b | 1636 | { |
559fb51b | 1637 | struct adapter *adapter = data; |
356bd146 | 1638 | struct net_device *dev = adapter->sge->netdev; |
559fb51b | 1639 | struct sge *sge = adapter->sge; |
356bd146 | 1640 | u32 cause; |
7fe26a60 | 1641 | int handled = 0; |
8199d3a7 | 1642 | |
7fe26a60 SH |
1643 | cause = readl(adapter->regs + A_PL_CAUSE); |
1644 | if (cause == 0 || cause == ~0) | |
1645 | return IRQ_NONE; | |
559fb51b SB |
1646 | |
1647 | spin_lock(&adapter->async_lock); | |
356bd146 | 1648 | if (cause & F_PL_INTR_SGE_DATA) { |
7fe26a60 | 1649 | struct respQ *q = &adapter->sge->respQ; |
559fb51b SB |
1650 | struct respQ_e *e = &q->entries[q->cidx]; |
1651 | ||
356bd146 FR |
1652 | handled = 1; |
1653 | writel(F_PL_INTR_SGE_DATA, adapter->regs + A_PL_CAUSE); | |
7fe26a60 SH |
1654 | |
1655 | if (e->GenerationBit == q->genbit && | |
1656 | __netif_rx_schedule_prep(dev)) { | |
1657 | if (e->DataValid || process_pure_responses(adapter, e)) { | |
1658 | /* mask off data IRQ */ | |
1659 | writel(adapter->slow_intr_mask, | |
1660 | adapter->regs + A_PL_ENABLE); | |
1661 | __netif_rx_schedule(sge->netdev); | |
1662 | goto unlock; | |
1663 | } | |
1664 | /* no data, no NAPI needed */ | |
1665 | netif_poll_enable(dev); | |
1666 | ||
1667 | } | |
1668 | writel(q->cidx, adapter->regs + A_SG_SLEEPING); | |
1669 | } else | |
1670 | handled = t1_slow_intr_handler(adapter); | |
1671 | ||
559fb51b SB |
1672 | if (!handled) |
1673 | sge->stats.unhandled_irqs++; | |
7fe26a60 | 1674 | unlock: |
559fb51b SB |
1675 | spin_unlock(&adapter->async_lock); |
1676 | return IRQ_RETVAL(handled != 0); | |
1677 | } | |
8199d3a7 | 1678 | |
7fe26a60 | 1679 | #else |
559fb51b SB |
1680 | /* |
1681 | * Main interrupt handler, optimized assuming that we took a 'DATA' | |
1682 | * interrupt. | |
1683 | * | |
1684 | * 1. Clear the interrupt | |
1685 | * 2. Loop while we find valid descriptors and process them; accumulate | |
1686 | * information that can be processed after the loop | |
1687 | * 3. Tell the SGE at which index we stopped processing descriptors | |
1688 | * 4. Bookkeeping; free TX buffers, ring doorbell if there are any | |
1689 | * outstanding TX buffers waiting, replenish RX buffers, potentially | |
1690 | * reenable upper layers if they were turned off due to lack of TX | |
1691 | * resources which are available again. | |
1692 | * 5. If we took an interrupt, but no valid respQ descriptors was found we | |
1693 | * let the slow_intr_handler run and do error handling. | |
1694 | */ | |
7fe26a60 | 1695 | irqreturn_t t1_interrupt(int irq, void *cookie) |
559fb51b SB |
1696 | { |
1697 | int work_done; | |
1698 | struct respQ_e *e; | |
1699 | struct adapter *adapter = cookie; | |
1700 | struct respQ *Q = &adapter->sge->respQ; | |
8199d3a7 | 1701 | |
559fb51b SB |
1702 | spin_lock(&adapter->async_lock); |
1703 | e = &Q->entries[Q->cidx]; | |
1704 | prefetch(e); | |
8199d3a7 | 1705 | |
559fb51b | 1706 | writel(F_PL_INTR_SGE_DATA, adapter->regs + A_PL_CAUSE); |
8199d3a7 | 1707 | |
559fb51b SB |
1708 | if (likely(e->GenerationBit == Q->genbit)) |
1709 | work_done = process_responses(adapter, -1); | |
1710 | else | |
1711 | work_done = t1_slow_intr_handler(adapter); | |
8199d3a7 | 1712 | |
559fb51b SB |
1713 | /* |
1714 | * The unconditional clearing of the PL_CAUSE above may have raced | |
1715 | * with DMA completion and the corresponding generation of a response | |
1716 | * to cause us to miss the resulting data interrupt. The next write | |
1717 | * is also unconditional to recover the missed interrupt and render | |
1718 | * this race harmless. | |
1719 | */ | |
1720 | writel(Q->cidx, adapter->regs + A_SG_SLEEPING); | |
1721 | ||
1722 | if (!work_done) | |
1723 | adapter->sge->stats.unhandled_irqs++; | |
1724 | spin_unlock(&adapter->async_lock); | |
1725 | return IRQ_RETVAL(work_done != 0); | |
1726 | } | |
7fe26a60 | 1727 | #endif |
559fb51b SB |
1728 | |
1729 | /* | |
1730 | * Enqueues the sk_buff onto the cmdQ[qid] and has hardware fetch it. | |
1731 | * | |
1732 | * The code figures out how many entries the sk_buff will require in the | |
1733 | * cmdQ and updates the cmdQ data structure with the state once the enqueue | |
1734 | * has complete. Then, it doesn't access the global structure anymore, but | |
1735 | * uses the corresponding fields on the stack. In conjuction with a spinlock | |
1736 | * around that code, we can make the function reentrant without holding the | |
1737 | * lock when we actually enqueue (which might be expensive, especially on | |
1738 | * architectures with IO MMUs). | |
1739 | * | |
1740 | * This runs with softirqs disabled. | |
1741 | */ | |
aa84505f SH |
1742 | static int t1_sge_tx(struct sk_buff *skb, struct adapter *adapter, |
1743 | unsigned int qid, struct net_device *dev) | |
559fb51b SB |
1744 | { |
1745 | struct sge *sge = adapter->sge; | |
1746 | struct cmdQ *q = &sge->cmdQ[qid]; | |
f1d3d38a | 1747 | unsigned int credits, pidx, genbit, count, use_sched_skb = 0; |
559fb51b | 1748 | |
cabdfb37 SH |
1749 | if (!spin_trylock(&q->lock)) |
1750 | return NETDEV_TX_LOCKED; | |
1751 | ||
559fb51b SB |
1752 | reclaim_completed_tx(sge, q); |
1753 | ||
1754 | pidx = q->pidx; | |
1755 | credits = q->size - q->in_use; | |
1756 | count = 1 + skb_shinfo(skb)->nr_frags; | |
f1d3d38a | 1757 | count += compute_large_page_tx_descs(skb); |
559fb51b | 1758 | |
f1d3d38a SH |
1759 | /* Ethernet packet */ |
1760 | if (unlikely(credits < count)) { | |
1761 | if (!netif_queue_stopped(dev)) { | |
559fb51b SB |
1762 | netif_stop_queue(dev); |
1763 | set_bit(dev->if_port, &sge->stopped_tx_queues); | |
232a347a | 1764 | sge->stats.cmdQ_full[2]++; |
f1d3d38a SH |
1765 | CH_ERR("%s: Tx ring full while queue awake!\n", |
1766 | adapter->name); | |
8199d3a7 | 1767 | } |
f1d3d38a SH |
1768 | spin_unlock(&q->lock); |
1769 | return NETDEV_TX_BUSY; | |
1770 | } | |
1771 | ||
1772 | if (unlikely(credits - count < q->stop_thres)) { | |
1773 | netif_stop_queue(dev); | |
1774 | set_bit(dev->if_port, &sge->stopped_tx_queues); | |
1775 | sge->stats.cmdQ_full[2]++; | |
1776 | } | |
1777 | ||
1778 | /* T204 cmdQ0 skbs that are destined for a certain port have to go | |
1779 | * through the scheduler. | |
1780 | */ | |
1781 | if (sge->tx_sched && !qid && skb->dev) { | |
356bd146 | 1782 | use_sched: |
f1d3d38a SH |
1783 | use_sched_skb = 1; |
1784 | /* Note that the scheduler might return a different skb than | |
1785 | * the one passed in. | |
1786 | */ | |
1787 | skb = sched_skb(sge, skb, credits); | |
1788 | if (!skb) { | |
1789 | spin_unlock(&q->lock); | |
1790 | return NETDEV_TX_OK; | |
559fb51b | 1791 | } |
f1d3d38a SH |
1792 | pidx = q->pidx; |
1793 | count = 1 + skb_shinfo(skb)->nr_frags; | |
1794 | count += compute_large_page_tx_descs(skb); | |
559fb51b | 1795 | } |
f1d3d38a | 1796 | |
559fb51b SB |
1797 | q->in_use += count; |
1798 | genbit = q->genbit; | |
f1d3d38a | 1799 | pidx = q->pidx; |
559fb51b SB |
1800 | q->pidx += count; |
1801 | if (q->pidx >= q->size) { | |
1802 | q->pidx -= q->size; | |
1803 | q->genbit ^= 1; | |
8199d3a7 | 1804 | } |
559fb51b | 1805 | spin_unlock(&q->lock); |
8199d3a7 | 1806 | |
559fb51b | 1807 | write_tx_descs(adapter, skb, pidx, genbit, q); |
8199d3a7 CL |
1808 | |
1809 | /* | |
1810 | * We always ring the doorbell for cmdQ1. For cmdQ0, we only ring | |
1811 | * the doorbell if the Q is asleep. There is a natural race, where | |
1812 | * the hardware is going to sleep just after we checked, however, | |
1813 | * then the interrupt handler will detect the outstanding TX packet | |
1814 | * and ring the doorbell for us. | |
1815 | */ | |
559fb51b SB |
1816 | if (qid) |
1817 | doorbell_pio(adapter, F_CMDQ1_ENABLE); | |
1818 | else { | |
1819 | clear_bit(CMDQ_STAT_LAST_PKT_DB, &q->status); | |
1820 | if (test_and_set_bit(CMDQ_STAT_RUNNING, &q->status) == 0) { | |
1821 | set_bit(CMDQ_STAT_LAST_PKT_DB, &q->status); | |
1822 | writel(F_CMDQ0_ENABLE, adapter->regs + A_SG_DOORBELL); | |
1823 | } | |
8199d3a7 | 1824 | } |
f1d3d38a SH |
1825 | |
1826 | if (use_sched_skb) { | |
1827 | if (spin_trylock(&q->lock)) { | |
1828 | credits = q->size - q->in_use; | |
1829 | skb = NULL; | |
1830 | goto use_sched; | |
1831 | } | |
1832 | } | |
aa84505f | 1833 | return NETDEV_TX_OK; |
8199d3a7 CL |
1834 | } |
1835 | ||
1836 | #define MK_ETH_TYPE_MSS(type, mss) (((mss) & 0x3FFF) | ((type) << 14)) | |
1837 | ||
559fb51b SB |
1838 | /* |
1839 | * eth_hdr_len - return the length of an Ethernet header | |
1840 | * @data: pointer to the start of the Ethernet header | |
1841 | * | |
1842 | * Returns the length of an Ethernet header, including optional VLAN tag. | |
1843 | */ | |
1844 | static inline int eth_hdr_len(const void *data) | |
1845 | { | |
1846 | const struct ethhdr *e = data; | |
1847 | ||
1848 | return e->h_proto == htons(ETH_P_8021Q) ? VLAN_ETH_HLEN : ETH_HLEN; | |
1849 | } | |
1850 | ||
8199d3a7 CL |
1851 | /* |
1852 | * Adds the CPL header to the sk_buff and passes it to t1_sge_tx. | |
1853 | */ | |
1854 | int t1_start_xmit(struct sk_buff *skb, struct net_device *dev) | |
1855 | { | |
1856 | struct adapter *adapter = dev->priv; | |
559fb51b | 1857 | struct sge *sge = adapter->sge; |
56f643c2 | 1858 | struct sge_port_stats *st = per_cpu_ptr(sge->port_stats[dev->if_port], smp_processor_id()); |
8199d3a7 | 1859 | struct cpl_tx_pkt *cpl; |
cabdfb37 SH |
1860 | struct sk_buff *orig_skb = skb; |
1861 | int ret; | |
8199d3a7 | 1862 | |
f1d3d38a SH |
1863 | if (skb->protocol == htons(ETH_P_CPL5)) |
1864 | goto send; | |
1865 | ||
1866 | if (skb_shinfo(skb)->gso_size) { | |
8199d3a7 CL |
1867 | int eth_type; |
1868 | struct cpl_tx_pkt_lso *hdr; | |
1869 | ||
56f643c2 | 1870 | ++st->tx_tso; |
559fb51b | 1871 | |
8199d3a7 CL |
1872 | eth_type = skb->nh.raw - skb->data == ETH_HLEN ? |
1873 | CPL_ETH_II : CPL_ETH_II_VLAN; | |
1874 | ||
1875 | hdr = (struct cpl_tx_pkt_lso *)skb_push(skb, sizeof(*hdr)); | |
1876 | hdr->opcode = CPL_TX_PKT_LSO; | |
1877 | hdr->ip_csum_dis = hdr->l4_csum_dis = 0; | |
1878 | hdr->ip_hdr_words = skb->nh.iph->ihl; | |
1879 | hdr->tcp_hdr_words = skb->h.th->doff; | |
1880 | hdr->eth_type_mss = htons(MK_ETH_TYPE_MSS(eth_type, | |
f1d3d38a | 1881 | skb_shinfo(skb)->gso_size)); |
8199d3a7 CL |
1882 | hdr->len = htonl(skb->len - sizeof(*hdr)); |
1883 | cpl = (struct cpl_tx_pkt *)hdr; | |
f1d3d38a | 1884 | } else { |
8199d3a7 | 1885 | /* |
356bd146 | 1886 | * Packets shorter than ETH_HLEN can break the MAC, drop them |
559fb51b SB |
1887 | * early. Also, we may get oversized packets because some |
1888 | * parts of the kernel don't handle our unusual hard_header_len | |
1889 | * right, drop those too. | |
8199d3a7 | 1890 | */ |
559fb51b SB |
1891 | if (unlikely(skb->len < ETH_HLEN || |
1892 | skb->len > dev->mtu + eth_hdr_len(skb->data))) { | |
f1d3d38a SH |
1893 | pr_debug("%s: packet size %d hdr %d mtu%d\n", dev->name, |
1894 | skb->len, eth_hdr_len(skb->data), dev->mtu); | |
559fb51b | 1895 | dev_kfree_skb_any(skb); |
aa84505f | 1896 | return NETDEV_TX_OK; |
559fb51b SB |
1897 | } |
1898 | ||
1899 | /* | |
1900 | * We are using a non-standard hard_header_len and some kernel | |
1901 | * components, such as pktgen, do not handle it right. | |
1902 | * Complain when this happens but try to fix things up. | |
1903 | */ | |
f1d3d38a | 1904 | if (unlikely(skb_headroom(skb) < dev->hard_header_len - ETH_HLEN)) { |
f1d3d38a SH |
1905 | pr_debug("%s: headroom %d header_len %d\n", dev->name, |
1906 | skb_headroom(skb), dev->hard_header_len); | |
1907 | ||
559fb51b SB |
1908 | if (net_ratelimit()) |
1909 | printk(KERN_ERR "%s: inadequate headroom in " | |
1910 | "Tx packet\n", dev->name); | |
1911 | skb = skb_realloc_headroom(skb, sizeof(*cpl)); | |
1912 | dev_kfree_skb_any(orig_skb); | |
1913 | if (!skb) | |
aa84505f | 1914 | return NETDEV_TX_OK; |
559fb51b | 1915 | } |
8199d3a7 CL |
1916 | |
1917 | if (!(adapter->flags & UDP_CSUM_CAPABLE) && | |
84fa7933 | 1918 | skb->ip_summed == CHECKSUM_PARTIAL && |
f1d3d38a | 1919 | skb->nh.iph->protocol == IPPROTO_UDP) { |
84fa7933 | 1920 | if (unlikely(skb_checksum_help(skb))) { |
f1d3d38a | 1921 | pr_debug("%s: unable to do udp checksum\n", dev->name); |
559fb51b | 1922 | dev_kfree_skb_any(skb); |
aa84505f | 1923 | return NETDEV_TX_OK; |
559fb51b | 1924 | } |
f1d3d38a | 1925 | } |
8199d3a7 | 1926 | |
559fb51b SB |
1927 | /* Hmmm, assuming to catch the gratious arp... and we'll use |
1928 | * it to flush out stuck espi packets... | |
f1d3d38a SH |
1929 | */ |
1930 | if ((unlikely(!adapter->sge->espibug_skb[dev->if_port]))) { | |
8199d3a7 | 1931 | if (skb->protocol == htons(ETH_P_ARP) && |
559fb51b | 1932 | skb->nh.arph->ar_op == htons(ARPOP_REQUEST)) { |
f1d3d38a | 1933 | adapter->sge->espibug_skb[dev->if_port] = skb; |
559fb51b SB |
1934 | /* We want to re-use this skb later. We |
1935 | * simply bump the reference count and it | |
1936 | * will not be freed... | |
1937 | */ | |
1938 | skb = skb_get(skb); | |
1939 | } | |
8199d3a7 | 1940 | } |
559fb51b SB |
1941 | |
1942 | cpl = (struct cpl_tx_pkt *)__skb_push(skb, sizeof(*cpl)); | |
8199d3a7 CL |
1943 | cpl->opcode = CPL_TX_PKT; |
1944 | cpl->ip_csum_dis = 1; /* SW calculates IP csum */ | |
84fa7933 | 1945 | cpl->l4_csum_dis = skb->ip_summed == CHECKSUM_PARTIAL ? 0 : 1; |
8199d3a7 | 1946 | /* the length field isn't used so don't bother setting it */ |
559fb51b | 1947 | |
84fa7933 | 1948 | st->tx_cso += (skb->ip_summed == CHECKSUM_PARTIAL); |
8199d3a7 CL |
1949 | } |
1950 | cpl->iff = dev->if_port; | |
1951 | ||
1952 | #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE) | |
1953 | if (adapter->vlan_grp && vlan_tx_tag_present(skb)) { | |
1954 | cpl->vlan_valid = 1; | |
1955 | cpl->vlan = htons(vlan_tx_tag_get(skb)); | |
559fb51b | 1956 | st->vlan_insert++; |
8199d3a7 CL |
1957 | } else |
1958 | #endif | |
1959 | cpl->vlan_valid = 0; | |
1960 | ||
f1d3d38a | 1961 | send: |
56f643c2 | 1962 | st->tx_packets++; |
8199d3a7 | 1963 | dev->trans_start = jiffies; |
cabdfb37 SH |
1964 | ret = t1_sge_tx(skb, adapter, 0, dev); |
1965 | ||
1966 | /* If transmit busy, and we reallocated skb's due to headroom limit, | |
1967 | * then silently discard to avoid leak. | |
1968 | */ | |
1969 | if (unlikely(ret != NETDEV_TX_OK && skb != orig_skb)) { | |
356bd146 | 1970 | dev_kfree_skb_any(skb); |
cabdfb37 | 1971 | ret = NETDEV_TX_OK; |
356bd146 | 1972 | } |
cabdfb37 | 1973 | return ret; |
559fb51b | 1974 | } |
8199d3a7 | 1975 | |
559fb51b SB |
1976 | /* |
1977 | * Callback for the Tx buffer reclaim timer. Runs with softirqs disabled. | |
1978 | */ | |
1979 | static void sge_tx_reclaim_cb(unsigned long data) | |
1980 | { | |
1981 | int i; | |
1982 | struct sge *sge = (struct sge *)data; | |
1983 | ||
1984 | for (i = 0; i < SGE_CMDQ_N; ++i) { | |
1985 | struct cmdQ *q = &sge->cmdQ[i]; | |
1986 | ||
1987 | if (!spin_trylock(&q->lock)) | |
1988 | continue; | |
8199d3a7 | 1989 | |
559fb51b | 1990 | reclaim_completed_tx(sge, q); |
f1d3d38a SH |
1991 | if (i == 0 && q->in_use) { /* flush pending credits */ |
1992 | writel(F_CMDQ0_ENABLE, sge->adapter->regs + A_SG_DOORBELL); | |
1993 | } | |
559fb51b SB |
1994 | spin_unlock(&q->lock); |
1995 | } | |
1996 | mod_timer(&sge->tx_reclaim_timer, jiffies + TX_RECLAIM_PERIOD); | |
1997 | } | |
1998 | ||
1999 | /* | |
2000 | * Propagate changes of the SGE coalescing parameters to the HW. | |
2001 | */ | |
2002 | int t1_sge_set_coalesce_params(struct sge *sge, struct sge_params *p) | |
2003 | { | |
559fb51b SB |
2004 | sge->fixed_intrtimer = p->rx_coalesce_usecs * |
2005 | core_ticks_per_usec(sge->adapter); | |
2006 | writel(sge->fixed_intrtimer, sge->adapter->regs + A_SG_INTRTIMER); | |
8199d3a7 CL |
2007 | return 0; |
2008 | } | |
2009 | ||
559fb51b SB |
2010 | /* |
2011 | * Allocates both RX and TX resources and configures the SGE. However, | |
2012 | * the hardware is not enabled yet. | |
2013 | */ | |
2014 | int t1_sge_configure(struct sge *sge, struct sge_params *p) | |
8199d3a7 | 2015 | { |
559fb51b SB |
2016 | if (alloc_rx_resources(sge, p)) |
2017 | return -ENOMEM; | |
2018 | if (alloc_tx_resources(sge, p)) { | |
2019 | free_rx_resources(sge); | |
2020 | return -ENOMEM; | |
2021 | } | |
2022 | configure_sge(sge, p); | |
2023 | ||
2024 | /* | |
2025 | * Now that we have sized the free lists calculate the payload | |
2026 | * capacity of the large buffers. Other parts of the driver use | |
2027 | * this to set the max offload coalescing size so that RX packets | |
2028 | * do not overflow our large buffers. | |
2029 | */ | |
2030 | p->large_buf_capacity = jumbo_payload_capacity(sge); | |
2031 | return 0; | |
2032 | } | |
8199d3a7 | 2033 | |
559fb51b SB |
2034 | /* |
2035 | * Disables the DMA engine. | |
2036 | */ | |
2037 | void t1_sge_stop(struct sge *sge) | |
2038 | { | |
f1d3d38a | 2039 | int i; |
559fb51b | 2040 | writel(0, sge->adapter->regs + A_SG_CONTROL); |
f1d3d38a SH |
2041 | readl(sge->adapter->regs + A_SG_CONTROL); /* flush */ |
2042 | ||
559fb51b SB |
2043 | if (is_T2(sge->adapter)) |
2044 | del_timer_sync(&sge->espibug_timer); | |
f1d3d38a | 2045 | |
559fb51b | 2046 | del_timer_sync(&sge->tx_reclaim_timer); |
f1d3d38a SH |
2047 | if (sge->tx_sched) |
2048 | tx_sched_stop(sge); | |
2049 | ||
2050 | for (i = 0; i < MAX_NPORTS; i++) | |
2051 | if (sge->espibug_skb[i]) | |
2052 | kfree_skb(sge->espibug_skb[i]); | |
8199d3a7 CL |
2053 | } |
2054 | ||
559fb51b SB |
2055 | /* |
2056 | * Enables the DMA engine. | |
2057 | */ | |
2058 | void t1_sge_start(struct sge *sge) | |
8199d3a7 | 2059 | { |
559fb51b SB |
2060 | refill_free_list(sge, &sge->freelQ[0]); |
2061 | refill_free_list(sge, &sge->freelQ[1]); | |
2062 | ||
2063 | writel(sge->sge_control, sge->adapter->regs + A_SG_CONTROL); | |
2064 | doorbell_pio(sge->adapter, F_FL0_ENABLE | F_FL1_ENABLE); | |
f1d3d38a | 2065 | readl(sge->adapter->regs + A_SG_CONTROL); /* flush */ |
559fb51b SB |
2066 | |
2067 | mod_timer(&sge->tx_reclaim_timer, jiffies + TX_RECLAIM_PERIOD); | |
2068 | ||
f1d3d38a | 2069 | if (is_T2(sge->adapter)) |
559fb51b SB |
2070 | mod_timer(&sge->espibug_timer, jiffies + sge->espibug_timeout); |
2071 | } | |
2072 | ||
2073 | /* | |
2074 | * Callback for the T2 ESPI 'stuck packet feature' workaorund | |
2075 | */ | |
f1d3d38a | 2076 | static void espibug_workaround_t204(unsigned long data) |
559fb51b SB |
2077 | { |
2078 | struct adapter *adapter = (struct adapter *)data; | |
8199d3a7 | 2079 | struct sge *sge = adapter->sge; |
f1d3d38a SH |
2080 | unsigned int nports = adapter->params.nports; |
2081 | u32 seop[MAX_NPORTS]; | |
8199d3a7 | 2082 | |
f1d3d38a SH |
2083 | if (adapter->open_device_map & PORT_MASK) { |
2084 | int i; | |
356bd146 FR |
2085 | |
2086 | if (t1_espi_get_mon_t204(adapter, &(seop[0]), 0) < 0) | |
f1d3d38a | 2087 | return; |
356bd146 | 2088 | |
f1d3d38a | 2089 | for (i = 0; i < nports; i++) { |
356bd146 FR |
2090 | struct sk_buff *skb = sge->espibug_skb[i]; |
2091 | ||
2092 | if (!netif_running(adapter->port[i].dev) || | |
2093 | netif_queue_stopped(adapter->port[i].dev) || | |
2094 | !seop[i] || ((seop[i] & 0xfff) != 0) || !skb) | |
2095 | continue; | |
2096 | ||
2097 | if (!skb->cb[0]) { | |
2098 | u8 ch_mac_addr[ETH_ALEN] = { | |
2099 | 0x0, 0x7, 0x43, 0x0, 0x0, 0x0 | |
2100 | }; | |
2101 | ||
2102 | memcpy(skb->data + sizeof(struct cpl_tx_pkt), | |
2103 | ch_mac_addr, ETH_ALEN); | |
2104 | memcpy(skb->data + skb->len - 10, | |
2105 | ch_mac_addr, ETH_ALEN); | |
2106 | skb->cb[0] = 0xff; | |
559fb51b | 2107 | } |
356bd146 FR |
2108 | |
2109 | /* bump the reference count to avoid freeing of | |
2110 | * the skb once the DMA has completed. | |
2111 | */ | |
2112 | skb = skb_get(skb); | |
2113 | t1_sge_tx(skb, adapter, 0, adapter->port[i].dev); | |
559fb51b SB |
2114 | } |
2115 | } | |
2116 | mod_timer(&sge->espibug_timer, jiffies + sge->espibug_timeout); | |
8199d3a7 CL |
2117 | } |
2118 | ||
f1d3d38a SH |
2119 | static void espibug_workaround(unsigned long data) |
2120 | { | |
2121 | struct adapter *adapter = (struct adapter *)data; | |
2122 | struct sge *sge = adapter->sge; | |
2123 | ||
2124 | if (netif_running(adapter->port[0].dev)) { | |
2125 | struct sk_buff *skb = sge->espibug_skb[0]; | |
2126 | u32 seop = t1_espi_get_mon(adapter, 0x930, 0); | |
2127 | ||
2128 | if ((seop & 0xfff0fff) == 0xfff && skb) { | |
2129 | if (!skb->cb[0]) { | |
2130 | u8 ch_mac_addr[ETH_ALEN] = | |
2131 | {0x0, 0x7, 0x43, 0x0, 0x0, 0x0}; | |
2132 | memcpy(skb->data + sizeof(struct cpl_tx_pkt), | |
2133 | ch_mac_addr, ETH_ALEN); | |
2134 | memcpy(skb->data + skb->len - 10, ch_mac_addr, | |
2135 | ETH_ALEN); | |
2136 | skb->cb[0] = 0xff; | |
2137 | } | |
2138 | ||
2139 | /* bump the reference count to avoid freeing of the | |
2140 | * skb once the DMA has completed. | |
2141 | */ | |
2142 | skb = skb_get(skb); | |
2143 | t1_sge_tx(skb, adapter, 0, adapter->port[0].dev); | |
2144 | } | |
2145 | } | |
2146 | mod_timer(&sge->espibug_timer, jiffies + sge->espibug_timeout); | |
2147 | } | |
2148 | ||
559fb51b SB |
2149 | /* |
2150 | * Creates a t1_sge structure and returns suggested resource parameters. | |
2151 | */ | |
2152 | struct sge * __devinit t1_sge_create(struct adapter *adapter, | |
2153 | struct sge_params *p) | |
2154 | { | |
cbee9f91 | 2155 | struct sge *sge = kzalloc(sizeof(*sge), GFP_KERNEL); |
56f643c2 | 2156 | int i; |
559fb51b SB |
2157 | |
2158 | if (!sge) | |
2159 | return NULL; | |
559fb51b SB |
2160 | |
2161 | sge->adapter = adapter; | |
2162 | sge->netdev = adapter->port[0].dev; | |
2163 | sge->rx_pkt_pad = t1_is_T1B(adapter) ? 0 : 2; | |
2164 | sge->jumbo_fl = t1_is_T1B(adapter) ? 1 : 0; | |
2165 | ||
56f643c2 SH |
2166 | for_each_port(adapter, i) { |
2167 | sge->port_stats[i] = alloc_percpu(struct sge_port_stats); | |
2168 | if (!sge->port_stats[i]) | |
2169 | goto nomem_port; | |
2170 | } | |
2171 | ||
559fb51b SB |
2172 | init_timer(&sge->tx_reclaim_timer); |
2173 | sge->tx_reclaim_timer.data = (unsigned long)sge; | |
2174 | sge->tx_reclaim_timer.function = sge_tx_reclaim_cb; | |
2175 | ||
2176 | if (is_T2(sge->adapter)) { | |
2177 | init_timer(&sge->espibug_timer); | |
f1d3d38a SH |
2178 | |
2179 | if (adapter->params.nports > 1) { | |
2180 | tx_sched_init(sge); | |
2181 | sge->espibug_timer.function = espibug_workaround_t204; | |
d7487421 | 2182 | } else |
f1d3d38a | 2183 | sge->espibug_timer.function = espibug_workaround; |
559fb51b | 2184 | sge->espibug_timer.data = (unsigned long)sge->adapter; |
f1d3d38a | 2185 | |
559fb51b | 2186 | sge->espibug_timeout = 1; |
f1d3d38a SH |
2187 | /* for T204, every 10ms */ |
2188 | if (adapter->params.nports > 1) | |
2189 | sge->espibug_timeout = HZ/100; | |
559fb51b | 2190 | } |
356bd146 | 2191 | |
559fb51b SB |
2192 | |
2193 | p->cmdQ_size[0] = SGE_CMDQ0_E_N; | |
2194 | p->cmdQ_size[1] = SGE_CMDQ1_E_N; | |
2195 | p->freelQ_size[!sge->jumbo_fl] = SGE_FREEL_SIZE; | |
2196 | p->freelQ_size[sge->jumbo_fl] = SGE_JUMBO_FREEL_SIZE; | |
f1d3d38a SH |
2197 | if (sge->tx_sched) { |
2198 | if (board_info(sge->adapter)->board == CHBT_BOARD_CHT204) | |
2199 | p->rx_coalesce_usecs = 15; | |
2200 | else | |
2201 | p->rx_coalesce_usecs = 50; | |
2202 | } else | |
2203 | p->rx_coalesce_usecs = 50; | |
2204 | ||
559fb51b SB |
2205 | p->coalesce_enable = 0; |
2206 | p->sample_interval_usecs = 0; | |
559fb51b SB |
2207 | |
2208 | return sge; | |
56f643c2 SH |
2209 | nomem_port: |
2210 | while (i >= 0) { | |
2211 | free_percpu(sge->port_stats[i]); | |
2212 | --i; | |
2213 | } | |
2214 | kfree(sge); | |
2215 | return NULL; | |
2216 | ||
559fb51b | 2217 | } |