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signals: consolidate checks for whether or not to ignore a signal
[deliverable/linux.git] / drivers / net / chelsio / subr.c
CommitLineData
8199d3a7
CL		 1/*****************************************************************************
2 * *
3 * File: subr.c *
559fb51b
SB		 4 * $Revision: 1.27 $ *
5 * $Date: 2005/06/22 01:08:36 $ *
8199d3a7
CL		 6 * Description: *
7 * Various subroutines (intr,pio,etc.) used by Chelsio 10G Ethernet driver. *
8 * part of the Chelsio 10Gb Ethernet Driver. *
9 * *
10 * This program is free software; you can redistribute it and/or modify *
11 * it under the terms of the GNU General Public License, version 2, as *
12 * published by the Free Software Foundation. *
13 * *
14 * You should have received a copy of the GNU General Public License along *
15 * with this program; if not, write to the Free Software Foundation, Inc., *
16 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
17 * *
18 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED *
19 * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF *
20 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. *
21 * *
22 * http://www.chelsio.com *
23 * *
24 * Copyright (c) 2003 - 2005 Chelsio Communications, Inc. *
25 * All rights reserved. *
26 * *
27 * Maintainers: maintainers@chelsio.com *
28 * *
29 * Authors: Dimitrios Michailidis <dm@chelsio.com> *
30 * Tina Yang <tainay@chelsio.com> *
31 * Felix Marti <felix@chelsio.com> *
32 * Scott Bardone <sbardone@chelsio.com> *
33 * Kurt Ottaway <kottaway@chelsio.com> *
34 * Frank DiMambro <frank@chelsio.com> *
35 * *
36 * History: *
37 * *
38 ****************************************************************************/
39
40#include "common.h"
41#include "elmer0.h"
42#include "regs.h"
8199d3a7
CL		 43#include "gmac.h"
44#include "cphy.h"
45#include "sge.h"
f1d3d38a 46#include "tp.h"
8199d3a7
CL		 47#include "espi.h"
48
49/**
50 * t1_wait_op_done - wait until an operation is completed
51 * @adapter: the adapter performing the operation
52 * @reg: the register to check for completion
53 * @mask: a single-bit field within @reg that indicates completion
54 * @polarity: the value of the field when the operation is completed
55 * @attempts: number of check iterations
56 * @delay: delay in usecs between iterations
57 *
58 * Wait until an operation is completed by checking a bit in a register
59 * up to @attempts times. Returns %0 if the operation completes and %1
60 * otherwise.
61 */
62static int t1_wait_op_done(adapter_t *adapter, int reg, u32 mask, int polarity,
f1d3d38a 63 int attempts, int delay)
8199d3a7
CL		 64{
65 while (1) {
559fb51b 66 u32 val = readl(adapter->regs + reg) & mask;
8199d3a7
CL		 67
68 if (!!val == polarity)
69 return 0;
70 if (--attempts == 0)
71 return 1;
72 if (delay)
73 udelay(delay);
74 }
75}
76
77#define TPI_ATTEMPTS 50
78
79/*
80 * Write a register over the TPI interface (unlocked and locked versions).
81 */
f1d3d38a 82int __t1_tpi_write(adapter_t *adapter, u32 addr, u32 value)
8199d3a7
CL		 83{
84 int tpi_busy;
85
559fb51b
SB		 86 writel(addr, adapter->regs + A_TPI_ADDR);
87 writel(value, adapter->regs + A_TPI_WR_DATA);
88 writel(F_TPIWR, adapter->regs + A_TPI_CSR);
8199d3a7
CL		 89
90 tpi_busy = t1_wait_op_done(adapter, A_TPI_CSR, F_TPIRDY, 1,
91 TPI_ATTEMPTS, 3);
92 if (tpi_busy)
93 CH_ALERT("%s: TPI write to 0x%x failed\n",
94 adapter->name, addr);
95 return tpi_busy;
96}
97
98int t1_tpi_write(adapter_t *adapter, u32 addr, u32 value)
99{
100 int ret;
101
f1d3d38a 102 spin_lock(&adapter->tpi_lock);
8199d3a7 103 ret = __t1_tpi_write(adapter, addr, value);
f1d3d38a 104 spin_unlock(&adapter->tpi_lock);
8199d3a7
CL		 105 return ret;
106}
107
108/*
109 * Read a register over the TPI interface (unlocked and locked versions).
110 */
f1d3d38a 111int __t1_tpi_read(adapter_t *adapter, u32 addr, u32 *valp)
8199d3a7
CL		 112{
113 int tpi_busy;
114
559fb51b
SB		 115 writel(addr, adapter->regs + A_TPI_ADDR);
116 writel(0, adapter->regs + A_TPI_CSR);
8199d3a7
CL		 117
118 tpi_busy = t1_wait_op_done(adapter, A_TPI_CSR, F_TPIRDY, 1,
119 TPI_ATTEMPTS, 3);
120 if (tpi_busy)
121 CH_ALERT("%s: TPI read from 0x%x failed\n",
122 adapter->name, addr);
123 else
559fb51b 124 *valp = readl(adapter->regs + A_TPI_RD_DATA);
8199d3a7
CL		 125 return tpi_busy;
126}
127
128int t1_tpi_read(adapter_t *adapter, u32 addr, u32 *valp)
129{
130 int ret;
131
f1d3d38a 132 spin_lock(&adapter->tpi_lock);
8199d3a7 133 ret = __t1_tpi_read(adapter, addr, valp);
f1d3d38a 134 spin_unlock(&adapter->tpi_lock);
8199d3a7
CL		 135 return ret;
136}
137
f1d3d38a
SH		 138/*
139 * Set a TPI parameter.
140 */
141static void t1_tpi_par(adapter_t *adapter, u32 value)
142{
143 writel(V_TPIPAR(value), adapter->regs + A_TPI_PAR);
144}
145
8199d3a7
CL		 146/*
147 * Called when a port's link settings change to propagate the new values to the
148 * associated PHY and MAC. After performing the common tasks it invokes an
149 * OS-specific handler.
150 */
f1d3d38a 151void t1_link_changed(adapter_t *adapter, int port_id)
8199d3a7
CL		 152{
153 int link_ok, speed, duplex, fc;
154 struct cphy *phy = adapter->port[port_id].phy;
155 struct link_config *lc = &adapter->port[port_id].link_config;
156
157 phy->ops->get_link_status(phy, &link_ok, &speed, &duplex, &fc);
158
159 lc->speed = speed < 0 ? SPEED_INVALID : speed;
160 lc->duplex = duplex < 0 ? DUPLEX_INVALID : duplex;
161 if (!(lc->requested_fc & PAUSE_AUTONEG))
162 fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
163
164 if (link_ok && speed >= 0 && lc->autoneg == AUTONEG_ENABLE) {
165 /* Set MAC speed, duplex, and flow control to match PHY. */
166 struct cmac *mac = adapter->port[port_id].mac;
167
168 mac->ops->set_speed_duplex_fc(mac, speed, duplex, fc);
169 lc->fc = (unsigned char)fc;
170 }
f1d3d38a 171 t1_link_negotiated(adapter, port_id, link_ok, speed, duplex, fc);
8199d3a7
CL		 172}
173
174static int t1_pci_intr_handler(adapter_t *adapter)
175{
176 u32 pcix_cause;
177
11e5a202 178 pci_read_config_dword(adapter->pdev, A_PCICFG_INTR_CAUSE, &pcix_cause);
8199d3a7
CL		 179
180 if (pcix_cause) {
181 pci_write_config_dword(adapter->pdev, A_PCICFG_INTR_CAUSE,
11e5a202 182 pcix_cause);
8199d3a7
CL		 183 t1_fatal_err(adapter); /* PCI errors are fatal */
184 }
185 return 0;
186}
187
352c417d
SH		 188#ifdef CONFIG_CHELSIO_T1_COUGAR
189#include "cspi.h"
190#endif
191#ifdef CONFIG_CHELSIO_T1_1G
192#include "fpga_defs.h"
193
194/*
195 * PHY interrupt handler for FPGA boards.
196 */
197static int fpga_phy_intr_handler(adapter_t *adapter)
198{
199 int p;
200 u32 cause = readl(adapter->regs + FPGA_GMAC_ADDR_INTERRUPT_CAUSE);
201
202 for_each_port(adapter, p)
203 if (cause & (1 << p)) {
204 struct cphy *phy = adapter->port[p].phy;
205 int phy_cause = phy->ops->interrupt_handler(phy);
206
207 if (phy_cause & cphy_cause_link_change)
208 t1_link_changed(adapter, p);
209 }
210 writel(cause, adapter->regs + FPGA_GMAC_ADDR_INTERRUPT_CAUSE);
211 return 0;
212}
213
214/*
215 * Slow path interrupt handler for FPGAs.
216 */
217static int fpga_slow_intr(adapter_t *adapter)
218{
219 u32 cause = readl(adapter->regs + A_PL_CAUSE);
220
221 cause &= ~F_PL_INTR_SGE_DATA;
222 if (cause & F_PL_INTR_SGE_ERR)
223 t1_sge_intr_error_handler(adapter->sge);
224
225 if (cause & FPGA_PCIX_INTERRUPT_GMAC)
356bd146 226 fpga_phy_intr_handler(adapter);
352c417d
SH		 227
228 if (cause & FPGA_PCIX_INTERRUPT_TP) {
356bd146 229 /*
352c417d
SH		 230 * FPGA doesn't support MC4 interrupts and it requires
231 * this odd layer of indirection for MC5.
356bd146 232 */
352c417d
SH		 233 u32 tp_cause = readl(adapter->regs + FPGA_TP_ADDR_INTERRUPT_CAUSE);
234
235 /* Clear TP interrupt */
236 writel(tp_cause, adapter->regs + FPGA_TP_ADDR_INTERRUPT_CAUSE);
237 }
238 if (cause & FPGA_PCIX_INTERRUPT_PCIX)
239 t1_pci_intr_handler(adapter);
240
241 /* Clear the interrupts just processed. */
242 if (cause)
243 writel(cause, adapter->regs + A_PL_CAUSE);
244
245 return cause != 0;
246}
247#endif
8199d3a7
CL		 248
249/*
250 * Wait until Elmer's MI1 interface is ready for new operations.
251 */
252static int mi1_wait_until_ready(adapter_t *adapter, int mi1_reg)
253{
254 int attempts = 100, busy;
255
256 do {
257 u32 val;
258
259 __t1_tpi_read(adapter, mi1_reg, &val);
260 busy = val & F_MI1_OP_BUSY;
261 if (busy)
262 udelay(10);
263 } while (busy && --attempts);
264 if (busy)
356bd146 265 CH_ALERT("%s: MDIO operation timed out\n", adapter->name);
8199d3a7
CL		 266 return busy;
267}
268
269/*
270 * MI1 MDIO initialization.
271 */
272static void mi1_mdio_init(adapter_t *adapter, const struct board_info *bi)
273{
274 u32 clkdiv = bi->clock_elmer0 / (2 * bi->mdio_mdc) - 1;
275 u32 val = F_MI1_PREAMBLE_ENABLE | V_MI1_MDI_INVERT(bi->mdio_mdiinv) |
276 V_MI1_MDI_ENABLE(bi->mdio_mdien) | V_MI1_CLK_DIV(clkdiv);
277
278 if (!(bi->caps & SUPPORTED_10000baseT_Full))
279 val |= V_MI1_SOF(1);
280 t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_CFG, val);
281}
282
352c417d
SH		 283#if defined(CONFIG_CHELSIO_T1_1G) || defined(CONFIG_CHELSIO_T1_COUGAR)
284/*
285 * Elmer MI1 MDIO read/write operations.
286 */
287static int mi1_mdio_read(adapter_t *adapter, int phy_addr, int mmd_addr,
288 int reg_addr, unsigned int *valp)
289{
290 u32 addr = V_MI1_REG_ADDR(reg_addr) | V_MI1_PHY_ADDR(phy_addr);
291
292 if (mmd_addr)
293 return -EINVAL;
294
295 spin_lock(&adapter->tpi_lock);
296 __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_ADDR, addr);
297 __t1_tpi_write(adapter,
298 A_ELMER0_PORT0_MI1_OP, MI1_OP_DIRECT_READ);
299 mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);
300 __t1_tpi_read(adapter, A_ELMER0_PORT0_MI1_DATA, valp);
301 spin_unlock(&adapter->tpi_lock);
302 return 0;
303}
304
305static int mi1_mdio_write(adapter_t *adapter, int phy_addr, int mmd_addr,
306 int reg_addr, unsigned int val)
307{
308 u32 addr = V_MI1_REG_ADDR(reg_addr) | V_MI1_PHY_ADDR(phy_addr);
309
310 if (mmd_addr)
311 return -EINVAL;
312
313 spin_lock(&adapter->tpi_lock);
314 __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_ADDR, addr);
315 __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_DATA, val);
316 __t1_tpi_write(adapter,
317 A_ELMER0_PORT0_MI1_OP, MI1_OP_DIRECT_WRITE);
318 mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);
319 spin_unlock(&adapter->tpi_lock);
320 return 0;
321}
322
323#if defined(CONFIG_CHELSIO_T1_1G) || defined(CONFIG_CHELSIO_T1_COUGAR)
459e536b 324static const struct mdio_ops mi1_mdio_ops = {
4c247db1
SH		 325 .init = mi1_mdio_init,
326 .read = mi1_mdio_read,
327 .write = mi1_mdio_write
352c417d
SH		 328};
329#endif
330
331#endif
332
8199d3a7
CL		 333static int mi1_mdio_ext_read(adapter_t *adapter, int phy_addr, int mmd_addr,
334 int reg_addr, unsigned int *valp)
335{
336 u32 addr = V_MI1_REG_ADDR(mmd_addr) | V_MI1_PHY_ADDR(phy_addr);
337
f1d3d38a 338 spin_lock(&adapter->tpi_lock);
8199d3a7
CL		 339
340 /* Write the address we want. */
341 __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_ADDR, addr);
342 __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_DATA, reg_addr);
343 __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_OP,
344 MI1_OP_INDIRECT_ADDRESS);
345 mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);
346
347 /* Write the operation we want. */
f1d3d38a
SH		 348 __t1_tpi_write(adapter,
349 A_ELMER0_PORT0_MI1_OP, MI1_OP_INDIRECT_READ);
8199d3a7
CL		 350 mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);
351
352 /* Read the data. */
353 __t1_tpi_read(adapter, A_ELMER0_PORT0_MI1_DATA, valp);
f1d3d38a 354 spin_unlock(&adapter->tpi_lock);
8199d3a7
CL		 355 return 0;
356}
357
358static int mi1_mdio_ext_write(adapter_t *adapter, int phy_addr, int mmd_addr,
359 int reg_addr, unsigned int val)
360{
361 u32 addr = V_MI1_REG_ADDR(mmd_addr) | V_MI1_PHY_ADDR(phy_addr);
362
f1d3d38a 363 spin_lock(&adapter->tpi_lock);
8199d3a7
CL		 364
365 /* Write the address we want. */
366 __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_ADDR, addr);
367 __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_DATA, reg_addr);
368 __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_OP,
369 MI1_OP_INDIRECT_ADDRESS);
370 mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);
371
372 /* Write the data. */
373 __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_DATA, val);
374 __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_OP, MI1_OP_INDIRECT_WRITE);
375 mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);
f1d3d38a 376 spin_unlock(&adapter->tpi_lock);
8199d3a7
CL		 377 return 0;
378}
379
459e536b 380static const struct mdio_ops mi1_mdio_ext_ops = {
4c247db1
SH		 381 .init = mi1_mdio_init,
382 .read = mi1_mdio_ext_read,
383 .write = mi1_mdio_ext_write
8199d3a7
CL		 384};
385
386enum {
f1d3d38a 387 CH_BRD_T110_1CU,
8199d3a7
CL		 388 CH_BRD_N110_1F,
389 CH_BRD_N210_1F,
f1d3d38a
SH		 390 CH_BRD_T210_1F,
391 CH_BRD_T210_1CU,
392 CH_BRD_N204_4CU,
8199d3a7
CL		 393};
394
4c247db1
SH		 395static const struct board_info t1_board[] = {
396 {
397 .board = CHBT_BOARD_CHT110,
398 .port_number = 1,
399 .caps = SUPPORTED_10000baseT_Full,
400 .chip_term = CHBT_TERM_T1,
401 .chip_mac = CHBT_MAC_PM3393,
402 .chip_phy = CHBT_PHY_MY3126,
403 .clock_core = 125000000,
404 .clock_mc3 = 150000000,
405 .clock_mc4 = 125000000,
406 .espi_nports = 1,
407 .clock_elmer0 = 44,
408 .mdio_mdien = 1,
409 .mdio_mdiinv = 1,
410 .mdio_mdc = 1,
411 .mdio_phybaseaddr = 1,
412 .gmac = &t1_pm3393_ops,
413 .gphy = &t1_my3126_ops,
414 .mdio_ops = &mi1_mdio_ext_ops,
415 .desc = "Chelsio T110 1x10GBase-CX4 TOE",
416 },
417
418 {
419 .board = CHBT_BOARD_N110,
420 .port_number = 1,
421 .caps = SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE,
422 .chip_term = CHBT_TERM_T1,
423 .chip_mac = CHBT_MAC_PM3393,
424 .chip_phy = CHBT_PHY_88X2010,
425 .clock_core = 125000000,
426 .espi_nports = 1,
427 .clock_elmer0 = 44,
428 .mdio_mdien = 0,
429 .mdio_mdiinv = 0,
430 .mdio_mdc = 1,
431 .mdio_phybaseaddr = 0,
432 .gmac = &t1_pm3393_ops,
433 .gphy = &t1_mv88x201x_ops,
434 .mdio_ops = &mi1_mdio_ext_ops,
435 .desc = "Chelsio N110 1x10GBaseX NIC",
436 },
437
438 {
439 .board = CHBT_BOARD_N210,
440 .port_number = 1,
441 .caps = SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE,
442 .chip_term = CHBT_TERM_T2,
443 .chip_mac = CHBT_MAC_PM3393,
444 .chip_phy = CHBT_PHY_88X2010,
445 .clock_core = 125000000,
446 .espi_nports = 1,
447 .clock_elmer0 = 44,
448 .mdio_mdien = 0,
449 .mdio_mdiinv = 0,
450 .mdio_mdc = 1,
451 .mdio_phybaseaddr = 0,
452 .gmac = &t1_pm3393_ops,
453 .gphy = &t1_mv88x201x_ops,
454 .mdio_ops = &mi1_mdio_ext_ops,
455 .desc = "Chelsio N210 1x10GBaseX NIC",
456 },
457
458 {
459 .board = CHBT_BOARD_CHT210,
460 .port_number = 1,
461 .caps = SUPPORTED_10000baseT_Full,
462 .chip_term = CHBT_TERM_T2,
463 .chip_mac = CHBT_MAC_PM3393,
464 .chip_phy = CHBT_PHY_88X2010,
465 .clock_core = 125000000,
466 .clock_mc3 = 133000000,
467 .clock_mc4 = 125000000,
468 .espi_nports = 1,
469 .clock_elmer0 = 44,
470 .mdio_mdien = 0,
471 .mdio_mdiinv = 0,
472 .mdio_mdc = 1,
473 .mdio_phybaseaddr = 0,
474 .gmac = &t1_pm3393_ops,
475 .gphy = &t1_mv88x201x_ops,
476 .mdio_ops = &mi1_mdio_ext_ops,
477 .desc = "Chelsio T210 1x10GBaseX TOE",
478 },
479
480 {
481 .board = CHBT_BOARD_CHT210,
482 .port_number = 1,
483 .caps = SUPPORTED_10000baseT_Full,
484 .chip_term = CHBT_TERM_T2,
485 .chip_mac = CHBT_MAC_PM3393,
486 .chip_phy = CHBT_PHY_MY3126,
487 .clock_core = 125000000,
488 .clock_mc3 = 133000000,
489 .clock_mc4 = 125000000,
490 .espi_nports = 1,
491 .clock_elmer0 = 44,
492 .mdio_mdien = 1,
493 .mdio_mdiinv = 1,
494 .mdio_mdc = 1,
495 .mdio_phybaseaddr = 1,
496 .gmac = &t1_pm3393_ops,
497 .gphy = &t1_my3126_ops,
498 .mdio_ops = &mi1_mdio_ext_ops,
499 .desc = "Chelsio T210 1x10GBase-CX4 TOE",
500 },
f1d3d38a 501
352c417d 502#ifdef CONFIG_CHELSIO_T1_1G
4c247db1
SH		 503 {
504 .board = CHBT_BOARD_CHN204,
505 .port_number = 4,
506 .caps = SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full
507 | SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full
508 | SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg |
509 SUPPORTED_PAUSE | SUPPORTED_TP,
510 .chip_term = CHBT_TERM_T2,
511 .chip_mac = CHBT_MAC_VSC7321,
512 .chip_phy = CHBT_PHY_88E1111,
513 .clock_core = 100000000,
514 .espi_nports = 4,
515 .clock_elmer0 = 44,
516 .mdio_mdien = 0,
517 .mdio_mdiinv = 0,
518 .mdio_mdc = 0,
519 .mdio_phybaseaddr = 4,
520 .gmac = &t1_vsc7326_ops,
521 .gphy = &t1_mv88e1xxx_ops,
522 .mdio_ops = &mi1_mdio_ops,
523 .desc = "Chelsio N204 4x100/1000BaseT NIC",
524 },
352c417d 525#endif
f1d3d38a 526
8199d3a7
CL		 527};
528
529struct pci_device_id t1_pci_tbl[] = {
f1d3d38a
SH		 530 CH_DEVICE(8, 0, CH_BRD_T110_1CU),
531 CH_DEVICE(8, 1, CH_BRD_T110_1CU),
8199d3a7
CL		 532 CH_DEVICE(7, 0, CH_BRD_N110_1F),
533 CH_DEVICE(10, 1, CH_BRD_N210_1F),
f1d3d38a
SH		 534 CH_DEVICE(11, 1, CH_BRD_T210_1F),
535 CH_DEVICE(14, 1, CH_BRD_T210_1CU),
536 CH_DEVICE(16, 1, CH_BRD_N204_4CU),
537 { 0 }
8199d3a7
CL		 538};
539
559fb51b
SB		 540MODULE_DEVICE_TABLE(pci, t1_pci_tbl);
541
8199d3a7
CL		 542/*
543 * Return the board_info structure with a given index. Out-of-range indices
544 * return NULL.
545 */
546const struct board_info *t1_get_board_info(unsigned int board_id)
547{
559fb51b 548 return board_id < ARRAY_SIZE(t1_board) ? &t1_board[board_id] : NULL;
8199d3a7
CL		 549}
550
551struct chelsio_vpd_t {
552 u32 format_version;
553 u8 serial_number[16];
554 u8 mac_base_address[6];
555 u8 pad[2]; /* make multiple-of-4 size requirement explicit */
556};
557
558#define EEPROMSIZE (8 * 1024)
559#define EEPROM_MAX_POLL 4
560
561/*
562 * Read SEEPROM. A zero is written to the flag register when the addres is
563 * written to the Control register. The hardware device will set the flag to a
564 * one when 4B have been transferred to the Data register.
565 */
ac390c60 566int t1_seeprom_read(adapter_t *adapter, u32 addr, __le32 *data)
8199d3a7
CL		 567{
568 int i = EEPROM_MAX_POLL;
569 u16 val;
ac390c60 570 u32 v;
8199d3a7
CL		 571
572 if (addr >= EEPROMSIZE || (addr & 3))
573 return -EINVAL;
574
575 pci_write_config_word(adapter->pdev, A_PCICFG_VPD_ADDR, (u16)addr);
576 do {
577 udelay(50);
578 pci_read_config_word(adapter->pdev, A_PCICFG_VPD_ADDR, &val);
579 } while (!(val & F_VPD_OP_FLAG) && --i);
580
581 if (!(val & F_VPD_OP_FLAG)) {
582 CH_ERR("%s: reading EEPROM address 0x%x failed\n",
583 adapter->name, addr);
584 return -EIO;
585 }
ac390c60
AV		 586 pci_read_config_dword(adapter->pdev, A_PCICFG_VPD_DATA, &v);
587 *data = cpu_to_le32(v);
8199d3a7
CL		 588 return 0;
589}
590
591static int t1_eeprom_vpd_get(adapter_t *adapter, struct chelsio_vpd_t *vpd)
592{
593 int addr, ret = 0;
594
595 for (addr = 0; !ret && addr < sizeof(*vpd); addr += sizeof(u32))
596 ret = t1_seeprom_read(adapter, addr,
ac390c60 597 (__le32 *)((u8 *)vpd + addr));
8199d3a7
CL		 598
599 return ret;
600}
601
602/*
603 * Read a port's MAC address from the VPD ROM.
604 */
605static int vpd_macaddress_get(adapter_t *adapter, int index, u8 mac_addr[])
606{
607 struct chelsio_vpd_t vpd;
608
609 if (t1_eeprom_vpd_get(adapter, &vpd))
610 return 1;
611 memcpy(mac_addr, vpd.mac_base_address, 5);
612 mac_addr[5] = vpd.mac_base_address[5] + index;
613 return 0;
614}
615
616/*
617 * Set up the MAC/PHY according to the requested link settings.
618 *
619 * If the PHY can auto-negotiate first decide what to advertise, then
620 * enable/disable auto-negotiation as desired and reset.
621 *
622 * If the PHY does not auto-negotiate we just reset it.
623 *
624 * If auto-negotiation is off set the MAC to the proper speed/duplex/FC,
625 * otherwise do it later based on the outcome of auto-negotiation.
626 */
627int t1_link_start(struct cphy *phy, struct cmac *mac, struct link_config *lc)
628{
629 unsigned int fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
630
631 if (lc->supported & SUPPORTED_Autoneg) {
632 lc->advertising &= ~(ADVERTISED_ASYM_PAUSE | ADVERTISED_PAUSE);
633 if (fc) {
f1d3d38a
SH		 634 if (fc == ((PAUSE_RX | PAUSE_TX) &
635 (mac->adapter->params.nports < 2)))
8199d3a7 636 lc->advertising |= ADVERTISED_PAUSE;
f1d3d38a
SH		 637 else {
638 lc->advertising |= ADVERTISED_ASYM_PAUSE;
639 if (fc == PAUSE_RX)
640 lc->advertising |= ADVERTISED_PAUSE;
641 }
8199d3a7
CL		 642 }
643 phy->ops->advertise(phy, lc->advertising);
644
645 if (lc->autoneg == AUTONEG_DISABLE) {
646 lc->speed = lc->requested_speed;
647 lc->duplex = lc->requested_duplex;
648 lc->fc = (unsigned char)fc;
649 mac->ops->set_speed_duplex_fc(mac, lc->speed,
650 lc->duplex, fc);
651 /* Also disables autoneg */
f1d3d38a 652 phy->state = PHY_AUTONEG_RDY;
8199d3a7
CL		 653 phy->ops->set_speed_duplex(phy, lc->speed, lc->duplex);
654 phy->ops->reset(phy, 0);
f1d3d38a
SH		 655 } else {
656 phy->state = PHY_AUTONEG_EN;
8199d3a7 657 phy->ops->autoneg_enable(phy); /* also resets PHY */
f1d3d38a 658 }
8199d3a7 659 } else {
f1d3d38a 660 phy->state = PHY_AUTONEG_RDY;
8199d3a7
CL		 661 mac->ops->set_speed_duplex_fc(mac, -1, -1, fc);
662 lc->fc = (unsigned char)fc;
663 phy->ops->reset(phy, 0);
664 }
665 return 0;
666}
667
668/*
669 * External interrupt handler for boards using elmer0.
670 */
f1d3d38a 671int t1_elmer0_ext_intr_handler(adapter_t *adapter)
8199d3a7 672{
11e5a202 673 struct cphy *phy;
8199d3a7 674 int phy_cause;
11e5a202 675 u32 cause;
8199d3a7
CL		 676
677 t1_tpi_read(adapter, A_ELMER0_INT_CAUSE, &cause);
678
679 switch (board_info(adapter)->board) {
352c417d 680#ifdef CONFIG_CHELSIO_T1_1G
356bd146
FR		 681 case CHBT_BOARD_CHT204:
682 case CHBT_BOARD_CHT204E:
683 case CHBT_BOARD_CHN204:
684 case CHBT_BOARD_CHT204V: {
685 int i, port_bit;
352c417d
SH		 686 for_each_port(adapter, i) {
687 port_bit = i + 1;
c697f83e
FR		 688 if (!(cause & (1 << port_bit)))
689 continue;
352c417d 690
356bd146 691 phy = adapter->port[i].phy;
352c417d
SH		 692 phy_cause = phy->ops->interrupt_handler(phy);
693 if (phy_cause & cphy_cause_link_change)
694 t1_link_changed(adapter, i);
695 }
356bd146
FR		 696 break;
697 }
352c417d
SH		 698 case CHBT_BOARD_CHT101:
699 if (cause & ELMER0_GP_BIT1) { /* Marvell 88E1111 interrupt */
700 phy = adapter->port[0].phy;
701 phy_cause = phy->ops->interrupt_handler(phy);
702 if (phy_cause & cphy_cause_link_change)
703 t1_link_changed(adapter, 0);
704 }
705 break;
706 case CHBT_BOARD_7500: {
707 int p;
356bd146 708 /*
352c417d
SH		 709 * Elmer0's interrupt cause isn't useful here because there is
710 * only one bit that can be set for all 4 ports. This means
711 * we are forced to check every PHY's interrupt status
712 * register to see who initiated the interrupt.
356bd146
FR		 713 */
714 for_each_port(adapter, p) {
352c417d
SH		 715 phy = adapter->port[p].phy;
716 phy_cause = phy->ops->interrupt_handler(phy);
717 if (phy_cause & cphy_cause_link_change)
718 t1_link_changed(adapter, p);
719 }
720 break;
721 }
722#endif
f1d3d38a 723 case CHBT_BOARD_CHT210:
8199d3a7
CL		 724 case CHBT_BOARD_N210:
725 case CHBT_BOARD_N110:
726 if (cause & ELMER0_GP_BIT6) { /* Marvell 88x2010 interrupt */
727 phy = adapter->port[0].phy;
728 phy_cause = phy->ops->interrupt_handler(phy);
729 if (phy_cause & cphy_cause_link_change)
f1d3d38a
SH		 730 t1_link_changed(adapter, 0);
731 }
732 break;
733 case CHBT_BOARD_8000:
734 case CHBT_BOARD_CHT110:
356bd146 735 CH_DBG(adapter, INTR, "External interrupt cause 0x%x\n",
f1d3d38a
SH		 736 cause);
737 if (cause & ELMER0_GP_BIT1) { /* PMC3393 INTB */
738 struct cmac *mac = adapter->port[0].mac;
739
740 mac->ops->interrupt_handler(mac);
8199d3a7 741 }
f1d3d38a
SH		 742 if (cause & ELMER0_GP_BIT5) { /* XPAK MOD_DETECT */
743 u32 mod_detect;
744
745 t1_tpi_read(adapter,
746 A_ELMER0_GPI_STAT, &mod_detect);
356bd146 747 CH_MSG(adapter, INFO, LINK, "XPAK %s\n",
f1d3d38a 748 mod_detect ? "removed" : "inserted");
356bd146 749 }
8199d3a7 750 break;
352c417d
SH		 751#ifdef CONFIG_CHELSIO_T1_COUGAR
752 case CHBT_BOARD_COUGAR:
753 if (adapter->params.nports == 1) {
754 if (cause & ELMER0_GP_BIT1) { /* Vitesse MAC */
755 struct cmac *mac = adapter->port[0].mac;
756 mac->ops->interrupt_handler(mac);
757 }
758 if (cause & ELMER0_GP_BIT5) { /* XPAK MOD_DETECT */
759 }
760 } else {
761 int i, port_bit;
762
763 for_each_port(adapter, i) {
764 port_bit = i ? i + 1 : 0;
c697f83e
FR		 765 if (!(cause & (1 << port_bit)))
766 continue;
352c417d
SH		 767
768 phy = adapter->port[i].phy;
769 phy_cause = phy->ops->interrupt_handler(phy);
770 if (phy_cause & cphy_cause_link_change)
771 t1_link_changed(adapter, i);
772 }
773 }
774 break;
775#endif
8199d3a7
CL		 776 }
777 t1_tpi_write(adapter, A_ELMER0_INT_CAUSE, cause);
778 return 0;
779}
780
781/* Enables all interrupts. */
782void t1_interrupts_enable(adapter_t *adapter)
783{
784 unsigned int i;
785
f1d3d38a 786 adapter->slow_intr_mask = F_PL_INTR_SGE_ERR | F_PL_INTR_TP;
8199d3a7
CL		 787
788 t1_sge_intr_enable(adapter->sge);
f1d3d38a 789 t1_tp_intr_enable(adapter->tp);
8199d3a7
CL		 790 if (adapter->espi) {
791 adapter->slow_intr_mask |= F_PL_INTR_ESPI;
792 t1_espi_intr_enable(adapter->espi);
793 }
794
795 /* Enable MAC/PHY interrupts for each port. */
796 for_each_port(adapter, i) {
797 adapter->port[i].mac->ops->interrupt_enable(adapter->port[i].mac);
798 adapter->port[i].phy->ops->interrupt_enable(adapter->port[i].phy);
799 }
800
801 /* Enable PCIX & external chip interrupts on ASIC boards. */
f1d3d38a
SH		 802 if (t1_is_asic(adapter)) {
803 u32 pl_intr = readl(adapter->regs + A_PL_ENABLE);
8199d3a7 804
f1d3d38a
SH		 805 /* PCI-X interrupts */
806 pci_write_config_dword(adapter->pdev, A_PCICFG_INTR_ENABLE,
807 0xffffffff);
8199d3a7 808
f1d3d38a
SH		 809 adapter->slow_intr_mask |= F_PL_INTR_EXT | F_PL_INTR_PCIX;
810 pl_intr |= F_PL_INTR_EXT | F_PL_INTR_PCIX;
811 writel(pl_intr, adapter->regs + A_PL_ENABLE);
812 }
8199d3a7
CL		 813}
814
815/* Disables all interrupts. */
816void t1_interrupts_disable(adapter_t* adapter)
817{
818 unsigned int i;
819
820 t1_sge_intr_disable(adapter->sge);
f1d3d38a 821 t1_tp_intr_disable(adapter->tp);
8199d3a7
CL		 822 if (adapter->espi)
823 t1_espi_intr_disable(adapter->espi);
824
825 /* Disable MAC/PHY interrupts for each port. */
826 for_each_port(adapter, i) {
827 adapter->port[i].mac->ops->interrupt_disable(adapter->port[i].mac);
828 adapter->port[i].phy->ops->interrupt_disable(adapter->port[i].phy);
829 }
830
831 /* Disable PCIX & external chip interrupts. */
f1d3d38a 832 if (t1_is_asic(adapter))
356bd146 833 writel(0, adapter->regs + A_PL_ENABLE);
8199d3a7
CL		 834
835 /* PCI-X interrupts */
836 pci_write_config_dword(adapter->pdev, A_PCICFG_INTR_ENABLE, 0);
837
838 adapter->slow_intr_mask = 0;
839}
840
841/* Clears all interrupts */
842void t1_interrupts_clear(adapter_t* adapter)
843{
844 unsigned int i;
845
846 t1_sge_intr_clear(adapter->sge);
f1d3d38a 847 t1_tp_intr_clear(adapter->tp);
8199d3a7
CL		 848 if (adapter->espi)
849 t1_espi_intr_clear(adapter->espi);
850
851 /* Clear MAC/PHY interrupts for each port. */
852 for_each_port(adapter, i) {
853 adapter->port[i].mac->ops->interrupt_clear(adapter->port[i].mac);
854 adapter->port[i].phy->ops->interrupt_clear(adapter->port[i].phy);
855 }
856
857 /* Enable interrupts for external devices. */
f1d3d38a
SH		 858 if (t1_is_asic(adapter)) {
859 u32 pl_intr = readl(adapter->regs + A_PL_CAUSE);
8199d3a7 860
f1d3d38a
SH		 861 writel(pl_intr | F_PL_INTR_EXT | F_PL_INTR_PCIX,
862 adapter->regs + A_PL_CAUSE);
863 }
8199d3a7
CL		 864
865 /* PCI-X interrupts */
866 pci_write_config_dword(adapter->pdev, A_PCICFG_INTR_CAUSE, 0xffffffff);
867}
868
869/*
870 * Slow path interrupt handler for ASICs.
871 */
f1d3d38a 872static int asic_slow_intr(adapter_t *adapter)
8199d3a7 873{
559fb51b 874 u32 cause = readl(adapter->regs + A_PL_CAUSE);
8199d3a7
CL		 875
876 cause &= adapter->slow_intr_mask;
877 if (!cause)
878 return 0;
879 if (cause & F_PL_INTR_SGE_ERR)
880 t1_sge_intr_error_handler(adapter->sge);
f1d3d38a
SH		 881 if (cause & F_PL_INTR_TP)
882 t1_tp_intr_handler(adapter->tp);
8199d3a7
CL		 883 if (cause & F_PL_INTR_ESPI)
884 t1_espi_intr_handler(adapter->espi);
885 if (cause & F_PL_INTR_PCIX)
886 t1_pci_intr_handler(adapter);
887 if (cause & F_PL_INTR_EXT)
33a85aa1 888 t1_elmer0_ext_intr(adapter);
8199d3a7
CL		 889
890 /* Clear the interrupts just processed. */
559fb51b 891 writel(cause, adapter->regs + A_PL_CAUSE);
f1d3d38a 892 readl(adapter->regs + A_PL_CAUSE); /* flush writes */
8199d3a7
CL		 893 return 1;
894}
895
f1d3d38a 896int t1_slow_intr_handler(adapter_t *adapter)
8199d3a7 897{
352c417d
SH		 898#ifdef CONFIG_CHELSIO_T1_1G
899 if (!t1_is_asic(adapter))
900 return fpga_slow_intr(adapter);
901#endif
f1d3d38a 902 return asic_slow_intr(adapter);
559fb51b 903}
8199d3a7 904
f1d3d38a
SH		 905/* Power sequencing is a work-around for Intel's XPAKs. */
906static void power_sequence_xpak(adapter_t* adapter)
559fb51b 907{
356bd146
FR		 908 u32 mod_detect;
909 u32 gpo;
559fb51b 910
356bd146
FR		 911 /* Check for XPAK */
912 t1_tpi_read(adapter, A_ELMER0_GPI_STAT, &mod_detect);
f1d3d38a
SH		 913 if (!(ELMER0_GP_BIT5 & mod_detect)) {
914 /* XPAK is present */
915 t1_tpi_read(adapter, A_ELMER0_GPO, &gpo);
916 gpo |= ELMER0_GP_BIT18;
917 t1_tpi_write(adapter, A_ELMER0_GPO, gpo);
8199d3a7
CL		 918 }
919}
920
921int __devinit t1_get_board_rev(adapter_t *adapter, const struct board_info *bi,
922 struct adapter_params *p)
923{
924 p->chip_version = bi->chip_term;
f1d3d38a 925 p->is_asic = (p->chip_version != CHBT_TERM_FPGA);
8199d3a7 926 if (p->chip_version == CHBT_TERM_T1 ||
f1d3d38a
SH		 927 p->chip_version == CHBT_TERM_T2 ||
928 p->chip_version == CHBT_TERM_FPGA) {
559fb51b 929 u32 val = readl(adapter->regs + A_TP_PC_CONFIG);
8199d3a7
CL		 930
931 val = G_TP_PC_REV(val);
932 if (val == 2)
933 p->chip_revision = TERM_T1B;
934 else if (val == 3)
935 p->chip_revision = TERM_T2;
936 else
937 return -1;
938 } else
939 return -1;
940 return 0;
941}
942
943/*
944 * Enable board components other than the Chelsio chip, such as external MAC
945 * and PHY.
946 */
947static int board_init(adapter_t *adapter, const struct board_info *bi)
948{
949 switch (bi->board) {
f1d3d38a 950 case CHBT_BOARD_8000:
8199d3a7
CL		 951 case CHBT_BOARD_N110:
952 case CHBT_BOARD_N210:
f1d3d38a
SH		 953 case CHBT_BOARD_CHT210:
954 case CHBT_BOARD_COUGAR:
356bd146
FR		 955 t1_tpi_par(adapter, 0xf);
956 t1_tpi_write(adapter, A_ELMER0_GPO, 0x800);
f1d3d38a
SH		 957 break;
958 case CHBT_BOARD_CHT110:
356bd146
FR		 959 t1_tpi_par(adapter, 0xf);
960 t1_tpi_write(adapter, A_ELMER0_GPO, 0x1800);
f1d3d38a 961
356bd146
FR		 962 /* TBD XXX Might not need. This fixes a problem
963 * described in the Intel SR XPAK errata.
964 */
965 power_sequence_xpak(adapter);
8199d3a7 966 break;
352c417d 967#ifdef CONFIG_CHELSIO_T1_1G
356bd146
FR		 968 case CHBT_BOARD_CHT204E:
969 /* add config space write here */
352c417d
SH		 970 case CHBT_BOARD_CHT204:
971 case CHBT_BOARD_CHT204V:
972 case CHBT_BOARD_CHN204:
356bd146
FR		 973 t1_tpi_par(adapter, 0xf);
974 t1_tpi_write(adapter, A_ELMER0_GPO, 0x804);
975 break;
352c417d
SH		 976 case CHBT_BOARD_CHT101:
977 case CHBT_BOARD_7500:
356bd146
FR		 978 t1_tpi_par(adapter, 0xf);
979 t1_tpi_write(adapter, A_ELMER0_GPO, 0x1804);
352c417d
SH		 980 break;
981#endif
8199d3a7
CL		 982 }
983 return 0;
984}
985
986/*
987 * Initialize and configure the Terminator HW modules. Note that external
988 * MAC and PHYs are initialized separately.
989 */
990int t1_init_hw_modules(adapter_t *adapter)
991{
992 int err = -EIO;
993 const struct board_info *bi = board_info(adapter);
994
559fb51b
SB		 995 if (!bi->clock_mc4) {
996 u32 val = readl(adapter->regs + A_MC4_CFG);
8199d3a7 997
559fb51b
SB		 998 writel(val | F_READY | F_MC4_SLOW, adapter->regs + A_MC4_CFG);
999 writel(F_M_BUS_ENABLE | F_TCAM_RESET,
1000 adapter->regs + A_MC5_CONFIG);
8199d3a7
CL		 1001 }
1002
352c417d
SH		 1003#ifdef CONFIG_CHELSIO_T1_COUGAR
1004 if (adapter->cspi && t1_cspi_init(adapter->cspi))
1005 goto out_err;
1006#endif
8199d3a7
CL		 1007 if (adapter->espi && t1_espi_init(adapter->espi, bi->chip_mac,
1008 bi->espi_nports))
1009 goto out_err;
1010
f1d3d38a
SH		 1011 if (t1_tp_reset(adapter->tp, &adapter->params.tp, bi->clock_core))
1012 goto out_err;
8199d3a7
CL		 1013
1014 err = t1_sge_configure(adapter->sge, &adapter->params.sge);
1015 if (err)
1016 goto out_err;
1017
1018 err = 0;
356bd146 1019out_err:
8199d3a7
CL		 1020 return err;
1021}
1022
1023/*
1024 * Determine a card's PCI mode.
1025 */
559fb51b 1026static void __devinit get_pci_mode(adapter_t *adapter, struct chelsio_pci_params *p)
8199d3a7 1027{
f71e1309 1028 static const unsigned short speed_map[] = { 33, 66, 100, 133 };
8199d3a7
CL		 1029 u32 pci_mode;
1030
1031 pci_read_config_dword(adapter->pdev, A_PCICFG_MODE, &pci_mode);
1032 p->speed = speed_map[G_PCI_MODE_CLK(pci_mode)];
1033 p->width = (pci_mode & F_PCI_MODE_64BIT) ? 64 : 32;
1034 p->is_pcix = (pci_mode & F_PCI_MODE_PCIX) != 0;
1035}
1036
1037/*
1038 * Release the structures holding the SW per-Terminator-HW-module state.
1039 */
1040void t1_free_sw_modules(adapter_t *adapter)
1041{
1042 unsigned int i;
1043
1044 for_each_port(adapter, i) {
1045 struct cmac *mac = adapter->port[i].mac;
1046 struct cphy *phy = adapter->port[i].phy;
1047
1048 if (mac)
1049 mac->ops->destroy(mac);
1050 if (phy)
1051 phy->ops->destroy(phy);
1052 }
1053
1054 if (adapter->sge)
1055 t1_sge_destroy(adapter->sge);
f1d3d38a
SH		 1056 if (adapter->tp)
1057 t1_tp_destroy(adapter->tp);
8199d3a7
CL		 1058 if (adapter->espi)
1059 t1_espi_destroy(adapter->espi);
352c417d 1060#ifdef CONFIG_CHELSIO_T1_COUGAR
356bd146 1061 if (adapter->cspi)
352c417d
SH		 1062 t1_cspi_destroy(adapter->cspi);
1063#endif
8199d3a7
CL		 1064}
1065
1066static void __devinit init_link_config(struct link_config *lc,
1067 const struct board_info *bi)
1068{
1069 lc->supported = bi->caps;
1070 lc->requested_speed = lc->speed = SPEED_INVALID;
1071 lc->requested_duplex = lc->duplex = DUPLEX_INVALID;
1072 lc->requested_fc = lc->fc = PAUSE_RX | PAUSE_TX;
1073 if (lc->supported & SUPPORTED_Autoneg) {
1074 lc->advertising = lc->supported;
1075 lc->autoneg = AUTONEG_ENABLE;
1076 lc->requested_fc |= PAUSE_AUTONEG;
1077 } else {
1078 lc->advertising = 0;
1079 lc->autoneg = AUTONEG_DISABLE;
1080 }
1081}
1082
352c417d
SH		 1083#ifdef CONFIG_CHELSIO_T1_COUGAR
1084 if (bi->clock_cspi && !(adapter->cspi = t1_cspi_create(adapter))) {
1085 CH_ERR("%s: CSPI initialization failed\n",
1086 adapter->name);
1087 goto error;
356bd146 1088 }
352c417d 1089#endif
8199d3a7
CL		 1090
1091/*
1092 * Allocate and initialize the data structures that hold the SW state of
1093 * the Terminator HW modules.
1094 */
1095int __devinit t1_init_sw_modules(adapter_t *adapter,
1096 const struct board_info *bi)
1097{
1098 unsigned int i;
1099
1100 adapter->params.brd_info = bi;
1101 adapter->params.nports = bi->port_number;
1102 adapter->params.stats_update_period = bi->gmac->stats_update_period;
1103
1104 adapter->sge = t1_sge_create(adapter, &adapter->params.sge);
1105 if (!adapter->sge) {
1106 CH_ERR("%s: SGE initialization failed\n",
1107 adapter->name);
1108 goto error;
1109 }
1110
8199d3a7
CL		 1111 if (bi->espi_nports && !(adapter->espi = t1_espi_create(adapter))) {
1112 CH_ERR("%s: ESPI initialization failed\n",
1113 adapter->name);
1114 goto error;
1115 }
1116
f1d3d38a
SH		 1117 adapter->tp = t1_tp_create(adapter, &adapter->params.tp);
1118 if (!adapter->tp) {
1119 CH_ERR("%s: TP initialization failed\n",
1120 adapter->name);
1121 goto error;
1122 }
1123
8199d3a7
CL		 1124 board_init(adapter, bi);
1125 bi->mdio_ops->init(adapter, bi);
1126 if (bi->gphy->reset)
1127 bi->gphy->reset(adapter);
1128 if (bi->gmac->reset)
1129 bi->gmac->reset(adapter);
1130
1131 for_each_port(adapter, i) {
1132 u8 hw_addr[6];
1133 struct cmac *mac;
1134 int phy_addr = bi->mdio_phybaseaddr + i;
1135
1136 adapter->port[i].phy = bi->gphy->create(adapter, phy_addr,
1137 bi->mdio_ops);
1138 if (!adapter->port[i].phy) {
1139 CH_ERR("%s: PHY %d initialization failed\n",
1140 adapter->name, i);
1141 goto error;
1142 }
1143
1144 adapter->port[i].mac = mac = bi->gmac->create(adapter, i);
1145 if (!mac) {
1146 CH_ERR("%s: MAC %d initialization failed\n",
1147 adapter->name, i);
1148 goto error;
1149 }
1150
1151 /*
1152 * Get the port's MAC addresses either from the EEPROM if one
1153 * exists or the one hardcoded in the MAC.
1154 */
f1d3d38a
SH		 1155 if (!t1_is_asic(adapter) || bi->chip_mac == CHBT_MAC_DUMMY)
1156 mac->ops->macaddress_get(mac, hw_addr);
1157 else if (vpd_macaddress_get(adapter, i, hw_addr)) {
8199d3a7 1158 CH_ERR("%s: could not read MAC address from VPD ROM\n",
559fb51b 1159 adapter->port[i].dev->name);
8199d3a7
CL		 1160 goto error;
1161 }
559fb51b 1162 memcpy(adapter->port[i].dev->dev_addr, hw_addr, ETH_ALEN);
8199d3a7
CL		 1163 init_link_config(&adapter->port[i].link_config, bi);
1164 }
1165
1166 get_pci_mode(adapter, &adapter->params.pci);
1167 t1_interrupts_clear(adapter);
1168 return 0;
1169
f1d3d38a 1170error:
8199d3a7
CL		 1171 t1_free_sw_modules(adapter);
1172 return -1;
1173}
Linux kernel - Deliverables
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