[deliverable/linux.git] / drivers / net / cxgb3 / adapter.h

/*
 * Copyright (c) 2003-2007 Chelsio, Inc. All rights reserved.
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * OpenIB.org BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *      - Redistributions of source code must retain the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer.
 *
 *      - Redistributions in binary form must reproduce the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer in the documentation and/or other materials
 *        provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 */

/* This file should not be included directly.  Include common.h instead. */

#ifndef __T3_ADAPTER_H__
#define __T3_ADAPTER_H__

#include <linux/pci.h>
#include <linux/spinlock.h>
#include <linux/interrupt.h>
#include <linux/timer.h>
#include <linux/cache.h>
#include <linux/mutex.h>
#include <linux/bitops.h>
#include <linux/inet_lro.h>
#include "t3cdev.h"
#include <asm/io.h>

struct vlan_group;
struct adapter;
struct sge_qset;

struct port_info {
	struct adapter *adapter;
	struct vlan_group *vlan_grp;
	struct sge_qset *qs;
	const struct port_type_info *port_type;
	u8 port_id;
	u8 rx_csum_offload;
	u8 nqsets;
	u8 first_qset;
	struct cphy phy;
	struct cmac mac;
	struct link_config link_config;
	struct net_device_stats netstats;
	int activity;
};

enum {				/* adapter flags */
	FULL_INIT_DONE = (1 << 0),
	USING_MSI = (1 << 1),
	USING_MSIX = (1 << 2),
	QUEUES_BOUND = (1 << 3),
	TP_PARITY_INIT = (1 << 4),
	NAPI_INIT = (1 << 5),
};

struct fl_pg_chunk {
	struct page *page;
	void *va;
	unsigned int offset;
};

struct rx_desc;
struct rx_sw_desc;

struct sge_fl {                     /* SGE per free-buffer list state */
	unsigned int buf_size;      /* size of each Rx buffer */
	unsigned int credits;       /* # of available Rx buffers */
	unsigned int size;          /* capacity of free list */
	unsigned int cidx;          /* consumer index */
	unsigned int pidx;          /* producer index */
	unsigned int gen;           /* free list generation */
	struct fl_pg_chunk pg_chunk;/* page chunk cache */
	unsigned int use_pages;     /* whether FL uses pages or sk_buffs */
	unsigned int order;	    /* order of page allocations */
	struct rx_desc *desc;       /* address of HW Rx descriptor ring */
	struct rx_sw_desc *sdesc;   /* address of SW Rx descriptor ring */
	dma_addr_t   phys_addr;     /* physical address of HW ring start */
	unsigned int cntxt_id;      /* SGE context id for the free list */
	unsigned long empty;        /* # of times queue ran out of buffers */
	unsigned long alloc_failed; /* # of times buffer allocation failed */
};

/*
 * Bundle size for grouping offload RX packets for delivery to the stack.
 * Don't make this too big as we do prefetch on each packet in a bundle.
 */
# define RX_BUNDLE_SIZE 8

struct rsp_desc;

struct sge_rspq {		/* state for an SGE response queue */
	unsigned int credits;	/* # of pending response credits */
	unsigned int size;	/* capacity of response queue */
	unsigned int cidx;	/* consumer index */
	unsigned int gen;	/* current generation bit */
	unsigned int polling;	/* is the queue serviced through NAPI? */
	unsigned int holdoff_tmr;	/* interrupt holdoff timer in 100ns */
	unsigned int next_holdoff;	/* holdoff time for next interrupt */
	unsigned int rx_recycle_buf; /* whether recycling occurred
					within current sop-eop */
	struct rsp_desc *desc;	/* address of HW response ring */
	dma_addr_t phys_addr;	/* physical address of the ring */
	unsigned int cntxt_id;	/* SGE context id for the response q */
	spinlock_t lock;	/* guards response processing */
	struct sk_buff_head rx_queue; /* offload packet receive queue */
	struct sk_buff *pg_skb; /* used to build frag list in napi handler */

	unsigned long offload_pkts;
	unsigned long offload_bundles;
	unsigned long eth_pkts;	/* # of ethernet packets */
	unsigned long pure_rsps;	/* # of pure (non-data) responses */
	unsigned long imm_data;	/* responses with immediate data */
	unsigned long rx_drops;	/* # of packets dropped due to no mem */
	unsigned long async_notif; /* # of asynchronous notification events */
	unsigned long empty;	/* # of times queue ran out of credits */
	unsigned long nomem;	/* # of responses deferred due to no mem */
	unsigned long unhandled_irqs;	/* # of spurious intrs */
	unsigned long starved;
	unsigned long restarted;
};

struct tx_desc;
struct tx_sw_desc;

struct sge_txq {		/* state for an SGE Tx queue */
	unsigned long flags;	/* HW DMA fetch status */
	unsigned int in_use;	/* # of in-use Tx descriptors */
	unsigned int size;	/* # of descriptors */
	unsigned int processed;	/* total # of descs HW has processed */
	unsigned int cleaned;	/* total # of descs SW has reclaimed */
	unsigned int stop_thres;	/* SW TX queue suspend threshold */
	unsigned int cidx;	/* consumer index */
	unsigned int pidx;	/* producer index */
	unsigned int gen;	/* current value of generation bit */
	unsigned int unacked;	/* Tx descriptors used since last COMPL */
	struct tx_desc *desc;	/* address of HW Tx descriptor ring */
	struct tx_sw_desc *sdesc;	/* address of SW Tx descriptor ring */
	spinlock_t lock;	/* guards enqueueing of new packets */
	unsigned int token;	/* WR token */
	dma_addr_t phys_addr;	/* physical address of the ring */
	struct sk_buff_head sendq;	/* List of backpressured offload packets */
	struct tasklet_struct qresume_tsk;	/* restarts the queue */
	unsigned int cntxt_id;	/* SGE context id for the Tx q */
	unsigned long stops;	/* # of times q has been stopped */
	unsigned long restarts;	/* # of queue restarts */
};

enum {				/* per port SGE statistics */
	SGE_PSTAT_TSO,		/* # of TSO requests */
	SGE_PSTAT_RX_CSUM_GOOD,	/* # of successful RX csum offloads */
	SGE_PSTAT_TX_CSUM,	/* # of TX checksum offloads */
	SGE_PSTAT_VLANEX,	/* # of VLAN tag extractions */
	SGE_PSTAT_VLANINS,	/* # of VLAN tag insertions */
	SGE_PSTAT_LRO_AGGR,	/* # of page chunks added to LRO sessions */
	SGE_PSTAT_LRO_FLUSHED,	/* # of flushed LRO sessions */
	SGE_PSTAT_LRO_NO_DESC,	/* # of overflown LRO sessions */

	SGE_PSTAT_MAX		/* must be last */
};

#define T3_MAX_LRO_SES 8
#define T3_MAX_LRO_MAX_PKTS 64

struct sge_qset {		/* an SGE queue set */
	struct adapter *adap;
	struct napi_struct napi;
	struct sge_rspq rspq;
	struct sge_fl fl[SGE_RXQ_PER_SET];
	struct sge_txq txq[SGE_TXQ_PER_SET];
	struct net_lro_mgr lro_mgr;
	struct net_lro_desc lro_desc[T3_MAX_LRO_SES];
	struct skb_frag_struct *lro_frag_tbl;
	int lro_nfrags;
	int lro_enabled;
	int lro_frag_len;
	void *lro_va;
	struct net_device *netdev;
	unsigned long txq_stopped;	/* which Tx queues are stopped */
	struct timer_list tx_reclaim_timer;	/* reclaims TX buffers */
	unsigned long port_stats[SGE_PSTAT_MAX];
} ____cacheline_aligned;

struct sge {
	struct sge_qset qs[SGE_QSETS];
	spinlock_t reg_lock;	/* guards non-atomic SGE registers (eg context) */
};

struct adapter {
	struct t3cdev tdev;
	struct list_head adapter_list;
	void __iomem *regs;
	struct pci_dev *pdev;
	unsigned long registered_device_map;
	unsigned long open_device_map;
	unsigned long flags;

	const char *name;
	int msg_enable;
	unsigned int mmio_len;

	struct adapter_params params;
	unsigned int slow_intr_mask;
	unsigned long irq_stats[IRQ_NUM_STATS];

	struct {
		unsigned short vec;
		char desc[22];
	} msix_info[SGE_QSETS + 1];

	/* T3 modules */
	struct sge sge;
	struct mc7 pmrx;
	struct mc7 pmtx;
	struct mc7 cm;
	struct mc5 mc5;

	struct net_device *port[MAX_NPORTS];
	unsigned int check_task_cnt;
	struct delayed_work adap_check_task;
	struct work_struct ext_intr_handler_task;
	struct work_struct fatal_error_handler_task;

	struct dentry *debugfs_root;

	struct mutex mdio_lock;
	spinlock_t stats_lock;
	spinlock_t work_lock;
};

static inline u32 t3_read_reg(struct adapter *adapter, u32 reg_addr)
{
	u32 val = readl(adapter->regs + reg_addr);

	CH_DBG(adapter, MMIO, "read register 0x%x value 0x%x\n", reg_addr, val);
	return val;
}

static inline void t3_write_reg(struct adapter *adapter, u32 reg_addr, u32 val)
{
	CH_DBG(adapter, MMIO, "setting register 0x%x to 0x%x\n", reg_addr, val);
	writel(val, adapter->regs + reg_addr);
}

static inline struct port_info *adap2pinfo(struct adapter *adap, int idx)
{
	return netdev_priv(adap->port[idx]);
}

#define OFFLOAD_DEVMAP_BIT 15

#define tdev2adap(d) container_of(d, struct adapter, tdev)

static inline int offload_running(struct adapter *adapter)
{
	return test_bit(OFFLOAD_DEVMAP_BIT, &adapter->open_device_map);
}

int t3_offload_tx(struct t3cdev *tdev, struct sk_buff *skb);

void t3_os_ext_intr_handler(struct adapter *adapter);
void t3_os_link_changed(struct adapter *adapter, int port_id, int link_status,
			int speed, int duplex, int fc);

void t3_sge_start(struct adapter *adap);
void t3_sge_stop(struct adapter *adap);
void t3_stop_sge_timers(struct adapter *adap);
void t3_free_sge_resources(struct adapter *adap);
void t3_sge_err_intr_handler(struct adapter *adapter);
irq_handler_t t3_intr_handler(struct adapter *adap, int polling);
int t3_eth_xmit(struct sk_buff *skb, struct net_device *dev);
int t3_mgmt_tx(struct adapter *adap, struct sk_buff *skb);
void t3_update_qset_coalesce(struct sge_qset *qs, const struct qset_params *p);
int t3_sge_alloc_qset(struct adapter *adapter, unsigned int id, int nports,
		      int irq_vec_idx, const struct qset_params *p,
		      int ntxq, struct net_device *dev);
int t3_get_desc(const struct sge_qset *qs, unsigned int qnum, unsigned int idx,
		unsigned char *data);
irqreturn_t t3_sge_intr_msix(int irq, void *cookie);

#endif				/* __T3_ADAPTER_H__ */
Commit	Line	Data
4d22de3e	1	/*
1d68e93d	2	* Copyright (c) 2003-2007 Chelsio, Inc. All rights reserved.
4d22de3e	3	*
1d68e93d DLR	4	* This software is available to you under a choice of one of two
	5	* licenses. You may choose to be licensed under the terms of the GNU
	6	* General Public License (GPL) Version 2, available from the file
	7	* COPYING in the main directory of this source tree, or the
	8	* OpenIB.org BSD license below:
4d22de3e	9	*
1d68e93d DLR	10	* Redistribution and use in source and binary forms, with or
	11	* without modification, are permitted provided that the following
	12	* conditions are met:
	13	*
	14	* - Redistributions of source code must retain the above
	15	* copyright notice, this list of conditions and the following
	16	* disclaimer.
	17	*
	18	* - Redistributions in binary form must reproduce the above
	19	* copyright notice, this list of conditions and the following
	20	* disclaimer in the documentation and/or other materials
	21	* provided with the distribution.
	22	*
	23	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	24	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	25	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	26	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
	27	* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
	28	* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
	29	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	30	* SOFTWARE.
4d22de3e DLR	31	*/
	32
	33	/* This file should not be included directly. Include common.h instead. */
	34
	35	#ifndef __T3_ADAPTER_H__
	36	#define __T3_ADAPTER_H__
	37
	38	#include <linux/pci.h>
	39	#include <linux/spinlock.h>
	40	#include <linux/interrupt.h>
	41	#include <linux/timer.h>
	42	#include <linux/cache.h>
a13fbee0	43	#include <linux/mutex.h>
1977f032	44	#include <linux/bitops.h>
b47385bd	45	#include <linux/inet_lro.h>
4d22de3e	46	#include "t3cdev.h"
4d22de3e DLR	47	#include <asm/io.h>
4d22de3e DLR	48
4d22de3e	49	struct vlan_group;
5fbf816f	50	struct adapter;
bea3348e SH	51	struct sge_qset;
bea3348e SH	52
4d22de3e	53	struct port_info {
5fbf816f	54	struct adapter *adapter;
4d22de3e	55	struct vlan_group *vlan_grp;
bea3348e	56	struct sge_qset *qs;
4d22de3e DLR	57	const struct port_type_info *port_type;
	58	u8 port_id;
	59	u8 rx_csum_offload;
	60	u8 nqsets;
	61	u8 first_qset;
	62	struct cphy phy;
	63	struct cmac mac;
	64	struct link_config link_config;
	65	struct net_device_stats netstats;
	66	int activity;
	67	};
	68
	69	enum { /* adapter flags */
	70	FULL_INIT_DONE = (1 << 0),
	71	USING_MSI = (1 << 1),
	72	USING_MSIX = (1 << 2),
14ab9892	73	QUEUES_BOUND = (1 << 3),
b881955b	74	TP_PARITY_INIT = (1 << 4),
48c4b6db	75	NAPI_INIT = (1 << 5),
4d22de3e DLR	76	};
4d22de3e DLR	77
cf992af5 DLR	78	struct fl_pg_chunk {
	79	struct page *page;
	80	void *va;
	81	unsigned int offset;
	82	};
	83
4d22de3e DLR	84	struct rx_desc;
	85	struct rx_sw_desc;
	86
cf992af5 DLR	87	struct sge_fl { /* SGE per free-buffer list state */
	88	unsigned int buf_size; /* size of each Rx buffer */
	89	unsigned int credits; /* # of available Rx buffers */
	90	unsigned int size; /* capacity of free list */
	91	unsigned int cidx; /* consumer index */
	92	unsigned int pidx; /* producer index */
	93	unsigned int gen; /* free list generation */
	94	struct fl_pg_chunk pg_chunk;/* page chunk cache */
	95	unsigned int use_pages; /* whether FL uses pages or sk_buffs */
7385ecf3	96	unsigned int order; /* order of page allocations */
cf992af5 DLR	97	struct rx_desc desc; / address of HW Rx descriptor ring */
	98	struct rx_sw_desc sdesc; / address of SW Rx descriptor ring */
	99	dma_addr_t phys_addr; /* physical address of HW ring start */
	100	unsigned int cntxt_id; /* SGE context id for the free list */
	101	unsigned long empty; /* # of times queue ran out of buffers */
e0994eb1	102	unsigned long alloc_failed; /* # of times buffer allocation failed */
4d22de3e DLR	103	};
	104
	105	/*
	106	* Bundle size for grouping offload RX packets for delivery to the stack.
	107	* Don't make this too big as we do prefetch on each packet in a bundle.
	108	*/
	109	# define RX_BUNDLE_SIZE 8
	110
	111	struct rsp_desc;
	112
	113	struct sge_rspq { /* state for an SGE response queue */
	114	unsigned int credits; /* # of pending response credits */
	115	unsigned int size; /* capacity of response queue */
	116	unsigned int cidx; /* consumer index */
	117	unsigned int gen; /* current generation bit */
	118	unsigned int polling; /* is the queue serviced through NAPI? */
	119	unsigned int holdoff_tmr; /* interrupt holdoff timer in 100ns */
	120	unsigned int next_holdoff; /* holdoff time for next interrupt */
7385ecf3 DLR	121	unsigned int rx_recycle_buf; /* whether recycling occurred
7385ecf3 DLR	122	within current sop-eop */
4d22de3e DLR	123	struct rsp_desc desc; / address of HW response ring */
	124	dma_addr_t phys_addr; /* physical address of the ring */
	125	unsigned int cntxt_id; /* SGE context id for the response q */
	126	spinlock_t lock; /* guards response processing */
147e70e6	127	struct sk_buff_head rx_queue; /* offload packet receive queue */
7385ecf3	128	struct sk_buff pg_skb; / used to build frag list in napi handler */
4d22de3e DLR	129
	130	unsigned long offload_pkts;
	131	unsigned long offload_bundles;
	132	unsigned long eth_pkts; /* # of ethernet packets */
	133	unsigned long pure_rsps; /* # of pure (non-data) responses */
	134	unsigned long imm_data; /* responses with immediate data */
	135	unsigned long rx_drops; /* # of packets dropped due to no mem */
	136	unsigned long async_notif; /* # of asynchronous notification events */
	137	unsigned long empty; /* # of times queue ran out of credits */
	138	unsigned long nomem; /* # of responses deferred due to no mem */
	139	unsigned long unhandled_irqs; /* # of spurious intrs */
bae73f44 DLR	140	unsigned long starved;
bae73f44 DLR	141	unsigned long restarted;
4d22de3e DLR	142	};
	143
	144	struct tx_desc;
	145	struct tx_sw_desc;
	146
	147	struct sge_txq { /* state for an SGE Tx queue */
	148	unsigned long flags; /* HW DMA fetch status */
	149	unsigned int in_use; /* # of in-use Tx descriptors */
	150	unsigned int size; /* # of descriptors */
	151	unsigned int processed; /* total # of descs HW has processed */
	152	unsigned int cleaned; /* total # of descs SW has reclaimed */
	153	unsigned int stop_thres; /* SW TX queue suspend threshold */
	154	unsigned int cidx; /* consumer index */
	155	unsigned int pidx; /* producer index */
	156	unsigned int gen; /* current value of generation bit */
	157	unsigned int unacked; /* Tx descriptors used since last COMPL */
	158	struct tx_desc desc; / address of HW Tx descriptor ring */
	159	struct tx_sw_desc sdesc; / address of SW Tx descriptor ring */
	160	spinlock_t lock; /* guards enqueueing of new packets */
	161	unsigned int token; /* WR token */
	162	dma_addr_t phys_addr; /* physical address of the ring */
	163	struct sk_buff_head sendq; /* List of backpressured offload packets */
	164	struct tasklet_struct qresume_tsk; /* restarts the queue */
	165	unsigned int cntxt_id; /* SGE context id for the Tx q */
	166	unsigned long stops; /* # of times q has been stopped */
	167	unsigned long restarts; /* # of queue restarts */
	168	};
	169
	170	enum { /* per port SGE statistics */
	171	SGE_PSTAT_TSO, /* # of TSO requests */
	172	SGE_PSTAT_RX_CSUM_GOOD, /* # of successful RX csum offloads */
	173	SGE_PSTAT_TX_CSUM, /* # of TX checksum offloads */
	174	SGE_PSTAT_VLANEX, /* # of VLAN tag extractions */
	175	SGE_PSTAT_VLANINS, /* # of VLAN tag insertions */
b47385bd DLR	176	SGE_PSTAT_LRO_AGGR, /* # of page chunks added to LRO sessions */
	177	SGE_PSTAT_LRO_FLUSHED, /* # of flushed LRO sessions */
	178	SGE_PSTAT_LRO_NO_DESC, /* # of overflown LRO sessions */
4d22de3e DLR	179
	180	SGE_PSTAT_MAX /* must be last */
	181	};
	182
b47385bd DLR	183	#define T3_MAX_LRO_SES 8
	184	#define T3_MAX_LRO_MAX_PKTS 64
	185
4d22de3e	186	struct sge_qset { /* an SGE queue set */
bea3348e SH	187	struct adapter *adap;
bea3348e SH	188	struct napi_struct napi;
4d22de3e DLR	189	struct sge_rspq rspq;
	190	struct sge_fl fl[SGE_RXQ_PER_SET];
	191	struct sge_txq txq[SGE_TXQ_PER_SET];
b47385bd DLR	192	struct net_lro_mgr lro_mgr;
	193	struct net_lro_desc lro_desc[T3_MAX_LRO_SES];
	194	struct skb_frag_struct *lro_frag_tbl;
	195	int lro_nfrags;
	196	int lro_enabled;
	197	int lro_frag_len;
	198	void *lro_va;
bea3348e	199	struct net_device *netdev;
4d22de3e DLR	200	unsigned long txq_stopped; /* which Tx queues are stopped */
	201	struct timer_list tx_reclaim_timer; /* reclaims TX buffers */
	202	unsigned long port_stats[SGE_PSTAT_MAX];
	203	} ____cacheline_aligned;
	204
	205	struct sge {
	206	struct sge_qset qs[SGE_QSETS];
	207	spinlock_t reg_lock; /* guards non-atomic SGE registers (eg context) */
	208	};
	209
	210	struct adapter {
	211	struct t3cdev tdev;
	212	struct list_head adapter_list;
	213	void __iomem *regs;
	214	struct pci_dev *pdev;
	215	unsigned long registered_device_map;
	216	unsigned long open_device_map;
	217	unsigned long flags;
	218
	219	const char *name;
	220	int msg_enable;
	221	unsigned int mmio_len;
	222
	223	struct adapter_params params;
	224	unsigned int slow_intr_mask;
	225	unsigned long irq_stats[IRQ_NUM_STATS];
	226
	227	struct {
	228	unsigned short vec;
	229	char desc[22];
	230	} msix_info[SGE_QSETS + 1];
	231
	232	/* T3 modules */
	233	struct sge sge;
	234	struct mc7 pmrx;
	235	struct mc7 pmtx;
	236	struct mc7 cm;
	237	struct mc5 mc5;
	238
	239	struct net_device *port[MAX_NPORTS];
	240	unsigned int check_task_cnt;
	241	struct delayed_work adap_check_task;
	242	struct work_struct ext_intr_handler_task;
20d3fc11	243	struct work_struct fatal_error_handler_task;
4d22de3e	244
4d22de3e DLR	245	struct dentry *debugfs_root;
	246
	247	struct mutex mdio_lock;
	248	spinlock_t stats_lock;
	249	spinlock_t work_lock;
	250	};
	251
	252	static inline u32 t3_read_reg(struct adapter *adapter, u32 reg_addr)
	253	{
	254	u32 val = readl(adapter->regs + reg_addr);
	255
	256	CH_DBG(adapter, MMIO, "read register 0x%x value 0x%x\n", reg_addr, val);
	257	return val;
	258	}
	259
	260	static inline void t3_write_reg(struct adapter *adapter, u32 reg_addr, u32 val)
	261	{
	262	CH_DBG(adapter, MMIO, "setting register 0x%x to 0x%x\n", reg_addr, val);
	263	writel(val, adapter->regs + reg_addr);
	264	}
	265
	266	static inline struct port_info adap2pinfo(struct adapter adap, int idx)
	267	{
	268	return netdev_priv(adap->port[idx]);
	269	}
	270
4d22de3e DLR	271	#define OFFLOAD_DEVMAP_BIT 15
	272
	273	#define tdev2adap(d) container_of(d, struct adapter, tdev)
	274
	275	static inline int offload_running(struct adapter *adapter)
	276	{
	277	return test_bit(OFFLOAD_DEVMAP_BIT, &adapter->open_device_map);
	278	}
	279
	280	int t3_offload_tx(struct t3cdev tdev, struct sk_buff skb);
	281
	282	void t3_os_ext_intr_handler(struct adapter *adapter);
	283	void t3_os_link_changed(struct adapter *adapter, int port_id, int link_status,
	284	int speed, int duplex, int fc);
	285
	286	void t3_sge_start(struct adapter *adap);
	287	void t3_sge_stop(struct adapter *adap);
0ca41c04	288	void t3_stop_sge_timers(struct adapter *adap);
4d22de3e DLR	289	void t3_free_sge_resources(struct adapter *adap);
4d22de3e DLR	290	void t3_sge_err_intr_handler(struct adapter *adapter);
7c239975	291	irq_handler_t t3_intr_handler(struct adapter *adap, int polling);
4d22de3e	292	int t3_eth_xmit(struct sk_buff skb, struct net_device dev);
14ab9892	293	int t3_mgmt_tx(struct adapter adap, struct sk_buff skb);
4d22de3e DLR	294	void t3_update_qset_coalesce(struct sge_qset qs, const struct qset_params p);
	295	int t3_sge_alloc_qset(struct adapter *adapter, unsigned int id, int nports,
	296	int irq_vec_idx, const struct qset_params *p,
bea3348e	297	int ntxq, struct net_device *dev);
4d22de3e DLR	298	int t3_get_desc(const struct sge_qset *qs, unsigned int qnum, unsigned int idx,
	299	unsigned char *data);
	300	irqreturn_t t3_sge_intr_msix(int irq, void *cookie);
	301
	302	#endif /* __T3_ADAPTER_H__ */