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net: cxgb3: convert to hw_features
[deliverable/linux.git] / drivers / net / cxgb3 / common.h
CommitLineData
4d22de3e 1/*
a02d44a0 2 * Copyright (c) 2005-2008 Chelsio, Inc. All rights reserved.
4d22de3e 3 *
1d68e93d
DLR		 4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
4d22de3e 9 *
1d68e93d
DLR		 10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
4d22de3e 31 */
4d22de3e
DLR		 32#ifndef __CHELSIO_COMMON_H
33#define __CHELSIO_COMMON_H
34
35#include <linux/kernel.h>
36#include <linux/types.h>
37#include <linux/ctype.h>
38#include <linux/delay.h>
39#include <linux/init.h>
40#include <linux/netdevice.h>
41#include <linux/ethtool.h>
0f07c4ee 42#include <linux/mdio.h>
4d22de3e
DLR		 43#include "version.h"
44
45#define CH_ERR(adap, fmt, ...) dev_err(&adap->pdev->dev, fmt, ## __VA_ARGS__)
46#define CH_WARN(adap, fmt, ...) dev_warn(&adap->pdev->dev, fmt, ## __VA_ARGS__)
47#define CH_ALERT(adap, fmt, ...) \
48 dev_printk(KERN_ALERT, &adap->pdev->dev, fmt, ## __VA_ARGS__)
49
50/*
51 * More powerful macro that selectively prints messages based on msg_enable.
52 * For info and debugging messages.
53 */
54#define CH_MSG(adapter, level, category, fmt, ...) do { \
55 if ((adapter)->msg_enable & NETIF_MSG_##category) \
56 dev_printk(KERN_##level, &adapter->pdev->dev, fmt, \
57 ## __VA_ARGS__); \
58} while (0)
59
60#ifdef DEBUG
61# define CH_DBG(adapter, category, fmt, ...) \
62 CH_MSG(adapter, DEBUG, category, fmt, ## __VA_ARGS__)
63#else
64# define CH_DBG(adapter, category, fmt, ...)
65#endif
66
67/* Additional NETIF_MSG_* categories */
68#define NETIF_MSG_MMIO 0x8000000
69
4d22de3e
DLR		 70enum {
71 MAX_NPORTS = 2, /* max # of ports */
72 MAX_FRAME_SIZE = 10240, /* max MAC frame size, including header + FCS */
73 EEPROMSIZE = 8192, /* Serial EEPROM size */
167cdf5f 74 SERNUM_LEN = 16, /* Serial # length */
4d22de3e
DLR		 75 RSS_TABLE_SIZE = 64, /* size of RSS lookup and mapping tables */
76 TCB_SIZE = 128, /* TCB size */
77 NMTUS = 16, /* size of MTU table */
78 NCCTRL_WIN = 32, /* # of congestion control windows */
480fe1a3 79 PROTO_SRAM_LINES = 128, /* size of TP sram */
4d22de3e
DLR		 80};
81
52b810d3 82#define MAX_RX_COALESCING_LEN 12288U
4d22de3e
DLR		 83
84enum {
85 PAUSE_RX = 1 << 0,
86 PAUSE_TX = 1 << 1,
87 PAUSE_AUTONEG = 1 << 2
88};
89
90enum {
8ac3ba68 91 SUPPORTED_IRQ = 1 << 24
4d22de3e
DLR		 92};
93
94enum { /* adapter interrupt-maintained statistics */
95 STAT_ULP_CH0_PBL_OOB,
96 STAT_ULP_CH1_PBL_OOB,
97 STAT_PCI_CORR_ECC,
98
99 IRQ_NUM_STATS /* keep last */
100};
101
34336ec0
BH		 102#define TP_VERSION_MAJOR 1
103#define TP_VERSION_MINOR 1
104#define TP_VERSION_MICRO 0
480fe1a3
DLR		 105
106#define S_TP_VERSION_MAJOR 16
107#define M_TP_VERSION_MAJOR 0xFF
108#define V_TP_VERSION_MAJOR(x) ((x) << S_TP_VERSION_MAJOR)
109#define G_TP_VERSION_MAJOR(x) \
110 (((x) >> S_TP_VERSION_MAJOR) & M_TP_VERSION_MAJOR)
111
112#define S_TP_VERSION_MINOR 8
113#define M_TP_VERSION_MINOR 0xFF
114#define V_TP_VERSION_MINOR(x) ((x) << S_TP_VERSION_MINOR)
115#define G_TP_VERSION_MINOR(x) \
116 (((x) >> S_TP_VERSION_MINOR) & M_TP_VERSION_MINOR)
117
118#define S_TP_VERSION_MICRO 0
119#define M_TP_VERSION_MICRO 0xFF
120#define V_TP_VERSION_MICRO(x) ((x) << S_TP_VERSION_MICRO)
121#define G_TP_VERSION_MICRO(x) \
122 (((x) >> S_TP_VERSION_MICRO) & M_TP_VERSION_MICRO)
123
4d22de3e
DLR		 124enum {
125 SGE_QSETS = 8, /* # of SGE Tx/Rx/RspQ sets */
126 SGE_RXQ_PER_SET = 2, /* # of Rx queues per set */
127 SGE_TXQ_PER_SET = 3 /* # of Tx queues per set */
128};
129
130enum sge_context_type { /* SGE egress context types */
131 SGE_CNTXT_RDMA = 0,
132 SGE_CNTXT_ETH = 2,
133 SGE_CNTXT_OFLD = 4,
134 SGE_CNTXT_CTRL = 5
135};
136
137enum {
138 AN_PKT_SIZE = 32, /* async notification packet size */
139 IMMED_PKT_SIZE = 48 /* packet size for immediate data */
140};
141
142struct sg_ent { /* SGE scatter/gather entry */
fb8e4444
AV		 143 __be32 len[2];
144 __be64 addr[2];
4d22de3e
DLR		 145};
146
147#ifndef SGE_NUM_GENBITS
148/* Must be 1 or 2 */
149# define SGE_NUM_GENBITS 2
150#endif
151
152#define TX_DESC_FLITS 16U
153#define WR_FLITS (TX_DESC_FLITS + 1 - SGE_NUM_GENBITS)
154
155struct cphy;
156struct adapter;
157
158struct mdio_ops {
0f07c4ee
BH		 159 int (*read)(struct net_device *dev, int phy_addr, int mmd_addr,
160 u16 reg_addr);
161 int (*write)(struct net_device *dev, int phy_addr, int mmd_addr,
162 u16 reg_addr, u16 val);
163 unsigned mode_support;
4d22de3e
DLR		 164};
165
166struct adapter_info {
952cdf33
DLR		 167 unsigned char nports0; /* # of ports on channel 0 */
168 unsigned char nports1; /* # of ports on channel 1 */
4d22de3e 169 unsigned char phy_base_addr; /* MDIO PHY base address */
4d22de3e 170 unsigned int gpio_out; /* GPIO output settings */
f231e0a5 171 unsigned char gpio_intr[MAX_NPORTS]; /* GPIO PHY IRQ pins */
4d22de3e
DLR		 172 unsigned long caps; /* adapter capabilities */
173 const struct mdio_ops *mdio_ops; /* MDIO operations */
174 const char *desc; /* product description */
175};
176
4d22de3e
DLR		 177struct mc5_stats {
178 unsigned long parity_err;
179 unsigned long active_rgn_full;
180 unsigned long nfa_srch_err;
181 unsigned long unknown_cmd;
182 unsigned long reqq_parity_err;
183 unsigned long dispq_parity_err;
184 unsigned long del_act_empty;
185};
186
187struct mc7_stats {
188 unsigned long corr_err;
189 unsigned long uncorr_err;
190 unsigned long parity_err;
191 unsigned long addr_err;
192};
193
194struct mac_stats {
195 u64 tx_octets; /* total # of octets in good frames */
196 u64 tx_octets_bad; /* total # of octets in error frames */
197 u64 tx_frames; /* all good frames */
198 u64 tx_mcast_frames; /* good multicast frames */
199 u64 tx_bcast_frames; /* good broadcast frames */
200 u64 tx_pause; /* # of transmitted pause frames */
201 u64 tx_deferred; /* frames with deferred transmissions */
202 u64 tx_late_collisions; /* # of late collisions */
203 u64 tx_total_collisions; /* # of total collisions */
204 u64 tx_excess_collisions; /* frame errors from excessive collissions */
205 u64 tx_underrun; /* # of Tx FIFO underruns */
206 u64 tx_len_errs; /* # of Tx length errors */
207 u64 tx_mac_internal_errs; /* # of internal MAC errors on Tx */
208 u64 tx_excess_deferral; /* # of frames with excessive deferral */
209 u64 tx_fcs_errs; /* # of frames with bad FCS */
210
211 u64 tx_frames_64; /* # of Tx frames in a particular range */
212 u64 tx_frames_65_127;
213 u64 tx_frames_128_255;
214 u64 tx_frames_256_511;
215 u64 tx_frames_512_1023;
216 u64 tx_frames_1024_1518;
217 u64 tx_frames_1519_max;
218
219 u64 rx_octets; /* total # of octets in good frames */
220 u64 rx_octets_bad; /* total # of octets in error frames */
221 u64 rx_frames; /* all good frames */
222 u64 rx_mcast_frames; /* good multicast frames */
223 u64 rx_bcast_frames; /* good broadcast frames */
224 u64 rx_pause; /* # of received pause frames */
225 u64 rx_fcs_errs; /* # of received frames with bad FCS */
226 u64 rx_align_errs; /* alignment errors */
227 u64 rx_symbol_errs; /* symbol errors */
228 u64 rx_data_errs; /* data errors */
229 u64 rx_sequence_errs; /* sequence errors */
230 u64 rx_runt; /* # of runt frames */
231 u64 rx_jabber; /* # of jabber frames */
232 u64 rx_short; /* # of short frames */
233 u64 rx_too_long; /* # of oversized frames */
234 u64 rx_mac_internal_errs; /* # of internal MAC errors on Rx */
235
236 u64 rx_frames_64; /* # of Rx frames in a particular range */
237 u64 rx_frames_65_127;
238 u64 rx_frames_128_255;
239 u64 rx_frames_256_511;
240 u64 rx_frames_512_1023;
241 u64 rx_frames_1024_1518;
242 u64 rx_frames_1519_max;
243
244 u64 rx_cong_drops; /* # of Rx drops due to SGE congestion */
245
246 unsigned long tx_fifo_parity_err;
247 unsigned long rx_fifo_parity_err;
248 unsigned long tx_fifo_urun;
249 unsigned long rx_fifo_ovfl;
250 unsigned long serdes_signal_loss;
251 unsigned long xaui_pcs_ctc_err;
252 unsigned long xaui_pcs_align_change;
fc90664e
DLR		 253
254 unsigned long num_toggled; /* # times toggled TxEn due to stuck TX */
255 unsigned long num_resets; /* # times reset due to stuck TX */
256
bf792094 257 unsigned long link_faults; /* # detected link faults */
4d22de3e
DLR		 258};
259
260struct tp_mib_stats {
261 u32 ipInReceive_hi;
262 u32 ipInReceive_lo;
263 u32 ipInHdrErrors_hi;
264 u32 ipInHdrErrors_lo;
265 u32 ipInAddrErrors_hi;
266 u32 ipInAddrErrors_lo;
267 u32 ipInUnknownProtos_hi;
268 u32 ipInUnknownProtos_lo;
269 u32 ipInDiscards_hi;
270 u32 ipInDiscards_lo;
271 u32 ipInDelivers_hi;
272 u32 ipInDelivers_lo;
273 u32 ipOutRequests_hi;
274 u32 ipOutRequests_lo;
275 u32 ipOutDiscards_hi;
276 u32 ipOutDiscards_lo;
277 u32 ipOutNoRoutes_hi;
278 u32 ipOutNoRoutes_lo;
279 u32 ipReasmTimeout;
280 u32 ipReasmReqds;
281 u32 ipReasmOKs;
282 u32 ipReasmFails;
283
284 u32 reserved[8];
285
286 u32 tcpActiveOpens;
287 u32 tcpPassiveOpens;
288 u32 tcpAttemptFails;
289 u32 tcpEstabResets;
290 u32 tcpOutRsts;
291 u32 tcpCurrEstab;
292 u32 tcpInSegs_hi;
293 u32 tcpInSegs_lo;
294 u32 tcpOutSegs_hi;
295 u32 tcpOutSegs_lo;
296 u32 tcpRetransSeg_hi;
297 u32 tcpRetransSeg_lo;
298 u32 tcpInErrs_hi;
299 u32 tcpInErrs_lo;
300 u32 tcpRtoMin;
301 u32 tcpRtoMax;
302};
303
304struct tp_params {
305 unsigned int nchan; /* # of channels */
306 unsigned int pmrx_size; /* total PMRX capacity */
307 unsigned int pmtx_size; /* total PMTX capacity */
308 unsigned int cm_size; /* total CM capacity */
309 unsigned int chan_rx_size; /* per channel Rx size */
310 unsigned int chan_tx_size; /* per channel Tx size */
311 unsigned int rx_pg_size; /* Rx page size */
312 unsigned int tx_pg_size; /* Tx page size */
313 unsigned int rx_num_pgs; /* # of Rx pages */
314 unsigned int tx_num_pgs; /* # of Tx pages */
315 unsigned int ntimer_qs; /* # of timer queues */
316};
317
318struct qset_params { /* SGE queue set parameters */
319 unsigned int polling; /* polling/interrupt service for rspq */
320 unsigned int coalesce_usecs; /* irq coalescing timer */
321 unsigned int rspq_size; /* # of entries in response queue */
322 unsigned int fl_size; /* # of entries in regular free list */
323 unsigned int jumbo_size; /* # of entries in jumbo free list */
324 unsigned int txq_size[SGE_TXQ_PER_SET]; /* Tx queue sizes */
325 unsigned int cong_thres; /* FL congestion threshold */
8c263761 326 unsigned int vector; /* Interrupt (line or vector) number */
4d22de3e
DLR		 327};
328
329struct sge_params {
330 unsigned int max_pkt_size; /* max offload pkt size */
331 struct qset_params qset[SGE_QSETS];
332};
333
334struct mc5_params {
335 unsigned int mode; /* selects MC5 width */
336 unsigned int nservers; /* size of server region */
337 unsigned int nfilters; /* size of filter region */
338 unsigned int nroutes; /* size of routing region */
339};
340
341/* Default MC5 region sizes */
342enum {
343 DEFAULT_NSERVERS = 512,
344 DEFAULT_NFILTERS = 128
345};
346
347/* MC5 modes, these must be non-0 */
348enum {
349 MC5_MODE_144_BIT = 1,
350 MC5_MODE_72_BIT = 2
351};
352
9f238486
DLR		 353/* MC5 min active region size */
354enum { MC5_MIN_TIDS = 16 };
355
4d22de3e
DLR		 356struct vpd_params {
357 unsigned int cclk;
358 unsigned int mclk;
359 unsigned int uclk;
360 unsigned int mdc;
361 unsigned int mem_timing;
167cdf5f 362 u8 sn[SERNUM_LEN + 1];
4d22de3e
DLR		 363 u8 eth_base[6];
364 u8 port_type[MAX_NPORTS];
365 unsigned short xauicfg[2];
366};
367
368struct pci_params {
369 unsigned int vpd_cap_addr;
370 unsigned int pcie_cap_addr;
371 unsigned short speed;
372 unsigned char width;
373 unsigned char variant;
374};
375
376enum {
377 PCI_VARIANT_PCI,
378 PCI_VARIANT_PCIX_MODE1_PARITY,
379 PCI_VARIANT_PCIX_MODE1_ECC,
380 PCI_VARIANT_PCIX_266_MODE2,
381 PCI_VARIANT_PCIE
382};
383
384struct adapter_params {
385 struct sge_params sge;
386 struct mc5_params mc5;
387 struct tp_params tp;
388 struct vpd_params vpd;
389 struct pci_params pci;
390
391 const struct adapter_info *info;
392
393 unsigned short mtus[NMTUS];
394 unsigned short a_wnd[NCCTRL_WIN];
395 unsigned short b_wnd[NCCTRL_WIN];
396
397 unsigned int nports; /* # of ethernet ports */
952cdf33 398 unsigned int chan_map; /* bitmap of in-use Tx channels */
4d22de3e
DLR		 399 unsigned int stats_update_period; /* MAC stats accumulation period */
400 unsigned int linkpoll_period; /* link poll period in 0.1s */
401 unsigned int rev; /* chip revision */
8ac3ba68 402 unsigned int offload;
4d22de3e
DLR		 403};
404
fc90664e
DLR		 405enum { /* chip revisions */
406 T3_REV_A = 0,
407 T3_REV_B = 2,
408 T3_REV_B2 = 3,
1aafee26 409 T3_REV_C = 4,
fc90664e
DLR		 410};
411
4d22de3e
DLR		 412struct trace_params {
413 u32 sip;
414 u32 sip_mask;
415 u32 dip;
416 u32 dip_mask;
417 u16 sport;
418 u16 sport_mask;
419 u16 dport;
420 u16 dport_mask;
421 u32 vlan:12;
422 u32 vlan_mask:12;
423 u32 intf:4;
424 u32 intf_mask:4;
425 u8 proto;
426 u8 proto_mask;
427};
428
429struct link_config {
430 unsigned int supported; /* link capabilities */
431 unsigned int advertising; /* advertised capabilities */
432 unsigned short requested_speed; /* speed user has requested */
433 unsigned short speed; /* actual link speed */
434 unsigned char requested_duplex; /* duplex user has requested */
435 unsigned char duplex; /* actual link duplex */
436 unsigned char requested_fc; /* flow control user has requested */
437 unsigned char fc; /* actual link flow control */
438 unsigned char autoneg; /* autonegotiating? */
439 unsigned int link_ok; /* link up? */
440};
441
442#define SPEED_INVALID 0xffff
443#define DUPLEX_INVALID 0xff
444
445struct mc5 {
446 struct adapter *adapter;
447 unsigned int tcam_size;
448 unsigned char part_type;
449 unsigned char parity_enabled;
450 unsigned char mode;
451 struct mc5_stats stats;
452};
453
454static inline unsigned int t3_mc5_size(const struct mc5 *p)
455{
456 return p->tcam_size;
457}
458
459struct mc7 {
460 struct adapter *adapter; /* backpointer to adapter */
461 unsigned int size; /* memory size in bytes */
462 unsigned int width; /* MC7 interface width */
463 unsigned int offset; /* register address offset for MC7 instance */
464 const char *name; /* name of MC7 instance */
465 struct mc7_stats stats; /* MC7 statistics */
466};
467
468static inline unsigned int t3_mc7_size(const struct mc7 *p)
469{
470 return p->size;
471}
472
473struct cmac {
474 struct adapter *adapter;
475 unsigned int offset;
476 unsigned int nucast; /* # of address filters for unicast MACs */
59cf8107
DLR		 477 unsigned int tx_tcnt;
478 unsigned int tx_xcnt;
479 u64 tx_mcnt;
480 unsigned int rx_xcnt;
b1c9e0f7 481 unsigned int rx_ocnt;
59cf8107 482 u64 rx_mcnt;
fc90664e
DLR		 483 unsigned int toggle_cnt;
484 unsigned int txen;
b4687ff7 485 u64 rx_pause;
4d22de3e
DLR		 486 struct mac_stats stats;
487};
488
489enum {
490 MAC_DIRECTION_RX = 1,
491 MAC_DIRECTION_TX = 2,
492 MAC_RXFIFO_SIZE = 32768
493};
494
4d22de3e
DLR		 495/* PHY loopback direction */
496enum {
497 PHY_LOOPBACK_TX = 1,
498 PHY_LOOPBACK_RX = 2
499};
500
501/* PHY interrupt types */
502enum {
503 cphy_cause_link_change = 1,
1e882025
DLR		 504 cphy_cause_fifo_error = 2,
505 cphy_cause_module_change = 4,
506};
507
508/* PHY module types */
509enum {
510 phy_modtype_none,
511 phy_modtype_sr,
512 phy_modtype_lr,
513 phy_modtype_lrm,
514 phy_modtype_twinax,
515 phy_modtype_twinax_long,
516 phy_modtype_unknown
4d22de3e
DLR		 517};
518
519/* PHY operations */
520struct cphy_ops {
4d22de3e
DLR		 521 int (*reset)(struct cphy *phy, int wait);
522
523 int (*intr_enable)(struct cphy *phy);
524 int (*intr_disable)(struct cphy *phy);
525 int (*intr_clear)(struct cphy *phy);
526 int (*intr_handler)(struct cphy *phy);
527
528 int (*autoneg_enable)(struct cphy *phy);
529 int (*autoneg_restart)(struct cphy *phy);
530
531 int (*advertise)(struct cphy *phy, unsigned int advertise_map);
532 int (*set_loopback)(struct cphy *phy, int mmd, int dir, int enable);
533 int (*set_speed_duplex)(struct cphy *phy, int speed, int duplex);
534 int (*get_link_status)(struct cphy *phy, int *link_ok, int *speed,
535 int *duplex, int *fc);
536 int (*power_down)(struct cphy *phy, int enable);
0f07c4ee
BH		 537
538 u32 mmds;
4d22de3e 539};
2e8c07c3
DLR		 540enum {
541 EDC_OPT_AEL2005 = 0,
542 EDC_OPT_AEL2005_SIZE = 1084,
543 EDC_TWX_AEL2005 = 1,
544 EDC_TWX_AEL2005_SIZE = 1464,
545 EDC_TWX_AEL2020 = 2,
546 EDC_TWX_AEL2020_SIZE = 1628,
547 EDC_MAX_SIZE = EDC_TWX_AEL2020_SIZE, /* Max cache size */
548};
4d22de3e
DLR		 549
550/* A PHY instance */
551struct cphy {
1e882025
DLR		 552 u8 modtype; /* PHY module type */
553 short priv; /* scratch pad */
04497982 554 unsigned int caps; /* PHY capabilities */
4d22de3e 555 struct adapter *adapter; /* associated adapter */
04497982 556 const char *desc; /* PHY description */
4d22de3e
DLR		 557 unsigned long fifo_errors; /* FIFO over/under-flows */
558 const struct cphy_ops *ops; /* PHY operations */
0f07c4ee 559 struct mdio_if_info mdio;
2e8c07c3 560 u16 phy_cache[EDC_MAX_SIZE]; /* EDC cache */
4d22de3e
DLR		 561};
562
563/* Convenience MDIO read/write wrappers */
0f07c4ee
BH		 564static inline int t3_mdio_read(struct cphy *phy, int mmd, int reg,
565 unsigned int *valp)
4d22de3e 566{
0f07c4ee
BH		 567 int rc = phy->mdio.mdio_read(phy->mdio.dev, phy->mdio.prtad, mmd, reg);
568 *valp = (rc >= 0) ? rc : -1;
569 return (rc >= 0) ? 0 : rc;
4d22de3e
DLR		 570}
571
0f07c4ee
BH		 572static inline int t3_mdio_write(struct cphy *phy, int mmd, int reg,
573 unsigned int val)
4d22de3e 574{
0f07c4ee
BH		 575 return phy->mdio.mdio_write(phy->mdio.dev, phy->mdio.prtad, mmd,
576 reg, val);
4d22de3e
DLR		 577}
578
579/* Convenience initializer */
580static inline void cphy_init(struct cphy *phy, struct adapter *adapter,
581 int phy_addr, struct cphy_ops *phy_ops,
04497982
DLR		 582 const struct mdio_ops *mdio_ops,
583 unsigned int caps, const char *desc)
4d22de3e 584{
04497982
DLR		 585 phy->caps = caps;
586 phy->adapter = adapter;
587 phy->desc = desc;
4d22de3e
DLR		 588 phy->ops = phy_ops;
589 if (mdio_ops) {
0f07c4ee
BH		 590 phy->mdio.prtad = phy_addr;
591 phy->mdio.mmds = phy_ops->mmds;
592 phy->mdio.mode_support = mdio_ops->mode_support;
593 phy->mdio.mdio_read = mdio_ops->read;
594 phy->mdio.mdio_write = mdio_ops->write;
4d22de3e
DLR		 595 }
596}
597
598/* Accumulate MAC statistics every 180 seconds. For 1G we multiply by 10. */
599#define MAC_STATS_ACCUM_SECS 180
600
601#define XGM_REG(reg_addr, idx) \
602 ((reg_addr) + (idx) * (XGMAC0_1_BASE_ADDR - XGMAC0_0_BASE_ADDR))
603
604struct addr_val_pair {
605 unsigned int reg_addr;
606 unsigned int val;
607};
608
609#include "adapter.h"
610
611#ifndef PCI_VENDOR_ID_CHELSIO
612# define PCI_VENDOR_ID_CHELSIO 0x1425
613#endif
614
615#define for_each_port(adapter, iter) \
616 for (iter = 0; iter < (adapter)->params.nports; ++iter)
617
618#define adapter_info(adap) ((adap)->params.info)
619
620static inline int uses_xaui(const struct adapter *adap)
621{
622 return adapter_info(adap)->caps & SUPPORTED_AUI;
623}
624
625static inline int is_10G(const struct adapter *adap)
626{
627 return adapter_info(adap)->caps & SUPPORTED_10000baseT_Full;
628}
629
630static inline int is_offload(const struct adapter *adap)
631{
8ac3ba68 632 return adap->params.offload;
4d22de3e
DLR		 633}
634
635static inline unsigned int core_ticks_per_usec(const struct adapter *adap)
636{
637 return adap->params.vpd.cclk / 1000;
638}
639
640static inline unsigned int is_pcie(const struct adapter *adap)
641{
642 return adap->params.pci.variant == PCI_VARIANT_PCIE;
643}
644
645void t3_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask,
646 u32 val);
647void t3_write_regs(struct adapter *adapter, const struct addr_val_pair *p,
648 int n, unsigned int offset);
649int t3_wait_op_done_val(struct adapter *adapter, int reg, u32 mask,
650 int polarity, int attempts, int delay, u32 *valp);
651static inline int t3_wait_op_done(struct adapter *adapter, int reg, u32 mask,
652 int polarity, int attempts, int delay)
653{
654 return t3_wait_op_done_val(adapter, reg, mask, polarity, attempts,
655 delay, NULL);
656}
657int t3_mdio_change_bits(struct cphy *phy, int mmd, int reg, unsigned int clear,
658 unsigned int set);
659int t3_phy_reset(struct cphy *phy, int mmd, int wait);
660int t3_phy_advertise(struct cphy *phy, unsigned int advert);
0ce2f03b 661int t3_phy_advertise_fiber(struct cphy *phy, unsigned int advert);
4d22de3e 662int t3_set_phy_speed_duplex(struct cphy *phy, int speed, int duplex);
9b1e3656
DLR		 663int t3_phy_lasi_intr_enable(struct cphy *phy);
664int t3_phy_lasi_intr_disable(struct cphy *phy);
665int t3_phy_lasi_intr_clear(struct cphy *phy);
666int t3_phy_lasi_intr_handler(struct cphy *phy);
4d22de3e
DLR		 667
668void t3_intr_enable(struct adapter *adapter);
669void t3_intr_disable(struct adapter *adapter);
670void t3_intr_clear(struct adapter *adapter);
bf792094
DLR		 671void t3_xgm_intr_enable(struct adapter *adapter, int idx);
672void t3_xgm_intr_disable(struct adapter *adapter, int idx);
4d22de3e
DLR		 673void t3_port_intr_enable(struct adapter *adapter, int idx);
674void t3_port_intr_disable(struct adapter *adapter, int idx);
4d22de3e
DLR		 675int t3_slow_intr_handler(struct adapter *adapter);
676int t3_phy_intr_handler(struct adapter *adapter);
677
678void t3_link_changed(struct adapter *adapter, int port_id);
bf792094 679void t3_link_fault(struct adapter *adapter, int port_id);
4d22de3e
DLR		 680int t3_link_start(struct cphy *phy, struct cmac *mac, struct link_config *lc);
681const struct adapter_info *t3_get_adapter_info(unsigned int board_id);
05e5c116
AV		 682int t3_seeprom_read(struct adapter *adapter, u32 addr, __le32 *data);
683int t3_seeprom_write(struct adapter *adapter, u32 addr, __le32 data);
4d22de3e 684int t3_seeprom_wp(struct adapter *adapter, int enable);
47330077 685int t3_get_tp_version(struct adapter *adapter, u32 *vers);
8207befa 686int t3_check_tpsram_version(struct adapter *adapter);
2c733a16
DW		 687int t3_check_tpsram(struct adapter *adapter, const u8 *tp_ram,
688 unsigned int size);
689int t3_set_proto_sram(struct adapter *adap, const u8 *data);
4d22de3e
DLR		 690int t3_load_fw(struct adapter *adapter, const u8 * fw_data, unsigned int size);
691int t3_get_fw_version(struct adapter *adapter, u32 *vers);
8207befa 692int t3_check_fw_version(struct adapter *adapter);
4d22de3e 693int t3_init_hw(struct adapter *adapter, u32 fw_params);
20d3fc11 694int t3_reset_adapter(struct adapter *adapter);
4d22de3e
DLR		 695int t3_prep_adapter(struct adapter *adapter, const struct adapter_info *ai,
696 int reset);
204e2f98 697int t3_replay_prep_adapter(struct adapter *adapter);
4d22de3e
DLR		 698void t3_led_ready(struct adapter *adapter);
699void t3_fatal_err(struct adapter *adapter);
700void t3_set_vlan_accel(struct adapter *adapter, unsigned int ports, int on);
701void t3_config_rss(struct adapter *adapter, unsigned int rss_config,
702 const u8 * cpus, const u16 *rspq);
4d22de3e
DLR		 703int t3_cim_ctl_blk_read(struct adapter *adap, unsigned int addr,
704 unsigned int n, unsigned int *valp);
705int t3_mc7_bd_read(struct mc7 *mc7, unsigned int start, unsigned int n,
706 u64 *buf);
707
708int t3_mac_reset(struct cmac *mac);
709void t3b_pcs_reset(struct cmac *mac);
bf792094
DLR		 710void t3_mac_disable_exact_filters(struct cmac *mac);
711void t3_mac_enable_exact_filters(struct cmac *mac);
4d22de3e
DLR		 712int t3_mac_enable(struct cmac *mac, int which);
713int t3_mac_disable(struct cmac *mac, int which);
714int t3_mac_set_mtu(struct cmac *mac, unsigned int mtu);
0988d269 715int t3_mac_set_rx_mode(struct cmac *mac, struct net_device *dev);
4d22de3e
DLR		 716int t3_mac_set_address(struct cmac *mac, unsigned int idx, u8 addr[6]);
717int t3_mac_set_num_ucast(struct cmac *mac, int n);
718const struct mac_stats *t3_mac_update_stats(struct cmac *mac);
719int t3_mac_set_speed_duplex_fc(struct cmac *mac, int speed, int duplex, int fc);
fc90664e 720int t3b2_mac_watchdog_task(struct cmac *mac);
4d22de3e
DLR		 721
722void t3_mc5_prep(struct adapter *adapter, struct mc5 *mc5, int mode);
723int t3_mc5_init(struct mc5 *mc5, unsigned int nservers, unsigned int nfilters,
724 unsigned int nroutes);
725void t3_mc5_intr_handler(struct mc5 *mc5);
4d22de3e 726
4d22de3e
DLR		 727void t3_tp_set_offload_mode(struct adapter *adap, int enable);
728void t3_tp_get_mib_stats(struct adapter *adap, struct tp_mib_stats *tps);
729void t3_load_mtus(struct adapter *adap, unsigned short mtus[NMTUS],
730 unsigned short alpha[NCCTRL_WIN],
731 unsigned short beta[NCCTRL_WIN], unsigned short mtu_cap);
4d22de3e
DLR		 732void t3_config_trace_filter(struct adapter *adapter,
733 const struct trace_params *tp, int filter_index,
734 int invert, int enable);
735int t3_config_sched(struct adapter *adap, unsigned int kbps, int sched);
736
737void t3_sge_prep(struct adapter *adap, struct sge_params *p);
738void t3_sge_init(struct adapter *adap, struct sge_params *p);
739int t3_sge_init_ecntxt(struct adapter *adapter, unsigned int id, int gts_enable,
740 enum sge_context_type type, int respq, u64 base_addr,
741 unsigned int size, unsigned int token, int gen,
742 unsigned int cidx);
743int t3_sge_init_flcntxt(struct adapter *adapter, unsigned int id,
744 int gts_enable, u64 base_addr, unsigned int size,
745 unsigned int esize, unsigned int cong_thres, int gen,
746 unsigned int cidx);
747int t3_sge_init_rspcntxt(struct adapter *adapter, unsigned int id,
748 int irq_vec_idx, u64 base_addr, unsigned int size,
749 unsigned int fl_thres, int gen, unsigned int cidx);
750int t3_sge_init_cqcntxt(struct adapter *adapter, unsigned int id, u64 base_addr,
751 unsigned int size, int rspq, int ovfl_mode,
752 unsigned int credits, unsigned int credit_thres);
753int t3_sge_enable_ecntxt(struct adapter *adapter, unsigned int id, int enable);
754int t3_sge_disable_fl(struct adapter *adapter, unsigned int id);
755int t3_sge_disable_rspcntxt(struct adapter *adapter, unsigned int id);
756int t3_sge_disable_cqcntxt(struct adapter *adapter, unsigned int id);
4d22de3e
DLR		 757int t3_sge_cqcntxt_op(struct adapter *adapter, unsigned int id, unsigned int op,
758 unsigned int credits);
759
78e4689e
DLR		 760int t3_vsc8211_phy_prep(struct cphy *phy, struct adapter *adapter,
761 int phy_addr, const struct mdio_ops *mdio_ops);
762int t3_ael1002_phy_prep(struct cphy *phy, struct adapter *adapter,
763 int phy_addr, const struct mdio_ops *mdio_ops);
764int t3_ael1006_phy_prep(struct cphy *phy, struct adapter *adapter,
765 int phy_addr, const struct mdio_ops *mdio_ops);
1e882025
DLR		 766int t3_ael2005_phy_prep(struct cphy *phy, struct adapter *adapter,
767 int phy_addr, const struct mdio_ops *mdio_ops);
74451424
DLR		 768int t3_ael2020_phy_prep(struct cphy *phy, struct adapter *adapter,
769 int phy_addr, const struct mdio_ops *mdio_ops);
78e4689e
DLR		 770int t3_qt2045_phy_prep(struct cphy *phy, struct adapter *adapter, int phy_addr,
771 const struct mdio_ops *mdio_ops);
772int t3_xaui_direct_phy_prep(struct cphy *phy, struct adapter *adapter,
773 int phy_addr, const struct mdio_ops *mdio_ops);
f22a563b
DLR		 774int t3_aq100x_phy_prep(struct cphy *phy, struct adapter *adapter,
775 int phy_addr, const struct mdio_ops *mdio_ops);
4d22de3e 776#endif /* __CHELSIO_COMMON_H */
Linux kernel - Deliverables
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