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cxgb3 - MAC watchdog update
[deliverable/linux.git] / drivers / net / cxgb3 / xgmac.c
CommitLineData
4d22de3e 1/*
1d68e93d 2 * Copyright (c) 2005-2007 Chelsio, Inc. All rights reserved.
4d22de3e 3 *
1d68e93d
DLR		 4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
4d22de3e 9 *
1d68e93d
DLR		 10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
4d22de3e 31 */
4d22de3e
DLR		 32#include "common.h"
33#include "regs.h"
34
35/*
36 * # of exact address filters. The first one is used for the station address,
37 * the rest are available for multicast addresses.
38 */
39#define EXACT_ADDR_FILTERS 8
40
41static inline int macidx(const struct cmac *mac)
42{
43 return mac->offset / (XGMAC0_1_BASE_ADDR - XGMAC0_0_BASE_ADDR);
44}
45
46static void xaui_serdes_reset(struct cmac *mac)
47{
48 static const unsigned int clear[] = {
49 F_PWRDN0 | F_PWRDN1, F_RESETPLL01, F_RESET0 | F_RESET1,
50 F_PWRDN2 | F_PWRDN3, F_RESETPLL23, F_RESET2 | F_RESET3
51 };
52
53 int i;
54 struct adapter *adap = mac->adapter;
55 u32 ctrl = A_XGM_SERDES_CTRL0 + mac->offset;
56
57 t3_write_reg(adap, ctrl, adap->params.vpd.xauicfg[macidx(mac)] |
58 F_RESET3 | F_RESET2 | F_RESET1 | F_RESET0 |
59 F_PWRDN3 | F_PWRDN2 | F_PWRDN1 | F_PWRDN0 |
60 F_RESETPLL23 | F_RESETPLL01);
61 t3_read_reg(adap, ctrl);
62 udelay(15);
63
64 for (i = 0; i < ARRAY_SIZE(clear); i++) {
65 t3_set_reg_field(adap, ctrl, clear[i], 0);
66 udelay(15);
67 }
68}
69
70void t3b_pcs_reset(struct cmac *mac)
71{
72 t3_set_reg_field(mac->adapter, A_XGM_RESET_CTRL + mac->offset,
73 F_PCS_RESET_, 0);
74 udelay(20);
75 t3_set_reg_field(mac->adapter, A_XGM_RESET_CTRL + mac->offset, 0,
76 F_PCS_RESET_);
77}
78
79int t3_mac_reset(struct cmac *mac)
80{
81 static const struct addr_val_pair mac_reset_avp[] = {
82 {A_XGM_TX_CTRL, 0},
83 {A_XGM_RX_CTRL, 0},
84 {A_XGM_RX_CFG, F_DISPAUSEFRAMES | F_EN1536BFRAMES |
85 F_RMFCS | F_ENJUMBO | F_ENHASHMCAST},
86 {A_XGM_RX_HASH_LOW, 0},
87 {A_XGM_RX_HASH_HIGH, 0},
88 {A_XGM_RX_EXACT_MATCH_LOW_1, 0},
89 {A_XGM_RX_EXACT_MATCH_LOW_2, 0},
90 {A_XGM_RX_EXACT_MATCH_LOW_3, 0},
91 {A_XGM_RX_EXACT_MATCH_LOW_4, 0},
92 {A_XGM_RX_EXACT_MATCH_LOW_5, 0},
93 {A_XGM_RX_EXACT_MATCH_LOW_6, 0},
94 {A_XGM_RX_EXACT_MATCH_LOW_7, 0},
95 {A_XGM_RX_EXACT_MATCH_LOW_8, 0},
96 {A_XGM_STAT_CTRL, F_CLRSTATS}
97 };
98 u32 val;
99 struct adapter *adap = mac->adapter;
100 unsigned int oft = mac->offset;
101
102 t3_write_reg(adap, A_XGM_RESET_CTRL + oft, F_MAC_RESET_);
103 t3_read_reg(adap, A_XGM_RESET_CTRL + oft); /* flush */
104
105 t3_write_regs(adap, mac_reset_avp, ARRAY_SIZE(mac_reset_avp), oft);
106 t3_set_reg_field(adap, A_XGM_RXFIFO_CFG + oft,
107 F_RXSTRFRWRD | F_DISERRFRAMES,
108 uses_xaui(adap) ? 0 : F_RXSTRFRWRD);
109
110 if (uses_xaui(adap)) {
111 if (adap->params.rev == 0) {
112 t3_set_reg_field(adap, A_XGM_SERDES_CTRL + oft, 0,
113 F_RXENABLE | F_TXENABLE);
114 if (t3_wait_op_done(adap, A_XGM_SERDES_STATUS1 + oft,
115 F_CMULOCK, 1, 5, 2)) {
116 CH_ERR(adap,
117 "MAC %d XAUI SERDES CMU lock failed\n",
118 macidx(mac));
119 return -1;
120 }
121 t3_set_reg_field(adap, A_XGM_SERDES_CTRL + oft, 0,
122 F_SERDESRESET_);
123 } else
124 xaui_serdes_reset(mac);
125 }
126
4d22de3e
DLR		 127 val = F_MAC_RESET_;
128 if (is_10G(adap))
129 val |= F_PCS_RESET_;
130 else if (uses_xaui(adap))
131 val |= F_PCS_RESET_ | F_XG2G_RESET_;
132 else
133 val |= F_RGMII_RESET_ | F_XG2G_RESET_;
134 t3_write_reg(adap, A_XGM_RESET_CTRL + oft, val);
135 t3_read_reg(adap, A_XGM_RESET_CTRL + oft); /* flush */
136 if ((val & F_PCS_RESET_) && adap->params.rev) {
137 msleep(1);
138 t3b_pcs_reset(mac);
139 }
140
141 memset(&mac->stats, 0, sizeof(mac->stats));
142 return 0;
143}
144
fc90664e
DLR		 145int t3b2_mac_reset(struct cmac *mac)
146{
147 struct adapter *adap = mac->adapter;
148 unsigned int oft = mac->offset;
149 u32 val;
150
151 if (!macidx(mac))
152 t3_set_reg_field(adap, A_MPS_CFG, F_PORT0ACTIVE, 0);
153 else
154 t3_set_reg_field(adap, A_MPS_CFG, F_PORT1ACTIVE, 0);
155
156 t3_write_reg(adap, A_XGM_RESET_CTRL + oft, F_MAC_RESET_);
157 t3_read_reg(adap, A_XGM_RESET_CTRL + oft); /* flush */
158
159 msleep(10);
160
161 /* Check for xgm Rx fifo empty */
162 if (t3_wait_op_done(adap, A_XGM_RX_MAX_PKT_SIZE_ERR_CNT + oft,
163 0x80000000, 1, 5, 2)) {
164 CH_ERR(adap, "MAC %d Rx fifo drain failed\n",
165 macidx(mac));
166 return -1;
167 }
168
169 t3_write_reg(adap, A_XGM_RESET_CTRL + oft, 0);
170 t3_read_reg(adap, A_XGM_RESET_CTRL + oft); /* flush */
171
172 val = F_MAC_RESET_;
173 if (is_10G(adap))
174 val |= F_PCS_RESET_;
175 else if (uses_xaui(adap))
176 val |= F_PCS_RESET_ | F_XG2G_RESET_;
177 else
178 val |= F_RGMII_RESET_ | F_XG2G_RESET_;
179 t3_write_reg(adap, A_XGM_RESET_CTRL + oft, val);
180 t3_read_reg(adap, A_XGM_RESET_CTRL + oft); /* flush */
181 if ((val & F_PCS_RESET_) && adap->params.rev) {
182 msleep(1);
183 t3b_pcs_reset(mac);
184 }
185 t3_write_reg(adap, A_XGM_RX_CFG + oft,
186 F_DISPAUSEFRAMES | F_EN1536BFRAMES |
187 F_RMFCS | F_ENJUMBO | F_ENHASHMCAST);
188
189 if (!macidx(mac))
190 t3_set_reg_field(adap, A_MPS_CFG, 0, F_PORT0ACTIVE);
191 else
192 t3_set_reg_field(adap, A_MPS_CFG, 0, F_PORT1ACTIVE);
193
194 return 0;
195}
196
4d22de3e
DLR		 197/*
198 * Set the exact match register 'idx' to recognize the given Ethernet address.
199 */
200static void set_addr_filter(struct cmac *mac, int idx, const u8 * addr)
201{
202 u32 addr_lo, addr_hi;
203 unsigned int oft = mac->offset + idx * 8;
204
205 addr_lo = (addr[3] << 24) | (addr[2] << 16) | (addr[1] << 8) | addr[0];
206 addr_hi = (addr[5] << 8) | addr[4];
207
208 t3_write_reg(mac->adapter, A_XGM_RX_EXACT_MATCH_LOW_1 + oft, addr_lo);
209 t3_write_reg(mac->adapter, A_XGM_RX_EXACT_MATCH_HIGH_1 + oft, addr_hi);
210}
211
212/* Set one of the station's unicast MAC addresses. */
213int t3_mac_set_address(struct cmac *mac, unsigned int idx, u8 addr[6])
214{
215 if (idx >= mac->nucast)
216 return -EINVAL;
217 set_addr_filter(mac, idx, addr);
218 return 0;
219}
220
221/*
222 * Specify the number of exact address filters that should be reserved for
223 * unicast addresses. Caller should reload the unicast and multicast addresses
224 * after calling this.
225 */
226int t3_mac_set_num_ucast(struct cmac *mac, int n)
227{
228 if (n > EXACT_ADDR_FILTERS)
229 return -EINVAL;
230 mac->nucast = n;
231 return 0;
232}
233
234/* Calculate the RX hash filter index of an Ethernet address */
235static int hash_hw_addr(const u8 * addr)
236{
237 int hash = 0, octet, bit, i = 0, c;
238
239 for (octet = 0; octet < 6; ++octet)
240 for (c = addr[octet], bit = 0; bit < 8; c >>= 1, ++bit) {
241 hash ^= (c & 1) << i;
242 if (++i == 6)
243 i = 0;
244 }
245 return hash;
246}
247
248int t3_mac_set_rx_mode(struct cmac *mac, struct t3_rx_mode *rm)
249{
250 u32 val, hash_lo, hash_hi;
251 struct adapter *adap = mac->adapter;
252 unsigned int oft = mac->offset;
253
254 val = t3_read_reg(adap, A_XGM_RX_CFG + oft) & ~F_COPYALLFRAMES;
255 if (rm->dev->flags & IFF_PROMISC)
256 val |= F_COPYALLFRAMES;
257 t3_write_reg(adap, A_XGM_RX_CFG + oft, val);
258
259 if (rm->dev->flags & IFF_ALLMULTI)
260 hash_lo = hash_hi = 0xffffffff;
261 else {
262 u8 *addr;
263 int exact_addr_idx = mac->nucast;
264
265 hash_lo = hash_hi = 0;
266 while ((addr = t3_get_next_mcaddr(rm)))
267 if (exact_addr_idx < EXACT_ADDR_FILTERS)
268 set_addr_filter(mac, exact_addr_idx++, addr);
269 else {
270 int hash = hash_hw_addr(addr);
271
272 if (hash < 32)
273 hash_lo |= (1 << hash);
274 else
275 hash_hi |= (1 << (hash - 32));
276 }
277 }
278
279 t3_write_reg(adap, A_XGM_RX_HASH_LOW + oft, hash_lo);
280 t3_write_reg(adap, A_XGM_RX_HASH_HIGH + oft, hash_hi);
281 return 0;
282}
283
284int t3_mac_set_mtu(struct cmac *mac, unsigned int mtu)
285{
286 int hwm, lwm;
287 unsigned int thres, v;
288 struct adapter *adap = mac->adapter;
289
290 /*
291 * MAX_FRAME_SIZE inludes header + FCS, mtu doesn't. The HW max
292 * packet size register includes header, but not FCS.
293 */
294 mtu += 14;
295 if (mtu > MAX_FRAME_SIZE - 4)
296 return -EINVAL;
297 t3_write_reg(adap, A_XGM_RX_MAX_PKT_SIZE + mac->offset, mtu);
298
299 /*
300 * Adjust the PAUSE frame watermarks. We always set the LWM, and the
301 * HWM only if flow-control is enabled.
302 */
fc90664e
DLR		 303 hwm = max_t(unsigned int, MAC_RXFIFO_SIZE - 3 * mtu,
304 MAC_RXFIFO_SIZE * 38 / 100);
305 hwm = min(hwm, MAC_RXFIFO_SIZE - 8192);
306 lwm = min(3 * (int)mtu, MAC_RXFIFO_SIZE / 4);
307
4d22de3e
DLR		 308 v = t3_read_reg(adap, A_XGM_RXFIFO_CFG + mac->offset);
309 v &= ~V_RXFIFOPAUSELWM(M_RXFIFOPAUSELWM);
310 v |= V_RXFIFOPAUSELWM(lwm / 8);
311 if (G_RXFIFOPAUSEHWM(v))
312 v = (v & ~V_RXFIFOPAUSEHWM(M_RXFIFOPAUSEHWM)) |
313 V_RXFIFOPAUSEHWM(hwm / 8);
314 t3_write_reg(adap, A_XGM_RXFIFO_CFG + mac->offset, v);
315
316 /* Adjust the TX FIFO threshold based on the MTU */
317 thres = (adap->params.vpd.cclk * 1000) / 15625;
318 thres = (thres * mtu) / 1000;
319 if (is_10G(adap))
320 thres /= 10;
321 thres = mtu > thres ? (mtu - thres + 7) / 8 : 0;
322 thres = max(thres, 8U); /* need at least 8 */
323 t3_set_reg_field(adap, A_XGM_TXFIFO_CFG + mac->offset,
fc90664e
DLR		 324 V_TXFIFOTHRESH(M_TXFIFOTHRESH) | V_TXIPG(M_TXIPG),
325 V_TXFIFOTHRESH(thres) | V_TXIPG(1));
326
327 if (adap->params.rev > 0)
328 t3_write_reg(adap, A_XGM_PAUSE_TIMER + mac->offset,
329 (hwm - lwm) * 4 / 8);
330 t3_write_reg(adap, A_XGM_TX_PAUSE_QUANTA + mac->offset,
331 MAC_RXFIFO_SIZE * 4 * 8 / 512);
332
4d22de3e
DLR		 333 return 0;
334}
335
336int t3_mac_set_speed_duplex_fc(struct cmac *mac, int speed, int duplex, int fc)
337{
338 u32 val;
339 struct adapter *adap = mac->adapter;
340 unsigned int oft = mac->offset;
341
342 if (duplex >= 0 && duplex != DUPLEX_FULL)
343 return -EINVAL;
344 if (speed >= 0) {
345 if (speed == SPEED_10)
346 val = V_PORTSPEED(0);
347 else if (speed == SPEED_100)
348 val = V_PORTSPEED(1);
349 else if (speed == SPEED_1000)
350 val = V_PORTSPEED(2);
351 else if (speed == SPEED_10000)
352 val = V_PORTSPEED(3);
353 else
354 return -EINVAL;
355
356 t3_set_reg_field(adap, A_XGM_PORT_CFG + oft,
357 V_PORTSPEED(M_PORTSPEED), val);
358 }
359
4d22de3e
DLR		 360 t3_set_reg_field(adap, A_XGM_TX_CFG + oft, F_TXPAUSEEN,
361 (fc & PAUSE_RX) ? F_TXPAUSEEN : 0);
362 return 0;
363}
364
365int t3_mac_enable(struct cmac *mac, int which)
366{
367 int idx = macidx(mac);
368 struct adapter *adap = mac->adapter;
369 unsigned int oft = mac->offset;
59cf8107
DLR		 370 struct mac_stats *s = &mac->stats;
371
4d22de3e
DLR		 372 if (which & MAC_DIRECTION_TX) {
373 t3_write_reg(adap, A_XGM_TX_CTRL + oft, F_TXEN);
374 t3_write_reg(adap, A_TP_PIO_ADDR, A_TP_TX_DROP_CFG_CH0 + idx);
fc90664e 375 t3_write_reg(adap, A_TP_PIO_DATA, 0xc0ede401);
4d22de3e
DLR		 376 t3_write_reg(adap, A_TP_PIO_ADDR, A_TP_TX_DROP_MODE);
377 t3_set_reg_field(adap, A_TP_PIO_DATA, 1 << idx, 1 << idx);
fc90664e
DLR		 378
379 t3_write_reg(adap, A_TP_PIO_ADDR, A_TP_TX_DROP_CNT_CH0 + idx);
59cf8107
DLR		 380 mac->tx_mcnt = s->tx_frames;
381 mac->tx_tcnt = (G_TXDROPCNTCH0RCVD(t3_read_reg(adap,
382 A_TP_PIO_DATA)));
383 mac->tx_xcnt = (G_TXSPI4SOPCNT(t3_read_reg(adap,
384 A_XGM_TX_SPI4_SOP_EOP_CNT +
385 oft)));
386 mac->rx_mcnt = s->rx_frames;
387 mac->rx_xcnt = (G_TXSPI4SOPCNT(t3_read_reg(adap,
388 A_XGM_RX_SPI4_SOP_EOP_CNT +
389 oft)));
fc90664e
DLR		 390 mac->txen = F_TXEN;
391 mac->toggle_cnt = 0;
4d22de3e
DLR		 392 }
393 if (which & MAC_DIRECTION_RX)
394 t3_write_reg(adap, A_XGM_RX_CTRL + oft, F_RXEN);
395 return 0;
396}
397
398int t3_mac_disable(struct cmac *mac, int which)
399{
400 int idx = macidx(mac);
401 struct adapter *adap = mac->adapter;
59cf8107 402 int val;
4d22de3e
DLR		 403
404 if (which & MAC_DIRECTION_TX) {
405 t3_write_reg(adap, A_XGM_TX_CTRL + mac->offset, 0);
406 t3_write_reg(adap, A_TP_PIO_ADDR, A_TP_TX_DROP_CFG_CH0 + idx);
407 t3_write_reg(adap, A_TP_PIO_DATA, 0xc000001f);
408 t3_write_reg(adap, A_TP_PIO_ADDR, A_TP_TX_DROP_MODE);
fc90664e
DLR		 409 t3_set_reg_field(adap, A_TP_PIO_DATA, 1 << idx, 1 << idx);
410 mac->txen = 0;
4d22de3e 411 }
59cf8107
DLR		 412 if (which & MAC_DIRECTION_RX) {
413 t3_set_reg_field(mac->adapter, A_XGM_RESET_CTRL + mac->offset,
414 F_PCS_RESET_, 0);
415 msleep(100);
4d22de3e 416 t3_write_reg(adap, A_XGM_RX_CTRL + mac->offset, 0);
59cf8107
DLR		 417 val = F_MAC_RESET_;
418 if (is_10G(adap))
419 val |= F_PCS_RESET_;
420 else if (uses_xaui(adap))
421 val |= F_PCS_RESET_ | F_XG2G_RESET_;
422 else
423 val |= F_RGMII_RESET_ | F_XG2G_RESET_;
424 t3_write_reg(mac->adapter, A_XGM_RESET_CTRL + mac->offset, val);
425 }
4d22de3e
DLR		 426 return 0;
427}
428
fc90664e
DLR		 429int t3b2_mac_watchdog_task(struct cmac *mac)
430{
431 struct adapter *adap = mac->adapter;
59cf8107
DLR		 432 struct mac_stats *s = &mac->stats;
433 unsigned int tx_tcnt, tx_xcnt;
434 unsigned int tx_mcnt = s->tx_frames;
435 unsigned int rx_mcnt = s->rx_frames;
436 unsigned int rx_xcnt;
fc90664e
DLR		 437 int status;
438
59cf8107
DLR		 439 if (tx_mcnt == mac->tx_mcnt) {
440 tx_xcnt = (G_TXSPI4SOPCNT(t3_read_reg(adap,
441 A_XGM_TX_SPI4_SOP_EOP_CNT +
442 mac->offset)));
443 if (tx_xcnt == 0) {
444 t3_write_reg(adap, A_TP_PIO_ADDR,
445 A_TP_TX_DROP_CNT_CH0 + macidx(mac));
446 tx_tcnt = (G_TXDROPCNTCH0RCVD(t3_read_reg(adap,
447 A_TP_PIO_DATA)));
448 } else {
fc90664e 449 mac->toggle_cnt = 0;
59cf8107
DLR		 450 return 0;
451 }
452 } else {
453 mac->toggle_cnt = 0;
454 return 0;
455 }
456
457 if (((tx_tcnt != mac->tx_tcnt) &&
458 (tx_xcnt == 0) && (mac->tx_xcnt == 0)) ||
459 ((mac->tx_mcnt == tx_mcnt) &&
460 (tx_xcnt != 0) && (mac->tx_xcnt != 0))) {
461 if (mac->toggle_cnt > 4)
fc90664e 462 status = 2;
59cf8107 463 else
fc90664e 464 status = 1;
fc90664e
DLR		 465 } else {
466 mac->toggle_cnt = 0;
59cf8107 467 return 0;
fc90664e 468 }
fc90664e 469
59cf8107
DLR		 470 if (rx_mcnt != mac->rx_mcnt)
471 rx_xcnt = (G_TXSPI4SOPCNT(t3_read_reg(adap,
472 A_XGM_RX_SPI4_SOP_EOP_CNT +
473 mac->offset)));
474 else
475 return 0;
476
477 if (mac->rx_mcnt != s->rx_frames && rx_xcnt == 0 && mac->rx_xcnt == 0)
478 status = 2;
479
480 mac->tx_tcnt = tx_tcnt;
481 mac->tx_xcnt = tx_xcnt;
482 mac->tx_mcnt = s->tx_frames;
483 mac->rx_xcnt = rx_xcnt;
484 mac->rx_mcnt = s->rx_frames;
485 if (status == 1) {
486 t3_write_reg(adap, A_XGM_TX_CTRL + mac->offset, 0);
487 t3_read_reg(adap, A_XGM_TX_CTRL + mac->offset); /* flush */
488 t3_write_reg(adap, A_XGM_TX_CTRL + mac->offset, mac->txen);
489 t3_read_reg(adap, A_XGM_TX_CTRL + mac->offset); /* flush */
490 mac->toggle_cnt++;
491 } else if (status == 2) {
492 t3b2_mac_reset(mac);
493 mac->toggle_cnt = 0;
494 }
fc90664e
DLR		 495 return status;
496}
497
4d22de3e
DLR		 498/*
499 * This function is called periodically to accumulate the current values of the
500 * RMON counters into the port statistics. Since the packet counters are only
501 * 32 bits they can overflow in ~286 secs at 10G, so the function should be
502 * called more frequently than that. The byte counters are 45-bit wide, they
503 * would overflow in ~7.8 hours.
504 */
505const struct mac_stats *t3_mac_update_stats(struct cmac *mac)
506{
507#define RMON_READ(mac, addr) t3_read_reg(mac->adapter, addr + mac->offset)
508#define RMON_UPDATE(mac, name, reg) \
509 (mac)->stats.name += (u64)RMON_READ(mac, A_XGM_STAT_##reg)
510#define RMON_UPDATE64(mac, name, reg_lo, reg_hi) \
511 (mac)->stats.name += RMON_READ(mac, A_XGM_STAT_##reg_lo) + \
512 ((u64)RMON_READ(mac, A_XGM_STAT_##reg_hi) << 32)
513
514 u32 v, lo;
515
516 RMON_UPDATE64(mac, rx_octets, RX_BYTES_LOW, RX_BYTES_HIGH);
517 RMON_UPDATE64(mac, rx_frames, RX_FRAMES_LOW, RX_FRAMES_HIGH);
518 RMON_UPDATE(mac, rx_mcast_frames, RX_MCAST_FRAMES);
519 RMON_UPDATE(mac, rx_bcast_frames, RX_BCAST_FRAMES);
520 RMON_UPDATE(mac, rx_fcs_errs, RX_CRC_ERR_FRAMES);
521 RMON_UPDATE(mac, rx_pause, RX_PAUSE_FRAMES);
522 RMON_UPDATE(mac, rx_jabber, RX_JABBER_FRAMES);
523 RMON_UPDATE(mac, rx_short, RX_SHORT_FRAMES);
524 RMON_UPDATE(mac, rx_symbol_errs, RX_SYM_CODE_ERR_FRAMES);
525
526 RMON_UPDATE(mac, rx_too_long, RX_OVERSIZE_FRAMES);
4d22de3e 527
fc90664e
DLR		 528 v = RMON_READ(mac, A_XGM_RX_MAX_PKT_SIZE_ERR_CNT);
529 if (mac->adapter->params.rev == T3_REV_B2)
530 v &= 0x7fffffff;
531 mac->stats.rx_too_long += v;
532
4d22de3e
DLR		 533 RMON_UPDATE(mac, rx_frames_64, RX_64B_FRAMES);
534 RMON_UPDATE(mac, rx_frames_65_127, RX_65_127B_FRAMES);
535 RMON_UPDATE(mac, rx_frames_128_255, RX_128_255B_FRAMES);
536 RMON_UPDATE(mac, rx_frames_256_511, RX_256_511B_FRAMES);
537 RMON_UPDATE(mac, rx_frames_512_1023, RX_512_1023B_FRAMES);
538 RMON_UPDATE(mac, rx_frames_1024_1518, RX_1024_1518B_FRAMES);
539 RMON_UPDATE(mac, rx_frames_1519_max, RX_1519_MAXB_FRAMES);
540
541 RMON_UPDATE64(mac, tx_octets, TX_BYTE_LOW, TX_BYTE_HIGH);
542 RMON_UPDATE64(mac, tx_frames, TX_FRAME_LOW, TX_FRAME_HIGH);
543 RMON_UPDATE(mac, tx_mcast_frames, TX_MCAST);
544 RMON_UPDATE(mac, tx_bcast_frames, TX_BCAST);
545 RMON_UPDATE(mac, tx_pause, TX_PAUSE);
546 /* This counts error frames in general (bad FCS, underrun, etc). */
547 RMON_UPDATE(mac, tx_underrun, TX_ERR_FRAMES);
548
549 RMON_UPDATE(mac, tx_frames_64, TX_64B_FRAMES);
550 RMON_UPDATE(mac, tx_frames_65_127, TX_65_127B_FRAMES);
551 RMON_UPDATE(mac, tx_frames_128_255, TX_128_255B_FRAMES);
552 RMON_UPDATE(mac, tx_frames_256_511, TX_256_511B_FRAMES);
553 RMON_UPDATE(mac, tx_frames_512_1023, TX_512_1023B_FRAMES);
554 RMON_UPDATE(mac, tx_frames_1024_1518, TX_1024_1518B_FRAMES);
555 RMON_UPDATE(mac, tx_frames_1519_max, TX_1519_MAXB_FRAMES);
556
557 /* The next stat isn't clear-on-read. */
558 t3_write_reg(mac->adapter, A_TP_MIB_INDEX, mac->offset ? 51 : 50);
559 v = t3_read_reg(mac->adapter, A_TP_MIB_RDATA);
560 lo = (u32) mac->stats.rx_cong_drops;
561 mac->stats.rx_cong_drops += (u64) (v - lo);
562
563 return &mac->stats;
564}
Linux kernel - Deliverables
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