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a6286ee6 AG |
1 | /* |
2 | * DaVinci Ethernet Medium Access Controller | |
3 | * | |
4 | * DaVinci EMAC is based upon CPPI 3.0 TI DMA engine | |
5 | * | |
6 | * Copyright (C) 2009 Texas Instruments. | |
7 | * | |
8 | * --------------------------------------------------------------------------- | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; either version 2 of the License, or | |
13 | * (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
23 | * --------------------------------------------------------------------------- | |
24 | * History: | |
25 | * 0-5 A number of folks worked on this driver in bits and pieces but the major | |
26 | * contribution came from Suraj Iyer and Anant Gole | |
27 | * 6.0 Anant Gole - rewrote the driver as per Linux conventions | |
28 | * 6.1 Chaithrika U S - added support for Gigabit and RMII features, | |
29 | * PHY layer usage | |
30 | */ | |
31 | ||
a6286ee6 AG |
32 | #include <linux/module.h> |
33 | #include <linux/kernel.h> | |
34 | #include <linux/sched.h> | |
35 | #include <linux/string.h> | |
36 | #include <linux/timer.h> | |
37 | #include <linux/errno.h> | |
38 | #include <linux/in.h> | |
39 | #include <linux/ioport.h> | |
40 | #include <linux/slab.h> | |
41 | #include <linux/mm.h> | |
42 | #include <linux/interrupt.h> | |
43 | #include <linux/init.h> | |
44 | #include <linux/netdevice.h> | |
45 | #include <linux/etherdevice.h> | |
46 | #include <linux/skbuff.h> | |
47 | #include <linux/ethtool.h> | |
48 | #include <linux/highmem.h> | |
49 | #include <linux/proc_fs.h> | |
50 | #include <linux/ctype.h> | |
51 | #include <linux/version.h> | |
52 | #include <linux/spinlock.h> | |
53 | #include <linux/dma-mapping.h> | |
54 | #include <linux/clk.h> | |
55 | #include <linux/platform_device.h> | |
56 | #include <linux/semaphore.h> | |
57 | #include <linux/phy.h> | |
58 | #include <linux/bitops.h> | |
59 | #include <linux/io.h> | |
60 | #include <linux/uaccess.h> | |
8ee2bf9a | 61 | #include <linux/davinci_emac.h> |
a6286ee6 AG |
62 | |
63 | #include <asm/irq.h> | |
64 | #include <asm/page.h> | |
65 | ||
a6286ee6 AG |
66 | static int debug_level; |
67 | module_param(debug_level, int, 0); | |
68 | MODULE_PARM_DESC(debug_level, "DaVinci EMAC debug level (NETIF_MSG bits)"); | |
69 | ||
70 | /* Netif debug messages possible */ | |
71 | #define DAVINCI_EMAC_DEBUG (NETIF_MSG_DRV | \ | |
72 | NETIF_MSG_PROBE | \ | |
73 | NETIF_MSG_LINK | \ | |
74 | NETIF_MSG_TIMER | \ | |
75 | NETIF_MSG_IFDOWN | \ | |
76 | NETIF_MSG_IFUP | \ | |
77 | NETIF_MSG_RX_ERR | \ | |
78 | NETIF_MSG_TX_ERR | \ | |
79 | NETIF_MSG_TX_QUEUED | \ | |
80 | NETIF_MSG_INTR | \ | |
81 | NETIF_MSG_TX_DONE | \ | |
82 | NETIF_MSG_RX_STATUS | \ | |
83 | NETIF_MSG_PKTDATA | \ | |
84 | NETIF_MSG_HW | \ | |
85 | NETIF_MSG_WOL) | |
86 | ||
87 | /* version info */ | |
88 | #define EMAC_MAJOR_VERSION 6 | |
89 | #define EMAC_MINOR_VERSION 1 | |
90 | #define EMAC_MODULE_VERSION "6.1" | |
91 | MODULE_VERSION(EMAC_MODULE_VERSION); | |
92 | static const char emac_version_string[] = "TI DaVinci EMAC Linux v6.1"; | |
93 | ||
94 | /* Configuration items */ | |
95 | #define EMAC_DEF_PASS_CRC (0) /* Do not pass CRC upto frames */ | |
96 | #define EMAC_DEF_QOS_EN (0) /* EMAC proprietary QoS disabled */ | |
97 | #define EMAC_DEF_NO_BUFF_CHAIN (0) /* No buffer chain */ | |
98 | #define EMAC_DEF_MACCTRL_FRAME_EN (0) /* Discard Maccontrol frames */ | |
99 | #define EMAC_DEF_SHORT_FRAME_EN (0) /* Discard short frames */ | |
100 | #define EMAC_DEF_ERROR_FRAME_EN (0) /* Discard error frames */ | |
101 | #define EMAC_DEF_PROM_EN (0) /* Promiscous disabled */ | |
102 | #define EMAC_DEF_PROM_CH (0) /* Promiscous channel is 0 */ | |
103 | #define EMAC_DEF_BCAST_EN (1) /* Broadcast enabled */ | |
104 | #define EMAC_DEF_BCAST_CH (0) /* Broadcast channel is 0 */ | |
105 | #define EMAC_DEF_MCAST_EN (1) /* Multicast enabled */ | |
106 | #define EMAC_DEF_MCAST_CH (0) /* Multicast channel is 0 */ | |
107 | ||
108 | #define EMAC_DEF_TXPRIO_FIXED (1) /* TX Priority is fixed */ | |
109 | #define EMAC_DEF_TXPACING_EN (0) /* TX pacing NOT supported*/ | |
110 | ||
111 | #define EMAC_DEF_BUFFER_OFFSET (0) /* Buffer offset to DMA (future) */ | |
112 | #define EMAC_DEF_MIN_ETHPKTSIZE (60) /* Minimum ethernet pkt size */ | |
113 | #define EMAC_DEF_MAX_FRAME_SIZE (1500 + 14 + 4 + 4) | |
114 | #define EMAC_DEF_TX_CH (0) /* Default 0th channel */ | |
115 | #define EMAC_DEF_RX_CH (0) /* Default 0th channel */ | |
a6286ee6 AG |
116 | #define EMAC_DEF_MAX_TX_CH (1) /* Max TX channels configured */ |
117 | #define EMAC_DEF_MAX_RX_CH (1) /* Max RX channels configured */ | |
118 | #define EMAC_POLL_WEIGHT (64) /* Default NAPI poll weight */ | |
119 | ||
120 | /* Buffer descriptor parameters */ | |
121 | #define EMAC_DEF_TX_MAX_SERVICE (32) /* TX max service BD's */ | |
122 | #define EMAC_DEF_RX_MAX_SERVICE (64) /* should = netdev->weight */ | |
123 | ||
124 | /* EMAC register related defines */ | |
125 | #define EMAC_ALL_MULTI_REG_VALUE (0xFFFFFFFF) | |
126 | #define EMAC_NUM_MULTICAST_BITS (64) | |
127 | #define EMAC_TEARDOWN_VALUE (0xFFFFFFFC) | |
128 | #define EMAC_TX_CONTROL_TX_ENABLE_VAL (0x1) | |
129 | #define EMAC_RX_CONTROL_RX_ENABLE_VAL (0x1) | |
130 | #define EMAC_MAC_HOST_ERR_INTMASK_VAL (0x2) | |
131 | #define EMAC_RX_UNICAST_CLEAR_ALL (0xFF) | |
132 | #define EMAC_INT_MASK_CLEAR (0xFF) | |
133 | ||
134 | /* RX MBP register bit positions */ | |
135 | #define EMAC_RXMBP_PASSCRC_MASK BIT(30) | |
136 | #define EMAC_RXMBP_QOSEN_MASK BIT(29) | |
137 | #define EMAC_RXMBP_NOCHAIN_MASK BIT(28) | |
138 | #define EMAC_RXMBP_CMFEN_MASK BIT(24) | |
139 | #define EMAC_RXMBP_CSFEN_MASK BIT(23) | |
140 | #define EMAC_RXMBP_CEFEN_MASK BIT(22) | |
141 | #define EMAC_RXMBP_CAFEN_MASK BIT(21) | |
142 | #define EMAC_RXMBP_PROMCH_SHIFT (16) | |
143 | #define EMAC_RXMBP_PROMCH_MASK (0x7 << 16) | |
144 | #define EMAC_RXMBP_BROADEN_MASK BIT(13) | |
145 | #define EMAC_RXMBP_BROADCH_SHIFT (8) | |
146 | #define EMAC_RXMBP_BROADCH_MASK (0x7 << 8) | |
147 | #define EMAC_RXMBP_MULTIEN_MASK BIT(5) | |
148 | #define EMAC_RXMBP_MULTICH_SHIFT (0) | |
149 | #define EMAC_RXMBP_MULTICH_MASK (0x7) | |
150 | #define EMAC_RXMBP_CHMASK (0x7) | |
151 | ||
152 | /* EMAC register definitions/bit maps used */ | |
153 | # define EMAC_MBP_RXPROMISC (0x00200000) | |
154 | # define EMAC_MBP_PROMISCCH(ch) (((ch) & 0x7) << 16) | |
155 | # define EMAC_MBP_RXBCAST (0x00002000) | |
156 | # define EMAC_MBP_BCASTCHAN(ch) (((ch) & 0x7) << 8) | |
157 | # define EMAC_MBP_RXMCAST (0x00000020) | |
158 | # define EMAC_MBP_MCASTCHAN(ch) ((ch) & 0x7) | |
159 | ||
160 | /* EMAC mac_control register */ | |
69ef9694 | 161 | #define EMAC_MACCONTROL_TXPTYPE BIT(9) |
162 | #define EMAC_MACCONTROL_TXPACEEN BIT(6) | |
163 | #define EMAC_MACCONTROL_GMIIEN BIT(5) | |
164 | #define EMAC_MACCONTROL_GIGABITEN BIT(7) | |
165 | #define EMAC_MACCONTROL_FULLDUPLEXEN BIT(0) | |
a6286ee6 AG |
166 | #define EMAC_MACCONTROL_RMIISPEED_MASK BIT(15) |
167 | ||
168 | /* GIGABIT MODE related bits */ | |
a6286ee6 AG |
169 | #define EMAC_DM646X_MACCONTORL_GIG BIT(7) |
170 | #define EMAC_DM646X_MACCONTORL_GIGFORCE BIT(17) | |
171 | ||
172 | /* EMAC mac_status register */ | |
173 | #define EMAC_MACSTATUS_TXERRCODE_MASK (0xF00000) | |
174 | #define EMAC_MACSTATUS_TXERRCODE_SHIFT (20) | |
175 | #define EMAC_MACSTATUS_TXERRCH_MASK (0x7) | |
176 | #define EMAC_MACSTATUS_TXERRCH_SHIFT (16) | |
177 | #define EMAC_MACSTATUS_RXERRCODE_MASK (0xF000) | |
178 | #define EMAC_MACSTATUS_RXERRCODE_SHIFT (12) | |
179 | #define EMAC_MACSTATUS_RXERRCH_MASK (0x7) | |
180 | #define EMAC_MACSTATUS_RXERRCH_SHIFT (8) | |
181 | ||
182 | /* EMAC RX register masks */ | |
183 | #define EMAC_RX_MAX_LEN_MASK (0xFFFF) | |
184 | #define EMAC_RX_BUFFER_OFFSET_MASK (0xFFFF) | |
185 | ||
186 | /* MAC_IN_VECTOR (0x180) register bit fields */ | |
69ef9694 | 187 | #define EMAC_DM644X_MAC_IN_VECTOR_HOST_INT BIT(17) |
188 | #define EMAC_DM644X_MAC_IN_VECTOR_STATPEND_INT BIT(16) | |
189 | #define EMAC_DM644X_MAC_IN_VECTOR_RX_INT_VEC BIT(8) | |
190 | #define EMAC_DM644X_MAC_IN_VECTOR_TX_INT_VEC BIT(0) | |
a6286ee6 AG |
191 | |
192 | /** NOTE:: For DM646x the IN_VECTOR has changed */ | |
193 | #define EMAC_DM646X_MAC_IN_VECTOR_RX_INT_VEC BIT(EMAC_DEF_RX_CH) | |
194 | #define EMAC_DM646X_MAC_IN_VECTOR_TX_INT_VEC BIT(16 + EMAC_DEF_TX_CH) | |
43c2ed8e S |
195 | #define EMAC_DM646X_MAC_IN_VECTOR_HOST_INT BIT(26) |
196 | #define EMAC_DM646X_MAC_IN_VECTOR_STATPEND_INT BIT(27) | |
197 | ||
a6286ee6 AG |
198 | /* CPPI bit positions */ |
199 | #define EMAC_CPPI_SOP_BIT BIT(31) | |
200 | #define EMAC_CPPI_EOP_BIT BIT(30) | |
201 | #define EMAC_CPPI_OWNERSHIP_BIT BIT(29) | |
202 | #define EMAC_CPPI_EOQ_BIT BIT(28) | |
203 | #define EMAC_CPPI_TEARDOWN_COMPLETE_BIT BIT(27) | |
204 | #define EMAC_CPPI_PASS_CRC_BIT BIT(26) | |
205 | #define EMAC_RX_BD_BUF_SIZE (0xFFFF) | |
206 | #define EMAC_BD_LENGTH_FOR_CACHE (16) /* only CPPI bytes */ | |
207 | #define EMAC_RX_BD_PKT_LENGTH_MASK (0xFFFF) | |
208 | ||
209 | /* Max hardware defines */ | |
210 | #define EMAC_MAX_TXRX_CHANNELS (8) /* Max hardware channels */ | |
211 | #define EMAC_DEF_MAX_MULTICAST_ADDRESSES (64) /* Max mcast addr's */ | |
212 | ||
213 | /* EMAC Peripheral Device Register Memory Layout structure */ | |
214 | #define EMAC_TXIDVER 0x0 | |
215 | #define EMAC_TXCONTROL 0x4 | |
216 | #define EMAC_TXTEARDOWN 0x8 | |
217 | #define EMAC_RXIDVER 0x10 | |
218 | #define EMAC_RXCONTROL 0x14 | |
219 | #define EMAC_RXTEARDOWN 0x18 | |
220 | #define EMAC_TXINTSTATRAW 0x80 | |
221 | #define EMAC_TXINTSTATMASKED 0x84 | |
222 | #define EMAC_TXINTMASKSET 0x88 | |
223 | #define EMAC_TXINTMASKCLEAR 0x8C | |
224 | #define EMAC_MACINVECTOR 0x90 | |
225 | ||
226 | #define EMAC_DM646X_MACEOIVECTOR 0x94 | |
227 | ||
228 | #define EMAC_RXINTSTATRAW 0xA0 | |
229 | #define EMAC_RXINTSTATMASKED 0xA4 | |
230 | #define EMAC_RXINTMASKSET 0xA8 | |
231 | #define EMAC_RXINTMASKCLEAR 0xAC | |
232 | #define EMAC_MACINTSTATRAW 0xB0 | |
233 | #define EMAC_MACINTSTATMASKED 0xB4 | |
234 | #define EMAC_MACINTMASKSET 0xB8 | |
235 | #define EMAC_MACINTMASKCLEAR 0xBC | |
236 | ||
237 | #define EMAC_RXMBPENABLE 0x100 | |
238 | #define EMAC_RXUNICASTSET 0x104 | |
239 | #define EMAC_RXUNICASTCLEAR 0x108 | |
240 | #define EMAC_RXMAXLEN 0x10C | |
241 | #define EMAC_RXBUFFEROFFSET 0x110 | |
242 | #define EMAC_RXFILTERLOWTHRESH 0x114 | |
243 | ||
244 | #define EMAC_MACCONTROL 0x160 | |
245 | #define EMAC_MACSTATUS 0x164 | |
246 | #define EMAC_EMCONTROL 0x168 | |
247 | #define EMAC_FIFOCONTROL 0x16C | |
248 | #define EMAC_MACCONFIG 0x170 | |
249 | #define EMAC_SOFTRESET 0x174 | |
250 | #define EMAC_MACSRCADDRLO 0x1D0 | |
251 | #define EMAC_MACSRCADDRHI 0x1D4 | |
252 | #define EMAC_MACHASH1 0x1D8 | |
253 | #define EMAC_MACHASH2 0x1DC | |
254 | #define EMAC_MACADDRLO 0x500 | |
255 | #define EMAC_MACADDRHI 0x504 | |
256 | #define EMAC_MACINDEX 0x508 | |
257 | ||
258 | /* EMAC HDP and Completion registors */ | |
259 | #define EMAC_TXHDP(ch) (0x600 + (ch * 4)) | |
260 | #define EMAC_RXHDP(ch) (0x620 + (ch * 4)) | |
261 | #define EMAC_TXCP(ch) (0x640 + (ch * 4)) | |
262 | #define EMAC_RXCP(ch) (0x660 + (ch * 4)) | |
263 | ||
264 | /* EMAC statistics registers */ | |
265 | #define EMAC_RXGOODFRAMES 0x200 | |
266 | #define EMAC_RXBCASTFRAMES 0x204 | |
267 | #define EMAC_RXMCASTFRAMES 0x208 | |
268 | #define EMAC_RXPAUSEFRAMES 0x20C | |
269 | #define EMAC_RXCRCERRORS 0x210 | |
270 | #define EMAC_RXALIGNCODEERRORS 0x214 | |
271 | #define EMAC_RXOVERSIZED 0x218 | |
272 | #define EMAC_RXJABBER 0x21C | |
273 | #define EMAC_RXUNDERSIZED 0x220 | |
274 | #define EMAC_RXFRAGMENTS 0x224 | |
275 | #define EMAC_RXFILTERED 0x228 | |
276 | #define EMAC_RXQOSFILTERED 0x22C | |
277 | #define EMAC_RXOCTETS 0x230 | |
278 | #define EMAC_TXGOODFRAMES 0x234 | |
279 | #define EMAC_TXBCASTFRAMES 0x238 | |
280 | #define EMAC_TXMCASTFRAMES 0x23C | |
281 | #define EMAC_TXPAUSEFRAMES 0x240 | |
282 | #define EMAC_TXDEFERRED 0x244 | |
283 | #define EMAC_TXCOLLISION 0x248 | |
284 | #define EMAC_TXSINGLECOLL 0x24C | |
285 | #define EMAC_TXMULTICOLL 0x250 | |
286 | #define EMAC_TXEXCESSIVECOLL 0x254 | |
287 | #define EMAC_TXLATECOLL 0x258 | |
288 | #define EMAC_TXUNDERRUN 0x25C | |
289 | #define EMAC_TXCARRIERSENSE 0x260 | |
290 | #define EMAC_TXOCTETS 0x264 | |
291 | #define EMAC_NETOCTETS 0x280 | |
292 | #define EMAC_RXSOFOVERRUNS 0x284 | |
293 | #define EMAC_RXMOFOVERRUNS 0x288 | |
294 | #define EMAC_RXDMAOVERRUNS 0x28C | |
295 | ||
296 | /* EMAC DM644x control registers */ | |
297 | #define EMAC_CTRL_EWCTL (0x4) | |
298 | #define EMAC_CTRL_EWINTTCNT (0x8) | |
299 | ||
84da2658 S |
300 | /* EMAC DM644x control module masks */ |
301 | #define EMAC_DM644X_EWINTCNT_MASK 0x1FFFF | |
302 | #define EMAC_DM644X_INTMIN_INTVL 0x1 | |
303 | #define EMAC_DM644X_INTMAX_INTVL (EMAC_DM644X_EWINTCNT_MASK) | |
304 | ||
a6286ee6 | 305 | /* EMAC DM646X control module registers */ |
84da2658 S |
306 | #define EMAC_DM646X_CMINTCTRL 0x0C |
307 | #define EMAC_DM646X_CMRXINTEN 0x14 | |
308 | #define EMAC_DM646X_CMTXINTEN 0x18 | |
309 | #define EMAC_DM646X_CMRXINTMAX 0x70 | |
310 | #define EMAC_DM646X_CMTXINTMAX 0x74 | |
311 | ||
312 | /* EMAC DM646X control module masks */ | |
313 | #define EMAC_DM646X_INTPACEEN (0x3 << 16) | |
314 | #define EMAC_DM646X_INTPRESCALE_MASK (0x7FF << 0) | |
315 | #define EMAC_DM646X_CMINTMAX_CNT 63 | |
316 | #define EMAC_DM646X_CMINTMIN_CNT 2 | |
317 | #define EMAC_DM646X_CMINTMAX_INTVL (1000 / EMAC_DM646X_CMINTMIN_CNT) | |
318 | #define EMAC_DM646X_CMINTMIN_INTVL ((1000 / EMAC_DM646X_CMINTMAX_CNT) + 1) | |
319 | ||
a6286ee6 AG |
320 | |
321 | /* EMAC EOI codes for C0 */ | |
322 | #define EMAC_DM646X_MAC_EOI_C0_RXEN (0x01) | |
323 | #define EMAC_DM646X_MAC_EOI_C0_TXEN (0x02) | |
324 | ||
0fe7463a S |
325 | /* EMAC Stats Clear Mask */ |
326 | #define EMAC_STATS_CLR_MASK (0xFFFFFFFF) | |
327 | ||
a6286ee6 AG |
328 | /** net_buf_obj: EMAC network bufferdata structure |
329 | * | |
330 | * EMAC network buffer data structure | |
331 | */ | |
332 | struct emac_netbufobj { | |
333 | void *buf_token; | |
334 | char *data_ptr; | |
335 | int length; | |
336 | }; | |
337 | ||
338 | /** net_pkt_obj: EMAC network packet data structure | |
339 | * | |
340 | * EMAC network packet data structure - supports buffer list (for future) | |
341 | */ | |
342 | struct emac_netpktobj { | |
343 | void *pkt_token; /* data token may hold tx/rx chan id */ | |
344 | struct emac_netbufobj *buf_list; /* array of network buffer objects */ | |
345 | int num_bufs; | |
346 | int pkt_length; | |
347 | }; | |
348 | ||
349 | /** emac_tx_bd: EMAC TX Buffer descriptor data structure | |
350 | * | |
351 | * EMAC TX Buffer descriptor data structure | |
352 | */ | |
353 | struct emac_tx_bd { | |
354 | int h_next; | |
355 | int buff_ptr; | |
356 | int off_b_len; | |
357 | int mode; /* SOP, EOP, ownership, EOQ, teardown,Qstarv, length */ | |
358 | struct emac_tx_bd __iomem *next; | |
359 | void *buf_token; | |
360 | }; | |
361 | ||
362 | /** emac_txch: EMAC TX Channel data structure | |
363 | * | |
364 | * EMAC TX Channel data structure | |
365 | */ | |
366 | struct emac_txch { | |
367 | /* Config related */ | |
368 | u32 num_bd; | |
369 | u32 service_max; | |
370 | ||
371 | /* CPPI specific */ | |
372 | u32 alloc_size; | |
373 | void __iomem *bd_mem; | |
374 | struct emac_tx_bd __iomem *bd_pool_head; | |
375 | struct emac_tx_bd __iomem *active_queue_head; | |
376 | struct emac_tx_bd __iomem *active_queue_tail; | |
377 | struct emac_tx_bd __iomem *last_hw_bdprocessed; | |
378 | u32 queue_active; | |
379 | u32 teardown_pending; | |
380 | u32 *tx_complete; | |
381 | ||
382 | /** statistics */ | |
383 | u32 proc_count; /* TX: # of times emac_tx_bdproc is called */ | |
384 | u32 mis_queued_packets; | |
385 | u32 queue_reinit; | |
386 | u32 end_of_queue_add; | |
387 | u32 out_of_tx_bd; | |
388 | u32 no_active_pkts; /* IRQ when there were no packets to process */ | |
389 | u32 active_queue_count; | |
390 | }; | |
391 | ||
392 | /** emac_rx_bd: EMAC RX Buffer descriptor data structure | |
393 | * | |
394 | * EMAC RX Buffer descriptor data structure | |
395 | */ | |
396 | struct emac_rx_bd { | |
397 | int h_next; | |
398 | int buff_ptr; | |
399 | int off_b_len; | |
400 | int mode; | |
401 | struct emac_rx_bd __iomem *next; | |
402 | void *data_ptr; | |
403 | void *buf_token; | |
404 | }; | |
405 | ||
406 | /** emac_rxch: EMAC RX Channel data structure | |
407 | * | |
408 | * EMAC RX Channel data structure | |
409 | */ | |
410 | struct emac_rxch { | |
411 | /* configuration info */ | |
412 | u32 num_bd; | |
413 | u32 service_max; | |
414 | u32 buf_size; | |
415 | char mac_addr[6]; | |
416 | ||
417 | /** CPPI specific */ | |
418 | u32 alloc_size; | |
419 | void __iomem *bd_mem; | |
420 | struct emac_rx_bd __iomem *bd_pool_head; | |
421 | struct emac_rx_bd __iomem *active_queue_head; | |
422 | struct emac_rx_bd __iomem *active_queue_tail; | |
423 | u32 queue_active; | |
424 | u32 teardown_pending; | |
425 | ||
426 | /* packet and buffer objects */ | |
427 | struct emac_netpktobj pkt_queue; | |
428 | struct emac_netbufobj buf_queue; | |
429 | ||
430 | /** statistics */ | |
431 | u32 proc_count; /* number of times emac_rx_bdproc is called */ | |
432 | u32 processed_bd; | |
433 | u32 recycled_bd; | |
434 | u32 out_of_rx_bd; | |
435 | u32 out_of_rx_buffers; | |
436 | u32 queue_reinit; | |
437 | u32 end_of_queue_add; | |
438 | u32 end_of_queue; | |
439 | u32 mis_queued_packets; | |
440 | }; | |
441 | ||
442 | /* emac_priv: EMAC private data structure | |
443 | * | |
444 | * EMAC adapter private data structure | |
445 | */ | |
446 | struct emac_priv { | |
447 | u32 msg_enable; | |
448 | struct net_device *ndev; | |
449 | struct platform_device *pdev; | |
450 | struct napi_struct napi; | |
451 | char mac_addr[6]; | |
452 | spinlock_t tx_lock; | |
453 | spinlock_t rx_lock; | |
454 | void __iomem *remap_addr; | |
455 | u32 emac_base_phys; | |
456 | void __iomem *emac_base; | |
457 | void __iomem *ctrl_base; | |
458 | void __iomem *emac_ctrl_ram; | |
459 | u32 ctrl_ram_size; | |
ad021ae8 | 460 | u32 hw_ram_addr; |
a6286ee6 AG |
461 | struct emac_txch *txch[EMAC_DEF_MAX_TX_CH]; |
462 | struct emac_rxch *rxch[EMAC_DEF_MAX_RX_CH]; | |
463 | u32 link; /* 1=link on, 0=link off */ | |
464 | u32 speed; /* 0=Auto Neg, 1=No PHY, 10,100, 1000 - mbps */ | |
465 | u32 duplex; /* Link duplex: 0=Half, 1=Full */ | |
466 | u32 rx_buf_size; | |
467 | u32 isr_count; | |
84da2658 S |
468 | u32 coal_intvl; |
469 | u32 bus_freq_mhz; | |
a6286ee6 AG |
470 | u8 rmii_en; |
471 | u8 version; | |
a6286ee6 AG |
472 | u32 mac_hash1; |
473 | u32 mac_hash2; | |
474 | u32 multicast_hash_cnt[EMAC_NUM_MULTICAST_BITS]; | |
475 | u32 rx_addr_type; | |
5d69e007 | 476 | const char *phy_id; |
a6286ee6 AG |
477 | struct phy_device *phydev; |
478 | spinlock_t lock; | |
01a9af36 S |
479 | /*platform specific members*/ |
480 | void (*int_enable) (void); | |
481 | void (*int_disable) (void); | |
a6286ee6 AG |
482 | }; |
483 | ||
484 | /* clock frequency for EMAC */ | |
485 | static struct clk *emac_clk; | |
486 | static unsigned long emac_bus_frequency; | |
a6286ee6 | 487 | |
ad021ae8 S |
488 | #define emac_virt_to_phys(addr, priv) \ |
489 | (((u32 __force)(addr) - (u32 __force)(priv->emac_ctrl_ram)) \ | |
490 | + priv->hw_ram_addr) | |
a6286ee6 AG |
491 | |
492 | /* Cache macros - Packet buffers would be from skb pool which is cached */ | |
493 | #define EMAC_VIRT_NOCACHE(addr) (addr) | |
a6286ee6 AG |
494 | |
495 | /* DM644x does not have BD's in cached memory - so no cache functions */ | |
496 | #define BD_CACHE_INVALIDATE(addr, size) | |
497 | #define BD_CACHE_WRITEBACK(addr, size) | |
498 | #define BD_CACHE_WRITEBACK_INVALIDATE(addr, size) | |
499 | ||
500 | /* EMAC TX Host Error description strings */ | |
501 | static char *emac_txhost_errcodes[16] = { | |
502 | "No error", "SOP error", "Ownership bit not set in SOP buffer", | |
503 | "Zero Next Buffer Descriptor Pointer Without EOP", | |
504 | "Zero Buffer Pointer", "Zero Buffer Length", "Packet Length Error", | |
505 | "Reserved", "Reserved", "Reserved", "Reserved", "Reserved", | |
506 | "Reserved", "Reserved", "Reserved", "Reserved" | |
507 | }; | |
508 | ||
509 | /* EMAC RX Host Error description strings */ | |
510 | static char *emac_rxhost_errcodes[16] = { | |
511 | "No error", "Reserved", "Ownership bit not set in input buffer", | |
512 | "Reserved", "Zero Buffer Pointer", "Reserved", "Reserved", | |
513 | "Reserved", "Reserved", "Reserved", "Reserved", "Reserved", | |
514 | "Reserved", "Reserved", "Reserved", "Reserved" | |
515 | }; | |
516 | ||
517 | /* Helper macros */ | |
518 | #define emac_read(reg) ioread32(priv->emac_base + (reg)) | |
519 | #define emac_write(reg, val) iowrite32(val, priv->emac_base + (reg)) | |
520 | ||
521 | #define emac_ctrl_read(reg) ioread32((priv->ctrl_base + (reg))) | |
522 | #define emac_ctrl_write(reg, val) iowrite32(val, (priv->ctrl_base + (reg))) | |
523 | ||
a6286ee6 AG |
524 | /** |
525 | * emac_dump_regs: Dump important EMAC registers to debug terminal | |
526 | * @priv: The DaVinci EMAC private adapter structure | |
527 | * | |
528 | * Executes ethtool set cmd & sets phy mode | |
529 | * | |
530 | */ | |
531 | static void emac_dump_regs(struct emac_priv *priv) | |
532 | { | |
533 | struct device *emac_dev = &priv->ndev->dev; | |
534 | ||
535 | /* Print important registers in EMAC */ | |
536 | dev_info(emac_dev, "EMAC Basic registers\n"); | |
e994762f S |
537 | if (priv->version == EMAC_VERSION_1) { |
538 | dev_info(emac_dev, "EMAC: EWCTL: %08X, EWINTTCNT: %08X\n", | |
539 | emac_ctrl_read(EMAC_CTRL_EWCTL), | |
540 | emac_ctrl_read(EMAC_CTRL_EWINTTCNT)); | |
541 | } | |
a6286ee6 AG |
542 | dev_info(emac_dev, "EMAC: TXID: %08X %s, RXID: %08X %s\n", |
543 | emac_read(EMAC_TXIDVER), | |
544 | ((emac_read(EMAC_TXCONTROL)) ? "enabled" : "disabled"), | |
545 | emac_read(EMAC_RXIDVER), | |
546 | ((emac_read(EMAC_RXCONTROL)) ? "enabled" : "disabled")); | |
547 | dev_info(emac_dev, "EMAC: TXIntRaw:%08X, TxIntMasked: %08X, "\ | |
548 | "TxIntMasSet: %08X\n", emac_read(EMAC_TXINTSTATRAW), | |
549 | emac_read(EMAC_TXINTSTATMASKED), emac_read(EMAC_TXINTMASKSET)); | |
550 | dev_info(emac_dev, "EMAC: RXIntRaw:%08X, RxIntMasked: %08X, "\ | |
551 | "RxIntMasSet: %08X\n", emac_read(EMAC_RXINTSTATRAW), | |
552 | emac_read(EMAC_RXINTSTATMASKED), emac_read(EMAC_RXINTMASKSET)); | |
553 | dev_info(emac_dev, "EMAC: MacIntRaw:%08X, MacIntMasked: %08X, "\ | |
554 | "MacInVector=%08X\n", emac_read(EMAC_MACINTSTATRAW), | |
555 | emac_read(EMAC_MACINTSTATMASKED), emac_read(EMAC_MACINVECTOR)); | |
556 | dev_info(emac_dev, "EMAC: EmuControl:%08X, FifoControl: %08X\n", | |
557 | emac_read(EMAC_EMCONTROL), emac_read(EMAC_FIFOCONTROL)); | |
558 | dev_info(emac_dev, "EMAC: MBPEnable:%08X, RXUnicastSet: %08X, "\ | |
559 | "RXMaxLen=%08X\n", emac_read(EMAC_RXMBPENABLE), | |
560 | emac_read(EMAC_RXUNICASTSET), emac_read(EMAC_RXMAXLEN)); | |
561 | dev_info(emac_dev, "EMAC: MacControl:%08X, MacStatus: %08X, "\ | |
562 | "MacConfig=%08X\n", emac_read(EMAC_MACCONTROL), | |
563 | emac_read(EMAC_MACSTATUS), emac_read(EMAC_MACCONFIG)); | |
564 | dev_info(emac_dev, "EMAC: TXHDP[0]:%08X, RXHDP[0]: %08X\n", | |
565 | emac_read(EMAC_TXHDP(0)), emac_read(EMAC_RXHDP(0))); | |
566 | dev_info(emac_dev, "EMAC Statistics\n"); | |
567 | dev_info(emac_dev, "EMAC: rx_good_frames:%d\n", | |
568 | emac_read(EMAC_RXGOODFRAMES)); | |
569 | dev_info(emac_dev, "EMAC: rx_broadcast_frames:%d\n", | |
570 | emac_read(EMAC_RXBCASTFRAMES)); | |
571 | dev_info(emac_dev, "EMAC: rx_multicast_frames:%d\n", | |
572 | emac_read(EMAC_RXMCASTFRAMES)); | |
573 | dev_info(emac_dev, "EMAC: rx_pause_frames:%d\n", | |
574 | emac_read(EMAC_RXPAUSEFRAMES)); | |
575 | dev_info(emac_dev, "EMAC: rx_crcerrors:%d\n", | |
576 | emac_read(EMAC_RXCRCERRORS)); | |
577 | dev_info(emac_dev, "EMAC: rx_align_code_errors:%d\n", | |
578 | emac_read(EMAC_RXALIGNCODEERRORS)); | |
579 | dev_info(emac_dev, "EMAC: rx_oversized_frames:%d\n", | |
580 | emac_read(EMAC_RXOVERSIZED)); | |
581 | dev_info(emac_dev, "EMAC: rx_jabber_frames:%d\n", | |
582 | emac_read(EMAC_RXJABBER)); | |
583 | dev_info(emac_dev, "EMAC: rx_undersized_frames:%d\n", | |
584 | emac_read(EMAC_RXUNDERSIZED)); | |
585 | dev_info(emac_dev, "EMAC: rx_fragments:%d\n", | |
586 | emac_read(EMAC_RXFRAGMENTS)); | |
587 | dev_info(emac_dev, "EMAC: rx_filtered_frames:%d\n", | |
588 | emac_read(EMAC_RXFILTERED)); | |
589 | dev_info(emac_dev, "EMAC: rx_qos_filtered_frames:%d\n", | |
590 | emac_read(EMAC_RXQOSFILTERED)); | |
591 | dev_info(emac_dev, "EMAC: rx_octets:%d\n", | |
592 | emac_read(EMAC_RXOCTETS)); | |
593 | dev_info(emac_dev, "EMAC: tx_goodframes:%d\n", | |
594 | emac_read(EMAC_TXGOODFRAMES)); | |
595 | dev_info(emac_dev, "EMAC: tx_bcastframes:%d\n", | |
596 | emac_read(EMAC_TXBCASTFRAMES)); | |
597 | dev_info(emac_dev, "EMAC: tx_mcastframes:%d\n", | |
598 | emac_read(EMAC_TXMCASTFRAMES)); | |
599 | dev_info(emac_dev, "EMAC: tx_pause_frames:%d\n", | |
600 | emac_read(EMAC_TXPAUSEFRAMES)); | |
601 | dev_info(emac_dev, "EMAC: tx_deferred_frames:%d\n", | |
602 | emac_read(EMAC_TXDEFERRED)); | |
603 | dev_info(emac_dev, "EMAC: tx_collision_frames:%d\n", | |
604 | emac_read(EMAC_TXCOLLISION)); | |
605 | dev_info(emac_dev, "EMAC: tx_single_coll_frames:%d\n", | |
606 | emac_read(EMAC_TXSINGLECOLL)); | |
607 | dev_info(emac_dev, "EMAC: tx_mult_coll_frames:%d\n", | |
608 | emac_read(EMAC_TXMULTICOLL)); | |
609 | dev_info(emac_dev, "EMAC: tx_excessive_collisions:%d\n", | |
610 | emac_read(EMAC_TXEXCESSIVECOLL)); | |
611 | dev_info(emac_dev, "EMAC: tx_late_collisions:%d\n", | |
612 | emac_read(EMAC_TXLATECOLL)); | |
613 | dev_info(emac_dev, "EMAC: tx_underrun:%d\n", | |
614 | emac_read(EMAC_TXUNDERRUN)); | |
615 | dev_info(emac_dev, "EMAC: tx_carrier_sense_errors:%d\n", | |
616 | emac_read(EMAC_TXCARRIERSENSE)); | |
617 | dev_info(emac_dev, "EMAC: tx_octets:%d\n", | |
618 | emac_read(EMAC_TXOCTETS)); | |
619 | dev_info(emac_dev, "EMAC: net_octets:%d\n", | |
620 | emac_read(EMAC_NETOCTETS)); | |
621 | dev_info(emac_dev, "EMAC: rx_sof_overruns:%d\n", | |
622 | emac_read(EMAC_RXSOFOVERRUNS)); | |
623 | dev_info(emac_dev, "EMAC: rx_mof_overruns:%d\n", | |
624 | emac_read(EMAC_RXMOFOVERRUNS)); | |
625 | dev_info(emac_dev, "EMAC: rx_dma_overruns:%d\n", | |
626 | emac_read(EMAC_RXDMAOVERRUNS)); | |
627 | } | |
628 | ||
a6286ee6 AG |
629 | /** |
630 | * emac_get_drvinfo: Get EMAC driver information | |
631 | * @ndev: The DaVinci EMAC network adapter | |
632 | * @info: ethtool info structure containing name and version | |
633 | * | |
634 | * Returns EMAC driver information (name and version) | |
635 | * | |
636 | */ | |
637 | static void emac_get_drvinfo(struct net_device *ndev, | |
638 | struct ethtool_drvinfo *info) | |
639 | { | |
640 | strcpy(info->driver, emac_version_string); | |
641 | strcpy(info->version, EMAC_MODULE_VERSION); | |
642 | } | |
643 | ||
644 | /** | |
645 | * emac_get_settings: Get EMAC settings | |
646 | * @ndev: The DaVinci EMAC network adapter | |
647 | * @ecmd: ethtool command | |
648 | * | |
649 | * Executes ethool get command | |
650 | * | |
651 | */ | |
652 | static int emac_get_settings(struct net_device *ndev, | |
653 | struct ethtool_cmd *ecmd) | |
654 | { | |
655 | struct emac_priv *priv = netdev_priv(ndev); | |
5d69e007 | 656 | if (priv->phydev) |
a6286ee6 AG |
657 | return phy_ethtool_gset(priv->phydev, ecmd); |
658 | else | |
659 | return -EOPNOTSUPP; | |
660 | ||
661 | } | |
662 | ||
663 | /** | |
664 | * emac_set_settings: Set EMAC settings | |
665 | * @ndev: The DaVinci EMAC network adapter | |
666 | * @ecmd: ethtool command | |
667 | * | |
668 | * Executes ethool set command | |
669 | * | |
670 | */ | |
671 | static int emac_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd) | |
672 | { | |
673 | struct emac_priv *priv = netdev_priv(ndev); | |
5d69e007 | 674 | if (priv->phydev) |
a6286ee6 AG |
675 | return phy_ethtool_sset(priv->phydev, ecmd); |
676 | else | |
677 | return -EOPNOTSUPP; | |
678 | ||
679 | } | |
680 | ||
84da2658 S |
681 | /** |
682 | * emac_get_coalesce : Get interrupt coalesce settings for this device | |
683 | * @ndev : The DaVinci EMAC network adapter | |
684 | * @coal : ethtool coalesce settings structure | |
685 | * | |
686 | * Fetch the current interrupt coalesce settings | |
687 | * | |
688 | */ | |
689 | static int emac_get_coalesce(struct net_device *ndev, | |
690 | struct ethtool_coalesce *coal) | |
691 | { | |
692 | struct emac_priv *priv = netdev_priv(ndev); | |
693 | ||
694 | coal->rx_coalesce_usecs = priv->coal_intvl; | |
695 | return 0; | |
696 | ||
697 | } | |
698 | ||
699 | /** | |
700 | * emac_set_coalesce : Set interrupt coalesce settings for this device | |
701 | * @ndev : The DaVinci EMAC network adapter | |
702 | * @coal : ethtool coalesce settings structure | |
703 | * | |
704 | * Set interrupt coalesce parameters | |
705 | * | |
706 | */ | |
707 | static int emac_set_coalesce(struct net_device *ndev, | |
708 | struct ethtool_coalesce *coal) | |
709 | { | |
710 | struct emac_priv *priv = netdev_priv(ndev); | |
711 | u32 int_ctrl, num_interrupts = 0; | |
712 | u32 prescale = 0, addnl_dvdr = 1, coal_intvl = 0; | |
713 | ||
714 | if (!coal->rx_coalesce_usecs) | |
715 | return -EINVAL; | |
716 | ||
717 | coal_intvl = coal->rx_coalesce_usecs; | |
718 | ||
719 | switch (priv->version) { | |
720 | case EMAC_VERSION_2: | |
721 | int_ctrl = emac_ctrl_read(EMAC_DM646X_CMINTCTRL); | |
722 | prescale = priv->bus_freq_mhz * 4; | |
723 | ||
724 | if (coal_intvl < EMAC_DM646X_CMINTMIN_INTVL) | |
725 | coal_intvl = EMAC_DM646X_CMINTMIN_INTVL; | |
726 | ||
727 | if (coal_intvl > EMAC_DM646X_CMINTMAX_INTVL) { | |
728 | /* | |
729 | * Interrupt pacer works with 4us Pulse, we can | |
730 | * throttle further by dilating the 4us pulse. | |
731 | */ | |
732 | addnl_dvdr = EMAC_DM646X_INTPRESCALE_MASK / prescale; | |
733 | ||
734 | if (addnl_dvdr > 1) { | |
735 | prescale *= addnl_dvdr; | |
736 | if (coal_intvl > (EMAC_DM646X_CMINTMAX_INTVL | |
737 | * addnl_dvdr)) | |
738 | coal_intvl = (EMAC_DM646X_CMINTMAX_INTVL | |
739 | * addnl_dvdr); | |
740 | } else { | |
741 | addnl_dvdr = 1; | |
742 | coal_intvl = EMAC_DM646X_CMINTMAX_INTVL; | |
743 | } | |
744 | } | |
745 | ||
746 | num_interrupts = (1000 * addnl_dvdr) / coal_intvl; | |
747 | ||
748 | int_ctrl |= EMAC_DM646X_INTPACEEN; | |
749 | int_ctrl &= (~EMAC_DM646X_INTPRESCALE_MASK); | |
750 | int_ctrl |= (prescale & EMAC_DM646X_INTPRESCALE_MASK); | |
751 | emac_ctrl_write(EMAC_DM646X_CMINTCTRL, int_ctrl); | |
752 | ||
753 | emac_ctrl_write(EMAC_DM646X_CMRXINTMAX, num_interrupts); | |
754 | emac_ctrl_write(EMAC_DM646X_CMTXINTMAX, num_interrupts); | |
755 | ||
756 | break; | |
757 | default: | |
758 | int_ctrl = emac_ctrl_read(EMAC_CTRL_EWINTTCNT); | |
759 | int_ctrl &= (~EMAC_DM644X_EWINTCNT_MASK); | |
760 | prescale = coal_intvl * priv->bus_freq_mhz; | |
761 | if (prescale > EMAC_DM644X_EWINTCNT_MASK) { | |
762 | prescale = EMAC_DM644X_EWINTCNT_MASK; | |
763 | coal_intvl = prescale / priv->bus_freq_mhz; | |
764 | } | |
765 | emac_ctrl_write(EMAC_CTRL_EWINTTCNT, (int_ctrl | prescale)); | |
766 | ||
767 | break; | |
768 | } | |
769 | ||
770 | printk(KERN_INFO"Set coalesce to %d usecs.\n", coal_intvl); | |
771 | priv->coal_intvl = coal_intvl; | |
772 | ||
773 | return 0; | |
774 | ||
775 | } | |
776 | ||
777 | ||
a6286ee6 AG |
778 | /** |
779 | * ethtool_ops: DaVinci EMAC Ethtool structure | |
780 | * | |
781 | * Ethtool support for EMAC adapter | |
782 | * | |
783 | */ | |
784 | static const struct ethtool_ops ethtool_ops = { | |
785 | .get_drvinfo = emac_get_drvinfo, | |
786 | .get_settings = emac_get_settings, | |
787 | .set_settings = emac_set_settings, | |
788 | .get_link = ethtool_op_get_link, | |
84da2658 S |
789 | .get_coalesce = emac_get_coalesce, |
790 | .set_coalesce = emac_set_coalesce, | |
a6286ee6 AG |
791 | }; |
792 | ||
793 | /** | |
794 | * emac_update_phystatus: Update Phy status | |
795 | * @priv: The DaVinci EMAC private adapter structure | |
796 | * | |
797 | * Updates phy status and takes action for network queue if required | |
798 | * based upon link status | |
799 | * | |
800 | */ | |
801 | static void emac_update_phystatus(struct emac_priv *priv) | |
802 | { | |
803 | u32 mac_control; | |
804 | u32 new_duplex; | |
805 | u32 cur_duplex; | |
806 | struct net_device *ndev = priv->ndev; | |
807 | ||
808 | mac_control = emac_read(EMAC_MACCONTROL); | |
809 | cur_duplex = (mac_control & EMAC_MACCONTROL_FULLDUPLEXEN) ? | |
810 | DUPLEX_FULL : DUPLEX_HALF; | |
5d69e007 | 811 | if (priv->phydev) |
a6286ee6 AG |
812 | new_duplex = priv->phydev->duplex; |
813 | else | |
814 | new_duplex = DUPLEX_FULL; | |
815 | ||
816 | /* We get called only if link has changed (speed/duplex/status) */ | |
817 | if ((priv->link) && (new_duplex != cur_duplex)) { | |
818 | priv->duplex = new_duplex; | |
819 | if (DUPLEX_FULL == priv->duplex) | |
820 | mac_control |= (EMAC_MACCONTROL_FULLDUPLEXEN); | |
821 | else | |
822 | mac_control &= ~(EMAC_MACCONTROL_FULLDUPLEXEN); | |
823 | } | |
824 | ||
825 | if (priv->speed == SPEED_1000 && (priv->version == EMAC_VERSION_2)) { | |
826 | mac_control = emac_read(EMAC_MACCONTROL); | |
69ef9694 | 827 | mac_control |= (EMAC_DM646X_MACCONTORL_GIG | |
a6286ee6 AG |
828 | EMAC_DM646X_MACCONTORL_GIGFORCE); |
829 | } else { | |
830 | /* Clear the GIG bit and GIGFORCE bit */ | |
831 | mac_control &= ~(EMAC_DM646X_MACCONTORL_GIGFORCE | | |
832 | EMAC_DM646X_MACCONTORL_GIG); | |
833 | ||
834 | if (priv->rmii_en && (priv->speed == SPEED_100)) | |
835 | mac_control |= EMAC_MACCONTROL_RMIISPEED_MASK; | |
836 | else | |
837 | mac_control &= ~EMAC_MACCONTROL_RMIISPEED_MASK; | |
838 | } | |
839 | ||
840 | /* Update mac_control if changed */ | |
841 | emac_write(EMAC_MACCONTROL, mac_control); | |
842 | ||
843 | if (priv->link) { | |
844 | /* link ON */ | |
845 | if (!netif_carrier_ok(ndev)) | |
846 | netif_carrier_on(ndev); | |
847 | /* reactivate the transmit queue if it is stopped */ | |
848 | if (netif_running(ndev) && netif_queue_stopped(ndev)) | |
849 | netif_wake_queue(ndev); | |
850 | } else { | |
851 | /* link OFF */ | |
852 | if (netif_carrier_ok(ndev)) | |
853 | netif_carrier_off(ndev); | |
854 | if (!netif_queue_stopped(ndev)) | |
855 | netif_stop_queue(ndev); | |
856 | } | |
857 | } | |
858 | ||
859 | /** | |
860 | * hash_get: Calculate hash value from mac address | |
861 | * @addr: mac address to delete from hash table | |
862 | * | |
863 | * Calculates hash value from mac address | |
864 | * | |
865 | */ | |
866 | static u32 hash_get(u8 *addr) | |
867 | { | |
868 | u32 hash; | |
869 | u8 tmpval; | |
870 | int cnt; | |
871 | hash = 0; | |
872 | ||
873 | for (cnt = 0; cnt < 2; cnt++) { | |
874 | tmpval = *addr++; | |
875 | hash ^= (tmpval >> 2) ^ (tmpval << 4); | |
876 | tmpval = *addr++; | |
877 | hash ^= (tmpval >> 4) ^ (tmpval << 2); | |
878 | tmpval = *addr++; | |
879 | hash ^= (tmpval >> 6) ^ (tmpval); | |
880 | } | |
881 | ||
882 | return hash & 0x3F; | |
883 | } | |
884 | ||
885 | /** | |
886 | * hash_add: Hash function to add mac addr from hash table | |
887 | * @priv: The DaVinci EMAC private adapter structure | |
888 | * mac_addr: mac address to delete from hash table | |
889 | * | |
890 | * Adds mac address to the internal hash table | |
891 | * | |
892 | */ | |
893 | static int hash_add(struct emac_priv *priv, u8 *mac_addr) | |
894 | { | |
895 | struct device *emac_dev = &priv->ndev->dev; | |
896 | u32 rc = 0; | |
897 | u32 hash_bit; | |
898 | u32 hash_value = hash_get(mac_addr); | |
899 | ||
900 | if (hash_value >= EMAC_NUM_MULTICAST_BITS) { | |
901 | if (netif_msg_drv(priv)) { | |
902 | dev_err(emac_dev, "DaVinci EMAC: hash_add(): Invalid "\ | |
903 | "Hash %08x, should not be greater than %08x", | |
904 | hash_value, (EMAC_NUM_MULTICAST_BITS - 1)); | |
905 | } | |
906 | return -1; | |
907 | } | |
908 | ||
909 | /* set the hash bit only if not previously set */ | |
910 | if (priv->multicast_hash_cnt[hash_value] == 0) { | |
911 | rc = 1; /* hash value changed */ | |
912 | if (hash_value < 32) { | |
913 | hash_bit = BIT(hash_value); | |
914 | priv->mac_hash1 |= hash_bit; | |
915 | } else { | |
916 | hash_bit = BIT((hash_value - 32)); | |
917 | priv->mac_hash2 |= hash_bit; | |
918 | } | |
919 | } | |
920 | ||
921 | /* incr counter for num of mcast addr's mapped to "this" hash bit */ | |
922 | ++priv->multicast_hash_cnt[hash_value]; | |
923 | ||
924 | return rc; | |
925 | } | |
926 | ||
927 | /** | |
928 | * hash_del: Hash function to delete mac addr from hash table | |
929 | * @priv: The DaVinci EMAC private adapter structure | |
930 | * mac_addr: mac address to delete from hash table | |
931 | * | |
932 | * Removes mac address from the internal hash table | |
933 | * | |
934 | */ | |
935 | static int hash_del(struct emac_priv *priv, u8 *mac_addr) | |
936 | { | |
937 | u32 hash_value; | |
938 | u32 hash_bit; | |
939 | ||
940 | hash_value = hash_get(mac_addr); | |
941 | if (priv->multicast_hash_cnt[hash_value] > 0) { | |
942 | /* dec cntr for num of mcast addr's mapped to this hash bit */ | |
943 | --priv->multicast_hash_cnt[hash_value]; | |
944 | } | |
945 | ||
946 | /* if counter still > 0, at least one multicast address refers | |
947 | * to this hash bit. so return 0 */ | |
948 | if (priv->multicast_hash_cnt[hash_value] > 0) | |
949 | return 0; | |
950 | ||
951 | if (hash_value < 32) { | |
952 | hash_bit = BIT(hash_value); | |
953 | priv->mac_hash1 &= ~hash_bit; | |
954 | } else { | |
955 | hash_bit = BIT((hash_value - 32)); | |
956 | priv->mac_hash2 &= ~hash_bit; | |
957 | } | |
958 | ||
959 | /* return 1 to indicate change in mac_hash registers reqd */ | |
960 | return 1; | |
961 | } | |
962 | ||
963 | /* EMAC multicast operation */ | |
964 | #define EMAC_MULTICAST_ADD 0 | |
965 | #define EMAC_MULTICAST_DEL 1 | |
966 | #define EMAC_ALL_MULTI_SET 2 | |
967 | #define EMAC_ALL_MULTI_CLR 3 | |
968 | ||
969 | /** | |
970 | * emac_add_mcast: Set multicast address in the EMAC adapter (Internal) | |
971 | * @priv: The DaVinci EMAC private adapter structure | |
972 | * @action: multicast operation to perform | |
973 | * mac_addr: mac address to set | |
974 | * | |
975 | * Set multicast addresses in EMAC adapter - internal function | |
976 | * | |
977 | */ | |
978 | static void emac_add_mcast(struct emac_priv *priv, u32 action, u8 *mac_addr) | |
979 | { | |
980 | struct device *emac_dev = &priv->ndev->dev; | |
981 | int update = -1; | |
982 | ||
983 | switch (action) { | |
984 | case EMAC_MULTICAST_ADD: | |
985 | update = hash_add(priv, mac_addr); | |
986 | break; | |
987 | case EMAC_MULTICAST_DEL: | |
988 | update = hash_del(priv, mac_addr); | |
989 | break; | |
990 | case EMAC_ALL_MULTI_SET: | |
991 | update = 1; | |
992 | priv->mac_hash1 = EMAC_ALL_MULTI_REG_VALUE; | |
993 | priv->mac_hash2 = EMAC_ALL_MULTI_REG_VALUE; | |
994 | break; | |
995 | case EMAC_ALL_MULTI_CLR: | |
996 | update = 1; | |
997 | priv->mac_hash1 = 0; | |
998 | priv->mac_hash2 = 0; | |
999 | memset(&(priv->multicast_hash_cnt[0]), 0, | |
1000 | sizeof(priv->multicast_hash_cnt[0]) * | |
1001 | EMAC_NUM_MULTICAST_BITS); | |
1002 | break; | |
1003 | default: | |
1004 | if (netif_msg_drv(priv)) | |
1005 | dev_err(emac_dev, "DaVinci EMAC: add_mcast"\ | |
1006 | ": bad operation %d", action); | |
1007 | break; | |
1008 | } | |
1009 | ||
1010 | /* write to the hardware only if the register status chances */ | |
1011 | if (update > 0) { | |
1012 | emac_write(EMAC_MACHASH1, priv->mac_hash1); | |
1013 | emac_write(EMAC_MACHASH2, priv->mac_hash2); | |
1014 | } | |
1015 | } | |
1016 | ||
1017 | /** | |
1018 | * emac_dev_mcast_set: Set multicast address in the EMAC adapter | |
1019 | * @ndev: The DaVinci EMAC network adapter | |
1020 | * | |
1021 | * Set multicast addresses in EMAC adapter | |
1022 | * | |
1023 | */ | |
1024 | static void emac_dev_mcast_set(struct net_device *ndev) | |
1025 | { | |
1026 | u32 mbp_enable; | |
1027 | struct emac_priv *priv = netdev_priv(ndev); | |
1028 | ||
1029 | mbp_enable = emac_read(EMAC_RXMBPENABLE); | |
1030 | if (ndev->flags & IFF_PROMISC) { | |
1031 | mbp_enable &= (~EMAC_MBP_PROMISCCH(EMAC_DEF_PROM_CH)); | |
1032 | mbp_enable |= (EMAC_MBP_RXPROMISC); | |
1033 | } else { | |
1034 | mbp_enable = (mbp_enable & ~EMAC_MBP_RXPROMISC); | |
1035 | if ((ndev->flags & IFF_ALLMULTI) || | |
4cd24eaf | 1036 | netdev_mc_count(ndev) > EMAC_DEF_MAX_MULTICAST_ADDRESSES) { |
a6286ee6 AG |
1037 | mbp_enable = (mbp_enable | EMAC_MBP_RXMCAST); |
1038 | emac_add_mcast(priv, EMAC_ALL_MULTI_SET, NULL); | |
1039 | } | |
4cd24eaf | 1040 | if (!netdev_mc_empty(ndev)) { |
22bedad3 JP |
1041 | struct netdev_hw_addr *ha; |
1042 | ||
a6286ee6 AG |
1043 | mbp_enable = (mbp_enable | EMAC_MBP_RXMCAST); |
1044 | emac_add_mcast(priv, EMAC_ALL_MULTI_CLR, NULL); | |
1045 | /* program multicast address list into EMAC hardware */ | |
22bedad3 | 1046 | netdev_for_each_mc_addr(ha, ndev) { |
a6286ee6 | 1047 | emac_add_mcast(priv, EMAC_MULTICAST_ADD, |
22bedad3 | 1048 | (u8 *) ha->addr); |
a6286ee6 AG |
1049 | } |
1050 | } else { | |
1051 | mbp_enable = (mbp_enable & ~EMAC_MBP_RXMCAST); | |
1052 | emac_add_mcast(priv, EMAC_ALL_MULTI_CLR, NULL); | |
1053 | } | |
1054 | } | |
1055 | /* Set mbp config register */ | |
1056 | emac_write(EMAC_RXMBPENABLE, mbp_enable); | |
1057 | } | |
1058 | ||
1059 | /************************************************************************* | |
1060 | * EMAC Hardware manipulation | |
1061 | *************************************************************************/ | |
1062 | ||
1063 | /** | |
1064 | * emac_int_disable: Disable EMAC module interrupt (from adapter) | |
1065 | * @priv: The DaVinci EMAC private adapter structure | |
1066 | * | |
1067 | * Disable EMAC interrupt on the adapter | |
1068 | * | |
1069 | */ | |
1070 | static void emac_int_disable(struct emac_priv *priv) | |
1071 | { | |
1072 | if (priv->version == EMAC_VERSION_2) { | |
1073 | unsigned long flags; | |
1074 | ||
1075 | local_irq_save(flags); | |
1076 | ||
1077 | /* Program C0_Int_En to zero to turn off | |
1078 | * interrupts to the CPU */ | |
1079 | emac_ctrl_write(EMAC_DM646X_CMRXINTEN, 0x0); | |
1080 | emac_ctrl_write(EMAC_DM646X_CMTXINTEN, 0x0); | |
1081 | /* NOTE: Rx Threshold and Misc interrupts are not disabled */ | |
01a9af36 S |
1082 | if (priv->int_disable) |
1083 | priv->int_disable(); | |
a6286ee6 AG |
1084 | |
1085 | local_irq_restore(flags); | |
1086 | ||
1087 | } else { | |
1088 | /* Set DM644x control registers for interrupt control */ | |
1089 | emac_ctrl_write(EMAC_CTRL_EWCTL, 0x0); | |
1090 | } | |
1091 | } | |
1092 | ||
1093 | /** | |
1094 | * emac_int_enable: Enable EMAC module interrupt (from adapter) | |
1095 | * @priv: The DaVinci EMAC private adapter structure | |
1096 | * | |
1097 | * Enable EMAC interrupt on the adapter | |
1098 | * | |
1099 | */ | |
1100 | static void emac_int_enable(struct emac_priv *priv) | |
1101 | { | |
1102 | if (priv->version == EMAC_VERSION_2) { | |
01a9af36 S |
1103 | if (priv->int_enable) |
1104 | priv->int_enable(); | |
1105 | ||
a6286ee6 AG |
1106 | emac_ctrl_write(EMAC_DM646X_CMRXINTEN, 0xff); |
1107 | emac_ctrl_write(EMAC_DM646X_CMTXINTEN, 0xff); | |
1108 | ||
1109 | /* In addition to turning on interrupt Enable, we need | |
1110 | * ack by writing appropriate values to the EOI | |
1111 | * register */ | |
1112 | ||
1113 | /* NOTE: Rx Threshold and Misc interrupts are not enabled */ | |
1114 | ||
1115 | /* ack rxen only then a new pulse will be generated */ | |
1116 | emac_write(EMAC_DM646X_MACEOIVECTOR, | |
1117 | EMAC_DM646X_MAC_EOI_C0_RXEN); | |
1118 | ||
1119 | /* ack txen- only then a new pulse will be generated */ | |
1120 | emac_write(EMAC_DM646X_MACEOIVECTOR, | |
1121 | EMAC_DM646X_MAC_EOI_C0_TXEN); | |
1122 | ||
1123 | } else { | |
1124 | /* Set DM644x control registers for interrupt control */ | |
1125 | emac_ctrl_write(EMAC_CTRL_EWCTL, 0x1); | |
1126 | } | |
1127 | } | |
1128 | ||
1129 | /** | |
1130 | * emac_irq: EMAC interrupt handler | |
1131 | * @irq: interrupt number | |
1132 | * @dev_id: EMAC network adapter data structure ptr | |
1133 | * | |
1134 | * EMAC Interrupt handler - we only schedule NAPI and not process any packets | |
1135 | * here. EVen the interrupt status is checked (TX/RX/Err) in NAPI poll function | |
1136 | * | |
1137 | * Returns interrupt handled condition | |
1138 | */ | |
1139 | static irqreturn_t emac_irq(int irq, void *dev_id) | |
1140 | { | |
1141 | struct net_device *ndev = (struct net_device *)dev_id; | |
1142 | struct emac_priv *priv = netdev_priv(ndev); | |
1143 | ||
1144 | ++priv->isr_count; | |
1145 | if (likely(netif_running(priv->ndev))) { | |
1146 | emac_int_disable(priv); | |
1147 | napi_schedule(&priv->napi); | |
1148 | } else { | |
1149 | /* we are closing down, so dont process anything */ | |
1150 | } | |
1151 | return IRQ_HANDLED; | |
1152 | } | |
1153 | ||
1154 | /** EMAC on-chip buffer descriptor memory | |
1155 | * | |
1156 | * WARNING: Please note that the on chip memory is used for both TX and RX | |
1157 | * buffer descriptor queues and is equally divided between TX and RX desc's | |
1158 | * If the number of TX or RX descriptors change this memory pointers need | |
1159 | * to be adjusted. If external memory is allocated then these pointers can | |
1160 | * pointer to the memory | |
1161 | * | |
1162 | */ | |
1163 | #define EMAC_TX_BD_MEM(priv) ((priv)->emac_ctrl_ram) | |
1164 | #define EMAC_RX_BD_MEM(priv) ((priv)->emac_ctrl_ram + \ | |
1165 | (((priv)->ctrl_ram_size) >> 1)) | |
1166 | ||
1167 | /** | |
1168 | * emac_init_txch: TX channel initialization | |
1169 | * @priv: The DaVinci EMAC private adapter structure | |
1170 | * @ch: RX channel number | |
1171 | * | |
1172 | * Called during device init to setup a TX channel (allocate buffer desc | |
1173 | * create free pool and keep ready for transmission | |
1174 | * | |
1175 | * Returns success(0) or mem alloc failures error code | |
1176 | */ | |
1177 | static int emac_init_txch(struct emac_priv *priv, u32 ch) | |
1178 | { | |
1179 | struct device *emac_dev = &priv->ndev->dev; | |
1180 | u32 cnt, bd_size; | |
1181 | void __iomem *mem; | |
1182 | struct emac_tx_bd __iomem *curr_bd; | |
1183 | struct emac_txch *txch = NULL; | |
1184 | ||
1185 | txch = kzalloc(sizeof(struct emac_txch), GFP_KERNEL); | |
1186 | if (NULL == txch) { | |
1187 | dev_err(emac_dev, "DaVinci EMAC: TX Ch mem alloc failed"); | |
1188 | return -ENOMEM; | |
1189 | } | |
1190 | priv->txch[ch] = txch; | |
1191 | txch->service_max = EMAC_DEF_TX_MAX_SERVICE; | |
1192 | txch->active_queue_head = NULL; | |
1193 | txch->active_queue_tail = NULL; | |
1194 | txch->queue_active = 0; | |
1195 | txch->teardown_pending = 0; | |
1196 | ||
1197 | /* allocate memory for TX CPPI channel on a 4 byte boundry */ | |
1198 | txch->tx_complete = kzalloc(txch->service_max * sizeof(u32), | |
1199 | GFP_KERNEL); | |
1200 | if (NULL == txch->tx_complete) { | |
1201 | dev_err(emac_dev, "DaVinci EMAC: Tx service mem alloc failed"); | |
1202 | kfree(txch); | |
1203 | return -ENOMEM; | |
1204 | } | |
1205 | ||
1206 | /* allocate buffer descriptor pool align every BD on four word | |
1207 | * boundry for future requirements */ | |
1208 | bd_size = (sizeof(struct emac_tx_bd) + 0xF) & ~0xF; | |
1209 | txch->num_bd = (priv->ctrl_ram_size >> 1) / bd_size; | |
1210 | txch->alloc_size = (((bd_size * txch->num_bd) + 0xF) & ~0xF); | |
1211 | ||
1212 | /* alloc TX BD memory */ | |
1213 | txch->bd_mem = EMAC_TX_BD_MEM(priv); | |
1214 | __memzero((void __force *)txch->bd_mem, txch->alloc_size); | |
1215 | ||
1216 | /* initialize the BD linked list */ | |
1217 | mem = (void __force __iomem *) | |
1218 | (((u32 __force) txch->bd_mem + 0xF) & ~0xF); | |
1219 | txch->bd_pool_head = NULL; | |
1220 | for (cnt = 0; cnt < txch->num_bd; cnt++) { | |
1221 | curr_bd = mem + (cnt * bd_size); | |
1222 | curr_bd->next = txch->bd_pool_head; | |
1223 | txch->bd_pool_head = curr_bd; | |
1224 | } | |
1225 | ||
1226 | /* reset statistics counters */ | |
1227 | txch->out_of_tx_bd = 0; | |
1228 | txch->no_active_pkts = 0; | |
1229 | txch->active_queue_count = 0; | |
1230 | ||
1231 | return 0; | |
1232 | } | |
1233 | ||
1234 | /** | |
1235 | * emac_cleanup_txch: Book-keep function to clean TX channel resources | |
1236 | * @priv: The DaVinci EMAC private adapter structure | |
1237 | * @ch: TX channel number | |
1238 | * | |
1239 | * Called to clean up TX channel resources | |
1240 | * | |
1241 | */ | |
1242 | static void emac_cleanup_txch(struct emac_priv *priv, u32 ch) | |
1243 | { | |
1244 | struct emac_txch *txch = priv->txch[ch]; | |
1245 | ||
1246 | if (txch) { | |
1247 | if (txch->bd_mem) | |
1248 | txch->bd_mem = NULL; | |
1249 | kfree(txch->tx_complete); | |
1250 | kfree(txch); | |
1251 | priv->txch[ch] = NULL; | |
1252 | } | |
1253 | } | |
1254 | ||
1255 | /** | |
1256 | * emac_net_tx_complete: TX packet completion function | |
1257 | * @priv: The DaVinci EMAC private adapter structure | |
1258 | * @net_data_tokens: packet token - skb pointer | |
1259 | * @num_tokens: number of skb's to free | |
1260 | * @ch: TX channel number | |
1261 | * | |
1262 | * Frees the skb once packet is transmitted | |
1263 | * | |
1264 | */ | |
1265 | static int emac_net_tx_complete(struct emac_priv *priv, | |
1266 | void **net_data_tokens, | |
1267 | int num_tokens, u32 ch) | |
1268 | { | |
78e8c532 | 1269 | struct net_device *ndev = priv->ndev; |
a6286ee6 AG |
1270 | u32 cnt; |
1271 | ||
eabd8ba9 HC |
1272 | if (unlikely(num_tokens && netif_queue_stopped(ndev))) |
1273 | netif_start_queue(ndev); | |
a6286ee6 AG |
1274 | for (cnt = 0; cnt < num_tokens; cnt++) { |
1275 | struct sk_buff *skb = (struct sk_buff *)net_data_tokens[cnt]; | |
1276 | if (skb == NULL) | |
1277 | continue; | |
78e8c532 KV |
1278 | ndev->stats.tx_packets++; |
1279 | ndev->stats.tx_bytes += skb->len; | |
a6286ee6 AG |
1280 | dev_kfree_skb_any(skb); |
1281 | } | |
1282 | return 0; | |
1283 | } | |
1284 | ||
1285 | /** | |
1286 | * emac_txch_teardown: TX channel teardown | |
1287 | * @priv: The DaVinci EMAC private adapter structure | |
1288 | * @ch: TX channel number | |
1289 | * | |
1290 | * Called to teardown TX channel | |
1291 | * | |
1292 | */ | |
1293 | static void emac_txch_teardown(struct emac_priv *priv, u32 ch) | |
1294 | { | |
1295 | struct device *emac_dev = &priv->ndev->dev; | |
1296 | u32 teardown_cnt = 0xFFFFFFF0; /* Some high value */ | |
1297 | struct emac_txch *txch = priv->txch[ch]; | |
1298 | struct emac_tx_bd __iomem *curr_bd; | |
1299 | ||
1300 | while ((emac_read(EMAC_TXCP(ch)) & EMAC_TEARDOWN_VALUE) != | |
1301 | EMAC_TEARDOWN_VALUE) { | |
1302 | /* wait till tx teardown complete */ | |
1303 | cpu_relax(); /* TODO: check if this helps ... */ | |
1304 | --teardown_cnt; | |
1305 | if (0 == teardown_cnt) { | |
1306 | dev_err(emac_dev, "EMAC: TX teardown aborted\n"); | |
1307 | break; | |
1308 | } | |
1309 | } | |
1310 | emac_write(EMAC_TXCP(ch), EMAC_TEARDOWN_VALUE); | |
1311 | ||
1312 | /* process sent packets and return skb's to upper layer */ | |
1313 | if (1 == txch->queue_active) { | |
1314 | curr_bd = txch->active_queue_head; | |
1315 | while (curr_bd != NULL) { | |
be5bce2b SN |
1316 | dma_unmap_single(emac_dev, curr_bd->buff_ptr, |
1317 | curr_bd->off_b_len & EMAC_RX_BD_BUF_SIZE, | |
1318 | DMA_TO_DEVICE); | |
1319 | ||
a6286ee6 AG |
1320 | emac_net_tx_complete(priv, (void __force *) |
1321 | &curr_bd->buf_token, 1, ch); | |
1322 | if (curr_bd != txch->active_queue_tail) | |
1323 | curr_bd = curr_bd->next; | |
1324 | else | |
1325 | break; | |
1326 | } | |
1327 | txch->bd_pool_head = txch->active_queue_head; | |
1328 | txch->active_queue_head = | |
1329 | txch->active_queue_tail = NULL; | |
1330 | } | |
1331 | } | |
1332 | ||
1333 | /** | |
1334 | * emac_stop_txch: Stop TX channel operation | |
1335 | * @priv: The DaVinci EMAC private adapter structure | |
1336 | * @ch: TX channel number | |
1337 | * | |
1338 | * Called to stop TX channel operation | |
1339 | * | |
1340 | */ | |
1341 | static void emac_stop_txch(struct emac_priv *priv, u32 ch) | |
1342 | { | |
1343 | struct emac_txch *txch = priv->txch[ch]; | |
1344 | ||
1345 | if (txch) { | |
1346 | txch->teardown_pending = 1; | |
1347 | emac_write(EMAC_TXTEARDOWN, 0); | |
1348 | emac_txch_teardown(priv, ch); | |
1349 | txch->teardown_pending = 0; | |
1350 | emac_write(EMAC_TXINTMASKCLEAR, BIT(ch)); | |
1351 | } | |
1352 | } | |
1353 | ||
1354 | /** | |
1355 | * emac_tx_bdproc: TX buffer descriptor (packet) processing | |
1356 | * @priv: The DaVinci EMAC private adapter structure | |
1357 | * @ch: TX channel number to process buffer descriptors for | |
1358 | * @budget: number of packets allowed to process | |
1359 | * @pending: indication to caller that packets are pending to process | |
1360 | * | |
1361 | * Processes TX buffer descriptors after packets are transmitted - checks | |
1362 | * ownership bit on the TX * descriptor and requeues it to free pool & frees | |
1363 | * the SKB buffer. Only "budget" number of packets are processed and | |
1364 | * indication of pending packets provided to the caller | |
1365 | * | |
1366 | * Returns number of packets processed | |
1367 | */ | |
1368 | static int emac_tx_bdproc(struct emac_priv *priv, u32 ch, u32 budget) | |
1369 | { | |
1370 | struct device *emac_dev = &priv->ndev->dev; | |
1371 | unsigned long flags; | |
1372 | u32 frame_status; | |
1373 | u32 pkts_processed = 0; | |
1374 | u32 tx_complete_cnt = 0; | |
1375 | struct emac_tx_bd __iomem *curr_bd; | |
1376 | struct emac_txch *txch = priv->txch[ch]; | |
1377 | u32 *tx_complete_ptr = txch->tx_complete; | |
1378 | ||
1379 | if (unlikely(1 == txch->teardown_pending)) { | |
1380 | if (netif_msg_tx_err(priv) && net_ratelimit()) { | |
1381 | dev_err(emac_dev, "DaVinci EMAC:emac_tx_bdproc: "\ | |
1382 | "teardown pending\n"); | |
1383 | } | |
1384 | return 0; /* dont handle any pkt completions */ | |
1385 | } | |
1386 | ||
1387 | ++txch->proc_count; | |
1388 | spin_lock_irqsave(&priv->tx_lock, flags); | |
1389 | curr_bd = txch->active_queue_head; | |
1390 | if (NULL == curr_bd) { | |
1391 | emac_write(EMAC_TXCP(ch), | |
ad021ae8 | 1392 | emac_virt_to_phys(txch->last_hw_bdprocessed, priv)); |
a6286ee6 AG |
1393 | txch->no_active_pkts++; |
1394 | spin_unlock_irqrestore(&priv->tx_lock, flags); | |
1395 | return 0; | |
1396 | } | |
1397 | BD_CACHE_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE); | |
1398 | frame_status = curr_bd->mode; | |
1399 | while ((curr_bd) && | |
1400 | ((frame_status & EMAC_CPPI_OWNERSHIP_BIT) == 0) && | |
1401 | (pkts_processed < budget)) { | |
ad021ae8 | 1402 | emac_write(EMAC_TXCP(ch), emac_virt_to_phys(curr_bd, priv)); |
a6286ee6 AG |
1403 | txch->active_queue_head = curr_bd->next; |
1404 | if (frame_status & EMAC_CPPI_EOQ_BIT) { | |
1405 | if (curr_bd->next) { /* misqueued packet */ | |
1406 | emac_write(EMAC_TXHDP(ch), curr_bd->h_next); | |
1407 | ++txch->mis_queued_packets; | |
1408 | } else { | |
1409 | txch->queue_active = 0; /* end of queue */ | |
1410 | } | |
1411 | } | |
be5bce2b SN |
1412 | |
1413 | dma_unmap_single(emac_dev, curr_bd->buff_ptr, | |
1414 | curr_bd->off_b_len & EMAC_RX_BD_BUF_SIZE, | |
1415 | DMA_TO_DEVICE); | |
1416 | ||
a6286ee6 AG |
1417 | *tx_complete_ptr = (u32) curr_bd->buf_token; |
1418 | ++tx_complete_ptr; | |
1419 | ++tx_complete_cnt; | |
1420 | curr_bd->next = txch->bd_pool_head; | |
1421 | txch->bd_pool_head = curr_bd; | |
1422 | --txch->active_queue_count; | |
1423 | pkts_processed++; | |
1424 | txch->last_hw_bdprocessed = curr_bd; | |
1425 | curr_bd = txch->active_queue_head; | |
1426 | if (curr_bd) { | |
1427 | BD_CACHE_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE); | |
1428 | frame_status = curr_bd->mode; | |
1429 | } | |
1430 | } /* end of pkt processing loop */ | |
1431 | ||
1432 | emac_net_tx_complete(priv, | |
1433 | (void *)&txch->tx_complete[0], | |
1434 | tx_complete_cnt, ch); | |
1435 | spin_unlock_irqrestore(&priv->tx_lock, flags); | |
1436 | return pkts_processed; | |
1437 | } | |
1438 | ||
1439 | #define EMAC_ERR_TX_OUT_OF_BD -1 | |
1440 | ||
1441 | /** | |
1442 | * emac_send: EMAC Transmit function (internal) | |
1443 | * @priv: The DaVinci EMAC private adapter structure | |
1444 | * @pkt: packet pointer (contains skb ptr) | |
1445 | * @ch: TX channel number | |
1446 | * | |
1447 | * Called by the transmit function to queue the packet in EMAC hardware queue | |
1448 | * | |
1449 | * Returns success(0) or error code (typically out of desc's) | |
1450 | */ | |
1451 | static int emac_send(struct emac_priv *priv, struct emac_netpktobj *pkt, u32 ch) | |
1452 | { | |
1453 | unsigned long flags; | |
1454 | struct emac_tx_bd __iomem *curr_bd; | |
1455 | struct emac_txch *txch; | |
1456 | struct emac_netbufobj *buf_list; | |
1457 | ||
1458 | txch = priv->txch[ch]; | |
1459 | buf_list = pkt->buf_list; /* get handle to the buffer array */ | |
1460 | ||
1461 | /* check packet size and pad if short */ | |
1462 | if (pkt->pkt_length < EMAC_DEF_MIN_ETHPKTSIZE) { | |
1463 | buf_list->length += (EMAC_DEF_MIN_ETHPKTSIZE - pkt->pkt_length); | |
1464 | pkt->pkt_length = EMAC_DEF_MIN_ETHPKTSIZE; | |
1465 | } | |
1466 | ||
1467 | spin_lock_irqsave(&priv->tx_lock, flags); | |
1468 | curr_bd = txch->bd_pool_head; | |
1469 | if (curr_bd == NULL) { | |
1470 | txch->out_of_tx_bd++; | |
1471 | spin_unlock_irqrestore(&priv->tx_lock, flags); | |
1472 | return EMAC_ERR_TX_OUT_OF_BD; | |
1473 | } | |
1474 | ||
1475 | txch->bd_pool_head = curr_bd->next; | |
1476 | curr_bd->buf_token = buf_list->buf_token; | |
be5bce2b SN |
1477 | curr_bd->buff_ptr = dma_map_single(&priv->ndev->dev, buf_list->data_ptr, |
1478 | buf_list->length, DMA_TO_DEVICE); | |
a6286ee6 AG |
1479 | curr_bd->off_b_len = buf_list->length; |
1480 | curr_bd->h_next = 0; | |
1481 | curr_bd->next = NULL; | |
1482 | curr_bd->mode = (EMAC_CPPI_SOP_BIT | EMAC_CPPI_OWNERSHIP_BIT | | |
1483 | EMAC_CPPI_EOP_BIT | pkt->pkt_length); | |
1484 | ||
1485 | /* flush the packet from cache if write back cache is present */ | |
1486 | BD_CACHE_WRITEBACK_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE); | |
1487 | ||
1488 | /* send the packet */ | |
1489 | if (txch->active_queue_head == NULL) { | |
1490 | txch->active_queue_head = curr_bd; | |
1491 | txch->active_queue_tail = curr_bd; | |
1492 | if (1 != txch->queue_active) { | |
1493 | emac_write(EMAC_TXHDP(ch), | |
ad021ae8 | 1494 | emac_virt_to_phys(curr_bd, priv)); |
a6286ee6 AG |
1495 | txch->queue_active = 1; |
1496 | } | |
1497 | ++txch->queue_reinit; | |
1498 | } else { | |
1499 | register struct emac_tx_bd __iomem *tail_bd; | |
1500 | register u32 frame_status; | |
1501 | ||
1502 | tail_bd = txch->active_queue_tail; | |
1503 | tail_bd->next = curr_bd; | |
1504 | txch->active_queue_tail = curr_bd; | |
1505 | tail_bd = EMAC_VIRT_NOCACHE(tail_bd); | |
ad021ae8 | 1506 | tail_bd->h_next = (int)emac_virt_to_phys(curr_bd, priv); |
a6286ee6 AG |
1507 | frame_status = tail_bd->mode; |
1508 | if (frame_status & EMAC_CPPI_EOQ_BIT) { | |
ad021ae8 S |
1509 | emac_write(EMAC_TXHDP(ch), |
1510 | emac_virt_to_phys(curr_bd, priv)); | |
a6286ee6 AG |
1511 | frame_status &= ~(EMAC_CPPI_EOQ_BIT); |
1512 | tail_bd->mode = frame_status; | |
1513 | ++txch->end_of_queue_add; | |
1514 | } | |
1515 | } | |
1516 | txch->active_queue_count++; | |
1517 | spin_unlock_irqrestore(&priv->tx_lock, flags); | |
1518 | return 0; | |
1519 | } | |
1520 | ||
1521 | /** | |
1522 | * emac_dev_xmit: EMAC Transmit function | |
1523 | * @skb: SKB pointer | |
1524 | * @ndev: The DaVinci EMAC network adapter | |
1525 | * | |
1526 | * Called by the system to transmit a packet - we queue the packet in | |
1527 | * EMAC hardware transmit queue | |
1528 | * | |
1529 | * Returns success(NETDEV_TX_OK) or error code (typically out of desc's) | |
1530 | */ | |
1531 | static int emac_dev_xmit(struct sk_buff *skb, struct net_device *ndev) | |
1532 | { | |
1533 | struct device *emac_dev = &ndev->dev; | |
1534 | int ret_code; | |
1535 | struct emac_netbufobj tx_buf; /* buffer obj-only single frame support */ | |
1536 | struct emac_netpktobj tx_packet; /* packet object */ | |
1537 | struct emac_priv *priv = netdev_priv(ndev); | |
1538 | ||
1539 | /* If no link, return */ | |
1540 | if (unlikely(!priv->link)) { | |
1541 | if (netif_msg_tx_err(priv) && net_ratelimit()) | |
1542 | dev_err(emac_dev, "DaVinci EMAC: No link to transmit"); | |
1543 | return NETDEV_TX_BUSY; | |
1544 | } | |
1545 | ||
1546 | /* Build the buffer and packet objects - Since only single fragment is | |
1547 | * supported, need not set length and token in both packet & object. | |
1548 | * Doing so for completeness sake & to show that this needs to be done | |
1549 | * in multifragment case | |
1550 | */ | |
1551 | tx_packet.buf_list = &tx_buf; | |
1552 | tx_packet.num_bufs = 1; /* only single fragment supported */ | |
1553 | tx_packet.pkt_length = skb->len; | |
1554 | tx_packet.pkt_token = (void *)skb; | |
1555 | tx_buf.length = skb->len; | |
1556 | tx_buf.buf_token = (void *)skb; | |
1557 | tx_buf.data_ptr = skb->data; | |
a6286ee6 AG |
1558 | ret_code = emac_send(priv, &tx_packet, EMAC_DEF_TX_CH); |
1559 | if (unlikely(ret_code != 0)) { | |
1560 | if (ret_code == EMAC_ERR_TX_OUT_OF_BD) { | |
1561 | if (netif_msg_tx_err(priv) && net_ratelimit()) | |
1562 | dev_err(emac_dev, "DaVinci EMAC: xmit() fatal"\ | |
1563 | " err. Out of TX BD's"); | |
1564 | netif_stop_queue(priv->ndev); | |
1565 | } | |
78e8c532 | 1566 | ndev->stats.tx_dropped++; |
a6286ee6 AG |
1567 | return NETDEV_TX_BUSY; |
1568 | } | |
1569 | ||
1570 | return NETDEV_TX_OK; | |
1571 | } | |
1572 | ||
1573 | /** | |
1574 | * emac_dev_tx_timeout: EMAC Transmit timeout function | |
1575 | * @ndev: The DaVinci EMAC network adapter | |
1576 | * | |
1577 | * Called when system detects that a skb timeout period has expired | |
1578 | * potentially due to a fault in the adapter in not being able to send | |
1579 | * it out on the wire. We teardown the TX channel assuming a hardware | |
1580 | * error and re-initialize the TX channel for hardware operation | |
1581 | * | |
1582 | */ | |
1583 | static void emac_dev_tx_timeout(struct net_device *ndev) | |
1584 | { | |
1585 | struct emac_priv *priv = netdev_priv(ndev); | |
1586 | struct device *emac_dev = &ndev->dev; | |
1587 | ||
1588 | if (netif_msg_tx_err(priv)) | |
1589 | dev_err(emac_dev, "DaVinci EMAC: xmit timeout, restarting TX"); | |
1590 | ||
78e8c532 | 1591 | ndev->stats.tx_errors++; |
a6286ee6 AG |
1592 | emac_int_disable(priv); |
1593 | emac_stop_txch(priv, EMAC_DEF_TX_CH); | |
1594 | emac_cleanup_txch(priv, EMAC_DEF_TX_CH); | |
1595 | emac_init_txch(priv, EMAC_DEF_TX_CH); | |
1596 | emac_write(EMAC_TXHDP(0), 0); | |
1597 | emac_write(EMAC_TXINTMASKSET, BIT(EMAC_DEF_TX_CH)); | |
1598 | emac_int_enable(priv); | |
1599 | } | |
1600 | ||
1601 | /** | |
1602 | * emac_net_alloc_rx_buf: Allocate a skb for RX | |
1603 | * @priv: The DaVinci EMAC private adapter structure | |
1604 | * @buf_size: size of SKB data buffer to allocate | |
1605 | * @data_token: data token returned (skb handle for storing in buffer desc) | |
1606 | * @ch: RX channel number | |
1607 | * | |
1608 | * Called during RX channel setup - allocates skb buffer of required size | |
1609 | * and provides the skb handle and allocated buffer data pointer to caller | |
1610 | * | |
1611 | * Returns skb data pointer or 0 on failure to alloc skb | |
1612 | */ | |
1613 | static void *emac_net_alloc_rx_buf(struct emac_priv *priv, int buf_size, | |
1614 | void **data_token, u32 ch) | |
1615 | { | |
1616 | struct net_device *ndev = priv->ndev; | |
1617 | struct device *emac_dev = &ndev->dev; | |
1618 | struct sk_buff *p_skb; | |
1619 | ||
1620 | p_skb = dev_alloc_skb(buf_size); | |
1621 | if (unlikely(NULL == p_skb)) { | |
1622 | if (netif_msg_rx_err(priv) && net_ratelimit()) | |
1623 | dev_err(emac_dev, "DaVinci EMAC: failed to alloc skb"); | |
1624 | return NULL; | |
1625 | } | |
1626 | ||
1627 | /* set device pointer in skb and reserve space for extra bytes */ | |
1628 | p_skb->dev = ndev; | |
1629 | skb_reserve(p_skb, NET_IP_ALIGN); | |
1630 | *data_token = (void *) p_skb; | |
a6286ee6 AG |
1631 | return p_skb->data; |
1632 | } | |
1633 | ||
1634 | /** | |
1635 | * emac_init_rxch: RX channel initialization | |
1636 | * @priv: The DaVinci EMAC private adapter structure | |
1637 | * @ch: RX channel number | |
1638 | * @param: mac address for RX channel | |
1639 | * | |
1640 | * Called during device init to setup a RX channel (allocate buffers and | |
1641 | * buffer descriptors, create queue and keep ready for reception | |
1642 | * | |
1643 | * Returns success(0) or mem alloc failures error code | |
1644 | */ | |
1645 | static int emac_init_rxch(struct emac_priv *priv, u32 ch, char *param) | |
1646 | { | |
1647 | struct device *emac_dev = &priv->ndev->dev; | |
1648 | u32 cnt, bd_size; | |
1649 | void __iomem *mem; | |
1650 | struct emac_rx_bd __iomem *curr_bd; | |
1651 | struct emac_rxch *rxch = NULL; | |
1652 | ||
1653 | rxch = kzalloc(sizeof(struct emac_rxch), GFP_KERNEL); | |
1654 | if (NULL == rxch) { | |
1655 | dev_err(emac_dev, "DaVinci EMAC: RX Ch mem alloc failed"); | |
1656 | return -ENOMEM; | |
1657 | } | |
1658 | priv->rxch[ch] = rxch; | |
1659 | rxch->buf_size = priv->rx_buf_size; | |
1660 | rxch->service_max = EMAC_DEF_RX_MAX_SERVICE; | |
1661 | rxch->queue_active = 0; | |
1662 | rxch->teardown_pending = 0; | |
1663 | ||
1664 | /* save mac address */ | |
1665 | for (cnt = 0; cnt < 6; cnt++) | |
1666 | rxch->mac_addr[cnt] = param[cnt]; | |
1667 | ||
1668 | /* allocate buffer descriptor pool align every BD on four word | |
1669 | * boundry for future requirements */ | |
1670 | bd_size = (sizeof(struct emac_rx_bd) + 0xF) & ~0xF; | |
1671 | rxch->num_bd = (priv->ctrl_ram_size >> 1) / bd_size; | |
1672 | rxch->alloc_size = (((bd_size * rxch->num_bd) + 0xF) & ~0xF); | |
1673 | rxch->bd_mem = EMAC_RX_BD_MEM(priv); | |
1674 | __memzero((void __force *)rxch->bd_mem, rxch->alloc_size); | |
1675 | rxch->pkt_queue.buf_list = &rxch->buf_queue; | |
1676 | ||
1677 | /* allocate RX buffer and initialize the BD linked list */ | |
1678 | mem = (void __force __iomem *) | |
1679 | (((u32 __force) rxch->bd_mem + 0xF) & ~0xF); | |
1680 | rxch->active_queue_head = NULL; | |
1681 | rxch->active_queue_tail = mem; | |
1682 | for (cnt = 0; cnt < rxch->num_bd; cnt++) { | |
1683 | curr_bd = mem + (cnt * bd_size); | |
1684 | /* for future use the last parameter contains the BD ptr */ | |
1685 | curr_bd->data_ptr = emac_net_alloc_rx_buf(priv, | |
1686 | rxch->buf_size, | |
1687 | (void __force **)&curr_bd->buf_token, | |
1688 | EMAC_DEF_RX_CH); | |
1689 | if (curr_bd->data_ptr == NULL) { | |
1690 | dev_err(emac_dev, "DaVinci EMAC: RX buf mem alloc " \ | |
1691 | "failed for ch %d\n", ch); | |
1692 | kfree(rxch); | |
1693 | return -ENOMEM; | |
1694 | } | |
1695 | ||
1696 | /* populate the hardware descriptor */ | |
ad021ae8 S |
1697 | curr_bd->h_next = emac_virt_to_phys(rxch->active_queue_head, |
1698 | priv); | |
be5bce2b SN |
1699 | curr_bd->buff_ptr = dma_map_single(emac_dev, curr_bd->data_ptr, |
1700 | rxch->buf_size, DMA_FROM_DEVICE); | |
a6286ee6 AG |
1701 | curr_bd->off_b_len = rxch->buf_size; |
1702 | curr_bd->mode = EMAC_CPPI_OWNERSHIP_BIT; | |
1703 | ||
1704 | /* write back to hardware memory */ | |
1705 | BD_CACHE_WRITEBACK_INVALIDATE((u32) curr_bd, | |
1706 | EMAC_BD_LENGTH_FOR_CACHE); | |
1707 | curr_bd->next = rxch->active_queue_head; | |
1708 | rxch->active_queue_head = curr_bd; | |
1709 | } | |
1710 | ||
1711 | /* At this point rxCppi->activeQueueHead points to the first | |
1712 | RX BD ready to be given to RX HDP and rxch->active_queue_tail | |
1713 | points to the last RX BD | |
1714 | */ | |
1715 | return 0; | |
1716 | } | |
1717 | ||
1718 | /** | |
1719 | * emac_rxch_teardown: RX channel teardown | |
1720 | * @priv: The DaVinci EMAC private adapter structure | |
1721 | * @ch: RX channel number | |
1722 | * | |
1723 | * Called during device stop to teardown RX channel | |
1724 | * | |
1725 | */ | |
1726 | static void emac_rxch_teardown(struct emac_priv *priv, u32 ch) | |
1727 | { | |
1728 | struct device *emac_dev = &priv->ndev->dev; | |
1729 | u32 teardown_cnt = 0xFFFFFFF0; /* Some high value */ | |
1730 | ||
1731 | while ((emac_read(EMAC_RXCP(ch)) & EMAC_TEARDOWN_VALUE) != | |
1732 | EMAC_TEARDOWN_VALUE) { | |
1733 | /* wait till tx teardown complete */ | |
1734 | cpu_relax(); /* TODO: check if this helps ... */ | |
1735 | --teardown_cnt; | |
1736 | if (0 == teardown_cnt) { | |
1737 | dev_err(emac_dev, "EMAC: RX teardown aborted\n"); | |
1738 | break; | |
1739 | } | |
1740 | } | |
1741 | emac_write(EMAC_RXCP(ch), EMAC_TEARDOWN_VALUE); | |
1742 | } | |
1743 | ||
1744 | /** | |
1745 | * emac_stop_rxch: Stop RX channel operation | |
1746 | * @priv: The DaVinci EMAC private adapter structure | |
1747 | * @ch: RX channel number | |
1748 | * | |
1749 | * Called during device stop to stop RX channel operation | |
1750 | * | |
1751 | */ | |
1752 | static void emac_stop_rxch(struct emac_priv *priv, u32 ch) | |
1753 | { | |
1754 | struct emac_rxch *rxch = priv->rxch[ch]; | |
1755 | ||
1756 | if (rxch) { | |
1757 | rxch->teardown_pending = 1; | |
1758 | emac_write(EMAC_RXTEARDOWN, ch); | |
1759 | /* wait for teardown complete */ | |
1760 | emac_rxch_teardown(priv, ch); | |
1761 | rxch->teardown_pending = 0; | |
1762 | emac_write(EMAC_RXINTMASKCLEAR, BIT(ch)); | |
1763 | } | |
1764 | } | |
1765 | ||
1766 | /** | |
1767 | * emac_cleanup_rxch: Book-keep function to clean RX channel resources | |
1768 | * @priv: The DaVinci EMAC private adapter structure | |
1769 | * @ch: RX channel number | |
1770 | * | |
1771 | * Called during device stop to clean up RX channel resources | |
1772 | * | |
1773 | */ | |
1774 | static void emac_cleanup_rxch(struct emac_priv *priv, u32 ch) | |
1775 | { | |
1776 | struct emac_rxch *rxch = priv->rxch[ch]; | |
1777 | struct emac_rx_bd __iomem *curr_bd; | |
1778 | ||
1779 | if (rxch) { | |
1780 | /* free the receive buffers previously allocated */ | |
1781 | curr_bd = rxch->active_queue_head; | |
1782 | while (curr_bd) { | |
1783 | if (curr_bd->buf_token) { | |
be5bce2b SN |
1784 | dma_unmap_single(&priv->ndev->dev, |
1785 | curr_bd->buff_ptr, | |
1786 | curr_bd->off_b_len | |
1787 | & EMAC_RX_BD_BUF_SIZE, | |
1788 | DMA_FROM_DEVICE); | |
1789 | ||
a6286ee6 AG |
1790 | dev_kfree_skb_any((struct sk_buff *)\ |
1791 | curr_bd->buf_token); | |
1792 | } | |
1793 | curr_bd = curr_bd->next; | |
1794 | } | |
1795 | if (rxch->bd_mem) | |
1796 | rxch->bd_mem = NULL; | |
1797 | kfree(rxch); | |
1798 | priv->rxch[ch] = NULL; | |
1799 | } | |
1800 | } | |
1801 | ||
1802 | /** | |
1803 | * emac_set_type0addr: Set EMAC Type0 mac address | |
1804 | * @priv: The DaVinci EMAC private adapter structure | |
1805 | * @ch: RX channel number | |
1806 | * @mac_addr: MAC address to set in device | |
1807 | * | |
1808 | * Called internally to set Type0 mac address of the adapter (Device) | |
1809 | * | |
1810 | * Returns success (0) or appropriate error code (none as of now) | |
1811 | */ | |
1812 | static void emac_set_type0addr(struct emac_priv *priv, u32 ch, char *mac_addr) | |
1813 | { | |
1814 | u32 val; | |
1815 | val = ((mac_addr[5] << 8) | (mac_addr[4])); | |
1816 | emac_write(EMAC_MACSRCADDRLO, val); | |
1817 | ||
1818 | val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \ | |
1819 | (mac_addr[1] << 8) | (mac_addr[0])); | |
1820 | emac_write(EMAC_MACSRCADDRHI, val); | |
1821 | val = emac_read(EMAC_RXUNICASTSET); | |
1822 | val |= BIT(ch); | |
1823 | emac_write(EMAC_RXUNICASTSET, val); | |
1824 | val = emac_read(EMAC_RXUNICASTCLEAR); | |
1825 | val &= ~BIT(ch); | |
1826 | emac_write(EMAC_RXUNICASTCLEAR, val); | |
1827 | } | |
1828 | ||
1829 | /** | |
1830 | * emac_set_type1addr: Set EMAC Type1 mac address | |
1831 | * @priv: The DaVinci EMAC private adapter structure | |
1832 | * @ch: RX channel number | |
1833 | * @mac_addr: MAC address to set in device | |
1834 | * | |
1835 | * Called internally to set Type1 mac address of the adapter (Device) | |
1836 | * | |
1837 | * Returns success (0) or appropriate error code (none as of now) | |
1838 | */ | |
1839 | static void emac_set_type1addr(struct emac_priv *priv, u32 ch, char *mac_addr) | |
1840 | { | |
1841 | u32 val; | |
1842 | emac_write(EMAC_MACINDEX, ch); | |
1843 | val = ((mac_addr[5] << 8) | mac_addr[4]); | |
1844 | emac_write(EMAC_MACADDRLO, val); | |
1845 | val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \ | |
1846 | (mac_addr[1] << 8) | (mac_addr[0])); | |
1847 | emac_write(EMAC_MACADDRHI, val); | |
1848 | emac_set_type0addr(priv, ch, mac_addr); | |
1849 | } | |
1850 | ||
1851 | /** | |
1852 | * emac_set_type2addr: Set EMAC Type2 mac address | |
1853 | * @priv: The DaVinci EMAC private adapter structure | |
1854 | * @ch: RX channel number | |
1855 | * @mac_addr: MAC address to set in device | |
1856 | * @index: index into RX address entries | |
1857 | * @match: match parameter for RX address matching logic | |
1858 | * | |
1859 | * Called internally to set Type2 mac address of the adapter (Device) | |
1860 | * | |
1861 | * Returns success (0) or appropriate error code (none as of now) | |
1862 | */ | |
1863 | static void emac_set_type2addr(struct emac_priv *priv, u32 ch, | |
1864 | char *mac_addr, int index, int match) | |
1865 | { | |
1866 | u32 val; | |
1867 | emac_write(EMAC_MACINDEX, index); | |
1868 | val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \ | |
1869 | (mac_addr[1] << 8) | (mac_addr[0])); | |
1870 | emac_write(EMAC_MACADDRHI, val); | |
1871 | val = ((mac_addr[5] << 8) | mac_addr[4] | ((ch & 0x7) << 16) | \ | |
1872 | (match << 19) | BIT(20)); | |
1873 | emac_write(EMAC_MACADDRLO, val); | |
1874 | emac_set_type0addr(priv, ch, mac_addr); | |
1875 | } | |
1876 | ||
1877 | /** | |
1878 | * emac_setmac: Set mac address in the adapter (internal function) | |
1879 | * @priv: The DaVinci EMAC private adapter structure | |
1880 | * @ch: RX channel number | |
1881 | * @mac_addr: MAC address to set in device | |
1882 | * | |
1883 | * Called internally to set the mac address of the adapter (Device) | |
1884 | * | |
1885 | * Returns success (0) or appropriate error code (none as of now) | |
1886 | */ | |
1887 | static void emac_setmac(struct emac_priv *priv, u32 ch, char *mac_addr) | |
1888 | { | |
1889 | struct device *emac_dev = &priv->ndev->dev; | |
1890 | ||
1891 | if (priv->rx_addr_type == 0) { | |
1892 | emac_set_type0addr(priv, ch, mac_addr); | |
1893 | } else if (priv->rx_addr_type == 1) { | |
1894 | u32 cnt; | |
1895 | for (cnt = 0; cnt < EMAC_MAX_TXRX_CHANNELS; cnt++) | |
1896 | emac_set_type1addr(priv, ch, mac_addr); | |
1897 | } else if (priv->rx_addr_type == 2) { | |
1898 | emac_set_type2addr(priv, ch, mac_addr, ch, 1); | |
1899 | emac_set_type0addr(priv, ch, mac_addr); | |
1900 | } else { | |
1901 | if (netif_msg_drv(priv)) | |
1902 | dev_err(emac_dev, "DaVinci EMAC: Wrong addressing\n"); | |
1903 | } | |
1904 | } | |
1905 | ||
1906 | /** | |
1907 | * emac_dev_setmac_addr: Set mac address in the adapter | |
1908 | * @ndev: The DaVinci EMAC network adapter | |
1909 | * @addr: MAC address to set in device | |
1910 | * | |
1911 | * Called by the system to set the mac address of the adapter (Device) | |
1912 | * | |
1913 | * Returns success (0) or appropriate error code (none as of now) | |
1914 | */ | |
1915 | static int emac_dev_setmac_addr(struct net_device *ndev, void *addr) | |
1916 | { | |
1917 | struct emac_priv *priv = netdev_priv(ndev); | |
1918 | struct emac_rxch *rxch = priv->rxch[EMAC_DEF_RX_CH]; | |
1919 | struct device *emac_dev = &priv->ndev->dev; | |
1920 | struct sockaddr *sa = addr; | |
a6286ee6 | 1921 | |
64c8165b PB |
1922 | if (!is_valid_ether_addr(sa->sa_data)) |
1923 | return -EINVAL; | |
1924 | ||
a6286ee6 AG |
1925 | /* Store mac addr in priv and rx channel and set it in EMAC hw */ |
1926 | memcpy(priv->mac_addr, sa->sa_data, ndev->addr_len); | |
a6286ee6 | 1927 | memcpy(ndev->dev_addr, sa->sa_data, ndev->addr_len); |
64c8165b PB |
1928 | |
1929 | /* If the interface is down - rxch is NULL. */ | |
1930 | /* MAC address is configured only after the interface is enabled. */ | |
1931 | if (netif_running(ndev)) { | |
1932 | memcpy(rxch->mac_addr, sa->sa_data, ndev->addr_len); | |
1933 | emac_setmac(priv, EMAC_DEF_RX_CH, rxch->mac_addr); | |
1934 | } | |
a6286ee6 AG |
1935 | |
1936 | if (netif_msg_drv(priv)) | |
5c726166 C |
1937 | dev_notice(emac_dev, "DaVinci EMAC: emac_dev_setmac_addr %pM\n", |
1938 | priv->mac_addr); | |
a6286ee6 AG |
1939 | |
1940 | return 0; | |
1941 | } | |
1942 | ||
1943 | /** | |
1944 | * emac_addbd_to_rx_queue: Recycle RX buffer descriptor | |
1945 | * @priv: The DaVinci EMAC private adapter structure | |
1946 | * @ch: RX channel number to process buffer descriptors for | |
1947 | * @curr_bd: current buffer descriptor | |
1948 | * @buffer: buffer pointer for descriptor | |
1949 | * @buf_token: buffer token (stores skb information) | |
1950 | * | |
1951 | * Prepares the recycled buffer descriptor and addes it to hardware | |
1952 | * receive queue - if queue empty this descriptor becomes the head | |
1953 | * else addes the descriptor to end of queue | |
1954 | * | |
1955 | */ | |
1956 | static void emac_addbd_to_rx_queue(struct emac_priv *priv, u32 ch, | |
1957 | struct emac_rx_bd __iomem *curr_bd, | |
1958 | char *buffer, void *buf_token) | |
1959 | { | |
1960 | struct emac_rxch *rxch = priv->rxch[ch]; | |
1961 | ||
1962 | /* populate the hardware descriptor */ | |
1963 | curr_bd->h_next = 0; | |
be5bce2b SN |
1964 | curr_bd->buff_ptr = dma_map_single(&priv->ndev->dev, buffer, |
1965 | rxch->buf_size, DMA_FROM_DEVICE); | |
a6286ee6 AG |
1966 | curr_bd->off_b_len = rxch->buf_size; |
1967 | curr_bd->mode = EMAC_CPPI_OWNERSHIP_BIT; | |
1968 | curr_bd->next = NULL; | |
1969 | curr_bd->data_ptr = buffer; | |
1970 | curr_bd->buf_token = buf_token; | |
1971 | ||
1972 | /* write back */ | |
1973 | BD_CACHE_WRITEBACK_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE); | |
1974 | if (rxch->active_queue_head == NULL) { | |
1975 | rxch->active_queue_head = curr_bd; | |
1976 | rxch->active_queue_tail = curr_bd; | |
1977 | if (0 != rxch->queue_active) { | |
1978 | emac_write(EMAC_RXHDP(ch), | |
ad021ae8 | 1979 | emac_virt_to_phys(rxch->active_queue_head, priv)); |
a6286ee6 AG |
1980 | rxch->queue_active = 1; |
1981 | } | |
1982 | } else { | |
1983 | struct emac_rx_bd __iomem *tail_bd; | |
1984 | u32 frame_status; | |
1985 | ||
1986 | tail_bd = rxch->active_queue_tail; | |
1987 | rxch->active_queue_tail = curr_bd; | |
1988 | tail_bd->next = curr_bd; | |
1989 | tail_bd = EMAC_VIRT_NOCACHE(tail_bd); | |
ad021ae8 | 1990 | tail_bd->h_next = emac_virt_to_phys(curr_bd, priv); |
a6286ee6 AG |
1991 | frame_status = tail_bd->mode; |
1992 | if (frame_status & EMAC_CPPI_EOQ_BIT) { | |
1993 | emac_write(EMAC_RXHDP(ch), | |
ad021ae8 | 1994 | emac_virt_to_phys(curr_bd, priv)); |
a6286ee6 AG |
1995 | frame_status &= ~(EMAC_CPPI_EOQ_BIT); |
1996 | tail_bd->mode = frame_status; | |
1997 | ++rxch->end_of_queue_add; | |
1998 | } | |
1999 | } | |
2000 | ++rxch->recycled_bd; | |
2001 | } | |
2002 | ||
2003 | /** | |
2004 | * emac_net_rx_cb: Prepares packet and sends to upper layer | |
2005 | * @priv: The DaVinci EMAC private adapter structure | |
2006 | * @net_pkt_list: Network packet list (received packets) | |
2007 | * | |
2008 | * Invalidates packet buffer memory and sends the received packet to upper | |
2009 | * layer | |
2010 | * | |
2011 | * Returns success or appropriate error code (none as of now) | |
2012 | */ | |
2013 | static int emac_net_rx_cb(struct emac_priv *priv, | |
2014 | struct emac_netpktobj *net_pkt_list) | |
2015 | { | |
78e8c532 KV |
2016 | struct net_device *ndev = priv->ndev; |
2017 | struct sk_buff *p_skb = net_pkt_list->pkt_token; | |
a6286ee6 AG |
2018 | /* set length of packet */ |
2019 | skb_put(p_skb, net_pkt_list->pkt_length); | |
a6286ee6 | 2020 | p_skb->protocol = eth_type_trans(p_skb, priv->ndev); |
a6286ee6 | 2021 | netif_receive_skb(p_skb); |
78e8c532 KV |
2022 | ndev->stats.rx_bytes += net_pkt_list->pkt_length; |
2023 | ndev->stats.rx_packets++; | |
a6286ee6 AG |
2024 | return 0; |
2025 | } | |
2026 | ||
2027 | /** | |
2028 | * emac_rx_bdproc: RX buffer descriptor (packet) processing | |
2029 | * @priv: The DaVinci EMAC private adapter structure | |
2030 | * @ch: RX channel number to process buffer descriptors for | |
2031 | * @budget: number of packets allowed to process | |
2032 | * @pending: indication to caller that packets are pending to process | |
2033 | * | |
2034 | * Processes RX buffer descriptors - checks ownership bit on the RX buffer | |
2035 | * descriptor, sends the receive packet to upper layer, allocates a new SKB | |
2036 | * and recycles the buffer descriptor (requeues it in hardware RX queue). | |
2037 | * Only "budget" number of packets are processed and indication of pending | |
2038 | * packets provided to the caller. | |
2039 | * | |
2040 | * Returns number of packets processed (and indication of pending packets) | |
2041 | */ | |
2042 | static int emac_rx_bdproc(struct emac_priv *priv, u32 ch, u32 budget) | |
2043 | { | |
2044 | unsigned long flags; | |
2045 | u32 frame_status; | |
2046 | u32 pkts_processed = 0; | |
2047 | char *new_buffer; | |
2048 | struct emac_rx_bd __iomem *curr_bd; | |
2049 | struct emac_rx_bd __iomem *last_bd; | |
2050 | struct emac_netpktobj *curr_pkt, pkt_obj; | |
2051 | struct emac_netbufobj buf_obj; | |
2052 | struct emac_netbufobj *rx_buf_obj; | |
2053 | void *new_buf_token; | |
2054 | struct emac_rxch *rxch = priv->rxch[ch]; | |
2055 | ||
2056 | if (unlikely(1 == rxch->teardown_pending)) | |
2057 | return 0; | |
2058 | ++rxch->proc_count; | |
2059 | spin_lock_irqsave(&priv->rx_lock, flags); | |
2060 | pkt_obj.buf_list = &buf_obj; | |
2061 | curr_pkt = &pkt_obj; | |
2062 | curr_bd = rxch->active_queue_head; | |
2063 | BD_CACHE_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE); | |
2064 | frame_status = curr_bd->mode; | |
2065 | ||
2066 | while ((curr_bd) && | |
2067 | ((frame_status & EMAC_CPPI_OWNERSHIP_BIT) == 0) && | |
2068 | (pkts_processed < budget)) { | |
2069 | ||
2070 | new_buffer = emac_net_alloc_rx_buf(priv, rxch->buf_size, | |
2071 | &new_buf_token, EMAC_DEF_RX_CH); | |
2072 | if (unlikely(NULL == new_buffer)) { | |
2073 | ++rxch->out_of_rx_buffers; | |
2074 | goto end_emac_rx_bdproc; | |
2075 | } | |
2076 | ||
2077 | /* populate received packet data structure */ | |
2078 | rx_buf_obj = &curr_pkt->buf_list[0]; | |
2079 | rx_buf_obj->data_ptr = (char *)curr_bd->data_ptr; | |
2080 | rx_buf_obj->length = curr_bd->off_b_len & EMAC_RX_BD_BUF_SIZE; | |
2081 | rx_buf_obj->buf_token = curr_bd->buf_token; | |
be5bce2b SN |
2082 | |
2083 | dma_unmap_single(&priv->ndev->dev, curr_bd->buff_ptr, | |
2084 | curr_bd->off_b_len & EMAC_RX_BD_BUF_SIZE, | |
2085 | DMA_FROM_DEVICE); | |
2086 | ||
a6286ee6 AG |
2087 | curr_pkt->pkt_token = curr_pkt->buf_list->buf_token; |
2088 | curr_pkt->num_bufs = 1; | |
2089 | curr_pkt->pkt_length = | |
2090 | (frame_status & EMAC_RX_BD_PKT_LENGTH_MASK); | |
ad021ae8 | 2091 | emac_write(EMAC_RXCP(ch), emac_virt_to_phys(curr_bd, priv)); |
a6286ee6 AG |
2092 | ++rxch->processed_bd; |
2093 | last_bd = curr_bd; | |
2094 | curr_bd = last_bd->next; | |
2095 | rxch->active_queue_head = curr_bd; | |
2096 | ||
2097 | /* check if end of RX queue ? */ | |
2098 | if (frame_status & EMAC_CPPI_EOQ_BIT) { | |
2099 | if (curr_bd) { | |
2100 | ++rxch->mis_queued_packets; | |
2101 | emac_write(EMAC_RXHDP(ch), | |
ad021ae8 | 2102 | emac_virt_to_phys(curr_bd, priv)); |
a6286ee6 AG |
2103 | } else { |
2104 | ++rxch->end_of_queue; | |
2105 | rxch->queue_active = 0; | |
2106 | } | |
2107 | } | |
2108 | ||
2109 | /* recycle BD */ | |
2110 | emac_addbd_to_rx_queue(priv, ch, last_bd, new_buffer, | |
2111 | new_buf_token); | |
2112 | ||
2113 | /* return the packet to the user - BD ptr passed in | |
2114 | * last parameter for potential *future* use */ | |
2115 | spin_unlock_irqrestore(&priv->rx_lock, flags); | |
2116 | emac_net_rx_cb(priv, curr_pkt); | |
2117 | spin_lock_irqsave(&priv->rx_lock, flags); | |
2118 | curr_bd = rxch->active_queue_head; | |
2119 | if (curr_bd) { | |
2120 | BD_CACHE_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE); | |
2121 | frame_status = curr_bd->mode; | |
2122 | } | |
2123 | ++pkts_processed; | |
2124 | } | |
2125 | ||
2126 | end_emac_rx_bdproc: | |
2127 | spin_unlock_irqrestore(&priv->rx_lock, flags); | |
2128 | return pkts_processed; | |
2129 | } | |
2130 | ||
2131 | /** | |
2132 | * emac_hw_enable: Enable EMAC hardware for packet transmission/reception | |
2133 | * @priv: The DaVinci EMAC private adapter structure | |
2134 | * | |
2135 | * Enables EMAC hardware for packet processing - enables PHY, enables RX | |
2136 | * for packet reception and enables device interrupts and then NAPI | |
2137 | * | |
2138 | * Returns success (0) or appropriate error code (none right now) | |
2139 | */ | |
2140 | static int emac_hw_enable(struct emac_priv *priv) | |
2141 | { | |
2142 | u32 ch, val, mbp_enable, mac_control; | |
2143 | ||
2144 | /* Soft reset */ | |
2145 | emac_write(EMAC_SOFTRESET, 1); | |
2146 | while (emac_read(EMAC_SOFTRESET)) | |
2147 | cpu_relax(); | |
2148 | ||
2149 | /* Disable interrupt & Set pacing for more interrupts initially */ | |
2150 | emac_int_disable(priv); | |
2151 | ||
2152 | /* Full duplex enable bit set when auto negotiation happens */ | |
2153 | mac_control = | |
2154 | (((EMAC_DEF_TXPRIO_FIXED) ? (EMAC_MACCONTROL_TXPTYPE) : 0x0) | | |
2155 | ((priv->speed == 1000) ? EMAC_MACCONTROL_GIGABITEN : 0x0) | | |
2156 | ((EMAC_DEF_TXPACING_EN) ? (EMAC_MACCONTROL_TXPACEEN) : 0x0) | | |
2157 | ((priv->duplex == DUPLEX_FULL) ? 0x1 : 0)); | |
2158 | emac_write(EMAC_MACCONTROL, mac_control); | |
2159 | ||
2160 | mbp_enable = | |
2161 | (((EMAC_DEF_PASS_CRC) ? (EMAC_RXMBP_PASSCRC_MASK) : 0x0) | | |
2162 | ((EMAC_DEF_QOS_EN) ? (EMAC_RXMBP_QOSEN_MASK) : 0x0) | | |
2163 | ((EMAC_DEF_NO_BUFF_CHAIN) ? (EMAC_RXMBP_NOCHAIN_MASK) : 0x0) | | |
2164 | ((EMAC_DEF_MACCTRL_FRAME_EN) ? (EMAC_RXMBP_CMFEN_MASK) : 0x0) | | |
2165 | ((EMAC_DEF_SHORT_FRAME_EN) ? (EMAC_RXMBP_CSFEN_MASK) : 0x0) | | |
2166 | ((EMAC_DEF_ERROR_FRAME_EN) ? (EMAC_RXMBP_CEFEN_MASK) : 0x0) | | |
2167 | ((EMAC_DEF_PROM_EN) ? (EMAC_RXMBP_CAFEN_MASK) : 0x0) | | |
2168 | ((EMAC_DEF_PROM_CH & EMAC_RXMBP_CHMASK) << \ | |
2169 | EMAC_RXMBP_PROMCH_SHIFT) | | |
2170 | ((EMAC_DEF_BCAST_EN) ? (EMAC_RXMBP_BROADEN_MASK) : 0x0) | | |
2171 | ((EMAC_DEF_BCAST_CH & EMAC_RXMBP_CHMASK) << \ | |
2172 | EMAC_RXMBP_BROADCH_SHIFT) | | |
2173 | ((EMAC_DEF_MCAST_EN) ? (EMAC_RXMBP_MULTIEN_MASK) : 0x0) | | |
2174 | ((EMAC_DEF_MCAST_CH & EMAC_RXMBP_CHMASK) << \ | |
2175 | EMAC_RXMBP_MULTICH_SHIFT)); | |
2176 | emac_write(EMAC_RXMBPENABLE, mbp_enable); | |
2177 | emac_write(EMAC_RXMAXLEN, (EMAC_DEF_MAX_FRAME_SIZE & | |
2178 | EMAC_RX_MAX_LEN_MASK)); | |
2179 | emac_write(EMAC_RXBUFFEROFFSET, (EMAC_DEF_BUFFER_OFFSET & | |
2180 | EMAC_RX_BUFFER_OFFSET_MASK)); | |
2181 | emac_write(EMAC_RXFILTERLOWTHRESH, 0); | |
2182 | emac_write(EMAC_RXUNICASTCLEAR, EMAC_RX_UNICAST_CLEAR_ALL); | |
2183 | priv->rx_addr_type = (emac_read(EMAC_MACCONFIG) >> 8) & 0xFF; | |
2184 | ||
2185 | val = emac_read(EMAC_TXCONTROL); | |
2186 | val |= EMAC_TX_CONTROL_TX_ENABLE_VAL; | |
2187 | emac_write(EMAC_TXCONTROL, val); | |
2188 | val = emac_read(EMAC_RXCONTROL); | |
2189 | val |= EMAC_RX_CONTROL_RX_ENABLE_VAL; | |
2190 | emac_write(EMAC_RXCONTROL, val); | |
2191 | emac_write(EMAC_MACINTMASKSET, EMAC_MAC_HOST_ERR_INTMASK_VAL); | |
2192 | ||
2193 | for (ch = 0; ch < EMAC_DEF_MAX_TX_CH; ch++) { | |
2194 | emac_write(EMAC_TXHDP(ch), 0); | |
2195 | emac_write(EMAC_TXINTMASKSET, BIT(ch)); | |
2196 | } | |
2197 | for (ch = 0; ch < EMAC_DEF_MAX_RX_CH; ch++) { | |
2198 | struct emac_rxch *rxch = priv->rxch[ch]; | |
2199 | emac_setmac(priv, ch, rxch->mac_addr); | |
2200 | emac_write(EMAC_RXINTMASKSET, BIT(ch)); | |
2201 | rxch->queue_active = 1; | |
2202 | emac_write(EMAC_RXHDP(ch), | |
ad021ae8 | 2203 | emac_virt_to_phys(rxch->active_queue_head, priv)); |
a6286ee6 AG |
2204 | } |
2205 | ||
2206 | /* Enable MII */ | |
2207 | val = emac_read(EMAC_MACCONTROL); | |
69ef9694 | 2208 | val |= (EMAC_MACCONTROL_GMIIEN); |
a6286ee6 AG |
2209 | emac_write(EMAC_MACCONTROL, val); |
2210 | ||
2211 | /* Enable NAPI and interrupts */ | |
2212 | napi_enable(&priv->napi); | |
2213 | emac_int_enable(priv); | |
2214 | return 0; | |
2215 | ||
2216 | } | |
2217 | ||
2218 | /** | |
2219 | * emac_poll: EMAC NAPI Poll function | |
2220 | * @ndev: The DaVinci EMAC network adapter | |
2221 | * @budget: Number of receive packets to process (as told by NAPI layer) | |
2222 | * | |
2223 | * NAPI Poll function implemented to process packets as per budget. We check | |
2224 | * the type of interrupt on the device and accordingly call the TX or RX | |
2225 | * packet processing functions. We follow the budget for RX processing and | |
2226 | * also put a cap on number of TX pkts processed through config param. The | |
2227 | * NAPI schedule function is called if more packets pending. | |
2228 | * | |
2229 | * Returns number of packets received (in most cases; else TX pkts - rarely) | |
2230 | */ | |
2231 | static int emac_poll(struct napi_struct *napi, int budget) | |
2232 | { | |
2233 | unsigned int mask; | |
2234 | struct emac_priv *priv = container_of(napi, struct emac_priv, napi); | |
2235 | struct net_device *ndev = priv->ndev; | |
2236 | struct device *emac_dev = &ndev->dev; | |
2237 | u32 status = 0; | |
3725b1fe | 2238 | u32 num_tx_pkts = 0, num_rx_pkts = 0; |
a6286ee6 | 2239 | |
a6286ee6 AG |
2240 | /* Check interrupt vectors and call packet processing */ |
2241 | status = emac_read(EMAC_MACINVECTOR); | |
2242 | ||
2243 | mask = EMAC_DM644X_MAC_IN_VECTOR_TX_INT_VEC; | |
2244 | ||
2245 | if (priv->version == EMAC_VERSION_2) | |
2246 | mask = EMAC_DM646X_MAC_IN_VECTOR_TX_INT_VEC; | |
2247 | ||
2248 | if (status & mask) { | |
3725b1fe | 2249 | num_tx_pkts = emac_tx_bdproc(priv, EMAC_DEF_TX_CH, |
a6286ee6 AG |
2250 | EMAC_DEF_TX_MAX_SERVICE); |
2251 | } /* TX processing */ | |
2252 | ||
a6286ee6 AG |
2253 | mask = EMAC_DM644X_MAC_IN_VECTOR_RX_INT_VEC; |
2254 | ||
2255 | if (priv->version == EMAC_VERSION_2) | |
2256 | mask = EMAC_DM646X_MAC_IN_VECTOR_RX_INT_VEC; | |
2257 | ||
2258 | if (status & mask) { | |
3725b1fe | 2259 | num_rx_pkts = emac_rx_bdproc(priv, EMAC_DEF_RX_CH, budget); |
a6286ee6 AG |
2260 | } /* RX processing */ |
2261 | ||
43c2ed8e S |
2262 | mask = EMAC_DM644X_MAC_IN_VECTOR_HOST_INT; |
2263 | if (priv->version == EMAC_VERSION_2) | |
2264 | mask = EMAC_DM646X_MAC_IN_VECTOR_HOST_INT; | |
2265 | ||
2266 | if (unlikely(status & mask)) { | |
a6286ee6 AG |
2267 | u32 ch, cause; |
2268 | dev_err(emac_dev, "DaVinci EMAC: Fatal Hardware Error\n"); | |
2269 | netif_stop_queue(ndev); | |
2270 | napi_disable(&priv->napi); | |
2271 | ||
2272 | status = emac_read(EMAC_MACSTATUS); | |
2273 | cause = ((status & EMAC_MACSTATUS_TXERRCODE_MASK) >> | |
2274 | EMAC_MACSTATUS_TXERRCODE_SHIFT); | |
2275 | if (cause) { | |
2276 | ch = ((status & EMAC_MACSTATUS_TXERRCH_MASK) >> | |
2277 | EMAC_MACSTATUS_TXERRCH_SHIFT); | |
2278 | if (net_ratelimit()) { | |
2279 | dev_err(emac_dev, "TX Host error %s on ch=%d\n", | |
2280 | &emac_txhost_errcodes[cause][0], ch); | |
2281 | } | |
2282 | } | |
2283 | cause = ((status & EMAC_MACSTATUS_RXERRCODE_MASK) >> | |
2284 | EMAC_MACSTATUS_RXERRCODE_SHIFT); | |
2285 | if (cause) { | |
2286 | ch = ((status & EMAC_MACSTATUS_RXERRCH_MASK) >> | |
2287 | EMAC_MACSTATUS_RXERRCH_SHIFT); | |
2288 | if (netif_msg_hw(priv) && net_ratelimit()) | |
2289 | dev_err(emac_dev, "RX Host error %s on ch=%d\n", | |
2290 | &emac_rxhost_errcodes[cause][0], ch); | |
2291 | } | |
3725b1fe S |
2292 | } else if (num_rx_pkts < budget) { |
2293 | napi_complete(napi); | |
2294 | emac_int_enable(priv); | |
2295 | } | |
a6286ee6 | 2296 | |
3725b1fe | 2297 | return num_rx_pkts; |
a6286ee6 AG |
2298 | } |
2299 | ||
2300 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
2301 | /** | |
2302 | * emac_poll_controller: EMAC Poll controller function | |
2303 | * @ndev: The DaVinci EMAC network adapter | |
2304 | * | |
2305 | * Polled functionality used by netconsole and others in non interrupt mode | |
2306 | * | |
2307 | */ | |
2308 | void emac_poll_controller(struct net_device *ndev) | |
2309 | { | |
2310 | struct emac_priv *priv = netdev_priv(ndev); | |
2311 | ||
2312 | emac_int_disable(priv); | |
c8ee5538 | 2313 | emac_irq(ndev->irq, ndev); |
a6286ee6 AG |
2314 | emac_int_enable(priv); |
2315 | } | |
2316 | #endif | |
2317 | ||
a6286ee6 AG |
2318 | static void emac_adjust_link(struct net_device *ndev) |
2319 | { | |
2320 | struct emac_priv *priv = netdev_priv(ndev); | |
2321 | struct phy_device *phydev = priv->phydev; | |
2322 | unsigned long flags; | |
2323 | int new_state = 0; | |
2324 | ||
2325 | spin_lock_irqsave(&priv->lock, flags); | |
2326 | ||
2327 | if (phydev->link) { | |
2328 | /* check the mode of operation - full/half duplex */ | |
2329 | if (phydev->duplex != priv->duplex) { | |
2330 | new_state = 1; | |
2331 | priv->duplex = phydev->duplex; | |
2332 | } | |
2333 | if (phydev->speed != priv->speed) { | |
2334 | new_state = 1; | |
2335 | priv->speed = phydev->speed; | |
2336 | } | |
2337 | if (!priv->link) { | |
2338 | new_state = 1; | |
2339 | priv->link = 1; | |
2340 | } | |
2341 | ||
2342 | } else if (priv->link) { | |
2343 | new_state = 1; | |
2344 | priv->link = 0; | |
2345 | priv->speed = 0; | |
2346 | priv->duplex = ~0; | |
2347 | } | |
2348 | if (new_state) { | |
2349 | emac_update_phystatus(priv); | |
2350 | phy_print_status(priv->phydev); | |
2351 | } | |
2352 | ||
2353 | spin_unlock_irqrestore(&priv->lock, flags); | |
2354 | } | |
2355 | ||
2356 | /************************************************************************* | |
2357 | * Linux Driver Model | |
2358 | *************************************************************************/ | |
2359 | ||
2360 | /** | |
2361 | * emac_devioctl: EMAC adapter ioctl | |
2362 | * @ndev: The DaVinci EMAC network adapter | |
2363 | * @ifrq: request parameter | |
2364 | * @cmd: command parameter | |
2365 | * | |
2366 | * EMAC driver ioctl function | |
2367 | * | |
2368 | * Returns success(0) or appropriate error code | |
2369 | */ | |
2370 | static int emac_devioctl(struct net_device *ndev, struct ifreq *ifrq, int cmd) | |
2371 | { | |
2372 | dev_warn(&ndev->dev, "DaVinci EMAC: ioctl not supported\n"); | |
2373 | ||
2374 | if (!(netif_running(ndev))) | |
2375 | return -EINVAL; | |
2376 | ||
2377 | /* TODO: Add phy read and write and private statistics get feature */ | |
2378 | ||
2379 | return -EOPNOTSUPP; | |
2380 | } | |
2381 | ||
5d69e007 CC |
2382 | static int match_first_device(struct device *dev, void *data) |
2383 | { | |
2384 | return 1; | |
2385 | } | |
2386 | ||
a6286ee6 AG |
2387 | /** |
2388 | * emac_dev_open: EMAC device open | |
2389 | * @ndev: The DaVinci EMAC network adapter | |
2390 | * | |
2391 | * Called when system wants to start the interface. We init TX/RX channels | |
2392 | * and enable the hardware for packet reception/transmission and start the | |
2393 | * network queue. | |
2394 | * | |
2395 | * Returns 0 for a successful open, or appropriate error code | |
2396 | */ | |
2397 | static int emac_dev_open(struct net_device *ndev) | |
2398 | { | |
2399 | struct device *emac_dev = &ndev->dev; | |
2400 | u32 rc, cnt, ch; | |
a6286ee6 AG |
2401 | struct resource *res; |
2402 | int q, m; | |
2403 | int i = 0; | |
2404 | int k = 0; | |
2405 | struct emac_priv *priv = netdev_priv(ndev); | |
2406 | ||
2407 | netif_carrier_off(ndev); | |
4d27b877 | 2408 | for (cnt = 0; cnt < ETH_ALEN; cnt++) |
a6286ee6 AG |
2409 | ndev->dev_addr[cnt] = priv->mac_addr[cnt]; |
2410 | ||
2411 | /* Configuration items */ | |
2412 | priv->rx_buf_size = EMAC_DEF_MAX_FRAME_SIZE + NET_IP_ALIGN; | |
2413 | ||
2414 | /* Clear basic hardware */ | |
2415 | for (ch = 0; ch < EMAC_MAX_TXRX_CHANNELS; ch++) { | |
2416 | emac_write(EMAC_TXHDP(ch), 0); | |
2417 | emac_write(EMAC_RXHDP(ch), 0); | |
2418 | emac_write(EMAC_RXHDP(ch), 0); | |
2419 | emac_write(EMAC_RXINTMASKCLEAR, EMAC_INT_MASK_CLEAR); | |
2420 | emac_write(EMAC_TXINTMASKCLEAR, EMAC_INT_MASK_CLEAR); | |
2421 | } | |
2422 | priv->mac_hash1 = 0; | |
2423 | priv->mac_hash2 = 0; | |
2424 | emac_write(EMAC_MACHASH1, 0); | |
2425 | emac_write(EMAC_MACHASH2, 0); | |
2426 | ||
2427 | /* multi ch not supported - open 1 TX, 1RX ch by default */ | |
2428 | rc = emac_init_txch(priv, EMAC_DEF_TX_CH); | |
2429 | if (0 != rc) { | |
2430 | dev_err(emac_dev, "DaVinci EMAC: emac_init_txch() failed"); | |
2431 | return rc; | |
2432 | } | |
2433 | rc = emac_init_rxch(priv, EMAC_DEF_RX_CH, priv->mac_addr); | |
2434 | if (0 != rc) { | |
2435 | dev_err(emac_dev, "DaVinci EMAC: emac_init_rxch() failed"); | |
2436 | return rc; | |
2437 | } | |
2438 | ||
2439 | /* Request IRQ */ | |
2440 | ||
2441 | while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, k))) { | |
2442 | for (i = res->start; i <= res->end; i++) { | |
2443 | if (request_irq(i, emac_irq, IRQF_DISABLED, | |
2444 | ndev->name, ndev)) | |
2445 | goto rollback; | |
2446 | } | |
2447 | k++; | |
2448 | } | |
2449 | ||
2450 | /* Start/Enable EMAC hardware */ | |
2451 | emac_hw_enable(priv); | |
2452 | ||
84da2658 S |
2453 | /* Enable Interrupt pacing if configured */ |
2454 | if (priv->coal_intvl != 0) { | |
2455 | struct ethtool_coalesce coal; | |
2456 | ||
2457 | coal.rx_coalesce_usecs = (priv->coal_intvl << 4); | |
2458 | emac_set_coalesce(ndev, &coal); | |
2459 | } | |
2460 | ||
a6286ee6 | 2461 | priv->phydev = NULL; |
5d69e007 CC |
2462 | /* use the first phy on the bus if pdata did not give us a phy id */ |
2463 | if (!priv->phy_id) { | |
2464 | struct device *phy; | |
a6286ee6 | 2465 | |
5d69e007 CC |
2466 | phy = bus_find_device(&mdio_bus_type, NULL, NULL, |
2467 | match_first_device); | |
2468 | if (phy) | |
2469 | priv->phy_id = dev_name(phy); | |
2470 | } | |
a6286ee6 | 2471 | |
5d69e007 CC |
2472 | if (priv->phy_id && *priv->phy_id) { |
2473 | priv->phydev = phy_connect(ndev, priv->phy_id, | |
2474 | &emac_adjust_link, 0, | |
2475 | PHY_INTERFACE_MODE_MII); | |
a6286ee6 AG |
2476 | |
2477 | if (IS_ERR(priv->phydev)) { | |
5d69e007 CC |
2478 | dev_err(emac_dev, "could not connect to phy %s\n", |
2479 | priv->phy_id); | |
2480 | priv->phydev = NULL; | |
a6286ee6 AG |
2481 | return PTR_ERR(priv->phydev); |
2482 | } | |
2483 | ||
2484 | priv->link = 0; | |
2485 | priv->speed = 0; | |
2486 | priv->duplex = ~0; | |
2487 | ||
5d69e007 CC |
2488 | dev_info(emac_dev, "attached PHY driver [%s] " |
2489 | "(mii_bus:phy_addr=%s, id=%x)\n", | |
a6286ee6 AG |
2490 | priv->phydev->drv->name, dev_name(&priv->phydev->dev), |
2491 | priv->phydev->phy_id); | |
5d69e007 | 2492 | } else { |
a6286ee6 | 2493 | /* No PHY , fix the link, speed and duplex settings */ |
5d69e007 | 2494 | dev_notice(emac_dev, "no phy, defaulting to 100/full\n"); |
a6286ee6 AG |
2495 | priv->link = 1; |
2496 | priv->speed = SPEED_100; | |
2497 | priv->duplex = DUPLEX_FULL; | |
2498 | emac_update_phystatus(priv); | |
2499 | } | |
2500 | ||
2501 | if (!netif_running(ndev)) /* debug only - to avoid compiler warning */ | |
2502 | emac_dump_regs(priv); | |
2503 | ||
2504 | if (netif_msg_drv(priv)) | |
2505 | dev_notice(emac_dev, "DaVinci EMAC: Opened %s\n", ndev->name); | |
2506 | ||
5d69e007 | 2507 | if (priv->phydev) |
a6286ee6 AG |
2508 | phy_start(priv->phydev); |
2509 | ||
2510 | return 0; | |
2511 | ||
2512 | rollback: | |
2513 | ||
2514 | dev_err(emac_dev, "DaVinci EMAC: request_irq() failed"); | |
2515 | ||
2516 | for (q = k; k >= 0; k--) { | |
2517 | for (m = i; m >= res->start; m--) | |
2518 | free_irq(m, ndev); | |
2519 | res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, k-1); | |
2520 | m = res->end; | |
2521 | } | |
2522 | return -EBUSY; | |
2523 | } | |
2524 | ||
2525 | /** | |
2526 | * emac_dev_stop: EMAC device stop | |
2527 | * @ndev: The DaVinci EMAC network adapter | |
2528 | * | |
2529 | * Called when system wants to stop or down the interface. We stop the network | |
2530 | * queue, disable interrupts and cleanup TX/RX channels. | |
2531 | * | |
2532 | * We return the statistics in net_device_stats structure pulled from emac | |
2533 | */ | |
2534 | static int emac_dev_stop(struct net_device *ndev) | |
2535 | { | |
2536 | struct resource *res; | |
2537 | int i = 0; | |
2538 | int irq_num; | |
2539 | struct emac_priv *priv = netdev_priv(ndev); | |
2540 | struct device *emac_dev = &ndev->dev; | |
2541 | ||
2542 | /* inform the upper layers. */ | |
2543 | netif_stop_queue(ndev); | |
2544 | napi_disable(&priv->napi); | |
2545 | ||
2546 | netif_carrier_off(ndev); | |
2547 | emac_int_disable(priv); | |
2548 | emac_stop_txch(priv, EMAC_DEF_TX_CH); | |
2549 | emac_stop_rxch(priv, EMAC_DEF_RX_CH); | |
2550 | emac_cleanup_txch(priv, EMAC_DEF_TX_CH); | |
2551 | emac_cleanup_rxch(priv, EMAC_DEF_RX_CH); | |
2552 | emac_write(EMAC_SOFTRESET, 1); | |
2553 | ||
2554 | if (priv->phydev) | |
2555 | phy_disconnect(priv->phydev); | |
2556 | ||
2557 | /* Free IRQ */ | |
2558 | while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, i))) { | |
2559 | for (irq_num = res->start; irq_num <= res->end; irq_num++) | |
2560 | free_irq(irq_num, priv->ndev); | |
2561 | i++; | |
2562 | } | |
2563 | ||
2564 | if (netif_msg_drv(priv)) | |
2565 | dev_notice(emac_dev, "DaVinci EMAC: %s stopped\n", ndev->name); | |
2566 | ||
2567 | return 0; | |
2568 | } | |
2569 | ||
2570 | /** | |
2571 | * emac_dev_getnetstats: EMAC get statistics function | |
2572 | * @ndev: The DaVinci EMAC network adapter | |
2573 | * | |
2574 | * Called when system wants to get statistics from the device. | |
2575 | * | |
2576 | * We return the statistics in net_device_stats structure pulled from emac | |
2577 | */ | |
2578 | static struct net_device_stats *emac_dev_getnetstats(struct net_device *ndev) | |
2579 | { | |
2580 | struct emac_priv *priv = netdev_priv(ndev); | |
0fe7463a S |
2581 | u32 mac_control; |
2582 | u32 stats_clear_mask; | |
a6286ee6 AG |
2583 | |
2584 | /* update emac hardware stats and reset the registers*/ | |
2585 | ||
0fe7463a S |
2586 | mac_control = emac_read(EMAC_MACCONTROL); |
2587 | ||
2588 | if (mac_control & EMAC_MACCONTROL_GMIIEN) | |
2589 | stats_clear_mask = EMAC_STATS_CLR_MASK; | |
2590 | else | |
2591 | stats_clear_mask = 0; | |
2592 | ||
78e8c532 | 2593 | ndev->stats.multicast += emac_read(EMAC_RXMCASTFRAMES); |
0fe7463a | 2594 | emac_write(EMAC_RXMCASTFRAMES, stats_clear_mask); |
a6286ee6 | 2595 | |
78e8c532 | 2596 | ndev->stats.collisions += (emac_read(EMAC_TXCOLLISION) + |
a6286ee6 AG |
2597 | emac_read(EMAC_TXSINGLECOLL) + |
2598 | emac_read(EMAC_TXMULTICOLL)); | |
0fe7463a S |
2599 | emac_write(EMAC_TXCOLLISION, stats_clear_mask); |
2600 | emac_write(EMAC_TXSINGLECOLL, stats_clear_mask); | |
2601 | emac_write(EMAC_TXMULTICOLL, stats_clear_mask); | |
a6286ee6 | 2602 | |
78e8c532 | 2603 | ndev->stats.rx_length_errors += (emac_read(EMAC_RXOVERSIZED) + |
a6286ee6 AG |
2604 | emac_read(EMAC_RXJABBER) + |
2605 | emac_read(EMAC_RXUNDERSIZED)); | |
0fe7463a S |
2606 | emac_write(EMAC_RXOVERSIZED, stats_clear_mask); |
2607 | emac_write(EMAC_RXJABBER, stats_clear_mask); | |
2608 | emac_write(EMAC_RXUNDERSIZED, stats_clear_mask); | |
a6286ee6 | 2609 | |
78e8c532 | 2610 | ndev->stats.rx_over_errors += (emac_read(EMAC_RXSOFOVERRUNS) + |
a6286ee6 | 2611 | emac_read(EMAC_RXMOFOVERRUNS)); |
0fe7463a S |
2612 | emac_write(EMAC_RXSOFOVERRUNS, stats_clear_mask); |
2613 | emac_write(EMAC_RXMOFOVERRUNS, stats_clear_mask); | |
a6286ee6 | 2614 | |
78e8c532 | 2615 | ndev->stats.rx_fifo_errors += emac_read(EMAC_RXDMAOVERRUNS); |
0fe7463a | 2616 | emac_write(EMAC_RXDMAOVERRUNS, stats_clear_mask); |
a6286ee6 | 2617 | |
78e8c532 | 2618 | ndev->stats.tx_carrier_errors += |
a6286ee6 | 2619 | emac_read(EMAC_TXCARRIERSENSE); |
0fe7463a | 2620 | emac_write(EMAC_TXCARRIERSENSE, stats_clear_mask); |
a6286ee6 | 2621 | |
78e8c532 | 2622 | ndev->stats.tx_fifo_errors = emac_read(EMAC_TXUNDERRUN); |
0fe7463a | 2623 | emac_write(EMAC_TXUNDERRUN, stats_clear_mask); |
a6286ee6 | 2624 | |
78e8c532 | 2625 | return &ndev->stats; |
a6286ee6 AG |
2626 | } |
2627 | ||
2628 | static const struct net_device_ops emac_netdev_ops = { | |
2629 | .ndo_open = emac_dev_open, | |
2630 | .ndo_stop = emac_dev_stop, | |
2631 | .ndo_start_xmit = emac_dev_xmit, | |
2632 | .ndo_set_multicast_list = emac_dev_mcast_set, | |
2633 | .ndo_set_mac_address = emac_dev_setmac_addr, | |
2634 | .ndo_do_ioctl = emac_devioctl, | |
2635 | .ndo_tx_timeout = emac_dev_tx_timeout, | |
2636 | .ndo_get_stats = emac_dev_getnetstats, | |
2637 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
2638 | .ndo_poll_controller = emac_poll_controller, | |
2639 | #endif | |
2640 | }; | |
2641 | ||
2642 | /** | |
2643 | * davinci_emac_probe: EMAC device probe | |
2644 | * @pdev: The DaVinci EMAC device that we are removing | |
2645 | * | |
2646 | * Called when probing for emac devicesr. We get details of instances and | |
2647 | * resource information from platform init and register a network device | |
2648 | * and allocate resources necessary for driver to perform | |
2649 | */ | |
2650 | static int __devinit davinci_emac_probe(struct platform_device *pdev) | |
2651 | { | |
2652 | int rc = 0; | |
2653 | struct resource *res; | |
2654 | struct net_device *ndev; | |
2655 | struct emac_priv *priv; | |
2656 | unsigned long size; | |
2657 | struct emac_platform_data *pdata; | |
2658 | struct device *emac_dev; | |
2659 | ||
2660 | /* obtain emac clock from kernel */ | |
2661 | emac_clk = clk_get(&pdev->dev, NULL); | |
2662 | if (IS_ERR(emac_clk)) { | |
2663 | printk(KERN_ERR "DaVinci EMAC: Failed to get EMAC clock\n"); | |
2664 | return -EBUSY; | |
2665 | } | |
2666 | emac_bus_frequency = clk_get_rate(emac_clk); | |
2667 | /* TODO: Probe PHY here if possible */ | |
2668 | ||
2669 | ndev = alloc_etherdev(sizeof(struct emac_priv)); | |
2670 | if (!ndev) { | |
2671 | printk(KERN_ERR "DaVinci EMAC: Error allocating net_device\n"); | |
2672 | clk_put(emac_clk); | |
2673 | return -ENOMEM; | |
2674 | } | |
2675 | ||
2676 | platform_set_drvdata(pdev, ndev); | |
2677 | priv = netdev_priv(ndev); | |
2678 | priv->pdev = pdev; | |
2679 | priv->ndev = ndev; | |
2680 | priv->msg_enable = netif_msg_init(debug_level, DAVINCI_EMAC_DEBUG); | |
2681 | ||
2682 | spin_lock_init(&priv->tx_lock); | |
2683 | spin_lock_init(&priv->rx_lock); | |
2684 | spin_lock_init(&priv->lock); | |
2685 | ||
2686 | pdata = pdev->dev.platform_data; | |
2687 | if (!pdata) { | |
0747e3bc | 2688 | printk(KERN_ERR "DaVinci EMAC: No platform data\n"); |
a6286ee6 AG |
2689 | return -ENODEV; |
2690 | } | |
2691 | ||
2692 | /* MAC addr and PHY mask , RMII enable info from platform_data */ | |
2693 | memcpy(priv->mac_addr, pdata->mac_addr, 6); | |
5d69e007 | 2694 | priv->phy_id = pdata->phy_id; |
a6286ee6 AG |
2695 | priv->rmii_en = pdata->rmii_en; |
2696 | priv->version = pdata->version; | |
01a9af36 S |
2697 | priv->int_enable = pdata->interrupt_enable; |
2698 | priv->int_disable = pdata->interrupt_disable; | |
2699 | ||
84da2658 S |
2700 | priv->coal_intvl = 0; |
2701 | priv->bus_freq_mhz = (u32)(emac_bus_frequency / 1000000); | |
2702 | ||
a6286ee6 AG |
2703 | emac_dev = &ndev->dev; |
2704 | /* Get EMAC platform data */ | |
2705 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
2706 | if (!res) { | |
2707 | dev_err(emac_dev, "DaVinci EMAC: Error getting res\n"); | |
2708 | rc = -ENOENT; | |
2709 | goto probe_quit; | |
2710 | } | |
2711 | ||
2712 | priv->emac_base_phys = res->start + pdata->ctrl_reg_offset; | |
2713 | size = res->end - res->start + 1; | |
2714 | if (!request_mem_region(res->start, size, ndev->name)) { | |
235ecb1d | 2715 | dev_err(emac_dev, "DaVinci EMAC: failed request_mem_region() for regs\n"); |
a6286ee6 AG |
2716 | rc = -ENXIO; |
2717 | goto probe_quit; | |
2718 | } | |
2719 | ||
2720 | priv->remap_addr = ioremap(res->start, size); | |
2721 | if (!priv->remap_addr) { | |
2722 | dev_err(emac_dev, "Unable to map IO\n"); | |
2723 | rc = -ENOMEM; | |
2724 | release_mem_region(res->start, size); | |
2725 | goto probe_quit; | |
2726 | } | |
2727 | priv->emac_base = priv->remap_addr + pdata->ctrl_reg_offset; | |
2728 | ndev->base_addr = (unsigned long)priv->remap_addr; | |
2729 | ||
2730 | priv->ctrl_base = priv->remap_addr + pdata->ctrl_mod_reg_offset; | |
2731 | priv->ctrl_ram_size = pdata->ctrl_ram_size; | |
2732 | priv->emac_ctrl_ram = priv->remap_addr + pdata->ctrl_ram_offset; | |
2733 | ||
ad021ae8 S |
2734 | if (pdata->hw_ram_addr) |
2735 | priv->hw_ram_addr = pdata->hw_ram_addr; | |
2736 | else | |
2737 | priv->hw_ram_addr = (u32 __force)res->start + | |
2738 | pdata->ctrl_ram_offset; | |
2739 | ||
a6286ee6 AG |
2740 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); |
2741 | if (!res) { | |
2742 | dev_err(emac_dev, "DaVinci EMAC: Error getting irq res\n"); | |
2743 | rc = -ENOENT; | |
2744 | goto no_irq_res; | |
2745 | } | |
2746 | ndev->irq = res->start; | |
2747 | ||
2748 | if (!is_valid_ether_addr(priv->mac_addr)) { | |
a6286ee6 AG |
2749 | /* Use random MAC if none passed */ |
2750 | random_ether_addr(priv->mac_addr); | |
5c726166 C |
2751 | printk(KERN_WARNING "%s: using random MAC addr: %pM\n", |
2752 | __func__, priv->mac_addr); | |
a6286ee6 AG |
2753 | } |
2754 | ||
2755 | ndev->netdev_ops = &emac_netdev_ops; | |
2756 | SET_ETHTOOL_OPS(ndev, ðtool_ops); | |
2757 | netif_napi_add(ndev, &priv->napi, emac_poll, EMAC_POLL_WEIGHT); | |
2758 | ||
1ca518b6 S |
2759 | clk_enable(emac_clk); |
2760 | ||
a6286ee6 AG |
2761 | /* register the network device */ |
2762 | SET_NETDEV_DEV(ndev, &pdev->dev); | |
2763 | rc = register_netdev(ndev); | |
2764 | if (rc) { | |
2765 | dev_err(emac_dev, "DaVinci EMAC: Error in register_netdev\n"); | |
2766 | rc = -ENODEV; | |
2767 | goto netdev_reg_err; | |
2768 | } | |
2769 | ||
a6286ee6 | 2770 | |
a6286ee6 AG |
2771 | if (netif_msg_probe(priv)) { |
2772 | dev_notice(emac_dev, "DaVinci EMAC Probe found device "\ | |
2773 | "(regs: %p, irq: %d)\n", | |
2774 | (void *)priv->emac_base_phys, ndev->irq); | |
2775 | } | |
2776 | return 0; | |
2777 | ||
a6286ee6 | 2778 | netdev_reg_err: |
1ca518b6 | 2779 | clk_disable(emac_clk); |
a6286ee6 AG |
2780 | no_irq_res: |
2781 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
2782 | release_mem_region(res->start, res->end - res->start + 1); | |
2783 | iounmap(priv->remap_addr); | |
2784 | ||
2785 | probe_quit: | |
2786 | clk_put(emac_clk); | |
2787 | free_netdev(ndev); | |
2788 | return rc; | |
2789 | } | |
2790 | ||
2791 | /** | |
2792 | * davinci_emac_remove: EMAC device remove | |
2793 | * @pdev: The DaVinci EMAC device that we are removing | |
2794 | * | |
2795 | * Called when removing the device driver. We disable clock usage and release | |
2796 | * the resources taken up by the driver and unregister network device | |
2797 | */ | |
2798 | static int __devexit davinci_emac_remove(struct platform_device *pdev) | |
2799 | { | |
2800 | struct resource *res; | |
2801 | struct net_device *ndev = platform_get_drvdata(pdev); | |
2802 | struct emac_priv *priv = netdev_priv(ndev); | |
2803 | ||
2804 | dev_notice(&ndev->dev, "DaVinci EMAC: davinci_emac_remove()\n"); | |
2805 | ||
a6286ee6 AG |
2806 | platform_set_drvdata(pdev, NULL); |
2807 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
a6286ee6 AG |
2808 | |
2809 | release_mem_region(res->start, res->end - res->start + 1); | |
2810 | ||
2811 | unregister_netdev(ndev); | |
a6286ee6 | 2812 | iounmap(priv->remap_addr); |
2a1bc0d5 | 2813 | free_netdev(ndev); |
a6286ee6 AG |
2814 | |
2815 | clk_disable(emac_clk); | |
2816 | clk_put(emac_clk); | |
2817 | ||
2818 | return 0; | |
2819 | } | |
2820 | ||
d4fdcd92 | 2821 | static int davinci_emac_suspend(struct device *dev) |
8d044fe6 | 2822 | { |
d4fdcd92 | 2823 | struct platform_device *pdev = to_platform_device(dev); |
2824 | struct net_device *ndev = platform_get_drvdata(pdev); | |
8d044fe6 | 2825 | |
d4fdcd92 | 2826 | if (netif_running(ndev)) |
2827 | emac_dev_stop(ndev); | |
8d044fe6 RL |
2828 | |
2829 | clk_disable(emac_clk); | |
2830 | ||
2831 | return 0; | |
2832 | } | |
2833 | ||
d4fdcd92 | 2834 | static int davinci_emac_resume(struct device *dev) |
8d044fe6 | 2835 | { |
d4fdcd92 | 2836 | struct platform_device *pdev = to_platform_device(dev); |
2837 | struct net_device *ndev = platform_get_drvdata(pdev); | |
8d044fe6 RL |
2838 | |
2839 | clk_enable(emac_clk); | |
2840 | ||
d4fdcd92 | 2841 | if (netif_running(ndev)) |
2842 | emac_dev_open(ndev); | |
8d044fe6 RL |
2843 | |
2844 | return 0; | |
2845 | } | |
2846 | ||
d4fdcd92 | 2847 | static const struct dev_pm_ops davinci_emac_pm_ops = { |
2848 | .suspend = davinci_emac_suspend, | |
2849 | .resume = davinci_emac_resume, | |
2850 | }; | |
2851 | ||
a6286ee6 AG |
2852 | /** |
2853 | * davinci_emac_driver: EMAC platform driver structure | |
a6286ee6 AG |
2854 | */ |
2855 | static struct platform_driver davinci_emac_driver = { | |
2856 | .driver = { | |
2857 | .name = "davinci_emac", | |
2858 | .owner = THIS_MODULE, | |
d4fdcd92 | 2859 | .pm = &davinci_emac_pm_ops, |
a6286ee6 AG |
2860 | }, |
2861 | .probe = davinci_emac_probe, | |
2862 | .remove = __devexit_p(davinci_emac_remove), | |
2863 | }; | |
2864 | ||
2865 | /** | |
2866 | * davinci_emac_init: EMAC driver module init | |
2867 | * | |
2868 | * Called when initializing the driver. We register the driver with | |
2869 | * the platform. | |
2870 | */ | |
2871 | static int __init davinci_emac_init(void) | |
2872 | { | |
2873 | return platform_driver_register(&davinci_emac_driver); | |
2874 | } | |
2db9517e | 2875 | late_initcall(davinci_emac_init); |
a6286ee6 AG |
2876 | |
2877 | /** | |
2878 | * davinci_emac_exit: EMAC driver module exit | |
2879 | * | |
2880 | * Called when exiting the driver completely. We unregister the driver with | |
2881 | * the platform and exit | |
2882 | */ | |
2883 | static void __exit davinci_emac_exit(void) | |
2884 | { | |
2885 | platform_driver_unregister(&davinci_emac_driver); | |
2886 | } | |
2887 | module_exit(davinci_emac_exit); | |
2888 | ||
2889 | MODULE_LICENSE("GPL"); | |
2890 | MODULE_AUTHOR("DaVinci EMAC Maintainer: Anant Gole <anantgole@ti.com>"); | |
2891 | MODULE_AUTHOR("DaVinci EMAC Maintainer: Chaithrika U S <chaithrika@ti.com>"); | |
2892 | MODULE_DESCRIPTION("DaVinci EMAC Ethernet driver"); |