Commit | Line | Data |
---|---|---|
a1365275 | 1 | /* |
41c340f0 | 2 | * Davicom DM9000 Fast Ethernet driver for Linux. |
a1365275 SH |
3 | * Copyright (C) 1997 Sten Wang |
4 | * | |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License | |
7 | * as published by the Free Software Foundation; either version 2 | |
8 | * of the License, or (at your option) any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
41c340f0 | 15 | * (C) Copyright 1997-1998 DAVICOM Semiconductor,Inc. All Rights Reserved. |
9ef9ac51 | 16 | * |
41c340f0 BD |
17 | * Additional updates, Copyright: |
18 | * Ben Dooks <ben@simtec.co.uk> | |
19 | * Sascha Hauer <s.hauer@pengutronix.de> | |
a1365275 SH |
20 | */ |
21 | ||
22 | #include <linux/module.h> | |
23 | #include <linux/ioport.h> | |
24 | #include <linux/netdevice.h> | |
25 | #include <linux/etherdevice.h> | |
26 | #include <linux/init.h> | |
27 | #include <linux/skbuff.h> | |
a1365275 SH |
28 | #include <linux/spinlock.h> |
29 | #include <linux/crc32.h> | |
30 | #include <linux/mii.h> | |
7da99859 | 31 | #include <linux/ethtool.h> |
a1365275 SH |
32 | #include <linux/dm9000.h> |
33 | #include <linux/delay.h> | |
d052d1be | 34 | #include <linux/platform_device.h> |
4e4fc05a | 35 | #include <linux/irq.h> |
a1365275 SH |
36 | |
37 | #include <asm/delay.h> | |
38 | #include <asm/irq.h> | |
39 | #include <asm/io.h> | |
40 | ||
41 | #include "dm9000.h" | |
42 | ||
43 | /* Board/System/Debug information/definition ---------------- */ | |
44 | ||
45 | #define DM9000_PHY 0x40 /* PHY address 0x01 */ | |
46 | ||
a1365275 SH |
47 | #define CARDNAME "dm9000" |
48 | #define PFX CARDNAME ": " | |
7da99859 | 49 | #define DRV_VERSION "1.30" |
a1365275 | 50 | |
f40d24d9 AL |
51 | #ifdef CONFIG_BLACKFIN |
52 | #define readsb insb | |
53 | #define readsw insw | |
54 | #define readsl insl | |
55 | #define writesb outsb | |
56 | #define writesw outsw | |
57 | #define writesl outsl | |
1a5f1c4f | 58 | #define DEFAULT_TRIGGER IRQF_TRIGGER_HIGH |
f40d24d9 | 59 | #else |
1a5f1c4f | 60 | #define DEFAULT_TRIGGER (0) |
f40d24d9 AL |
61 | #endif |
62 | ||
a1365275 SH |
63 | /* |
64 | * Transmit timeout, default 5 seconds. | |
65 | */ | |
66 | static int watchdog = 5000; | |
67 | module_param(watchdog, int, 0400); | |
68 | MODULE_PARM_DESC(watchdog, "transmit timeout in milliseconds"); | |
69 | ||
9a2f037c BD |
70 | /* DM9000 register address locking. |
71 | * | |
72 | * The DM9000 uses an address register to control where data written | |
73 | * to the data register goes. This means that the address register | |
74 | * must be preserved over interrupts or similar calls. | |
75 | * | |
76 | * During interrupt and other critical calls, a spinlock is used to | |
77 | * protect the system, but the calls themselves save the address | |
78 | * in the address register in case they are interrupting another | |
79 | * access to the device. | |
80 | * | |
81 | * For general accesses a lock is provided so that calls which are | |
82 | * allowed to sleep are serialised so that the address register does | |
83 | * not need to be saved. This lock also serves to serialise access | |
84 | * to the EEPROM and PHY access registers which are shared between | |
85 | * these two devices. | |
86 | */ | |
87 | ||
a1365275 SH |
88 | /* Structure/enum declaration ------------------------------- */ |
89 | typedef struct board_info { | |
90 | ||
91 | void __iomem *io_addr; /* Register I/O base address */ | |
92 | void __iomem *io_data; /* Data I/O address */ | |
93 | u16 irq; /* IRQ */ | |
94 | ||
95 | u16 tx_pkt_cnt; | |
96 | u16 queue_pkt_len; | |
97 | u16 queue_start_addr; | |
98 | u16 dbug_cnt; | |
99 | u8 io_mode; /* 0:word, 2:byte */ | |
100 | u8 phy_addr; | |
33ba5091 | 101 | unsigned int flags; |
321f69a4 | 102 | unsigned int in_suspend :1; |
a1365275 | 103 | |
5b2b4ff0 BD |
104 | int debug_level; |
105 | ||
a1365275 SH |
106 | void (*inblk)(void __iomem *port, void *data, int length); |
107 | void (*outblk)(void __iomem *port, void *data, int length); | |
108 | void (*dumpblk)(void __iomem *port, int length); | |
109 | ||
a76836f9 BD |
110 | struct device *dev; /* parent device */ |
111 | ||
a1365275 SH |
112 | struct resource *addr_res; /* resources found */ |
113 | struct resource *data_res; | |
114 | struct resource *addr_req; /* resources requested */ | |
115 | struct resource *data_req; | |
116 | struct resource *irq_res; | |
117 | ||
9a2f037c BD |
118 | struct mutex addr_lock; /* phy and eeprom access lock */ |
119 | ||
a1365275 SH |
120 | spinlock_t lock; |
121 | ||
122 | struct mii_if_info mii; | |
123 | u32 msg_enable; | |
124 | } board_info_t; | |
125 | ||
5b2b4ff0 BD |
126 | /* debug code */ |
127 | ||
128 | #define dm9000_dbg(db, lev, msg...) do { \ | |
129 | if ((lev) < CONFIG_DM9000_DEBUGLEVEL && \ | |
130 | (lev) < db->debug_level) { \ | |
131 | dev_dbg(db->dev, msg); \ | |
132 | } \ | |
133 | } while (0) | |
134 | ||
7da99859 BD |
135 | static inline board_info_t *to_dm9000_board(struct net_device *dev) |
136 | { | |
137 | return dev->priv; | |
138 | } | |
139 | ||
a1365275 | 140 | /* function declaration ------------------------------------- */ |
3ae5eaec | 141 | static int dm9000_probe(struct platform_device *); |
a1365275 SH |
142 | static int dm9000_open(struct net_device *); |
143 | static int dm9000_start_xmit(struct sk_buff *, struct net_device *); | |
144 | static int dm9000_stop(struct net_device *); | |
f42d8aea | 145 | static int dm9000_ioctl(struct net_device *dev, struct ifreq *req, int cmd); |
a1365275 | 146 | |
a1365275 SH |
147 | static void dm9000_init_dm9000(struct net_device *); |
148 | ||
7d12e780 | 149 | static irqreturn_t dm9000_interrupt(int, void *); |
a1365275 SH |
150 | |
151 | static int dm9000_phy_read(struct net_device *dev, int phyaddr_unsused, int reg); | |
152 | static void dm9000_phy_write(struct net_device *dev, int phyaddr_unused, int reg, | |
153 | int value); | |
86c62fab | 154 | |
29d52e54 BD |
155 | static void dm9000_read_eeprom(board_info_t *, int addr, u8 *to); |
156 | static void dm9000_write_eeprom(board_info_t *, int addr, u8 *dp); | |
a1365275 SH |
157 | static void dm9000_rx(struct net_device *); |
158 | static void dm9000_hash_table(struct net_device *); | |
159 | ||
a1365275 SH |
160 | /* DM9000 network board routine ---------------------------- */ |
161 | ||
162 | static void | |
163 | dm9000_reset(board_info_t * db) | |
164 | { | |
a76836f9 BD |
165 | dev_dbg(db->dev, "resetting device\n"); |
166 | ||
a1365275 SH |
167 | /* RESET device */ |
168 | writeb(DM9000_NCR, db->io_addr); | |
169 | udelay(200); | |
170 | writeb(NCR_RST, db->io_data); | |
171 | udelay(200); | |
172 | } | |
173 | ||
174 | /* | |
175 | * Read a byte from I/O port | |
176 | */ | |
177 | static u8 | |
178 | ior(board_info_t * db, int reg) | |
179 | { | |
180 | writeb(reg, db->io_addr); | |
181 | return readb(db->io_data); | |
182 | } | |
183 | ||
184 | /* | |
185 | * Write a byte to I/O port | |
186 | */ | |
187 | ||
188 | static void | |
189 | iow(board_info_t * db, int reg, int value) | |
190 | { | |
191 | writeb(reg, db->io_addr); | |
192 | writeb(value, db->io_data); | |
193 | } | |
194 | ||
195 | /* routines for sending block to chip */ | |
196 | ||
197 | static void dm9000_outblk_8bit(void __iomem *reg, void *data, int count) | |
198 | { | |
199 | writesb(reg, data, count); | |
200 | } | |
201 | ||
202 | static void dm9000_outblk_16bit(void __iomem *reg, void *data, int count) | |
203 | { | |
204 | writesw(reg, data, (count+1) >> 1); | |
205 | } | |
206 | ||
207 | static void dm9000_outblk_32bit(void __iomem *reg, void *data, int count) | |
208 | { | |
209 | writesl(reg, data, (count+3) >> 2); | |
210 | } | |
211 | ||
212 | /* input block from chip to memory */ | |
213 | ||
214 | static void dm9000_inblk_8bit(void __iomem *reg, void *data, int count) | |
215 | { | |
5f6b5517 | 216 | readsb(reg, data, count); |
a1365275 SH |
217 | } |
218 | ||
219 | ||
220 | static void dm9000_inblk_16bit(void __iomem *reg, void *data, int count) | |
221 | { | |
222 | readsw(reg, data, (count+1) >> 1); | |
223 | } | |
224 | ||
225 | static void dm9000_inblk_32bit(void __iomem *reg, void *data, int count) | |
226 | { | |
227 | readsl(reg, data, (count+3) >> 2); | |
228 | } | |
229 | ||
230 | /* dump block from chip to null */ | |
231 | ||
232 | static void dm9000_dumpblk_8bit(void __iomem *reg, int count) | |
233 | { | |
234 | int i; | |
235 | int tmp; | |
236 | ||
237 | for (i = 0; i < count; i++) | |
238 | tmp = readb(reg); | |
239 | } | |
240 | ||
241 | static void dm9000_dumpblk_16bit(void __iomem *reg, int count) | |
242 | { | |
243 | int i; | |
244 | int tmp; | |
245 | ||
246 | count = (count + 1) >> 1; | |
247 | ||
248 | for (i = 0; i < count; i++) | |
249 | tmp = readw(reg); | |
250 | } | |
251 | ||
252 | static void dm9000_dumpblk_32bit(void __iomem *reg, int count) | |
253 | { | |
254 | int i; | |
255 | int tmp; | |
256 | ||
257 | count = (count + 3) >> 2; | |
258 | ||
259 | for (i = 0; i < count; i++) | |
260 | tmp = readl(reg); | |
261 | } | |
262 | ||
263 | /* dm9000_set_io | |
264 | * | |
265 | * select the specified set of io routines to use with the | |
266 | * device | |
267 | */ | |
268 | ||
269 | static void dm9000_set_io(struct board_info *db, int byte_width) | |
270 | { | |
271 | /* use the size of the data resource to work out what IO | |
272 | * routines we want to use | |
273 | */ | |
274 | ||
275 | switch (byte_width) { | |
276 | case 1: | |
277 | db->dumpblk = dm9000_dumpblk_8bit; | |
278 | db->outblk = dm9000_outblk_8bit; | |
279 | db->inblk = dm9000_inblk_8bit; | |
280 | break; | |
281 | ||
a1365275 SH |
282 | |
283 | case 3: | |
a76836f9 BD |
284 | dev_dbg(db->dev, ": 3 byte IO, falling back to 16bit\n"); |
285 | case 2: | |
a1365275 SH |
286 | db->dumpblk = dm9000_dumpblk_16bit; |
287 | db->outblk = dm9000_outblk_16bit; | |
288 | db->inblk = dm9000_inblk_16bit; | |
289 | break; | |
290 | ||
291 | case 4: | |
292 | default: | |
293 | db->dumpblk = dm9000_dumpblk_32bit; | |
294 | db->outblk = dm9000_outblk_32bit; | |
295 | db->inblk = dm9000_inblk_32bit; | |
296 | break; | |
297 | } | |
298 | } | |
299 | ||
300 | ||
301 | /* Our watchdog timed out. Called by the networking layer */ | |
302 | static void dm9000_timeout(struct net_device *dev) | |
303 | { | |
304 | board_info_t *db = (board_info_t *) dev->priv; | |
305 | u8 reg_save; | |
306 | unsigned long flags; | |
307 | ||
308 | /* Save previous register address */ | |
309 | reg_save = readb(db->io_addr); | |
9ef9ac51 | 310 | spin_lock_irqsave(&db->lock,flags); |
a1365275 SH |
311 | |
312 | netif_stop_queue(dev); | |
313 | dm9000_reset(db); | |
314 | dm9000_init_dm9000(dev); | |
315 | /* We can accept TX packets again */ | |
316 | dev->trans_start = jiffies; | |
317 | netif_wake_queue(dev); | |
318 | ||
319 | /* Restore previous register address */ | |
320 | writeb(reg_save, db->io_addr); | |
9ef9ac51 | 321 | spin_unlock_irqrestore(&db->lock,flags); |
a1365275 SH |
322 | } |
323 | ||
2fd0e33f KH |
324 | #ifdef CONFIG_NET_POLL_CONTROLLER |
325 | /* | |
326 | *Used by netconsole | |
327 | */ | |
328 | static void dm9000_poll_controller(struct net_device *dev) | |
329 | { | |
330 | disable_irq(dev->irq); | |
28431146 | 331 | dm9000_interrupt(dev->irq,dev); |
2fd0e33f KH |
332 | enable_irq(dev->irq); |
333 | } | |
334 | #endif | |
a1365275 | 335 | |
f42d8aea BD |
336 | static int dm9000_ioctl(struct net_device *dev, struct ifreq *req, int cmd) |
337 | { | |
338 | board_info_t *dm = to_dm9000_board(dev); | |
339 | ||
340 | if (!netif_running(dev)) | |
341 | return -EINVAL; | |
342 | ||
343 | return generic_mii_ioctl(&dm->mii, if_mii(req), cmd, NULL); | |
344 | } | |
345 | ||
7da99859 BD |
346 | /* ethtool ops */ |
347 | ||
348 | static void dm9000_get_drvinfo(struct net_device *dev, | |
349 | struct ethtool_drvinfo *info) | |
350 | { | |
351 | board_info_t *dm = to_dm9000_board(dev); | |
352 | ||
353 | strcpy(info->driver, CARDNAME); | |
354 | strcpy(info->version, DRV_VERSION); | |
355 | strcpy(info->bus_info, to_platform_device(dm->dev)->name); | |
356 | } | |
357 | ||
e662ee02 BD |
358 | static u32 dm9000_get_msglevel(struct net_device *dev) |
359 | { | |
360 | board_info_t *dm = to_dm9000_board(dev); | |
361 | ||
362 | return dm->msg_enable; | |
363 | } | |
364 | ||
365 | static void dm9000_set_msglevel(struct net_device *dev, u32 value) | |
366 | { | |
367 | board_info_t *dm = to_dm9000_board(dev); | |
368 | ||
369 | dm->msg_enable = value; | |
370 | } | |
371 | ||
7da99859 BD |
372 | static int dm9000_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
373 | { | |
374 | board_info_t *dm = to_dm9000_board(dev); | |
7da99859 | 375 | |
7da99859 | 376 | mii_ethtool_gset(&dm->mii, cmd); |
7da99859 BD |
377 | return 0; |
378 | } | |
379 | ||
380 | static int dm9000_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
381 | { | |
382 | board_info_t *dm = to_dm9000_board(dev); | |
7da99859 | 383 | |
9a2f037c | 384 | return mii_ethtool_sset(&dm->mii, cmd); |
7da99859 BD |
385 | } |
386 | ||
387 | static int dm9000_nway_reset(struct net_device *dev) | |
388 | { | |
389 | board_info_t *dm = to_dm9000_board(dev); | |
390 | return mii_nway_restart(&dm->mii); | |
391 | } | |
392 | ||
393 | static u32 dm9000_get_link(struct net_device *dev) | |
394 | { | |
395 | board_info_t *dm = to_dm9000_board(dev); | |
396 | return mii_link_ok(&dm->mii); | |
397 | } | |
398 | ||
29d52e54 BD |
399 | #define DM_EEPROM_MAGIC (0x444D394B) |
400 | ||
401 | static int dm9000_get_eeprom_len(struct net_device *dev) | |
402 | { | |
403 | return 128; | |
404 | } | |
405 | ||
406 | static int dm9000_get_eeprom(struct net_device *dev, | |
407 | struct ethtool_eeprom *ee, u8 *data) | |
408 | { | |
409 | board_info_t *dm = to_dm9000_board(dev); | |
410 | int offset = ee->offset; | |
411 | int len = ee->len; | |
412 | int i; | |
413 | ||
414 | /* EEPROM access is aligned to two bytes */ | |
415 | ||
416 | if ((len & 1) != 0 || (offset & 1) != 0) | |
417 | return -EINVAL; | |
418 | ||
bb44fb70 BD |
419 | if (dm->flags & DM9000_PLATF_NO_EEPROM) |
420 | return -ENOENT; | |
421 | ||
29d52e54 BD |
422 | ee->magic = DM_EEPROM_MAGIC; |
423 | ||
424 | for (i = 0; i < len; i += 2) | |
425 | dm9000_read_eeprom(dm, (offset + i) / 2, data + i); | |
426 | ||
427 | return 0; | |
428 | } | |
429 | ||
430 | static int dm9000_set_eeprom(struct net_device *dev, | |
431 | struct ethtool_eeprom *ee, u8 *data) | |
432 | { | |
433 | board_info_t *dm = to_dm9000_board(dev); | |
434 | int offset = ee->offset; | |
435 | int len = ee->len; | |
436 | int i; | |
437 | ||
438 | /* EEPROM access is aligned to two bytes */ | |
439 | ||
440 | if ((len & 1) != 0 || (offset & 1) != 0) | |
441 | return -EINVAL; | |
442 | ||
bb44fb70 BD |
443 | if (dm->flags & DM9000_PLATF_NO_EEPROM) |
444 | return -ENOENT; | |
445 | ||
29d52e54 BD |
446 | if (ee->magic != DM_EEPROM_MAGIC) |
447 | return -EINVAL; | |
448 | ||
449 | for (i = 0; i < len; i += 2) | |
450 | dm9000_write_eeprom(dm, (offset + i) / 2, data + i); | |
451 | ||
452 | return 0; | |
453 | } | |
454 | ||
7da99859 BD |
455 | static const struct ethtool_ops dm9000_ethtool_ops = { |
456 | .get_drvinfo = dm9000_get_drvinfo, | |
457 | .get_settings = dm9000_get_settings, | |
458 | .set_settings = dm9000_set_settings, | |
e662ee02 BD |
459 | .get_msglevel = dm9000_get_msglevel, |
460 | .set_msglevel = dm9000_set_msglevel, | |
7da99859 BD |
461 | .nway_reset = dm9000_nway_reset, |
462 | .get_link = dm9000_get_link, | |
29d52e54 BD |
463 | .get_eeprom_len = dm9000_get_eeprom_len, |
464 | .get_eeprom = dm9000_get_eeprom, | |
465 | .set_eeprom = dm9000_set_eeprom, | |
7da99859 BD |
466 | }; |
467 | ||
468 | ||
a1365275 SH |
469 | /* dm9000_release_board |
470 | * | |
471 | * release a board, and any mapped resources | |
472 | */ | |
473 | ||
474 | static void | |
475 | dm9000_release_board(struct platform_device *pdev, struct board_info *db) | |
476 | { | |
477 | if (db->data_res == NULL) { | |
478 | if (db->addr_res != NULL) | |
479 | release_mem_region((unsigned long)db->io_addr, 4); | |
480 | return; | |
481 | } | |
482 | ||
483 | /* unmap our resources */ | |
484 | ||
485 | iounmap(db->io_addr); | |
486 | iounmap(db->io_data); | |
487 | ||
488 | /* release the resources */ | |
489 | ||
490 | if (db->data_req != NULL) { | |
491 | release_resource(db->data_req); | |
492 | kfree(db->data_req); | |
493 | } | |
494 | ||
51985487 DO |
495 | if (db->addr_req != NULL) { |
496 | release_resource(db->addr_req); | |
a1365275 SH |
497 | kfree(db->addr_req); |
498 | } | |
499 | } | |
500 | ||
501 | #define res_size(_r) (((_r)->end - (_r)->start) + 1) | |
502 | ||
503 | /* | |
504 | * Search DM9000 board, allocate space and register it | |
505 | */ | |
506 | static int | |
3ae5eaec | 507 | dm9000_probe(struct platform_device *pdev) |
a1365275 | 508 | { |
a1365275 SH |
509 | struct dm9000_plat_data *pdata = pdev->dev.platform_data; |
510 | struct board_info *db; /* Point a board information structure */ | |
511 | struct net_device *ndev; | |
179c743f | 512 | const unsigned char *mac_src; |
a1365275 SH |
513 | unsigned long base; |
514 | int ret = 0; | |
515 | int iosize; | |
516 | int i; | |
517 | u32 id_val; | |
518 | ||
a1365275 SH |
519 | /* Init network device */ |
520 | ndev = alloc_etherdev(sizeof (struct board_info)); | |
521 | if (!ndev) { | |
a76836f9 | 522 | dev_err(&pdev->dev, "could not allocate device.\n"); |
a1365275 SH |
523 | return -ENOMEM; |
524 | } | |
525 | ||
3ae5eaec | 526 | SET_NETDEV_DEV(ndev, &pdev->dev); |
a1365275 | 527 | |
a76836f9 | 528 | dev_dbg(&pdev->dev, "dm9000_probe()"); |
a1365275 SH |
529 | |
530 | /* setup board info structure */ | |
531 | db = (struct board_info *) ndev->priv; | |
532 | memset(db, 0, sizeof (*db)); | |
533 | ||
a76836f9 BD |
534 | db->dev = &pdev->dev; |
535 | ||
9ef9ac51 | 536 | spin_lock_init(&db->lock); |
9a2f037c | 537 | mutex_init(&db->addr_lock); |
9ef9ac51 | 538 | |
a1365275 SH |
539 | if (pdev->num_resources < 2) { |
540 | ret = -ENODEV; | |
541 | goto out; | |
b4ed03ff | 542 | } else if (pdev->num_resources == 2) { |
a1365275 SH |
543 | base = pdev->resource[0].start; |
544 | ||
545 | if (!request_mem_region(base, 4, ndev->name)) { | |
546 | ret = -EBUSY; | |
547 | goto out; | |
548 | } | |
549 | ||
550 | ndev->base_addr = base; | |
551 | ndev->irq = pdev->resource[1].start; | |
b4ed03ff BD |
552 | db->io_addr = (void __iomem *)base; |
553 | db->io_data = (void __iomem *)(base + 4); | |
a1365275 | 554 | |
f40d24d9 AL |
555 | /* ensure at least we have a default set of IO routines */ |
556 | dm9000_set_io(db, 2); | |
557 | ||
b4ed03ff | 558 | } else { |
a1365275 SH |
559 | db->addr_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
560 | db->data_res = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
561 | db->irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | |
562 | ||
b4ed03ff BD |
563 | if (db->addr_res == NULL || db->data_res == NULL || |
564 | db->irq_res == NULL) { | |
a76836f9 | 565 | dev_err(db->dev, "insufficient resources\n"); |
a1365275 SH |
566 | ret = -ENOENT; |
567 | goto out; | |
568 | } | |
569 | ||
570 | i = res_size(db->addr_res); | |
571 | db->addr_req = request_mem_region(db->addr_res->start, i, | |
572 | pdev->name); | |
573 | ||
574 | if (db->addr_req == NULL) { | |
a76836f9 | 575 | dev_err(db->dev, "cannot claim address reg area\n"); |
a1365275 SH |
576 | ret = -EIO; |
577 | goto out; | |
578 | } | |
579 | ||
580 | db->io_addr = ioremap(db->addr_res->start, i); | |
581 | ||
582 | if (db->io_addr == NULL) { | |
a76836f9 | 583 | dev_err(db->dev, "failed to ioremap address reg\n"); |
a1365275 SH |
584 | ret = -EINVAL; |
585 | goto out; | |
586 | } | |
587 | ||
588 | iosize = res_size(db->data_res); | |
589 | db->data_req = request_mem_region(db->data_res->start, iosize, | |
590 | pdev->name); | |
591 | ||
592 | if (db->data_req == NULL) { | |
a76836f9 | 593 | dev_err(db->dev, "cannot claim data reg area\n"); |
a1365275 SH |
594 | ret = -EIO; |
595 | goto out; | |
596 | } | |
597 | ||
598 | db->io_data = ioremap(db->data_res->start, iosize); | |
599 | ||
600 | if (db->io_data == NULL) { | |
a76836f9 | 601 | dev_err(db->dev,"failed to ioremap data reg\n"); |
a1365275 SH |
602 | ret = -EINVAL; |
603 | goto out; | |
604 | } | |
605 | ||
606 | /* fill in parameters for net-dev structure */ | |
607 | ||
608 | ndev->base_addr = (unsigned long)db->io_addr; | |
609 | ndev->irq = db->irq_res->start; | |
610 | ||
611 | /* ensure at least we have a default set of IO routines */ | |
612 | dm9000_set_io(db, iosize); | |
a1365275 SH |
613 | } |
614 | ||
615 | /* check to see if anything is being over-ridden */ | |
616 | if (pdata != NULL) { | |
617 | /* check to see if the driver wants to over-ride the | |
618 | * default IO width */ | |
619 | ||
620 | if (pdata->flags & DM9000_PLATF_8BITONLY) | |
621 | dm9000_set_io(db, 1); | |
622 | ||
623 | if (pdata->flags & DM9000_PLATF_16BITONLY) | |
624 | dm9000_set_io(db, 2); | |
625 | ||
626 | if (pdata->flags & DM9000_PLATF_32BITONLY) | |
627 | dm9000_set_io(db, 4); | |
628 | ||
629 | /* check to see if there are any IO routine | |
630 | * over-rides */ | |
631 | ||
632 | if (pdata->inblk != NULL) | |
633 | db->inblk = pdata->inblk; | |
634 | ||
635 | if (pdata->outblk != NULL) | |
636 | db->outblk = pdata->outblk; | |
637 | ||
638 | if (pdata->dumpblk != NULL) | |
639 | db->dumpblk = pdata->dumpblk; | |
33ba5091 BD |
640 | |
641 | db->flags = pdata->flags; | |
a1365275 SH |
642 | } |
643 | ||
644 | dm9000_reset(db); | |
645 | ||
646 | /* try two times, DM9000 sometimes gets the first read wrong */ | |
513b6bee | 647 | for (i = 0; i < 8; i++) { |
a1365275 SH |
648 | id_val = ior(db, DM9000_VIDL); |
649 | id_val |= (u32)ior(db, DM9000_VIDH) << 8; | |
650 | id_val |= (u32)ior(db, DM9000_PIDL) << 16; | |
651 | id_val |= (u32)ior(db, DM9000_PIDH) << 24; | |
652 | ||
653 | if (id_val == DM9000_ID) | |
654 | break; | |
a76836f9 | 655 | dev_err(db->dev, "read wrong id 0x%08x\n", id_val); |
a1365275 SH |
656 | } |
657 | ||
658 | if (id_val != DM9000_ID) { | |
a76836f9 | 659 | dev_err(db->dev, "wrong id: 0x%08x\n", id_val); |
418d6f87 MR |
660 | ret = -ENODEV; |
661 | goto out; | |
a1365275 SH |
662 | } |
663 | ||
664 | /* from this point we assume that we have found a DM9000 */ | |
665 | ||
666 | /* driver system function */ | |
667 | ether_setup(ndev); | |
668 | ||
669 | ndev->open = &dm9000_open; | |
670 | ndev->hard_start_xmit = &dm9000_start_xmit; | |
671 | ndev->tx_timeout = &dm9000_timeout; | |
672 | ndev->watchdog_timeo = msecs_to_jiffies(watchdog); | |
673 | ndev->stop = &dm9000_stop; | |
a1365275 | 674 | ndev->set_multicast_list = &dm9000_hash_table; |
7da99859 | 675 | ndev->ethtool_ops = &dm9000_ethtool_ops; |
f42d8aea | 676 | ndev->do_ioctl = &dm9000_ioctl; |
7da99859 | 677 | |
2fd0e33f KH |
678 | #ifdef CONFIG_NET_POLL_CONTROLLER |
679 | ndev->poll_controller = &dm9000_poll_controller; | |
680 | #endif | |
a1365275 | 681 | |
a1365275 SH |
682 | db->msg_enable = NETIF_MSG_LINK; |
683 | db->mii.phy_id_mask = 0x1f; | |
684 | db->mii.reg_num_mask = 0x1f; | |
685 | db->mii.force_media = 0; | |
686 | db->mii.full_duplex = 0; | |
687 | db->mii.dev = ndev; | |
688 | db->mii.mdio_read = dm9000_phy_read; | |
689 | db->mii.mdio_write = dm9000_phy_write; | |
690 | ||
179c743f BD |
691 | mac_src = "eeprom"; |
692 | ||
86c62fab BD |
693 | /* try reading the node address from the attached EEPROM */ |
694 | for (i = 0; i < 6; i += 2) | |
695 | dm9000_read_eeprom(db, i / 2, ndev->dev_addr+i); | |
a1365275 | 696 | |
5b55dda6 BD |
697 | if (!is_valid_ether_addr(ndev->dev_addr)) { |
698 | /* try reading from mac */ | |
179c743f BD |
699 | |
700 | mac_src = "chip"; | |
5b55dda6 BD |
701 | for (i = 0; i < 6; i++) |
702 | ndev->dev_addr[i] = ior(db, i+DM9000_PAR); | |
703 | } | |
704 | ||
a1365275 | 705 | if (!is_valid_ether_addr(ndev->dev_addr)) |
a76836f9 BD |
706 | dev_warn(db->dev, "%s: Invalid ethernet MAC address. Please " |
707 | "set using ifconfig\n", ndev->name); | |
a1365275 | 708 | |
3ae5eaec | 709 | platform_set_drvdata(pdev, ndev); |
a1365275 SH |
710 | ret = register_netdev(ndev); |
711 | ||
712 | if (ret == 0) { | |
0795af57 | 713 | DECLARE_MAC_BUF(mac); |
179c743f | 714 | printk("%s: dm9000 at %p,%p IRQ %d MAC: %s (%s)\n", |
0795af57 | 715 | ndev->name, db->io_addr, db->io_data, ndev->irq, |
179c743f | 716 | print_mac(mac, ndev->dev_addr), mac_src); |
a1365275 SH |
717 | } |
718 | return 0; | |
719 | ||
418d6f87 | 720 | out: |
a76836f9 | 721 | dev_err(db->dev, "not found (%d).\n", ret); |
a1365275 SH |
722 | |
723 | dm9000_release_board(pdev, db); | |
9fd9f9b6 | 724 | free_netdev(ndev); |
a1365275 SH |
725 | |
726 | return ret; | |
727 | } | |
728 | ||
729 | /* | |
730 | * Open the interface. | |
731 | * The interface is opened whenever "ifconfig" actives it. | |
732 | */ | |
733 | static int | |
734 | dm9000_open(struct net_device *dev) | |
735 | { | |
736 | board_info_t *db = (board_info_t *) dev->priv; | |
1a5f1c4f | 737 | unsigned long irqflags = db->irq_res->flags & IRQF_TRIGGER_MASK; |
a1365275 | 738 | |
c991d168 BD |
739 | if (netif_msg_ifup(db)) |
740 | dev_dbg(db->dev, "enabling %s\n", dev->name); | |
a1365275 | 741 | |
1a5f1c4f BD |
742 | /* If there is no IRQ type specified, default to something that |
743 | * may work, and tell the user that this is a problem */ | |
744 | ||
745 | if (irqflags == IRQF_TRIGGER_NONE) { | |
746 | dev_warn(db->dev, "WARNING: no IRQ resource flags set.\n"); | |
747 | irqflags = DEFAULT_TRIGGER; | |
748 | } | |
749 | ||
750 | irqflags |= IRQF_SHARED; | |
751 | ||
752 | if (request_irq(dev->irq, &dm9000_interrupt, irqflags, dev->name, dev)) | |
a1365275 SH |
753 | return -EAGAIN; |
754 | ||
755 | /* Initialize DM9000 board */ | |
756 | dm9000_reset(db); | |
757 | dm9000_init_dm9000(dev); | |
758 | ||
759 | /* Init driver variable */ | |
760 | db->dbug_cnt = 0; | |
761 | ||
a1365275 SH |
762 | mii_check_media(&db->mii, netif_msg_link(db), 1); |
763 | netif_start_queue(dev); | |
764 | ||
765 | return 0; | |
766 | } | |
767 | ||
768 | /* | |
769 | * Initilize dm9000 board | |
770 | */ | |
771 | static void | |
772 | dm9000_init_dm9000(struct net_device *dev) | |
773 | { | |
774 | board_info_t *db = (board_info_t *) dev->priv; | |
775 | ||
5b2b4ff0 | 776 | dm9000_dbg(db, 1, "entering %s\n", __func__); |
a1365275 SH |
777 | |
778 | /* I/O mode */ | |
779 | db->io_mode = ior(db, DM9000_ISR) >> 6; /* ISR bit7:6 keeps I/O mode */ | |
780 | ||
781 | /* GPIO0 on pre-activate PHY */ | |
782 | iow(db, DM9000_GPR, 0); /* REG_1F bit0 activate phyxcer */ | |
783 | iow(db, DM9000_GPCR, GPCR_GEP_CNTL); /* Let GPIO0 output */ | |
784 | iow(db, DM9000_GPR, 0); /* Enable PHY */ | |
785 | ||
33ba5091 BD |
786 | if (db->flags & DM9000_PLATF_EXT_PHY) |
787 | iow(db, DM9000_NCR, NCR_EXT_PHY); | |
788 | ||
a1365275 SH |
789 | /* Program operating register */ |
790 | iow(db, DM9000_TCR, 0); /* TX Polling clear */ | |
791 | iow(db, DM9000_BPTR, 0x3f); /* Less 3Kb, 200us */ | |
792 | iow(db, DM9000_FCR, 0xff); /* Flow Control */ | |
793 | iow(db, DM9000_SMCR, 0); /* Special Mode */ | |
794 | /* clear TX status */ | |
795 | iow(db, DM9000_NSR, NSR_WAKEST | NSR_TX2END | NSR_TX1END); | |
796 | iow(db, DM9000_ISR, ISR_CLR_STATUS); /* Clear interrupt status */ | |
797 | ||
798 | /* Set address filter table */ | |
799 | dm9000_hash_table(dev); | |
800 | ||
801 | /* Activate DM9000 */ | |
802 | iow(db, DM9000_RCR, RCR_DIS_LONG | RCR_DIS_CRC | RCR_RXEN); | |
803 | /* Enable TX/RX interrupt mask */ | |
804 | iow(db, DM9000_IMR, IMR_PAR | IMR_PTM | IMR_PRM); | |
805 | ||
806 | /* Init Driver variable */ | |
807 | db->tx_pkt_cnt = 0; | |
808 | db->queue_pkt_len = 0; | |
809 | dev->trans_start = 0; | |
a1365275 SH |
810 | } |
811 | ||
812 | /* | |
813 | * Hardware start transmission. | |
814 | * Send a packet to media from the upper layer. | |
815 | */ | |
816 | static int | |
817 | dm9000_start_xmit(struct sk_buff *skb, struct net_device *dev) | |
818 | { | |
c46ac946 | 819 | unsigned long flags; |
a1365275 SH |
820 | board_info_t *db = (board_info_t *) dev->priv; |
821 | ||
5b2b4ff0 | 822 | dm9000_dbg(db, 3, "%s:\n", __func__); |
a1365275 SH |
823 | |
824 | if (db->tx_pkt_cnt > 1) | |
825 | return 1; | |
826 | ||
c46ac946 | 827 | spin_lock_irqsave(&db->lock, flags); |
a1365275 SH |
828 | |
829 | /* Move data to DM9000 TX RAM */ | |
830 | writeb(DM9000_MWCMD, db->io_addr); | |
831 | ||
832 | (db->outblk)(db->io_data, skb->data, skb->len); | |
09f75cd7 | 833 | dev->stats.tx_bytes += skb->len; |
a1365275 | 834 | |
c46ac946 | 835 | db->tx_pkt_cnt++; |
a1365275 | 836 | /* TX control: First packet immediately send, second packet queue */ |
c46ac946 | 837 | if (db->tx_pkt_cnt == 1) { |
a1365275 | 838 | /* Set TX length to DM9000 */ |
073d3f46 BD |
839 | iow(db, DM9000_TXPLL, skb->len); |
840 | iow(db, DM9000_TXPLH, skb->len >> 8); | |
a1365275 SH |
841 | |
842 | /* Issue TX polling command */ | |
843 | iow(db, DM9000_TCR, TCR_TXREQ); /* Cleared after TX complete */ | |
844 | ||
845 | dev->trans_start = jiffies; /* save the time stamp */ | |
a1365275 SH |
846 | } else { |
847 | /* Second packet */ | |
a1365275 | 848 | db->queue_pkt_len = skb->len; |
c46ac946 | 849 | netif_stop_queue(dev); |
a1365275 SH |
850 | } |
851 | ||
c46ac946 FW |
852 | spin_unlock_irqrestore(&db->lock, flags); |
853 | ||
a1365275 SH |
854 | /* free this SKB */ |
855 | dev_kfree_skb(skb); | |
856 | ||
a1365275 SH |
857 | return 0; |
858 | } | |
859 | ||
860 | static void | |
861 | dm9000_shutdown(struct net_device *dev) | |
862 | { | |
863 | board_info_t *db = (board_info_t *) dev->priv; | |
864 | ||
865 | /* RESET device */ | |
866 | dm9000_phy_write(dev, 0, MII_BMCR, BMCR_RESET); /* PHY RESET */ | |
867 | iow(db, DM9000_GPR, 0x01); /* Power-Down PHY */ | |
868 | iow(db, DM9000_IMR, IMR_PAR); /* Disable all interrupt */ | |
869 | iow(db, DM9000_RCR, 0x00); /* Disable RX */ | |
870 | } | |
871 | ||
872 | /* | |
873 | * Stop the interface. | |
874 | * The interface is stopped when it is brought. | |
875 | */ | |
876 | static int | |
877 | dm9000_stop(struct net_device *ndev) | |
878 | { | |
879 | board_info_t *db = (board_info_t *) ndev->priv; | |
880 | ||
c991d168 BD |
881 | if (netif_msg_ifdown(db)) |
882 | dev_dbg(db->dev, "shutting down %s\n", ndev->name); | |
a1365275 | 883 | |
a1365275 SH |
884 | netif_stop_queue(ndev); |
885 | netif_carrier_off(ndev); | |
886 | ||
887 | /* free interrupt */ | |
888 | free_irq(ndev->irq, ndev); | |
889 | ||
890 | dm9000_shutdown(ndev); | |
891 | ||
892 | return 0; | |
893 | } | |
894 | ||
895 | /* | |
896 | * DM9000 interrupt handler | |
897 | * receive the packet to upper layer, free the transmitted packet | |
898 | */ | |
899 | ||
5d22a312 | 900 | static void |
a1365275 SH |
901 | dm9000_tx_done(struct net_device *dev, board_info_t * db) |
902 | { | |
903 | int tx_status = ior(db, DM9000_NSR); /* Got TX status */ | |
904 | ||
905 | if (tx_status & (NSR_TX2END | NSR_TX1END)) { | |
906 | /* One packet sent complete */ | |
907 | db->tx_pkt_cnt--; | |
09f75cd7 | 908 | dev->stats.tx_packets++; |
a1365275 | 909 | |
c991d168 BD |
910 | if (netif_msg_tx_done(db)) |
911 | dev_dbg(db->dev, "tx done, NSR %02x\n", tx_status); | |
912 | ||
a1365275 SH |
913 | /* Queue packet check & send */ |
914 | if (db->tx_pkt_cnt > 0) { | |
073d3f46 BD |
915 | iow(db, DM9000_TXPLL, db->queue_pkt_len); |
916 | iow(db, DM9000_TXPLH, db->queue_pkt_len >> 8); | |
a1365275 SH |
917 | iow(db, DM9000_TCR, TCR_TXREQ); |
918 | dev->trans_start = jiffies; | |
919 | } | |
920 | netif_wake_queue(dev); | |
921 | } | |
922 | } | |
923 | ||
924 | static irqreturn_t | |
7d12e780 | 925 | dm9000_interrupt(int irq, void *dev_id) |
a1365275 SH |
926 | { |
927 | struct net_device *dev = dev_id; | |
5b2b4ff0 | 928 | board_info_t *db = (board_info_t *) dev->priv; |
a1365275 SH |
929 | int int_status; |
930 | u8 reg_save; | |
931 | ||
5b2b4ff0 | 932 | dm9000_dbg(db, 3, "entering %s\n", __func__); |
a1365275 SH |
933 | |
934 | /* A real interrupt coming */ | |
5b2b4ff0 | 935 | |
a1365275 SH |
936 | spin_lock(&db->lock); |
937 | ||
938 | /* Save previous register address */ | |
939 | reg_save = readb(db->io_addr); | |
940 | ||
941 | /* Disable all interrupts */ | |
942 | iow(db, DM9000_IMR, IMR_PAR); | |
943 | ||
944 | /* Got DM9000 interrupt status */ | |
945 | int_status = ior(db, DM9000_ISR); /* Got ISR */ | |
946 | iow(db, DM9000_ISR, int_status); /* Clear ISR status */ | |
947 | ||
c991d168 BD |
948 | if (netif_msg_intr(db)) |
949 | dev_dbg(db->dev, "interrupt status %02x\n", int_status); | |
950 | ||
a1365275 SH |
951 | /* Received the coming packet */ |
952 | if (int_status & ISR_PRS) | |
953 | dm9000_rx(dev); | |
954 | ||
955 | /* Trnasmit Interrupt check */ | |
956 | if (int_status & ISR_PTS) | |
957 | dm9000_tx_done(dev, db); | |
958 | ||
959 | /* Re-enable interrupt mask */ | |
960 | iow(db, DM9000_IMR, IMR_PAR | IMR_PTM | IMR_PRM); | |
961 | ||
962 | /* Restore previous register address */ | |
963 | writeb(reg_save, db->io_addr); | |
964 | ||
965 | spin_unlock(&db->lock); | |
966 | ||
967 | return IRQ_HANDLED; | |
968 | } | |
969 | ||
a1365275 | 970 | struct dm9000_rxhdr { |
93116573 BD |
971 | u8 RxPktReady; |
972 | u8 RxStatus; | |
a1365275 SH |
973 | u16 RxLen; |
974 | } __attribute__((__packed__)); | |
975 | ||
976 | /* | |
977 | * Received a packet and pass to upper layer | |
978 | */ | |
979 | static void | |
980 | dm9000_rx(struct net_device *dev) | |
981 | { | |
982 | board_info_t *db = (board_info_t *) dev->priv; | |
983 | struct dm9000_rxhdr rxhdr; | |
984 | struct sk_buff *skb; | |
985 | u8 rxbyte, *rdptr; | |
6478fac6 | 986 | bool GoodPacket; |
a1365275 SH |
987 | int RxLen; |
988 | ||
989 | /* Check packet ready or not */ | |
990 | do { | |
991 | ior(db, DM9000_MRCMDX); /* Dummy read */ | |
992 | ||
993 | /* Get most updated data */ | |
994 | rxbyte = readb(db->io_data); | |
995 | ||
996 | /* Status check: this byte must be 0 or 1 */ | |
997 | if (rxbyte > DM9000_PKT_RDY) { | |
a76836f9 | 998 | dev_warn(db->dev, "status check fail: %d\n", rxbyte); |
a1365275 SH |
999 | iow(db, DM9000_RCR, 0x00); /* Stop Device */ |
1000 | iow(db, DM9000_ISR, IMR_PAR); /* Stop INT request */ | |
1001 | return; | |
1002 | } | |
1003 | ||
1004 | if (rxbyte != DM9000_PKT_RDY) | |
1005 | return; | |
1006 | ||
1007 | /* A packet ready now & Get status/length */ | |
6478fac6 | 1008 | GoodPacket = true; |
a1365275 SH |
1009 | writeb(DM9000_MRCMD, db->io_addr); |
1010 | ||
1011 | (db->inblk)(db->io_data, &rxhdr, sizeof(rxhdr)); | |
1012 | ||
93116573 | 1013 | RxLen = le16_to_cpu(rxhdr.RxLen); |
a1365275 | 1014 | |
c991d168 BD |
1015 | if (netif_msg_rx_status(db)) |
1016 | dev_dbg(db->dev, "RX: status %02x, length %04x\n", | |
1017 | rxhdr.RxStatus, RxLen); | |
1018 | ||
a1365275 SH |
1019 | /* Packet Status check */ |
1020 | if (RxLen < 0x40) { | |
6478fac6 | 1021 | GoodPacket = false; |
c991d168 BD |
1022 | if (netif_msg_rx_err(db)) |
1023 | dev_dbg(db->dev, "RX: Bad Packet (runt)\n"); | |
a1365275 SH |
1024 | } |
1025 | ||
1026 | if (RxLen > DM9000_PKT_MAX) { | |
a76836f9 | 1027 | dev_dbg(db->dev, "RST: RX Len:%x\n", RxLen); |
a1365275 SH |
1028 | } |
1029 | ||
93116573 | 1030 | if (rxhdr.RxStatus & 0xbf) { |
6478fac6 | 1031 | GoodPacket = false; |
93116573 | 1032 | if (rxhdr.RxStatus & 0x01) { |
c991d168 BD |
1033 | if (netif_msg_rx_err(db)) |
1034 | dev_dbg(db->dev, "fifo error\n"); | |
09f75cd7 | 1035 | dev->stats.rx_fifo_errors++; |
a1365275 | 1036 | } |
93116573 | 1037 | if (rxhdr.RxStatus & 0x02) { |
c991d168 BD |
1038 | if (netif_msg_rx_err(db)) |
1039 | dev_dbg(db->dev, "crc error\n"); | |
09f75cd7 | 1040 | dev->stats.rx_crc_errors++; |
a1365275 | 1041 | } |
93116573 | 1042 | if (rxhdr.RxStatus & 0x80) { |
c991d168 BD |
1043 | if (netif_msg_rx_err(db)) |
1044 | dev_dbg(db->dev, "length error\n"); | |
09f75cd7 | 1045 | dev->stats.rx_length_errors++; |
a1365275 SH |
1046 | } |
1047 | } | |
1048 | ||
1049 | /* Move data from DM9000 */ | |
1050 | if (GoodPacket | |
1051 | && ((skb = dev_alloc_skb(RxLen + 4)) != NULL)) { | |
a1365275 SH |
1052 | skb_reserve(skb, 2); |
1053 | rdptr = (u8 *) skb_put(skb, RxLen - 4); | |
1054 | ||
1055 | /* Read received packet from RX SRAM */ | |
1056 | ||
1057 | (db->inblk)(db->io_data, rdptr, RxLen); | |
09f75cd7 | 1058 | dev->stats.rx_bytes += RxLen; |
a1365275 SH |
1059 | |
1060 | /* Pass to upper layer */ | |
1061 | skb->protocol = eth_type_trans(skb, dev); | |
1062 | netif_rx(skb); | |
09f75cd7 | 1063 | dev->stats.rx_packets++; |
a1365275 SH |
1064 | |
1065 | } else { | |
1066 | /* need to dump the packet's data */ | |
1067 | ||
1068 | (db->dumpblk)(db->io_data, RxLen); | |
1069 | } | |
1070 | } while (rxbyte == DM9000_PKT_RDY); | |
1071 | } | |
1072 | ||
39c341a8 BD |
1073 | static unsigned int |
1074 | dm9000_read_locked(board_info_t *db, int reg) | |
1075 | { | |
1076 | unsigned long flags; | |
1077 | unsigned int ret; | |
1078 | ||
1079 | spin_lock_irqsave(&db->lock, flags); | |
1080 | ret = ior(db, reg); | |
1081 | spin_unlock_irqrestore(&db->lock, flags); | |
1082 | ||
1083 | return ret; | |
1084 | } | |
1085 | ||
1086 | static int dm9000_wait_eeprom(board_info_t *db) | |
1087 | { | |
1088 | unsigned int status; | |
1089 | int timeout = 8; /* wait max 8msec */ | |
1090 | ||
1091 | /* The DM9000 data sheets say we should be able to | |
1092 | * poll the ERRE bit in EPCR to wait for the EEPROM | |
1093 | * operation. From testing several chips, this bit | |
1094 | * does not seem to work. | |
1095 | * | |
1096 | * We attempt to use the bit, but fall back to the | |
1097 | * timeout (which is why we do not return an error | |
1098 | * on expiry) to say that the EEPROM operation has | |
1099 | * completed. | |
1100 | */ | |
1101 | ||
1102 | while (1) { | |
1103 | status = dm9000_read_locked(db, DM9000_EPCR); | |
1104 | ||
1105 | if ((status & EPCR_ERRE) == 0) | |
1106 | break; | |
1107 | ||
1108 | if (timeout-- < 0) { | |
1109 | dev_dbg(db->dev, "timeout waiting EEPROM\n"); | |
1110 | break; | |
1111 | } | |
1112 | } | |
1113 | ||
1114 | return 0; | |
1115 | } | |
1116 | ||
a1365275 | 1117 | /* |
86c62fab | 1118 | * Read a word data from EEPROM |
a1365275 | 1119 | */ |
86c62fab | 1120 | static void |
29d52e54 | 1121 | dm9000_read_eeprom(board_info_t *db, int offset, u8 *to) |
a1365275 | 1122 | { |
621ddcb0 BD |
1123 | unsigned long flags; |
1124 | ||
bb44fb70 BD |
1125 | if (db->flags & DM9000_PLATF_NO_EEPROM) { |
1126 | to[0] = 0xff; | |
1127 | to[1] = 0xff; | |
1128 | return; | |
1129 | } | |
1130 | ||
9a2f037c BD |
1131 | mutex_lock(&db->addr_lock); |
1132 | ||
621ddcb0 BD |
1133 | spin_lock_irqsave(&db->lock, flags); |
1134 | ||
a1365275 SH |
1135 | iow(db, DM9000_EPAR, offset); |
1136 | iow(db, DM9000_EPCR, EPCR_ERPRR); | |
621ddcb0 BD |
1137 | |
1138 | spin_unlock_irqrestore(&db->lock, flags); | |
1139 | ||
39c341a8 BD |
1140 | dm9000_wait_eeprom(db); |
1141 | ||
1142 | /* delay for at-least 150uS */ | |
1143 | msleep(1); | |
621ddcb0 BD |
1144 | |
1145 | spin_lock_irqsave(&db->lock, flags); | |
1146 | ||
a1365275 | 1147 | iow(db, DM9000_EPCR, 0x0); |
86c62fab BD |
1148 | |
1149 | to[0] = ior(db, DM9000_EPDRL); | |
1150 | to[1] = ior(db, DM9000_EPDRH); | |
9a2f037c | 1151 | |
621ddcb0 BD |
1152 | spin_unlock_irqrestore(&db->lock, flags); |
1153 | ||
9a2f037c | 1154 | mutex_unlock(&db->addr_lock); |
a1365275 SH |
1155 | } |
1156 | ||
a1365275 SH |
1157 | /* |
1158 | * Write a word data to SROM | |
1159 | */ | |
1160 | static void | |
29d52e54 | 1161 | dm9000_write_eeprom(board_info_t *db, int offset, u8 *data) |
a1365275 | 1162 | { |
621ddcb0 BD |
1163 | unsigned long flags; |
1164 | ||
bb44fb70 BD |
1165 | if (db->flags & DM9000_PLATF_NO_EEPROM) |
1166 | return; | |
1167 | ||
9a2f037c BD |
1168 | mutex_lock(&db->addr_lock); |
1169 | ||
621ddcb0 | 1170 | spin_lock_irqsave(&db->lock, flags); |
a1365275 | 1171 | iow(db, DM9000_EPAR, offset); |
29d52e54 BD |
1172 | iow(db, DM9000_EPDRH, data[1]); |
1173 | iow(db, DM9000_EPDRL, data[0]); | |
a1365275 | 1174 | iow(db, DM9000_EPCR, EPCR_WEP | EPCR_ERPRW); |
621ddcb0 BD |
1175 | spin_unlock_irqrestore(&db->lock, flags); |
1176 | ||
39c341a8 BD |
1177 | dm9000_wait_eeprom(db); |
1178 | ||
1179 | mdelay(1); /* wait at least 150uS to clear */ | |
621ddcb0 BD |
1180 | |
1181 | spin_lock_irqsave(&db->lock, flags); | |
a1365275 | 1182 | iow(db, DM9000_EPCR, 0); |
621ddcb0 | 1183 | spin_unlock_irqrestore(&db->lock, flags); |
9a2f037c BD |
1184 | |
1185 | mutex_unlock(&db->addr_lock); | |
a1365275 SH |
1186 | } |
1187 | ||
a1365275 SH |
1188 | /* |
1189 | * Set DM9000 multicast address | |
1190 | */ | |
1191 | static void | |
1192 | dm9000_hash_table(struct net_device *dev) | |
1193 | { | |
1194 | board_info_t *db = (board_info_t *) dev->priv; | |
1195 | struct dev_mc_list *mcptr = dev->mc_list; | |
1196 | int mc_cnt = dev->mc_count; | |
d39cb786 | 1197 | int i, oft; |
a1365275 | 1198 | u32 hash_val; |
d39cb786 | 1199 | u16 hash_table[4]; |
a1365275 SH |
1200 | unsigned long flags; |
1201 | ||
5b2b4ff0 | 1202 | dm9000_dbg(db, 1, "entering %s\n", __func__); |
a1365275 | 1203 | |
d39cb786 | 1204 | spin_lock_irqsave(&db->lock, flags); |
a1365275 | 1205 | |
d39cb786 | 1206 | for (i = 0, oft = DM9000_PAR; i < 6; i++, oft++) |
a1365275 SH |
1207 | iow(db, oft, dev->dev_addr[i]); |
1208 | ||
1209 | /* Clear Hash Table */ | |
1210 | for (i = 0; i < 4; i++) | |
1211 | hash_table[i] = 0x0; | |
1212 | ||
1213 | /* broadcast address */ | |
1214 | hash_table[3] = 0x8000; | |
1215 | ||
1216 | /* the multicast address in Hash Table : 64 bits */ | |
1217 | for (i = 0; i < mc_cnt; i++, mcptr = mcptr->next) { | |
d39cb786 | 1218 | hash_val = ether_crc_le(6, mcptr->dmi_addr) & 0x3f; |
a1365275 SH |
1219 | hash_table[hash_val / 16] |= (u16) 1 << (hash_val % 16); |
1220 | } | |
1221 | ||
1222 | /* Write the hash table to MAC MD table */ | |
d39cb786 BD |
1223 | for (i = 0, oft = DM9000_MAR; i < 4; i++) { |
1224 | iow(db, oft++, hash_table[i]); | |
1225 | iow(db, oft++, hash_table[i] >> 8); | |
a1365275 SH |
1226 | } |
1227 | ||
d39cb786 | 1228 | spin_unlock_irqrestore(&db->lock, flags); |
a1365275 SH |
1229 | } |
1230 | ||
1231 | ||
321f69a4 BD |
1232 | /* |
1233 | * Sleep, either by using msleep() or if we are suspending, then | |
1234 | * use mdelay() to sleep. | |
1235 | */ | |
1236 | static void dm9000_msleep(board_info_t *db, unsigned int ms) | |
1237 | { | |
1238 | if (db->in_suspend) | |
1239 | mdelay(ms); | |
1240 | else | |
1241 | msleep(ms); | |
1242 | } | |
1243 | ||
a1365275 SH |
1244 | /* |
1245 | * Read a word from phyxcer | |
1246 | */ | |
1247 | static int | |
1248 | dm9000_phy_read(struct net_device *dev, int phy_reg_unused, int reg) | |
1249 | { | |
1250 | board_info_t *db = (board_info_t *) dev->priv; | |
1251 | unsigned long flags; | |
9ef9ac51 | 1252 | unsigned int reg_save; |
a1365275 SH |
1253 | int ret; |
1254 | ||
9a2f037c BD |
1255 | mutex_lock(&db->addr_lock); |
1256 | ||
a1365275 | 1257 | spin_lock_irqsave(&db->lock,flags); |
9ef9ac51 BD |
1258 | |
1259 | /* Save previous register address */ | |
1260 | reg_save = readb(db->io_addr); | |
1261 | ||
a1365275 SH |
1262 | /* Fill the phyxcer register into REG_0C */ |
1263 | iow(db, DM9000_EPAR, DM9000_PHY | reg); | |
1264 | ||
1265 | iow(db, DM9000_EPCR, 0xc); /* Issue phyxcer read command */ | |
89c8b0e6 BD |
1266 | |
1267 | writeb(reg_save, db->io_addr); | |
1268 | spin_unlock_irqrestore(&db->lock,flags); | |
1269 | ||
321f69a4 | 1270 | dm9000_msleep(db, 1); /* Wait read complete */ |
89c8b0e6 BD |
1271 | |
1272 | spin_lock_irqsave(&db->lock,flags); | |
1273 | reg_save = readb(db->io_addr); | |
1274 | ||
a1365275 SH |
1275 | iow(db, DM9000_EPCR, 0x0); /* Clear phyxcer read command */ |
1276 | ||
1277 | /* The read data keeps on REG_0D & REG_0E */ | |
1278 | ret = (ior(db, DM9000_EPDRH) << 8) | ior(db, DM9000_EPDRL); | |
1279 | ||
9ef9ac51 BD |
1280 | /* restore the previous address */ |
1281 | writeb(reg_save, db->io_addr); | |
a1365275 SH |
1282 | spin_unlock_irqrestore(&db->lock,flags); |
1283 | ||
9a2f037c | 1284 | mutex_unlock(&db->addr_lock); |
a1365275 SH |
1285 | return ret; |
1286 | } | |
1287 | ||
1288 | /* | |
1289 | * Write a word to phyxcer | |
1290 | */ | |
1291 | static void | |
1292 | dm9000_phy_write(struct net_device *dev, int phyaddr_unused, int reg, int value) | |
1293 | { | |
1294 | board_info_t *db = (board_info_t *) dev->priv; | |
1295 | unsigned long flags; | |
9ef9ac51 | 1296 | unsigned long reg_save; |
a1365275 | 1297 | |
9a2f037c BD |
1298 | mutex_lock(&db->addr_lock); |
1299 | ||
a1365275 SH |
1300 | spin_lock_irqsave(&db->lock,flags); |
1301 | ||
9ef9ac51 BD |
1302 | /* Save previous register address */ |
1303 | reg_save = readb(db->io_addr); | |
1304 | ||
a1365275 SH |
1305 | /* Fill the phyxcer register into REG_0C */ |
1306 | iow(db, DM9000_EPAR, DM9000_PHY | reg); | |
1307 | ||
1308 | /* Fill the written data into REG_0D & REG_0E */ | |
073d3f46 BD |
1309 | iow(db, DM9000_EPDRL, value); |
1310 | iow(db, DM9000_EPDRH, value >> 8); | |
a1365275 SH |
1311 | |
1312 | iow(db, DM9000_EPCR, 0xa); /* Issue phyxcer write command */ | |
89c8b0e6 BD |
1313 | |
1314 | writeb(reg_save, db->io_addr); | |
9a2f037c | 1315 | spin_unlock_irqrestore(&db->lock, flags); |
89c8b0e6 | 1316 | |
321f69a4 | 1317 | dm9000_msleep(db, 1); /* Wait write complete */ |
89c8b0e6 BD |
1318 | |
1319 | spin_lock_irqsave(&db->lock,flags); | |
1320 | reg_save = readb(db->io_addr); | |
1321 | ||
a1365275 SH |
1322 | iow(db, DM9000_EPCR, 0x0); /* Clear phyxcer write command */ |
1323 | ||
9ef9ac51 BD |
1324 | /* restore the previous address */ |
1325 | writeb(reg_save, db->io_addr); | |
1326 | ||
9a2f037c BD |
1327 | spin_unlock_irqrestore(&db->lock, flags); |
1328 | mutex_unlock(&db->addr_lock); | |
a1365275 SH |
1329 | } |
1330 | ||
1331 | static int | |
3ae5eaec | 1332 | dm9000_drv_suspend(struct platform_device *dev, pm_message_t state) |
a1365275 | 1333 | { |
3ae5eaec | 1334 | struct net_device *ndev = platform_get_drvdata(dev); |
321f69a4 | 1335 | board_info_t *db; |
a1365275 | 1336 | |
9480e307 | 1337 | if (ndev) { |
321f69a4 BD |
1338 | db = (board_info_t *) ndev->priv; |
1339 | db->in_suspend = 1; | |
1340 | ||
a1365275 SH |
1341 | if (netif_running(ndev)) { |
1342 | netif_device_detach(ndev); | |
1343 | dm9000_shutdown(ndev); | |
1344 | } | |
1345 | } | |
1346 | return 0; | |
1347 | } | |
1348 | ||
1349 | static int | |
3ae5eaec | 1350 | dm9000_drv_resume(struct platform_device *dev) |
a1365275 | 1351 | { |
3ae5eaec | 1352 | struct net_device *ndev = platform_get_drvdata(dev); |
a1365275 SH |
1353 | board_info_t *db = (board_info_t *) ndev->priv; |
1354 | ||
9480e307 | 1355 | if (ndev) { |
a1365275 SH |
1356 | |
1357 | if (netif_running(ndev)) { | |
1358 | dm9000_reset(db); | |
1359 | dm9000_init_dm9000(ndev); | |
1360 | ||
1361 | netif_device_attach(ndev); | |
1362 | } | |
321f69a4 BD |
1363 | |
1364 | db->in_suspend = 0; | |
a1365275 SH |
1365 | } |
1366 | return 0; | |
1367 | } | |
1368 | ||
1369 | static int | |
3ae5eaec | 1370 | dm9000_drv_remove(struct platform_device *pdev) |
a1365275 | 1371 | { |
3ae5eaec | 1372 | struct net_device *ndev = platform_get_drvdata(pdev); |
a1365275 | 1373 | |
3ae5eaec | 1374 | platform_set_drvdata(pdev, NULL); |
a1365275 SH |
1375 | |
1376 | unregister_netdev(ndev); | |
1377 | dm9000_release_board(pdev, (board_info_t *) ndev->priv); | |
9fd9f9b6 | 1378 | free_netdev(ndev); /* free device structure */ |
a1365275 | 1379 | |
a76836f9 | 1380 | dev_dbg(&pdev->dev, "released and freed device\n"); |
a1365275 SH |
1381 | return 0; |
1382 | } | |
1383 | ||
3ae5eaec | 1384 | static struct platform_driver dm9000_driver = { |
5d22a312 BD |
1385 | .driver = { |
1386 | .name = "dm9000", | |
1387 | .owner = THIS_MODULE, | |
1388 | }, | |
a1365275 SH |
1389 | .probe = dm9000_probe, |
1390 | .remove = dm9000_drv_remove, | |
1391 | .suspend = dm9000_drv_suspend, | |
1392 | .resume = dm9000_drv_resume, | |
1393 | }; | |
1394 | ||
1395 | static int __init | |
1396 | dm9000_init(void) | |
1397 | { | |
7da99859 | 1398 | printk(KERN_INFO "%s Ethernet Driver, V%s\n", CARDNAME, DRV_VERSION); |
2ae2d77c | 1399 | |
3ae5eaec | 1400 | return platform_driver_register(&dm9000_driver); /* search board and register */ |
a1365275 SH |
1401 | } |
1402 | ||
1403 | static void __exit | |
1404 | dm9000_cleanup(void) | |
1405 | { | |
3ae5eaec | 1406 | platform_driver_unregister(&dm9000_driver); |
a1365275 SH |
1407 | } |
1408 | ||
1409 | module_init(dm9000_init); | |
1410 | module_exit(dm9000_cleanup); | |
1411 | ||
1412 | MODULE_AUTHOR("Sascha Hauer, Ben Dooks"); | |
1413 | MODULE_DESCRIPTION("Davicom DM9000 network driver"); | |
1414 | MODULE_LICENSE("GPL"); |