Commit | Line | Data |
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a1365275 | 1 | /* |
41c340f0 | 2 | * Davicom DM9000 Fast Ethernet driver for Linux. |
a1365275 SH |
3 | * Copyright (C) 1997 Sten Wang |
4 | * | |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License | |
7 | * as published by the Free Software Foundation; either version 2 | |
8 | * of the License, or (at your option) any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
41c340f0 | 15 | * (C) Copyright 1997-1998 DAVICOM Semiconductor,Inc. All Rights Reserved. |
9ef9ac51 | 16 | * |
41c340f0 BD |
17 | * Additional updates, Copyright: |
18 | * Ben Dooks <ben@simtec.co.uk> | |
19 | * Sascha Hauer <s.hauer@pengutronix.de> | |
a1365275 SH |
20 | */ |
21 | ||
22 | #include <linux/module.h> | |
23 | #include <linux/ioport.h> | |
24 | #include <linux/netdevice.h> | |
25 | #include <linux/etherdevice.h> | |
26 | #include <linux/init.h> | |
27 | #include <linux/skbuff.h> | |
a1365275 SH |
28 | #include <linux/spinlock.h> |
29 | #include <linux/crc32.h> | |
30 | #include <linux/mii.h> | |
7da99859 | 31 | #include <linux/ethtool.h> |
a1365275 SH |
32 | #include <linux/dm9000.h> |
33 | #include <linux/delay.h> | |
d052d1be | 34 | #include <linux/platform_device.h> |
4e4fc05a | 35 | #include <linux/irq.h> |
a1365275 SH |
36 | |
37 | #include <asm/delay.h> | |
38 | #include <asm/irq.h> | |
39 | #include <asm/io.h> | |
40 | ||
41 | #include "dm9000.h" | |
42 | ||
43 | /* Board/System/Debug information/definition ---------------- */ | |
44 | ||
45 | #define DM9000_PHY 0x40 /* PHY address 0x01 */ | |
46 | ||
59eae1fa BD |
47 | #define CARDNAME "dm9000" |
48 | #define DRV_VERSION "1.31" | |
a1365275 | 49 | |
f40d24d9 AL |
50 | #ifdef CONFIG_BLACKFIN |
51 | #define readsb insb | |
52 | #define readsw insw | |
53 | #define readsl insl | |
54 | #define writesb outsb | |
55 | #define writesw outsw | |
56 | #define writesl outsl | |
1a5f1c4f | 57 | #define DEFAULT_TRIGGER IRQF_TRIGGER_HIGH |
f40d24d9 | 58 | #else |
1a5f1c4f | 59 | #define DEFAULT_TRIGGER (0) |
f40d24d9 AL |
60 | #endif |
61 | ||
a1365275 SH |
62 | /* |
63 | * Transmit timeout, default 5 seconds. | |
64 | */ | |
65 | static int watchdog = 5000; | |
66 | module_param(watchdog, int, 0400); | |
67 | MODULE_PARM_DESC(watchdog, "transmit timeout in milliseconds"); | |
68 | ||
9a2f037c BD |
69 | /* DM9000 register address locking. |
70 | * | |
71 | * The DM9000 uses an address register to control where data written | |
72 | * to the data register goes. This means that the address register | |
73 | * must be preserved over interrupts or similar calls. | |
74 | * | |
75 | * During interrupt and other critical calls, a spinlock is used to | |
76 | * protect the system, but the calls themselves save the address | |
77 | * in the address register in case they are interrupting another | |
78 | * access to the device. | |
79 | * | |
80 | * For general accesses a lock is provided so that calls which are | |
81 | * allowed to sleep are serialised so that the address register does | |
82 | * not need to be saved. This lock also serves to serialise access | |
83 | * to the EEPROM and PHY access registers which are shared between | |
84 | * these two devices. | |
85 | */ | |
86 | ||
6d406b3c BD |
87 | /* The driver supports the original DM9000E, and now the two newer |
88 | * devices, DM9000A and DM9000B. | |
89 | */ | |
90 | ||
91 | enum dm9000_type { | |
92 | TYPE_DM9000E, /* original DM9000 */ | |
93 | TYPE_DM9000A, | |
94 | TYPE_DM9000B | |
95 | }; | |
96 | ||
a1365275 SH |
97 | /* Structure/enum declaration ------------------------------- */ |
98 | typedef struct board_info { | |
99 | ||
59eae1fa BD |
100 | void __iomem *io_addr; /* Register I/O base address */ |
101 | void __iomem *io_data; /* Data I/O address */ | |
102 | u16 irq; /* IRQ */ | |
a1365275 | 103 | |
59eae1fa BD |
104 | u16 tx_pkt_cnt; |
105 | u16 queue_pkt_len; | |
106 | u16 queue_start_addr; | |
107 | u16 dbug_cnt; | |
108 | u8 io_mode; /* 0:word, 2:byte */ | |
109 | u8 phy_addr; | |
110 | u8 imr_all; | |
111 | ||
112 | unsigned int flags; | |
113 | unsigned int in_suspend :1; | |
114 | int debug_level; | |
a1365275 | 115 | |
6d406b3c | 116 | enum dm9000_type type; |
5b2b4ff0 | 117 | |
a1365275 SH |
118 | void (*inblk)(void __iomem *port, void *data, int length); |
119 | void (*outblk)(void __iomem *port, void *data, int length); | |
120 | void (*dumpblk)(void __iomem *port, int length); | |
121 | ||
a76836f9 BD |
122 | struct device *dev; /* parent device */ |
123 | ||
a1365275 SH |
124 | struct resource *addr_res; /* resources found */ |
125 | struct resource *data_res; | |
126 | struct resource *addr_req; /* resources requested */ | |
127 | struct resource *data_req; | |
128 | struct resource *irq_res; | |
129 | ||
9a2f037c BD |
130 | struct mutex addr_lock; /* phy and eeprom access lock */ |
131 | ||
8f5bf5f2 BD |
132 | struct delayed_work phy_poll; |
133 | struct net_device *ndev; | |
134 | ||
59eae1fa | 135 | spinlock_t lock; |
a1365275 SH |
136 | |
137 | struct mii_if_info mii; | |
59eae1fa | 138 | u32 msg_enable; |
a1365275 SH |
139 | } board_info_t; |
140 | ||
5b2b4ff0 BD |
141 | /* debug code */ |
142 | ||
143 | #define dm9000_dbg(db, lev, msg...) do { \ | |
144 | if ((lev) < CONFIG_DM9000_DEBUGLEVEL && \ | |
145 | (lev) < db->debug_level) { \ | |
146 | dev_dbg(db->dev, msg); \ | |
147 | } \ | |
148 | } while (0) | |
149 | ||
7da99859 BD |
150 | static inline board_info_t *to_dm9000_board(struct net_device *dev) |
151 | { | |
152 | return dev->priv; | |
153 | } | |
154 | ||
a1365275 SH |
155 | /* DM9000 network board routine ---------------------------- */ |
156 | ||
157 | static void | |
158 | dm9000_reset(board_info_t * db) | |
159 | { | |
a76836f9 BD |
160 | dev_dbg(db->dev, "resetting device\n"); |
161 | ||
a1365275 SH |
162 | /* RESET device */ |
163 | writeb(DM9000_NCR, db->io_addr); | |
164 | udelay(200); | |
165 | writeb(NCR_RST, db->io_data); | |
166 | udelay(200); | |
167 | } | |
168 | ||
169 | /* | |
170 | * Read a byte from I/O port | |
171 | */ | |
172 | static u8 | |
173 | ior(board_info_t * db, int reg) | |
174 | { | |
175 | writeb(reg, db->io_addr); | |
176 | return readb(db->io_data); | |
177 | } | |
178 | ||
179 | /* | |
180 | * Write a byte to I/O port | |
181 | */ | |
182 | ||
183 | static void | |
184 | iow(board_info_t * db, int reg, int value) | |
185 | { | |
186 | writeb(reg, db->io_addr); | |
187 | writeb(value, db->io_data); | |
188 | } | |
189 | ||
190 | /* routines for sending block to chip */ | |
191 | ||
192 | static void dm9000_outblk_8bit(void __iomem *reg, void *data, int count) | |
193 | { | |
194 | writesb(reg, data, count); | |
195 | } | |
196 | ||
197 | static void dm9000_outblk_16bit(void __iomem *reg, void *data, int count) | |
198 | { | |
199 | writesw(reg, data, (count+1) >> 1); | |
200 | } | |
201 | ||
202 | static void dm9000_outblk_32bit(void __iomem *reg, void *data, int count) | |
203 | { | |
204 | writesl(reg, data, (count+3) >> 2); | |
205 | } | |
206 | ||
207 | /* input block from chip to memory */ | |
208 | ||
209 | static void dm9000_inblk_8bit(void __iomem *reg, void *data, int count) | |
210 | { | |
5f6b5517 | 211 | readsb(reg, data, count); |
a1365275 SH |
212 | } |
213 | ||
214 | ||
215 | static void dm9000_inblk_16bit(void __iomem *reg, void *data, int count) | |
216 | { | |
217 | readsw(reg, data, (count+1) >> 1); | |
218 | } | |
219 | ||
220 | static void dm9000_inblk_32bit(void __iomem *reg, void *data, int count) | |
221 | { | |
222 | readsl(reg, data, (count+3) >> 2); | |
223 | } | |
224 | ||
225 | /* dump block from chip to null */ | |
226 | ||
227 | static void dm9000_dumpblk_8bit(void __iomem *reg, int count) | |
228 | { | |
229 | int i; | |
230 | int tmp; | |
231 | ||
232 | for (i = 0; i < count; i++) | |
233 | tmp = readb(reg); | |
234 | } | |
235 | ||
236 | static void dm9000_dumpblk_16bit(void __iomem *reg, int count) | |
237 | { | |
238 | int i; | |
239 | int tmp; | |
240 | ||
241 | count = (count + 1) >> 1; | |
242 | ||
243 | for (i = 0; i < count; i++) | |
244 | tmp = readw(reg); | |
245 | } | |
246 | ||
247 | static void dm9000_dumpblk_32bit(void __iomem *reg, int count) | |
248 | { | |
249 | int i; | |
250 | int tmp; | |
251 | ||
252 | count = (count + 3) >> 2; | |
253 | ||
254 | for (i = 0; i < count; i++) | |
255 | tmp = readl(reg); | |
256 | } | |
257 | ||
258 | /* dm9000_set_io | |
259 | * | |
260 | * select the specified set of io routines to use with the | |
261 | * device | |
262 | */ | |
263 | ||
264 | static void dm9000_set_io(struct board_info *db, int byte_width) | |
265 | { | |
266 | /* use the size of the data resource to work out what IO | |
267 | * routines we want to use | |
268 | */ | |
269 | ||
270 | switch (byte_width) { | |
271 | case 1: | |
272 | db->dumpblk = dm9000_dumpblk_8bit; | |
273 | db->outblk = dm9000_outblk_8bit; | |
274 | db->inblk = dm9000_inblk_8bit; | |
275 | break; | |
276 | ||
a1365275 SH |
277 | |
278 | case 3: | |
a76836f9 BD |
279 | dev_dbg(db->dev, ": 3 byte IO, falling back to 16bit\n"); |
280 | case 2: | |
a1365275 SH |
281 | db->dumpblk = dm9000_dumpblk_16bit; |
282 | db->outblk = dm9000_outblk_16bit; | |
283 | db->inblk = dm9000_inblk_16bit; | |
284 | break; | |
285 | ||
286 | case 4: | |
287 | default: | |
288 | db->dumpblk = dm9000_dumpblk_32bit; | |
289 | db->outblk = dm9000_outblk_32bit; | |
290 | db->inblk = dm9000_inblk_32bit; | |
291 | break; | |
292 | } | |
293 | } | |
294 | ||
8f5bf5f2 BD |
295 | static void dm9000_schedule_poll(board_info_t *db) |
296 | { | |
6d406b3c BD |
297 | if (db->type == TYPE_DM9000E) |
298 | schedule_delayed_work(&db->phy_poll, HZ * 2); | |
8f5bf5f2 | 299 | } |
a1365275 | 300 | |
f8d79e79 BD |
301 | static int dm9000_ioctl(struct net_device *dev, struct ifreq *req, int cmd) |
302 | { | |
303 | board_info_t *dm = to_dm9000_board(dev); | |
304 | ||
305 | if (!netif_running(dev)) | |
306 | return -EINVAL; | |
307 | ||
308 | return generic_mii_ioctl(&dm->mii, if_mii(req), cmd, NULL); | |
309 | } | |
310 | ||
311 | static unsigned int | |
312 | dm9000_read_locked(board_info_t *db, int reg) | |
a1365275 | 313 | { |
a1365275 | 314 | unsigned long flags; |
f8d79e79 | 315 | unsigned int ret; |
a1365275 | 316 | |
f8d79e79 BD |
317 | spin_lock_irqsave(&db->lock, flags); |
318 | ret = ior(db, reg); | |
319 | spin_unlock_irqrestore(&db->lock, flags); | |
a1365275 | 320 | |
f8d79e79 BD |
321 | return ret; |
322 | } | |
a1365275 | 323 | |
f8d79e79 BD |
324 | static int dm9000_wait_eeprom(board_info_t *db) |
325 | { | |
326 | unsigned int status; | |
327 | int timeout = 8; /* wait max 8msec */ | |
328 | ||
329 | /* The DM9000 data sheets say we should be able to | |
330 | * poll the ERRE bit in EPCR to wait for the EEPROM | |
331 | * operation. From testing several chips, this bit | |
332 | * does not seem to work. | |
333 | * | |
334 | * We attempt to use the bit, but fall back to the | |
335 | * timeout (which is why we do not return an error | |
336 | * on expiry) to say that the EEPROM operation has | |
337 | * completed. | |
338 | */ | |
339 | ||
340 | while (1) { | |
341 | status = dm9000_read_locked(db, DM9000_EPCR); | |
342 | ||
343 | if ((status & EPCR_ERRE) == 0) | |
344 | break; | |
345 | ||
346 | if (timeout-- < 0) { | |
347 | dev_dbg(db->dev, "timeout waiting EEPROM\n"); | |
348 | break; | |
349 | } | |
350 | } | |
351 | ||
352 | return 0; | |
a1365275 SH |
353 | } |
354 | ||
2fd0e33f | 355 | /* |
f8d79e79 | 356 | * Read a word data from EEPROM |
2fd0e33f | 357 | */ |
f8d79e79 BD |
358 | static void |
359 | dm9000_read_eeprom(board_info_t *db, int offset, u8 *to) | |
2fd0e33f | 360 | { |
f8d79e79 BD |
361 | unsigned long flags; |
362 | ||
363 | if (db->flags & DM9000_PLATF_NO_EEPROM) { | |
364 | to[0] = 0xff; | |
365 | to[1] = 0xff; | |
366 | return; | |
367 | } | |
368 | ||
369 | mutex_lock(&db->addr_lock); | |
370 | ||
371 | spin_lock_irqsave(&db->lock, flags); | |
372 | ||
373 | iow(db, DM9000_EPAR, offset); | |
374 | iow(db, DM9000_EPCR, EPCR_ERPRR); | |
375 | ||
376 | spin_unlock_irqrestore(&db->lock, flags); | |
377 | ||
378 | dm9000_wait_eeprom(db); | |
379 | ||
380 | /* delay for at-least 150uS */ | |
381 | msleep(1); | |
382 | ||
383 | spin_lock_irqsave(&db->lock, flags); | |
384 | ||
385 | iow(db, DM9000_EPCR, 0x0); | |
386 | ||
387 | to[0] = ior(db, DM9000_EPDRL); | |
388 | to[1] = ior(db, DM9000_EPDRH); | |
389 | ||
390 | spin_unlock_irqrestore(&db->lock, flags); | |
391 | ||
392 | mutex_unlock(&db->addr_lock); | |
2fd0e33f | 393 | } |
a1365275 | 394 | |
f8d79e79 BD |
395 | /* |
396 | * Write a word data to SROM | |
397 | */ | |
398 | static void | |
399 | dm9000_write_eeprom(board_info_t *db, int offset, u8 *data) | |
f42d8aea | 400 | { |
f8d79e79 | 401 | unsigned long flags; |
f42d8aea | 402 | |
f8d79e79 BD |
403 | if (db->flags & DM9000_PLATF_NO_EEPROM) |
404 | return; | |
f42d8aea | 405 | |
f8d79e79 BD |
406 | mutex_lock(&db->addr_lock); |
407 | ||
408 | spin_lock_irqsave(&db->lock, flags); | |
409 | iow(db, DM9000_EPAR, offset); | |
410 | iow(db, DM9000_EPDRH, data[1]); | |
411 | iow(db, DM9000_EPDRL, data[0]); | |
412 | iow(db, DM9000_EPCR, EPCR_WEP | EPCR_ERPRW); | |
413 | spin_unlock_irqrestore(&db->lock, flags); | |
414 | ||
415 | dm9000_wait_eeprom(db); | |
416 | ||
417 | mdelay(1); /* wait at least 150uS to clear */ | |
418 | ||
419 | spin_lock_irqsave(&db->lock, flags); | |
420 | iow(db, DM9000_EPCR, 0); | |
421 | spin_unlock_irqrestore(&db->lock, flags); | |
422 | ||
423 | mutex_unlock(&db->addr_lock); | |
f42d8aea BD |
424 | } |
425 | ||
7da99859 BD |
426 | /* ethtool ops */ |
427 | ||
428 | static void dm9000_get_drvinfo(struct net_device *dev, | |
429 | struct ethtool_drvinfo *info) | |
430 | { | |
431 | board_info_t *dm = to_dm9000_board(dev); | |
432 | ||
433 | strcpy(info->driver, CARDNAME); | |
434 | strcpy(info->version, DRV_VERSION); | |
435 | strcpy(info->bus_info, to_platform_device(dm->dev)->name); | |
436 | } | |
437 | ||
e662ee02 BD |
438 | static u32 dm9000_get_msglevel(struct net_device *dev) |
439 | { | |
440 | board_info_t *dm = to_dm9000_board(dev); | |
441 | ||
442 | return dm->msg_enable; | |
443 | } | |
444 | ||
445 | static void dm9000_set_msglevel(struct net_device *dev, u32 value) | |
446 | { | |
447 | board_info_t *dm = to_dm9000_board(dev); | |
448 | ||
449 | dm->msg_enable = value; | |
450 | } | |
451 | ||
7da99859 BD |
452 | static int dm9000_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
453 | { | |
454 | board_info_t *dm = to_dm9000_board(dev); | |
7da99859 | 455 | |
7da99859 | 456 | mii_ethtool_gset(&dm->mii, cmd); |
7da99859 BD |
457 | return 0; |
458 | } | |
459 | ||
460 | static int dm9000_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
461 | { | |
462 | board_info_t *dm = to_dm9000_board(dev); | |
7da99859 | 463 | |
9a2f037c | 464 | return mii_ethtool_sset(&dm->mii, cmd); |
7da99859 BD |
465 | } |
466 | ||
467 | static int dm9000_nway_reset(struct net_device *dev) | |
468 | { | |
469 | board_info_t *dm = to_dm9000_board(dev); | |
470 | return mii_nway_restart(&dm->mii); | |
471 | } | |
472 | ||
473 | static u32 dm9000_get_link(struct net_device *dev) | |
474 | { | |
475 | board_info_t *dm = to_dm9000_board(dev); | |
aa1eb452 BD |
476 | u32 ret; |
477 | ||
478 | if (dm->flags & DM9000_PLATF_EXT_PHY) | |
479 | ret = mii_link_ok(&dm->mii); | |
480 | else | |
481 | ret = dm9000_read_locked(dm, DM9000_NSR) & NSR_LINKST ? 1 : 0; | |
482 | ||
483 | return ret; | |
7da99859 BD |
484 | } |
485 | ||
29d52e54 BD |
486 | #define DM_EEPROM_MAGIC (0x444D394B) |
487 | ||
488 | static int dm9000_get_eeprom_len(struct net_device *dev) | |
489 | { | |
490 | return 128; | |
491 | } | |
492 | ||
493 | static int dm9000_get_eeprom(struct net_device *dev, | |
494 | struct ethtool_eeprom *ee, u8 *data) | |
495 | { | |
496 | board_info_t *dm = to_dm9000_board(dev); | |
497 | int offset = ee->offset; | |
498 | int len = ee->len; | |
499 | int i; | |
500 | ||
501 | /* EEPROM access is aligned to two bytes */ | |
502 | ||
503 | if ((len & 1) != 0 || (offset & 1) != 0) | |
504 | return -EINVAL; | |
505 | ||
bb44fb70 BD |
506 | if (dm->flags & DM9000_PLATF_NO_EEPROM) |
507 | return -ENOENT; | |
508 | ||
29d52e54 BD |
509 | ee->magic = DM_EEPROM_MAGIC; |
510 | ||
511 | for (i = 0; i < len; i += 2) | |
512 | dm9000_read_eeprom(dm, (offset + i) / 2, data + i); | |
513 | ||
514 | return 0; | |
515 | } | |
516 | ||
517 | static int dm9000_set_eeprom(struct net_device *dev, | |
518 | struct ethtool_eeprom *ee, u8 *data) | |
519 | { | |
520 | board_info_t *dm = to_dm9000_board(dev); | |
521 | int offset = ee->offset; | |
522 | int len = ee->len; | |
523 | int i; | |
524 | ||
525 | /* EEPROM access is aligned to two bytes */ | |
526 | ||
527 | if ((len & 1) != 0 || (offset & 1) != 0) | |
528 | return -EINVAL; | |
529 | ||
bb44fb70 BD |
530 | if (dm->flags & DM9000_PLATF_NO_EEPROM) |
531 | return -ENOENT; | |
532 | ||
29d52e54 BD |
533 | if (ee->magic != DM_EEPROM_MAGIC) |
534 | return -EINVAL; | |
535 | ||
536 | for (i = 0; i < len; i += 2) | |
537 | dm9000_write_eeprom(dm, (offset + i) / 2, data + i); | |
538 | ||
539 | return 0; | |
540 | } | |
541 | ||
7da99859 BD |
542 | static const struct ethtool_ops dm9000_ethtool_ops = { |
543 | .get_drvinfo = dm9000_get_drvinfo, | |
544 | .get_settings = dm9000_get_settings, | |
545 | .set_settings = dm9000_set_settings, | |
e662ee02 BD |
546 | .get_msglevel = dm9000_get_msglevel, |
547 | .set_msglevel = dm9000_set_msglevel, | |
7da99859 BD |
548 | .nway_reset = dm9000_nway_reset, |
549 | .get_link = dm9000_get_link, | |
29d52e54 BD |
550 | .get_eeprom_len = dm9000_get_eeprom_len, |
551 | .get_eeprom = dm9000_get_eeprom, | |
552 | .set_eeprom = dm9000_set_eeprom, | |
7da99859 BD |
553 | }; |
554 | ||
8f5bf5f2 BD |
555 | static void |
556 | dm9000_poll_work(struct work_struct *w) | |
557 | { | |
558 | struct delayed_work *dw = container_of(w, struct delayed_work, work); | |
559 | board_info_t *db = container_of(dw, board_info_t, phy_poll); | |
560 | ||
561 | mii_check_media(&db->mii, netif_msg_link(db), 0); | |
562 | ||
563 | if (netif_running(db->ndev)) | |
564 | dm9000_schedule_poll(db); | |
565 | } | |
7da99859 | 566 | |
a1365275 SH |
567 | /* dm9000_release_board |
568 | * | |
569 | * release a board, and any mapped resources | |
570 | */ | |
571 | ||
572 | static void | |
573 | dm9000_release_board(struct platform_device *pdev, struct board_info *db) | |
574 | { | |
a1365275 SH |
575 | /* unmap our resources */ |
576 | ||
577 | iounmap(db->io_addr); | |
578 | iounmap(db->io_data); | |
579 | ||
580 | /* release the resources */ | |
581 | ||
9088fa4f BD |
582 | release_resource(db->data_req); |
583 | kfree(db->data_req); | |
a1365275 | 584 | |
9088fa4f BD |
585 | release_resource(db->addr_req); |
586 | kfree(db->addr_req); | |
a1365275 SH |
587 | } |
588 | ||
6d406b3c BD |
589 | static unsigned char dm9000_type_to_char(enum dm9000_type type) |
590 | { | |
591 | switch (type) { | |
592 | case TYPE_DM9000E: return 'e'; | |
593 | case TYPE_DM9000A: return 'a'; | |
594 | case TYPE_DM9000B: return 'b'; | |
595 | } | |
596 | ||
597 | return '?'; | |
598 | } | |
599 | ||
a1365275 | 600 | /* |
f8d79e79 | 601 | * Set DM9000 multicast address |
a1365275 | 602 | */ |
f8d79e79 BD |
603 | static void |
604 | dm9000_hash_table(struct net_device *dev) | |
a1365275 | 605 | { |
f8d79e79 BD |
606 | board_info_t *db = (board_info_t *) dev->priv; |
607 | struct dev_mc_list *mcptr = dev->mc_list; | |
608 | int mc_cnt = dev->mc_count; | |
609 | int i, oft; | |
610 | u32 hash_val; | |
611 | u16 hash_table[4]; | |
612 | u8 rcr = RCR_DIS_LONG | RCR_DIS_CRC | RCR_RXEN; | |
613 | unsigned long flags; | |
a1365275 | 614 | |
f8d79e79 | 615 | dm9000_dbg(db, 1, "entering %s\n", __func__); |
a1365275 | 616 | |
f8d79e79 | 617 | spin_lock_irqsave(&db->lock, flags); |
a1365275 | 618 | |
f8d79e79 BD |
619 | for (i = 0, oft = DM9000_PAR; i < 6; i++, oft++) |
620 | iow(db, oft, dev->dev_addr[i]); | |
a1365275 | 621 | |
f8d79e79 BD |
622 | /* Clear Hash Table */ |
623 | for (i = 0; i < 4; i++) | |
624 | hash_table[i] = 0x0; | |
a76836f9 | 625 | |
f8d79e79 BD |
626 | /* broadcast address */ |
627 | hash_table[3] = 0x8000; | |
9ef9ac51 | 628 | |
f8d79e79 BD |
629 | if (dev->flags & IFF_PROMISC) |
630 | rcr |= RCR_PRMSC; | |
8f5bf5f2 | 631 | |
f8d79e79 BD |
632 | if (dev->flags & IFF_ALLMULTI) |
633 | rcr |= RCR_ALL; | |
08c3f57c | 634 | |
f8d79e79 BD |
635 | /* the multicast address in Hash Table : 64 bits */ |
636 | for (i = 0; i < mc_cnt; i++, mcptr = mcptr->next) { | |
637 | hash_val = ether_crc_le(6, mcptr->dmi_addr) & 0x3f; | |
638 | hash_table[hash_val / 16] |= (u16) 1 << (hash_val % 16); | |
08c3f57c LP |
639 | } |
640 | ||
f8d79e79 BD |
641 | /* Write the hash table to MAC MD table */ |
642 | for (i = 0, oft = DM9000_MAR; i < 4; i++) { | |
643 | iow(db, oft++, hash_table[i]); | |
644 | iow(db, oft++, hash_table[i] >> 8); | |
08c3f57c LP |
645 | } |
646 | ||
f8d79e79 BD |
647 | iow(db, DM9000_RCR, rcr); |
648 | spin_unlock_irqrestore(&db->lock, flags); | |
649 | } | |
08c3f57c | 650 | |
f8d79e79 BD |
651 | /* |
652 | * Initilize dm9000 board | |
653 | */ | |
654 | static void | |
655 | dm9000_init_dm9000(struct net_device *dev) | |
656 | { | |
657 | board_info_t *db = dev->priv; | |
658 | unsigned int imr; | |
08c3f57c | 659 | |
f8d79e79 | 660 | dm9000_dbg(db, 1, "entering %s\n", __func__); |
08c3f57c | 661 | |
f8d79e79 BD |
662 | /* I/O mode */ |
663 | db->io_mode = ior(db, DM9000_ISR) >> 6; /* ISR bit7:6 keeps I/O mode */ | |
08c3f57c | 664 | |
f8d79e79 BD |
665 | /* GPIO0 on pre-activate PHY */ |
666 | iow(db, DM9000_GPR, 0); /* REG_1F bit0 activate phyxcer */ | |
667 | iow(db, DM9000_GPCR, GPCR_GEP_CNTL); /* Let GPIO0 output */ | |
668 | iow(db, DM9000_GPR, 0); /* Enable PHY */ | |
08c3f57c | 669 | |
f8d79e79 BD |
670 | if (db->flags & DM9000_PLATF_EXT_PHY) |
671 | iow(db, DM9000_NCR, NCR_EXT_PHY); | |
33ba5091 | 672 | |
a1365275 SH |
673 | /* Program operating register */ |
674 | iow(db, DM9000_TCR, 0); /* TX Polling clear */ | |
675 | iow(db, DM9000_BPTR, 0x3f); /* Less 3Kb, 200us */ | |
676 | iow(db, DM9000_FCR, 0xff); /* Flow Control */ | |
677 | iow(db, DM9000_SMCR, 0); /* Special Mode */ | |
678 | /* clear TX status */ | |
679 | iow(db, DM9000_NSR, NSR_WAKEST | NSR_TX2END | NSR_TX1END); | |
680 | iow(db, DM9000_ISR, ISR_CLR_STATUS); /* Clear interrupt status */ | |
681 | ||
682 | /* Set address filter table */ | |
683 | dm9000_hash_table(dev); | |
684 | ||
6d406b3c BD |
685 | imr = IMR_PAR | IMR_PTM | IMR_PRM; |
686 | if (db->type != TYPE_DM9000E) | |
687 | imr |= IMR_LNKCHNG; | |
688 | ||
689 | db->imr_all = imr; | |
690 | ||
a1365275 | 691 | /* Enable TX/RX interrupt mask */ |
6d406b3c | 692 | iow(db, DM9000_IMR, imr); |
a1365275 SH |
693 | |
694 | /* Init Driver variable */ | |
695 | db->tx_pkt_cnt = 0; | |
696 | db->queue_pkt_len = 0; | |
697 | dev->trans_start = 0; | |
a1365275 SH |
698 | } |
699 | ||
f8d79e79 BD |
700 | /* Our watchdog timed out. Called by the networking layer */ |
701 | static void dm9000_timeout(struct net_device *dev) | |
702 | { | |
703 | board_info_t *db = (board_info_t *) dev->priv; | |
704 | u8 reg_save; | |
705 | unsigned long flags; | |
706 | ||
707 | /* Save previous register address */ | |
708 | reg_save = readb(db->io_addr); | |
709 | spin_lock_irqsave(&db->lock, flags); | |
710 | ||
711 | netif_stop_queue(dev); | |
712 | dm9000_reset(db); | |
713 | dm9000_init_dm9000(dev); | |
714 | /* We can accept TX packets again */ | |
715 | dev->trans_start = jiffies; | |
716 | netif_wake_queue(dev); | |
717 | ||
718 | /* Restore previous register address */ | |
719 | writeb(reg_save, db->io_addr); | |
720 | spin_unlock_irqrestore(&db->lock, flags); | |
721 | } | |
722 | ||
a1365275 SH |
723 | /* |
724 | * Hardware start transmission. | |
725 | * Send a packet to media from the upper layer. | |
726 | */ | |
727 | static int | |
728 | dm9000_start_xmit(struct sk_buff *skb, struct net_device *dev) | |
729 | { | |
c46ac946 | 730 | unsigned long flags; |
59eae1fa | 731 | board_info_t *db = dev->priv; |
a1365275 | 732 | |
5b2b4ff0 | 733 | dm9000_dbg(db, 3, "%s:\n", __func__); |
a1365275 SH |
734 | |
735 | if (db->tx_pkt_cnt > 1) | |
736 | return 1; | |
737 | ||
c46ac946 | 738 | spin_lock_irqsave(&db->lock, flags); |
a1365275 SH |
739 | |
740 | /* Move data to DM9000 TX RAM */ | |
741 | writeb(DM9000_MWCMD, db->io_addr); | |
742 | ||
743 | (db->outblk)(db->io_data, skb->data, skb->len); | |
09f75cd7 | 744 | dev->stats.tx_bytes += skb->len; |
a1365275 | 745 | |
c46ac946 | 746 | db->tx_pkt_cnt++; |
a1365275 | 747 | /* TX control: First packet immediately send, second packet queue */ |
c46ac946 | 748 | if (db->tx_pkt_cnt == 1) { |
a1365275 | 749 | /* Set TX length to DM9000 */ |
073d3f46 BD |
750 | iow(db, DM9000_TXPLL, skb->len); |
751 | iow(db, DM9000_TXPLH, skb->len >> 8); | |
a1365275 SH |
752 | |
753 | /* Issue TX polling command */ | |
754 | iow(db, DM9000_TCR, TCR_TXREQ); /* Cleared after TX complete */ | |
755 | ||
756 | dev->trans_start = jiffies; /* save the time stamp */ | |
a1365275 SH |
757 | } else { |
758 | /* Second packet */ | |
a1365275 | 759 | db->queue_pkt_len = skb->len; |
c46ac946 | 760 | netif_stop_queue(dev); |
a1365275 SH |
761 | } |
762 | ||
c46ac946 FW |
763 | spin_unlock_irqrestore(&db->lock, flags); |
764 | ||
a1365275 SH |
765 | /* free this SKB */ |
766 | dev_kfree_skb(skb); | |
767 | ||
a1365275 SH |
768 | return 0; |
769 | } | |
770 | ||
a1365275 | 771 | /* |
f8d79e79 BD |
772 | * DM9000 interrupt handler |
773 | * receive the packet to upper layer, free the transmitted packet | |
a1365275 | 774 | */ |
f8d79e79 BD |
775 | |
776 | static void dm9000_tx_done(struct net_device *dev, board_info_t *db) | |
a1365275 | 777 | { |
f8d79e79 | 778 | int tx_status = ior(db, DM9000_NSR); /* Got TX status */ |
a1365275 | 779 | |
f8d79e79 BD |
780 | if (tx_status & (NSR_TX2END | NSR_TX1END)) { |
781 | /* One packet sent complete */ | |
782 | db->tx_pkt_cnt--; | |
783 | dev->stats.tx_packets++; | |
a1365275 | 784 | |
f8d79e79 BD |
785 | if (netif_msg_tx_done(db)) |
786 | dev_dbg(db->dev, "tx done, NSR %02x\n", tx_status); | |
c991d168 | 787 | |
a1365275 SH |
788 | /* Queue packet check & send */ |
789 | if (db->tx_pkt_cnt > 0) { | |
073d3f46 BD |
790 | iow(db, DM9000_TXPLL, db->queue_pkt_len); |
791 | iow(db, DM9000_TXPLH, db->queue_pkt_len >> 8); | |
a1365275 SH |
792 | iow(db, DM9000_TCR, TCR_TXREQ); |
793 | dev->trans_start = jiffies; | |
794 | } | |
795 | netif_wake_queue(dev); | |
796 | } | |
797 | } | |
798 | ||
a1365275 | 799 | struct dm9000_rxhdr { |
93116573 BD |
800 | u8 RxPktReady; |
801 | u8 RxStatus; | |
8b9fc8ae | 802 | __le16 RxLen; |
a1365275 SH |
803 | } __attribute__((__packed__)); |
804 | ||
805 | /* | |
806 | * Received a packet and pass to upper layer | |
807 | */ | |
808 | static void | |
809 | dm9000_rx(struct net_device *dev) | |
810 | { | |
811 | board_info_t *db = (board_info_t *) dev->priv; | |
812 | struct dm9000_rxhdr rxhdr; | |
813 | struct sk_buff *skb; | |
814 | u8 rxbyte, *rdptr; | |
6478fac6 | 815 | bool GoodPacket; |
a1365275 SH |
816 | int RxLen; |
817 | ||
818 | /* Check packet ready or not */ | |
819 | do { | |
820 | ior(db, DM9000_MRCMDX); /* Dummy read */ | |
821 | ||
822 | /* Get most updated data */ | |
823 | rxbyte = readb(db->io_data); | |
824 | ||
825 | /* Status check: this byte must be 0 or 1 */ | |
826 | if (rxbyte > DM9000_PKT_RDY) { | |
a76836f9 | 827 | dev_warn(db->dev, "status check fail: %d\n", rxbyte); |
a1365275 SH |
828 | iow(db, DM9000_RCR, 0x00); /* Stop Device */ |
829 | iow(db, DM9000_ISR, IMR_PAR); /* Stop INT request */ | |
830 | return; | |
831 | } | |
832 | ||
833 | if (rxbyte != DM9000_PKT_RDY) | |
834 | return; | |
835 | ||
836 | /* A packet ready now & Get status/length */ | |
6478fac6 | 837 | GoodPacket = true; |
a1365275 SH |
838 | writeb(DM9000_MRCMD, db->io_addr); |
839 | ||
840 | (db->inblk)(db->io_data, &rxhdr, sizeof(rxhdr)); | |
841 | ||
93116573 | 842 | RxLen = le16_to_cpu(rxhdr.RxLen); |
a1365275 | 843 | |
c991d168 BD |
844 | if (netif_msg_rx_status(db)) |
845 | dev_dbg(db->dev, "RX: status %02x, length %04x\n", | |
846 | rxhdr.RxStatus, RxLen); | |
847 | ||
a1365275 SH |
848 | /* Packet Status check */ |
849 | if (RxLen < 0x40) { | |
6478fac6 | 850 | GoodPacket = false; |
c991d168 BD |
851 | if (netif_msg_rx_err(db)) |
852 | dev_dbg(db->dev, "RX: Bad Packet (runt)\n"); | |
a1365275 SH |
853 | } |
854 | ||
855 | if (RxLen > DM9000_PKT_MAX) { | |
a76836f9 | 856 | dev_dbg(db->dev, "RST: RX Len:%x\n", RxLen); |
a1365275 SH |
857 | } |
858 | ||
93116573 | 859 | if (rxhdr.RxStatus & 0xbf) { |
6478fac6 | 860 | GoodPacket = false; |
93116573 | 861 | if (rxhdr.RxStatus & 0x01) { |
c991d168 BD |
862 | if (netif_msg_rx_err(db)) |
863 | dev_dbg(db->dev, "fifo error\n"); | |
09f75cd7 | 864 | dev->stats.rx_fifo_errors++; |
a1365275 | 865 | } |
93116573 | 866 | if (rxhdr.RxStatus & 0x02) { |
c991d168 BD |
867 | if (netif_msg_rx_err(db)) |
868 | dev_dbg(db->dev, "crc error\n"); | |
09f75cd7 | 869 | dev->stats.rx_crc_errors++; |
a1365275 | 870 | } |
93116573 | 871 | if (rxhdr.RxStatus & 0x80) { |
c991d168 BD |
872 | if (netif_msg_rx_err(db)) |
873 | dev_dbg(db->dev, "length error\n"); | |
09f75cd7 | 874 | dev->stats.rx_length_errors++; |
a1365275 SH |
875 | } |
876 | } | |
877 | ||
878 | /* Move data from DM9000 */ | |
879 | if (GoodPacket | |
880 | && ((skb = dev_alloc_skb(RxLen + 4)) != NULL)) { | |
a1365275 SH |
881 | skb_reserve(skb, 2); |
882 | rdptr = (u8 *) skb_put(skb, RxLen - 4); | |
883 | ||
884 | /* Read received packet from RX SRAM */ | |
885 | ||
886 | (db->inblk)(db->io_data, rdptr, RxLen); | |
09f75cd7 | 887 | dev->stats.rx_bytes += RxLen; |
a1365275 SH |
888 | |
889 | /* Pass to upper layer */ | |
890 | skb->protocol = eth_type_trans(skb, dev); | |
891 | netif_rx(skb); | |
09f75cd7 | 892 | dev->stats.rx_packets++; |
a1365275 SH |
893 | |
894 | } else { | |
895 | /* need to dump the packet's data */ | |
896 | ||
897 | (db->dumpblk)(db->io_data, RxLen); | |
898 | } | |
899 | } while (rxbyte == DM9000_PKT_RDY); | |
900 | } | |
901 | ||
f8d79e79 | 902 | static irqreturn_t dm9000_interrupt(int irq, void *dev_id) |
39c341a8 | 903 | { |
f8d79e79 BD |
904 | struct net_device *dev = dev_id; |
905 | board_info_t *db = dev->priv; | |
906 | int int_status; | |
907 | u8 reg_save; | |
39c341a8 | 908 | |
f8d79e79 | 909 | dm9000_dbg(db, 3, "entering %s\n", __func__); |
39c341a8 | 910 | |
f8d79e79 | 911 | /* A real interrupt coming */ |
39c341a8 | 912 | |
f8d79e79 | 913 | spin_lock(&db->lock); |
39c341a8 | 914 | |
f8d79e79 BD |
915 | /* Save previous register address */ |
916 | reg_save = readb(db->io_addr); | |
39c341a8 | 917 | |
f8d79e79 BD |
918 | /* Disable all interrupts */ |
919 | iow(db, DM9000_IMR, IMR_PAR); | |
39c341a8 | 920 | |
f8d79e79 BD |
921 | /* Got DM9000 interrupt status */ |
922 | int_status = ior(db, DM9000_ISR); /* Got ISR */ | |
923 | iow(db, DM9000_ISR, int_status); /* Clear ISR status */ | |
39c341a8 | 924 | |
f8d79e79 BD |
925 | if (netif_msg_intr(db)) |
926 | dev_dbg(db->dev, "interrupt status %02x\n", int_status); | |
927 | ||
928 | /* Received the coming packet */ | |
929 | if (int_status & ISR_PRS) | |
930 | dm9000_rx(dev); | |
931 | ||
932 | /* Trnasmit Interrupt check */ | |
933 | if (int_status & ISR_PTS) | |
934 | dm9000_tx_done(dev, db); | |
935 | ||
936 | if (db->type != TYPE_DM9000E) { | |
937 | if (int_status & ISR_LNKCHNG) { | |
938 | /* fire a link-change request */ | |
939 | schedule_delayed_work(&db->phy_poll, 1); | |
39c341a8 BD |
940 | } |
941 | } | |
942 | ||
f8d79e79 BD |
943 | /* Re-enable interrupt mask */ |
944 | iow(db, DM9000_IMR, db->imr_all); | |
945 | ||
946 | /* Restore previous register address */ | |
947 | writeb(reg_save, db->io_addr); | |
948 | ||
949 | spin_unlock(&db->lock); | |
950 | ||
951 | return IRQ_HANDLED; | |
39c341a8 BD |
952 | } |
953 | ||
f8d79e79 | 954 | #ifdef CONFIG_NET_POLL_CONTROLLER |
a1365275 | 955 | /* |
f8d79e79 | 956 | *Used by netconsole |
a1365275 | 957 | */ |
f8d79e79 | 958 | static void dm9000_poll_controller(struct net_device *dev) |
a1365275 | 959 | { |
f8d79e79 BD |
960 | disable_irq(dev->irq); |
961 | dm9000_interrupt(dev->irq, dev); | |
962 | enable_irq(dev->irq); | |
963 | } | |
964 | #endif | |
9a2f037c | 965 | |
f8d79e79 BD |
966 | /* |
967 | * Open the interface. | |
968 | * The interface is opened whenever "ifconfig" actives it. | |
969 | */ | |
970 | static int | |
971 | dm9000_open(struct net_device *dev) | |
972 | { | |
973 | board_info_t *db = dev->priv; | |
974 | unsigned long irqflags = db->irq_res->flags & IRQF_TRIGGER_MASK; | |
621ddcb0 | 975 | |
f8d79e79 BD |
976 | if (netif_msg_ifup(db)) |
977 | dev_dbg(db->dev, "enabling %s\n", dev->name); | |
621ddcb0 | 978 | |
f8d79e79 BD |
979 | /* If there is no IRQ type specified, default to something that |
980 | * may work, and tell the user that this is a problem */ | |
621ddcb0 | 981 | |
f8d79e79 BD |
982 | if (irqflags == IRQF_TRIGGER_NONE) { |
983 | dev_warn(db->dev, "WARNING: no IRQ resource flags set.\n"); | |
984 | irqflags = DEFAULT_TRIGGER; | |
985 | } | |
986 | ||
987 | irqflags |= IRQF_SHARED; | |
39c341a8 | 988 | |
f8d79e79 BD |
989 | if (request_irq(dev->irq, &dm9000_interrupt, irqflags, dev->name, dev)) |
990 | return -EAGAIN; | |
621ddcb0 | 991 | |
f8d79e79 BD |
992 | /* Initialize DM9000 board */ |
993 | dm9000_reset(db); | |
994 | dm9000_init_dm9000(dev); | |
621ddcb0 | 995 | |
f8d79e79 BD |
996 | /* Init driver variable */ |
997 | db->dbug_cnt = 0; | |
86c62fab | 998 | |
f8d79e79 BD |
999 | mii_check_media(&db->mii, netif_msg_link(db), 1); |
1000 | netif_start_queue(dev); | |
1001 | ||
1002 | dm9000_schedule_poll(db); | |
9a2f037c | 1003 | |
f8d79e79 BD |
1004 | return 0; |
1005 | } | |
621ddcb0 | 1006 | |
f8d79e79 BD |
1007 | /* |
1008 | * Sleep, either by using msleep() or if we are suspending, then | |
1009 | * use mdelay() to sleep. | |
1010 | */ | |
1011 | static void dm9000_msleep(board_info_t *db, unsigned int ms) | |
1012 | { | |
1013 | if (db->in_suspend) | |
1014 | mdelay(ms); | |
1015 | else | |
1016 | msleep(ms); | |
a1365275 SH |
1017 | } |
1018 | ||
a1365275 | 1019 | /* |
f8d79e79 | 1020 | * Read a word from phyxcer |
a1365275 | 1021 | */ |
f8d79e79 BD |
1022 | static int |
1023 | dm9000_phy_read(struct net_device *dev, int phy_reg_unused, int reg) | |
a1365275 | 1024 | { |
f8d79e79 | 1025 | board_info_t *db = (board_info_t *) dev->priv; |
621ddcb0 | 1026 | unsigned long flags; |
f8d79e79 BD |
1027 | unsigned int reg_save; |
1028 | int ret; | |
bb44fb70 | 1029 | |
9a2f037c BD |
1030 | mutex_lock(&db->addr_lock); |
1031 | ||
f8d79e79 | 1032 | spin_lock_irqsave(&db->lock,flags); |
621ddcb0 | 1033 | |
f8d79e79 BD |
1034 | /* Save previous register address */ |
1035 | reg_save = readb(db->io_addr); | |
39c341a8 | 1036 | |
f8d79e79 BD |
1037 | /* Fill the phyxcer register into REG_0C */ |
1038 | iow(db, DM9000_EPAR, DM9000_PHY | reg); | |
621ddcb0 | 1039 | |
f8d79e79 | 1040 | iow(db, DM9000_EPCR, 0xc); /* Issue phyxcer read command */ |
9a2f037c | 1041 | |
f8d79e79 BD |
1042 | writeb(reg_save, db->io_addr); |
1043 | spin_unlock_irqrestore(&db->lock,flags); | |
89c8b0e6 | 1044 | |
321f69a4 | 1045 | dm9000_msleep(db, 1); /* Wait read complete */ |
89c8b0e6 BD |
1046 | |
1047 | spin_lock_irqsave(&db->lock,flags); | |
1048 | reg_save = readb(db->io_addr); | |
1049 | ||
a1365275 SH |
1050 | iow(db, DM9000_EPCR, 0x0); /* Clear phyxcer read command */ |
1051 | ||
1052 | /* The read data keeps on REG_0D & REG_0E */ | |
1053 | ret = (ior(db, DM9000_EPDRH) << 8) | ior(db, DM9000_EPDRL); | |
1054 | ||
9ef9ac51 BD |
1055 | /* restore the previous address */ |
1056 | writeb(reg_save, db->io_addr); | |
a1365275 SH |
1057 | spin_unlock_irqrestore(&db->lock,flags); |
1058 | ||
9a2f037c | 1059 | mutex_unlock(&db->addr_lock); |
37d5dca6 ES |
1060 | |
1061 | dm9000_dbg(db, 5, "phy_read[%02x] -> %04x\n", reg, ret); | |
a1365275 SH |
1062 | return ret; |
1063 | } | |
1064 | ||
1065 | /* | |
1066 | * Write a word to phyxcer | |
1067 | */ | |
1068 | static void | |
59eae1fa BD |
1069 | dm9000_phy_write(struct net_device *dev, |
1070 | int phyaddr_unused, int reg, int value) | |
a1365275 SH |
1071 | { |
1072 | board_info_t *db = (board_info_t *) dev->priv; | |
1073 | unsigned long flags; | |
9ef9ac51 | 1074 | unsigned long reg_save; |
a1365275 | 1075 | |
37d5dca6 | 1076 | dm9000_dbg(db, 5, "phy_write[%02x] = %04x\n", reg, value); |
9a2f037c BD |
1077 | mutex_lock(&db->addr_lock); |
1078 | ||
a1365275 SH |
1079 | spin_lock_irqsave(&db->lock,flags); |
1080 | ||
9ef9ac51 BD |
1081 | /* Save previous register address */ |
1082 | reg_save = readb(db->io_addr); | |
1083 | ||
a1365275 SH |
1084 | /* Fill the phyxcer register into REG_0C */ |
1085 | iow(db, DM9000_EPAR, DM9000_PHY | reg); | |
1086 | ||
1087 | /* Fill the written data into REG_0D & REG_0E */ | |
073d3f46 BD |
1088 | iow(db, DM9000_EPDRL, value); |
1089 | iow(db, DM9000_EPDRH, value >> 8); | |
a1365275 SH |
1090 | |
1091 | iow(db, DM9000_EPCR, 0xa); /* Issue phyxcer write command */ | |
89c8b0e6 BD |
1092 | |
1093 | writeb(reg_save, db->io_addr); | |
9a2f037c | 1094 | spin_unlock_irqrestore(&db->lock, flags); |
89c8b0e6 | 1095 | |
321f69a4 | 1096 | dm9000_msleep(db, 1); /* Wait write complete */ |
89c8b0e6 BD |
1097 | |
1098 | spin_lock_irqsave(&db->lock,flags); | |
1099 | reg_save = readb(db->io_addr); | |
1100 | ||
a1365275 SH |
1101 | iow(db, DM9000_EPCR, 0x0); /* Clear phyxcer write command */ |
1102 | ||
9ef9ac51 BD |
1103 | /* restore the previous address */ |
1104 | writeb(reg_save, db->io_addr); | |
1105 | ||
9a2f037c BD |
1106 | spin_unlock_irqrestore(&db->lock, flags); |
1107 | mutex_unlock(&db->addr_lock); | |
a1365275 SH |
1108 | } |
1109 | ||
f8d79e79 BD |
1110 | static void |
1111 | dm9000_shutdown(struct net_device *dev) | |
1112 | { | |
1113 | board_info_t *db = dev->priv; | |
1114 | ||
1115 | /* RESET device */ | |
1116 | dm9000_phy_write(dev, 0, MII_BMCR, BMCR_RESET); /* PHY RESET */ | |
1117 | iow(db, DM9000_GPR, 0x01); /* Power-Down PHY */ | |
1118 | iow(db, DM9000_IMR, IMR_PAR); /* Disable all interrupt */ | |
1119 | iow(db, DM9000_RCR, 0x00); /* Disable RX */ | |
1120 | } | |
1121 | ||
1122 | /* | |
1123 | * Stop the interface. | |
1124 | * The interface is stopped when it is brought. | |
1125 | */ | |
1126 | static int | |
1127 | dm9000_stop(struct net_device *ndev) | |
1128 | { | |
1129 | board_info_t *db = ndev->priv; | |
1130 | ||
1131 | if (netif_msg_ifdown(db)) | |
1132 | dev_dbg(db->dev, "shutting down %s\n", ndev->name); | |
1133 | ||
1134 | cancel_delayed_work_sync(&db->phy_poll); | |
1135 | ||
1136 | netif_stop_queue(ndev); | |
1137 | netif_carrier_off(ndev); | |
1138 | ||
1139 | /* free interrupt */ | |
1140 | free_irq(ndev->irq, ndev); | |
1141 | ||
1142 | dm9000_shutdown(ndev); | |
1143 | ||
1144 | return 0; | |
1145 | } | |
1146 | ||
1147 | #define res_size(_r) (((_r)->end - (_r)->start) + 1) | |
1148 | ||
1149 | /* | |
1150 | * Search DM9000 board, allocate space and register it | |
1151 | */ | |
1152 | static int __devinit | |
1153 | dm9000_probe(struct platform_device *pdev) | |
1154 | { | |
1155 | struct dm9000_plat_data *pdata = pdev->dev.platform_data; | |
1156 | struct board_info *db; /* Point a board information structure */ | |
1157 | struct net_device *ndev; | |
1158 | const unsigned char *mac_src; | |
1159 | int ret = 0; | |
1160 | int iosize; | |
1161 | int i; | |
1162 | u32 id_val; | |
1163 | ||
1164 | /* Init network device */ | |
1165 | ndev = alloc_etherdev(sizeof(struct board_info)); | |
1166 | if (!ndev) { | |
1167 | dev_err(&pdev->dev, "could not allocate device.\n"); | |
1168 | return -ENOMEM; | |
1169 | } | |
1170 | ||
1171 | SET_NETDEV_DEV(ndev, &pdev->dev); | |
1172 | ||
1173 | dev_dbg(&pdev->dev, "dm9000_probe()\n"); | |
1174 | ||
1175 | /* setup board info structure */ | |
1176 | db = ndev->priv; | |
1177 | memset(db, 0, sizeof(*db)); | |
1178 | ||
1179 | db->dev = &pdev->dev; | |
1180 | db->ndev = ndev; | |
1181 | ||
1182 | spin_lock_init(&db->lock); | |
1183 | mutex_init(&db->addr_lock); | |
1184 | ||
1185 | INIT_DELAYED_WORK(&db->phy_poll, dm9000_poll_work); | |
1186 | ||
1187 | db->addr_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1188 | db->data_res = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
1189 | db->irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | |
1190 | ||
1191 | if (db->addr_res == NULL || db->data_res == NULL || | |
1192 | db->irq_res == NULL) { | |
1193 | dev_err(db->dev, "insufficient resources\n"); | |
1194 | ret = -ENOENT; | |
1195 | goto out; | |
1196 | } | |
1197 | ||
1198 | iosize = res_size(db->addr_res); | |
1199 | db->addr_req = request_mem_region(db->addr_res->start, iosize, | |
1200 | pdev->name); | |
1201 | ||
1202 | if (db->addr_req == NULL) { | |
1203 | dev_err(db->dev, "cannot claim address reg area\n"); | |
1204 | ret = -EIO; | |
1205 | goto out; | |
1206 | } | |
1207 | ||
1208 | db->io_addr = ioremap(db->addr_res->start, iosize); | |
1209 | ||
1210 | if (db->io_addr == NULL) { | |
1211 | dev_err(db->dev, "failed to ioremap address reg\n"); | |
1212 | ret = -EINVAL; | |
1213 | goto out; | |
1214 | } | |
1215 | ||
1216 | iosize = res_size(db->data_res); | |
1217 | db->data_req = request_mem_region(db->data_res->start, iosize, | |
1218 | pdev->name); | |
1219 | ||
1220 | if (db->data_req == NULL) { | |
1221 | dev_err(db->dev, "cannot claim data reg area\n"); | |
1222 | ret = -EIO; | |
1223 | goto out; | |
1224 | } | |
1225 | ||
1226 | db->io_data = ioremap(db->data_res->start, iosize); | |
1227 | ||
1228 | if (db->io_data == NULL) { | |
1229 | dev_err(db->dev, "failed to ioremap data reg\n"); | |
1230 | ret = -EINVAL; | |
1231 | goto out; | |
1232 | } | |
1233 | ||
1234 | /* fill in parameters for net-dev structure */ | |
1235 | ndev->base_addr = (unsigned long)db->io_addr; | |
1236 | ndev->irq = db->irq_res->start; | |
1237 | ||
1238 | /* ensure at least we have a default set of IO routines */ | |
1239 | dm9000_set_io(db, iosize); | |
1240 | ||
1241 | /* check to see if anything is being over-ridden */ | |
1242 | if (pdata != NULL) { | |
1243 | /* check to see if the driver wants to over-ride the | |
1244 | * default IO width */ | |
1245 | ||
1246 | if (pdata->flags & DM9000_PLATF_8BITONLY) | |
1247 | dm9000_set_io(db, 1); | |
1248 | ||
1249 | if (pdata->flags & DM9000_PLATF_16BITONLY) | |
1250 | dm9000_set_io(db, 2); | |
1251 | ||
1252 | if (pdata->flags & DM9000_PLATF_32BITONLY) | |
1253 | dm9000_set_io(db, 4); | |
1254 | ||
1255 | /* check to see if there are any IO routine | |
1256 | * over-rides */ | |
1257 | ||
1258 | if (pdata->inblk != NULL) | |
1259 | db->inblk = pdata->inblk; | |
1260 | ||
1261 | if (pdata->outblk != NULL) | |
1262 | db->outblk = pdata->outblk; | |
1263 | ||
1264 | if (pdata->dumpblk != NULL) | |
1265 | db->dumpblk = pdata->dumpblk; | |
1266 | ||
1267 | db->flags = pdata->flags; | |
1268 | } | |
1269 | ||
1270 | dm9000_reset(db); | |
1271 | ||
1272 | /* try multiple times, DM9000 sometimes gets the read wrong */ | |
1273 | for (i = 0; i < 8; i++) { | |
1274 | id_val = ior(db, DM9000_VIDL); | |
1275 | id_val |= (u32)ior(db, DM9000_VIDH) << 8; | |
1276 | id_val |= (u32)ior(db, DM9000_PIDL) << 16; | |
1277 | id_val |= (u32)ior(db, DM9000_PIDH) << 24; | |
1278 | ||
1279 | if (id_val == DM9000_ID) | |
1280 | break; | |
1281 | dev_err(db->dev, "read wrong id 0x%08x\n", id_val); | |
1282 | } | |
1283 | ||
1284 | if (id_val != DM9000_ID) { | |
1285 | dev_err(db->dev, "wrong id: 0x%08x\n", id_val); | |
1286 | ret = -ENODEV; | |
1287 | goto out; | |
1288 | } | |
1289 | ||
1290 | /* Identify what type of DM9000 we are working on */ | |
1291 | ||
1292 | id_val = ior(db, DM9000_CHIPR); | |
1293 | dev_dbg(db->dev, "dm9000 revision 0x%02x\n", id_val); | |
1294 | ||
1295 | switch (id_val) { | |
1296 | case CHIPR_DM9000A: | |
1297 | db->type = TYPE_DM9000A; | |
1298 | break; | |
1299 | case CHIPR_DM9000B: | |
1300 | db->type = TYPE_DM9000B; | |
1301 | break; | |
1302 | default: | |
1303 | dev_dbg(db->dev, "ID %02x => defaulting to DM9000E\n", id_val); | |
1304 | db->type = TYPE_DM9000E; | |
1305 | } | |
1306 | ||
1307 | /* from this point we assume that we have found a DM9000 */ | |
1308 | ||
1309 | /* driver system function */ | |
1310 | ether_setup(ndev); | |
1311 | ||
1312 | ndev->open = &dm9000_open; | |
1313 | ndev->hard_start_xmit = &dm9000_start_xmit; | |
1314 | ndev->tx_timeout = &dm9000_timeout; | |
1315 | ndev->watchdog_timeo = msecs_to_jiffies(watchdog); | |
1316 | ndev->stop = &dm9000_stop; | |
1317 | ndev->set_multicast_list = &dm9000_hash_table; | |
1318 | ndev->ethtool_ops = &dm9000_ethtool_ops; | |
1319 | ndev->do_ioctl = &dm9000_ioctl; | |
1320 | ||
1321 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1322 | ndev->poll_controller = &dm9000_poll_controller; | |
1323 | #endif | |
1324 | ||
1325 | db->msg_enable = NETIF_MSG_LINK; | |
1326 | db->mii.phy_id_mask = 0x1f; | |
1327 | db->mii.reg_num_mask = 0x1f; | |
1328 | db->mii.force_media = 0; | |
1329 | db->mii.full_duplex = 0; | |
1330 | db->mii.dev = ndev; | |
1331 | db->mii.mdio_read = dm9000_phy_read; | |
1332 | db->mii.mdio_write = dm9000_phy_write; | |
1333 | ||
1334 | mac_src = "eeprom"; | |
1335 | ||
1336 | /* try reading the node address from the attached EEPROM */ | |
1337 | for (i = 0; i < 6; i += 2) | |
1338 | dm9000_read_eeprom(db, i / 2, ndev->dev_addr+i); | |
1339 | ||
1340 | if (!is_valid_ether_addr(ndev->dev_addr)) { | |
1341 | /* try reading from mac */ | |
1342 | ||
1343 | mac_src = "chip"; | |
1344 | for (i = 0; i < 6; i++) | |
1345 | ndev->dev_addr[i] = ior(db, i+DM9000_PAR); | |
1346 | } | |
1347 | ||
1348 | if (!is_valid_ether_addr(ndev->dev_addr)) | |
1349 | dev_warn(db->dev, "%s: Invalid ethernet MAC address. Please " | |
1350 | "set using ifconfig\n", ndev->name); | |
1351 | ||
1352 | platform_set_drvdata(pdev, ndev); | |
1353 | ret = register_netdev(ndev); | |
1354 | ||
1355 | if (ret == 0) { | |
1356 | DECLARE_MAC_BUF(mac); | |
1357 | printk(KERN_INFO "%s: dm9000%c at %p,%p IRQ %d MAC: %s (%s)\n", | |
1358 | ndev->name, dm9000_type_to_char(db->type), | |
1359 | db->io_addr, db->io_data, ndev->irq, | |
1360 | print_mac(mac, ndev->dev_addr), mac_src); | |
1361 | } | |
1362 | return 0; | |
1363 | ||
1364 | out: | |
1365 | dev_err(db->dev, "not found (%d).\n", ret); | |
1366 | ||
1367 | dm9000_release_board(pdev, db); | |
1368 | free_netdev(ndev); | |
1369 | ||
1370 | return ret; | |
1371 | } | |
1372 | ||
a1365275 | 1373 | static int |
3ae5eaec | 1374 | dm9000_drv_suspend(struct platform_device *dev, pm_message_t state) |
a1365275 | 1375 | { |
3ae5eaec | 1376 | struct net_device *ndev = platform_get_drvdata(dev); |
321f69a4 | 1377 | board_info_t *db; |
a1365275 | 1378 | |
9480e307 | 1379 | if (ndev) { |
321f69a4 BD |
1380 | db = (board_info_t *) ndev->priv; |
1381 | db->in_suspend = 1; | |
1382 | ||
a1365275 SH |
1383 | if (netif_running(ndev)) { |
1384 | netif_device_detach(ndev); | |
1385 | dm9000_shutdown(ndev); | |
1386 | } | |
1387 | } | |
1388 | return 0; | |
1389 | } | |
1390 | ||
1391 | static int | |
3ae5eaec | 1392 | dm9000_drv_resume(struct platform_device *dev) |
a1365275 | 1393 | { |
3ae5eaec | 1394 | struct net_device *ndev = platform_get_drvdata(dev); |
a1365275 SH |
1395 | board_info_t *db = (board_info_t *) ndev->priv; |
1396 | ||
9480e307 | 1397 | if (ndev) { |
a1365275 SH |
1398 | |
1399 | if (netif_running(ndev)) { | |
1400 | dm9000_reset(db); | |
1401 | dm9000_init_dm9000(ndev); | |
1402 | ||
1403 | netif_device_attach(ndev); | |
1404 | } | |
321f69a4 BD |
1405 | |
1406 | db->in_suspend = 0; | |
a1365275 SH |
1407 | } |
1408 | return 0; | |
1409 | } | |
1410 | ||
e21fd4f0 | 1411 | static int __devexit |
3ae5eaec | 1412 | dm9000_drv_remove(struct platform_device *pdev) |
a1365275 | 1413 | { |
3ae5eaec | 1414 | struct net_device *ndev = platform_get_drvdata(pdev); |
a1365275 | 1415 | |
3ae5eaec | 1416 | platform_set_drvdata(pdev, NULL); |
a1365275 SH |
1417 | |
1418 | unregister_netdev(ndev); | |
1419 | dm9000_release_board(pdev, (board_info_t *) ndev->priv); | |
9fd9f9b6 | 1420 | free_netdev(ndev); /* free device structure */ |
a1365275 | 1421 | |
a76836f9 | 1422 | dev_dbg(&pdev->dev, "released and freed device\n"); |
a1365275 SH |
1423 | return 0; |
1424 | } | |
1425 | ||
3ae5eaec | 1426 | static struct platform_driver dm9000_driver = { |
5d22a312 BD |
1427 | .driver = { |
1428 | .name = "dm9000", | |
1429 | .owner = THIS_MODULE, | |
1430 | }, | |
a1365275 | 1431 | .probe = dm9000_probe, |
e21fd4f0 | 1432 | .remove = __devexit_p(dm9000_drv_remove), |
a1365275 SH |
1433 | .suspend = dm9000_drv_suspend, |
1434 | .resume = dm9000_drv_resume, | |
1435 | }; | |
1436 | ||
1437 | static int __init | |
1438 | dm9000_init(void) | |
1439 | { | |
7da99859 | 1440 | printk(KERN_INFO "%s Ethernet Driver, V%s\n", CARDNAME, DRV_VERSION); |
2ae2d77c | 1441 | |
59eae1fa | 1442 | return platform_driver_register(&dm9000_driver); |
a1365275 SH |
1443 | } |
1444 | ||
1445 | static void __exit | |
1446 | dm9000_cleanup(void) | |
1447 | { | |
3ae5eaec | 1448 | platform_driver_unregister(&dm9000_driver); |
a1365275 SH |
1449 | } |
1450 | ||
1451 | module_init(dm9000_init); | |
1452 | module_exit(dm9000_cleanup); | |
1453 | ||
1454 | MODULE_AUTHOR("Sascha Hauer, Ben Dooks"); | |
1455 | MODULE_DESCRIPTION("Davicom DM9000 network driver"); | |
1456 | MODULE_LICENSE("GPL"); | |
72abb461 | 1457 | MODULE_ALIAS("platform:dm9000"); |