Commit | Line | Data |
---|---|---|
a1365275 | 1 | /* |
41c340f0 | 2 | * Davicom DM9000 Fast Ethernet driver for Linux. |
a1365275 SH |
3 | * Copyright (C) 1997 Sten Wang |
4 | * | |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License | |
7 | * as published by the Free Software Foundation; either version 2 | |
8 | * of the License, or (at your option) any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
41c340f0 | 15 | * (C) Copyright 1997-1998 DAVICOM Semiconductor,Inc. All Rights Reserved. |
9ef9ac51 | 16 | * |
41c340f0 BD |
17 | * Additional updates, Copyright: |
18 | * Ben Dooks <ben@simtec.co.uk> | |
19 | * Sascha Hauer <s.hauer@pengutronix.de> | |
a1365275 SH |
20 | */ |
21 | ||
22 | #include <linux/module.h> | |
23 | #include <linux/ioport.h> | |
24 | #include <linux/netdevice.h> | |
25 | #include <linux/etherdevice.h> | |
26 | #include <linux/init.h> | |
27 | #include <linux/skbuff.h> | |
a1365275 SH |
28 | #include <linux/spinlock.h> |
29 | #include <linux/crc32.h> | |
30 | #include <linux/mii.h> | |
7da99859 | 31 | #include <linux/ethtool.h> |
a1365275 SH |
32 | #include <linux/dm9000.h> |
33 | #include <linux/delay.h> | |
d052d1be | 34 | #include <linux/platform_device.h> |
4e4fc05a | 35 | #include <linux/irq.h> |
a1365275 SH |
36 | |
37 | #include <asm/delay.h> | |
38 | #include <asm/irq.h> | |
39 | #include <asm/io.h> | |
40 | ||
41 | #include "dm9000.h" | |
42 | ||
43 | /* Board/System/Debug information/definition ---------------- */ | |
44 | ||
45 | #define DM9000_PHY 0x40 /* PHY address 0x01 */ | |
46 | ||
a1365275 SH |
47 | #define CARDNAME "dm9000" |
48 | #define PFX CARDNAME ": " | |
7da99859 | 49 | #define DRV_VERSION "1.30" |
a1365275 | 50 | |
f40d24d9 AL |
51 | #ifdef CONFIG_BLACKFIN |
52 | #define readsb insb | |
53 | #define readsw insw | |
54 | #define readsl insl | |
55 | #define writesb outsb | |
56 | #define writesw outsw | |
57 | #define writesl outsl | |
1a5f1c4f | 58 | #define DEFAULT_TRIGGER IRQF_TRIGGER_HIGH |
f40d24d9 | 59 | #else |
1a5f1c4f | 60 | #define DEFAULT_TRIGGER (0) |
f40d24d9 AL |
61 | #endif |
62 | ||
a1365275 SH |
63 | /* |
64 | * Transmit timeout, default 5 seconds. | |
65 | */ | |
66 | static int watchdog = 5000; | |
67 | module_param(watchdog, int, 0400); | |
68 | MODULE_PARM_DESC(watchdog, "transmit timeout in milliseconds"); | |
69 | ||
9a2f037c BD |
70 | /* DM9000 register address locking. |
71 | * | |
72 | * The DM9000 uses an address register to control where data written | |
73 | * to the data register goes. This means that the address register | |
74 | * must be preserved over interrupts or similar calls. | |
75 | * | |
76 | * During interrupt and other critical calls, a spinlock is used to | |
77 | * protect the system, but the calls themselves save the address | |
78 | * in the address register in case they are interrupting another | |
79 | * access to the device. | |
80 | * | |
81 | * For general accesses a lock is provided so that calls which are | |
82 | * allowed to sleep are serialised so that the address register does | |
83 | * not need to be saved. This lock also serves to serialise access | |
84 | * to the EEPROM and PHY access registers which are shared between | |
85 | * these two devices. | |
86 | */ | |
87 | ||
a1365275 SH |
88 | /* Structure/enum declaration ------------------------------- */ |
89 | typedef struct board_info { | |
90 | ||
91 | void __iomem *io_addr; /* Register I/O base address */ | |
92 | void __iomem *io_data; /* Data I/O address */ | |
93 | u16 irq; /* IRQ */ | |
94 | ||
95 | u16 tx_pkt_cnt; | |
96 | u16 queue_pkt_len; | |
97 | u16 queue_start_addr; | |
98 | u16 dbug_cnt; | |
99 | u8 io_mode; /* 0:word, 2:byte */ | |
100 | u8 phy_addr; | |
33ba5091 | 101 | unsigned int flags; |
321f69a4 | 102 | unsigned int in_suspend :1; |
a1365275 | 103 | |
5b2b4ff0 BD |
104 | int debug_level; |
105 | ||
a1365275 SH |
106 | void (*inblk)(void __iomem *port, void *data, int length); |
107 | void (*outblk)(void __iomem *port, void *data, int length); | |
108 | void (*dumpblk)(void __iomem *port, int length); | |
109 | ||
a76836f9 BD |
110 | struct device *dev; /* parent device */ |
111 | ||
a1365275 SH |
112 | struct resource *addr_res; /* resources found */ |
113 | struct resource *data_res; | |
114 | struct resource *addr_req; /* resources requested */ | |
115 | struct resource *data_req; | |
116 | struct resource *irq_res; | |
117 | ||
9a2f037c BD |
118 | struct mutex addr_lock; /* phy and eeprom access lock */ |
119 | ||
8f5bf5f2 BD |
120 | struct delayed_work phy_poll; |
121 | struct net_device *ndev; | |
122 | ||
a1365275 SH |
123 | spinlock_t lock; |
124 | ||
125 | struct mii_if_info mii; | |
126 | u32 msg_enable; | |
127 | } board_info_t; | |
128 | ||
5b2b4ff0 BD |
129 | /* debug code */ |
130 | ||
131 | #define dm9000_dbg(db, lev, msg...) do { \ | |
132 | if ((lev) < CONFIG_DM9000_DEBUGLEVEL && \ | |
133 | (lev) < db->debug_level) { \ | |
134 | dev_dbg(db->dev, msg); \ | |
135 | } \ | |
136 | } while (0) | |
137 | ||
7da99859 BD |
138 | static inline board_info_t *to_dm9000_board(struct net_device *dev) |
139 | { | |
140 | return dev->priv; | |
141 | } | |
142 | ||
a1365275 | 143 | /* function declaration ------------------------------------- */ |
3ae5eaec | 144 | static int dm9000_probe(struct platform_device *); |
a1365275 SH |
145 | static int dm9000_open(struct net_device *); |
146 | static int dm9000_start_xmit(struct sk_buff *, struct net_device *); | |
147 | static int dm9000_stop(struct net_device *); | |
f42d8aea | 148 | static int dm9000_ioctl(struct net_device *dev, struct ifreq *req, int cmd); |
a1365275 | 149 | |
a1365275 SH |
150 | static void dm9000_init_dm9000(struct net_device *); |
151 | ||
7d12e780 | 152 | static irqreturn_t dm9000_interrupt(int, void *); |
a1365275 SH |
153 | |
154 | static int dm9000_phy_read(struct net_device *dev, int phyaddr_unsused, int reg); | |
155 | static void dm9000_phy_write(struct net_device *dev, int phyaddr_unused, int reg, | |
156 | int value); | |
86c62fab | 157 | |
29d52e54 BD |
158 | static void dm9000_read_eeprom(board_info_t *, int addr, u8 *to); |
159 | static void dm9000_write_eeprom(board_info_t *, int addr, u8 *dp); | |
a1365275 SH |
160 | static void dm9000_rx(struct net_device *); |
161 | static void dm9000_hash_table(struct net_device *); | |
162 | ||
a1365275 SH |
163 | /* DM9000 network board routine ---------------------------- */ |
164 | ||
165 | static void | |
166 | dm9000_reset(board_info_t * db) | |
167 | { | |
a76836f9 BD |
168 | dev_dbg(db->dev, "resetting device\n"); |
169 | ||
a1365275 SH |
170 | /* RESET device */ |
171 | writeb(DM9000_NCR, db->io_addr); | |
172 | udelay(200); | |
173 | writeb(NCR_RST, db->io_data); | |
174 | udelay(200); | |
175 | } | |
176 | ||
177 | /* | |
178 | * Read a byte from I/O port | |
179 | */ | |
180 | static u8 | |
181 | ior(board_info_t * db, int reg) | |
182 | { | |
183 | writeb(reg, db->io_addr); | |
184 | return readb(db->io_data); | |
185 | } | |
186 | ||
187 | /* | |
188 | * Write a byte to I/O port | |
189 | */ | |
190 | ||
191 | static void | |
192 | iow(board_info_t * db, int reg, int value) | |
193 | { | |
194 | writeb(reg, db->io_addr); | |
195 | writeb(value, db->io_data); | |
196 | } | |
197 | ||
198 | /* routines for sending block to chip */ | |
199 | ||
200 | static void dm9000_outblk_8bit(void __iomem *reg, void *data, int count) | |
201 | { | |
202 | writesb(reg, data, count); | |
203 | } | |
204 | ||
205 | static void dm9000_outblk_16bit(void __iomem *reg, void *data, int count) | |
206 | { | |
207 | writesw(reg, data, (count+1) >> 1); | |
208 | } | |
209 | ||
210 | static void dm9000_outblk_32bit(void __iomem *reg, void *data, int count) | |
211 | { | |
212 | writesl(reg, data, (count+3) >> 2); | |
213 | } | |
214 | ||
215 | /* input block from chip to memory */ | |
216 | ||
217 | static void dm9000_inblk_8bit(void __iomem *reg, void *data, int count) | |
218 | { | |
5f6b5517 | 219 | readsb(reg, data, count); |
a1365275 SH |
220 | } |
221 | ||
222 | ||
223 | static void dm9000_inblk_16bit(void __iomem *reg, void *data, int count) | |
224 | { | |
225 | readsw(reg, data, (count+1) >> 1); | |
226 | } | |
227 | ||
228 | static void dm9000_inblk_32bit(void __iomem *reg, void *data, int count) | |
229 | { | |
230 | readsl(reg, data, (count+3) >> 2); | |
231 | } | |
232 | ||
233 | /* dump block from chip to null */ | |
234 | ||
235 | static void dm9000_dumpblk_8bit(void __iomem *reg, int count) | |
236 | { | |
237 | int i; | |
238 | int tmp; | |
239 | ||
240 | for (i = 0; i < count; i++) | |
241 | tmp = readb(reg); | |
242 | } | |
243 | ||
244 | static void dm9000_dumpblk_16bit(void __iomem *reg, int count) | |
245 | { | |
246 | int i; | |
247 | int tmp; | |
248 | ||
249 | count = (count + 1) >> 1; | |
250 | ||
251 | for (i = 0; i < count; i++) | |
252 | tmp = readw(reg); | |
253 | } | |
254 | ||
255 | static void dm9000_dumpblk_32bit(void __iomem *reg, int count) | |
256 | { | |
257 | int i; | |
258 | int tmp; | |
259 | ||
260 | count = (count + 3) >> 2; | |
261 | ||
262 | for (i = 0; i < count; i++) | |
263 | tmp = readl(reg); | |
264 | } | |
265 | ||
266 | /* dm9000_set_io | |
267 | * | |
268 | * select the specified set of io routines to use with the | |
269 | * device | |
270 | */ | |
271 | ||
272 | static void dm9000_set_io(struct board_info *db, int byte_width) | |
273 | { | |
274 | /* use the size of the data resource to work out what IO | |
275 | * routines we want to use | |
276 | */ | |
277 | ||
278 | switch (byte_width) { | |
279 | case 1: | |
280 | db->dumpblk = dm9000_dumpblk_8bit; | |
281 | db->outblk = dm9000_outblk_8bit; | |
282 | db->inblk = dm9000_inblk_8bit; | |
283 | break; | |
284 | ||
a1365275 SH |
285 | |
286 | case 3: | |
a76836f9 BD |
287 | dev_dbg(db->dev, ": 3 byte IO, falling back to 16bit\n"); |
288 | case 2: | |
a1365275 SH |
289 | db->dumpblk = dm9000_dumpblk_16bit; |
290 | db->outblk = dm9000_outblk_16bit; | |
291 | db->inblk = dm9000_inblk_16bit; | |
292 | break; | |
293 | ||
294 | case 4: | |
295 | default: | |
296 | db->dumpblk = dm9000_dumpblk_32bit; | |
297 | db->outblk = dm9000_outblk_32bit; | |
298 | db->inblk = dm9000_inblk_32bit; | |
299 | break; | |
300 | } | |
301 | } | |
302 | ||
8f5bf5f2 BD |
303 | static void dm9000_schedule_poll(board_info_t *db) |
304 | { | |
305 | schedule_delayed_work(&db->phy_poll, HZ * 2); | |
306 | } | |
a1365275 SH |
307 | |
308 | /* Our watchdog timed out. Called by the networking layer */ | |
309 | static void dm9000_timeout(struct net_device *dev) | |
310 | { | |
311 | board_info_t *db = (board_info_t *) dev->priv; | |
312 | u8 reg_save; | |
313 | unsigned long flags; | |
314 | ||
315 | /* Save previous register address */ | |
316 | reg_save = readb(db->io_addr); | |
9ef9ac51 | 317 | spin_lock_irqsave(&db->lock,flags); |
a1365275 SH |
318 | |
319 | netif_stop_queue(dev); | |
320 | dm9000_reset(db); | |
321 | dm9000_init_dm9000(dev); | |
322 | /* We can accept TX packets again */ | |
323 | dev->trans_start = jiffies; | |
324 | netif_wake_queue(dev); | |
325 | ||
326 | /* Restore previous register address */ | |
327 | writeb(reg_save, db->io_addr); | |
9ef9ac51 | 328 | spin_unlock_irqrestore(&db->lock,flags); |
a1365275 SH |
329 | } |
330 | ||
2fd0e33f KH |
331 | #ifdef CONFIG_NET_POLL_CONTROLLER |
332 | /* | |
333 | *Used by netconsole | |
334 | */ | |
335 | static void dm9000_poll_controller(struct net_device *dev) | |
336 | { | |
337 | disable_irq(dev->irq); | |
28431146 | 338 | dm9000_interrupt(dev->irq,dev); |
2fd0e33f KH |
339 | enable_irq(dev->irq); |
340 | } | |
341 | #endif | |
a1365275 | 342 | |
f42d8aea BD |
343 | static int dm9000_ioctl(struct net_device *dev, struct ifreq *req, int cmd) |
344 | { | |
345 | board_info_t *dm = to_dm9000_board(dev); | |
346 | ||
347 | if (!netif_running(dev)) | |
348 | return -EINVAL; | |
349 | ||
350 | return generic_mii_ioctl(&dm->mii, if_mii(req), cmd, NULL); | |
351 | } | |
352 | ||
7da99859 BD |
353 | /* ethtool ops */ |
354 | ||
355 | static void dm9000_get_drvinfo(struct net_device *dev, | |
356 | struct ethtool_drvinfo *info) | |
357 | { | |
358 | board_info_t *dm = to_dm9000_board(dev); | |
359 | ||
360 | strcpy(info->driver, CARDNAME); | |
361 | strcpy(info->version, DRV_VERSION); | |
362 | strcpy(info->bus_info, to_platform_device(dm->dev)->name); | |
363 | } | |
364 | ||
e662ee02 BD |
365 | static u32 dm9000_get_msglevel(struct net_device *dev) |
366 | { | |
367 | board_info_t *dm = to_dm9000_board(dev); | |
368 | ||
369 | return dm->msg_enable; | |
370 | } | |
371 | ||
372 | static void dm9000_set_msglevel(struct net_device *dev, u32 value) | |
373 | { | |
374 | board_info_t *dm = to_dm9000_board(dev); | |
375 | ||
376 | dm->msg_enable = value; | |
377 | } | |
378 | ||
7da99859 BD |
379 | static int dm9000_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
380 | { | |
381 | board_info_t *dm = to_dm9000_board(dev); | |
7da99859 | 382 | |
7da99859 | 383 | mii_ethtool_gset(&dm->mii, cmd); |
7da99859 BD |
384 | return 0; |
385 | } | |
386 | ||
387 | static int dm9000_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
388 | { | |
389 | board_info_t *dm = to_dm9000_board(dev); | |
7da99859 | 390 | |
9a2f037c | 391 | return mii_ethtool_sset(&dm->mii, cmd); |
7da99859 BD |
392 | } |
393 | ||
394 | static int dm9000_nway_reset(struct net_device *dev) | |
395 | { | |
396 | board_info_t *dm = to_dm9000_board(dev); | |
397 | return mii_nway_restart(&dm->mii); | |
398 | } | |
399 | ||
400 | static u32 dm9000_get_link(struct net_device *dev) | |
401 | { | |
402 | board_info_t *dm = to_dm9000_board(dev); | |
403 | return mii_link_ok(&dm->mii); | |
404 | } | |
405 | ||
29d52e54 BD |
406 | #define DM_EEPROM_MAGIC (0x444D394B) |
407 | ||
408 | static int dm9000_get_eeprom_len(struct net_device *dev) | |
409 | { | |
410 | return 128; | |
411 | } | |
412 | ||
413 | static int dm9000_get_eeprom(struct net_device *dev, | |
414 | struct ethtool_eeprom *ee, u8 *data) | |
415 | { | |
416 | board_info_t *dm = to_dm9000_board(dev); | |
417 | int offset = ee->offset; | |
418 | int len = ee->len; | |
419 | int i; | |
420 | ||
421 | /* EEPROM access is aligned to two bytes */ | |
422 | ||
423 | if ((len & 1) != 0 || (offset & 1) != 0) | |
424 | return -EINVAL; | |
425 | ||
bb44fb70 BD |
426 | if (dm->flags & DM9000_PLATF_NO_EEPROM) |
427 | return -ENOENT; | |
428 | ||
29d52e54 BD |
429 | ee->magic = DM_EEPROM_MAGIC; |
430 | ||
431 | for (i = 0; i < len; i += 2) | |
432 | dm9000_read_eeprom(dm, (offset + i) / 2, data + i); | |
433 | ||
434 | return 0; | |
435 | } | |
436 | ||
437 | static int dm9000_set_eeprom(struct net_device *dev, | |
438 | struct ethtool_eeprom *ee, u8 *data) | |
439 | { | |
440 | board_info_t *dm = to_dm9000_board(dev); | |
441 | int offset = ee->offset; | |
442 | int len = ee->len; | |
443 | int i; | |
444 | ||
445 | /* EEPROM access is aligned to two bytes */ | |
446 | ||
447 | if ((len & 1) != 0 || (offset & 1) != 0) | |
448 | return -EINVAL; | |
449 | ||
bb44fb70 BD |
450 | if (dm->flags & DM9000_PLATF_NO_EEPROM) |
451 | return -ENOENT; | |
452 | ||
29d52e54 BD |
453 | if (ee->magic != DM_EEPROM_MAGIC) |
454 | return -EINVAL; | |
455 | ||
456 | for (i = 0; i < len; i += 2) | |
457 | dm9000_write_eeprom(dm, (offset + i) / 2, data + i); | |
458 | ||
459 | return 0; | |
460 | } | |
461 | ||
7da99859 BD |
462 | static const struct ethtool_ops dm9000_ethtool_ops = { |
463 | .get_drvinfo = dm9000_get_drvinfo, | |
464 | .get_settings = dm9000_get_settings, | |
465 | .set_settings = dm9000_set_settings, | |
e662ee02 BD |
466 | .get_msglevel = dm9000_get_msglevel, |
467 | .set_msglevel = dm9000_set_msglevel, | |
7da99859 BD |
468 | .nway_reset = dm9000_nway_reset, |
469 | .get_link = dm9000_get_link, | |
29d52e54 BD |
470 | .get_eeprom_len = dm9000_get_eeprom_len, |
471 | .get_eeprom = dm9000_get_eeprom, | |
472 | .set_eeprom = dm9000_set_eeprom, | |
7da99859 BD |
473 | }; |
474 | ||
8f5bf5f2 BD |
475 | static void |
476 | dm9000_poll_work(struct work_struct *w) | |
477 | { | |
478 | struct delayed_work *dw = container_of(w, struct delayed_work, work); | |
479 | board_info_t *db = container_of(dw, board_info_t, phy_poll); | |
480 | ||
481 | mii_check_media(&db->mii, netif_msg_link(db), 0); | |
482 | ||
483 | if (netif_running(db->ndev)) | |
484 | dm9000_schedule_poll(db); | |
485 | } | |
7da99859 | 486 | |
a1365275 SH |
487 | /* dm9000_release_board |
488 | * | |
489 | * release a board, and any mapped resources | |
490 | */ | |
491 | ||
492 | static void | |
493 | dm9000_release_board(struct platform_device *pdev, struct board_info *db) | |
494 | { | |
495 | if (db->data_res == NULL) { | |
496 | if (db->addr_res != NULL) | |
497 | release_mem_region((unsigned long)db->io_addr, 4); | |
498 | return; | |
499 | } | |
500 | ||
501 | /* unmap our resources */ | |
502 | ||
503 | iounmap(db->io_addr); | |
504 | iounmap(db->io_data); | |
505 | ||
506 | /* release the resources */ | |
507 | ||
508 | if (db->data_req != NULL) { | |
509 | release_resource(db->data_req); | |
510 | kfree(db->data_req); | |
511 | } | |
512 | ||
51985487 DO |
513 | if (db->addr_req != NULL) { |
514 | release_resource(db->addr_req); | |
a1365275 SH |
515 | kfree(db->addr_req); |
516 | } | |
517 | } | |
518 | ||
519 | #define res_size(_r) (((_r)->end - (_r)->start) + 1) | |
520 | ||
521 | /* | |
522 | * Search DM9000 board, allocate space and register it | |
523 | */ | |
e21fd4f0 | 524 | static int __devinit |
3ae5eaec | 525 | dm9000_probe(struct platform_device *pdev) |
a1365275 | 526 | { |
a1365275 SH |
527 | struct dm9000_plat_data *pdata = pdev->dev.platform_data; |
528 | struct board_info *db; /* Point a board information structure */ | |
529 | struct net_device *ndev; | |
179c743f | 530 | const unsigned char *mac_src; |
a1365275 SH |
531 | int ret = 0; |
532 | int iosize; | |
533 | int i; | |
534 | u32 id_val; | |
535 | ||
a1365275 SH |
536 | /* Init network device */ |
537 | ndev = alloc_etherdev(sizeof (struct board_info)); | |
538 | if (!ndev) { | |
a76836f9 | 539 | dev_err(&pdev->dev, "could not allocate device.\n"); |
a1365275 SH |
540 | return -ENOMEM; |
541 | } | |
542 | ||
3ae5eaec | 543 | SET_NETDEV_DEV(ndev, &pdev->dev); |
a1365275 | 544 | |
37d5dca6 | 545 | dev_dbg(&pdev->dev, "dm9000_probe()\n"); |
a1365275 SH |
546 | |
547 | /* setup board info structure */ | |
548 | db = (struct board_info *) ndev->priv; | |
549 | memset(db, 0, sizeof (*db)); | |
550 | ||
a76836f9 | 551 | db->dev = &pdev->dev; |
8f5bf5f2 | 552 | db->ndev = ndev; |
a76836f9 | 553 | |
9ef9ac51 | 554 | spin_lock_init(&db->lock); |
9a2f037c | 555 | mutex_init(&db->addr_lock); |
9ef9ac51 | 556 | |
8f5bf5f2 BD |
557 | INIT_DELAYED_WORK(&db->phy_poll, dm9000_poll_work); |
558 | ||
559 | ||
08c3f57c | 560 | if (pdev->num_resources < 3) { |
a1365275 SH |
561 | ret = -ENODEV; |
562 | goto out; | |
a1365275 SH |
563 | } |
564 | ||
08c3f57c LP |
565 | db->addr_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
566 | db->data_res = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
567 | db->irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | |
568 | ||
569 | if (db->addr_res == NULL || db->data_res == NULL || | |
570 | db->irq_res == NULL) { | |
571 | dev_err(db->dev, "insufficient resources\n"); | |
572 | ret = -ENOENT; | |
573 | goto out; | |
574 | } | |
575 | ||
576 | iosize = res_size(db->addr_res); | |
577 | db->addr_req = request_mem_region(db->addr_res->start, iosize, | |
578 | pdev->name); | |
579 | ||
580 | if (db->addr_req == NULL) { | |
581 | dev_err(db->dev, "cannot claim address reg area\n"); | |
582 | ret = -EIO; | |
583 | goto out; | |
584 | } | |
585 | ||
586 | db->io_addr = ioremap(db->addr_res->start, iosize); | |
587 | ||
588 | if (db->io_addr == NULL) { | |
589 | dev_err(db->dev, "failed to ioremap address reg\n"); | |
590 | ret = -EINVAL; | |
591 | goto out; | |
592 | } | |
593 | ||
594 | iosize = res_size(db->data_res); | |
595 | db->data_req = request_mem_region(db->data_res->start, iosize, | |
596 | pdev->name); | |
597 | ||
598 | if (db->data_req == NULL) { | |
599 | dev_err(db->dev, "cannot claim data reg area\n"); | |
600 | ret = -EIO; | |
601 | goto out; | |
602 | } | |
603 | ||
604 | db->io_data = ioremap(db->data_res->start, iosize); | |
605 | ||
606 | if (db->io_data == NULL) { | |
607 | dev_err(db->dev, "failed to ioremap data reg\n"); | |
608 | ret = -EINVAL; | |
609 | goto out; | |
610 | } | |
611 | ||
612 | /* fill in parameters for net-dev structure */ | |
613 | ndev->base_addr = (unsigned long)db->io_addr; | |
614 | ndev->irq = db->irq_res->start; | |
615 | ||
616 | /* ensure at least we have a default set of IO routines */ | |
617 | dm9000_set_io(db, iosize); | |
618 | ||
a1365275 SH |
619 | /* check to see if anything is being over-ridden */ |
620 | if (pdata != NULL) { | |
621 | /* check to see if the driver wants to over-ride the | |
622 | * default IO width */ | |
623 | ||
624 | if (pdata->flags & DM9000_PLATF_8BITONLY) | |
625 | dm9000_set_io(db, 1); | |
626 | ||
627 | if (pdata->flags & DM9000_PLATF_16BITONLY) | |
628 | dm9000_set_io(db, 2); | |
629 | ||
630 | if (pdata->flags & DM9000_PLATF_32BITONLY) | |
631 | dm9000_set_io(db, 4); | |
632 | ||
633 | /* check to see if there are any IO routine | |
634 | * over-rides */ | |
635 | ||
636 | if (pdata->inblk != NULL) | |
637 | db->inblk = pdata->inblk; | |
638 | ||
639 | if (pdata->outblk != NULL) | |
640 | db->outblk = pdata->outblk; | |
641 | ||
642 | if (pdata->dumpblk != NULL) | |
643 | db->dumpblk = pdata->dumpblk; | |
33ba5091 BD |
644 | |
645 | db->flags = pdata->flags; | |
a1365275 SH |
646 | } |
647 | ||
648 | dm9000_reset(db); | |
649 | ||
650 | /* try two times, DM9000 sometimes gets the first read wrong */ | |
513b6bee | 651 | for (i = 0; i < 8; i++) { |
a1365275 SH |
652 | id_val = ior(db, DM9000_VIDL); |
653 | id_val |= (u32)ior(db, DM9000_VIDH) << 8; | |
654 | id_val |= (u32)ior(db, DM9000_PIDL) << 16; | |
655 | id_val |= (u32)ior(db, DM9000_PIDH) << 24; | |
656 | ||
657 | if (id_val == DM9000_ID) | |
658 | break; | |
a76836f9 | 659 | dev_err(db->dev, "read wrong id 0x%08x\n", id_val); |
a1365275 SH |
660 | } |
661 | ||
662 | if (id_val != DM9000_ID) { | |
a76836f9 | 663 | dev_err(db->dev, "wrong id: 0x%08x\n", id_val); |
418d6f87 MR |
664 | ret = -ENODEV; |
665 | goto out; | |
a1365275 SH |
666 | } |
667 | ||
668 | /* from this point we assume that we have found a DM9000 */ | |
669 | ||
670 | /* driver system function */ | |
671 | ether_setup(ndev); | |
672 | ||
673 | ndev->open = &dm9000_open; | |
674 | ndev->hard_start_xmit = &dm9000_start_xmit; | |
675 | ndev->tx_timeout = &dm9000_timeout; | |
676 | ndev->watchdog_timeo = msecs_to_jiffies(watchdog); | |
677 | ndev->stop = &dm9000_stop; | |
a1365275 | 678 | ndev->set_multicast_list = &dm9000_hash_table; |
7da99859 | 679 | ndev->ethtool_ops = &dm9000_ethtool_ops; |
f42d8aea | 680 | ndev->do_ioctl = &dm9000_ioctl; |
7da99859 | 681 | |
2fd0e33f KH |
682 | #ifdef CONFIG_NET_POLL_CONTROLLER |
683 | ndev->poll_controller = &dm9000_poll_controller; | |
684 | #endif | |
a1365275 | 685 | |
a1365275 SH |
686 | db->msg_enable = NETIF_MSG_LINK; |
687 | db->mii.phy_id_mask = 0x1f; | |
688 | db->mii.reg_num_mask = 0x1f; | |
689 | db->mii.force_media = 0; | |
690 | db->mii.full_duplex = 0; | |
691 | db->mii.dev = ndev; | |
692 | db->mii.mdio_read = dm9000_phy_read; | |
693 | db->mii.mdio_write = dm9000_phy_write; | |
694 | ||
179c743f BD |
695 | mac_src = "eeprom"; |
696 | ||
86c62fab BD |
697 | /* try reading the node address from the attached EEPROM */ |
698 | for (i = 0; i < 6; i += 2) | |
699 | dm9000_read_eeprom(db, i / 2, ndev->dev_addr+i); | |
a1365275 | 700 | |
5b55dda6 BD |
701 | if (!is_valid_ether_addr(ndev->dev_addr)) { |
702 | /* try reading from mac */ | |
7d2e3cb7 | 703 | |
179c743f | 704 | mac_src = "chip"; |
5b55dda6 BD |
705 | for (i = 0; i < 6; i++) |
706 | ndev->dev_addr[i] = ior(db, i+DM9000_PAR); | |
707 | } | |
708 | ||
a1365275 | 709 | if (!is_valid_ether_addr(ndev->dev_addr)) |
a76836f9 BD |
710 | dev_warn(db->dev, "%s: Invalid ethernet MAC address. Please " |
711 | "set using ifconfig\n", ndev->name); | |
a1365275 | 712 | |
3ae5eaec | 713 | platform_set_drvdata(pdev, ndev); |
a1365275 SH |
714 | ret = register_netdev(ndev); |
715 | ||
716 | if (ret == 0) { | |
0795af57 | 717 | DECLARE_MAC_BUF(mac); |
179c743f | 718 | printk("%s: dm9000 at %p,%p IRQ %d MAC: %s (%s)\n", |
0795af57 | 719 | ndev->name, db->io_addr, db->io_data, ndev->irq, |
179c743f | 720 | print_mac(mac, ndev->dev_addr), mac_src); |
a1365275 SH |
721 | } |
722 | return 0; | |
723 | ||
418d6f87 | 724 | out: |
a76836f9 | 725 | dev_err(db->dev, "not found (%d).\n", ret); |
a1365275 SH |
726 | |
727 | dm9000_release_board(pdev, db); | |
9fd9f9b6 | 728 | free_netdev(ndev); |
a1365275 SH |
729 | |
730 | return ret; | |
731 | } | |
732 | ||
733 | /* | |
734 | * Open the interface. | |
735 | * The interface is opened whenever "ifconfig" actives it. | |
736 | */ | |
737 | static int | |
738 | dm9000_open(struct net_device *dev) | |
739 | { | |
740 | board_info_t *db = (board_info_t *) dev->priv; | |
1a5f1c4f | 741 | unsigned long irqflags = db->irq_res->flags & IRQF_TRIGGER_MASK; |
a1365275 | 742 | |
c991d168 BD |
743 | if (netif_msg_ifup(db)) |
744 | dev_dbg(db->dev, "enabling %s\n", dev->name); | |
a1365275 | 745 | |
1a5f1c4f BD |
746 | /* If there is no IRQ type specified, default to something that |
747 | * may work, and tell the user that this is a problem */ | |
748 | ||
749 | if (irqflags == IRQF_TRIGGER_NONE) { | |
750 | dev_warn(db->dev, "WARNING: no IRQ resource flags set.\n"); | |
751 | irqflags = DEFAULT_TRIGGER; | |
752 | } | |
7d2e3cb7 | 753 | |
1a5f1c4f BD |
754 | irqflags |= IRQF_SHARED; |
755 | ||
756 | if (request_irq(dev->irq, &dm9000_interrupt, irqflags, dev->name, dev)) | |
a1365275 SH |
757 | return -EAGAIN; |
758 | ||
759 | /* Initialize DM9000 board */ | |
760 | dm9000_reset(db); | |
761 | dm9000_init_dm9000(dev); | |
762 | ||
763 | /* Init driver variable */ | |
764 | db->dbug_cnt = 0; | |
765 | ||
a1365275 SH |
766 | mii_check_media(&db->mii, netif_msg_link(db), 1); |
767 | netif_start_queue(dev); | |
8f5bf5f2 BD |
768 | |
769 | dm9000_schedule_poll(db); | |
a1365275 SH |
770 | |
771 | return 0; | |
772 | } | |
773 | ||
774 | /* | |
775 | * Initilize dm9000 board | |
776 | */ | |
777 | static void | |
778 | dm9000_init_dm9000(struct net_device *dev) | |
779 | { | |
780 | board_info_t *db = (board_info_t *) dev->priv; | |
781 | ||
5b2b4ff0 | 782 | dm9000_dbg(db, 1, "entering %s\n", __func__); |
a1365275 SH |
783 | |
784 | /* I/O mode */ | |
785 | db->io_mode = ior(db, DM9000_ISR) >> 6; /* ISR bit7:6 keeps I/O mode */ | |
786 | ||
787 | /* GPIO0 on pre-activate PHY */ | |
788 | iow(db, DM9000_GPR, 0); /* REG_1F bit0 activate phyxcer */ | |
789 | iow(db, DM9000_GPCR, GPCR_GEP_CNTL); /* Let GPIO0 output */ | |
790 | iow(db, DM9000_GPR, 0); /* Enable PHY */ | |
791 | ||
33ba5091 BD |
792 | if (db->flags & DM9000_PLATF_EXT_PHY) |
793 | iow(db, DM9000_NCR, NCR_EXT_PHY); | |
794 | ||
a1365275 SH |
795 | /* Program operating register */ |
796 | iow(db, DM9000_TCR, 0); /* TX Polling clear */ | |
797 | iow(db, DM9000_BPTR, 0x3f); /* Less 3Kb, 200us */ | |
798 | iow(db, DM9000_FCR, 0xff); /* Flow Control */ | |
799 | iow(db, DM9000_SMCR, 0); /* Special Mode */ | |
800 | /* clear TX status */ | |
801 | iow(db, DM9000_NSR, NSR_WAKEST | NSR_TX2END | NSR_TX1END); | |
802 | iow(db, DM9000_ISR, ISR_CLR_STATUS); /* Clear interrupt status */ | |
803 | ||
804 | /* Set address filter table */ | |
805 | dm9000_hash_table(dev); | |
806 | ||
a1365275 SH |
807 | /* Enable TX/RX interrupt mask */ |
808 | iow(db, DM9000_IMR, IMR_PAR | IMR_PTM | IMR_PRM); | |
809 | ||
810 | /* Init Driver variable */ | |
811 | db->tx_pkt_cnt = 0; | |
812 | db->queue_pkt_len = 0; | |
813 | dev->trans_start = 0; | |
a1365275 SH |
814 | } |
815 | ||
816 | /* | |
817 | * Hardware start transmission. | |
818 | * Send a packet to media from the upper layer. | |
819 | */ | |
820 | static int | |
821 | dm9000_start_xmit(struct sk_buff *skb, struct net_device *dev) | |
822 | { | |
c46ac946 | 823 | unsigned long flags; |
a1365275 SH |
824 | board_info_t *db = (board_info_t *) dev->priv; |
825 | ||
5b2b4ff0 | 826 | dm9000_dbg(db, 3, "%s:\n", __func__); |
a1365275 SH |
827 | |
828 | if (db->tx_pkt_cnt > 1) | |
829 | return 1; | |
830 | ||
c46ac946 | 831 | spin_lock_irqsave(&db->lock, flags); |
a1365275 SH |
832 | |
833 | /* Move data to DM9000 TX RAM */ | |
834 | writeb(DM9000_MWCMD, db->io_addr); | |
835 | ||
836 | (db->outblk)(db->io_data, skb->data, skb->len); | |
09f75cd7 | 837 | dev->stats.tx_bytes += skb->len; |
a1365275 | 838 | |
c46ac946 | 839 | db->tx_pkt_cnt++; |
a1365275 | 840 | /* TX control: First packet immediately send, second packet queue */ |
c46ac946 | 841 | if (db->tx_pkt_cnt == 1) { |
a1365275 | 842 | /* Set TX length to DM9000 */ |
073d3f46 BD |
843 | iow(db, DM9000_TXPLL, skb->len); |
844 | iow(db, DM9000_TXPLH, skb->len >> 8); | |
a1365275 SH |
845 | |
846 | /* Issue TX polling command */ | |
847 | iow(db, DM9000_TCR, TCR_TXREQ); /* Cleared after TX complete */ | |
848 | ||
849 | dev->trans_start = jiffies; /* save the time stamp */ | |
a1365275 SH |
850 | } else { |
851 | /* Second packet */ | |
a1365275 | 852 | db->queue_pkt_len = skb->len; |
c46ac946 | 853 | netif_stop_queue(dev); |
a1365275 SH |
854 | } |
855 | ||
c46ac946 FW |
856 | spin_unlock_irqrestore(&db->lock, flags); |
857 | ||
a1365275 SH |
858 | /* free this SKB */ |
859 | dev_kfree_skb(skb); | |
860 | ||
a1365275 SH |
861 | return 0; |
862 | } | |
863 | ||
864 | static void | |
865 | dm9000_shutdown(struct net_device *dev) | |
866 | { | |
867 | board_info_t *db = (board_info_t *) dev->priv; | |
868 | ||
869 | /* RESET device */ | |
870 | dm9000_phy_write(dev, 0, MII_BMCR, BMCR_RESET); /* PHY RESET */ | |
871 | iow(db, DM9000_GPR, 0x01); /* Power-Down PHY */ | |
872 | iow(db, DM9000_IMR, IMR_PAR); /* Disable all interrupt */ | |
873 | iow(db, DM9000_RCR, 0x00); /* Disable RX */ | |
874 | } | |
875 | ||
876 | /* | |
877 | * Stop the interface. | |
878 | * The interface is stopped when it is brought. | |
879 | */ | |
880 | static int | |
881 | dm9000_stop(struct net_device *ndev) | |
882 | { | |
883 | board_info_t *db = (board_info_t *) ndev->priv; | |
884 | ||
c991d168 BD |
885 | if (netif_msg_ifdown(db)) |
886 | dev_dbg(db->dev, "shutting down %s\n", ndev->name); | |
a1365275 | 887 | |
5bceeda3 | 888 | cancel_delayed_work_sync(&db->phy_poll); |
8f5bf5f2 | 889 | |
a1365275 SH |
890 | netif_stop_queue(ndev); |
891 | netif_carrier_off(ndev); | |
892 | ||
893 | /* free interrupt */ | |
894 | free_irq(ndev->irq, ndev); | |
895 | ||
896 | dm9000_shutdown(ndev); | |
897 | ||
898 | return 0; | |
899 | } | |
900 | ||
901 | /* | |
902 | * DM9000 interrupt handler | |
903 | * receive the packet to upper layer, free the transmitted packet | |
904 | */ | |
905 | ||
5d22a312 | 906 | static void |
a1365275 SH |
907 | dm9000_tx_done(struct net_device *dev, board_info_t * db) |
908 | { | |
909 | int tx_status = ior(db, DM9000_NSR); /* Got TX status */ | |
910 | ||
911 | if (tx_status & (NSR_TX2END | NSR_TX1END)) { | |
912 | /* One packet sent complete */ | |
913 | db->tx_pkt_cnt--; | |
09f75cd7 | 914 | dev->stats.tx_packets++; |
a1365275 | 915 | |
c991d168 BD |
916 | if (netif_msg_tx_done(db)) |
917 | dev_dbg(db->dev, "tx done, NSR %02x\n", tx_status); | |
918 | ||
a1365275 SH |
919 | /* Queue packet check & send */ |
920 | if (db->tx_pkt_cnt > 0) { | |
073d3f46 BD |
921 | iow(db, DM9000_TXPLL, db->queue_pkt_len); |
922 | iow(db, DM9000_TXPLH, db->queue_pkt_len >> 8); | |
a1365275 SH |
923 | iow(db, DM9000_TCR, TCR_TXREQ); |
924 | dev->trans_start = jiffies; | |
925 | } | |
926 | netif_wake_queue(dev); | |
927 | } | |
928 | } | |
929 | ||
930 | static irqreturn_t | |
7d12e780 | 931 | dm9000_interrupt(int irq, void *dev_id) |
a1365275 SH |
932 | { |
933 | struct net_device *dev = dev_id; | |
5b2b4ff0 | 934 | board_info_t *db = (board_info_t *) dev->priv; |
a1365275 SH |
935 | int int_status; |
936 | u8 reg_save; | |
937 | ||
5b2b4ff0 | 938 | dm9000_dbg(db, 3, "entering %s\n", __func__); |
a1365275 SH |
939 | |
940 | /* A real interrupt coming */ | |
5b2b4ff0 | 941 | |
a1365275 SH |
942 | spin_lock(&db->lock); |
943 | ||
944 | /* Save previous register address */ | |
945 | reg_save = readb(db->io_addr); | |
946 | ||
947 | /* Disable all interrupts */ | |
948 | iow(db, DM9000_IMR, IMR_PAR); | |
949 | ||
950 | /* Got DM9000 interrupt status */ | |
951 | int_status = ior(db, DM9000_ISR); /* Got ISR */ | |
952 | iow(db, DM9000_ISR, int_status); /* Clear ISR status */ | |
953 | ||
c991d168 BD |
954 | if (netif_msg_intr(db)) |
955 | dev_dbg(db->dev, "interrupt status %02x\n", int_status); | |
956 | ||
a1365275 SH |
957 | /* Received the coming packet */ |
958 | if (int_status & ISR_PRS) | |
959 | dm9000_rx(dev); | |
960 | ||
961 | /* Trnasmit Interrupt check */ | |
962 | if (int_status & ISR_PTS) | |
963 | dm9000_tx_done(dev, db); | |
964 | ||
965 | /* Re-enable interrupt mask */ | |
966 | iow(db, DM9000_IMR, IMR_PAR | IMR_PTM | IMR_PRM); | |
967 | ||
968 | /* Restore previous register address */ | |
969 | writeb(reg_save, db->io_addr); | |
970 | ||
971 | spin_unlock(&db->lock); | |
972 | ||
973 | return IRQ_HANDLED; | |
974 | } | |
975 | ||
a1365275 | 976 | struct dm9000_rxhdr { |
93116573 BD |
977 | u8 RxPktReady; |
978 | u8 RxStatus; | |
8b9fc8ae | 979 | __le16 RxLen; |
a1365275 SH |
980 | } __attribute__((__packed__)); |
981 | ||
982 | /* | |
983 | * Received a packet and pass to upper layer | |
984 | */ | |
985 | static void | |
986 | dm9000_rx(struct net_device *dev) | |
987 | { | |
988 | board_info_t *db = (board_info_t *) dev->priv; | |
989 | struct dm9000_rxhdr rxhdr; | |
990 | struct sk_buff *skb; | |
991 | u8 rxbyte, *rdptr; | |
6478fac6 | 992 | bool GoodPacket; |
a1365275 SH |
993 | int RxLen; |
994 | ||
995 | /* Check packet ready or not */ | |
996 | do { | |
997 | ior(db, DM9000_MRCMDX); /* Dummy read */ | |
998 | ||
999 | /* Get most updated data */ | |
1000 | rxbyte = readb(db->io_data); | |
1001 | ||
1002 | /* Status check: this byte must be 0 or 1 */ | |
1003 | if (rxbyte > DM9000_PKT_RDY) { | |
a76836f9 | 1004 | dev_warn(db->dev, "status check fail: %d\n", rxbyte); |
a1365275 SH |
1005 | iow(db, DM9000_RCR, 0x00); /* Stop Device */ |
1006 | iow(db, DM9000_ISR, IMR_PAR); /* Stop INT request */ | |
1007 | return; | |
1008 | } | |
1009 | ||
1010 | if (rxbyte != DM9000_PKT_RDY) | |
1011 | return; | |
1012 | ||
1013 | /* A packet ready now & Get status/length */ | |
6478fac6 | 1014 | GoodPacket = true; |
a1365275 SH |
1015 | writeb(DM9000_MRCMD, db->io_addr); |
1016 | ||
1017 | (db->inblk)(db->io_data, &rxhdr, sizeof(rxhdr)); | |
1018 | ||
93116573 | 1019 | RxLen = le16_to_cpu(rxhdr.RxLen); |
a1365275 | 1020 | |
c991d168 BD |
1021 | if (netif_msg_rx_status(db)) |
1022 | dev_dbg(db->dev, "RX: status %02x, length %04x\n", | |
1023 | rxhdr.RxStatus, RxLen); | |
1024 | ||
a1365275 SH |
1025 | /* Packet Status check */ |
1026 | if (RxLen < 0x40) { | |
6478fac6 | 1027 | GoodPacket = false; |
c991d168 BD |
1028 | if (netif_msg_rx_err(db)) |
1029 | dev_dbg(db->dev, "RX: Bad Packet (runt)\n"); | |
a1365275 SH |
1030 | } |
1031 | ||
1032 | if (RxLen > DM9000_PKT_MAX) { | |
a76836f9 | 1033 | dev_dbg(db->dev, "RST: RX Len:%x\n", RxLen); |
a1365275 SH |
1034 | } |
1035 | ||
93116573 | 1036 | if (rxhdr.RxStatus & 0xbf) { |
6478fac6 | 1037 | GoodPacket = false; |
93116573 | 1038 | if (rxhdr.RxStatus & 0x01) { |
c991d168 BD |
1039 | if (netif_msg_rx_err(db)) |
1040 | dev_dbg(db->dev, "fifo error\n"); | |
09f75cd7 | 1041 | dev->stats.rx_fifo_errors++; |
a1365275 | 1042 | } |
93116573 | 1043 | if (rxhdr.RxStatus & 0x02) { |
c991d168 BD |
1044 | if (netif_msg_rx_err(db)) |
1045 | dev_dbg(db->dev, "crc error\n"); | |
09f75cd7 | 1046 | dev->stats.rx_crc_errors++; |
a1365275 | 1047 | } |
93116573 | 1048 | if (rxhdr.RxStatus & 0x80) { |
c991d168 BD |
1049 | if (netif_msg_rx_err(db)) |
1050 | dev_dbg(db->dev, "length error\n"); | |
09f75cd7 | 1051 | dev->stats.rx_length_errors++; |
a1365275 SH |
1052 | } |
1053 | } | |
1054 | ||
1055 | /* Move data from DM9000 */ | |
1056 | if (GoodPacket | |
1057 | && ((skb = dev_alloc_skb(RxLen + 4)) != NULL)) { | |
a1365275 SH |
1058 | skb_reserve(skb, 2); |
1059 | rdptr = (u8 *) skb_put(skb, RxLen - 4); | |
1060 | ||
1061 | /* Read received packet from RX SRAM */ | |
1062 | ||
1063 | (db->inblk)(db->io_data, rdptr, RxLen); | |
09f75cd7 | 1064 | dev->stats.rx_bytes += RxLen; |
a1365275 SH |
1065 | |
1066 | /* Pass to upper layer */ | |
1067 | skb->protocol = eth_type_trans(skb, dev); | |
1068 | netif_rx(skb); | |
09f75cd7 | 1069 | dev->stats.rx_packets++; |
a1365275 SH |
1070 | |
1071 | } else { | |
1072 | /* need to dump the packet's data */ | |
1073 | ||
1074 | (db->dumpblk)(db->io_data, RxLen); | |
1075 | } | |
1076 | } while (rxbyte == DM9000_PKT_RDY); | |
1077 | } | |
1078 | ||
39c341a8 BD |
1079 | static unsigned int |
1080 | dm9000_read_locked(board_info_t *db, int reg) | |
1081 | { | |
1082 | unsigned long flags; | |
1083 | unsigned int ret; | |
1084 | ||
1085 | spin_lock_irqsave(&db->lock, flags); | |
1086 | ret = ior(db, reg); | |
1087 | spin_unlock_irqrestore(&db->lock, flags); | |
1088 | ||
1089 | return ret; | |
1090 | } | |
1091 | ||
1092 | static int dm9000_wait_eeprom(board_info_t *db) | |
1093 | { | |
1094 | unsigned int status; | |
1095 | int timeout = 8; /* wait max 8msec */ | |
1096 | ||
1097 | /* The DM9000 data sheets say we should be able to | |
1098 | * poll the ERRE bit in EPCR to wait for the EEPROM | |
1099 | * operation. From testing several chips, this bit | |
7d2e3cb7 | 1100 | * does not seem to work. |
39c341a8 BD |
1101 | * |
1102 | * We attempt to use the bit, but fall back to the | |
1103 | * timeout (which is why we do not return an error | |
1104 | * on expiry) to say that the EEPROM operation has | |
1105 | * completed. | |
1106 | */ | |
1107 | ||
1108 | while (1) { | |
1109 | status = dm9000_read_locked(db, DM9000_EPCR); | |
1110 | ||
1111 | if ((status & EPCR_ERRE) == 0) | |
1112 | break; | |
1113 | ||
1114 | if (timeout-- < 0) { | |
1115 | dev_dbg(db->dev, "timeout waiting EEPROM\n"); | |
1116 | break; | |
1117 | } | |
1118 | } | |
1119 | ||
1120 | return 0; | |
1121 | } | |
1122 | ||
a1365275 | 1123 | /* |
86c62fab | 1124 | * Read a word data from EEPROM |
a1365275 | 1125 | */ |
86c62fab | 1126 | static void |
29d52e54 | 1127 | dm9000_read_eeprom(board_info_t *db, int offset, u8 *to) |
a1365275 | 1128 | { |
621ddcb0 BD |
1129 | unsigned long flags; |
1130 | ||
bb44fb70 BD |
1131 | if (db->flags & DM9000_PLATF_NO_EEPROM) { |
1132 | to[0] = 0xff; | |
1133 | to[1] = 0xff; | |
1134 | return; | |
1135 | } | |
1136 | ||
9a2f037c BD |
1137 | mutex_lock(&db->addr_lock); |
1138 | ||
621ddcb0 BD |
1139 | spin_lock_irqsave(&db->lock, flags); |
1140 | ||
a1365275 SH |
1141 | iow(db, DM9000_EPAR, offset); |
1142 | iow(db, DM9000_EPCR, EPCR_ERPRR); | |
621ddcb0 BD |
1143 | |
1144 | spin_unlock_irqrestore(&db->lock, flags); | |
1145 | ||
39c341a8 BD |
1146 | dm9000_wait_eeprom(db); |
1147 | ||
1148 | /* delay for at-least 150uS */ | |
1149 | msleep(1); | |
621ddcb0 BD |
1150 | |
1151 | spin_lock_irqsave(&db->lock, flags); | |
1152 | ||
a1365275 | 1153 | iow(db, DM9000_EPCR, 0x0); |
86c62fab BD |
1154 | |
1155 | to[0] = ior(db, DM9000_EPDRL); | |
1156 | to[1] = ior(db, DM9000_EPDRH); | |
9a2f037c | 1157 | |
621ddcb0 BD |
1158 | spin_unlock_irqrestore(&db->lock, flags); |
1159 | ||
9a2f037c | 1160 | mutex_unlock(&db->addr_lock); |
a1365275 SH |
1161 | } |
1162 | ||
a1365275 SH |
1163 | /* |
1164 | * Write a word data to SROM | |
1165 | */ | |
1166 | static void | |
29d52e54 | 1167 | dm9000_write_eeprom(board_info_t *db, int offset, u8 *data) |
a1365275 | 1168 | { |
621ddcb0 BD |
1169 | unsigned long flags; |
1170 | ||
bb44fb70 BD |
1171 | if (db->flags & DM9000_PLATF_NO_EEPROM) |
1172 | return; | |
1173 | ||
9a2f037c BD |
1174 | mutex_lock(&db->addr_lock); |
1175 | ||
621ddcb0 | 1176 | spin_lock_irqsave(&db->lock, flags); |
a1365275 | 1177 | iow(db, DM9000_EPAR, offset); |
29d52e54 BD |
1178 | iow(db, DM9000_EPDRH, data[1]); |
1179 | iow(db, DM9000_EPDRL, data[0]); | |
a1365275 | 1180 | iow(db, DM9000_EPCR, EPCR_WEP | EPCR_ERPRW); |
621ddcb0 BD |
1181 | spin_unlock_irqrestore(&db->lock, flags); |
1182 | ||
39c341a8 BD |
1183 | dm9000_wait_eeprom(db); |
1184 | ||
1185 | mdelay(1); /* wait at least 150uS to clear */ | |
621ddcb0 BD |
1186 | |
1187 | spin_lock_irqsave(&db->lock, flags); | |
a1365275 | 1188 | iow(db, DM9000_EPCR, 0); |
621ddcb0 | 1189 | spin_unlock_irqrestore(&db->lock, flags); |
9a2f037c BD |
1190 | |
1191 | mutex_unlock(&db->addr_lock); | |
a1365275 SH |
1192 | } |
1193 | ||
a1365275 SH |
1194 | /* |
1195 | * Set DM9000 multicast address | |
1196 | */ | |
1197 | static void | |
1198 | dm9000_hash_table(struct net_device *dev) | |
1199 | { | |
1200 | board_info_t *db = (board_info_t *) dev->priv; | |
1201 | struct dev_mc_list *mcptr = dev->mc_list; | |
1202 | int mc_cnt = dev->mc_count; | |
d39cb786 | 1203 | int i, oft; |
a1365275 | 1204 | u32 hash_val; |
d39cb786 | 1205 | u16 hash_table[4]; |
23d245b6 | 1206 | u8 rcr = RCR_DIS_LONG | RCR_DIS_CRC | RCR_RXEN; |
a1365275 SH |
1207 | unsigned long flags; |
1208 | ||
5b2b4ff0 | 1209 | dm9000_dbg(db, 1, "entering %s\n", __func__); |
a1365275 | 1210 | |
d39cb786 | 1211 | spin_lock_irqsave(&db->lock, flags); |
a1365275 | 1212 | |
d39cb786 | 1213 | for (i = 0, oft = DM9000_PAR; i < 6; i++, oft++) |
a1365275 SH |
1214 | iow(db, oft, dev->dev_addr[i]); |
1215 | ||
1216 | /* Clear Hash Table */ | |
1217 | for (i = 0; i < 4; i++) | |
1218 | hash_table[i] = 0x0; | |
1219 | ||
1220 | /* broadcast address */ | |
1221 | hash_table[3] = 0x8000; | |
1222 | ||
23d245b6 PK |
1223 | if (dev->flags & IFF_PROMISC) |
1224 | rcr |= RCR_PRMSC; | |
1225 | ||
1226 | if (dev->flags & IFF_ALLMULTI) | |
1227 | rcr |= RCR_ALL; | |
1228 | ||
a1365275 SH |
1229 | /* the multicast address in Hash Table : 64 bits */ |
1230 | for (i = 0; i < mc_cnt; i++, mcptr = mcptr->next) { | |
d39cb786 | 1231 | hash_val = ether_crc_le(6, mcptr->dmi_addr) & 0x3f; |
a1365275 SH |
1232 | hash_table[hash_val / 16] |= (u16) 1 << (hash_val % 16); |
1233 | } | |
1234 | ||
1235 | /* Write the hash table to MAC MD table */ | |
d39cb786 BD |
1236 | for (i = 0, oft = DM9000_MAR; i < 4; i++) { |
1237 | iow(db, oft++, hash_table[i]); | |
1238 | iow(db, oft++, hash_table[i] >> 8); | |
a1365275 SH |
1239 | } |
1240 | ||
23d245b6 | 1241 | iow(db, DM9000_RCR, rcr); |
d39cb786 | 1242 | spin_unlock_irqrestore(&db->lock, flags); |
a1365275 SH |
1243 | } |
1244 | ||
1245 | ||
321f69a4 BD |
1246 | /* |
1247 | * Sleep, either by using msleep() or if we are suspending, then | |
1248 | * use mdelay() to sleep. | |
1249 | */ | |
1250 | static void dm9000_msleep(board_info_t *db, unsigned int ms) | |
1251 | { | |
1252 | if (db->in_suspend) | |
1253 | mdelay(ms); | |
1254 | else | |
1255 | msleep(ms); | |
1256 | } | |
1257 | ||
a1365275 SH |
1258 | /* |
1259 | * Read a word from phyxcer | |
1260 | */ | |
1261 | static int | |
1262 | dm9000_phy_read(struct net_device *dev, int phy_reg_unused, int reg) | |
1263 | { | |
1264 | board_info_t *db = (board_info_t *) dev->priv; | |
1265 | unsigned long flags; | |
9ef9ac51 | 1266 | unsigned int reg_save; |
a1365275 SH |
1267 | int ret; |
1268 | ||
9a2f037c BD |
1269 | mutex_lock(&db->addr_lock); |
1270 | ||
a1365275 | 1271 | spin_lock_irqsave(&db->lock,flags); |
9ef9ac51 BD |
1272 | |
1273 | /* Save previous register address */ | |
1274 | reg_save = readb(db->io_addr); | |
1275 | ||
a1365275 SH |
1276 | /* Fill the phyxcer register into REG_0C */ |
1277 | iow(db, DM9000_EPAR, DM9000_PHY | reg); | |
1278 | ||
1279 | iow(db, DM9000_EPCR, 0xc); /* Issue phyxcer read command */ | |
89c8b0e6 BD |
1280 | |
1281 | writeb(reg_save, db->io_addr); | |
1282 | spin_unlock_irqrestore(&db->lock,flags); | |
1283 | ||
321f69a4 | 1284 | dm9000_msleep(db, 1); /* Wait read complete */ |
89c8b0e6 BD |
1285 | |
1286 | spin_lock_irqsave(&db->lock,flags); | |
1287 | reg_save = readb(db->io_addr); | |
1288 | ||
a1365275 SH |
1289 | iow(db, DM9000_EPCR, 0x0); /* Clear phyxcer read command */ |
1290 | ||
1291 | /* The read data keeps on REG_0D & REG_0E */ | |
1292 | ret = (ior(db, DM9000_EPDRH) << 8) | ior(db, DM9000_EPDRL); | |
1293 | ||
9ef9ac51 BD |
1294 | /* restore the previous address */ |
1295 | writeb(reg_save, db->io_addr); | |
a1365275 SH |
1296 | spin_unlock_irqrestore(&db->lock,flags); |
1297 | ||
9a2f037c | 1298 | mutex_unlock(&db->addr_lock); |
37d5dca6 ES |
1299 | |
1300 | dm9000_dbg(db, 5, "phy_read[%02x] -> %04x\n", reg, ret); | |
a1365275 SH |
1301 | return ret; |
1302 | } | |
1303 | ||
1304 | /* | |
1305 | * Write a word to phyxcer | |
1306 | */ | |
1307 | static void | |
1308 | dm9000_phy_write(struct net_device *dev, int phyaddr_unused, int reg, int value) | |
1309 | { | |
1310 | board_info_t *db = (board_info_t *) dev->priv; | |
1311 | unsigned long flags; | |
9ef9ac51 | 1312 | unsigned long reg_save; |
a1365275 | 1313 | |
37d5dca6 | 1314 | dm9000_dbg(db, 5, "phy_write[%02x] = %04x\n", reg, value); |
9a2f037c BD |
1315 | mutex_lock(&db->addr_lock); |
1316 | ||
a1365275 SH |
1317 | spin_lock_irqsave(&db->lock,flags); |
1318 | ||
9ef9ac51 BD |
1319 | /* Save previous register address */ |
1320 | reg_save = readb(db->io_addr); | |
1321 | ||
a1365275 SH |
1322 | /* Fill the phyxcer register into REG_0C */ |
1323 | iow(db, DM9000_EPAR, DM9000_PHY | reg); | |
1324 | ||
1325 | /* Fill the written data into REG_0D & REG_0E */ | |
073d3f46 BD |
1326 | iow(db, DM9000_EPDRL, value); |
1327 | iow(db, DM9000_EPDRH, value >> 8); | |
a1365275 SH |
1328 | |
1329 | iow(db, DM9000_EPCR, 0xa); /* Issue phyxcer write command */ | |
89c8b0e6 BD |
1330 | |
1331 | writeb(reg_save, db->io_addr); | |
9a2f037c | 1332 | spin_unlock_irqrestore(&db->lock, flags); |
89c8b0e6 | 1333 | |
321f69a4 | 1334 | dm9000_msleep(db, 1); /* Wait write complete */ |
89c8b0e6 BD |
1335 | |
1336 | spin_lock_irqsave(&db->lock,flags); | |
1337 | reg_save = readb(db->io_addr); | |
1338 | ||
a1365275 SH |
1339 | iow(db, DM9000_EPCR, 0x0); /* Clear phyxcer write command */ |
1340 | ||
9ef9ac51 BD |
1341 | /* restore the previous address */ |
1342 | writeb(reg_save, db->io_addr); | |
1343 | ||
9a2f037c BD |
1344 | spin_unlock_irqrestore(&db->lock, flags); |
1345 | mutex_unlock(&db->addr_lock); | |
a1365275 SH |
1346 | } |
1347 | ||
1348 | static int | |
3ae5eaec | 1349 | dm9000_drv_suspend(struct platform_device *dev, pm_message_t state) |
a1365275 | 1350 | { |
3ae5eaec | 1351 | struct net_device *ndev = platform_get_drvdata(dev); |
321f69a4 | 1352 | board_info_t *db; |
a1365275 | 1353 | |
9480e307 | 1354 | if (ndev) { |
321f69a4 BD |
1355 | db = (board_info_t *) ndev->priv; |
1356 | db->in_suspend = 1; | |
1357 | ||
a1365275 SH |
1358 | if (netif_running(ndev)) { |
1359 | netif_device_detach(ndev); | |
1360 | dm9000_shutdown(ndev); | |
1361 | } | |
1362 | } | |
1363 | return 0; | |
1364 | } | |
1365 | ||
1366 | static int | |
3ae5eaec | 1367 | dm9000_drv_resume(struct platform_device *dev) |
a1365275 | 1368 | { |
3ae5eaec | 1369 | struct net_device *ndev = platform_get_drvdata(dev); |
a1365275 SH |
1370 | board_info_t *db = (board_info_t *) ndev->priv; |
1371 | ||
9480e307 | 1372 | if (ndev) { |
a1365275 SH |
1373 | |
1374 | if (netif_running(ndev)) { | |
1375 | dm9000_reset(db); | |
1376 | dm9000_init_dm9000(ndev); | |
1377 | ||
1378 | netif_device_attach(ndev); | |
1379 | } | |
321f69a4 BD |
1380 | |
1381 | db->in_suspend = 0; | |
a1365275 SH |
1382 | } |
1383 | return 0; | |
1384 | } | |
1385 | ||
e21fd4f0 | 1386 | static int __devexit |
3ae5eaec | 1387 | dm9000_drv_remove(struct platform_device *pdev) |
a1365275 | 1388 | { |
3ae5eaec | 1389 | struct net_device *ndev = platform_get_drvdata(pdev); |
a1365275 | 1390 | |
3ae5eaec | 1391 | platform_set_drvdata(pdev, NULL); |
a1365275 SH |
1392 | |
1393 | unregister_netdev(ndev); | |
1394 | dm9000_release_board(pdev, (board_info_t *) ndev->priv); | |
9fd9f9b6 | 1395 | free_netdev(ndev); /* free device structure */ |
a1365275 | 1396 | |
a76836f9 | 1397 | dev_dbg(&pdev->dev, "released and freed device\n"); |
a1365275 SH |
1398 | return 0; |
1399 | } | |
1400 | ||
3ae5eaec | 1401 | static struct platform_driver dm9000_driver = { |
5d22a312 BD |
1402 | .driver = { |
1403 | .name = "dm9000", | |
1404 | .owner = THIS_MODULE, | |
1405 | }, | |
a1365275 | 1406 | .probe = dm9000_probe, |
e21fd4f0 | 1407 | .remove = __devexit_p(dm9000_drv_remove), |
a1365275 SH |
1408 | .suspend = dm9000_drv_suspend, |
1409 | .resume = dm9000_drv_resume, | |
1410 | }; | |
1411 | ||
1412 | static int __init | |
1413 | dm9000_init(void) | |
1414 | { | |
7da99859 | 1415 | printk(KERN_INFO "%s Ethernet Driver, V%s\n", CARDNAME, DRV_VERSION); |
2ae2d77c | 1416 | |
3ae5eaec | 1417 | return platform_driver_register(&dm9000_driver); /* search board and register */ |
a1365275 SH |
1418 | } |
1419 | ||
1420 | static void __exit | |
1421 | dm9000_cleanup(void) | |
1422 | { | |
3ae5eaec | 1423 | platform_driver_unregister(&dm9000_driver); |
a1365275 SH |
1424 | } |
1425 | ||
1426 | module_init(dm9000_init); | |
1427 | module_exit(dm9000_cleanup); | |
1428 | ||
1429 | MODULE_AUTHOR("Sascha Hauer, Ben Dooks"); | |
1430 | MODULE_DESCRIPTION("Davicom DM9000 network driver"); | |
1431 | MODULE_LICENSE("GPL"); | |
72abb461 | 1432 | MODULE_ALIAS("platform:dm9000"); |