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ARM: Hide finish_arch_post_lock_switch() from modules
[deliverable/linux.git] / drivers / net / dsa / bcm_sf2.c
CommitLineData
246d7f77
FF		 1/*
2 * Broadcom Starfighter 2 DSA switch driver
3 *
4 * Copyright (C) 2014, Broadcom Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
12#include <linux/list.h>
13#include <linux/module.h>
14#include <linux/netdevice.h>
15#include <linux/interrupt.h>
16#include <linux/platform_device.h>
17#include <linux/of.h>
18#include <linux/phy.h>
19#include <linux/phy_fixed.h>
20#include <linux/mii.h>
21#include <linux/of.h>
22#include <linux/of_irq.h>
23#include <linux/of_address.h>
8b7c94e3 24#include <linux/of_net.h>
246d7f77 25#include <net/dsa.h>
96e65d7f 26#include <linux/ethtool.h>
12f460f2 27#include <linux/if_bridge.h>
aafc66f1 28#include <linux/brcmphy.h>
680060d3
FF		 29#include <linux/etherdevice.h>
30#include <net/switchdev.h>
246d7f77
FF		 31
32#include "bcm_sf2.h"
33#include "bcm_sf2_regs.h"
34
35/* String, offset, and register size in bytes if different from 4 bytes */
36static const struct bcm_sf2_hw_stats bcm_sf2_mib[] = {
37 { "TxOctets", 0x000, 8 },
38 { "TxDropPkts", 0x020 },
39 { "TxQPKTQ0", 0x030 },
40 { "TxBroadcastPkts", 0x040 },
41 { "TxMulticastPkts", 0x050 },
42 { "TxUnicastPKts", 0x060 },
43 { "TxCollisions", 0x070 },
44 { "TxSingleCollision", 0x080 },
45 { "TxMultipleCollision", 0x090 },
46 { "TxDeferredCollision", 0x0a0 },
47 { "TxLateCollision", 0x0b0 },
48 { "TxExcessiveCollision", 0x0c0 },
49 { "TxFrameInDisc", 0x0d0 },
50 { "TxPausePkts", 0x0e0 },
51 { "TxQPKTQ1", 0x0f0 },
52 { "TxQPKTQ2", 0x100 },
53 { "TxQPKTQ3", 0x110 },
54 { "TxQPKTQ4", 0x120 },
55 { "TxQPKTQ5", 0x130 },
56 { "RxOctets", 0x140, 8 },
57 { "RxUndersizePkts", 0x160 },
58 { "RxPausePkts", 0x170 },
59 { "RxPkts64Octets", 0x180 },
60 { "RxPkts65to127Octets", 0x190 },
61 { "RxPkts128to255Octets", 0x1a0 },
62 { "RxPkts256to511Octets", 0x1b0 },
63 { "RxPkts512to1023Octets", 0x1c0 },
64 { "RxPkts1024toMaxPktsOctets", 0x1d0 },
65 { "RxOversizePkts", 0x1e0 },
66 { "RxJabbers", 0x1f0 },
67 { "RxAlignmentErrors", 0x200 },
68 { "RxFCSErrors", 0x210 },
69 { "RxGoodOctets", 0x220, 8 },
70 { "RxDropPkts", 0x240 },
71 { "RxUnicastPkts", 0x250 },
72 { "RxMulticastPkts", 0x260 },
73 { "RxBroadcastPkts", 0x270 },
74 { "RxSAChanges", 0x280 },
75 { "RxFragments", 0x290 },
76 { "RxJumboPkt", 0x2a0 },
77 { "RxSymblErr", 0x2b0 },
78 { "InRangeErrCount", 0x2c0 },
79 { "OutRangeErrCount", 0x2d0 },
80 { "EEELpiEvent", 0x2e0 },
81 { "EEELpiDuration", 0x2f0 },
82 { "RxDiscard", 0x300, 8 },
83 { "TxQPKTQ6", 0x320 },
84 { "TxQPKTQ7", 0x330 },
85 { "TxPkts64Octets", 0x340 },
86 { "TxPkts65to127Octets", 0x350 },
87 { "TxPkts128to255Octets", 0x360 },
88 { "TxPkts256to511Ocets", 0x370 },
89 { "TxPkts512to1023Ocets", 0x380 },
90 { "TxPkts1024toMaxPktOcets", 0x390 },
91};
92
93#define BCM_SF2_STATS_SIZE ARRAY_SIZE(bcm_sf2_mib)
94
95static void bcm_sf2_sw_get_strings(struct dsa_switch *ds,
96 int port, uint8_t *data)
97{
98 unsigned int i;
99
100 for (i = 0; i < BCM_SF2_STATS_SIZE; i++)
101 memcpy(data + i * ETH_GSTRING_LEN,
102 bcm_sf2_mib[i].string, ETH_GSTRING_LEN);
103}
104
105static void bcm_sf2_sw_get_ethtool_stats(struct dsa_switch *ds,
106 int port, uint64_t *data)
107{
108 struct bcm_sf2_priv *priv = ds_to_priv(ds);
109 const struct bcm_sf2_hw_stats *s;
110 unsigned int i;
111 u64 val = 0;
112 u32 offset;
113
114 mutex_lock(&priv->stats_mutex);
115
116 /* Now fetch the per-port counters */
117 for (i = 0; i < BCM_SF2_STATS_SIZE; i++) {
118 s = &bcm_sf2_mib[i];
119
120 /* Do a latched 64-bit read if needed */
121 offset = s->reg + CORE_P_MIB_OFFSET(port);
122 if (s->sizeof_stat == 8)
123 val = core_readq(priv, offset);
124 else
125 val = core_readl(priv, offset);
126
127 data[i] = (u64)val;
128 }
129
130 mutex_unlock(&priv->stats_mutex);
131}
132
133static int bcm_sf2_sw_get_sset_count(struct dsa_switch *ds)
134{
135 return BCM_SF2_STATS_SIZE;
136}
137
b4d2394d 138static char *bcm_sf2_sw_probe(struct device *host_dev, int sw_addr)
246d7f77
FF		 139{
140 return "Broadcom Starfighter 2";
141}
142
b6d045db 143static void bcm_sf2_imp_vlan_setup(struct dsa_switch *ds, int cpu_port)
246d7f77
FF		 144{
145 struct bcm_sf2_priv *priv = ds_to_priv(ds);
146 unsigned int i;
b6d045db
FF		 147 u32 reg;
148
149 /* Enable the IMP Port to be in the same VLAN as the other ports
150 * on a per-port basis such that we only have Port i and IMP in
151 * the same VLAN.
152 */
153 for (i = 0; i < priv->hw_params.num_ports; i++) {
154 if (!((1 << i) & ds->phys_port_mask))
155 continue;
156
157 reg = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(i));
158 reg |= (1 << cpu_port);
159 core_writel(priv, reg, CORE_PORT_VLAN_CTL_PORT(i));
160 }
161}
162
163static void bcm_sf2_imp_setup(struct dsa_switch *ds, int port)
164{
165 struct bcm_sf2_priv *priv = ds_to_priv(ds);
246d7f77
FF		 166 u32 reg, val;
167
168 /* Enable the port memories */
169 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
170 reg &= ~P_TXQ_PSM_VDD(port);
171 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
172
173 /* Enable Broadcast, Multicast, Unicast forwarding to IMP port */
174 reg = core_readl(priv, CORE_IMP_CTL);
175 reg |= (RX_BCST_EN | RX_MCST_EN | RX_UCST_EN);
176 reg &= ~(RX_DIS | TX_DIS);
177 core_writel(priv, reg, CORE_IMP_CTL);
178
179 /* Enable forwarding */
180 core_writel(priv, SW_FWDG_EN, CORE_SWMODE);
181
182 /* Enable IMP port in dumb mode */
183 reg = core_readl(priv, CORE_SWITCH_CTRL);
184 reg |= MII_DUMB_FWDG_EN;
185 core_writel(priv, reg, CORE_SWITCH_CTRL);
186
187 /* Resolve which bit controls the Broadcom tag */
188 switch (port) {
189 case 8:
190 val = BRCM_HDR_EN_P8;
191 break;
192 case 7:
193 val = BRCM_HDR_EN_P7;
194 break;
195 case 5:
196 val = BRCM_HDR_EN_P5;
197 break;
198 default:
199 val = 0;
200 break;
201 }
202
203 /* Enable Broadcom tags for IMP port */
204 reg = core_readl(priv, CORE_BRCM_HDR_CTRL);
205 reg |= val;
206 core_writel(priv, reg, CORE_BRCM_HDR_CTRL);
207
208 /* Enable reception Broadcom tag for CPU TX (switch RX) to
209 * allow us to tag outgoing frames
210 */
211 reg = core_readl(priv, CORE_BRCM_HDR_RX_DIS);
212 reg &= ~(1 << port);
213 core_writel(priv, reg, CORE_BRCM_HDR_RX_DIS);
214
215 /* Enable transmission of Broadcom tags from the switch (CPU RX) to
216 * allow delivering frames to the per-port net_devices
217 */
218 reg = core_readl(priv, CORE_BRCM_HDR_TX_DIS);
219 reg &= ~(1 << port);
220 core_writel(priv, reg, CORE_BRCM_HDR_TX_DIS);
221
222 /* Force link status for IMP port */
223 reg = core_readl(priv, CORE_STS_OVERRIDE_IMP);
224 reg |= (MII_SW_OR | LINK_STS);
225 core_writel(priv, reg, CORE_STS_OVERRIDE_IMP);
246d7f77
FF		 226}
227
450b05c1
FF		 228static void bcm_sf2_eee_enable_set(struct dsa_switch *ds, int port, bool enable)
229{
230 struct bcm_sf2_priv *priv = ds_to_priv(ds);
231 u32 reg;
232
233 reg = core_readl(priv, CORE_EEE_EN_CTRL);
234 if (enable)
235 reg |= 1 << port;
236 else
237 reg &= ~(1 << port);
238 core_writel(priv, reg, CORE_EEE_EN_CTRL);
239}
240
b083668c
FF		 241static void bcm_sf2_gphy_enable_set(struct dsa_switch *ds, bool enable)
242{
243 struct bcm_sf2_priv *priv = ds_to_priv(ds);
244 u32 reg;
245
b083668c 246 reg = reg_readl(priv, REG_SPHY_CNTRL);
9af197a8
FF		 247 if (enable) {
248 reg |= PHY_RESET;
249 reg &= ~(EXT_PWR_DOWN | IDDQ_BIAS | CK25_DIS);
250 reg_writel(priv, reg, REG_SPHY_CNTRL);
251 udelay(21);
252 reg = reg_readl(priv, REG_SPHY_CNTRL);
253 reg &= ~PHY_RESET;
254 } else {
255 reg |= EXT_PWR_DOWN | IDDQ_BIAS | PHY_RESET;
256 reg_writel(priv, reg, REG_SPHY_CNTRL);
257 mdelay(1);
258 reg |= CK25_DIS;
259 }
b083668c 260 reg_writel(priv, reg, REG_SPHY_CNTRL);
9af197a8
FF		 261
262 /* Use PHY-driven LED signaling */
263 if (!enable) {
264 reg = reg_readl(priv, REG_LED_CNTRL(0));
265 reg |= SPDLNK_SRC_SEL;
266 reg_writel(priv, reg, REG_LED_CNTRL(0));
267 }
b083668c
FF		 268}
269
8b7c94e3
FF		 270static inline void bcm_sf2_port_intr_enable(struct bcm_sf2_priv *priv,
271 int port)
272{
273 unsigned int off;
274
275 switch (port) {
276 case 7:
277 off = P7_IRQ_OFF;
278 break;
279 case 0:
280 /* Port 0 interrupts are located on the first bank */
281 intrl2_0_mask_clear(priv, P_IRQ_MASK(P0_IRQ_OFF));
282 return;
283 default:
284 off = P_IRQ_OFF(port);
285 break;
286 }
287
288 intrl2_1_mask_clear(priv, P_IRQ_MASK(off));
289}
290
291static inline void bcm_sf2_port_intr_disable(struct bcm_sf2_priv *priv,
292 int port)
293{
294 unsigned int off;
295
296 switch (port) {
297 case 7:
298 off = P7_IRQ_OFF;
299 break;
300 case 0:
301 /* Port 0 interrupts are located on the first bank */
302 intrl2_0_mask_set(priv, P_IRQ_MASK(P0_IRQ_OFF));
303 intrl2_0_writel(priv, P_IRQ_MASK(P0_IRQ_OFF), INTRL2_CPU_CLEAR);
304 return;
305 default:
306 off = P_IRQ_OFF(port);
307 break;
308 }
309
310 intrl2_1_mask_set(priv, P_IRQ_MASK(off));
311 intrl2_1_writel(priv, P_IRQ_MASK(off), INTRL2_CPU_CLEAR);
312}
313
b6d045db
FF		 314static int bcm_sf2_port_setup(struct dsa_switch *ds, int port,
315 struct phy_device *phy)
246d7f77
FF		 316{
317 struct bcm_sf2_priv *priv = ds_to_priv(ds);
b6d045db 318 s8 cpu_port = ds->dst[ds->index].cpu_port;
246d7f77
FF		 319 u32 reg;
320
321 /* Clear the memory power down */
322 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
323 reg &= ~P_TXQ_PSM_VDD(port);
324 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
325
326 /* Clear the Rx and Tx disable bits and set to no spanning tree */
327 core_writel(priv, 0, CORE_G_PCTL_PORT(port));
328
9af197a8 329 /* Re-enable the GPHY and re-apply workarounds */
8b7c94e3 330 if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1) {
9af197a8
FF		 331 bcm_sf2_gphy_enable_set(ds, true);
332 if (phy) {
333 /* if phy_stop() has been called before, phy
334 * will be in halted state, and phy_start()
335 * will call resume.
336 *
337 * the resume path does not configure back
338 * autoneg settings, and since we hard reset
339 * the phy manually here, we need to reset the
340 * state machine also.
341 */
342 phy->state = PHY_READY;
343 phy_init_hw(phy);
344 }
345 }
346
8b7c94e3
FF		 347 /* Enable MoCA port interrupts to get notified */
348 if (port == priv->moca_port)
349 bcm_sf2_port_intr_enable(priv, port);
246d7f77 350
12f460f2
FF		 351 /* Set this port, and only this one to be in the default VLAN,
352 * if member of a bridge, restore its membership prior to
353 * bringing down this port.
354 */
246d7f77
FF		 355 reg = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(port));
356 reg &= ~PORT_VLAN_CTRL_MASK;
357 reg |= (1 << port);
12f460f2 358 reg |= priv->port_sts[port].vlan_ctl_mask;
246d7f77 359 core_writel(priv, reg, CORE_PORT_VLAN_CTL_PORT(port));
b6d045db
FF		 360
361 bcm_sf2_imp_vlan_setup(ds, cpu_port);
362
450b05c1
FF		 363 /* If EEE was enabled, restore it */
364 if (priv->port_sts[port].eee.eee_enabled)
365 bcm_sf2_eee_enable_set(ds, port, true);
366
b6d045db 367 return 0;
246d7f77
FF		 368}
369
b6d045db
FF		 370static void bcm_sf2_port_disable(struct dsa_switch *ds, int port,
371 struct phy_device *phy)
246d7f77
FF		 372{
373 struct bcm_sf2_priv *priv = ds_to_priv(ds);
374 u32 off, reg;
375
96e65d7f
FF		 376 if (priv->wol_ports_mask & (1 << port))
377 return;
378
8b7c94e3
FF		 379 if (port == priv->moca_port)
380 bcm_sf2_port_intr_disable(priv, port);
b6d045db 381
8b7c94e3 382 if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1)
9af197a8
FF		 383 bcm_sf2_gphy_enable_set(ds, false);
384
246d7f77
FF		 385 if (dsa_is_cpu_port(ds, port))
386 off = CORE_IMP_CTL;
387 else
388 off = CORE_G_PCTL_PORT(port);
389
390 reg = core_readl(priv, off);
391 reg |= RX_DIS | TX_DIS;
392 core_writel(priv, reg, off);
393
394 /* Power down the port memory */
395 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
396 reg |= P_TXQ_PSM_VDD(port);
397 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
398}
399
450b05c1
FF		 400/* Returns 0 if EEE was not enabled, or 1 otherwise
401 */
402static int bcm_sf2_eee_init(struct dsa_switch *ds, int port,
403 struct phy_device *phy)
404{
405 struct bcm_sf2_priv *priv = ds_to_priv(ds);
406 struct ethtool_eee *p = &priv->port_sts[port].eee;
407 int ret;
408
409 p->supported = (SUPPORTED_1000baseT_Full | SUPPORTED_100baseT_Full);
410
411 ret = phy_init_eee(phy, 0);
412 if (ret)
413 return 0;
414
415 bcm_sf2_eee_enable_set(ds, port, true);
416
417 return 1;
418}
419
420static int bcm_sf2_sw_get_eee(struct dsa_switch *ds, int port,
421 struct ethtool_eee *e)
422{
423 struct bcm_sf2_priv *priv = ds_to_priv(ds);
424 struct ethtool_eee *p = &priv->port_sts[port].eee;
425 u32 reg;
426
427 reg = core_readl(priv, CORE_EEE_LPI_INDICATE);
428 e->eee_enabled = p->eee_enabled;
429 e->eee_active = !!(reg & (1 << port));
430
431 return 0;
432}
433
434static int bcm_sf2_sw_set_eee(struct dsa_switch *ds, int port,
435 struct phy_device *phydev,
436 struct ethtool_eee *e)
437{
438 struct bcm_sf2_priv *priv = ds_to_priv(ds);
439 struct ethtool_eee *p = &priv->port_sts[port].eee;
440
441 p->eee_enabled = e->eee_enabled;
442
443 if (!p->eee_enabled) {
444 bcm_sf2_eee_enable_set(ds, port, false);
445 } else {
446 p->eee_enabled = bcm_sf2_eee_init(ds, port, phydev);
447 if (!p->eee_enabled)
448 return -EOPNOTSUPP;
449 }
450
451 return 0;
452}
453
12f460f2
FF		 454/* Fast-ageing of ARL entries for a given port, equivalent to an ARL
455 * flush for that port.
456 */
457static int bcm_sf2_sw_fast_age_port(struct dsa_switch *ds, int port)
458{
459 struct bcm_sf2_priv *priv = ds_to_priv(ds);
460 unsigned int timeout = 1000;
461 u32 reg;
462
463 core_writel(priv, port, CORE_FAST_AGE_PORT);
464
465 reg = core_readl(priv, CORE_FAST_AGE_CTRL);
39797a27 466 reg |= EN_AGE_PORT | EN_AGE_DYNAMIC | FAST_AGE_STR_DONE;
12f460f2
FF		 467 core_writel(priv, reg, CORE_FAST_AGE_CTRL);
468
469 do {
470 reg = core_readl(priv, CORE_FAST_AGE_CTRL);
471 if (!(reg & FAST_AGE_STR_DONE))
472 break;
473
474 cpu_relax();
475 } while (timeout--);
476
477 if (!timeout)
478 return -ETIMEDOUT;
479
39797a27
FF		 480 core_writel(priv, 0, CORE_FAST_AGE_CTRL);
481
12f460f2
FF		 482 return 0;
483}
484
485static int bcm_sf2_sw_br_join(struct dsa_switch *ds, int port,
a6692754 486 struct net_device *bridge)
12f460f2
FF		 487{
488 struct bcm_sf2_priv *priv = ds_to_priv(ds);
489 unsigned int i;
490 u32 reg, p_ctl;
491
a6692754 492 priv->port_sts[port].bridge_dev = bridge;
12f460f2
FF		 493 p_ctl = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(port));
494
495 for (i = 0; i < priv->hw_params.num_ports; i++) {
a6692754 496 if (priv->port_sts[i].bridge_dev != bridge)
12f460f2
FF		 497 continue;
498
499 /* Add this local port to the remote port VLAN control
500 * membership and update the remote port bitmask
501 */
502 reg = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(i));
503 reg |= 1 << port;
504 core_writel(priv, reg, CORE_PORT_VLAN_CTL_PORT(i));
505 priv->port_sts[i].vlan_ctl_mask = reg;
506
507 p_ctl |= 1 << i;
508 }
509
510 /* Configure the local port VLAN control membership to include
511 * remote ports and update the local port bitmask
512 */
513 core_writel(priv, p_ctl, CORE_PORT_VLAN_CTL_PORT(port));
514 priv->port_sts[port].vlan_ctl_mask = p_ctl;
515
516 return 0;
517}
518
16bfa702 519static void bcm_sf2_sw_br_leave(struct dsa_switch *ds, int port)
12f460f2
FF		 520{
521 struct bcm_sf2_priv *priv = ds_to_priv(ds);
a6692754 522 struct net_device *bridge = priv->port_sts[port].bridge_dev;
12f460f2
FF		 523 unsigned int i;
524 u32 reg, p_ctl;
525
526 p_ctl = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(port));
527
528 for (i = 0; i < priv->hw_params.num_ports; i++) {
529 /* Don't touch the remaining ports */
a6692754 530 if (priv->port_sts[i].bridge_dev != bridge)
12f460f2
FF		 531 continue;
532
533 reg = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(i));
534 reg &= ~(1 << port);
535 core_writel(priv, reg, CORE_PORT_VLAN_CTL_PORT(i));
536 priv->port_sts[port].vlan_ctl_mask = reg;
537
538 /* Prevent self removal to preserve isolation */
539 if (port != i)
540 p_ctl &= ~(1 << i);
541 }
542
543 core_writel(priv, p_ctl, CORE_PORT_VLAN_CTL_PORT(port));
544 priv->port_sts[port].vlan_ctl_mask = p_ctl;
a6692754 545 priv->port_sts[port].bridge_dev = NULL;
12f460f2
FF		 546}
547
548static int bcm_sf2_sw_br_set_stp_state(struct dsa_switch *ds, int port,
549 u8 state)
550{
551 struct bcm_sf2_priv *priv = ds_to_priv(ds);
552 u8 hw_state, cur_hw_state;
553 int ret = 0;
554 u32 reg;
555
556 reg = core_readl(priv, CORE_G_PCTL_PORT(port));
39797a27 557 cur_hw_state = reg & (G_MISTP_STATE_MASK << G_MISTP_STATE_SHIFT);
12f460f2
FF		 558
559 switch (state) {
560 case BR_STATE_DISABLED:
561 hw_state = G_MISTP_DIS_STATE;
562 break;
563 case BR_STATE_LISTENING:
564 hw_state = G_MISTP_LISTEN_STATE;
565 break;
566 case BR_STATE_LEARNING:
567 hw_state = G_MISTP_LEARN_STATE;
568 break;
569 case BR_STATE_FORWARDING:
570 hw_state = G_MISTP_FWD_STATE;
571 break;
572 case BR_STATE_BLOCKING:
573 hw_state = G_MISTP_BLOCK_STATE;
574 break;
575 default:
576 pr_err("%s: invalid STP state: %d\n", __func__, state);
577 return -EINVAL;
578 }
579
580 /* Fast-age ARL entries if we are moving a port from Learning or
39797a27
FF		 581 * Forwarding (cur_hw_state) state to Disabled, Blocking or Listening
582 * state (hw_state)
12f460f2
FF		 583 */
584 if (cur_hw_state != hw_state) {
39797a27
FF		 585 if (cur_hw_state >= G_MISTP_LEARN_STATE &&
586 hw_state <= G_MISTP_LISTEN_STATE) {
12f460f2
FF		 587 ret = bcm_sf2_sw_fast_age_port(ds, port);
588 if (ret) {
589 pr_err("%s: fast-ageing failed\n", __func__);
590 return ret;
591 }
592 }
593 }
594
595 reg = core_readl(priv, CORE_G_PCTL_PORT(port));
596 reg &= ~(G_MISTP_STATE_MASK << G_MISTP_STATE_SHIFT);
597 reg |= hw_state;
598 core_writel(priv, reg, CORE_G_PCTL_PORT(port));
599
600 return 0;
601}
602
680060d3
FF		 603/* Address Resolution Logic routines */
604static int bcm_sf2_arl_op_wait(struct bcm_sf2_priv *priv)
605{
606 unsigned int timeout = 10;
607 u32 reg;
608
609 do {
610 reg = core_readl(priv, CORE_ARLA_RWCTL);
611 if (!(reg & ARL_STRTDN))
612 return 0;
613
614 usleep_range(1000, 2000);
615 } while (timeout--);
616
617 return -ETIMEDOUT;
618}
619
620static int bcm_sf2_arl_rw_op(struct bcm_sf2_priv *priv, unsigned int op)
621{
622 u32 cmd;
623
624 if (op > ARL_RW)
625 return -EINVAL;
626
627 cmd = core_readl(priv, CORE_ARLA_RWCTL);
628 cmd &= ~IVL_SVL_SELECT;
629 cmd |= ARL_STRTDN;
630 if (op)
631 cmd |= ARL_RW;
632 else
633 cmd &= ~ARL_RW;
634 core_writel(priv, cmd, CORE_ARLA_RWCTL);
635
636 return bcm_sf2_arl_op_wait(priv);
637}
638
639static int bcm_sf2_arl_read(struct bcm_sf2_priv *priv, u64 mac,
640 u16 vid, struct bcm_sf2_arl_entry *ent, u8 *idx,
641 bool is_valid)
642{
643 unsigned int i;
644 int ret;
645
646 ret = bcm_sf2_arl_op_wait(priv);
647 if (ret)
648 return ret;
649
650 /* Read the 4 bins */
651 for (i = 0; i < 4; i++) {
652 u64 mac_vid;
653 u32 fwd_entry;
654
655 mac_vid = core_readq(priv, CORE_ARLA_MACVID_ENTRY(i));
656 fwd_entry = core_readl(priv, CORE_ARLA_FWD_ENTRY(i));
657 bcm_sf2_arl_to_entry(ent, mac_vid, fwd_entry);
658
659 if (ent->is_valid && is_valid) {
660 *idx = i;
661 return 0;
662 }
663
664 /* This is the MAC we just deleted */
665 if (!is_valid && (mac_vid & mac))
666 return 0;
667 }
668
669 return -ENOENT;
670}
671
672static int bcm_sf2_arl_op(struct bcm_sf2_priv *priv, int op, int port,
673 const unsigned char *addr, u16 vid, bool is_valid)
674{
675 struct bcm_sf2_arl_entry ent;
676 u32 fwd_entry;
677 u64 mac, mac_vid = 0;
678 u8 idx = 0;
679 int ret;
680
681 /* Convert the array into a 64-bit MAC */
682 mac = bcm_sf2_mac_to_u64(addr);
683
684 /* Perform a read for the given MAC and VID */
685 core_writeq(priv, mac, CORE_ARLA_MAC);
686 core_writel(priv, vid, CORE_ARLA_VID);
687
688 /* Issue a read operation for this MAC */
689 ret = bcm_sf2_arl_rw_op(priv, 1);
690 if (ret)
691 return ret;
692
693 ret = bcm_sf2_arl_read(priv, mac, vid, &ent, &idx, is_valid);
694 /* If this is a read, just finish now */
695 if (op)
696 return ret;
697
698 /* We could not find a matching MAC, so reset to a new entry */
699 if (ret) {
700 fwd_entry = 0;
701 idx = 0;
702 }
703
704 memset(&ent, 0, sizeof(ent));
705 ent.port = port;
706 ent.is_valid = is_valid;
707 ent.vid = vid;
708 ent.is_static = true;
709 memcpy(ent.mac, addr, ETH_ALEN);
710 bcm_sf2_arl_from_entry(&mac_vid, &fwd_entry, &ent);
711
712 core_writeq(priv, mac_vid, CORE_ARLA_MACVID_ENTRY(idx));
713 core_writel(priv, fwd_entry, CORE_ARLA_FWD_ENTRY(idx));
714
715 ret = bcm_sf2_arl_rw_op(priv, 0);
716 if (ret)
717 return ret;
718
719 /* Re-read the entry to check */
720 return bcm_sf2_arl_read(priv, mac, vid, &ent, &idx, is_valid);
721}
722
723static int bcm_sf2_sw_fdb_prepare(struct dsa_switch *ds, int port,
724 const struct switchdev_obj_port_fdb *fdb,
725 struct switchdev_trans *trans)
726{
727 /* We do not need to do anything specific here yet */
728 return 0;
729}
730
731static int bcm_sf2_sw_fdb_add(struct dsa_switch *ds, int port,
732 const struct switchdev_obj_port_fdb *fdb,
733 struct switchdev_trans *trans)
734{
735 struct bcm_sf2_priv *priv = ds_to_priv(ds);
736
737 return bcm_sf2_arl_op(priv, 0, port, fdb->addr, fdb->vid, true);
738}
739
740static int bcm_sf2_sw_fdb_del(struct dsa_switch *ds, int port,
741 const struct switchdev_obj_port_fdb *fdb)
742{
743 struct bcm_sf2_priv *priv = ds_to_priv(ds);
744
745 return bcm_sf2_arl_op(priv, 0, port, fdb->addr, fdb->vid, false);
746}
747
748static int bcm_sf2_arl_search_wait(struct bcm_sf2_priv *priv)
749{
750 unsigned timeout = 1000;
751 u32 reg;
752
753 do {
754 reg = core_readl(priv, CORE_ARLA_SRCH_CTL);
755 if (!(reg & ARLA_SRCH_STDN))
756 return 0;
757
758 if (reg & ARLA_SRCH_VLID)
759 return 0;
760
761 usleep_range(1000, 2000);
762 } while (timeout--);
763
764 return -ETIMEDOUT;
765}
766
767static void bcm_sf2_arl_search_rd(struct bcm_sf2_priv *priv, u8 idx,
768 struct bcm_sf2_arl_entry *ent)
769{
770 u64 mac_vid;
771 u32 fwd_entry;
772
773 mac_vid = core_readq(priv, CORE_ARLA_SRCH_RSLT_MACVID(idx));
774 fwd_entry = core_readl(priv, CORE_ARLA_SRCH_RSLT(idx));
775 bcm_sf2_arl_to_entry(ent, mac_vid, fwd_entry);
776}
777
778static int bcm_sf2_sw_fdb_copy(struct net_device *dev, int port,
779 const struct bcm_sf2_arl_entry *ent,
780 struct switchdev_obj_port_fdb *fdb,
781 int (*cb)(struct switchdev_obj *obj))
782{
783 if (!ent->is_valid)
784 return 0;
785
786 if (port != ent->port)
787 return 0;
788
789 ether_addr_copy(fdb->addr, ent->mac);
790 fdb->vid = ent->vid;
791 fdb->ndm_state = ent->is_static ? NUD_NOARP : NUD_REACHABLE;
792
793 return cb(&fdb->obj);
794}
795
796static int bcm_sf2_sw_fdb_dump(struct dsa_switch *ds, int port,
797 struct switchdev_obj_port_fdb *fdb,
798 int (*cb)(struct switchdev_obj *obj))
799{
800 struct bcm_sf2_priv *priv = ds_to_priv(ds);
801 struct net_device *dev = ds->ports[port];
802 struct bcm_sf2_arl_entry results[2];
803 unsigned int count = 0;
804 int ret;
805
806 /* Start search operation */
807 core_writel(priv, ARLA_SRCH_STDN, CORE_ARLA_SRCH_CTL);
808
809 do {
810 ret = bcm_sf2_arl_search_wait(priv);
811 if (ret)
812 return ret;
813
814 /* Read both entries, then return their values back */
815 bcm_sf2_arl_search_rd(priv, 0, &results[0]);
816 ret = bcm_sf2_sw_fdb_copy(dev, port, &results[0], fdb, cb);
817 if (ret)
818 return ret;
819
820 bcm_sf2_arl_search_rd(priv, 1, &results[1]);
821 ret = bcm_sf2_sw_fdb_copy(dev, port, &results[1], fdb, cb);
822 if (ret)
823 return ret;
824
825 if (!results[0].is_valid && !results[1].is_valid)
826 break;
827
828 } while (count++ < CORE_ARLA_NUM_ENTRIES);
829
830 return 0;
831}
832
246d7f77
FF		 833static irqreturn_t bcm_sf2_switch_0_isr(int irq, void *dev_id)
834{
835 struct bcm_sf2_priv *priv = dev_id;
836
837 priv->irq0_stat = intrl2_0_readl(priv, INTRL2_CPU_STATUS) &
838 ~priv->irq0_mask;
839 intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR);
840
841 return IRQ_HANDLED;
842}
843
844static irqreturn_t bcm_sf2_switch_1_isr(int irq, void *dev_id)
845{
846 struct bcm_sf2_priv *priv = dev_id;
847
848 priv->irq1_stat = intrl2_1_readl(priv, INTRL2_CPU_STATUS) &
849 ~priv->irq1_mask;
850 intrl2_1_writel(priv, priv->irq1_stat, INTRL2_CPU_CLEAR);
851
852 if (priv->irq1_stat & P_LINK_UP_IRQ(P7_IRQ_OFF))
853 priv->port_sts[7].link = 1;
854 if (priv->irq1_stat & P_LINK_DOWN_IRQ(P7_IRQ_OFF))
855 priv->port_sts[7].link = 0;
856
857 return IRQ_HANDLED;
858}
859
33f84614
FF		 860static int bcm_sf2_sw_rst(struct bcm_sf2_priv *priv)
861{
862 unsigned int timeout = 1000;
863 u32 reg;
864
865 reg = core_readl(priv, CORE_WATCHDOG_CTRL);
866 reg |= SOFTWARE_RESET | EN_CHIP_RST | EN_SW_RESET;
867 core_writel(priv, reg, CORE_WATCHDOG_CTRL);
868
869 do {
870 reg = core_readl(priv, CORE_WATCHDOG_CTRL);
871 if (!(reg & SOFTWARE_RESET))
872 break;
873
874 usleep_range(1000, 2000);
875 } while (timeout-- > 0);
876
877 if (timeout == 0)
878 return -ETIMEDOUT;
879
880 return 0;
881}
882
691c9a8f
FF		 883static void bcm_sf2_intr_disable(struct bcm_sf2_priv *priv)
884{
885 intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_MASK_SET);
886 intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
887 intrl2_0_writel(priv, 0, INTRL2_CPU_MASK_CLEAR);
888 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_MASK_SET);
889 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
890 intrl2_1_writel(priv, 0, INTRL2_CPU_MASK_CLEAR);
891}
892
8b7c94e3
FF		 893static void bcm_sf2_identify_ports(struct bcm_sf2_priv *priv,
894 struct device_node *dn)
895{
896 struct device_node *port;
897 const char *phy_mode_str;
898 int mode;
899 unsigned int port_num;
900 int ret;
901
902 priv->moca_port = -1;
903
904 for_each_available_child_of_node(dn, port) {
905 if (of_property_read_u32(port, "reg", &port_num))
906 continue;
907
908 /* Internal PHYs get assigned a specific 'phy-mode' property
909 * value: "internal" to help flag them before MDIO probing
910 * has completed, since they might be turned off at that
911 * time
912 */
913 mode = of_get_phy_mode(port);
914 if (mode < 0) {
915 ret = of_property_read_string(port, "phy-mode",
916 &phy_mode_str);
917 if (ret < 0)
918 continue;
919
920 if (!strcasecmp(phy_mode_str, "internal"))
921 priv->int_phy_mask |= 1 << port_num;
922 }
923
924 if (mode == PHY_INTERFACE_MODE_MOCA)
925 priv->moca_port = port_num;
926 }
927}
928
246d7f77
FF		 929static int bcm_sf2_sw_setup(struct dsa_switch *ds)
930{
931 const char *reg_names[BCM_SF2_REGS_NUM] = BCM_SF2_REGS_NAME;
932 struct bcm_sf2_priv *priv = ds_to_priv(ds);
933 struct device_node *dn;
934 void __iomem **base;
935 unsigned int port;
936 unsigned int i;
937 u32 reg, rev;
938 int ret;
939
940 spin_lock_init(&priv->indir_lock);
941 mutex_init(&priv->stats_mutex);
942
943 /* All the interesting properties are at the parent device_node
944 * level
945 */
946 dn = ds->pd->of_node->parent;
8b7c94e3 947 bcm_sf2_identify_ports(priv, ds->pd->of_node);
246d7f77
FF		 948
949 priv->irq0 = irq_of_parse_and_map(dn, 0);
950 priv->irq1 = irq_of_parse_and_map(dn, 1);
951
952 base = &priv->core;
953 for (i = 0; i < BCM_SF2_REGS_NUM; i++) {
954 *base = of_iomap(dn, i);
955 if (*base == NULL) {
956 pr_err("unable to find register: %s\n", reg_names[i]);
a566059d
FF		 957 ret = -ENOMEM;
958 goto out_unmap;
246d7f77
FF		 959 }
960 base++;
961 }
962
33f84614
FF		 963 ret = bcm_sf2_sw_rst(priv);
964 if (ret) {
965 pr_err("unable to software reset switch: %d\n", ret);
966 goto out_unmap;
967 }
968
246d7f77 969 /* Disable all interrupts and request them */
691c9a8f 970 bcm_sf2_intr_disable(priv);
246d7f77
FF		 971
972 ret = request_irq(priv->irq0, bcm_sf2_switch_0_isr, 0,
973 "switch_0", priv);
974 if (ret < 0) {
975 pr_err("failed to request switch_0 IRQ\n");
976 goto out_unmap;
977 }
978
979 ret = request_irq(priv->irq1, bcm_sf2_switch_1_isr, 0,
980 "switch_1", priv);
981 if (ret < 0) {
982 pr_err("failed to request switch_1 IRQ\n");
983 goto out_free_irq0;
984 }
985
986 /* Reset the MIB counters */
987 reg = core_readl(priv, CORE_GMNCFGCFG);
988 reg |= RST_MIB_CNT;
989 core_writel(priv, reg, CORE_GMNCFGCFG);
990 reg &= ~RST_MIB_CNT;
991 core_writel(priv, reg, CORE_GMNCFGCFG);
992
993 /* Get the maximum number of ports for this switch */
994 priv->hw_params.num_ports = core_readl(priv, CORE_IMP0_PRT_ID) + 1;
995 if (priv->hw_params.num_ports > DSA_MAX_PORTS)
996 priv->hw_params.num_ports = DSA_MAX_PORTS;
997
998 /* Assume a single GPHY setup if we can't read that property */
999 if (of_property_read_u32(dn, "brcm,num-gphy",
1000 &priv->hw_params.num_gphy))
1001 priv->hw_params.num_gphy = 1;
1002
1003 /* Enable all valid ports and disable those unused */
1004 for (port = 0; port < priv->hw_params.num_ports; port++) {
1005 /* IMP port receives special treatment */
1006 if ((1 << port) & ds->phys_port_mask)
b6d045db 1007 bcm_sf2_port_setup(ds, port, NULL);
246d7f77
FF		 1008 else if (dsa_is_cpu_port(ds, port))
1009 bcm_sf2_imp_setup(ds, port);
1010 else
b6d045db 1011 bcm_sf2_port_disable(ds, port, NULL);
246d7f77
FF		 1012 }
1013
1014 /* Include the pseudo-PHY address and the broadcast PHY address to
b8c6cd1d
FF		 1015 * divert reads towards our workaround. This is only required for
1016 * 7445D0, since 7445E0 disconnects the internal switch pseudo-PHY such
1017 * that we can use the regular SWITCH_MDIO master controller instead.
1018 *
1019 * By default, DSA initializes ds->phys_mii_mask to ds->phys_port_mask
1020 * to have a 1:1 mapping between Port address and PHY address in order
1021 * to utilize the slave_mii_bus instance to read from Port PHYs. This is
1022 * not what we want here, so we initialize phys_mii_mask 0 to always
1023 * utilize the "master" MDIO bus backed by the "mdio-unimac" driver.
246d7f77 1024 */
b8c6cd1d
FF		 1025 if (of_machine_is_compatible("brcm,bcm7445d0"))
1026 ds->phys_mii_mask |= ((1 << BRCM_PSEUDO_PHY_ADDR) | (1 << 0));
1027 else
1028 ds->phys_mii_mask = 0;
246d7f77
FF		 1029
1030 rev = reg_readl(priv, REG_SWITCH_REVISION);
1031 priv->hw_params.top_rev = (rev >> SWITCH_TOP_REV_SHIFT) &
1032 SWITCH_TOP_REV_MASK;
1033 priv->hw_params.core_rev = (rev & SF2_REV_MASK);
1034
aa9aef77
FF		 1035 rev = reg_readl(priv, REG_PHY_REVISION);
1036 priv->hw_params.gphy_rev = rev & PHY_REVISION_MASK;
1037
246d7f77
FF		 1038 pr_info("Starfighter 2 top: %x.%02x, core: %x.%02x base: 0x%p, IRQs: %d, %d\n",
1039 priv->hw_params.top_rev >> 8, priv->hw_params.top_rev & 0xff,
1040 priv->hw_params.core_rev >> 8, priv->hw_params.core_rev & 0xff,
1041 priv->core, priv->irq0, priv->irq1);
1042
1043 return 0;
1044
1045out_free_irq0:
1046 free_irq(priv->irq0, priv);
1047out_unmap:
1048 base = &priv->core;
1049 for (i = 0; i < BCM_SF2_REGS_NUM; i++) {
a566059d
FF		 1050 if (*base)
1051 iounmap(*base);
246d7f77
FF		 1052 base++;
1053 }
1054 return ret;
1055}
1056
1057static int bcm_sf2_sw_set_addr(struct dsa_switch *ds, u8 *addr)
1058{
1059 return 0;
1060}
1061
aa9aef77
FF		 1062static u32 bcm_sf2_sw_get_phy_flags(struct dsa_switch *ds, int port)
1063{
1064 struct bcm_sf2_priv *priv = ds_to_priv(ds);
1065
1066 /* The BCM7xxx PHY driver expects to find the integrated PHY revision
1067 * in bits 15:8 and the patch level in bits 7:0 which is exactly what
1068 * the REG_PHY_REVISION register layout is.
1069 */
1070
1071 return priv->hw_params.gphy_rev;
1072}
1073
246d7f77
FF		 1074static int bcm_sf2_sw_indir_rw(struct dsa_switch *ds, int op, int addr,
1075 int regnum, u16 val)
1076{
1077 struct bcm_sf2_priv *priv = ds_to_priv(ds);
1078 int ret = 0;
1079 u32 reg;
1080
1081 reg = reg_readl(priv, REG_SWITCH_CNTRL);
1082 reg |= MDIO_MASTER_SEL;
1083 reg_writel(priv, reg, REG_SWITCH_CNTRL);
1084
1085 /* Page << 8 | offset */
1086 reg = 0x70;
1087 reg <<= 2;
1088 core_writel(priv, addr, reg);
1089
1090 /* Page << 8 | offset */
1091 reg = 0x80 << 8 | regnum << 1;
1092 reg <<= 2;
1093
1094 if (op)
1095 ret = core_readl(priv, reg);
1096 else
1097 core_writel(priv, val, reg);
1098
1099 reg = reg_readl(priv, REG_SWITCH_CNTRL);
1100 reg &= ~MDIO_MASTER_SEL;
1101 reg_writel(priv, reg, REG_SWITCH_CNTRL);
1102
1103 return ret & 0xffff;
1104}
1105
1106static int bcm_sf2_sw_phy_read(struct dsa_switch *ds, int addr, int regnum)
1107{
1108 /* Intercept reads from the MDIO broadcast address or Broadcom
1109 * pseudo-PHY address
1110 */
1111 switch (addr) {
1112 case 0:
aafc66f1 1113 case BRCM_PSEUDO_PHY_ADDR:
246d7f77
FF		 1114 return bcm_sf2_sw_indir_rw(ds, 1, addr, regnum, 0);
1115 default:
1116 return 0xffff;
1117 }
1118}
1119
1120static int bcm_sf2_sw_phy_write(struct dsa_switch *ds, int addr, int regnum,
1121 u16 val)
1122{
1123 /* Intercept writes to the MDIO broadcast address or Broadcom
1124 * pseudo-PHY address
1125 */
1126 switch (addr) {
1127 case 0:
aafc66f1 1128 case BRCM_PSEUDO_PHY_ADDR:
246d7f77
FF		 1129 bcm_sf2_sw_indir_rw(ds, 0, addr, regnum, val);
1130 break;
1131 }
1132
1133 return 0;
1134}
1135
1136static void bcm_sf2_sw_adjust_link(struct dsa_switch *ds, int port,
1137 struct phy_device *phydev)
1138{
1139 struct bcm_sf2_priv *priv = ds_to_priv(ds);
1140 u32 id_mode_dis = 0, port_mode;
1141 const char *str = NULL;
1142 u32 reg;
1143
1144 switch (phydev->interface) {
1145 case PHY_INTERFACE_MODE_RGMII:
1146 str = "RGMII (no delay)";
1147 id_mode_dis = 1;
1148 case PHY_INTERFACE_MODE_RGMII_TXID:
1149 if (!str)
1150 str = "RGMII (TX delay)";
1151 port_mode = EXT_GPHY;
1152 break;
1153 case PHY_INTERFACE_MODE_MII:
1154 str = "MII";
1155 port_mode = EXT_EPHY;
1156 break;
1157 case PHY_INTERFACE_MODE_REVMII:
1158 str = "Reverse MII";
1159 port_mode = EXT_REVMII;
1160 break;
1161 default:
7de1557c
FF		 1162 /* All other PHYs: internal and MoCA */
1163 goto force_link;
1164 }
1165
1166 /* If the link is down, just disable the interface to conserve power */
1167 if (!phydev->link) {
1168 reg = reg_readl(priv, REG_RGMII_CNTRL_P(port));
1169 reg &= ~RGMII_MODE_EN;
1170 reg_writel(priv, reg, REG_RGMII_CNTRL_P(port));
246d7f77
FF		 1171 goto force_link;
1172 }
1173
1174 /* Clear id_mode_dis bit, and the existing port mode, but
1175 * make sure we enable the RGMII block for data to pass
1176 */
1177 reg = reg_readl(priv, REG_RGMII_CNTRL_P(port));
1178 reg &= ~ID_MODE_DIS;
1179 reg &= ~(PORT_MODE_MASK << PORT_MODE_SHIFT);
1180 reg &= ~(RX_PAUSE_EN | TX_PAUSE_EN);
1181
1182 reg |= port_mode | RGMII_MODE_EN;
1183 if (id_mode_dis)
1184 reg |= ID_MODE_DIS;
1185
1186 if (phydev->pause) {
1187 if (phydev->asym_pause)
1188 reg |= TX_PAUSE_EN;
1189 reg |= RX_PAUSE_EN;
1190 }
1191
1192 reg_writel(priv, reg, REG_RGMII_CNTRL_P(port));
1193
1194 pr_info("Port %d configured for %s\n", port, str);
1195
1196force_link:
1197 /* Force link settings detected from the PHY */
1198 reg = SW_OVERRIDE;
1199 switch (phydev->speed) {
1200 case SPEED_1000:
1201 reg |= SPDSTS_1000 << SPEED_SHIFT;
1202 break;
1203 case SPEED_100:
1204 reg |= SPDSTS_100 << SPEED_SHIFT;
1205 break;
1206 }
1207
1208 if (phydev->link)
1209 reg |= LINK_STS;
1210 if (phydev->duplex == DUPLEX_FULL)
1211 reg |= DUPLX_MODE;
1212
1213 core_writel(priv, reg, CORE_STS_OVERRIDE_GMIIP_PORT(port));
1214}
1215
1216static void bcm_sf2_sw_fixed_link_update(struct dsa_switch *ds, int port,
1217 struct fixed_phy_status *status)
1218{
1219 struct bcm_sf2_priv *priv = ds_to_priv(ds);
d2eac98f 1220 u32 duplex, pause;
246d7f77
FF		 1221 u32 reg;
1222
246d7f77
FF		 1223 duplex = core_readl(priv, CORE_DUPSTS);
1224 pause = core_readl(priv, CORE_PAUSESTS);
246d7f77
FF		 1225
1226 status->link = 0;
1227
8b7c94e3 1228 /* MoCA port is special as we do not get link status from CORE_LNKSTS,
246d7f77
FF		 1229 * which means that we need to force the link at the port override
1230 * level to get the data to flow. We do use what the interrupt handler
1231 * did determine before.
7855f675
FF		 1232 *
1233 * For the other ports, we just force the link status, since this is
1234 * a fixed PHY device.
246d7f77 1235 */
8b7c94e3 1236 if (port == priv->moca_port) {
246d7f77 1237 status->link = priv->port_sts[port].link;
4ab7f913
FF		 1238 /* For MoCA interfaces, also force a link down notification
1239 * since some version of the user-space daemon (mocad) use
1240 * cmd->autoneg to force the link, which messes up the PHY
1241 * state machine and make it go in PHY_FORCING state instead.
1242 */
1243 if (!status->link)
1244 netif_carrier_off(ds->ports[port]);
246d7f77
FF		 1245 status->duplex = 1;
1246 } else {
7855f675 1247 status->link = 1;
246d7f77
FF		 1248 status->duplex = !!(duplex & (1 << port));
1249 }
1250
7855f675
FF		 1251 reg = core_readl(priv, CORE_STS_OVERRIDE_GMIIP_PORT(port));
1252 reg |= SW_OVERRIDE;
1253 if (status->link)
1254 reg |= LINK_STS;
1255 else
1256 reg &= ~LINK_STS;
1257 core_writel(priv, reg, CORE_STS_OVERRIDE_GMIIP_PORT(port));
1258
246d7f77
FF		 1259 if ((pause & (1 << port)) &&
1260 (pause & (1 << (port + PAUSESTS_TX_PAUSE_SHIFT)))) {
1261 status->asym_pause = 1;
1262 status->pause = 1;
1263 }
1264
1265 if (pause & (1 << port))
1266 status->pause = 1;
1267}
1268
8cfa9498
FF		 1269static int bcm_sf2_sw_suspend(struct dsa_switch *ds)
1270{
1271 struct bcm_sf2_priv *priv = ds_to_priv(ds);
1272 unsigned int port;
1273
691c9a8f 1274 bcm_sf2_intr_disable(priv);
8cfa9498
FF		 1275
1276 /* Disable all ports physically present including the IMP
1277 * port, the other ones have already been disabled during
1278 * bcm_sf2_sw_setup
1279 */
1280 for (port = 0; port < DSA_MAX_PORTS; port++) {
1281 if ((1 << port) & ds->phys_port_mask ||
1282 dsa_is_cpu_port(ds, port))
b6d045db 1283 bcm_sf2_port_disable(ds, port, NULL);
8cfa9498
FF		 1284 }
1285
1286 return 0;
1287}
1288
8cfa9498
FF		 1289static int bcm_sf2_sw_resume(struct dsa_switch *ds)
1290{
1291 struct bcm_sf2_priv *priv = ds_to_priv(ds);
1292 unsigned int port;
8cfa9498
FF		 1293 int ret;
1294
1295 ret = bcm_sf2_sw_rst(priv);
1296 if (ret) {
1297 pr_err("%s: failed to software reset switch\n", __func__);
1298 return ret;
1299 }
1300
b083668c
FF		 1301 if (priv->hw_params.num_gphy == 1)
1302 bcm_sf2_gphy_enable_set(ds, true);
8cfa9498
FF		 1303
1304 for (port = 0; port < DSA_MAX_PORTS; port++) {
1305 if ((1 << port) & ds->phys_port_mask)
b6d045db 1306 bcm_sf2_port_setup(ds, port, NULL);
8cfa9498
FF		 1307 else if (dsa_is_cpu_port(ds, port))
1308 bcm_sf2_imp_setup(ds, port);
1309 }
1310
1311 return 0;
1312}
1313
96e65d7f
FF		 1314static void bcm_sf2_sw_get_wol(struct dsa_switch *ds, int port,
1315 struct ethtool_wolinfo *wol)
1316{
1317 struct net_device *p = ds->dst[ds->index].master_netdev;
1318 struct bcm_sf2_priv *priv = ds_to_priv(ds);
1319 struct ethtool_wolinfo pwol;
1320
1321 /* Get the parent device WoL settings */
1322 p->ethtool_ops->get_wol(p, &pwol);
1323
1324 /* Advertise the parent device supported settings */
1325 wol->supported = pwol.supported;
1326 memset(&wol->sopass, 0, sizeof(wol->sopass));
1327
1328 if (pwol.wolopts & WAKE_MAGICSECURE)
1329 memcpy(&wol->sopass, pwol.sopass, sizeof(wol->sopass));
1330
1331 if (priv->wol_ports_mask & (1 << port))
1332 wol->wolopts = pwol.wolopts;
1333 else
1334 wol->wolopts = 0;
1335}
1336
1337static int bcm_sf2_sw_set_wol(struct dsa_switch *ds, int port,
1338 struct ethtool_wolinfo *wol)
1339{
1340 struct net_device *p = ds->dst[ds->index].master_netdev;
1341 struct bcm_sf2_priv *priv = ds_to_priv(ds);
1342 s8 cpu_port = ds->dst[ds->index].cpu_port;
1343 struct ethtool_wolinfo pwol;
1344
1345 p->ethtool_ops->get_wol(p, &pwol);
1346 if (wol->wolopts & ~pwol.supported)
1347 return -EINVAL;
1348
1349 if (wol->wolopts)
1350 priv->wol_ports_mask |= (1 << port);
1351 else
1352 priv->wol_ports_mask &= ~(1 << port);
1353
1354 /* If we have at least one port enabled, make sure the CPU port
1355 * is also enabled. If the CPU port is the last one enabled, we disable
1356 * it since this configuration does not make sense.
1357 */
1358 if (priv->wol_ports_mask && priv->wol_ports_mask != (1 << cpu_port))
1359 priv->wol_ports_mask |= (1 << cpu_port);
1360 else
1361 priv->wol_ports_mask &= ~(1 << cpu_port);
1362
1363 return p->ethtool_ops->set_wol(p, wol);
1364}
1365
246d7f77 1366static struct dsa_switch_driver bcm_sf2_switch_driver = {
ac7a04c3 1367 .tag_protocol = DSA_TAG_PROTO_BRCM,
246d7f77
FF		 1368 .priv_size = sizeof(struct bcm_sf2_priv),
1369 .probe = bcm_sf2_sw_probe,
1370 .setup = bcm_sf2_sw_setup,
1371 .set_addr = bcm_sf2_sw_set_addr,
aa9aef77 1372 .get_phy_flags = bcm_sf2_sw_get_phy_flags,
246d7f77
FF		 1373 .phy_read = bcm_sf2_sw_phy_read,
1374 .phy_write = bcm_sf2_sw_phy_write,
1375 .get_strings = bcm_sf2_sw_get_strings,
1376 .get_ethtool_stats = bcm_sf2_sw_get_ethtool_stats,
1377 .get_sset_count = bcm_sf2_sw_get_sset_count,
1378 .adjust_link = bcm_sf2_sw_adjust_link,
1379 .fixed_link_update = bcm_sf2_sw_fixed_link_update,
8cfa9498
FF		 1380 .suspend = bcm_sf2_sw_suspend,
1381 .resume = bcm_sf2_sw_resume,
96e65d7f
FF		 1382 .get_wol = bcm_sf2_sw_get_wol,
1383 .set_wol = bcm_sf2_sw_set_wol,
b6d045db
FF		 1384 .port_enable = bcm_sf2_port_setup,
1385 .port_disable = bcm_sf2_port_disable,
450b05c1
FF		 1386 .get_eee = bcm_sf2_sw_get_eee,
1387 .set_eee = bcm_sf2_sw_set_eee,
71327a4e
VD		 1388 .port_bridge_join = bcm_sf2_sw_br_join,
1389 .port_bridge_leave = bcm_sf2_sw_br_leave,
12f460f2 1390 .port_stp_update = bcm_sf2_sw_br_set_stp_state,
680060d3
FF		 1391 .port_fdb_prepare = bcm_sf2_sw_fdb_prepare,
1392 .port_fdb_add = bcm_sf2_sw_fdb_add,
1393 .port_fdb_del = bcm_sf2_sw_fdb_del,
1394 .port_fdb_dump = bcm_sf2_sw_fdb_dump,
246d7f77
FF		 1395};
1396
1397static int __init bcm_sf2_init(void)
1398{
1399 register_switch_driver(&bcm_sf2_switch_driver);
1400
1401 return 0;
1402}
1403module_init(bcm_sf2_init);
1404
1405static void __exit bcm_sf2_exit(void)
1406{
1407 unregister_switch_driver(&bcm_sf2_switch_driver);
1408}
1409module_exit(bcm_sf2_exit);
1410
1411MODULE_AUTHOR("Broadcom Corporation");
1412MODULE_DESCRIPTION("Driver for Broadcom Starfighter 2 ethernet switch chip");
1413MODULE_LICENSE("GPL");
1414MODULE_ALIAS("platform:brcm-sf2");
Linux kernel - Deliverables
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