projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
net: dsa: bcm_sf2: disable RGMII interface(s) when link is down
[deliverable/linux.git] / drivers / net / dsa / bcm_sf2.c
CommitLineData
246d7f77
FF		 1/*
2 * Broadcom Starfighter 2 DSA switch driver
3 *
4 * Copyright (C) 2014, Broadcom Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
12#include <linux/list.h>
13#include <linux/module.h>
14#include <linux/netdevice.h>
15#include <linux/interrupt.h>
16#include <linux/platform_device.h>
17#include <linux/of.h>
18#include <linux/phy.h>
19#include <linux/phy_fixed.h>
20#include <linux/mii.h>
21#include <linux/of.h>
22#include <linux/of_irq.h>
23#include <linux/of_address.h>
24#include <net/dsa.h>
96e65d7f 25#include <linux/ethtool.h>
246d7f77
FF		 26
27#include "bcm_sf2.h"
28#include "bcm_sf2_regs.h"
29
30/* String, offset, and register size in bytes if different from 4 bytes */
31static const struct bcm_sf2_hw_stats bcm_sf2_mib[] = {
32 { "TxOctets", 0x000, 8 },
33 { "TxDropPkts", 0x020 },
34 { "TxQPKTQ0", 0x030 },
35 { "TxBroadcastPkts", 0x040 },
36 { "TxMulticastPkts", 0x050 },
37 { "TxUnicastPKts", 0x060 },
38 { "TxCollisions", 0x070 },
39 { "TxSingleCollision", 0x080 },
40 { "TxMultipleCollision", 0x090 },
41 { "TxDeferredCollision", 0x0a0 },
42 { "TxLateCollision", 0x0b0 },
43 { "TxExcessiveCollision", 0x0c0 },
44 { "TxFrameInDisc", 0x0d0 },
45 { "TxPausePkts", 0x0e0 },
46 { "TxQPKTQ1", 0x0f0 },
47 { "TxQPKTQ2", 0x100 },
48 { "TxQPKTQ3", 0x110 },
49 { "TxQPKTQ4", 0x120 },
50 { "TxQPKTQ5", 0x130 },
51 { "RxOctets", 0x140, 8 },
52 { "RxUndersizePkts", 0x160 },
53 { "RxPausePkts", 0x170 },
54 { "RxPkts64Octets", 0x180 },
55 { "RxPkts65to127Octets", 0x190 },
56 { "RxPkts128to255Octets", 0x1a0 },
57 { "RxPkts256to511Octets", 0x1b0 },
58 { "RxPkts512to1023Octets", 0x1c0 },
59 { "RxPkts1024toMaxPktsOctets", 0x1d0 },
60 { "RxOversizePkts", 0x1e0 },
61 { "RxJabbers", 0x1f0 },
62 { "RxAlignmentErrors", 0x200 },
63 { "RxFCSErrors", 0x210 },
64 { "RxGoodOctets", 0x220, 8 },
65 { "RxDropPkts", 0x240 },
66 { "RxUnicastPkts", 0x250 },
67 { "RxMulticastPkts", 0x260 },
68 { "RxBroadcastPkts", 0x270 },
69 { "RxSAChanges", 0x280 },
70 { "RxFragments", 0x290 },
71 { "RxJumboPkt", 0x2a0 },
72 { "RxSymblErr", 0x2b0 },
73 { "InRangeErrCount", 0x2c0 },
74 { "OutRangeErrCount", 0x2d0 },
75 { "EEELpiEvent", 0x2e0 },
76 { "EEELpiDuration", 0x2f0 },
77 { "RxDiscard", 0x300, 8 },
78 { "TxQPKTQ6", 0x320 },
79 { "TxQPKTQ7", 0x330 },
80 { "TxPkts64Octets", 0x340 },
81 { "TxPkts65to127Octets", 0x350 },
82 { "TxPkts128to255Octets", 0x360 },
83 { "TxPkts256to511Ocets", 0x370 },
84 { "TxPkts512to1023Ocets", 0x380 },
85 { "TxPkts1024toMaxPktOcets", 0x390 },
86};
87
88#define BCM_SF2_STATS_SIZE ARRAY_SIZE(bcm_sf2_mib)
89
90static void bcm_sf2_sw_get_strings(struct dsa_switch *ds,
91 int port, uint8_t *data)
92{
93 unsigned int i;
94
95 for (i = 0; i < BCM_SF2_STATS_SIZE; i++)
96 memcpy(data + i * ETH_GSTRING_LEN,
97 bcm_sf2_mib[i].string, ETH_GSTRING_LEN);
98}
99
100static void bcm_sf2_sw_get_ethtool_stats(struct dsa_switch *ds,
101 int port, uint64_t *data)
102{
103 struct bcm_sf2_priv *priv = ds_to_priv(ds);
104 const struct bcm_sf2_hw_stats *s;
105 unsigned int i;
106 u64 val = 0;
107 u32 offset;
108
109 mutex_lock(&priv->stats_mutex);
110
111 /* Now fetch the per-port counters */
112 for (i = 0; i < BCM_SF2_STATS_SIZE; i++) {
113 s = &bcm_sf2_mib[i];
114
115 /* Do a latched 64-bit read if needed */
116 offset = s->reg + CORE_P_MIB_OFFSET(port);
117 if (s->sizeof_stat == 8)
118 val = core_readq(priv, offset);
119 else
120 val = core_readl(priv, offset);
121
122 data[i] = (u64)val;
123 }
124
125 mutex_unlock(&priv->stats_mutex);
126}
127
128static int bcm_sf2_sw_get_sset_count(struct dsa_switch *ds)
129{
130 return BCM_SF2_STATS_SIZE;
131}
132
b4d2394d 133static char *bcm_sf2_sw_probe(struct device *host_dev, int sw_addr)
246d7f77
FF		 134{
135 return "Broadcom Starfighter 2";
136}
137
138static void bcm_sf2_imp_setup(struct dsa_switch *ds, int port)
139{
140 struct bcm_sf2_priv *priv = ds_to_priv(ds);
141 unsigned int i;
142 u32 reg, val;
143
144 /* Enable the port memories */
145 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
146 reg &= ~P_TXQ_PSM_VDD(port);
147 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
148
149 /* Enable Broadcast, Multicast, Unicast forwarding to IMP port */
150 reg = core_readl(priv, CORE_IMP_CTL);
151 reg |= (RX_BCST_EN | RX_MCST_EN | RX_UCST_EN);
152 reg &= ~(RX_DIS | TX_DIS);
153 core_writel(priv, reg, CORE_IMP_CTL);
154
155 /* Enable forwarding */
156 core_writel(priv, SW_FWDG_EN, CORE_SWMODE);
157
158 /* Enable IMP port in dumb mode */
159 reg = core_readl(priv, CORE_SWITCH_CTRL);
160 reg |= MII_DUMB_FWDG_EN;
161 core_writel(priv, reg, CORE_SWITCH_CTRL);
162
163 /* Resolve which bit controls the Broadcom tag */
164 switch (port) {
165 case 8:
166 val = BRCM_HDR_EN_P8;
167 break;
168 case 7:
169 val = BRCM_HDR_EN_P7;
170 break;
171 case 5:
172 val = BRCM_HDR_EN_P5;
173 break;
174 default:
175 val = 0;
176 break;
177 }
178
179 /* Enable Broadcom tags for IMP port */
180 reg = core_readl(priv, CORE_BRCM_HDR_CTRL);
181 reg |= val;
182 core_writel(priv, reg, CORE_BRCM_HDR_CTRL);
183
184 /* Enable reception Broadcom tag for CPU TX (switch RX) to
185 * allow us to tag outgoing frames
186 */
187 reg = core_readl(priv, CORE_BRCM_HDR_RX_DIS);
188 reg &= ~(1 << port);
189 core_writel(priv, reg, CORE_BRCM_HDR_RX_DIS);
190
191 /* Enable transmission of Broadcom tags from the switch (CPU RX) to
192 * allow delivering frames to the per-port net_devices
193 */
194 reg = core_readl(priv, CORE_BRCM_HDR_TX_DIS);
195 reg &= ~(1 << port);
196 core_writel(priv, reg, CORE_BRCM_HDR_TX_DIS);
197
198 /* Force link status for IMP port */
199 reg = core_readl(priv, CORE_STS_OVERRIDE_IMP);
200 reg |= (MII_SW_OR | LINK_STS);
201 core_writel(priv, reg, CORE_STS_OVERRIDE_IMP);
202
203 /* Enable the IMP Port to be in the same VLAN as the other ports
204 * on a per-port basis such that we only have Port i and IMP in
205 * the same VLAN.
206 */
207 for (i = 0; i < priv->hw_params.num_ports; i++) {
208 if (!((1 << i) & ds->phys_port_mask))
209 continue;
210
211 reg = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(i));
212 reg |= (1 << port);
213 core_writel(priv, reg, CORE_PORT_VLAN_CTL_PORT(i));
214 }
215}
216
217static void bcm_sf2_port_setup(struct dsa_switch *ds, int port)
218{
219 struct bcm_sf2_priv *priv = ds_to_priv(ds);
220 u32 reg;
221
222 /* Clear the memory power down */
223 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
224 reg &= ~P_TXQ_PSM_VDD(port);
225 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
226
227 /* Clear the Rx and Tx disable bits and set to no spanning tree */
228 core_writel(priv, 0, CORE_G_PCTL_PORT(port));
229
230 /* Enable port 7 interrupts to get notified */
231 if (port == 7)
232 intrl2_1_mask_clear(priv, P_IRQ_MASK(P7_IRQ_OFF));
233
234 /* Set this port, and only this one to be in the default VLAN */
235 reg = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(port));
236 reg &= ~PORT_VLAN_CTRL_MASK;
237 reg |= (1 << port);
238 core_writel(priv, reg, CORE_PORT_VLAN_CTL_PORT(port));
239}
240
241static void bcm_sf2_port_disable(struct dsa_switch *ds, int port)
242{
243 struct bcm_sf2_priv *priv = ds_to_priv(ds);
244 u32 off, reg;
245
96e65d7f
FF		 246 if (priv->wol_ports_mask & (1 << port))
247 return;
248
246d7f77
FF		 249 if (dsa_is_cpu_port(ds, port))
250 off = CORE_IMP_CTL;
251 else
252 off = CORE_G_PCTL_PORT(port);
253
254 reg = core_readl(priv, off);
255 reg |= RX_DIS | TX_DIS;
256 core_writel(priv, reg, off);
257
258 /* Power down the port memory */
259 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
260 reg |= P_TXQ_PSM_VDD(port);
261 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
262}
263
264static irqreturn_t bcm_sf2_switch_0_isr(int irq, void *dev_id)
265{
266 struct bcm_sf2_priv *priv = dev_id;
267
268 priv->irq0_stat = intrl2_0_readl(priv, INTRL2_CPU_STATUS) &
269 ~priv->irq0_mask;
270 intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR);
271
272 return IRQ_HANDLED;
273}
274
275static irqreturn_t bcm_sf2_switch_1_isr(int irq, void *dev_id)
276{
277 struct bcm_sf2_priv *priv = dev_id;
278
279 priv->irq1_stat = intrl2_1_readl(priv, INTRL2_CPU_STATUS) &
280 ~priv->irq1_mask;
281 intrl2_1_writel(priv, priv->irq1_stat, INTRL2_CPU_CLEAR);
282
283 if (priv->irq1_stat & P_LINK_UP_IRQ(P7_IRQ_OFF))
284 priv->port_sts[7].link = 1;
285 if (priv->irq1_stat & P_LINK_DOWN_IRQ(P7_IRQ_OFF))
286 priv->port_sts[7].link = 0;
287
288 return IRQ_HANDLED;
289}
290
291static int bcm_sf2_sw_setup(struct dsa_switch *ds)
292{
293 const char *reg_names[BCM_SF2_REGS_NUM] = BCM_SF2_REGS_NAME;
294 struct bcm_sf2_priv *priv = ds_to_priv(ds);
295 struct device_node *dn;
296 void __iomem **base;
297 unsigned int port;
298 unsigned int i;
299 u32 reg, rev;
300 int ret;
301
302 spin_lock_init(&priv->indir_lock);
303 mutex_init(&priv->stats_mutex);
304
305 /* All the interesting properties are at the parent device_node
306 * level
307 */
308 dn = ds->pd->of_node->parent;
309
310 priv->irq0 = irq_of_parse_and_map(dn, 0);
311 priv->irq1 = irq_of_parse_and_map(dn, 1);
312
313 base = &priv->core;
314 for (i = 0; i < BCM_SF2_REGS_NUM; i++) {
315 *base = of_iomap(dn, i);
316 if (*base == NULL) {
317 pr_err("unable to find register: %s\n", reg_names[i]);
318 return -ENODEV;
319 }
320 base++;
321 }
322
323 /* Disable all interrupts and request them */
324 intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_MASK_SET);
325 intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
326 intrl2_0_writel(priv, 0, INTRL2_CPU_MASK_CLEAR);
327 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_MASK_SET);
328 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
329 intrl2_1_writel(priv, 0, INTRL2_CPU_MASK_CLEAR);
330
331 ret = request_irq(priv->irq0, bcm_sf2_switch_0_isr, 0,
332 "switch_0", priv);
333 if (ret < 0) {
334 pr_err("failed to request switch_0 IRQ\n");
335 goto out_unmap;
336 }
337
338 ret = request_irq(priv->irq1, bcm_sf2_switch_1_isr, 0,
339 "switch_1", priv);
340 if (ret < 0) {
341 pr_err("failed to request switch_1 IRQ\n");
342 goto out_free_irq0;
343 }
344
345 /* Reset the MIB counters */
346 reg = core_readl(priv, CORE_GMNCFGCFG);
347 reg |= RST_MIB_CNT;
348 core_writel(priv, reg, CORE_GMNCFGCFG);
349 reg &= ~RST_MIB_CNT;
350 core_writel(priv, reg, CORE_GMNCFGCFG);
351
352 /* Get the maximum number of ports for this switch */
353 priv->hw_params.num_ports = core_readl(priv, CORE_IMP0_PRT_ID) + 1;
354 if (priv->hw_params.num_ports > DSA_MAX_PORTS)
355 priv->hw_params.num_ports = DSA_MAX_PORTS;
356
357 /* Assume a single GPHY setup if we can't read that property */
358 if (of_property_read_u32(dn, "brcm,num-gphy",
359 &priv->hw_params.num_gphy))
360 priv->hw_params.num_gphy = 1;
361
362 /* Enable all valid ports and disable those unused */
363 for (port = 0; port < priv->hw_params.num_ports; port++) {
364 /* IMP port receives special treatment */
365 if ((1 << port) & ds->phys_port_mask)
366 bcm_sf2_port_setup(ds, port);
367 else if (dsa_is_cpu_port(ds, port))
368 bcm_sf2_imp_setup(ds, port);
369 else
370 bcm_sf2_port_disable(ds, port);
371 }
372
373 /* Include the pseudo-PHY address and the broadcast PHY address to
374 * divert reads towards our workaround
375 */
376 ds->phys_mii_mask |= ((1 << 30) | (1 << 0));
377
378 rev = reg_readl(priv, REG_SWITCH_REVISION);
379 priv->hw_params.top_rev = (rev >> SWITCH_TOP_REV_SHIFT) &
380 SWITCH_TOP_REV_MASK;
381 priv->hw_params.core_rev = (rev & SF2_REV_MASK);
382
aa9aef77
FF		 383 rev = reg_readl(priv, REG_PHY_REVISION);
384 priv->hw_params.gphy_rev = rev & PHY_REVISION_MASK;
385
246d7f77
FF		 386 pr_info("Starfighter 2 top: %x.%02x, core: %x.%02x base: 0x%p, IRQs: %d, %d\n",
387 priv->hw_params.top_rev >> 8, priv->hw_params.top_rev & 0xff,
388 priv->hw_params.core_rev >> 8, priv->hw_params.core_rev & 0xff,
389 priv->core, priv->irq0, priv->irq1);
390
391 return 0;
392
393out_free_irq0:
394 free_irq(priv->irq0, priv);
395out_unmap:
396 base = &priv->core;
397 for (i = 0; i < BCM_SF2_REGS_NUM; i++) {
398 iounmap(*base);
399 base++;
400 }
401 return ret;
402}
403
404static int bcm_sf2_sw_set_addr(struct dsa_switch *ds, u8 *addr)
405{
406 return 0;
407}
408
aa9aef77
FF		 409static u32 bcm_sf2_sw_get_phy_flags(struct dsa_switch *ds, int port)
410{
411 struct bcm_sf2_priv *priv = ds_to_priv(ds);
412
413 /* The BCM7xxx PHY driver expects to find the integrated PHY revision
414 * in bits 15:8 and the patch level in bits 7:0 which is exactly what
415 * the REG_PHY_REVISION register layout is.
416 */
417
418 return priv->hw_params.gphy_rev;
419}
420
246d7f77
FF		 421static int bcm_sf2_sw_indir_rw(struct dsa_switch *ds, int op, int addr,
422 int regnum, u16 val)
423{
424 struct bcm_sf2_priv *priv = ds_to_priv(ds);
425 int ret = 0;
426 u32 reg;
427
428 reg = reg_readl(priv, REG_SWITCH_CNTRL);
429 reg |= MDIO_MASTER_SEL;
430 reg_writel(priv, reg, REG_SWITCH_CNTRL);
431
432 /* Page << 8 | offset */
433 reg = 0x70;
434 reg <<= 2;
435 core_writel(priv, addr, reg);
436
437 /* Page << 8 | offset */
438 reg = 0x80 << 8 | regnum << 1;
439 reg <<= 2;
440
441 if (op)
442 ret = core_readl(priv, reg);
443 else
444 core_writel(priv, val, reg);
445
446 reg = reg_readl(priv, REG_SWITCH_CNTRL);
447 reg &= ~MDIO_MASTER_SEL;
448 reg_writel(priv, reg, REG_SWITCH_CNTRL);
449
450 return ret & 0xffff;
451}
452
453static int bcm_sf2_sw_phy_read(struct dsa_switch *ds, int addr, int regnum)
454{
455 /* Intercept reads from the MDIO broadcast address or Broadcom
456 * pseudo-PHY address
457 */
458 switch (addr) {
459 case 0:
460 case 30:
461 return bcm_sf2_sw_indir_rw(ds, 1, addr, regnum, 0);
462 default:
463 return 0xffff;
464 }
465}
466
467static int bcm_sf2_sw_phy_write(struct dsa_switch *ds, int addr, int regnum,
468 u16 val)
469{
470 /* Intercept writes to the MDIO broadcast address or Broadcom
471 * pseudo-PHY address
472 */
473 switch (addr) {
474 case 0:
475 case 30:
476 bcm_sf2_sw_indir_rw(ds, 0, addr, regnum, val);
477 break;
478 }
479
480 return 0;
481}
482
483static void bcm_sf2_sw_adjust_link(struct dsa_switch *ds, int port,
484 struct phy_device *phydev)
485{
486 struct bcm_sf2_priv *priv = ds_to_priv(ds);
487 u32 id_mode_dis = 0, port_mode;
488 const char *str = NULL;
489 u32 reg;
490
491 switch (phydev->interface) {
492 case PHY_INTERFACE_MODE_RGMII:
493 str = "RGMII (no delay)";
494 id_mode_dis = 1;
495 case PHY_INTERFACE_MODE_RGMII_TXID:
496 if (!str)
497 str = "RGMII (TX delay)";
498 port_mode = EXT_GPHY;
499 break;
500 case PHY_INTERFACE_MODE_MII:
501 str = "MII";
502 port_mode = EXT_EPHY;
503 break;
504 case PHY_INTERFACE_MODE_REVMII:
505 str = "Reverse MII";
506 port_mode = EXT_REVMII;
507 break;
508 default:
7de1557c
FF		 509 /* All other PHYs: internal and MoCA */
510 goto force_link;
511 }
512
513 /* If the link is down, just disable the interface to conserve power */
514 if (!phydev->link) {
515 reg = reg_readl(priv, REG_RGMII_CNTRL_P(port));
516 reg &= ~RGMII_MODE_EN;
517 reg_writel(priv, reg, REG_RGMII_CNTRL_P(port));
246d7f77
FF		 518 goto force_link;
519 }
520
521 /* Clear id_mode_dis bit, and the existing port mode, but
522 * make sure we enable the RGMII block for data to pass
523 */
524 reg = reg_readl(priv, REG_RGMII_CNTRL_P(port));
525 reg &= ~ID_MODE_DIS;
526 reg &= ~(PORT_MODE_MASK << PORT_MODE_SHIFT);
527 reg &= ~(RX_PAUSE_EN | TX_PAUSE_EN);
528
529 reg |= port_mode | RGMII_MODE_EN;
530 if (id_mode_dis)
531 reg |= ID_MODE_DIS;
532
533 if (phydev->pause) {
534 if (phydev->asym_pause)
535 reg |= TX_PAUSE_EN;
536 reg |= RX_PAUSE_EN;
537 }
538
539 reg_writel(priv, reg, REG_RGMII_CNTRL_P(port));
540
541 pr_info("Port %d configured for %s\n", port, str);
542
543force_link:
544 /* Force link settings detected from the PHY */
545 reg = SW_OVERRIDE;
546 switch (phydev->speed) {
547 case SPEED_1000:
548 reg |= SPDSTS_1000 << SPEED_SHIFT;
549 break;
550 case SPEED_100:
551 reg |= SPDSTS_100 << SPEED_SHIFT;
552 break;
553 }
554
555 if (phydev->link)
556 reg |= LINK_STS;
557 if (phydev->duplex == DUPLEX_FULL)
558 reg |= DUPLX_MODE;
559
560 core_writel(priv, reg, CORE_STS_OVERRIDE_GMIIP_PORT(port));
561}
562
563static void bcm_sf2_sw_fixed_link_update(struct dsa_switch *ds, int port,
564 struct fixed_phy_status *status)
565{
566 struct bcm_sf2_priv *priv = ds_to_priv(ds);
567 u32 link, duplex, pause, speed;
568 u32 reg;
569
570 link = core_readl(priv, CORE_LNKSTS);
571 duplex = core_readl(priv, CORE_DUPSTS);
572 pause = core_readl(priv, CORE_PAUSESTS);
573 speed = core_readl(priv, CORE_SPDSTS);
574
575 speed >>= (port * SPDSTS_SHIFT);
576 speed &= SPDSTS_MASK;
577
578 status->link = 0;
579
580 /* Port 7 is special as we do not get link status from CORE_LNKSTS,
581 * which means that we need to force the link at the port override
582 * level to get the data to flow. We do use what the interrupt handler
583 * did determine before.
584 */
585 if (port == 7) {
586 status->link = priv->port_sts[port].link;
587 reg = core_readl(priv, CORE_STS_OVERRIDE_GMIIP_PORT(7));
588 reg |= SW_OVERRIDE;
589 if (status->link)
590 reg |= LINK_STS;
591 else
592 reg &= ~LINK_STS;
593 core_writel(priv, reg, CORE_STS_OVERRIDE_GMIIP_PORT(7));
594 status->duplex = 1;
595 } else {
596 status->link = !!(link & (1 << port));
597 status->duplex = !!(duplex & (1 << port));
598 }
599
600 switch (speed) {
601 case SPDSTS_10:
602 status->speed = SPEED_10;
603 break;
604 case SPDSTS_100:
605 status->speed = SPEED_100;
606 break;
607 case SPDSTS_1000:
608 status->speed = SPEED_1000;
609 break;
610 }
611
612 if ((pause & (1 << port)) &&
613 (pause & (1 << (port + PAUSESTS_TX_PAUSE_SHIFT)))) {
614 status->asym_pause = 1;
615 status->pause = 1;
616 }
617
618 if (pause & (1 << port))
619 status->pause = 1;
620}
621
8cfa9498
FF		 622static int bcm_sf2_sw_suspend(struct dsa_switch *ds)
623{
624 struct bcm_sf2_priv *priv = ds_to_priv(ds);
625 unsigned int port;
626
627 intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_MASK_SET);
628 intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
629 intrl2_0_writel(priv, 0, INTRL2_CPU_MASK_CLEAR);
630 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_MASK_SET);
631 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
632 intrl2_1_writel(priv, 0, INTRL2_CPU_MASK_CLEAR);
633
634 /* Disable all ports physically present including the IMP
635 * port, the other ones have already been disabled during
636 * bcm_sf2_sw_setup
637 */
638 for (port = 0; port < DSA_MAX_PORTS; port++) {
639 if ((1 << port) & ds->phys_port_mask ||
640 dsa_is_cpu_port(ds, port))
641 bcm_sf2_port_disable(ds, port);
642 }
643
644 return 0;
645}
646
647static int bcm_sf2_sw_rst(struct bcm_sf2_priv *priv)
648{
649 unsigned int timeout = 1000;
650 u32 reg;
651
652 reg = core_readl(priv, CORE_WATCHDOG_CTRL);
653 reg |= SOFTWARE_RESET | EN_CHIP_RST | EN_SW_RESET;
654 core_writel(priv, reg, CORE_WATCHDOG_CTRL);
655
656 do {
657 reg = core_readl(priv, CORE_WATCHDOG_CTRL);
658 if (!(reg & SOFTWARE_RESET))
659 break;
660
661 usleep_range(1000, 2000);
662 } while (timeout-- > 0);
663
664 if (timeout == 0)
665 return -ETIMEDOUT;
666
667 return 0;
668}
669
670static int bcm_sf2_sw_resume(struct dsa_switch *ds)
671{
672 struct bcm_sf2_priv *priv = ds_to_priv(ds);
673 unsigned int port;
674 u32 reg;
675 int ret;
676
677 ret = bcm_sf2_sw_rst(priv);
678 if (ret) {
679 pr_err("%s: failed to software reset switch\n", __func__);
680 return ret;
681 }
682
683 /* Reinitialize the single GPHY */
684 if (priv->hw_params.num_gphy == 1) {
685 reg = reg_readl(priv, REG_SPHY_CNTRL);
686 reg |= PHY_RESET;
687 reg &= ~(EXT_PWR_DOWN | IDDQ_BIAS);
688 reg_writel(priv, reg, REG_SPHY_CNTRL);
689 udelay(21);
690 reg = reg_readl(priv, REG_SPHY_CNTRL);
691 reg &= ~PHY_RESET;
692 reg_writel(priv, reg, REG_SPHY_CNTRL);
693 }
694
695 for (port = 0; port < DSA_MAX_PORTS; port++) {
696 if ((1 << port) & ds->phys_port_mask)
697 bcm_sf2_port_setup(ds, port);
698 else if (dsa_is_cpu_port(ds, port))
699 bcm_sf2_imp_setup(ds, port);
700 }
701
702 return 0;
703}
704
96e65d7f
FF		 705static void bcm_sf2_sw_get_wol(struct dsa_switch *ds, int port,
706 struct ethtool_wolinfo *wol)
707{
708 struct net_device *p = ds->dst[ds->index].master_netdev;
709 struct bcm_sf2_priv *priv = ds_to_priv(ds);
710 struct ethtool_wolinfo pwol;
711
712 /* Get the parent device WoL settings */
713 p->ethtool_ops->get_wol(p, &pwol);
714
715 /* Advertise the parent device supported settings */
716 wol->supported = pwol.supported;
717 memset(&wol->sopass, 0, sizeof(wol->sopass));
718
719 if (pwol.wolopts & WAKE_MAGICSECURE)
720 memcpy(&wol->sopass, pwol.sopass, sizeof(wol->sopass));
721
722 if (priv->wol_ports_mask & (1 << port))
723 wol->wolopts = pwol.wolopts;
724 else
725 wol->wolopts = 0;
726}
727
728static int bcm_sf2_sw_set_wol(struct dsa_switch *ds, int port,
729 struct ethtool_wolinfo *wol)
730{
731 struct net_device *p = ds->dst[ds->index].master_netdev;
732 struct bcm_sf2_priv *priv = ds_to_priv(ds);
733 s8 cpu_port = ds->dst[ds->index].cpu_port;
734 struct ethtool_wolinfo pwol;
735
736 p->ethtool_ops->get_wol(p, &pwol);
737 if (wol->wolopts & ~pwol.supported)
738 return -EINVAL;
739
740 if (wol->wolopts)
741 priv->wol_ports_mask |= (1 << port);
742 else
743 priv->wol_ports_mask &= ~(1 << port);
744
745 /* If we have at least one port enabled, make sure the CPU port
746 * is also enabled. If the CPU port is the last one enabled, we disable
747 * it since this configuration does not make sense.
748 */
749 if (priv->wol_ports_mask && priv->wol_ports_mask != (1 << cpu_port))
750 priv->wol_ports_mask |= (1 << cpu_port);
751 else
752 priv->wol_ports_mask &= ~(1 << cpu_port);
753
754 return p->ethtool_ops->set_wol(p, wol);
755}
756
246d7f77 757static struct dsa_switch_driver bcm_sf2_switch_driver = {
ac7a04c3 758 .tag_protocol = DSA_TAG_PROTO_BRCM,
246d7f77
FF		 759 .priv_size = sizeof(struct bcm_sf2_priv),
760 .probe = bcm_sf2_sw_probe,
761 .setup = bcm_sf2_sw_setup,
762 .set_addr = bcm_sf2_sw_set_addr,
aa9aef77 763 .get_phy_flags = bcm_sf2_sw_get_phy_flags,
246d7f77
FF		 764 .phy_read = bcm_sf2_sw_phy_read,
765 .phy_write = bcm_sf2_sw_phy_write,
766 .get_strings = bcm_sf2_sw_get_strings,
767 .get_ethtool_stats = bcm_sf2_sw_get_ethtool_stats,
768 .get_sset_count = bcm_sf2_sw_get_sset_count,
769 .adjust_link = bcm_sf2_sw_adjust_link,
770 .fixed_link_update = bcm_sf2_sw_fixed_link_update,
8cfa9498
FF		 771 .suspend = bcm_sf2_sw_suspend,
772 .resume = bcm_sf2_sw_resume,
96e65d7f
FF		 773 .get_wol = bcm_sf2_sw_get_wol,
774 .set_wol = bcm_sf2_sw_set_wol,
246d7f77
FF		 775};
776
777static int __init bcm_sf2_init(void)
778{
779 register_switch_driver(&bcm_sf2_switch_driver);
780
781 return 0;
782}
783module_init(bcm_sf2_init);
784
785static void __exit bcm_sf2_exit(void)
786{
787 unregister_switch_driver(&bcm_sf2_switch_driver);
788}
789module_exit(bcm_sf2_exit);
790
791MODULE_AUTHOR("Broadcom Corporation");
792MODULE_DESCRIPTION("Driver for Broadcom Starfighter 2 ethernet switch chip");
793MODULE_LICENSE("GPL");
794MODULE_ALIAS("platform:brcm-sf2");
Linux kernel - Deliverables
This page took 0.062913 seconds and 5 git commands to generate.