[deliverable/linux.git] / drivers / net / dsa / mv88e6060.c

/*
 * net/dsa/mv88e6060.c - Driver for Marvell 88e6060 switch chips
 * Copyright (c) 2008-2009 Marvell Semiconductor
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#include <linux/delay.h>
#include <linux/jiffies.h>
#include <linux/list.h>
#include <linux/module.h>
#include <linux/netdevice.h>
#include <linux/phy.h>
#include <net/dsa.h>
#include "mv88e6060.h"

static int reg_read(struct dsa_switch *ds, int addr, int reg)
{
	struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);

	if (bus == NULL)
		return -EINVAL;

	return mdiobus_read_nested(bus, ds->pd->sw_addr + addr, reg);
}

#define REG_READ(addr, reg)					\
	({							\
		int __ret;					\
								\
		__ret = reg_read(ds, addr, reg);		\
		if (__ret < 0)					\
			return __ret;				\
		__ret;						\
	})


static int reg_write(struct dsa_switch *ds, int addr, int reg, u16 val)
{
	struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);

	if (bus == NULL)
		return -EINVAL;

	return mdiobus_write_nested(bus, ds->pd->sw_addr + addr, reg, val);
}

#define REG_WRITE(addr, reg, val)				\
	({							\
		int __ret;					\
								\
		__ret = reg_write(ds, addr, reg, val);		\
		if (__ret < 0)					\
			return __ret;				\
	})

static char *mv88e6060_probe(struct device *host_dev, int sw_addr)
{
	struct mii_bus *bus = dsa_host_dev_to_mii_bus(host_dev);
	int ret;

	if (bus == NULL)
		return NULL;

	ret = mdiobus_read(bus, sw_addr + REG_PORT(0), PORT_SWITCH_ID);
	if (ret >= 0) {
		if (ret == PORT_SWITCH_ID_6060)
			return "Marvell 88E6060 (A0)";
		if (ret == PORT_SWITCH_ID_6060_R1 ||
		    ret == PORT_SWITCH_ID_6060_R2)
			return "Marvell 88E6060 (B0)";
		if ((ret & PORT_SWITCH_ID_6060_MASK) == PORT_SWITCH_ID_6060)
			return "Marvell 88E6060";
	}

	return NULL;
}

static int mv88e6060_switch_reset(struct dsa_switch *ds)
{
	int i;
	int ret;
	unsigned long timeout;

	/* Set all ports to the disabled state. */
	for (i = 0; i < MV88E6060_PORTS; i++) {
		ret = REG_READ(REG_PORT(i), PORT_CONTROL);
		REG_WRITE(REG_PORT(i), PORT_CONTROL,
			  ret & ~PORT_CONTROL_STATE_MASK);
	}

	/* Wait for transmit queues to drain. */
	usleep_range(2000, 4000);

	/* Reset the switch. */
	REG_WRITE(REG_GLOBAL, GLOBAL_ATU_CONTROL,
		  GLOBAL_ATU_CONTROL_SWRESET |
		  GLOBAL_ATU_CONTROL_ATUSIZE_1024 |
		  GLOBAL_ATU_CONTROL_ATE_AGE_5MIN);

	/* Wait up to one second for reset to complete. */
	timeout = jiffies + 1 * HZ;
	while (time_before(jiffies, timeout)) {
		ret = REG_READ(REG_GLOBAL, GLOBAL_STATUS);
		if (ret & GLOBAL_STATUS_INIT_READY)
			break;

		usleep_range(1000, 2000);
	}
	if (time_after(jiffies, timeout))
		return -ETIMEDOUT;

	return 0;
}

static int mv88e6060_setup_global(struct dsa_switch *ds)
{
	/* Disable discarding of frames with excessive collisions,
	 * set the maximum frame size to 1536 bytes, and mask all
	 * interrupt sources.
	 */
	REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL, GLOBAL_CONTROL_MAX_FRAME_1536);

	/* Enable automatic address learning, set the address
	 * database size to 1024 entries, and set the default aging
	 * time to 5 minutes.
	 */
	REG_WRITE(REG_GLOBAL, GLOBAL_ATU_CONTROL,
		  GLOBAL_ATU_CONTROL_ATUSIZE_1024 |
		  GLOBAL_ATU_CONTROL_ATE_AGE_5MIN);

	return 0;
}

static int mv88e6060_setup_port(struct dsa_switch *ds, int p)
{
	int addr = REG_PORT(p);

	/* Do not force flow control, disable Ingress and Egress
	 * Header tagging, disable VLAN tunneling, and set the port
	 * state to Forwarding.  Additionally, if this is the CPU
	 * port, enable Ingress and Egress Trailer tagging mode.
	 */
	REG_WRITE(addr, PORT_CONTROL,
		  dsa_is_cpu_port(ds, p) ?
			PORT_CONTROL_TRAILER |
			PORT_CONTROL_INGRESS_MODE |
			PORT_CONTROL_STATE_FORWARDING :
			PORT_CONTROL_STATE_FORWARDING);

	/* Port based VLAN map: give each port its own address
	 * database, allow the CPU port to talk to each of the 'real'
	 * ports, and allow each of the 'real' ports to only talk to
	 * the CPU port.
	 */
	REG_WRITE(addr, PORT_VLAN_MAP,
		  ((p & 0xf) << PORT_VLAN_MAP_DBNUM_SHIFT) |
		   (dsa_is_cpu_port(ds, p) ?
			ds->phys_port_mask :
			BIT(ds->dst->cpu_port)));

	/* Port Association Vector: when learning source addresses
	 * of packets, add the address to the address database using
	 * a port bitmap that has only the bit for this port set and
	 * the other bits clear.
	 */
	REG_WRITE(addr, PORT_ASSOC_VECTOR, BIT(p));

	return 0;
}

static int mv88e6060_setup(struct dsa_switch *ds)
{
	int i;
	int ret;

	ret = mv88e6060_switch_reset(ds);
	if (ret < 0)
		return ret;

	/* @@@ initialise atu */

	ret = mv88e6060_setup_global(ds);
	if (ret < 0)
		return ret;

	for (i = 0; i < MV88E6060_PORTS; i++) {
		ret = mv88e6060_setup_port(ds, i);
		if (ret < 0)
			return ret;
	}

	return 0;
}

static int mv88e6060_set_addr(struct dsa_switch *ds, u8 *addr)
{
	/* Use the same MAC Address as FD Pause frames for all ports */
	REG_WRITE(REG_GLOBAL, GLOBAL_MAC_01, (addr[0] << 9) | addr[1]);
	REG_WRITE(REG_GLOBAL, GLOBAL_MAC_23, (addr[2] << 8) | addr[3]);
	REG_WRITE(REG_GLOBAL, GLOBAL_MAC_45, (addr[4] << 8) | addr[5]);

	return 0;
}

static int mv88e6060_port_to_phy_addr(int port)
{
	if (port >= 0 && port < MV88E6060_PORTS)
		return port;
	return -1;
}

static int mv88e6060_phy_read(struct dsa_switch *ds, int port, int regnum)
{
	int addr;

	addr = mv88e6060_port_to_phy_addr(port);
	if (addr == -1)
		return 0xffff;

	return reg_read(ds, addr, regnum);
}

static int
mv88e6060_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val)
{
	int addr;

	addr = mv88e6060_port_to_phy_addr(port);
	if (addr == -1)
		return 0xffff;

	return reg_write(ds, addr, regnum, val);
}

static struct dsa_switch_driver mv88e6060_switch_driver = {
	.tag_protocol	= DSA_TAG_PROTO_TRAILER,
	.probe		= mv88e6060_probe,
	.setup		= mv88e6060_setup,
	.set_addr	= mv88e6060_set_addr,
	.phy_read	= mv88e6060_phy_read,
	.phy_write	= mv88e6060_phy_write,
};

static int __init mv88e6060_init(void)
{
	register_switch_driver(&mv88e6060_switch_driver);
	return 0;
}
module_init(mv88e6060_init);

static void __exit mv88e6060_cleanup(void)
{
	unregister_switch_driver(&mv88e6060_switch_driver);
}
module_exit(mv88e6060_cleanup);

MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
MODULE_DESCRIPTION("Driver for Marvell 88E6060 ethernet switch chip");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:mv88e6060");
Commit	Line	Data
2e16a77e LB	1	/*
2e16a77e LB	2	* net/dsa/mv88e6060.c - Driver for Marvell 88e6060 switch chips
e84665c9	3	* Copyright (c) 2008-2009 Marvell Semiconductor
2e16a77e LB	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License as published by
	7	* the Free Software Foundation; either version 2 of the License, or
	8	* (at your option) any later version.
	9	*/
	10
19b2f97e BG	11	#include <linux/delay.h>
19b2f97e BG	12	#include <linux/jiffies.h>
2e16a77e	13	#include <linux/list.h>
2bbba277	14	#include <linux/module.h>
2e16a77e LB	15	#include <linux/netdevice.h>
2e16a77e LB	16	#include <linux/phy.h>
c8f0b869	17	#include <net/dsa.h>
6a4b2980	18	#include "mv88e6060.h"
2e16a77e LB	19
	20	static int reg_read(struct dsa_switch *ds, int addr, int reg)
	21	{
b184e497 GR	22	struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);
	23
	24	if (bus == NULL)
	25	return -EINVAL;
	26
f0505610	27	return mdiobus_read_nested(bus, ds->pd->sw_addr + addr, reg);
2e16a77e LB	28	}
	29
	30	#define REG_READ(addr, reg) \
	31	({ \
	32	int __ret; \
	33	\
	34	__ret = reg_read(ds, addr, reg); \
	35	if (__ret < 0) \
	36	return __ret; \
	37	__ret; \
	38	})
	39
	40
	41	static int reg_write(struct dsa_switch *ds, int addr, int reg, u16 val)
	42	{
b184e497 GR	43	struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);
	44
	45	if (bus == NULL)
	46	return -EINVAL;
	47
f0505610	48	return mdiobus_write_nested(bus, ds->pd->sw_addr + addr, reg, val);
2e16a77e LB	49	}
	50
	51	#define REG_WRITE(addr, reg, val) \
	52	({ \
	53	int __ret; \
	54	\
	55	__ret = reg_write(ds, addr, reg, val); \
	56	if (__ret < 0) \
	57	return __ret; \
	58	})
	59
b4d2394d	60	static char mv88e6060_probe(struct device host_dev, int sw_addr)
2e16a77e	61	{
b4d2394d	62	struct mii_bus *bus = dsa_host_dev_to_mii_bus(host_dev);
2e16a77e LB	63	int ret;
2e16a77e LB	64
b4d2394d AD	65	if (bus == NULL)
	66	return NULL;
	67
6a4b2980	68	ret = mdiobus_read(bus, sw_addr + REG_PORT(0), PORT_SWITCH_ID);
2e16a77e	69	if (ret >= 0) {
6a4b2980	70	if (ret == PORT_SWITCH_ID_6060)
3de6aa4c	71	return "Marvell 88E6060 (A0)";
6a4b2980 NA	72	if (ret == PORT_SWITCH_ID_6060_R1 \|\|
6a4b2980 NA	73	ret == PORT_SWITCH_ID_6060_R2)
3de6aa4c	74	return "Marvell 88E6060 (B0)";
6a4b2980	75	if ((ret & PORT_SWITCH_ID_6060_MASK) == PORT_SWITCH_ID_6060)
2e16a77e LB	76	return "Marvell 88E6060";
	77	}
	78
	79	return NULL;
	80	}
	81
	82	static int mv88e6060_switch_reset(struct dsa_switch *ds)
	83	{
	84	int i;
	85	int ret;
19b2f97e	86	unsigned long timeout;
2e16a77e	87
3675c8d7	88	/* Set all ports to the disabled state. */
6a4b2980 NA	89	for (i = 0; i < MV88E6060_PORTS; i++) {
	90	ret = REG_READ(REG_PORT(i), PORT_CONTROL);
	91	REG_WRITE(REG_PORT(i), PORT_CONTROL,
	92	ret & ~PORT_CONTROL_STATE_MASK);
2e16a77e LB	93	}
2e16a77e LB	94
3675c8d7	95	/* Wait for transmit queues to drain. */
19b2f97e	96	usleep_range(2000, 4000);
2e16a77e	97
3675c8d7	98	/* Reset the switch. */
6a4b2980 NA	99	REG_WRITE(REG_GLOBAL, GLOBAL_ATU_CONTROL,
	100	GLOBAL_ATU_CONTROL_SWRESET \|
	101	GLOBAL_ATU_CONTROL_ATUSIZE_1024 \|
	102	GLOBAL_ATU_CONTROL_ATE_AGE_5MIN);
2e16a77e	103
3675c8d7	104	/* Wait up to one second for reset to complete. */
19b2f97e BG	105	timeout = jiffies + 1 * HZ;
19b2f97e BG	106	while (time_before(jiffies, timeout)) {
6a4b2980 NA	107	ret = REG_READ(REG_GLOBAL, GLOBAL_STATUS);
6a4b2980 NA	108	if (ret & GLOBAL_STATUS_INIT_READY)
2e16a77e LB	109	break;
2e16a77e LB	110
19b2f97e	111	usleep_range(1000, 2000);
2e16a77e	112	}
19b2f97e	113	if (time_after(jiffies, timeout))
2e16a77e LB	114	return -ETIMEDOUT;
	115
	116	return 0;
	117	}
	118
	119	static int mv88e6060_setup_global(struct dsa_switch *ds)
	120	{
3675c8d7	121	/* Disable discarding of frames with excessive collisions,
2e16a77e LB	122	* set the maximum frame size to 1536 bytes, and mask all
	123	* interrupt sources.
	124	*/
6a4b2980	125	REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL, GLOBAL_CONTROL_MAX_FRAME_1536);
2e16a77e	126
3675c8d7	127	/* Enable automatic address learning, set the address
2e16a77e LB	128	* database size to 1024 entries, and set the default aging
	129	* time to 5 minutes.
	130	*/
6a4b2980 NA	131	REG_WRITE(REG_GLOBAL, GLOBAL_ATU_CONTROL,
	132	GLOBAL_ATU_CONTROL_ATUSIZE_1024 \|
	133	GLOBAL_ATU_CONTROL_ATE_AGE_5MIN);
2e16a77e LB	134
	135	return 0;
	136	}
	137
	138	static int mv88e6060_setup_port(struct dsa_switch *ds, int p)
	139	{
	140	int addr = REG_PORT(p);
	141
3675c8d7	142	/* Do not force flow control, disable Ingress and Egress
2e16a77e LB	143	* Header tagging, disable VLAN tunneling, and set the port
	144	* state to Forwarding. Additionally, if this is the CPU
	145	* port, enable Ingress and Egress Trailer tagging mode.
	146	*/
6a4b2980 NA	147	REG_WRITE(addr, PORT_CONTROL,
	148	dsa_is_cpu_port(ds, p) ?
	149	PORT_CONTROL_TRAILER \|
	150	PORT_CONTROL_INGRESS_MODE \|
	151	PORT_CONTROL_STATE_FORWARDING :
	152	PORT_CONTROL_STATE_FORWARDING);
2e16a77e	153
3675c8d7	154	/* Port based VLAN map: give each port its own address
2e16a77e LB	155	* database, allow the CPU port to talk to each of the 'real'
	156	* ports, and allow each of the 'real' ports to only talk to
	157	* the CPU port.
	158	*/
6a4b2980 NA	159	REG_WRITE(addr, PORT_VLAN_MAP,
	160	((p & 0xf) << PORT_VLAN_MAP_DBNUM_SHIFT) \|
	161	(dsa_is_cpu_port(ds, p) ?
	162	ds->phys_port_mask :
	163	BIT(ds->dst->cpu_port)));
2e16a77e	164
3675c8d7	165	/* Port Association Vector: when learning source addresses
2e16a77e LB	166	* of packets, add the address to the address database using
	167	* a port bitmap that has only the bit for this port set and
	168	* the other bits clear.
	169	*/
6a4b2980	170	REG_WRITE(addr, PORT_ASSOC_VECTOR, BIT(p));
2e16a77e LB	171
	172	return 0;
	173	}
	174
	175	static int mv88e6060_setup(struct dsa_switch *ds)
	176	{
	177	int i;
	178	int ret;
	179
	180	ret = mv88e6060_switch_reset(ds);
	181	if (ret < 0)
	182	return ret;
	183
	184	/* @@@ initialise atu */
	185
	186	ret = mv88e6060_setup_global(ds);
	187	if (ret < 0)
	188	return ret;
	189
6a4b2980	190	for (i = 0; i < MV88E6060_PORTS; i++) {
2e16a77e LB	191	ret = mv88e6060_setup_port(ds, i);
	192	if (ret < 0)
	193	return ret;
	194	}
	195
	196	return 0;
	197	}
	198
	199	static int mv88e6060_set_addr(struct dsa_switch ds, u8 addr)
	200	{
83ea0f4c	201	/* Use the same MAC Address as FD Pause frames for all ports */
6a4b2980 NA	202	REG_WRITE(REG_GLOBAL, GLOBAL_MAC_01, (addr[0] << 9) \| addr[1]);
	203	REG_WRITE(REG_GLOBAL, GLOBAL_MAC_23, (addr[2] << 8) \| addr[3]);
	204	REG_WRITE(REG_GLOBAL, GLOBAL_MAC_45, (addr[4] << 8) \| addr[5]);
2e16a77e LB	205
	206	return 0;
	207	}
	208
	209	static int mv88e6060_port_to_phy_addr(int port)
	210	{
6a4b2980	211	if (port >= 0 && port < MV88E6060_PORTS)
2e16a77e LB	212	return port;
	213	return -1;
	214	}
	215
	216	static int mv88e6060_phy_read(struct dsa_switch *ds, int port, int regnum)
	217	{
	218	int addr;
	219
	220	addr = mv88e6060_port_to_phy_addr(port);
	221	if (addr == -1)
	222	return 0xffff;
	223
	224	return reg_read(ds, addr, regnum);
	225	}
	226
	227	static int
	228	mv88e6060_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val)
	229	{
	230	int addr;
	231
	232	addr = mv88e6060_port_to_phy_addr(port);
	233	if (addr == -1)
	234	return 0xffff;
	235
	236	return reg_write(ds, addr, regnum, val);
	237	}
	238
2e16a77e	239	static struct dsa_switch_driver mv88e6060_switch_driver = {
ac7a04c3	240	.tag_protocol = DSA_TAG_PROTO_TRAILER,
2e16a77e LB	241	.probe = mv88e6060_probe,
	242	.setup = mv88e6060_setup,
	243	.set_addr = mv88e6060_set_addr,
	244	.phy_read = mv88e6060_phy_read,
	245	.phy_write = mv88e6060_phy_write,
2e16a77e LB	246	};
2e16a77e LB	247
5eaa65b2	248	static int __init mv88e6060_init(void)
2e16a77e LB	249	{
	250	register_switch_driver(&mv88e6060_switch_driver);
	251	return 0;
	252	}
	253	module_init(mv88e6060_init);
	254
5eaa65b2	255	static void __exit mv88e6060_cleanup(void)
2e16a77e LB	256	{
	257	unregister_switch_driver(&mv88e6060_switch_driver);
	258	}
	259	module_exit(mv88e6060_cleanup);
3d825ede BH	260
	261	MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
	262	MODULE_DESCRIPTION("Driver for Marvell 88E6060 ethernet switch chip");
	263	MODULE_LICENSE("GPL");
	264	MODULE_ALIAS("platform:mv88e6060");