[deliverable/linux.git] / drivers / net / dsa / mv88e6060.c

/*
 * net/dsa/mv88e6060.c - Driver for Marvell 88e6060 switch chips
 * Copyright (c) 2008-2009 Marvell Semiconductor
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#include <linux/list.h>
#include <linux/module.h>
#include <linux/netdevice.h>
#include <linux/phy.h>
#include <net/dsa.h>

#define REG_PORT(p)		(8 + (p))
#define REG_GLOBAL		0x0f

static int reg_read(struct dsa_switch *ds, int addr, int reg)
{
	return mdiobus_read(ds->master_mii_bus, ds->pd->sw_addr + addr, reg);
}

#define REG_READ(addr, reg)					\
	({							\
		int __ret;					\
								\
		__ret = reg_read(ds, addr, reg);		\
		if (__ret < 0)					\
			return __ret;				\
		__ret;						\
	})


static int reg_write(struct dsa_switch *ds, int addr, int reg, u16 val)
{
	return mdiobus_write(ds->master_mii_bus, ds->pd->sw_addr + addr,
			     reg, val);
}

#define REG_WRITE(addr, reg, val)				\
	({							\
		int __ret;					\
								\
		__ret = reg_write(ds, addr, reg, val);		\
		if (__ret < 0)					\
			return __ret;				\
	})

static char *mv88e6060_probe(struct mii_bus *bus, int sw_addr)
{
	int ret;

	ret = mdiobus_read(bus, sw_addr + REG_PORT(0), 0x03);
	if (ret >= 0) {
		ret &= 0xfff0;
		if (ret == 0x0600)
			return "Marvell 88E6060";
	}

	return NULL;
}

static int mv88e6060_switch_reset(struct dsa_switch *ds)
{
	int i;
	int ret;

	/* Set all ports to the disabled state. */
	for (i = 0; i < 6; i++) {
		ret = REG_READ(REG_PORT(i), 0x04);
		REG_WRITE(REG_PORT(i), 0x04, ret & 0xfffc);
	}

	/* Wait for transmit queues to drain. */
	msleep(2);

	/* Reset the switch. */
	REG_WRITE(REG_GLOBAL, 0x0a, 0xa130);

	/* Wait up to one second for reset to complete. */
	for (i = 0; i < 1000; i++) {
		ret = REG_READ(REG_GLOBAL, 0x00);
		if ((ret & 0x8000) == 0x0000)
			break;

		msleep(1);
	}
	if (i == 1000)
		return -ETIMEDOUT;

	return 0;
}

static int mv88e6060_setup_global(struct dsa_switch *ds)
{
	/* Disable discarding of frames with excessive collisions,
	 * set the maximum frame size to 1536 bytes, and mask all
	 * interrupt sources.
	 */
	REG_WRITE(REG_GLOBAL, 0x04, 0x0800);

	/* Enable automatic address learning, set the address
	 * database size to 1024 entries, and set the default aging
	 * time to 5 minutes.
	 */
	REG_WRITE(REG_GLOBAL, 0x0a, 0x2130);

	return 0;
}

static int mv88e6060_setup_port(struct dsa_switch *ds, int p)
{
	int addr = REG_PORT(p);

	/* Do not force flow control, disable Ingress and Egress
	 * Header tagging, disable VLAN tunneling, and set the port
	 * state to Forwarding.  Additionally, if this is the CPU
	 * port, enable Ingress and Egress Trailer tagging mode.
	 */
	REG_WRITE(addr, 0x04, dsa_is_cpu_port(ds, p) ?  0x4103 : 0x0003);

	/* Port based VLAN map: give each port its own address
	 * database, allow the CPU port to talk to each of the 'real'
	 * ports, and allow each of the 'real' ports to only talk to
	 * the CPU port.
	 */
	REG_WRITE(addr, 0x06,
			((p & 0xf) << 12) |
			 (dsa_is_cpu_port(ds, p) ?
				ds->phys_port_mask :
				(1 << ds->dst->cpu_port)));

	/* Port Association Vector: when learning source addresses
	 * of packets, add the address to the address database using
	 * a port bitmap that has only the bit for this port set and
	 * the other bits clear.
	 */
	REG_WRITE(addr, 0x0b, 1 << p);

	return 0;
}

static int mv88e6060_setup(struct dsa_switch *ds)
{
	int i;
	int ret;

	ret = mv88e6060_switch_reset(ds);
	if (ret < 0)
		return ret;

	/* @@@ initialise atu */

	ret = mv88e6060_setup_global(ds);
	if (ret < 0)
		return ret;

	for (i = 0; i < 6; i++) {
		ret = mv88e6060_setup_port(ds, i);
		if (ret < 0)
			return ret;
	}

	return 0;
}

static int mv88e6060_set_addr(struct dsa_switch *ds, u8 *addr)
{
	REG_WRITE(REG_GLOBAL, 0x01, (addr[0] << 8) | addr[1]);
	REG_WRITE(REG_GLOBAL, 0x02, (addr[2] << 8) | addr[3]);
	REG_WRITE(REG_GLOBAL, 0x03, (addr[4] << 8) | addr[5]);

	return 0;
}

static int mv88e6060_port_to_phy_addr(int port)
{
	if (port >= 0 && port <= 5)
		return port;
	return -1;
}

static int mv88e6060_phy_read(struct dsa_switch *ds, int port, int regnum)
{
	int addr;

	addr = mv88e6060_port_to_phy_addr(port);
	if (addr == -1)
		return 0xffff;

	return reg_read(ds, addr, regnum);
}

static int
mv88e6060_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val)
{
	int addr;

	addr = mv88e6060_port_to_phy_addr(port);
	if (addr == -1)
		return 0xffff;

	return reg_write(ds, addr, regnum, val);
}

static void mv88e6060_poll_link(struct dsa_switch *ds)
{
	int i;

	for (i = 0; i < DSA_MAX_PORTS; i++) {
		struct net_device *dev;
		int uninitialized_var(port_status);
		int link;
		int speed;
		int duplex;
		int fc;

		dev = ds->ports[i];
		if (dev == NULL)
			continue;

		link = 0;
		if (dev->flags & IFF_UP) {
			port_status = reg_read(ds, REG_PORT(i), 0x00);
			if (port_status < 0)
				continue;

			link = !!(port_status & 0x1000);
		}

		if (!link) {
			if (netif_carrier_ok(dev)) {
				printk(KERN_INFO "%s: link down\n", dev->name);
				netif_carrier_off(dev);
			}
			continue;
		}

		speed = (port_status & 0x0100) ? 100 : 10;
		duplex = (port_status & 0x0200) ? 1 : 0;
		fc = ((port_status & 0xc000) == 0xc000) ? 1 : 0;

		if (!netif_carrier_ok(dev)) {
			printk(KERN_INFO "%s: link up, %d Mb/s, %s duplex, "
					 "flow control %sabled\n", dev->name,
					 speed, duplex ? "full" : "half",
					 fc ? "en" : "dis");
			netif_carrier_on(dev);
		}
	}
}

static struct dsa_switch_driver mv88e6060_switch_driver = {
	.tag_protocol	= htons(ETH_P_TRAILER),
	.probe		= mv88e6060_probe,
	.setup		= mv88e6060_setup,
	.set_addr	= mv88e6060_set_addr,
	.phy_read	= mv88e6060_phy_read,
	.phy_write	= mv88e6060_phy_write,
	.poll_link	= mv88e6060_poll_link,
};

static int __init mv88e6060_init(void)
{
	register_switch_driver(&mv88e6060_switch_driver);
	return 0;
}
module_init(mv88e6060_init);

static void __exit mv88e6060_cleanup(void)
{
	unregister_switch_driver(&mv88e6060_switch_driver);
}
module_exit(mv88e6060_cleanup);

MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
MODULE_DESCRIPTION("Driver for Marvell 88E6060 ethernet switch chip");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:mv88e6060");
Commit	Line	Data
2e16a77e LB	1	/*
2e16a77e LB	2	* net/dsa/mv88e6060.c - Driver for Marvell 88e6060 switch chips
e84665c9	3	* Copyright (c) 2008-2009 Marvell Semiconductor
2e16a77e LB	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License as published by
	7	* the Free Software Foundation; either version 2 of the License, or
	8	* (at your option) any later version.
	9	*/
	10
	11	#include <linux/list.h>
2bbba277	12	#include <linux/module.h>
2e16a77e LB	13	#include <linux/netdevice.h>
2e16a77e LB	14	#include <linux/phy.h>
c8f0b869	15	#include <net/dsa.h>
2e16a77e LB	16
	17	#define REG_PORT(p) (8 + (p))
	18	#define REG_GLOBAL 0x0f
	19
	20	static int reg_read(struct dsa_switch *ds, int addr, int reg)
	21	{
fdb838cd	22	return mdiobus_read(ds->master_mii_bus, ds->pd->sw_addr + addr, reg);
2e16a77e LB	23	}
	24
	25	#define REG_READ(addr, reg) \
	26	({ \
	27	int __ret; \
	28	\
	29	__ret = reg_read(ds, addr, reg); \
	30	if (__ret < 0) \
	31	return __ret; \
	32	__ret; \
	33	})
	34
	35
	36	static int reg_write(struct dsa_switch *ds, int addr, int reg, u16 val)
	37	{
fdb838cd PK	38	return mdiobus_write(ds->master_mii_bus, ds->pd->sw_addr + addr,
fdb838cd PK	39	reg, val);
2e16a77e LB	40	}
	41
	42	#define REG_WRITE(addr, reg, val) \
	43	({ \
	44	int __ret; \
	45	\
	46	__ret = reg_write(ds, addr, reg, val); \
	47	if (__ret < 0) \
	48	return __ret; \
	49	})
	50
	51	static char mv88e6060_probe(struct mii_bus bus, int sw_addr)
	52	{
	53	int ret;
	54
fdb838cd	55	ret = mdiobus_read(bus, sw_addr + REG_PORT(0), 0x03);
2e16a77e LB	56	if (ret >= 0) {
	57	ret &= 0xfff0;
	58	if (ret == 0x0600)
	59	return "Marvell 88E6060";
	60	}
	61
	62	return NULL;
	63	}
	64
	65	static int mv88e6060_switch_reset(struct dsa_switch *ds)
	66	{
	67	int i;
	68	int ret;
	69
3675c8d7	70	/* Set all ports to the disabled state. */
2e16a77e LB	71	for (i = 0; i < 6; i++) {
	72	ret = REG_READ(REG_PORT(i), 0x04);
	73	REG_WRITE(REG_PORT(i), 0x04, ret & 0xfffc);
	74	}
	75
3675c8d7	76	/* Wait for transmit queues to drain. */
2e16a77e LB	77	msleep(2);
2e16a77e LB	78
3675c8d7	79	/* Reset the switch. */
e84665c9	80	REG_WRITE(REG_GLOBAL, 0x0a, 0xa130);
2e16a77e	81
3675c8d7	82	/* Wait up to one second for reset to complete. */
2e16a77e LB	83	for (i = 0; i < 1000; i++) {
	84	ret = REG_READ(REG_GLOBAL, 0x00);
	85	if ((ret & 0x8000) == 0x0000)
	86	break;
	87
	88	msleep(1);
	89	}
	90	if (i == 1000)
	91	return -ETIMEDOUT;
	92
	93	return 0;
	94	}
	95
	96	static int mv88e6060_setup_global(struct dsa_switch *ds)
	97	{
3675c8d7	98	/* Disable discarding of frames with excessive collisions,
2e16a77e LB	99	* set the maximum frame size to 1536 bytes, and mask all
	100	* interrupt sources.
	101	*/
	102	REG_WRITE(REG_GLOBAL, 0x04, 0x0800);
	103
3675c8d7	104	/* Enable automatic address learning, set the address
2e16a77e LB	105	* database size to 1024 entries, and set the default aging
	106	* time to 5 minutes.
	107	*/
	108	REG_WRITE(REG_GLOBAL, 0x0a, 0x2130);
	109
	110	return 0;
	111	}
	112
	113	static int mv88e6060_setup_port(struct dsa_switch *ds, int p)
	114	{
	115	int addr = REG_PORT(p);
	116
3675c8d7	117	/* Do not force flow control, disable Ingress and Egress
2e16a77e LB	118	* Header tagging, disable VLAN tunneling, and set the port
	119	* state to Forwarding. Additionally, if this is the CPU
	120	* port, enable Ingress and Egress Trailer tagging mode.
	121	*/
e84665c9	122	REG_WRITE(addr, 0x04, dsa_is_cpu_port(ds, p) ? 0x4103 : 0x0003);
2e16a77e	123
3675c8d7	124	/* Port based VLAN map: give each port its own address
2e16a77e LB	125	* database, allow the CPU port to talk to each of the 'real'
	126	* ports, and allow each of the 'real' ports to only talk to
	127	* the CPU port.
	128	*/
	129	REG_WRITE(addr, 0x06,
	130	((p & 0xf) << 12) \|
e84665c9 LB	131	(dsa_is_cpu_port(ds, p) ?
	132	ds->phys_port_mask :
	133	(1 << ds->dst->cpu_port)));
2e16a77e	134
3675c8d7	135	/* Port Association Vector: when learning source addresses
2e16a77e LB	136	* of packets, add the address to the address database using
	137	* a port bitmap that has only the bit for this port set and
	138	* the other bits clear.
	139	*/
	140	REG_WRITE(addr, 0x0b, 1 << p);
	141
	142	return 0;
	143	}
	144
	145	static int mv88e6060_setup(struct dsa_switch *ds)
	146	{
	147	int i;
	148	int ret;
	149
	150	ret = mv88e6060_switch_reset(ds);
	151	if (ret < 0)
	152	return ret;
	153
	154	/* @@@ initialise atu */
	155
	156	ret = mv88e6060_setup_global(ds);
	157	if (ret < 0)
	158	return ret;
	159
	160	for (i = 0; i < 6; i++) {
	161	ret = mv88e6060_setup_port(ds, i);
	162	if (ret < 0)
	163	return ret;
	164	}
	165
	166	return 0;
	167	}
	168
	169	static int mv88e6060_set_addr(struct dsa_switch ds, u8 addr)
	170	{
	171	REG_WRITE(REG_GLOBAL, 0x01, (addr[0] << 8) \| addr[1]);
	172	REG_WRITE(REG_GLOBAL, 0x02, (addr[2] << 8) \| addr[3]);
	173	REG_WRITE(REG_GLOBAL, 0x03, (addr[4] << 8) \| addr[5]);
	174
	175	return 0;
	176	}
	177
	178	static int mv88e6060_port_to_phy_addr(int port)
	179	{
	180	if (port >= 0 && port <= 5)
	181	return port;
	182	return -1;
	183	}
	184
	185	static int mv88e6060_phy_read(struct dsa_switch *ds, int port, int regnum)
	186	{
	187	int addr;
	188
	189	addr = mv88e6060_port_to_phy_addr(port);
	190	if (addr == -1)
	191	return 0xffff;
	192
	193	return reg_read(ds, addr, regnum);
	194	}
	195
	196	static int
	197	mv88e6060_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val)
	198	{
	199	int addr;
200
201	addr = mv88e6060_port_to_phy_addr(port);
202	if (addr == -1)
203	return 0xffff;
204
205	return reg_write(ds, addr, regnum, val);
206	}
207
208	static void mv88e6060_poll_link(struct dsa_switch *ds)
209	{
210	int i;
211
212	for (i = 0; i < DSA_MAX_PORTS; i++) {
213	struct net_device *dev;
d3f644da	214	int uninitialized_var(port_status);
2e16a77e LB	215	int link;
	216	int speed;
	217	int duplex;
	218	int fc;
	219
	220	dev = ds->ports[i];
	221	if (dev == NULL)
	222	continue;
	223
	224	link = 0;
	225	if (dev->flags & IFF_UP) {
	226	port_status = reg_read(ds, REG_PORT(i), 0x00);
	227	if (port_status < 0)
	228	continue;
	229
	230	link = !!(port_status & 0x1000);
	231	}
	232
	233	if (!link) {
	234	if (netif_carrier_ok(dev)) {
	235	printk(KERN_INFO "%s: link down\n", dev->name);
	236	netif_carrier_off(dev);
	237	}
	238	continue;
	239	}
	240
	241	speed = (port_status & 0x0100) ? 100 : 10;
	242	duplex = (port_status & 0x0200) ? 1 : 0;
	243	fc = ((port_status & 0xc000) == 0xc000) ? 1 : 0;
	244
	245	if (!netif_carrier_ok(dev)) {
	246	printk(KERN_INFO "%s: link up, %d Mb/s, %s duplex, "
	247	"flow control %sabled\n", dev->name,
	248	speed, duplex ? "full" : "half",
	249	fc ? "en" : "dis");
	250	netif_carrier_on(dev);
	251	}
	252	}
	253	}
	254
	255	static struct dsa_switch_driver mv88e6060_switch_driver = {
	256	.tag_protocol = htons(ETH_P_TRAILER),
	257	.probe = mv88e6060_probe,
	258	.setup = mv88e6060_setup,
	259	.set_addr = mv88e6060_set_addr,
	260	.phy_read = mv88e6060_phy_read,
	261	.phy_write = mv88e6060_phy_write,
	262	.poll_link = mv88e6060_poll_link,
	263	};
	264
5eaa65b2	265	static int __init mv88e6060_init(void)
2e16a77e LB	266	{
	267	register_switch_driver(&mv88e6060_switch_driver);
	268	return 0;
	269	}
	270	module_init(mv88e6060_init);
	271
5eaa65b2	272	static void __exit mv88e6060_cleanup(void)
2e16a77e LB	273	{
	274	unregister_switch_driver(&mv88e6060_switch_driver);
	275	}
	276	module_exit(mv88e6060_cleanup);
3d825ede BH	277
	278	MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
	279	MODULE_DESCRIPTION("Driver for Marvell 88E6060 ethernet switch chip");
	280	MODULE_LICENSE("GPL");
	281	MODULE_ALIAS("platform:mv88e6060");