net: dsa: Rename DSA probe function.
[deliverable/linux.git] / drivers / net / dsa / mv88e6060.c
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1/*
2 * net/dsa/mv88e6060.c - Driver for Marvell 88e6060 switch chips
e84665c9 3 * Copyright (c) 2008-2009 Marvell Semiconductor
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4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 */
10
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11#include <linux/delay.h>
12#include <linux/jiffies.h>
2e16a77e 13#include <linux/list.h>
2bbba277 14#include <linux/module.h>
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15#include <linux/netdevice.h>
16#include <linux/phy.h>
c8f0b869 17#include <net/dsa.h>
6a4b2980 18#include "mv88e6060.h"
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19
20static int reg_read(struct dsa_switch *ds, int addr, int reg)
21{
a77d43f1 22 struct mv88e6060_priv *priv = ds_to_priv(ds);
b184e497 23
a77d43f1 24 return mdiobus_read_nested(priv->bus, priv->sw_addr + addr, reg);
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25}
26
27#define REG_READ(addr, reg) \
28 ({ \
29 int __ret; \
30 \
31 __ret = reg_read(ds, addr, reg); \
32 if (__ret < 0) \
33 return __ret; \
34 __ret; \
35 })
36
37
38static int reg_write(struct dsa_switch *ds, int addr, int reg, u16 val)
39{
a77d43f1 40 struct mv88e6060_priv *priv = ds_to_priv(ds);
b184e497 41
a77d43f1 42 return mdiobus_write_nested(priv->bus, priv->sw_addr + addr, reg, val);
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43}
44
45#define REG_WRITE(addr, reg, val) \
46 ({ \
47 int __ret; \
48 \
49 __ret = reg_write(ds, addr, reg, val); \
50 if (__ret < 0) \
51 return __ret; \
52 })
53
a77d43f1 54static char *mv88e6060_get_name(struct mii_bus *bus, int sw_addr)
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55{
56 int ret;
57
6a4b2980 58 ret = mdiobus_read(bus, sw_addr + REG_PORT(0), PORT_SWITCH_ID);
2e16a77e 59 if (ret >= 0) {
6a4b2980 60 if (ret == PORT_SWITCH_ID_6060)
3de6aa4c 61 return "Marvell 88E6060 (A0)";
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62 if (ret == PORT_SWITCH_ID_6060_R1 ||
63 ret == PORT_SWITCH_ID_6060_R2)
3de6aa4c 64 return "Marvell 88E6060 (B0)";
6a4b2980 65 if ((ret & PORT_SWITCH_ID_6060_MASK) == PORT_SWITCH_ID_6060)
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66 return "Marvell 88E6060";
67 }
68
69 return NULL;
70}
71
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72static char *mv88e6060_drv_probe(struct device *dsa_dev,
73 struct device *host_dev,
74 int sw_addr, void **_priv)
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75{
76 struct mii_bus *bus = dsa_host_dev_to_mii_bus(host_dev);
77 struct mv88e6060_priv *priv;
78 char *name;
79
80 name = mv88e6060_get_name(bus, sw_addr);
81 if (name) {
82 priv = devm_kzalloc(dsa_dev, sizeof(*priv), GFP_KERNEL);
83 if (!priv)
84 return NULL;
85 *_priv = priv;
86 priv->bus = bus;
87 priv->sw_addr = sw_addr;
88 }
89
90 return name;
91}
92
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93static int mv88e6060_switch_reset(struct dsa_switch *ds)
94{
95 int i;
96 int ret;
19b2f97e 97 unsigned long timeout;
2e16a77e 98
3675c8d7 99 /* Set all ports to the disabled state. */
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100 for (i = 0; i < MV88E6060_PORTS; i++) {
101 ret = REG_READ(REG_PORT(i), PORT_CONTROL);
102 REG_WRITE(REG_PORT(i), PORT_CONTROL,
103 ret & ~PORT_CONTROL_STATE_MASK);
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104 }
105
3675c8d7 106 /* Wait for transmit queues to drain. */
19b2f97e 107 usleep_range(2000, 4000);
2e16a77e 108
3675c8d7 109 /* Reset the switch. */
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110 REG_WRITE(REG_GLOBAL, GLOBAL_ATU_CONTROL,
111 GLOBAL_ATU_CONTROL_SWRESET |
112 GLOBAL_ATU_CONTROL_ATUSIZE_1024 |
113 GLOBAL_ATU_CONTROL_ATE_AGE_5MIN);
2e16a77e 114
3675c8d7 115 /* Wait up to one second for reset to complete. */
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116 timeout = jiffies + 1 * HZ;
117 while (time_before(jiffies, timeout)) {
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118 ret = REG_READ(REG_GLOBAL, GLOBAL_STATUS);
119 if (ret & GLOBAL_STATUS_INIT_READY)
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120 break;
121
19b2f97e 122 usleep_range(1000, 2000);
2e16a77e 123 }
19b2f97e 124 if (time_after(jiffies, timeout))
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125 return -ETIMEDOUT;
126
127 return 0;
128}
129
130static int mv88e6060_setup_global(struct dsa_switch *ds)
131{
3675c8d7 132 /* Disable discarding of frames with excessive collisions,
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133 * set the maximum frame size to 1536 bytes, and mask all
134 * interrupt sources.
135 */
6a4b2980 136 REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL, GLOBAL_CONTROL_MAX_FRAME_1536);
2e16a77e 137
3675c8d7 138 /* Enable automatic address learning, set the address
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139 * database size to 1024 entries, and set the default aging
140 * time to 5 minutes.
141 */
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142 REG_WRITE(REG_GLOBAL, GLOBAL_ATU_CONTROL,
143 GLOBAL_ATU_CONTROL_ATUSIZE_1024 |
144 GLOBAL_ATU_CONTROL_ATE_AGE_5MIN);
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145
146 return 0;
147}
148
149static int mv88e6060_setup_port(struct dsa_switch *ds, int p)
150{
151 int addr = REG_PORT(p);
152
3675c8d7 153 /* Do not force flow control, disable Ingress and Egress
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154 * Header tagging, disable VLAN tunneling, and set the port
155 * state to Forwarding. Additionally, if this is the CPU
156 * port, enable Ingress and Egress Trailer tagging mode.
157 */
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158 REG_WRITE(addr, PORT_CONTROL,
159 dsa_is_cpu_port(ds, p) ?
160 PORT_CONTROL_TRAILER |
161 PORT_CONTROL_INGRESS_MODE |
162 PORT_CONTROL_STATE_FORWARDING :
163 PORT_CONTROL_STATE_FORWARDING);
2e16a77e 164
3675c8d7 165 /* Port based VLAN map: give each port its own address
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166 * database, allow the CPU port to talk to each of the 'real'
167 * ports, and allow each of the 'real' ports to only talk to
168 * the CPU port.
169 */
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170 REG_WRITE(addr, PORT_VLAN_MAP,
171 ((p & 0xf) << PORT_VLAN_MAP_DBNUM_SHIFT) |
172 (dsa_is_cpu_port(ds, p) ?
173 ds->phys_port_mask :
174 BIT(ds->dst->cpu_port)));
2e16a77e 175
3675c8d7 176 /* Port Association Vector: when learning source addresses
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177 * of packets, add the address to the address database using
178 * a port bitmap that has only the bit for this port set and
179 * the other bits clear.
180 */
6a4b2980 181 REG_WRITE(addr, PORT_ASSOC_VECTOR, BIT(p));
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182
183 return 0;
184}
185
186static int mv88e6060_setup(struct dsa_switch *ds)
187{
2e16a77e 188 int ret;
a77d43f1 189 int i;
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190
191 ret = mv88e6060_switch_reset(ds);
192 if (ret < 0)
193 return ret;
194
195 /* @@@ initialise atu */
196
197 ret = mv88e6060_setup_global(ds);
198 if (ret < 0)
199 return ret;
200
6a4b2980 201 for (i = 0; i < MV88E6060_PORTS; i++) {
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202 ret = mv88e6060_setup_port(ds, i);
203 if (ret < 0)
204 return ret;
205 }
206
207 return 0;
208}
209
210static int mv88e6060_set_addr(struct dsa_switch *ds, u8 *addr)
211{
83ea0f4c 212 /* Use the same MAC Address as FD Pause frames for all ports */
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213 REG_WRITE(REG_GLOBAL, GLOBAL_MAC_01, (addr[0] << 9) | addr[1]);
214 REG_WRITE(REG_GLOBAL, GLOBAL_MAC_23, (addr[2] << 8) | addr[3]);
215 REG_WRITE(REG_GLOBAL, GLOBAL_MAC_45, (addr[4] << 8) | addr[5]);
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216
217 return 0;
218}
219
220static int mv88e6060_port_to_phy_addr(int port)
221{
6a4b2980 222 if (port >= 0 && port < MV88E6060_PORTS)
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223 return port;
224 return -1;
225}
226
227static int mv88e6060_phy_read(struct dsa_switch *ds, int port, int regnum)
228{
229 int addr;
230
231 addr = mv88e6060_port_to_phy_addr(port);
232 if (addr == -1)
233 return 0xffff;
234
235 return reg_read(ds, addr, regnum);
236}
237
238static int
239mv88e6060_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val)
240{
241 int addr;
242
243 addr = mv88e6060_port_to_phy_addr(port);
244 if (addr == -1)
245 return 0xffff;
246
247 return reg_write(ds, addr, regnum, val);
248}
249
2e16a77e 250static struct dsa_switch_driver mv88e6060_switch_driver = {
ac7a04c3 251 .tag_protocol = DSA_TAG_PROTO_TRAILER,
e49bad31 252 .probe = mv88e6060_drv_probe,
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253 .setup = mv88e6060_setup,
254 .set_addr = mv88e6060_set_addr,
255 .phy_read = mv88e6060_phy_read,
256 .phy_write = mv88e6060_phy_write,
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257};
258
5eaa65b2 259static int __init mv88e6060_init(void)
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260{
261 register_switch_driver(&mv88e6060_switch_driver);
262 return 0;
263}
264module_init(mv88e6060_init);
265
5eaa65b2 266static void __exit mv88e6060_cleanup(void)
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267{
268 unregister_switch_driver(&mv88e6060_switch_driver);
269}
270module_exit(mv88e6060_cleanup);
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271
272MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
273MODULE_DESCRIPTION("Driver for Marvell 88E6060 ethernet switch chip");
274MODULE_LICENSE("GPL");
275MODULE_ALIAS("platform:mv88e6060");
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