projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| f7e39311 NA |
1 | /* |
| 2 | * drivers/net/dsa/mv88e6060.h - Marvell 88e6060 switch chip support | |
| 3 | * Copyright (c) 2015 Neil Armstrong | |
| 4 | * | |
| 5 | * Based on mv88e6xxx.h | |
| 6 | * Copyright (c) 2008 Marvell Semiconductor | |
| 7 | * | |
| 8 | * This program is free software; you can redistribute it and/or modify | |
| 9 | * it under the terms of the GNU General Public License as published by | |
| 10 | * the Free Software Foundation; either version 2 of the License, or | |
| 11 | * (at your option) any later version. | |
| 12 | */ | |
| 13 | ||
| 14 | #ifndef __MV88E6060_H | |
| 15 | #define __MV88E6060_H | |
| 16 | ||
| 17 | #define MV88E6060_PORTS 6 | |
| 18 | ||
| 19 | #define REG_PORT(p) (0x8 + (p)) | |
| 20 | #define PORT_STATUS 0x00 | |
| 21 | #define PORT_STATUS_PAUSE_EN BIT(15) | |
| 22 | #define PORT_STATUS_MY_PAUSE BIT(14) | |
| 23 | #define PORT_STATUS_FC (PORT_STATUS_MY_PAUSE | PORT_STATUS_PAUSE_EN) | |
| 24 | #define PORT_STATUS_RESOLVED BIT(13) | |
| 25 | #define PORT_STATUS_LINK BIT(12) | |
| 26 | #define PORT_STATUS_PORTMODE BIT(11) | |
| 27 | #define PORT_STATUS_PHYMODE BIT(10) | |
| 28 | #define PORT_STATUS_DUPLEX BIT(9) | |
| 29 | #define PORT_STATUS_SPEED BIT(8) | |
| 30 | #define PORT_SWITCH_ID 0x03 | |
| 31 | #define PORT_SWITCH_ID_6060 0x0600 | |
| 32 | #define PORT_SWITCH_ID_6060_MASK 0xfff0 | |
| 33 | #define PORT_SWITCH_ID_6060_R1 0x0601 | |
| 34 | #define PORT_SWITCH_ID_6060_R2 0x0602 | |
| 35 | #define PORT_CONTROL 0x04 | |
| 36 | #define PORT_CONTROL_FORCE_FLOW_CTRL BIT(15) | |
| 37 | #define PORT_CONTROL_TRAILER BIT(14) | |
| 38 | #define PORT_CONTROL_HEADER BIT(11) | |
| 39 | #define PORT_CONTROL_INGRESS_MODE BIT(8) | |
| 40 | #define PORT_CONTROL_VLAN_TUNNEL BIT(7) | |
| 41 | #define PORT_CONTROL_STATE_MASK 0x03 | |
| 42 | #define PORT_CONTROL_STATE_DISABLED 0x00 | |
| 43 | #define PORT_CONTROL_STATE_BLOCKING 0x01 | |
| 44 | #define PORT_CONTROL_STATE_LEARNING 0x02 | |
| 45 | #define PORT_CONTROL_STATE_FORWARDING 0x03 | |
| 46 | #define PORT_VLAN_MAP 0x06 | |
| 47 | #define PORT_VLAN_MAP_DBNUM_SHIFT 12 | |
| 48 | #define PORT_VLAN_MAP_TABLE_MASK 0x1f | |
| 49 | #define PORT_ASSOC_VECTOR 0x0b | |
| 50 | #define PORT_ASSOC_VECTOR_MONITOR BIT(15) | |
| 51 | #define PORT_ASSOC_VECTOR_PAV_MASK 0x1f | |
| 52 | #define PORT_RX_CNTR 0x10 | |
| 53 | #define PORT_TX_CNTR 0x11 | |
| 54 | ||
| 55 | #define REG_GLOBAL 0x0f | |
| 56 | #define GLOBAL_STATUS 0x00 | |
| 57 | #define GLOBAL_STATUS_SW_MODE_MASK (0x3 << 12) | |
| 58 | #define GLOBAL_STATUS_SW_MODE_0 (0x0 << 12) | |
| 59 | #define GLOBAL_STATUS_SW_MODE_1 (0x1 << 12) | |
| 60 | #define GLOBAL_STATUS_SW_MODE_2 (0x2 << 12) | |
| 61 | #define GLOBAL_STATUS_SW_MODE_3 (0x3 << 12) | |
| 62 | #define GLOBAL_STATUS_INIT_READY BIT(11) | |
| 63 | #define GLOBAL_STATUS_ATU_FULL BIT(3) | |
| 64 | #define GLOBAL_STATUS_ATU_DONE BIT(2) | |
| 65 | #define GLOBAL_STATUS_PHY_INT BIT(1) | |
| 66 | #define GLOBAL_STATUS_EEINT BIT(0) | |
| 67 | #define GLOBAL_MAC_01 0x01 | |
| 68 | #define GLOBAL_MAC_01_DIFF_ADDR BIT(8) | |
| 69 | #define GLOBAL_MAC_23 0x02 | |
| 70 | #define GLOBAL_MAC_45 0x03 | |
| 71 | #define GLOBAL_CONTROL 0x04 | |
| 72 | #define GLOBAL_CONTROL_DISCARD_EXCESS BIT(13) | |
| 73 | #define GLOBAL_CONTROL_MAX_FRAME_1536 BIT(10) | |
| 74 | #define GLOBAL_CONTROL_RELOAD_EEPROM BIT(9) | |
| 75 | #define GLOBAL_CONTROL_CTRMODE BIT(8) | |
| 76 | #define GLOBAL_CONTROL_ATU_FULL_EN BIT(3) | |
| 77 | #define GLOBAL_CONTROL_ATU_DONE_EN BIT(2) | |
| 78 | #define GLOBAL_CONTROL_PHYINT_EN BIT(1) | |
| 79 | #define GLOBAL_CONTROL_EEPROM_DONE_EN BIT(0) | |
| 80 | #define GLOBAL_ATU_CONTROL 0x0a | |
| 81 | #define GLOBAL_ATU_CONTROL_SWRESET BIT(15) | |
| 82 | #define GLOBAL_ATU_CONTROL_LEARNDIS BIT(14) | |
| 83 | #define GLOBAL_ATU_CONTROL_ATUSIZE_256 (0x0 << 12) | |
| 84 | #define GLOBAL_ATU_CONTROL_ATUSIZE_512 (0x1 << 12) | |
| 85 | #define GLOBAL_ATU_CONTROL_ATUSIZE_1024 (0x2 << 12) | |
| 86 | #define GLOBAL_ATU_CONTROL_ATE_AGE_SHIFT 4 | |
| 87 | #define GLOBAL_ATU_CONTROL_ATE_AGE_MASK (0xff << 4) | |
| 88 | #define GLOBAL_ATU_CONTROL_ATE_AGE_5MIN (0x13 << 4) | |
| 89 | #define GLOBAL_ATU_OP 0x0b | |
| 90 | #define GLOBAL_ATU_OP_BUSY BIT(15) | |
| 91 | #define GLOBAL_ATU_OP_NOP (0 << 12) | |
| 92 | #define GLOBAL_ATU_OP_FLUSH_ALL ((1 << 12) | GLOBAL_ATU_OP_BUSY) | |
| 93 | #define GLOBAL_ATU_OP_FLUSH_UNLOCKED ((2 << 12) | GLOBAL_ATU_OP_BUSY) | |
| 94 | #define GLOBAL_ATU_OP_LOAD_DB ((3 << 12) | GLOBAL_ATU_OP_BUSY) | |
| 95 | #define GLOBAL_ATU_OP_GET_NEXT_DB ((4 << 12) | GLOBAL_ATU_OP_BUSY) | |
| 96 | #define GLOBAL_ATU_OP_FLUSH_DB ((5 << 12) | GLOBAL_ATU_OP_BUSY) | |
| 97 | #define GLOBAL_ATU_OP_FLUSH_UNLOCKED_DB ((6 << 12) | GLOBAL_ATU_OP_BUSY) | |
| 98 | #define GLOBAL_ATU_DATA 0x0c | |
| 99 | #define GLOBAL_ATU_DATA_PORT_VECTOR_MASK 0x3f0 | |
| 100 | #define GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT 4 | |
| 101 | #define GLOBAL_ATU_DATA_STATE_MASK 0x0f | |
| 102 | #define GLOBAL_ATU_DATA_STATE_UNUSED 0x00 | |
| 103 | #define GLOBAL_ATU_DATA_STATE_UC_STATIC 0x0e | |
| 104 | #define GLOBAL_ATU_DATA_STATE_UC_LOCKED 0x0f | |
| 105 | #define GLOBAL_ATU_DATA_STATE_MC_STATIC 0x07 | |
| 106 | #define GLOBAL_ATU_DATA_STATE_MC_LOCKED 0x0e | |
| 107 | #define GLOBAL_ATU_MAC_01 0x0d | |
| 108 | #define GLOBAL_ATU_MAC_23 0x0e | |
| 109 | #define GLOBAL_ATU_MAC_45 0x0f | |
| 110 | ||
| 111 | #endif |