Commit | Line | Data |
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91da11f8 LB |
1 | /* |
2 | * net/dsa/mv88e6123_61_65.c - Marvell 88e6123/6161/6165 switch chip support | |
e84665c9 | 3 | * Copyright (c) 2008-2009 Marvell Semiconductor |
91da11f8 LB |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation; either version 2 of the License, or | |
8 | * (at your option) any later version. | |
9 | */ | |
10 | ||
19b2f97e BG |
11 | #include <linux/delay.h> |
12 | #include <linux/jiffies.h> | |
91da11f8 | 13 | #include <linux/list.h> |
2bbba277 | 14 | #include <linux/module.h> |
91da11f8 LB |
15 | #include <linux/netdevice.h> |
16 | #include <linux/phy.h> | |
c8f0b869 | 17 | #include <net/dsa.h> |
91da11f8 LB |
18 | #include "mv88e6xxx.h" |
19 | ||
ca3dfa51 | 20 | static const struct mv88e6xxx_switch_id mv88e6123_table[] = { |
b9b37713 VD |
21 | { PORT_SWITCH_ID_6123, "Marvell 88E6123" }, |
22 | { PORT_SWITCH_ID_6123_A1, "Marvell 88E6123 (A1)" }, | |
23 | { PORT_SWITCH_ID_6123_A2, "Marvell 88E6123 (A2)" }, | |
24 | { PORT_SWITCH_ID_6161, "Marvell 88E6161" }, | |
25 | { PORT_SWITCH_ID_6161_A1, "Marvell 88E6161 (A1)" }, | |
26 | { PORT_SWITCH_ID_6161_A2, "Marvell 88E6161 (A2)" }, | |
27 | { PORT_SWITCH_ID_6165, "Marvell 88E6165" }, | |
28 | { PORT_SWITCH_ID_6165_A1, "Marvell 88E6165 (A1)" }, | |
29 | { PORT_SWITCH_ID_6165_A2, "Marvell 88e6165 (A2)" }, | |
30 | }; | |
31 | ||
e49bad31 AL |
32 | static char *mv88e6123_drv_probe(struct device *dsa_dev, |
33 | struct device *host_dev, | |
34 | int sw_addr, void **priv) | |
91da11f8 | 35 | { |
a77d43f1 AL |
36 | return mv88e6xxx_drv_probe(dsa_dev, host_dev, sw_addr, priv, |
37 | mv88e6123_table, | |
38 | ARRAY_SIZE(mv88e6123_table)); | |
91da11f8 LB |
39 | } |
40 | ||
ca3dfa51 | 41 | static int mv88e6123_setup_global(struct dsa_switch *ds) |
91da11f8 | 42 | { |
15966a2a | 43 | u32 upstream_port = dsa_upstream_port(ds); |
91da11f8 | 44 | int ret; |
15966a2a | 45 | u32 reg; |
54d792f2 AL |
46 | |
47 | ret = mv88e6xxx_setup_global(ds); | |
48 | if (ret) | |
49 | return ret; | |
91da11f8 | 50 | |
3675c8d7 | 51 | /* Disable the PHY polling unit (since there won't be any |
91da11f8 LB |
52 | * external PHYs to poll), don't discard packets with |
53 | * excessive collisions, and mask all interrupt sources. | |
54 | */ | |
15966a2a | 55 | REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL, 0x0000); |
91da11f8 | 56 | |
3675c8d7 | 57 | /* Configure the upstream port, and configure the upstream |
e84665c9 LB |
58 | * port as the port to which ingress and egress monitor frames |
59 | * are to be sent. | |
91da11f8 | 60 | */ |
15966a2a AL |
61 | reg = upstream_port << GLOBAL_MONITOR_CONTROL_INGRESS_SHIFT | |
62 | upstream_port << GLOBAL_MONITOR_CONTROL_EGRESS_SHIFT | | |
63 | upstream_port << GLOBAL_MONITOR_CONTROL_ARP_SHIFT; | |
64 | REG_WRITE(REG_GLOBAL, GLOBAL_MONITOR_CONTROL, reg); | |
91da11f8 | 65 | |
3675c8d7 | 66 | /* Disable remote management for now, and set the switch's |
e84665c9 | 67 | * DSA device number. |
91da11f8 | 68 | */ |
15966a2a | 69 | REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL_2, ds->index & 0x1f); |
91da11f8 | 70 | |
91da11f8 LB |
71 | return 0; |
72 | } | |
73 | ||
ca3dfa51 | 74 | static int mv88e6123_setup(struct dsa_switch *ds) |
91da11f8 | 75 | { |
14ef6ad2 | 76 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); |
91da11f8 LB |
77 | int ret; |
78 | ||
7543a6d5 AL |
79 | ps->ds = ds; |
80 | ||
acdaffcc GR |
81 | ret = mv88e6xxx_setup_common(ds); |
82 | if (ret < 0) | |
83 | return ret; | |
91da11f8 | 84 | |
14ef6ad2 | 85 | switch (ps->id) { |
cca8b133 | 86 | case PORT_SWITCH_ID_6123: |
14ef6ad2 GR |
87 | ps->num_ports = 3; |
88 | break; | |
cca8b133 AL |
89 | case PORT_SWITCH_ID_6161: |
90 | case PORT_SWITCH_ID_6165: | |
14ef6ad2 GR |
91 | ps->num_ports = 6; |
92 | break; | |
93 | default: | |
94 | return -ENODEV; | |
95 | } | |
96 | ||
143a8307 | 97 | ret = mv88e6xxx_switch_reset(ds, false); |
91da11f8 LB |
98 | if (ret < 0) |
99 | return ret; | |
100 | ||
ca3dfa51 | 101 | ret = mv88e6123_setup_global(ds); |
91da11f8 LB |
102 | if (ret < 0) |
103 | return ret; | |
104 | ||
dbde9e66 | 105 | return mv88e6xxx_setup_ports(ds); |
91da11f8 LB |
106 | } |
107 | ||
ca3dfa51 | 108 | struct dsa_switch_driver mv88e6123_switch_driver = { |
ac7a04c3 | 109 | .tag_protocol = DSA_TAG_PROTO_EDSA, |
e49bad31 | 110 | .probe = mv88e6123_drv_probe, |
ca3dfa51 | 111 | .setup = mv88e6123_setup, |
91da11f8 | 112 | .set_addr = mv88e6xxx_set_addr_indirect, |
fd3a0ee4 AL |
113 | .phy_read = mv88e6xxx_phy_read, |
114 | .phy_write = mv88e6xxx_phy_write, | |
e413e7e1 AL |
115 | .get_strings = mv88e6xxx_get_strings, |
116 | .get_ethtool_stats = mv88e6xxx_get_ethtool_stats, | |
117 | .get_sset_count = mv88e6xxx_get_sset_count, | |
dea87024 | 118 | .adjust_link = mv88e6xxx_adjust_link, |
87e5f66b | 119 | #ifdef CONFIG_NET_DSA_HWMON |
eaa23765 | 120 | .get_temp = mv88e6xxx_get_temp, |
87e5f66b | 121 | #endif |
a1ab91f3 GR |
122 | .get_regs_len = mv88e6xxx_get_regs_len, |
123 | .get_regs = mv88e6xxx_get_regs, | |
91da11f8 | 124 | }; |
3d825ede BH |
125 | |
126 | MODULE_ALIAS("platform:mv88e6123"); | |
127 | MODULE_ALIAS("platform:mv88e6161"); | |
128 | MODULE_ALIAS("platform:mv88e6165"); |