Commit | Line | Data |
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91da11f8 LB |
1 | /* |
2 | * net/dsa/mv88e6123_61_65.c - Marvell 88e6123/6161/6165 switch chip support | |
e84665c9 | 3 | * Copyright (c) 2008-2009 Marvell Semiconductor |
91da11f8 LB |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation; either version 2 of the License, or | |
8 | * (at your option) any later version. | |
9 | */ | |
10 | ||
19b2f97e BG |
11 | #include <linux/delay.h> |
12 | #include <linux/jiffies.h> | |
91da11f8 | 13 | #include <linux/list.h> |
2bbba277 | 14 | #include <linux/module.h> |
91da11f8 LB |
15 | #include <linux/netdevice.h> |
16 | #include <linux/phy.h> | |
c8f0b869 | 17 | #include <net/dsa.h> |
91da11f8 LB |
18 | #include "mv88e6xxx.h" |
19 | ||
b4d2394d | 20 | static char *mv88e6123_61_65_probe(struct device *host_dev, int sw_addr) |
91da11f8 | 21 | { |
b4d2394d | 22 | struct mii_bus *bus = dsa_host_dev_to_mii_bus(host_dev); |
91da11f8 LB |
23 | int ret; |
24 | ||
b4d2394d AD |
25 | if (bus == NULL) |
26 | return NULL; | |
27 | ||
cca8b133 | 28 | ret = __mv88e6xxx_reg_read(bus, sw_addr, REG_PORT(0), PORT_SWITCH_ID); |
91da11f8 | 29 | if (ret >= 0) { |
cca8b133 | 30 | if (ret == PORT_SWITCH_ID_6123_A1) |
edd664bb | 31 | return "Marvell 88E6123 (A1)"; |
cca8b133 | 32 | if (ret == PORT_SWITCH_ID_6123_A2) |
edd664bb | 33 | return "Marvell 88E6123 (A2)"; |
cca8b133 | 34 | if ((ret & 0xfff0) == PORT_SWITCH_ID_6123) |
91da11f8 | 35 | return "Marvell 88E6123"; |
edd664bb | 36 | |
cca8b133 | 37 | if (ret == PORT_SWITCH_ID_6161_A1) |
edd664bb | 38 | return "Marvell 88E6161 (A1)"; |
cca8b133 | 39 | if (ret == PORT_SWITCH_ID_6161_A2) |
edd664bb | 40 | return "Marvell 88E6161 (A2)"; |
cca8b133 | 41 | if ((ret & 0xfff0) == PORT_SWITCH_ID_6161) |
91da11f8 | 42 | return "Marvell 88E6161"; |
edd664bb | 43 | |
cca8b133 | 44 | if (ret == PORT_SWITCH_ID_6165_A1) |
edd664bb | 45 | return "Marvell 88E6165 (A1)"; |
cca8b133 | 46 | if (ret == PORT_SWITCH_ID_6165_A2) |
edd664bb | 47 | return "Marvell 88e6165 (A2)"; |
cca8b133 | 48 | if ((ret & 0xfff0) == PORT_SWITCH_ID_6165) |
91da11f8 LB |
49 | return "Marvell 88E6165"; |
50 | } | |
51 | ||
52 | return NULL; | |
53 | } | |
54 | ||
91da11f8 LB |
55 | static int mv88e6123_61_65_setup_global(struct dsa_switch *ds) |
56 | { | |
15966a2a | 57 | u32 upstream_port = dsa_upstream_port(ds); |
91da11f8 | 58 | int ret; |
15966a2a | 59 | u32 reg; |
54d792f2 AL |
60 | |
61 | ret = mv88e6xxx_setup_global(ds); | |
62 | if (ret) | |
63 | return ret; | |
91da11f8 | 64 | |
3675c8d7 | 65 | /* Disable the PHY polling unit (since there won't be any |
91da11f8 LB |
66 | * external PHYs to poll), don't discard packets with |
67 | * excessive collisions, and mask all interrupt sources. | |
68 | */ | |
15966a2a | 69 | REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL, 0x0000); |
91da11f8 | 70 | |
3675c8d7 | 71 | /* Configure the upstream port, and configure the upstream |
e84665c9 LB |
72 | * port as the port to which ingress and egress monitor frames |
73 | * are to be sent. | |
91da11f8 | 74 | */ |
15966a2a AL |
75 | reg = upstream_port << GLOBAL_MONITOR_CONTROL_INGRESS_SHIFT | |
76 | upstream_port << GLOBAL_MONITOR_CONTROL_EGRESS_SHIFT | | |
77 | upstream_port << GLOBAL_MONITOR_CONTROL_ARP_SHIFT; | |
78 | REG_WRITE(REG_GLOBAL, GLOBAL_MONITOR_CONTROL, reg); | |
91da11f8 | 79 | |
3675c8d7 | 80 | /* Disable remote management for now, and set the switch's |
e84665c9 | 81 | * DSA device number. |
91da11f8 | 82 | */ |
15966a2a | 83 | REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL_2, ds->index & 0x1f); |
91da11f8 | 84 | |
91da11f8 LB |
85 | return 0; |
86 | } | |
87 | ||
91da11f8 LB |
88 | static int mv88e6123_61_65_setup(struct dsa_switch *ds) |
89 | { | |
14ef6ad2 | 90 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); |
91da11f8 LB |
91 | int ret; |
92 | ||
acdaffcc GR |
93 | ret = mv88e6xxx_setup_common(ds); |
94 | if (ret < 0) | |
95 | return ret; | |
91da11f8 | 96 | |
14ef6ad2 | 97 | switch (ps->id) { |
cca8b133 | 98 | case PORT_SWITCH_ID_6123: |
14ef6ad2 GR |
99 | ps->num_ports = 3; |
100 | break; | |
cca8b133 AL |
101 | case PORT_SWITCH_ID_6161: |
102 | case PORT_SWITCH_ID_6165: | |
14ef6ad2 GR |
103 | ps->num_ports = 6; |
104 | break; | |
105 | default: | |
106 | return -ENODEV; | |
107 | } | |
108 | ||
143a8307 | 109 | ret = mv88e6xxx_switch_reset(ds, false); |
91da11f8 LB |
110 | if (ret < 0) |
111 | return ret; | |
112 | ||
91da11f8 LB |
113 | ret = mv88e6123_61_65_setup_global(ds); |
114 | if (ret < 0) | |
115 | return ret; | |
116 | ||
dbde9e66 | 117 | return mv88e6xxx_setup_ports(ds); |
91da11f8 LB |
118 | } |
119 | ||
98e67308 | 120 | struct dsa_switch_driver mv88e6123_61_65_switch_driver = { |
ac7a04c3 | 121 | .tag_protocol = DSA_TAG_PROTO_EDSA, |
91da11f8 LB |
122 | .priv_size = sizeof(struct mv88e6xxx_priv_state), |
123 | .probe = mv88e6123_61_65_probe, | |
124 | .setup = mv88e6123_61_65_setup, | |
125 | .set_addr = mv88e6xxx_set_addr_indirect, | |
fd3a0ee4 AL |
126 | .phy_read = mv88e6xxx_phy_read, |
127 | .phy_write = mv88e6xxx_phy_write, | |
91da11f8 | 128 | .poll_link = mv88e6xxx_poll_link, |
e413e7e1 AL |
129 | .get_strings = mv88e6xxx_get_strings, |
130 | .get_ethtool_stats = mv88e6xxx_get_ethtool_stats, | |
131 | .get_sset_count = mv88e6xxx_get_sset_count, | |
87e5f66b | 132 | #ifdef CONFIG_NET_DSA_HWMON |
eaa23765 | 133 | .get_temp = mv88e6xxx_get_temp, |
87e5f66b | 134 | #endif |
a1ab91f3 GR |
135 | .get_regs_len = mv88e6xxx_get_regs_len, |
136 | .get_regs = mv88e6xxx_get_regs, | |
91da11f8 | 137 | }; |
3d825ede BH |
138 | |
139 | MODULE_ALIAS("platform:mv88e6123"); | |
140 | MODULE_ALIAS("platform:mv88e6161"); | |
141 | MODULE_ALIAS("platform:mv88e6165"); |