Commit | Line | Data |
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91da11f8 LB |
1 | /* |
2 | * net/dsa/mv88e6123_61_65.c - Marvell 88e6123/6161/6165 switch chip support | |
e84665c9 | 3 | * Copyright (c) 2008-2009 Marvell Semiconductor |
91da11f8 LB |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation; either version 2 of the License, or | |
8 | * (at your option) any later version. | |
9 | */ | |
10 | ||
19b2f97e BG |
11 | #include <linux/delay.h> |
12 | #include <linux/jiffies.h> | |
91da11f8 | 13 | #include <linux/list.h> |
2bbba277 | 14 | #include <linux/module.h> |
91da11f8 LB |
15 | #include <linux/netdevice.h> |
16 | #include <linux/phy.h> | |
c8f0b869 | 17 | #include <net/dsa.h> |
91da11f8 LB |
18 | #include "mv88e6xxx.h" |
19 | ||
b9b37713 VD |
20 | static const struct mv88e6xxx_switch_id mv88e6123_61_65_table[] = { |
21 | { PORT_SWITCH_ID_6123, "Marvell 88E6123" }, | |
22 | { PORT_SWITCH_ID_6123_A1, "Marvell 88E6123 (A1)" }, | |
23 | { PORT_SWITCH_ID_6123_A2, "Marvell 88E6123 (A2)" }, | |
24 | { PORT_SWITCH_ID_6161, "Marvell 88E6161" }, | |
25 | { PORT_SWITCH_ID_6161_A1, "Marvell 88E6161 (A1)" }, | |
26 | { PORT_SWITCH_ID_6161_A2, "Marvell 88E6161 (A2)" }, | |
27 | { PORT_SWITCH_ID_6165, "Marvell 88E6165" }, | |
28 | { PORT_SWITCH_ID_6165_A1, "Marvell 88E6165 (A1)" }, | |
29 | { PORT_SWITCH_ID_6165_A2, "Marvell 88e6165 (A2)" }, | |
30 | }; | |
31 | ||
b4d2394d | 32 | static char *mv88e6123_61_65_probe(struct device *host_dev, int sw_addr) |
91da11f8 | 33 | { |
b9b37713 VD |
34 | return mv88e6xxx_lookup_name(host_dev, sw_addr, mv88e6123_61_65_table, |
35 | ARRAY_SIZE(mv88e6123_61_65_table)); | |
91da11f8 LB |
36 | } |
37 | ||
91da11f8 LB |
38 | static int mv88e6123_61_65_setup_global(struct dsa_switch *ds) |
39 | { | |
15966a2a | 40 | u32 upstream_port = dsa_upstream_port(ds); |
91da11f8 | 41 | int ret; |
15966a2a | 42 | u32 reg; |
54d792f2 AL |
43 | |
44 | ret = mv88e6xxx_setup_global(ds); | |
45 | if (ret) | |
46 | return ret; | |
91da11f8 | 47 | |
3675c8d7 | 48 | /* Disable the PHY polling unit (since there won't be any |
91da11f8 LB |
49 | * external PHYs to poll), don't discard packets with |
50 | * excessive collisions, and mask all interrupt sources. | |
51 | */ | |
15966a2a | 52 | REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL, 0x0000); |
91da11f8 | 53 | |
3675c8d7 | 54 | /* Configure the upstream port, and configure the upstream |
e84665c9 LB |
55 | * port as the port to which ingress and egress monitor frames |
56 | * are to be sent. | |
91da11f8 | 57 | */ |
15966a2a AL |
58 | reg = upstream_port << GLOBAL_MONITOR_CONTROL_INGRESS_SHIFT | |
59 | upstream_port << GLOBAL_MONITOR_CONTROL_EGRESS_SHIFT | | |
60 | upstream_port << GLOBAL_MONITOR_CONTROL_ARP_SHIFT; | |
61 | REG_WRITE(REG_GLOBAL, GLOBAL_MONITOR_CONTROL, reg); | |
91da11f8 | 62 | |
3675c8d7 | 63 | /* Disable remote management for now, and set the switch's |
e84665c9 | 64 | * DSA device number. |
91da11f8 | 65 | */ |
15966a2a | 66 | REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL_2, ds->index & 0x1f); |
91da11f8 | 67 | |
91da11f8 LB |
68 | return 0; |
69 | } | |
70 | ||
91da11f8 LB |
71 | static int mv88e6123_61_65_setup(struct dsa_switch *ds) |
72 | { | |
14ef6ad2 | 73 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); |
91da11f8 LB |
74 | int ret; |
75 | ||
acdaffcc GR |
76 | ret = mv88e6xxx_setup_common(ds); |
77 | if (ret < 0) | |
78 | return ret; | |
91da11f8 | 79 | |
14ef6ad2 | 80 | switch (ps->id) { |
cca8b133 | 81 | case PORT_SWITCH_ID_6123: |
14ef6ad2 GR |
82 | ps->num_ports = 3; |
83 | break; | |
cca8b133 AL |
84 | case PORT_SWITCH_ID_6161: |
85 | case PORT_SWITCH_ID_6165: | |
14ef6ad2 GR |
86 | ps->num_ports = 6; |
87 | break; | |
88 | default: | |
89 | return -ENODEV; | |
90 | } | |
91 | ||
143a8307 | 92 | ret = mv88e6xxx_switch_reset(ds, false); |
91da11f8 LB |
93 | if (ret < 0) |
94 | return ret; | |
95 | ||
91da11f8 LB |
96 | ret = mv88e6123_61_65_setup_global(ds); |
97 | if (ret < 0) | |
98 | return ret; | |
99 | ||
dbde9e66 | 100 | return mv88e6xxx_setup_ports(ds); |
91da11f8 LB |
101 | } |
102 | ||
98e67308 | 103 | struct dsa_switch_driver mv88e6123_61_65_switch_driver = { |
ac7a04c3 | 104 | .tag_protocol = DSA_TAG_PROTO_EDSA, |
91da11f8 LB |
105 | .priv_size = sizeof(struct mv88e6xxx_priv_state), |
106 | .probe = mv88e6123_61_65_probe, | |
107 | .setup = mv88e6123_61_65_setup, | |
108 | .set_addr = mv88e6xxx_set_addr_indirect, | |
fd3a0ee4 AL |
109 | .phy_read = mv88e6xxx_phy_read, |
110 | .phy_write = mv88e6xxx_phy_write, | |
e413e7e1 AL |
111 | .get_strings = mv88e6xxx_get_strings, |
112 | .get_ethtool_stats = mv88e6xxx_get_ethtool_stats, | |
113 | .get_sset_count = mv88e6xxx_get_sset_count, | |
dea87024 | 114 | .adjust_link = mv88e6xxx_adjust_link, |
87e5f66b | 115 | #ifdef CONFIG_NET_DSA_HWMON |
eaa23765 | 116 | .get_temp = mv88e6xxx_get_temp, |
87e5f66b | 117 | #endif |
a1ab91f3 GR |
118 | .get_regs_len = mv88e6xxx_get_regs_len, |
119 | .get_regs = mv88e6xxx_get_regs, | |
91da11f8 | 120 | }; |
3d825ede BH |
121 | |
122 | MODULE_ALIAS("platform:mv88e6123"); | |
123 | MODULE_ALIAS("platform:mv88e6161"); | |
124 | MODULE_ALIAS("platform:mv88e6165"); |