Commit | Line | Data |
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91da11f8 LB |
1 | /* |
2 | * net/dsa/mv88e6123_61_65.c - Marvell 88e6123/6161/6165 switch chip support | |
e84665c9 | 3 | * Copyright (c) 2008-2009 Marvell Semiconductor |
91da11f8 LB |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation; either version 2 of the License, or | |
8 | * (at your option) any later version. | |
9 | */ | |
10 | ||
19b2f97e BG |
11 | #include <linux/delay.h> |
12 | #include <linux/jiffies.h> | |
91da11f8 | 13 | #include <linux/list.h> |
2bbba277 | 14 | #include <linux/module.h> |
91da11f8 LB |
15 | #include <linux/netdevice.h> |
16 | #include <linux/phy.h> | |
c8f0b869 | 17 | #include <net/dsa.h> |
91da11f8 LB |
18 | #include "mv88e6xxx.h" |
19 | ||
b4d2394d | 20 | static char *mv88e6123_61_65_probe(struct device *host_dev, int sw_addr) |
91da11f8 | 21 | { |
b4d2394d | 22 | struct mii_bus *bus = dsa_host_dev_to_mii_bus(host_dev); |
91da11f8 LB |
23 | int ret; |
24 | ||
b4d2394d AD |
25 | if (bus == NULL) |
26 | return NULL; | |
27 | ||
91da11f8 LB |
28 | ret = __mv88e6xxx_reg_read(bus, sw_addr, REG_PORT(0), 0x03); |
29 | if (ret >= 0) { | |
14ef6ad2 | 30 | if (ret == ID_6123_A1) |
edd664bb | 31 | return "Marvell 88E6123 (A1)"; |
14ef6ad2 | 32 | if (ret == ID_6123_A2) |
edd664bb | 33 | return "Marvell 88E6123 (A2)"; |
14ef6ad2 | 34 | if ((ret & 0xfff0) == ID_6123) |
91da11f8 | 35 | return "Marvell 88E6123"; |
edd664bb | 36 | |
14ef6ad2 | 37 | if (ret == ID_6161_A1) |
edd664bb | 38 | return "Marvell 88E6161 (A1)"; |
14ef6ad2 | 39 | if (ret == ID_6161_A2) |
edd664bb | 40 | return "Marvell 88E6161 (A2)"; |
14ef6ad2 | 41 | if ((ret & 0xfff0) == ID_6161) |
91da11f8 | 42 | return "Marvell 88E6161"; |
edd664bb | 43 | |
14ef6ad2 | 44 | if (ret == ID_6165_A1) |
edd664bb | 45 | return "Marvell 88E6165 (A1)"; |
14ef6ad2 | 46 | if (ret == ID_6165_A2) |
edd664bb | 47 | return "Marvell 88e6165 (A2)"; |
14ef6ad2 | 48 | if ((ret & 0xfff0) == ID_6165) |
91da11f8 LB |
49 | return "Marvell 88E6165"; |
50 | } | |
51 | ||
52 | return NULL; | |
53 | } | |
54 | ||
91da11f8 LB |
55 | static int mv88e6123_61_65_setup_global(struct dsa_switch *ds) |
56 | { | |
57 | int ret; | |
58 | int i; | |
59 | ||
3675c8d7 | 60 | /* Disable the PHY polling unit (since there won't be any |
91da11f8 LB |
61 | * external PHYs to poll), don't discard packets with |
62 | * excessive collisions, and mask all interrupt sources. | |
63 | */ | |
64 | REG_WRITE(REG_GLOBAL, 0x04, 0x0000); | |
65 | ||
3675c8d7 | 66 | /* Set the default address aging time to 5 minutes, and |
91da11f8 LB |
67 | * enable address learn messages to be sent to all message |
68 | * ports. | |
69 | */ | |
70 | REG_WRITE(REG_GLOBAL, 0x0a, 0x0148); | |
71 | ||
3675c8d7 | 72 | /* Configure the priority mapping registers. */ |
91da11f8 LB |
73 | ret = mv88e6xxx_config_prio(ds); |
74 | if (ret < 0) | |
75 | return ret; | |
76 | ||
3675c8d7 | 77 | /* Configure the upstream port, and configure the upstream |
e84665c9 LB |
78 | * port as the port to which ingress and egress monitor frames |
79 | * are to be sent. | |
91da11f8 | 80 | */ |
e84665c9 | 81 | REG_WRITE(REG_GLOBAL, 0x1a, (dsa_upstream_port(ds) * 0x1110)); |
91da11f8 | 82 | |
3675c8d7 | 83 | /* Disable remote management for now, and set the switch's |
e84665c9 | 84 | * DSA device number. |
91da11f8 | 85 | */ |
e84665c9 | 86 | REG_WRITE(REG_GLOBAL, 0x1c, ds->index & 0x1f); |
91da11f8 | 87 | |
3675c8d7 | 88 | /* Send all frames with destination addresses matching |
91da11f8 LB |
89 | * 01:80:c2:00:00:2x to the CPU port. |
90 | */ | |
91 | REG_WRITE(REG_GLOBAL2, 0x02, 0xffff); | |
92 | ||
3675c8d7 | 93 | /* Send all frames with destination addresses matching |
91da11f8 LB |
94 | * 01:80:c2:00:00:0x to the CPU port. |
95 | */ | |
96 | REG_WRITE(REG_GLOBAL2, 0x03, 0xffff); | |
97 | ||
3675c8d7 | 98 | /* Disable the loopback filter, disable flow control |
91da11f8 LB |
99 | * messages, disable flood broadcast override, disable |
100 | * removing of provider tags, disable ATU age violation | |
101 | * interrupts, disable tag flow control, force flow | |
102 | * control priority to the highest, and send all special | |
103 | * multicast frames to the CPU at the highest priority. | |
104 | */ | |
105 | REG_WRITE(REG_GLOBAL2, 0x05, 0x00ff); | |
106 | ||
3675c8d7 | 107 | /* Program the DSA routing table. */ |
e84665c9 LB |
108 | for (i = 0; i < 32; i++) { |
109 | int nexthop; | |
110 | ||
111 | nexthop = 0x1f; | |
112 | if (i != ds->index && i < ds->dst->pd->nr_chips) | |
113 | nexthop = ds->pd->rtable[i] & 0x1f; | |
114 | ||
115 | REG_WRITE(REG_GLOBAL2, 0x06, 0x8000 | (i << 8) | nexthop); | |
116 | } | |
91da11f8 | 117 | |
3675c8d7 | 118 | /* Clear all trunk masks. */ |
91da11f8 LB |
119 | for (i = 0; i < 8; i++) |
120 | REG_WRITE(REG_GLOBAL2, 0x07, 0x8000 | (i << 12) | 0xff); | |
121 | ||
3675c8d7 | 122 | /* Clear all trunk mappings. */ |
91da11f8 LB |
123 | for (i = 0; i < 16; i++) |
124 | REG_WRITE(REG_GLOBAL2, 0x08, 0x8000 | (i << 11)); | |
125 | ||
3675c8d7 | 126 | /* Disable ingress rate limiting by resetting all ingress |
91da11f8 LB |
127 | * rate limit registers to their initial state. |
128 | */ | |
129 | for (i = 0; i < 6; i++) | |
130 | REG_WRITE(REG_GLOBAL2, 0x09, 0x9000 | (i << 8)); | |
131 | ||
3675c8d7 | 132 | /* Initialise cross-chip port VLAN table to reset defaults. */ |
91da11f8 LB |
133 | REG_WRITE(REG_GLOBAL2, 0x0b, 0x9000); |
134 | ||
3675c8d7 | 135 | /* Clear the priority override table. */ |
91da11f8 LB |
136 | for (i = 0; i < 16; i++) |
137 | REG_WRITE(REG_GLOBAL2, 0x0f, 0x8000 | (i << 8)); | |
138 | ||
139 | /* @@@ initialise AVB (22/23) watchdog (27) sdet (29) registers */ | |
140 | ||
141 | return 0; | |
142 | } | |
143 | ||
144 | static int mv88e6123_61_65_setup_port(struct dsa_switch *ds, int p) | |
145 | { | |
146 | int addr = REG_PORT(p); | |
e84665c9 | 147 | u16 val; |
91da11f8 | 148 | |
3675c8d7 | 149 | /* MAC Forcing register: don't force link, speed, duplex |
e84665c9 LB |
150 | * or flow control state to any particular values on physical |
151 | * ports, but force the CPU port and all DSA ports to 1000 Mb/s | |
152 | * full duplex. | |
91da11f8 | 153 | */ |
e84665c9 LB |
154 | if (dsa_is_cpu_port(ds, p) || ds->dsa_port_mask & (1 << p)) |
155 | REG_WRITE(addr, 0x01, 0x003e); | |
156 | else | |
157 | REG_WRITE(addr, 0x01, 0x0003); | |
91da11f8 | 158 | |
3675c8d7 | 159 | /* Do not limit the period of time that this port can be |
91da11f8 LB |
160 | * paused for by the remote end or the period of time that |
161 | * this port can pause the remote end. | |
162 | */ | |
163 | REG_WRITE(addr, 0x02, 0x0000); | |
164 | ||
3675c8d7 | 165 | /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock, |
e84665c9 LB |
166 | * disable Header mode, enable IGMP/MLD snooping, disable VLAN |
167 | * tunneling, determine priority by looking at 802.1p and IP | |
168 | * priority fields (IP prio has precedence), and set STP state | |
169 | * to Forwarding. | |
170 | * | |
171 | * If this is the CPU link, use DSA or EDSA tagging depending | |
172 | * on which tagging mode was configured. | |
173 | * | |
174 | * If this is a link to another switch, use DSA tagging mode. | |
175 | * | |
176 | * If this is the upstream port for this switch, enable | |
177 | * forwarding of unknown unicasts and multicasts. | |
91da11f8 | 178 | */ |
e84665c9 LB |
179 | val = 0x0433; |
180 | if (dsa_is_cpu_port(ds, p)) { | |
ac7a04c3 | 181 | if (ds->dst->tag_protocol == DSA_TAG_PROTO_EDSA) |
e84665c9 LB |
182 | val |= 0x3300; |
183 | else | |
184 | val |= 0x0100; | |
185 | } | |
186 | if (ds->dsa_port_mask & (1 << p)) | |
187 | val |= 0x0100; | |
188 | if (p == dsa_upstream_port(ds)) | |
189 | val |= 0x000c; | |
190 | REG_WRITE(addr, 0x04, val); | |
91da11f8 | 191 | |
3675c8d7 | 192 | /* Port Control 2: don't force a good FCS, set the maximum |
91da11f8 LB |
193 | * frame size to 10240 bytes, don't let the switch add or |
194 | * strip 802.1q tags, don't discard tagged or untagged frames | |
195 | * on this port, do a destination address lookup on all | |
196 | * received packets as usual, disable ARP mirroring and don't | |
197 | * send a copy of all transmitted/received frames on this port | |
198 | * to the CPU. | |
199 | */ | |
200 | REG_WRITE(addr, 0x08, 0x2080); | |
201 | ||
3675c8d7 | 202 | /* Egress rate control: disable egress rate control. */ |
91da11f8 LB |
203 | REG_WRITE(addr, 0x09, 0x0001); |
204 | ||
3675c8d7 | 205 | /* Egress rate control 2: disable egress rate control. */ |
91da11f8 LB |
206 | REG_WRITE(addr, 0x0a, 0x0000); |
207 | ||
3675c8d7 | 208 | /* Port Association Vector: when learning source addresses |
91da11f8 LB |
209 | * of packets, add the address to the address database using |
210 | * a port bitmap that has only the bit for this port set and | |
211 | * the other bits clear. | |
212 | */ | |
213 | REG_WRITE(addr, 0x0b, 1 << p); | |
214 | ||
3675c8d7 | 215 | /* Port ATU control: disable limiting the number of address |
91da11f8 LB |
216 | * database entries that this port is allowed to use. |
217 | */ | |
218 | REG_WRITE(addr, 0x0c, 0x0000); | |
219 | ||
3675c8d7 | 220 | /* Priority Override: disable DA, SA and VTU priority override. */ |
91da11f8 LB |
221 | REG_WRITE(addr, 0x0d, 0x0000); |
222 | ||
3675c8d7 | 223 | /* Port Ethertype: use the Ethertype DSA Ethertype value. */ |
91da11f8 LB |
224 | REG_WRITE(addr, 0x0f, ETH_P_EDSA); |
225 | ||
3675c8d7 | 226 | /* Tag Remap: use an identity 802.1p prio -> switch prio |
91da11f8 LB |
227 | * mapping. |
228 | */ | |
229 | REG_WRITE(addr, 0x18, 0x3210); | |
230 | ||
3675c8d7 | 231 | /* Tag Remap 2: use an identity 802.1p prio -> switch prio |
91da11f8 LB |
232 | * mapping. |
233 | */ | |
234 | REG_WRITE(addr, 0x19, 0x7654); | |
235 | ||
54af0cf0 | 236 | return mv88e6xxx_setup_port_common(ds, p); |
91da11f8 LB |
237 | } |
238 | ||
239 | static int mv88e6123_61_65_setup(struct dsa_switch *ds) | |
240 | { | |
14ef6ad2 | 241 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); |
91da11f8 LB |
242 | int i; |
243 | int ret; | |
244 | ||
acdaffcc GR |
245 | ret = mv88e6xxx_setup_common(ds); |
246 | if (ret < 0) | |
247 | return ret; | |
91da11f8 | 248 | |
14ef6ad2 GR |
249 | switch (ps->id) { |
250 | case ID_6123: | |
251 | ps->num_ports = 3; | |
252 | break; | |
253 | case ID_6161: | |
254 | case ID_6165: | |
255 | ps->num_ports = 6; | |
256 | break; | |
257 | default: | |
258 | return -ENODEV; | |
259 | } | |
260 | ||
143a8307 | 261 | ret = mv88e6xxx_switch_reset(ds, false); |
91da11f8 LB |
262 | if (ret < 0) |
263 | return ret; | |
264 | ||
265 | /* @@@ initialise vtu and atu */ | |
266 | ||
267 | ret = mv88e6123_61_65_setup_global(ds); | |
268 | if (ret < 0) | |
269 | return ret; | |
270 | ||
14ef6ad2 | 271 | for (i = 0; i < ps->num_ports; i++) { |
91da11f8 LB |
272 | ret = mv88e6123_61_65_setup_port(ds, i); |
273 | if (ret < 0) | |
274 | return ret; | |
275 | } | |
276 | ||
277 | return 0; | |
278 | } | |
279 | ||
91da11f8 LB |
280 | static struct mv88e6xxx_hw_stat mv88e6123_61_65_hw_stats[] = { |
281 | { "in_good_octets", 8, 0x00, }, | |
282 | { "in_bad_octets", 4, 0x02, }, | |
283 | { "in_unicast", 4, 0x04, }, | |
284 | { "in_broadcasts", 4, 0x06, }, | |
285 | { "in_multicasts", 4, 0x07, }, | |
286 | { "in_pause", 4, 0x16, }, | |
287 | { "in_undersize", 4, 0x18, }, | |
288 | { "in_fragments", 4, 0x19, }, | |
289 | { "in_oversize", 4, 0x1a, }, | |
290 | { "in_jabber", 4, 0x1b, }, | |
291 | { "in_rx_error", 4, 0x1c, }, | |
292 | { "in_fcs_error", 4, 0x1d, }, | |
293 | { "out_octets", 8, 0x0e, }, | |
294 | { "out_unicast", 4, 0x10, }, | |
295 | { "out_broadcasts", 4, 0x13, }, | |
296 | { "out_multicasts", 4, 0x12, }, | |
297 | { "out_pause", 4, 0x15, }, | |
298 | { "excessive", 4, 0x11, }, | |
299 | { "collisions", 4, 0x1e, }, | |
300 | { "deferred", 4, 0x05, }, | |
301 | { "single", 4, 0x14, }, | |
302 | { "multiple", 4, 0x17, }, | |
303 | { "out_fcs_error", 4, 0x03, }, | |
304 | { "late", 4, 0x1f, }, | |
305 | { "hist_64bytes", 4, 0x08, }, | |
306 | { "hist_65_127bytes", 4, 0x09, }, | |
307 | { "hist_128_255bytes", 4, 0x0a, }, | |
308 | { "hist_256_511bytes", 4, 0x0b, }, | |
309 | { "hist_512_1023bytes", 4, 0x0c, }, | |
310 | { "hist_1024_max_bytes", 4, 0x0d, }, | |
17ee3e04 GR |
311 | { "sw_in_discards", 4, 0x110, }, |
312 | { "sw_in_filtered", 2, 0x112, }, | |
313 | { "sw_out_filtered", 2, 0x113, }, | |
91da11f8 LB |
314 | }; |
315 | ||
316 | static void | |
317 | mv88e6123_61_65_get_strings(struct dsa_switch *ds, int port, uint8_t *data) | |
318 | { | |
319 | mv88e6xxx_get_strings(ds, ARRAY_SIZE(mv88e6123_61_65_hw_stats), | |
320 | mv88e6123_61_65_hw_stats, port, data); | |
321 | } | |
322 | ||
323 | static void | |
324 | mv88e6123_61_65_get_ethtool_stats(struct dsa_switch *ds, | |
325 | int port, uint64_t *data) | |
326 | { | |
327 | mv88e6xxx_get_ethtool_stats(ds, ARRAY_SIZE(mv88e6123_61_65_hw_stats), | |
328 | mv88e6123_61_65_hw_stats, port, data); | |
329 | } | |
330 | ||
331 | static int mv88e6123_61_65_get_sset_count(struct dsa_switch *ds) | |
332 | { | |
333 | return ARRAY_SIZE(mv88e6123_61_65_hw_stats); | |
334 | } | |
335 | ||
98e67308 | 336 | struct dsa_switch_driver mv88e6123_61_65_switch_driver = { |
ac7a04c3 | 337 | .tag_protocol = DSA_TAG_PROTO_EDSA, |
91da11f8 LB |
338 | .priv_size = sizeof(struct mv88e6xxx_priv_state), |
339 | .probe = mv88e6123_61_65_probe, | |
340 | .setup = mv88e6123_61_65_setup, | |
341 | .set_addr = mv88e6xxx_set_addr_indirect, | |
fd3a0ee4 AL |
342 | .phy_read = mv88e6xxx_phy_read, |
343 | .phy_write = mv88e6xxx_phy_write, | |
91da11f8 LB |
344 | .poll_link = mv88e6xxx_poll_link, |
345 | .get_strings = mv88e6123_61_65_get_strings, | |
346 | .get_ethtool_stats = mv88e6123_61_65_get_ethtool_stats, | |
347 | .get_sset_count = mv88e6123_61_65_get_sset_count, | |
87e5f66b | 348 | #ifdef CONFIG_NET_DSA_HWMON |
eaa23765 | 349 | .get_temp = mv88e6xxx_get_temp, |
87e5f66b | 350 | #endif |
a1ab91f3 GR |
351 | .get_regs_len = mv88e6xxx_get_regs_len, |
352 | .get_regs = mv88e6xxx_get_regs, | |
91da11f8 | 353 | }; |
3d825ede BH |
354 | |
355 | MODULE_ALIAS("platform:mv88e6123"); | |
356 | MODULE_ALIAS("platform:mv88e6161"); | |
357 | MODULE_ALIAS("platform:mv88e6165"); |