[deliverable/linux.git] / drivers / net / dsa / mv88e6123_61_65.c

/*
 * net/dsa/mv88e6123_61_65.c - Marvell 88e6123/6161/6165 switch chip support
 * Copyright (c) 2008-2009 Marvell Semiconductor
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#include <linux/list.h>
#include <linux/module.h>
#include <linux/netdevice.h>
#include <linux/phy.h>
#include <net/dsa.h>
#include "mv88e6xxx.h"

static char *mv88e6123_61_65_probe(struct mii_bus *bus, int sw_addr)
{
	int ret;

	ret = __mv88e6xxx_reg_read(bus, sw_addr, REG_PORT(0), 0x03);
	if (ret >= 0) {
		if (ret == 0x1212)
			return "Marvell 88E6123 (A1)";
		if (ret == 0x1213)
			return "Marvell 88E6123 (A2)";
		if ((ret & 0xfff0) == 0x1210)
			return "Marvell 88E6123";

		if (ret == 0x1612)
			return "Marvell 88E6161 (A1)";
		if (ret == 0x1613)
			return "Marvell 88E6161 (A2)";
		if ((ret & 0xfff0) == 0x1610)
			return "Marvell 88E6161";

		if (ret == 0x1652)
			return "Marvell 88E6165 (A1)";
		if (ret == 0x1653)
			return "Marvell 88e6165 (A2)";
		if ((ret & 0xfff0) == 0x1650)
			return "Marvell 88E6165";
	}

	return NULL;
}

static int mv88e6123_61_65_switch_reset(struct dsa_switch *ds)
{
	int i;
	int ret;

	/* Set all ports to the disabled state. */
	for (i = 0; i < 8; i++) {
		ret = REG_READ(REG_PORT(i), 0x04);
		REG_WRITE(REG_PORT(i), 0x04, ret & 0xfffc);
	}

	/* Wait for transmit queues to drain. */
	msleep(2);

	/* Reset the switch. */
	REG_WRITE(REG_GLOBAL, 0x04, 0xc400);

	/* Wait up to one second for reset to complete. */
	for (i = 0; i < 1000; i++) {
		ret = REG_READ(REG_GLOBAL, 0x00);
		if ((ret & 0xc800) == 0xc800)
			break;

		msleep(1);
	}
	if (i == 1000)
		return -ETIMEDOUT;

	return 0;
}

static int mv88e6123_61_65_setup_global(struct dsa_switch *ds)
{
	int ret;
	int i;

	/* Disable the PHY polling unit (since there won't be any
	 * external PHYs to poll), don't discard packets with
	 * excessive collisions, and mask all interrupt sources.
	 */
	REG_WRITE(REG_GLOBAL, 0x04, 0x0000);

	/* Set the default address aging time to 5 minutes, and
	 * enable address learn messages to be sent to all message
	 * ports.
	 */
	REG_WRITE(REG_GLOBAL, 0x0a, 0x0148);

	/* Configure the priority mapping registers. */
	ret = mv88e6xxx_config_prio(ds);
	if (ret < 0)
		return ret;

	/* Configure the upstream port, and configure the upstream
	 * port as the port to which ingress and egress monitor frames
	 * are to be sent.
	 */
	REG_WRITE(REG_GLOBAL, 0x1a, (dsa_upstream_port(ds) * 0x1110));

	/* Disable remote management for now, and set the switch's
	 * DSA device number.
	 */
	REG_WRITE(REG_GLOBAL, 0x1c, ds->index & 0x1f);

	/* Send all frames with destination addresses matching
	 * 01:80:c2:00:00:2x to the CPU port.
	 */
	REG_WRITE(REG_GLOBAL2, 0x02, 0xffff);

	/* Send all frames with destination addresses matching
	 * 01:80:c2:00:00:0x to the CPU port.
	 */
	REG_WRITE(REG_GLOBAL2, 0x03, 0xffff);

	/* Disable the loopback filter, disable flow control
	 * messages, disable flood broadcast override, disable
	 * removing of provider tags, disable ATU age violation
	 * interrupts, disable tag flow control, force flow
	 * control priority to the highest, and send all special
	 * multicast frames to the CPU at the highest priority.
	 */
	REG_WRITE(REG_GLOBAL2, 0x05, 0x00ff);

	/* Program the DSA routing table. */
	for (i = 0; i < 32; i++) {
		int nexthop;

		nexthop = 0x1f;
		if (i != ds->index && i < ds->dst->pd->nr_chips)
			nexthop = ds->pd->rtable[i] & 0x1f;

		REG_WRITE(REG_GLOBAL2, 0x06, 0x8000 | (i << 8) | nexthop);
	}

	/* Clear all trunk masks. */
	for (i = 0; i < 8; i++)
		REG_WRITE(REG_GLOBAL2, 0x07, 0x8000 | (i << 12) | 0xff);

	/* Clear all trunk mappings. */
	for (i = 0; i < 16; i++)
		REG_WRITE(REG_GLOBAL2, 0x08, 0x8000 | (i << 11));

	/* Disable ingress rate limiting by resetting all ingress
	 * rate limit registers to their initial state.
	 */
	for (i = 0; i < 6; i++)
		REG_WRITE(REG_GLOBAL2, 0x09, 0x9000 | (i << 8));

	/* Initialise cross-chip port VLAN table to reset defaults. */
	REG_WRITE(REG_GLOBAL2, 0x0b, 0x9000);

	/* Clear the priority override table. */
	for (i = 0; i < 16; i++)
		REG_WRITE(REG_GLOBAL2, 0x0f, 0x8000 | (i << 8));

	/* @@@ initialise AVB (22/23) watchdog (27) sdet (29) registers */

	return 0;
}

static int mv88e6123_61_65_setup_port(struct dsa_switch *ds, int p)
{
	int addr = REG_PORT(p);
	u16 val;

	/* MAC Forcing register: don't force link, speed, duplex
	 * or flow control state to any particular values on physical
	 * ports, but force the CPU port and all DSA ports to 1000 Mb/s
	 * full duplex.
	 */
	if (dsa_is_cpu_port(ds, p) || ds->dsa_port_mask & (1 << p))
		REG_WRITE(addr, 0x01, 0x003e);
	else
		REG_WRITE(addr, 0x01, 0x0003);

	/* Do not limit the period of time that this port can be
	 * paused for by the remote end or the period of time that
	 * this port can pause the remote end.
	 */
	REG_WRITE(addr, 0x02, 0x0000);

	/* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
	 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
	 * tunneling, determine priority by looking at 802.1p and IP
	 * priority fields (IP prio has precedence), and set STP state
	 * to Forwarding.
	 *
	 * If this is the CPU link, use DSA or EDSA tagging depending
	 * on which tagging mode was configured.
	 *
	 * If this is a link to another switch, use DSA tagging mode.
	 *
	 * If this is the upstream port for this switch, enable
	 * forwarding of unknown unicasts and multicasts.
	 */
	val = 0x0433;
	if (dsa_is_cpu_port(ds, p)) {
		if (ds->dst->tag_protocol == htons(ETH_P_EDSA))
			val |= 0x3300;
		else
			val |= 0x0100;
	}
	if (ds->dsa_port_mask & (1 << p))
		val |= 0x0100;
	if (p == dsa_upstream_port(ds))
		val |= 0x000c;
	REG_WRITE(addr, 0x04, val);

	/* Port Control 1: disable trunking.  Also, if this is the
	 * CPU port, enable learn messages to be sent to this port.
	 */
	REG_WRITE(addr, 0x05, dsa_is_cpu_port(ds, p) ? 0x8000 : 0x0000);

	/* Port based VLAN map: give each port its own address
	 * database, allow the CPU port to talk to each of the 'real'
	 * ports, and allow each of the 'real' ports to only talk to
	 * the upstream port.
	 */
	val = (p & 0xf) << 12;
	if (dsa_is_cpu_port(ds, p))
		val |= ds->phys_port_mask;
	else
		val |= 1 << dsa_upstream_port(ds);
	REG_WRITE(addr, 0x06, val);

	/* Default VLAN ID and priority: don't set a default VLAN
	 * ID, and set the default packet priority to zero.
	 */
	REG_WRITE(addr, 0x07, 0x0000);

	/* Port Control 2: don't force a good FCS, set the maximum
	 * frame size to 10240 bytes, don't let the switch add or
	 * strip 802.1q tags, don't discard tagged or untagged frames
	 * on this port, do a destination address lookup on all
	 * received packets as usual, disable ARP mirroring and don't
	 * send a copy of all transmitted/received frames on this port
	 * to the CPU.
	 */
	REG_WRITE(addr, 0x08, 0x2080);

	/* Egress rate control: disable egress rate control. */
	REG_WRITE(addr, 0x09, 0x0001);

	/* Egress rate control 2: disable egress rate control. */
	REG_WRITE(addr, 0x0a, 0x0000);

	/* Port Association Vector: when learning source addresses
	 * of packets, add the address to the address database using
	 * a port bitmap that has only the bit for this port set and
	 * the other bits clear.
	 */
	REG_WRITE(addr, 0x0b, 1 << p);

	/* Port ATU control: disable limiting the number of address
	 * database entries that this port is allowed to use.
	 */
	REG_WRITE(addr, 0x0c, 0x0000);

	/* Priority Override: disable DA, SA and VTU priority override. */
	REG_WRITE(addr, 0x0d, 0x0000);

	/* Port Ethertype: use the Ethertype DSA Ethertype value. */
	REG_WRITE(addr, 0x0f, ETH_P_EDSA);

	/* Tag Remap: use an identity 802.1p prio -> switch prio
	 * mapping.
	 */
	REG_WRITE(addr, 0x18, 0x3210);

	/* Tag Remap 2: use an identity 802.1p prio -> switch prio
	 * mapping.
	 */
	REG_WRITE(addr, 0x19, 0x7654);

	return 0;
}

static int mv88e6123_61_65_setup(struct dsa_switch *ds)
{
	struct mv88e6xxx_priv_state *ps = (void *)(ds + 1);
	int i;
	int ret;

	mutex_init(&ps->smi_mutex);
	mutex_init(&ps->stats_mutex);

	ret = mv88e6123_61_65_switch_reset(ds);
	if (ret < 0)
		return ret;

	/* @@@ initialise vtu and atu */

	ret = mv88e6123_61_65_setup_global(ds);
	if (ret < 0)
		return ret;

	for (i = 0; i < 6; i++) {
		ret = mv88e6123_61_65_setup_port(ds, i);
		if (ret < 0)
			return ret;
	}

	return 0;
}

static int mv88e6123_61_65_port_to_phy_addr(int port)
{
	if (port >= 0 && port <= 4)
		return port;
	return -1;
}

static int
mv88e6123_61_65_phy_read(struct dsa_switch *ds, int port, int regnum)
{
	int addr = mv88e6123_61_65_port_to_phy_addr(port);
	return mv88e6xxx_phy_read(ds, addr, regnum);
}

static int
mv88e6123_61_65_phy_write(struct dsa_switch *ds,
			      int port, int regnum, u16 val)
{
	int addr = mv88e6123_61_65_port_to_phy_addr(port);
	return mv88e6xxx_phy_write(ds, addr, regnum, val);
}

static struct mv88e6xxx_hw_stat mv88e6123_61_65_hw_stats[] = {
	{ "in_good_octets", 8, 0x00, },
	{ "in_bad_octets", 4, 0x02, },
	{ "in_unicast", 4, 0x04, },
	{ "in_broadcasts", 4, 0x06, },
	{ "in_multicasts", 4, 0x07, },
	{ "in_pause", 4, 0x16, },
	{ "in_undersize", 4, 0x18, },
	{ "in_fragments", 4, 0x19, },
	{ "in_oversize", 4, 0x1a, },
	{ "in_jabber", 4, 0x1b, },
	{ "in_rx_error", 4, 0x1c, },
	{ "in_fcs_error", 4, 0x1d, },
	{ "out_octets", 8, 0x0e, },
	{ "out_unicast", 4, 0x10, },
	{ "out_broadcasts", 4, 0x13, },
	{ "out_multicasts", 4, 0x12, },
	{ "out_pause", 4, 0x15, },
	{ "excessive", 4, 0x11, },
	{ "collisions", 4, 0x1e, },
	{ "deferred", 4, 0x05, },
	{ "single", 4, 0x14, },
	{ "multiple", 4, 0x17, },
	{ "out_fcs_error", 4, 0x03, },
	{ "late", 4, 0x1f, },
	{ "hist_64bytes", 4, 0x08, },
	{ "hist_65_127bytes", 4, 0x09, },
	{ "hist_128_255bytes", 4, 0x0a, },
	{ "hist_256_511bytes", 4, 0x0b, },
	{ "hist_512_1023bytes", 4, 0x0c, },
	{ "hist_1024_max_bytes", 4, 0x0d, },
};

static void
mv88e6123_61_65_get_strings(struct dsa_switch *ds, int port, uint8_t *data)
{
	mv88e6xxx_get_strings(ds, ARRAY_SIZE(mv88e6123_61_65_hw_stats),
			      mv88e6123_61_65_hw_stats, port, data);
}

static void
mv88e6123_61_65_get_ethtool_stats(struct dsa_switch *ds,
				  int port, uint64_t *data)
{
	mv88e6xxx_get_ethtool_stats(ds, ARRAY_SIZE(mv88e6123_61_65_hw_stats),
				    mv88e6123_61_65_hw_stats, port, data);
}

static int mv88e6123_61_65_get_sset_count(struct dsa_switch *ds)
{
	return ARRAY_SIZE(mv88e6123_61_65_hw_stats);
}

struct dsa_switch_driver mv88e6123_61_65_switch_driver = {
	.tag_protocol		= cpu_to_be16(ETH_P_EDSA),
	.priv_size		= sizeof(struct mv88e6xxx_priv_state),
	.probe			= mv88e6123_61_65_probe,
	.setup			= mv88e6123_61_65_setup,
	.set_addr		= mv88e6xxx_set_addr_indirect,
	.phy_read		= mv88e6123_61_65_phy_read,
	.phy_write		= mv88e6123_61_65_phy_write,
	.poll_link		= mv88e6xxx_poll_link,
	.get_strings		= mv88e6123_61_65_get_strings,
	.get_ethtool_stats	= mv88e6123_61_65_get_ethtool_stats,
	.get_sset_count		= mv88e6123_61_65_get_sset_count,
};

MODULE_ALIAS("platform:mv88e6123");
MODULE_ALIAS("platform:mv88e6161");
MODULE_ALIAS("platform:mv88e6165");
Commit	Line	Data
91da11f8 LB	1	/*
91da11f8 LB	2	* net/dsa/mv88e6123_61_65.c - Marvell 88e6123/6161/6165 switch chip support
e84665c9	3	* Copyright (c) 2008-2009 Marvell Semiconductor
91da11f8 LB	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License as published by
	7	* the Free Software Foundation; either version 2 of the License, or
	8	* (at your option) any later version.
	9	*/
	10
	11	#include <linux/list.h>
2bbba277	12	#include <linux/module.h>
91da11f8 LB	13	#include <linux/netdevice.h>
91da11f8 LB	14	#include <linux/phy.h>
c8f0b869	15	#include <net/dsa.h>
91da11f8 LB	16	#include "mv88e6xxx.h"
	17
	18	static char mv88e6123_61_65_probe(struct mii_bus bus, int sw_addr)
	19	{
	20	int ret;
	21
	22	ret = __mv88e6xxx_reg_read(bus, sw_addr, REG_PORT(0), 0x03);
	23	if (ret >= 0) {
edd664bb CH	24	if (ret == 0x1212)
	25	return "Marvell 88E6123 (A1)";
	26	if (ret == 0x1213)
	27	return "Marvell 88E6123 (A2)";
	28	if ((ret & 0xfff0) == 0x1210)
91da11f8	29	return "Marvell 88E6123";
edd664bb CH	30
	31	if (ret == 0x1612)
	32	return "Marvell 88E6161 (A1)";
	33	if (ret == 0x1613)
	34	return "Marvell 88E6161 (A2)";
	35	if ((ret & 0xfff0) == 0x1610)
91da11f8	36	return "Marvell 88E6161";
edd664bb CH	37
	38	if (ret == 0x1652)
	39	return "Marvell 88E6165 (A1)";
	40	if (ret == 0x1653)
	41	return "Marvell 88e6165 (A2)";
	42	if ((ret & 0xfff0) == 0x1650)
91da11f8 LB	43	return "Marvell 88E6165";
	44	}
	45
	46	return NULL;
	47	}
	48
	49	static int mv88e6123_61_65_switch_reset(struct dsa_switch *ds)
	50	{
	51	int i;
	52	int ret;
	53
3675c8d7	54	/* Set all ports to the disabled state. */
91da11f8 LB	55	for (i = 0; i < 8; i++) {
	56	ret = REG_READ(REG_PORT(i), 0x04);
	57	REG_WRITE(REG_PORT(i), 0x04, ret & 0xfffc);
	58	}
	59
3675c8d7	60	/* Wait for transmit queues to drain. */
91da11f8 LB	61	msleep(2);
91da11f8 LB	62
3675c8d7	63	/* Reset the switch. */
91da11f8 LB	64	REG_WRITE(REG_GLOBAL, 0x04, 0xc400);
91da11f8 LB	65
3675c8d7	66	/* Wait up to one second for reset to complete. */
91da11f8 LB	67	for (i = 0; i < 1000; i++) {
	68	ret = REG_READ(REG_GLOBAL, 0x00);
	69	if ((ret & 0xc800) == 0xc800)
	70	break;
	71
	72	msleep(1);
	73	}
	74	if (i == 1000)
	75	return -ETIMEDOUT;
	76
	77	return 0;
	78	}
	79
	80	static int mv88e6123_61_65_setup_global(struct dsa_switch *ds)
	81	{
	82	int ret;
	83	int i;
	84
3675c8d7	85	/* Disable the PHY polling unit (since there won't be any
91da11f8 LB	86	* external PHYs to poll), don't discard packets with
	87	* excessive collisions, and mask all interrupt sources.
	88	*/
	89	REG_WRITE(REG_GLOBAL, 0x04, 0x0000);
	90
3675c8d7	91	/* Set the default address aging time to 5 minutes, and
91da11f8 LB	92	* enable address learn messages to be sent to all message
	93	* ports.
	94	*/
	95	REG_WRITE(REG_GLOBAL, 0x0a, 0x0148);
	96
3675c8d7	97	/* Configure the priority mapping registers. */
91da11f8 LB	98	ret = mv88e6xxx_config_prio(ds);
	99	if (ret < 0)
	100	return ret;
	101
3675c8d7	102	/* Configure the upstream port, and configure the upstream
e84665c9 LB	103	* port as the port to which ingress and egress monitor frames
e84665c9 LB	104	* are to be sent.
91da11f8	105	*/
e84665c9	106	REG_WRITE(REG_GLOBAL, 0x1a, (dsa_upstream_port(ds) * 0x1110));
91da11f8	107
3675c8d7	108	/* Disable remote management for now, and set the switch's
e84665c9	109	* DSA device number.
91da11f8	110	*/
e84665c9	111	REG_WRITE(REG_GLOBAL, 0x1c, ds->index & 0x1f);
91da11f8	112
3675c8d7	113	/* Send all frames with destination addresses matching
91da11f8 LB	114	* 01:80:c2:00:00:2x to the CPU port.
	115	*/
	116	REG_WRITE(REG_GLOBAL2, 0x02, 0xffff);
	117
3675c8d7	118	/* Send all frames with destination addresses matching
91da11f8 LB	119	* 01:80:c2:00:00:0x to the CPU port.
	120	*/
	121	REG_WRITE(REG_GLOBAL2, 0x03, 0xffff);
	122
3675c8d7	123	/* Disable the loopback filter, disable flow control
91da11f8 LB	124	* messages, disable flood broadcast override, disable
	125	* removing of provider tags, disable ATU age violation
	126	* interrupts, disable tag flow control, force flow
	127	* control priority to the highest, and send all special
	128	* multicast frames to the CPU at the highest priority.
	129	*/
	130	REG_WRITE(REG_GLOBAL2, 0x05, 0x00ff);
	131
3675c8d7	132	/* Program the DSA routing table. */
e84665c9 LB	133	for (i = 0; i < 32; i++) {
	134	int nexthop;
	135
	136	nexthop = 0x1f;
	137	if (i != ds->index && i < ds->dst->pd->nr_chips)
	138	nexthop = ds->pd->rtable[i] & 0x1f;
	139
	140	REG_WRITE(REG_GLOBAL2, 0x06, 0x8000 \| (i << 8) \| nexthop);
	141	}
91da11f8	142
3675c8d7	143	/* Clear all trunk masks. */
91da11f8 LB	144	for (i = 0; i < 8; i++)
	145	REG_WRITE(REG_GLOBAL2, 0x07, 0x8000 \| (i << 12) \| 0xff);
	146
3675c8d7	147	/* Clear all trunk mappings. */
91da11f8 LB	148	for (i = 0; i < 16; i++)
	149	REG_WRITE(REG_GLOBAL2, 0x08, 0x8000 \| (i << 11));
	150
3675c8d7	151	/* Disable ingress rate limiting by resetting all ingress
91da11f8 LB	152	* rate limit registers to their initial state.
	153	*/
	154	for (i = 0; i < 6; i++)
	155	REG_WRITE(REG_GLOBAL2, 0x09, 0x9000 \| (i << 8));
	156
3675c8d7	157	/* Initialise cross-chip port VLAN table to reset defaults. */
91da11f8 LB	158	REG_WRITE(REG_GLOBAL2, 0x0b, 0x9000);
91da11f8 LB	159
3675c8d7	160	/* Clear the priority override table. */
91da11f8 LB	161	for (i = 0; i < 16; i++)
	162	REG_WRITE(REG_GLOBAL2, 0x0f, 0x8000 \| (i << 8));
	163
	164	/* @@@ initialise AVB (22/23) watchdog (27) sdet (29) registers */
	165
	166	return 0;
	167	}
	168
	169	static int mv88e6123_61_65_setup_port(struct dsa_switch *ds, int p)
	170	{
	171	int addr = REG_PORT(p);
e84665c9	172	u16 val;
91da11f8	173
3675c8d7	174	/* MAC Forcing register: don't force link, speed, duplex
e84665c9 LB	175	* or flow control state to any particular values on physical
	176	* ports, but force the CPU port and all DSA ports to 1000 Mb/s
	177	* full duplex.
91da11f8	178	*/
e84665c9 LB	179	if (dsa_is_cpu_port(ds, p) \|\| ds->dsa_port_mask & (1 << p))
	180	REG_WRITE(addr, 0x01, 0x003e);
	181	else
	182	REG_WRITE(addr, 0x01, 0x0003);
91da11f8	183
3675c8d7	184	/* Do not limit the period of time that this port can be
91da11f8 LB	185	* paused for by the remote end or the period of time that
	186	* this port can pause the remote end.
	187	*/
	188	REG_WRITE(addr, 0x02, 0x0000);
	189
3675c8d7	190	/* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
e84665c9 LB	191	* disable Header mode, enable IGMP/MLD snooping, disable VLAN
	192	* tunneling, determine priority by looking at 802.1p and IP
	193	* priority fields (IP prio has precedence), and set STP state
	194	* to Forwarding.
	195	*
	196	* If this is the CPU link, use DSA or EDSA tagging depending
	197	* on which tagging mode was configured.
	198	*
	199	* If this is a link to another switch, use DSA tagging mode.
	200	*
	201	* If this is the upstream port for this switch, enable
	202	* forwarding of unknown unicasts and multicasts.
91da11f8	203	*/
e84665c9 LB	204	val = 0x0433;
	205	if (dsa_is_cpu_port(ds, p)) {
	206	if (ds->dst->tag_protocol == htons(ETH_P_EDSA))
	207	val \|= 0x3300;
	208	else
	209	val \|= 0x0100;
	210	}
	211	if (ds->dsa_port_mask & (1 << p))
	212	val \|= 0x0100;
	213	if (p == dsa_upstream_port(ds))
	214	val \|= 0x000c;
	215	REG_WRITE(addr, 0x04, val);
91da11f8	216
3675c8d7	217	/* Port Control 1: disable trunking. Also, if this is the
91da11f8 LB	218	* CPU port, enable learn messages to be sent to this port.
91da11f8 LB	219	*/
e84665c9	220	REG_WRITE(addr, 0x05, dsa_is_cpu_port(ds, p) ? 0x8000 : 0x0000);
91da11f8	221
3675c8d7	222	/* Port based VLAN map: give each port its own address
91da11f8 LB	223	* database, allow the CPU port to talk to each of the 'real'
91da11f8 LB	224	* ports, and allow each of the 'real' ports to only talk to
e84665c9	225	* the upstream port.
91da11f8	226	*/
e84665c9 LB	227	val = (p & 0xf) << 12;
	228	if (dsa_is_cpu_port(ds, p))
	229	val \|= ds->phys_port_mask;
	230	else
	231	val \|= 1 << dsa_upstream_port(ds);
	232	REG_WRITE(addr, 0x06, val);
91da11f8	233
3675c8d7	234	/* Default VLAN ID and priority: don't set a default VLAN
91da11f8 LB	235	* ID, and set the default packet priority to zero.
	236	*/
	237	REG_WRITE(addr, 0x07, 0x0000);
	238
3675c8d7	239	/* Port Control 2: don't force a good FCS, set the maximum
91da11f8 LB	240	* frame size to 10240 bytes, don't let the switch add or
	241	* strip 802.1q tags, don't discard tagged or untagged frames
	242	* on this port, do a destination address lookup on all
	243	* received packets as usual, disable ARP mirroring and don't
	244	* send a copy of all transmitted/received frames on this port
	245	* to the CPU.
	246	*/
	247	REG_WRITE(addr, 0x08, 0x2080);
	248
3675c8d7	249	/* Egress rate control: disable egress rate control. */
91da11f8 LB	250	REG_WRITE(addr, 0x09, 0x0001);
91da11f8 LB	251
3675c8d7	252	/* Egress rate control 2: disable egress rate control. */
91da11f8 LB	253	REG_WRITE(addr, 0x0a, 0x0000);
91da11f8 LB	254
3675c8d7	255	/* Port Association Vector: when learning source addresses
91da11f8 LB	256	* of packets, add the address to the address database using
	257	* a port bitmap that has only the bit for this port set and
	258	* the other bits clear.
	259	*/
	260	REG_WRITE(addr, 0x0b, 1 << p);
	261
3675c8d7	262	/* Port ATU control: disable limiting the number of address
91da11f8 LB	263	* database entries that this port is allowed to use.
	264	*/
	265	REG_WRITE(addr, 0x0c, 0x0000);
	266
3675c8d7	267	/* Priority Override: disable DA, SA and VTU priority override. */
91da11f8 LB	268	REG_WRITE(addr, 0x0d, 0x0000);
91da11f8 LB	269
3675c8d7	270	/* Port Ethertype: use the Ethertype DSA Ethertype value. */
91da11f8 LB	271	REG_WRITE(addr, 0x0f, ETH_P_EDSA);
91da11f8 LB	272
3675c8d7	273	/* Tag Remap: use an identity 802.1p prio -> switch prio
91da11f8 LB	274	* mapping.
	275	*/
	276	REG_WRITE(addr, 0x18, 0x3210);
	277
3675c8d7	278	/* Tag Remap 2: use an identity 802.1p prio -> switch prio
91da11f8 LB	279	* mapping.
	280	*/
	281	REG_WRITE(addr, 0x19, 0x7654);
	282
	283	return 0;
	284	}
	285
	286	static int mv88e6123_61_65_setup(struct dsa_switch *ds)
	287	{
	288	struct mv88e6xxx_priv_state ps = (void )(ds + 1);
	289	int i;
	290	int ret;
	291
	292	mutex_init(&ps->smi_mutex);
	293	mutex_init(&ps->stats_mutex);
	294
	295	ret = mv88e6123_61_65_switch_reset(ds);
	296	if (ret < 0)
	297	return ret;
	298
	299	/* @@@ initialise vtu and atu */
	300
	301	ret = mv88e6123_61_65_setup_global(ds);
	302	if (ret < 0)
	303	return ret;
	304
	305	for (i = 0; i < 6; i++) {
	306	ret = mv88e6123_61_65_setup_port(ds, i);
	307	if (ret < 0)
	308	return ret;
	309	}
	310
	311	return 0;
	312	}
	313
	314	static int mv88e6123_61_65_port_to_phy_addr(int port)
	315	{
	316	if (port >= 0 && port <= 4)
	317	return port;
	318	return -1;
	319	}
	320
	321	static int
	322	mv88e6123_61_65_phy_read(struct dsa_switch *ds, int port, int regnum)
	323	{
	324	int addr = mv88e6123_61_65_port_to_phy_addr(port);
	325	return mv88e6xxx_phy_read(ds, addr, regnum);
	326	}
	327
	328	static int
	329	mv88e6123_61_65_phy_write(struct dsa_switch *ds,
	330	int port, int regnum, u16 val)
	331	{
	332	int addr = mv88e6123_61_65_port_to_phy_addr(port);
	333	return mv88e6xxx_phy_write(ds, addr, regnum, val);
	334	}
	335
	336	static struct mv88e6xxx_hw_stat mv88e6123_61_65_hw_stats[] = {
	337	{ "in_good_octets", 8, 0x00, },
	338	{ "in_bad_octets", 4, 0x02, },
	339	{ "in_unicast", 4, 0x04, },
	340	{ "in_broadcasts", 4, 0x06, },
	341	{ "in_multicasts", 4, 0x07, },
	342	{ "in_pause", 4, 0x16, },
343	{ "in_undersize", 4, 0x18, },
344	{ "in_fragments", 4, 0x19, },
345	{ "in_oversize", 4, 0x1a, },
346	{ "in_jabber", 4, 0x1b, },
347	{ "in_rx_error", 4, 0x1c, },
348	{ "in_fcs_error", 4, 0x1d, },
349	{ "out_octets", 8, 0x0e, },
350	{ "out_unicast", 4, 0x10, },
351	{ "out_broadcasts", 4, 0x13, },
352	{ "out_multicasts", 4, 0x12, },
353	{ "out_pause", 4, 0x15, },
354	{ "excessive", 4, 0x11, },
355	{ "collisions", 4, 0x1e, },
356	{ "deferred", 4, 0x05, },
357	{ "single", 4, 0x14, },
358	{ "multiple", 4, 0x17, },
359	{ "out_fcs_error", 4, 0x03, },
360	{ "late", 4, 0x1f, },
361	{ "hist_64bytes", 4, 0x08, },
362	{ "hist_65_127bytes", 4, 0x09, },
363	{ "hist_128_255bytes", 4, 0x0a, },
364	{ "hist_256_511bytes", 4, 0x0b, },
365	{ "hist_512_1023bytes", 4, 0x0c, },
366	{ "hist_1024_max_bytes", 4, 0x0d, },
367	};
368
369	static void
370	mv88e6123_61_65_get_strings(struct dsa_switch ds, int port, uint8_t data)
371	{
372	mv88e6xxx_get_strings(ds, ARRAY_SIZE(mv88e6123_61_65_hw_stats),
373	mv88e6123_61_65_hw_stats, port, data);
374	}
375
376	static void
377	mv88e6123_61_65_get_ethtool_stats(struct dsa_switch *ds,
378	int port, uint64_t *data)
379	{
380	mv88e6xxx_get_ethtool_stats(ds, ARRAY_SIZE(mv88e6123_61_65_hw_stats),
381	mv88e6123_61_65_hw_stats, port, data);
382	}
383
384	static int mv88e6123_61_65_get_sset_count(struct dsa_switch *ds)
385	{
386	return ARRAY_SIZE(mv88e6123_61_65_hw_stats);
387	}
388
98e67308	389	struct dsa_switch_driver mv88e6123_61_65_switch_driver = {
09640e63	390	.tag_protocol = cpu_to_be16(ETH_P_EDSA),
91da11f8 LB	391	.priv_size = sizeof(struct mv88e6xxx_priv_state),
	392	.probe = mv88e6123_61_65_probe,
	393	.setup = mv88e6123_61_65_setup,
	394	.set_addr = mv88e6xxx_set_addr_indirect,
	395	.phy_read = mv88e6123_61_65_phy_read,
	396	.phy_write = mv88e6123_61_65_phy_write,
	397	.poll_link = mv88e6xxx_poll_link,
	398	.get_strings = mv88e6123_61_65_get_strings,
	399	.get_ethtool_stats = mv88e6123_61_65_get_ethtool_stats,
	400	.get_sset_count = mv88e6123_61_65_get_sset_count,
	401	};
3d825ede BH	402
	403	MODULE_ALIAS("platform:mv88e6123");
	404	MODULE_ALIAS("platform:mv88e6161");
	405	MODULE_ALIAS("platform:mv88e6165");