Commit | Line | Data |
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91da11f8 LB |
1 | /* |
2 | * net/dsa/mv88e6123_61_65.c - Marvell 88e6123/6161/6165 switch chip support | |
e84665c9 | 3 | * Copyright (c) 2008-2009 Marvell Semiconductor |
91da11f8 LB |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation; either version 2 of the License, or | |
8 | * (at your option) any later version. | |
9 | */ | |
10 | ||
19b2f97e BG |
11 | #include <linux/delay.h> |
12 | #include <linux/jiffies.h> | |
91da11f8 | 13 | #include <linux/list.h> |
2bbba277 | 14 | #include <linux/module.h> |
91da11f8 LB |
15 | #include <linux/netdevice.h> |
16 | #include <linux/phy.h> | |
c8f0b869 | 17 | #include <net/dsa.h> |
91da11f8 LB |
18 | #include "mv88e6xxx.h" |
19 | ||
b4d2394d | 20 | static char *mv88e6123_61_65_probe(struct device *host_dev, int sw_addr) |
91da11f8 | 21 | { |
b4d2394d | 22 | struct mii_bus *bus = dsa_host_dev_to_mii_bus(host_dev); |
91da11f8 LB |
23 | int ret; |
24 | ||
b4d2394d AD |
25 | if (bus == NULL) |
26 | return NULL; | |
27 | ||
91da11f8 LB |
28 | ret = __mv88e6xxx_reg_read(bus, sw_addr, REG_PORT(0), 0x03); |
29 | if (ret >= 0) { | |
edd664bb CH |
30 | if (ret == 0x1212) |
31 | return "Marvell 88E6123 (A1)"; | |
32 | if (ret == 0x1213) | |
33 | return "Marvell 88E6123 (A2)"; | |
34 | if ((ret & 0xfff0) == 0x1210) | |
91da11f8 | 35 | return "Marvell 88E6123"; |
edd664bb CH |
36 | |
37 | if (ret == 0x1612) | |
38 | return "Marvell 88E6161 (A1)"; | |
39 | if (ret == 0x1613) | |
40 | return "Marvell 88E6161 (A2)"; | |
41 | if ((ret & 0xfff0) == 0x1610) | |
91da11f8 | 42 | return "Marvell 88E6161"; |
edd664bb CH |
43 | |
44 | if (ret == 0x1652) | |
45 | return "Marvell 88E6165 (A1)"; | |
46 | if (ret == 0x1653) | |
47 | return "Marvell 88e6165 (A2)"; | |
48 | if ((ret & 0xfff0) == 0x1650) | |
91da11f8 LB |
49 | return "Marvell 88E6165"; |
50 | } | |
51 | ||
52 | return NULL; | |
53 | } | |
54 | ||
55 | static int mv88e6123_61_65_switch_reset(struct dsa_switch *ds) | |
56 | { | |
57 | int i; | |
58 | int ret; | |
19b2f97e | 59 | unsigned long timeout; |
91da11f8 | 60 | |
3675c8d7 | 61 | /* Set all ports to the disabled state. */ |
91da11f8 LB |
62 | for (i = 0; i < 8; i++) { |
63 | ret = REG_READ(REG_PORT(i), 0x04); | |
64 | REG_WRITE(REG_PORT(i), 0x04, ret & 0xfffc); | |
65 | } | |
66 | ||
3675c8d7 | 67 | /* Wait for transmit queues to drain. */ |
19b2f97e | 68 | usleep_range(2000, 4000); |
91da11f8 | 69 | |
3675c8d7 | 70 | /* Reset the switch. */ |
91da11f8 LB |
71 | REG_WRITE(REG_GLOBAL, 0x04, 0xc400); |
72 | ||
3675c8d7 | 73 | /* Wait up to one second for reset to complete. */ |
19b2f97e BG |
74 | timeout = jiffies + 1 * HZ; |
75 | while (time_before(jiffies, timeout)) { | |
91da11f8 LB |
76 | ret = REG_READ(REG_GLOBAL, 0x00); |
77 | if ((ret & 0xc800) == 0xc800) | |
78 | break; | |
79 | ||
19b2f97e | 80 | usleep_range(1000, 2000); |
91da11f8 | 81 | } |
19b2f97e | 82 | if (time_after(jiffies, timeout)) |
91da11f8 LB |
83 | return -ETIMEDOUT; |
84 | ||
85 | return 0; | |
86 | } | |
87 | ||
88 | static int mv88e6123_61_65_setup_global(struct dsa_switch *ds) | |
89 | { | |
90 | int ret; | |
91 | int i; | |
92 | ||
3675c8d7 | 93 | /* Disable the PHY polling unit (since there won't be any |
91da11f8 LB |
94 | * external PHYs to poll), don't discard packets with |
95 | * excessive collisions, and mask all interrupt sources. | |
96 | */ | |
97 | REG_WRITE(REG_GLOBAL, 0x04, 0x0000); | |
98 | ||
3675c8d7 | 99 | /* Set the default address aging time to 5 minutes, and |
91da11f8 LB |
100 | * enable address learn messages to be sent to all message |
101 | * ports. | |
102 | */ | |
103 | REG_WRITE(REG_GLOBAL, 0x0a, 0x0148); | |
104 | ||
3675c8d7 | 105 | /* Configure the priority mapping registers. */ |
91da11f8 LB |
106 | ret = mv88e6xxx_config_prio(ds); |
107 | if (ret < 0) | |
108 | return ret; | |
109 | ||
3675c8d7 | 110 | /* Configure the upstream port, and configure the upstream |
e84665c9 LB |
111 | * port as the port to which ingress and egress monitor frames |
112 | * are to be sent. | |
91da11f8 | 113 | */ |
e84665c9 | 114 | REG_WRITE(REG_GLOBAL, 0x1a, (dsa_upstream_port(ds) * 0x1110)); |
91da11f8 | 115 | |
3675c8d7 | 116 | /* Disable remote management for now, and set the switch's |
e84665c9 | 117 | * DSA device number. |
91da11f8 | 118 | */ |
e84665c9 | 119 | REG_WRITE(REG_GLOBAL, 0x1c, ds->index & 0x1f); |
91da11f8 | 120 | |
3675c8d7 | 121 | /* Send all frames with destination addresses matching |
91da11f8 LB |
122 | * 01:80:c2:00:00:2x to the CPU port. |
123 | */ | |
124 | REG_WRITE(REG_GLOBAL2, 0x02, 0xffff); | |
125 | ||
3675c8d7 | 126 | /* Send all frames with destination addresses matching |
91da11f8 LB |
127 | * 01:80:c2:00:00:0x to the CPU port. |
128 | */ | |
129 | REG_WRITE(REG_GLOBAL2, 0x03, 0xffff); | |
130 | ||
3675c8d7 | 131 | /* Disable the loopback filter, disable flow control |
91da11f8 LB |
132 | * messages, disable flood broadcast override, disable |
133 | * removing of provider tags, disable ATU age violation | |
134 | * interrupts, disable tag flow control, force flow | |
135 | * control priority to the highest, and send all special | |
136 | * multicast frames to the CPU at the highest priority. | |
137 | */ | |
138 | REG_WRITE(REG_GLOBAL2, 0x05, 0x00ff); | |
139 | ||
3675c8d7 | 140 | /* Program the DSA routing table. */ |
e84665c9 LB |
141 | for (i = 0; i < 32; i++) { |
142 | int nexthop; | |
143 | ||
144 | nexthop = 0x1f; | |
145 | if (i != ds->index && i < ds->dst->pd->nr_chips) | |
146 | nexthop = ds->pd->rtable[i] & 0x1f; | |
147 | ||
148 | REG_WRITE(REG_GLOBAL2, 0x06, 0x8000 | (i << 8) | nexthop); | |
149 | } | |
91da11f8 | 150 | |
3675c8d7 | 151 | /* Clear all trunk masks. */ |
91da11f8 LB |
152 | for (i = 0; i < 8; i++) |
153 | REG_WRITE(REG_GLOBAL2, 0x07, 0x8000 | (i << 12) | 0xff); | |
154 | ||
3675c8d7 | 155 | /* Clear all trunk mappings. */ |
91da11f8 LB |
156 | for (i = 0; i < 16; i++) |
157 | REG_WRITE(REG_GLOBAL2, 0x08, 0x8000 | (i << 11)); | |
158 | ||
3675c8d7 | 159 | /* Disable ingress rate limiting by resetting all ingress |
91da11f8 LB |
160 | * rate limit registers to their initial state. |
161 | */ | |
162 | for (i = 0; i < 6; i++) | |
163 | REG_WRITE(REG_GLOBAL2, 0x09, 0x9000 | (i << 8)); | |
164 | ||
3675c8d7 | 165 | /* Initialise cross-chip port VLAN table to reset defaults. */ |
91da11f8 LB |
166 | REG_WRITE(REG_GLOBAL2, 0x0b, 0x9000); |
167 | ||
3675c8d7 | 168 | /* Clear the priority override table. */ |
91da11f8 LB |
169 | for (i = 0; i < 16; i++) |
170 | REG_WRITE(REG_GLOBAL2, 0x0f, 0x8000 | (i << 8)); | |
171 | ||
172 | /* @@@ initialise AVB (22/23) watchdog (27) sdet (29) registers */ | |
173 | ||
174 | return 0; | |
175 | } | |
176 | ||
177 | static int mv88e6123_61_65_setup_port(struct dsa_switch *ds, int p) | |
178 | { | |
179 | int addr = REG_PORT(p); | |
e84665c9 | 180 | u16 val; |
91da11f8 | 181 | |
3675c8d7 | 182 | /* MAC Forcing register: don't force link, speed, duplex |
e84665c9 LB |
183 | * or flow control state to any particular values on physical |
184 | * ports, but force the CPU port and all DSA ports to 1000 Mb/s | |
185 | * full duplex. | |
91da11f8 | 186 | */ |
e84665c9 LB |
187 | if (dsa_is_cpu_port(ds, p) || ds->dsa_port_mask & (1 << p)) |
188 | REG_WRITE(addr, 0x01, 0x003e); | |
189 | else | |
190 | REG_WRITE(addr, 0x01, 0x0003); | |
91da11f8 | 191 | |
3675c8d7 | 192 | /* Do not limit the period of time that this port can be |
91da11f8 LB |
193 | * paused for by the remote end or the period of time that |
194 | * this port can pause the remote end. | |
195 | */ | |
196 | REG_WRITE(addr, 0x02, 0x0000); | |
197 | ||
3675c8d7 | 198 | /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock, |
e84665c9 LB |
199 | * disable Header mode, enable IGMP/MLD snooping, disable VLAN |
200 | * tunneling, determine priority by looking at 802.1p and IP | |
201 | * priority fields (IP prio has precedence), and set STP state | |
202 | * to Forwarding. | |
203 | * | |
204 | * If this is the CPU link, use DSA or EDSA tagging depending | |
205 | * on which tagging mode was configured. | |
206 | * | |
207 | * If this is a link to another switch, use DSA tagging mode. | |
208 | * | |
209 | * If this is the upstream port for this switch, enable | |
210 | * forwarding of unknown unicasts and multicasts. | |
91da11f8 | 211 | */ |
e84665c9 LB |
212 | val = 0x0433; |
213 | if (dsa_is_cpu_port(ds, p)) { | |
ac7a04c3 | 214 | if (ds->dst->tag_protocol == DSA_TAG_PROTO_EDSA) |
e84665c9 LB |
215 | val |= 0x3300; |
216 | else | |
217 | val |= 0x0100; | |
218 | } | |
219 | if (ds->dsa_port_mask & (1 << p)) | |
220 | val |= 0x0100; | |
221 | if (p == dsa_upstream_port(ds)) | |
222 | val |= 0x000c; | |
223 | REG_WRITE(addr, 0x04, val); | |
91da11f8 | 224 | |
3675c8d7 | 225 | /* Port Control 1: disable trunking. Also, if this is the |
91da11f8 LB |
226 | * CPU port, enable learn messages to be sent to this port. |
227 | */ | |
e84665c9 | 228 | REG_WRITE(addr, 0x05, dsa_is_cpu_port(ds, p) ? 0x8000 : 0x0000); |
91da11f8 | 229 | |
3675c8d7 | 230 | /* Port based VLAN map: give each port its own address |
91da11f8 LB |
231 | * database, allow the CPU port to talk to each of the 'real' |
232 | * ports, and allow each of the 'real' ports to only talk to | |
e84665c9 | 233 | * the upstream port. |
91da11f8 | 234 | */ |
e84665c9 LB |
235 | val = (p & 0xf) << 12; |
236 | if (dsa_is_cpu_port(ds, p)) | |
237 | val |= ds->phys_port_mask; | |
238 | else | |
239 | val |= 1 << dsa_upstream_port(ds); | |
240 | REG_WRITE(addr, 0x06, val); | |
91da11f8 | 241 | |
3675c8d7 | 242 | /* Default VLAN ID and priority: don't set a default VLAN |
91da11f8 LB |
243 | * ID, and set the default packet priority to zero. |
244 | */ | |
245 | REG_WRITE(addr, 0x07, 0x0000); | |
246 | ||
3675c8d7 | 247 | /* Port Control 2: don't force a good FCS, set the maximum |
91da11f8 LB |
248 | * frame size to 10240 bytes, don't let the switch add or |
249 | * strip 802.1q tags, don't discard tagged or untagged frames | |
250 | * on this port, do a destination address lookup on all | |
251 | * received packets as usual, disable ARP mirroring and don't | |
252 | * send a copy of all transmitted/received frames on this port | |
253 | * to the CPU. | |
254 | */ | |
255 | REG_WRITE(addr, 0x08, 0x2080); | |
256 | ||
3675c8d7 | 257 | /* Egress rate control: disable egress rate control. */ |
91da11f8 LB |
258 | REG_WRITE(addr, 0x09, 0x0001); |
259 | ||
3675c8d7 | 260 | /* Egress rate control 2: disable egress rate control. */ |
91da11f8 LB |
261 | REG_WRITE(addr, 0x0a, 0x0000); |
262 | ||
3675c8d7 | 263 | /* Port Association Vector: when learning source addresses |
91da11f8 LB |
264 | * of packets, add the address to the address database using |
265 | * a port bitmap that has only the bit for this port set and | |
266 | * the other bits clear. | |
267 | */ | |
268 | REG_WRITE(addr, 0x0b, 1 << p); | |
269 | ||
3675c8d7 | 270 | /* Port ATU control: disable limiting the number of address |
91da11f8 LB |
271 | * database entries that this port is allowed to use. |
272 | */ | |
273 | REG_WRITE(addr, 0x0c, 0x0000); | |
274 | ||
3675c8d7 | 275 | /* Priority Override: disable DA, SA and VTU priority override. */ |
91da11f8 LB |
276 | REG_WRITE(addr, 0x0d, 0x0000); |
277 | ||
3675c8d7 | 278 | /* Port Ethertype: use the Ethertype DSA Ethertype value. */ |
91da11f8 LB |
279 | REG_WRITE(addr, 0x0f, ETH_P_EDSA); |
280 | ||
3675c8d7 | 281 | /* Tag Remap: use an identity 802.1p prio -> switch prio |
91da11f8 LB |
282 | * mapping. |
283 | */ | |
284 | REG_WRITE(addr, 0x18, 0x3210); | |
285 | ||
3675c8d7 | 286 | /* Tag Remap 2: use an identity 802.1p prio -> switch prio |
91da11f8 LB |
287 | * mapping. |
288 | */ | |
289 | REG_WRITE(addr, 0x19, 0x7654); | |
290 | ||
291 | return 0; | |
292 | } | |
293 | ||
294 | static int mv88e6123_61_65_setup(struct dsa_switch *ds) | |
295 | { | |
a22adce5 | 296 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); |
91da11f8 LB |
297 | int i; |
298 | int ret; | |
299 | ||
300 | mutex_init(&ps->smi_mutex); | |
301 | mutex_init(&ps->stats_mutex); | |
87e5f66b | 302 | mutex_init(&ps->phy_mutex); |
91da11f8 LB |
303 | |
304 | ret = mv88e6123_61_65_switch_reset(ds); | |
305 | if (ret < 0) | |
306 | return ret; | |
307 | ||
308 | /* @@@ initialise vtu and atu */ | |
309 | ||
310 | ret = mv88e6123_61_65_setup_global(ds); | |
311 | if (ret < 0) | |
312 | return ret; | |
313 | ||
314 | for (i = 0; i < 6; i++) { | |
315 | ret = mv88e6123_61_65_setup_port(ds, i); | |
316 | if (ret < 0) | |
317 | return ret; | |
318 | } | |
319 | ||
320 | return 0; | |
321 | } | |
322 | ||
323 | static int mv88e6123_61_65_port_to_phy_addr(int port) | |
324 | { | |
325 | if (port >= 0 && port <= 4) | |
326 | return port; | |
327 | return -1; | |
328 | } | |
329 | ||
330 | static int | |
331 | mv88e6123_61_65_phy_read(struct dsa_switch *ds, int port, int regnum) | |
332 | { | |
87e5f66b | 333 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); |
91da11f8 | 334 | int addr = mv88e6123_61_65_port_to_phy_addr(port); |
87e5f66b GR |
335 | int ret; |
336 | ||
337 | mutex_lock(&ps->phy_mutex); | |
338 | ret = mv88e6xxx_phy_read(ds, addr, regnum); | |
339 | mutex_unlock(&ps->phy_mutex); | |
340 | return ret; | |
91da11f8 LB |
341 | } |
342 | ||
343 | static int | |
344 | mv88e6123_61_65_phy_write(struct dsa_switch *ds, | |
345 | int port, int regnum, u16 val) | |
346 | { | |
87e5f66b | 347 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); |
91da11f8 | 348 | int addr = mv88e6123_61_65_port_to_phy_addr(port); |
87e5f66b GR |
349 | int ret; |
350 | ||
351 | mutex_lock(&ps->phy_mutex); | |
352 | ret = mv88e6xxx_phy_write(ds, addr, regnum, val); | |
353 | mutex_unlock(&ps->phy_mutex); | |
354 | return ret; | |
91da11f8 LB |
355 | } |
356 | ||
357 | static struct mv88e6xxx_hw_stat mv88e6123_61_65_hw_stats[] = { | |
358 | { "in_good_octets", 8, 0x00, }, | |
359 | { "in_bad_octets", 4, 0x02, }, | |
360 | { "in_unicast", 4, 0x04, }, | |
361 | { "in_broadcasts", 4, 0x06, }, | |
362 | { "in_multicasts", 4, 0x07, }, | |
363 | { "in_pause", 4, 0x16, }, | |
364 | { "in_undersize", 4, 0x18, }, | |
365 | { "in_fragments", 4, 0x19, }, | |
366 | { "in_oversize", 4, 0x1a, }, | |
367 | { "in_jabber", 4, 0x1b, }, | |
368 | { "in_rx_error", 4, 0x1c, }, | |
369 | { "in_fcs_error", 4, 0x1d, }, | |
370 | { "out_octets", 8, 0x0e, }, | |
371 | { "out_unicast", 4, 0x10, }, | |
372 | { "out_broadcasts", 4, 0x13, }, | |
373 | { "out_multicasts", 4, 0x12, }, | |
374 | { "out_pause", 4, 0x15, }, | |
375 | { "excessive", 4, 0x11, }, | |
376 | { "collisions", 4, 0x1e, }, | |
377 | { "deferred", 4, 0x05, }, | |
378 | { "single", 4, 0x14, }, | |
379 | { "multiple", 4, 0x17, }, | |
380 | { "out_fcs_error", 4, 0x03, }, | |
381 | { "late", 4, 0x1f, }, | |
382 | { "hist_64bytes", 4, 0x08, }, | |
383 | { "hist_65_127bytes", 4, 0x09, }, | |
384 | { "hist_128_255bytes", 4, 0x0a, }, | |
385 | { "hist_256_511bytes", 4, 0x0b, }, | |
386 | { "hist_512_1023bytes", 4, 0x0c, }, | |
387 | { "hist_1024_max_bytes", 4, 0x0d, }, | |
17ee3e04 GR |
388 | { "sw_in_discards", 4, 0x110, }, |
389 | { "sw_in_filtered", 2, 0x112, }, | |
390 | { "sw_out_filtered", 2, 0x113, }, | |
91da11f8 LB |
391 | }; |
392 | ||
393 | static void | |
394 | mv88e6123_61_65_get_strings(struct dsa_switch *ds, int port, uint8_t *data) | |
395 | { | |
396 | mv88e6xxx_get_strings(ds, ARRAY_SIZE(mv88e6123_61_65_hw_stats), | |
397 | mv88e6123_61_65_hw_stats, port, data); | |
398 | } | |
399 | ||
400 | static void | |
401 | mv88e6123_61_65_get_ethtool_stats(struct dsa_switch *ds, | |
402 | int port, uint64_t *data) | |
403 | { | |
404 | mv88e6xxx_get_ethtool_stats(ds, ARRAY_SIZE(mv88e6123_61_65_hw_stats), | |
405 | mv88e6123_61_65_hw_stats, port, data); | |
406 | } | |
407 | ||
408 | static int mv88e6123_61_65_get_sset_count(struct dsa_switch *ds) | |
409 | { | |
410 | return ARRAY_SIZE(mv88e6123_61_65_hw_stats); | |
411 | } | |
412 | ||
98e67308 | 413 | struct dsa_switch_driver mv88e6123_61_65_switch_driver = { |
ac7a04c3 | 414 | .tag_protocol = DSA_TAG_PROTO_EDSA, |
91da11f8 LB |
415 | .priv_size = sizeof(struct mv88e6xxx_priv_state), |
416 | .probe = mv88e6123_61_65_probe, | |
417 | .setup = mv88e6123_61_65_setup, | |
418 | .set_addr = mv88e6xxx_set_addr_indirect, | |
419 | .phy_read = mv88e6123_61_65_phy_read, | |
420 | .phy_write = mv88e6123_61_65_phy_write, | |
421 | .poll_link = mv88e6xxx_poll_link, | |
422 | .get_strings = mv88e6123_61_65_get_strings, | |
423 | .get_ethtool_stats = mv88e6123_61_65_get_ethtool_stats, | |
424 | .get_sset_count = mv88e6123_61_65_get_sset_count, | |
87e5f66b | 425 | #ifdef CONFIG_NET_DSA_HWMON |
eaa23765 | 426 | .get_temp = mv88e6xxx_get_temp, |
87e5f66b | 427 | #endif |
a1ab91f3 GR |
428 | .get_regs_len = mv88e6xxx_get_regs_len, |
429 | .get_regs = mv88e6xxx_get_regs, | |
91da11f8 | 430 | }; |
3d825ede BH |
431 | |
432 | MODULE_ALIAS("platform:mv88e6123"); | |
433 | MODULE_ALIAS("platform:mv88e6161"); | |
434 | MODULE_ALIAS("platform:mv88e6165"); |