Commit | Line | Data |
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2e5f0320 | 1 | /* |
076d3e10 LB |
2 | * net/dsa/mv88e6131.c - Marvell 88e6095/6095f/6131 switch chip support |
3 | * Copyright (c) 2008-2009 Marvell Semiconductor | |
2e5f0320 LB |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation; either version 2 of the License, or | |
8 | * (at your option) any later version. | |
9 | */ | |
10 | ||
19b2f97e BG |
11 | #include <linux/delay.h> |
12 | #include <linux/jiffies.h> | |
2e5f0320 | 13 | #include <linux/list.h> |
2bbba277 | 14 | #include <linux/module.h> |
2e5f0320 LB |
15 | #include <linux/netdevice.h> |
16 | #include <linux/phy.h> | |
c8f0b869 | 17 | #include <net/dsa.h> |
2e5f0320 LB |
18 | #include "mv88e6xxx.h" |
19 | ||
b9b37713 VD |
20 | static const struct mv88e6xxx_switch_id mv88e6131_table[] = { |
21 | { PORT_SWITCH_ID_6085, "Marvell 88E6085" }, | |
22 | { PORT_SWITCH_ID_6095, "Marvell 88E6095/88E6095F" }, | |
23 | { PORT_SWITCH_ID_6131, "Marvell 88E6131" }, | |
24 | { PORT_SWITCH_ID_6131_B2, "Marvell 88E6131 (B2)" }, | |
25 | { PORT_SWITCH_ID_6185, "Marvell 88E6185" }, | |
26 | }; | |
27 | ||
b4d2394d | 28 | static char *mv88e6131_probe(struct device *host_dev, int sw_addr) |
2e5f0320 | 29 | { |
b9b37713 VD |
30 | return mv88e6xxx_lookup_name(host_dev, sw_addr, mv88e6131_table, |
31 | ARRAY_SIZE(mv88e6131_table)); | |
2e5f0320 LB |
32 | } |
33 | ||
2e5f0320 LB |
34 | static int mv88e6131_setup_global(struct dsa_switch *ds) |
35 | { | |
15966a2a | 36 | u32 upstream_port = dsa_upstream_port(ds); |
2e5f0320 | 37 | int ret; |
15966a2a | 38 | u32 reg; |
54d792f2 AL |
39 | |
40 | ret = mv88e6xxx_setup_global(ds); | |
41 | if (ret) | |
42 | return ret; | |
2e5f0320 | 43 | |
3675c8d7 | 44 | /* Enable the PHY polling unit, don't discard packets with |
2e5f0320 LB |
45 | * excessive collisions, use a weighted fair queueing scheme |
46 | * to arbitrate between packet queues, set the maximum frame | |
47 | * size to 1632, and mask all interrupt sources. | |
48 | */ | |
15966a2a AL |
49 | REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL, |
50 | GLOBAL_CONTROL_PPU_ENABLE | GLOBAL_CONTROL_MAX_FRAME_1632); | |
2e5f0320 | 51 | |
3675c8d7 | 52 | /* Set the VLAN ethertype to 0x8100. */ |
15966a2a | 53 | REG_WRITE(REG_GLOBAL, GLOBAL_CORE_TAG_TYPE, 0x8100); |
2e5f0320 | 54 | |
3675c8d7 | 55 | /* Disable ARP mirroring, and configure the upstream port as |
e84665c9 LB |
56 | * the port to which ingress and egress monitor frames are to |
57 | * be sent. | |
2e5f0320 | 58 | */ |
15966a2a AL |
59 | reg = upstream_port << GLOBAL_MONITOR_CONTROL_INGRESS_SHIFT | |
60 | upstream_port << GLOBAL_MONITOR_CONTROL_EGRESS_SHIFT | | |
61 | GLOBAL_MONITOR_CONTROL_ARP_DISABLED; | |
62 | REG_WRITE(REG_GLOBAL, GLOBAL_MONITOR_CONTROL, reg); | |
2e5f0320 | 63 | |
3675c8d7 | 64 | /* Disable cascade port functionality unless this device |
81399ec6 | 65 | * is used in a cascade configuration, and set the switch's |
e84665c9 | 66 | * DSA device number. |
2e5f0320 | 67 | */ |
81399ec6 | 68 | if (ds->dst->pd->nr_chips > 1) |
15966a2a AL |
69 | REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL_2, |
70 | GLOBAL_CONTROL_2_MULTIPLE_CASCADE | | |
71 | (ds->index & 0x1f)); | |
81399ec6 | 72 | else |
15966a2a AL |
73 | REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL_2, |
74 | GLOBAL_CONTROL_2_NO_CASCADE | | |
75 | (ds->index & 0x1f)); | |
2e5f0320 | 76 | |
3675c8d7 | 77 | /* Force the priority of IGMP/MLD snoop frames and ARP frames |
2e5f0320 LB |
78 | * to the highest setting. |
79 | */ | |
15966a2a AL |
80 | REG_WRITE(REG_GLOBAL2, GLOBAL2_PRIO_OVERRIDE, |
81 | GLOBAL2_PRIO_OVERRIDE_FORCE_SNOOP | | |
82 | 7 << GLOBAL2_PRIO_OVERRIDE_SNOOP_SHIFT | | |
83 | GLOBAL2_PRIO_OVERRIDE_FORCE_ARP | | |
84 | 7 << GLOBAL2_PRIO_OVERRIDE_ARP_SHIFT); | |
2e5f0320 LB |
85 | |
86 | return 0; | |
87 | } | |
88 | ||
2e5f0320 LB |
89 | static int mv88e6131_setup(struct dsa_switch *ds) |
90 | { | |
d198893e | 91 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); |
2e5f0320 LB |
92 | int ret; |
93 | ||
0d65da4a GR |
94 | ret = mv88e6xxx_setup_common(ds); |
95 | if (ret < 0) | |
96 | return ret; | |
2e5f0320 | 97 | |
0d65da4a | 98 | mv88e6xxx_ppu_state_init(ds); |
ec80bfcb | 99 | |
d198893e | 100 | switch (ps->id) { |
cca8b133 | 101 | case PORT_SWITCH_ID_6085: |
1441f4e5 | 102 | case PORT_SWITCH_ID_6185: |
d198893e GR |
103 | ps->num_ports = 10; |
104 | break; | |
cca8b133 | 105 | case PORT_SWITCH_ID_6095: |
d198893e GR |
106 | ps->num_ports = 11; |
107 | break; | |
cca8b133 AL |
108 | case PORT_SWITCH_ID_6131: |
109 | case PORT_SWITCH_ID_6131_B2: | |
d198893e GR |
110 | ps->num_ports = 8; |
111 | break; | |
112 | default: | |
113 | return -ENODEV; | |
114 | } | |
115 | ||
143a8307 | 116 | ret = mv88e6xxx_switch_reset(ds, false); |
2e5f0320 LB |
117 | if (ret < 0) |
118 | return ret; | |
119 | ||
2e5f0320 LB |
120 | ret = mv88e6131_setup_global(ds); |
121 | if (ret < 0) | |
122 | return ret; | |
123 | ||
dbde9e66 | 124 | return mv88e6xxx_setup_ports(ds); |
2e5f0320 LB |
125 | } |
126 | ||
d198893e | 127 | static int mv88e6131_port_to_phy_addr(struct dsa_switch *ds, int port) |
2e5f0320 | 128 | { |
d198893e GR |
129 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); |
130 | ||
131 | if (port >= 0 && port < ps->num_ports) | |
2e5f0320 | 132 | return port; |
d198893e GR |
133 | |
134 | return -EINVAL; | |
2e5f0320 LB |
135 | } |
136 | ||
137 | static int | |
138 | mv88e6131_phy_read(struct dsa_switch *ds, int port, int regnum) | |
139 | { | |
d198893e GR |
140 | int addr = mv88e6131_port_to_phy_addr(ds, port); |
141 | ||
142 | if (addr < 0) | |
143 | return addr; | |
144 | ||
2e5f0320 LB |
145 | return mv88e6xxx_phy_read_ppu(ds, addr, regnum); |
146 | } | |
147 | ||
148 | static int | |
149 | mv88e6131_phy_write(struct dsa_switch *ds, | |
150 | int port, int regnum, u16 val) | |
151 | { | |
d198893e GR |
152 | int addr = mv88e6131_port_to_phy_addr(ds, port); |
153 | ||
154 | if (addr < 0) | |
155 | return addr; | |
156 | ||
2e5f0320 LB |
157 | return mv88e6xxx_phy_write_ppu(ds, addr, regnum, val); |
158 | } | |
159 | ||
98e67308 | 160 | struct dsa_switch_driver mv88e6131_switch_driver = { |
ac7a04c3 | 161 | .tag_protocol = DSA_TAG_PROTO_DSA, |
2e5f0320 LB |
162 | .priv_size = sizeof(struct mv88e6xxx_priv_state), |
163 | .probe = mv88e6131_probe, | |
164 | .setup = mv88e6131_setup, | |
165 | .set_addr = mv88e6xxx_set_addr_direct, | |
166 | .phy_read = mv88e6131_phy_read, | |
167 | .phy_write = mv88e6131_phy_write, | |
e413e7e1 AL |
168 | .get_strings = mv88e6xxx_get_strings, |
169 | .get_ethtool_stats = mv88e6xxx_get_ethtool_stats, | |
170 | .get_sset_count = mv88e6xxx_get_sset_count, | |
dea87024 | 171 | .adjust_link = mv88e6xxx_adjust_link, |
2e5f0320 | 172 | }; |
3d825ede BH |
173 | |
174 | MODULE_ALIAS("platform:mv88e6085"); | |
175 | MODULE_ALIAS("platform:mv88e6095"); | |
176 | MODULE_ALIAS("platform:mv88e6095f"); | |
177 | MODULE_ALIAS("platform:mv88e6131"); |