Commit | Line | Data |
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2e5f0320 | 1 | /* |
076d3e10 LB |
2 | * net/dsa/mv88e6131.c - Marvell 88e6095/6095f/6131 switch chip support |
3 | * Copyright (c) 2008-2009 Marvell Semiconductor | |
2e5f0320 LB |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation; either version 2 of the License, or | |
8 | * (at your option) any later version. | |
9 | */ | |
10 | ||
19b2f97e BG |
11 | #include <linux/delay.h> |
12 | #include <linux/jiffies.h> | |
2e5f0320 | 13 | #include <linux/list.h> |
2bbba277 | 14 | #include <linux/module.h> |
2e5f0320 LB |
15 | #include <linux/netdevice.h> |
16 | #include <linux/phy.h> | |
c8f0b869 | 17 | #include <net/dsa.h> |
2e5f0320 LB |
18 | #include "mv88e6xxx.h" |
19 | ||
b9b37713 VD |
20 | static const struct mv88e6xxx_switch_id mv88e6131_table[] = { |
21 | { PORT_SWITCH_ID_6085, "Marvell 88E6085" }, | |
22 | { PORT_SWITCH_ID_6095, "Marvell 88E6095/88E6095F" }, | |
23 | { PORT_SWITCH_ID_6131, "Marvell 88E6131" }, | |
24 | { PORT_SWITCH_ID_6131_B2, "Marvell 88E6131 (B2)" }, | |
25 | { PORT_SWITCH_ID_6185, "Marvell 88E6185" }, | |
26 | }; | |
27 | ||
e49bad31 AL |
28 | static char *mv88e6131_drv_probe(struct device *dsa_dev, |
29 | struct device *host_dev, | |
30 | int sw_addr, void **priv) | |
2e5f0320 | 31 | { |
a77d43f1 AL |
32 | return mv88e6xxx_drv_probe(dsa_dev, host_dev, sw_addr, priv, |
33 | mv88e6131_table, | |
34 | ARRAY_SIZE(mv88e6131_table)); | |
2e5f0320 LB |
35 | } |
36 | ||
2e5f0320 LB |
37 | static int mv88e6131_setup_global(struct dsa_switch *ds) |
38 | { | |
15966a2a | 39 | u32 upstream_port = dsa_upstream_port(ds); |
2e5f0320 | 40 | int ret; |
15966a2a | 41 | u32 reg; |
54d792f2 AL |
42 | |
43 | ret = mv88e6xxx_setup_global(ds); | |
44 | if (ret) | |
45 | return ret; | |
2e5f0320 | 46 | |
3675c8d7 | 47 | /* Enable the PHY polling unit, don't discard packets with |
2e5f0320 LB |
48 | * excessive collisions, use a weighted fair queueing scheme |
49 | * to arbitrate between packet queues, set the maximum frame | |
50 | * size to 1632, and mask all interrupt sources. | |
51 | */ | |
15966a2a AL |
52 | REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL, |
53 | GLOBAL_CONTROL_PPU_ENABLE | GLOBAL_CONTROL_MAX_FRAME_1632); | |
2e5f0320 | 54 | |
3675c8d7 | 55 | /* Set the VLAN ethertype to 0x8100. */ |
15966a2a | 56 | REG_WRITE(REG_GLOBAL, GLOBAL_CORE_TAG_TYPE, 0x8100); |
2e5f0320 | 57 | |
3675c8d7 | 58 | /* Disable ARP mirroring, and configure the upstream port as |
e84665c9 LB |
59 | * the port to which ingress and egress monitor frames are to |
60 | * be sent. | |
2e5f0320 | 61 | */ |
15966a2a AL |
62 | reg = upstream_port << GLOBAL_MONITOR_CONTROL_INGRESS_SHIFT | |
63 | upstream_port << GLOBAL_MONITOR_CONTROL_EGRESS_SHIFT | | |
64 | GLOBAL_MONITOR_CONTROL_ARP_DISABLED; | |
65 | REG_WRITE(REG_GLOBAL, GLOBAL_MONITOR_CONTROL, reg); | |
2e5f0320 | 66 | |
3675c8d7 | 67 | /* Disable cascade port functionality unless this device |
81399ec6 | 68 | * is used in a cascade configuration, and set the switch's |
e84665c9 | 69 | * DSA device number. |
2e5f0320 | 70 | */ |
81399ec6 | 71 | if (ds->dst->pd->nr_chips > 1) |
15966a2a AL |
72 | REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL_2, |
73 | GLOBAL_CONTROL_2_MULTIPLE_CASCADE | | |
74 | (ds->index & 0x1f)); | |
81399ec6 | 75 | else |
15966a2a AL |
76 | REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL_2, |
77 | GLOBAL_CONTROL_2_NO_CASCADE | | |
78 | (ds->index & 0x1f)); | |
2e5f0320 | 79 | |
3675c8d7 | 80 | /* Force the priority of IGMP/MLD snoop frames and ARP frames |
2e5f0320 LB |
81 | * to the highest setting. |
82 | */ | |
15966a2a AL |
83 | REG_WRITE(REG_GLOBAL2, GLOBAL2_PRIO_OVERRIDE, |
84 | GLOBAL2_PRIO_OVERRIDE_FORCE_SNOOP | | |
85 | 7 << GLOBAL2_PRIO_OVERRIDE_SNOOP_SHIFT | | |
86 | GLOBAL2_PRIO_OVERRIDE_FORCE_ARP | | |
87 | 7 << GLOBAL2_PRIO_OVERRIDE_ARP_SHIFT); | |
2e5f0320 LB |
88 | |
89 | return 0; | |
90 | } | |
91 | ||
2e5f0320 LB |
92 | static int mv88e6131_setup(struct dsa_switch *ds) |
93 | { | |
d198893e | 94 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); |
2e5f0320 LB |
95 | int ret; |
96 | ||
7543a6d5 AL |
97 | ps->ds = ds; |
98 | ||
0d65da4a GR |
99 | ret = mv88e6xxx_setup_common(ds); |
100 | if (ret < 0) | |
101 | return ret; | |
2e5f0320 | 102 | |
0d65da4a | 103 | mv88e6xxx_ppu_state_init(ds); |
ec80bfcb | 104 | |
d198893e | 105 | switch (ps->id) { |
cca8b133 | 106 | case PORT_SWITCH_ID_6085: |
1441f4e5 | 107 | case PORT_SWITCH_ID_6185: |
d198893e GR |
108 | ps->num_ports = 10; |
109 | break; | |
cca8b133 | 110 | case PORT_SWITCH_ID_6095: |
d198893e GR |
111 | ps->num_ports = 11; |
112 | break; | |
cca8b133 AL |
113 | case PORT_SWITCH_ID_6131: |
114 | case PORT_SWITCH_ID_6131_B2: | |
d198893e GR |
115 | ps->num_ports = 8; |
116 | break; | |
117 | default: | |
118 | return -ENODEV; | |
119 | } | |
120 | ||
143a8307 | 121 | ret = mv88e6xxx_switch_reset(ds, false); |
2e5f0320 LB |
122 | if (ret < 0) |
123 | return ret; | |
124 | ||
2e5f0320 LB |
125 | ret = mv88e6131_setup_global(ds); |
126 | if (ret < 0) | |
127 | return ret; | |
128 | ||
dbde9e66 | 129 | return mv88e6xxx_setup_ports(ds); |
2e5f0320 LB |
130 | } |
131 | ||
d198893e | 132 | static int mv88e6131_port_to_phy_addr(struct dsa_switch *ds, int port) |
2e5f0320 | 133 | { |
d198893e GR |
134 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); |
135 | ||
136 | if (port >= 0 && port < ps->num_ports) | |
2e5f0320 | 137 | return port; |
d198893e GR |
138 | |
139 | return -EINVAL; | |
2e5f0320 LB |
140 | } |
141 | ||
142 | static int | |
143 | mv88e6131_phy_read(struct dsa_switch *ds, int port, int regnum) | |
144 | { | |
d198893e GR |
145 | int addr = mv88e6131_port_to_phy_addr(ds, port); |
146 | ||
147 | if (addr < 0) | |
148 | return addr; | |
149 | ||
2e5f0320 LB |
150 | return mv88e6xxx_phy_read_ppu(ds, addr, regnum); |
151 | } | |
152 | ||
153 | static int | |
154 | mv88e6131_phy_write(struct dsa_switch *ds, | |
155 | int port, int regnum, u16 val) | |
156 | { | |
d198893e GR |
157 | int addr = mv88e6131_port_to_phy_addr(ds, port); |
158 | ||
159 | if (addr < 0) | |
160 | return addr; | |
161 | ||
2e5f0320 LB |
162 | return mv88e6xxx_phy_write_ppu(ds, addr, regnum, val); |
163 | } | |
164 | ||
98e67308 | 165 | struct dsa_switch_driver mv88e6131_switch_driver = { |
ac7a04c3 | 166 | .tag_protocol = DSA_TAG_PROTO_DSA, |
e49bad31 | 167 | .probe = mv88e6131_drv_probe, |
2e5f0320 LB |
168 | .setup = mv88e6131_setup, |
169 | .set_addr = mv88e6xxx_set_addr_direct, | |
170 | .phy_read = mv88e6131_phy_read, | |
171 | .phy_write = mv88e6131_phy_write, | |
e413e7e1 AL |
172 | .get_strings = mv88e6xxx_get_strings, |
173 | .get_ethtool_stats = mv88e6xxx_get_ethtool_stats, | |
174 | .get_sset_count = mv88e6xxx_get_sset_count, | |
dea87024 | 175 | .adjust_link = mv88e6xxx_adjust_link, |
26892ffc VD |
176 | .port_bridge_join = mv88e6xxx_port_bridge_join, |
177 | .port_bridge_leave = mv88e6xxx_port_bridge_leave, | |
178 | .port_vlan_filtering = mv88e6xxx_port_vlan_filtering, | |
179 | .port_vlan_prepare = mv88e6xxx_port_vlan_prepare, | |
180 | .port_vlan_add = mv88e6xxx_port_vlan_add, | |
181 | .port_vlan_del = mv88e6xxx_port_vlan_del, | |
182 | .port_vlan_dump = mv88e6xxx_port_vlan_dump, | |
183 | .port_fdb_prepare = mv88e6xxx_port_fdb_prepare, | |
184 | .port_fdb_add = mv88e6xxx_port_fdb_add, | |
185 | .port_fdb_del = mv88e6xxx_port_fdb_del, | |
186 | .port_fdb_dump = mv88e6xxx_port_fdb_dump, | |
2e5f0320 | 187 | }; |
3d825ede BH |
188 | |
189 | MODULE_ALIAS("platform:mv88e6085"); | |
190 | MODULE_ALIAS("platform:mv88e6095"); | |
191 | MODULE_ALIAS("platform:mv88e6095f"); | |
192 | MODULE_ALIAS("platform:mv88e6131"); |