[deliverable/linux.git] / drivers / net / dsa / mv88e6352.c

/*
 * net/dsa/mv88e6352.c - Marvell 88e6352 switch chip support
 *
 * Copyright (c) 2014 Guenter Roeck
 *
 * Derived from mv88e6123_61_65.c
 * Copyright (c) 2008-2009 Marvell Semiconductor
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#include <linux/delay.h>
#include <linux/jiffies.h>
#include <linux/list.h>
#include <linux/module.h>
#include <linux/netdevice.h>
#include <linux/platform_device.h>
#include <linux/phy.h>
#include <net/dsa.h>
#include "mv88e6xxx.h"

static char *mv88e6352_probe(struct device *host_dev, int sw_addr)
{
	struct mii_bus *bus = dsa_host_dev_to_mii_bus(host_dev);
	int ret;

	if (bus == NULL)
		return NULL;

	ret = __mv88e6xxx_reg_read(bus, sw_addr, REG_PORT(0), PORT_SWITCH_ID);
	if (ret >= 0) {
		if ((ret & 0xfff0) == PORT_SWITCH_ID_6172)
			return "Marvell 88E6172";
		if ((ret & 0xfff0) == PORT_SWITCH_ID_6176)
			return "Marvell 88E6176";
		if (ret == PORT_SWITCH_ID_6320_A1)
			return "Marvell 88E6320 (A1)";
		if (ret == PORT_SWITCH_ID_6320_A2)
			return "Marvell 88e6320 (A2)";
		if ((ret & 0xfff0) == PORT_SWITCH_ID_6320)
			return "Marvell 88E6320";
		if (ret == PORT_SWITCH_ID_6321_A1)
			return "Marvell 88E6321 (A1)";
		if (ret == PORT_SWITCH_ID_6321_A2)
			return "Marvell 88e6321 (A2)";
		if ((ret & 0xfff0) == PORT_SWITCH_ID_6321)
			return "Marvell 88E6321";
		if (ret == PORT_SWITCH_ID_6352_A0)
			return "Marvell 88E6352 (A0)";
		if (ret == PORT_SWITCH_ID_6352_A1)
			return "Marvell 88E6352 (A1)";
		if ((ret & 0xfff0) == PORT_SWITCH_ID_6352)
			return "Marvell 88E6352";
	}

	return NULL;
}

static int mv88e6352_setup_global(struct dsa_switch *ds)
{
	u32 upstream_port = dsa_upstream_port(ds);
	int ret;
	u32 reg;

	ret = mv88e6xxx_setup_global(ds);
	if (ret)
		return ret;

	/* Discard packets with excessive collisions,
	 * mask all interrupt sources, enable PPU (bit 14, undocumented).
	 */
	REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL,
		  GLOBAL_CONTROL_PPU_ENABLE | GLOBAL_CONTROL_DISCARD_EXCESS);

	/* Configure the upstream port, and configure the upstream
	 * port as the port to which ingress and egress monitor frames
	 * are to be sent.
	 */
	reg = upstream_port << GLOBAL_MONITOR_CONTROL_INGRESS_SHIFT |
		upstream_port << GLOBAL_MONITOR_CONTROL_EGRESS_SHIFT |
		upstream_port << GLOBAL_MONITOR_CONTROL_ARP_SHIFT;
	REG_WRITE(REG_GLOBAL, GLOBAL_MONITOR_CONTROL, reg);

	/* Disable remote management for now, and set the switch's
	 * DSA device number.
	 */
	REG_WRITE(REG_GLOBAL, 0x1c, ds->index & 0x1f);

	return 0;
}

static int mv88e6352_setup(struct dsa_switch *ds)
{
	struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
	int ret;

	ret = mv88e6xxx_setup_common(ds);
	if (ret < 0)
		return ret;

	ps->num_ports = 7;

	mutex_init(&ps->eeprom_mutex);

	ret = mv88e6xxx_switch_reset(ds, true);
	if (ret < 0)
		return ret;

	ret = mv88e6352_setup_global(ds);
	if (ret < 0)
		return ret;

	return mv88e6xxx_setup_ports(ds);
}

static int mv88e6352_read_eeprom_word(struct dsa_switch *ds, int addr)
{
	struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
	int ret;

	mutex_lock(&ps->eeprom_mutex);

	ret = mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
				  GLOBAL2_EEPROM_OP_READ |
				  (addr & GLOBAL2_EEPROM_OP_ADDR_MASK));
	if (ret < 0)
		goto error;

	ret = mv88e6xxx_eeprom_busy_wait(ds);
	if (ret < 0)
		goto error;

	ret = mv88e6xxx_reg_read(ds, REG_GLOBAL2, GLOBAL2_EEPROM_DATA);
error:
	mutex_unlock(&ps->eeprom_mutex);
	return ret;
}

static int mv88e6352_get_eeprom(struct dsa_switch *ds,
				struct ethtool_eeprom *eeprom, u8 *data)
{
	int offset;
	int len;
	int ret;

	offset = eeprom->offset;
	len = eeprom->len;
	eeprom->len = 0;

	eeprom->magic = 0xc3ec4951;

	ret = mv88e6xxx_eeprom_load_wait(ds);
	if (ret < 0)
		return ret;

	if (offset & 1) {
		int word;

		word = mv88e6352_read_eeprom_word(ds, offset >> 1);
		if (word < 0)
			return word;

		*data++ = (word >> 8) & 0xff;

		offset++;
		len--;
		eeprom->len++;
	}

	while (len >= 2) {
		int word;

		word = mv88e6352_read_eeprom_word(ds, offset >> 1);
		if (word < 0)
			return word;

		*data++ = word & 0xff;
		*data++ = (word >> 8) & 0xff;

		offset += 2;
		len -= 2;
		eeprom->len += 2;
	}

	if (len) {
		int word;

		word = mv88e6352_read_eeprom_word(ds, offset >> 1);
		if (word < 0)
			return word;

		*data++ = word & 0xff;

		offset++;
		len--;
		eeprom->len++;
	}

	return 0;
}

static int mv88e6352_eeprom_is_readonly(struct dsa_switch *ds)
{
	int ret;

	ret = mv88e6xxx_reg_read(ds, REG_GLOBAL2, GLOBAL2_EEPROM_OP);
	if (ret < 0)
		return ret;

	if (!(ret & GLOBAL2_EEPROM_OP_WRITE_EN))
		return -EROFS;

	return 0;
}

static int mv88e6352_write_eeprom_word(struct dsa_switch *ds, int addr,
				       u16 data)
{
	struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
	int ret;

	mutex_lock(&ps->eeprom_mutex);

	ret = mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_EEPROM_DATA, data);
	if (ret < 0)
		goto error;

	ret = mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
				  GLOBAL2_EEPROM_OP_WRITE |
				  (addr & GLOBAL2_EEPROM_OP_ADDR_MASK));
	if (ret < 0)
		goto error;

	ret = mv88e6xxx_eeprom_busy_wait(ds);
error:
	mutex_unlock(&ps->eeprom_mutex);
	return ret;
}

static int mv88e6352_set_eeprom(struct dsa_switch *ds,
				struct ethtool_eeprom *eeprom, u8 *data)
{
	int offset;
	int ret;
	int len;

	if (eeprom->magic != 0xc3ec4951)
		return -EINVAL;

	ret = mv88e6352_eeprom_is_readonly(ds);
	if (ret)
		return ret;

	offset = eeprom->offset;
	len = eeprom->len;
	eeprom->len = 0;

	ret = mv88e6xxx_eeprom_load_wait(ds);
	if (ret < 0)
		return ret;

	if (offset & 1) {
		int word;

		word = mv88e6352_read_eeprom_word(ds, offset >> 1);
		if (word < 0)
			return word;

		word = (*data++ << 8) | (word & 0xff);

		ret = mv88e6352_write_eeprom_word(ds, offset >> 1, word);
		if (ret < 0)
			return ret;

		offset++;
		len--;
		eeprom->len++;
	}

	while (len >= 2) {
		int word;

		word = *data++;
		word |= *data++ << 8;

		ret = mv88e6352_write_eeprom_word(ds, offset >> 1, word);
		if (ret < 0)
			return ret;

		offset += 2;
		len -= 2;
		eeprom->len += 2;
	}

	if (len) {
		int word;

		word = mv88e6352_read_eeprom_word(ds, offset >> 1);
		if (word < 0)
			return word;

		word = (word & 0xff00) | *data++;

		ret = mv88e6352_write_eeprom_word(ds, offset >> 1, word);
		if (ret < 0)
			return ret;

		offset++;
		len--;
		eeprom->len++;
	}

	return 0;
}

struct dsa_switch_driver mv88e6352_switch_driver = {
	.tag_protocol		= DSA_TAG_PROTO_EDSA,
	.priv_size		= sizeof(struct mv88e6xxx_priv_state),
	.probe			= mv88e6352_probe,
	.setup			= mv88e6352_setup,
	.set_addr		= mv88e6xxx_set_addr_indirect,
	.phy_read		= mv88e6xxx_phy_read_indirect,
	.phy_write		= mv88e6xxx_phy_write_indirect,
	.get_strings		= mv88e6xxx_get_strings,
	.get_ethtool_stats	= mv88e6xxx_get_ethtool_stats,
	.get_sset_count		= mv88e6xxx_get_sset_count,
	.adjust_link		= mv88e6xxx_adjust_link,
	.set_eee		= mv88e6xxx_set_eee,
	.get_eee		= mv88e6xxx_get_eee,
#ifdef CONFIG_NET_DSA_HWMON
	.get_temp		= mv88e6xxx_get_temp,
	.get_temp_limit		= mv88e6xxx_get_temp_limit,
	.set_temp_limit		= mv88e6xxx_set_temp_limit,
	.get_temp_alarm		= mv88e6xxx_get_temp_alarm,
#endif
	.get_eeprom		= mv88e6352_get_eeprom,
	.set_eeprom		= mv88e6352_set_eeprom,
	.get_regs_len		= mv88e6xxx_get_regs_len,
	.get_regs		= mv88e6xxx_get_regs,
	.port_join_bridge	= mv88e6xxx_join_bridge,
	.port_leave_bridge	= mv88e6xxx_leave_bridge,
	.port_stp_update	= mv88e6xxx_port_stp_update,
	.port_pvid_get		= mv88e6xxx_port_pvid_get,
	.port_pvid_set		= mv88e6xxx_port_pvid_set,
	.port_vlan_add		= mv88e6xxx_port_vlan_add,
	.port_vlan_del		= mv88e6xxx_port_vlan_del,
	.vlan_getnext		= mv88e6xxx_vlan_getnext,
	.port_fdb_add		= mv88e6xxx_port_fdb_add,
	.port_fdb_del		= mv88e6xxx_port_fdb_del,
	.port_fdb_getnext	= mv88e6xxx_port_fdb_getnext,
};

MODULE_ALIAS("platform:mv88e6172");
MODULE_ALIAS("platform:mv88e6176");
MODULE_ALIAS("platform:mv88e6320");
MODULE_ALIAS("platform:mv88e6321");
MODULE_ALIAS("platform:mv88e6352");
Commit	Line	Data
3ad50cca GR	1	/*
	2	* net/dsa/mv88e6352.c - Marvell 88e6352 switch chip support
	3	*
	4	* Copyright (c) 2014 Guenter Roeck
	5	*
	6	* Derived from mv88e6123_61_65.c
	7	* Copyright (c) 2008-2009 Marvell Semiconductor
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License as published by
	11	* the Free Software Foundation; either version 2 of the License, or
	12	* (at your option) any later version.
	13	*/
	14
	15	#include <linux/delay.h>
	16	#include <linux/jiffies.h>
	17	#include <linux/list.h>
	18	#include <linux/module.h>
	19	#include <linux/netdevice.h>
	20	#include <linux/platform_device.h>
	21	#include <linux/phy.h>
	22	#include <net/dsa.h>
	23	#include "mv88e6xxx.h"
	24
3ad50cca GR	25	static char mv88e6352_probe(struct device host_dev, int sw_addr)
	26	{
	27	struct mii_bus *bus = dsa_host_dev_to_mii_bus(host_dev);
	28	int ret;
	29
	30	if (bus == NULL)
	31	return NULL;
	32
cca8b133	33	ret = __mv88e6xxx_reg_read(bus, sw_addr, REG_PORT(0), PORT_SWITCH_ID);
3ad50cca	34	if (ret >= 0) {
1636d883 AL	35	if ((ret & 0xfff0) == PORT_SWITCH_ID_6172)
1636d883 AL	36	return "Marvell 88E6172";
cca8b133	37	if ((ret & 0xfff0) == PORT_SWITCH_ID_6176)
2716777b	38	return "Marvell 88E6176";
7c3d0d67 AK	39	if (ret == PORT_SWITCH_ID_6320_A1)
	40	return "Marvell 88E6320 (A1)";
	41	if (ret == PORT_SWITCH_ID_6320_A2)
	42	return "Marvell 88e6320 (A2)";
	43	if ((ret & 0xfff0) == PORT_SWITCH_ID_6320)
	44	return "Marvell 88E6320";
	45	if (ret == PORT_SWITCH_ID_6321_A1)
	46	return "Marvell 88E6321 (A1)";
	47	if (ret == PORT_SWITCH_ID_6321_A2)
	48	return "Marvell 88e6321 (A2)";
	49	if ((ret & 0xfff0) == PORT_SWITCH_ID_6321)
	50	return "Marvell 88E6321";
cca8b133	51	if (ret == PORT_SWITCH_ID_6352_A0)
3ad50cca	52	return "Marvell 88E6352 (A0)";
cca8b133	53	if (ret == PORT_SWITCH_ID_6352_A1)
3ad50cca	54	return "Marvell 88E6352 (A1)";
cca8b133	55	if ((ret & 0xfff0) == PORT_SWITCH_ID_6352)
3ad50cca GR	56	return "Marvell 88E6352";
	57	}
	58
	59	return NULL;
	60	}
	61
3ad50cca GR	62	static int mv88e6352_setup_global(struct dsa_switch *ds)
3ad50cca GR	63	{
15966a2a	64	u32 upstream_port = dsa_upstream_port(ds);
3ad50cca	65	int ret;
15966a2a	66	u32 reg;
54d792f2 AL	67
	68	ret = mv88e6xxx_setup_global(ds);
	69	if (ret)
	70	return ret;
3ad50cca GR	71
	72	/* Discard packets with excessive collisions,
	73	* mask all interrupt sources, enable PPU (bit 14, undocumented).
	74	*/
15966a2a AL	75	REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL,
15966a2a AL	76	GLOBAL_CONTROL_PPU_ENABLE \| GLOBAL_CONTROL_DISCARD_EXCESS);
3ad50cca	77
3ad50cca GR	78	/* Configure the upstream port, and configure the upstream
	79	* port as the port to which ingress and egress monitor frames
	80	* are to be sent.
	81	*/
15966a2a AL	82	reg = upstream_port << GLOBAL_MONITOR_CONTROL_INGRESS_SHIFT \|
	83	upstream_port << GLOBAL_MONITOR_CONTROL_EGRESS_SHIFT \|
	84	upstream_port << GLOBAL_MONITOR_CONTROL_ARP_SHIFT;
	85	REG_WRITE(REG_GLOBAL, GLOBAL_MONITOR_CONTROL, reg);
3ad50cca GR	86
	87	/* Disable remote management for now, and set the switch's
	88	* DSA device number.
	89	*/
	90	REG_WRITE(REG_GLOBAL, 0x1c, ds->index & 0x1f);
	91
3ad50cca GR	92	return 0;
	93	}
	94
3ad50cca GR	95	static int mv88e6352_setup(struct dsa_switch *ds)
	96	{
	97	struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
	98	int ret;
3ad50cca	99
acdaffcc GR	100	ret = mv88e6xxx_setup_common(ds);
	101	if (ret < 0)
	102	return ret;
	103
44e50ddb AL	104	ps->num_ports = 7;
44e50ddb AL	105
33b43df4	106	mutex_init(&ps->eeprom_mutex);
3ad50cca	107
143a8307	108	ret = mv88e6xxx_switch_reset(ds, true);
3ad50cca GR	109	if (ret < 0)
	110	return ret;
	111
3ad50cca GR	112	ret = mv88e6352_setup_global(ds);
	113	if (ret < 0)
	114	return ret;
	115
dbde9e66	116	return mv88e6xxx_setup_ports(ds);
3ad50cca GR	117	}
3ad50cca GR	118
33b43df4 GR	119	static int mv88e6352_read_eeprom_word(struct dsa_switch *ds, int addr)
	120	{
	121	struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
	122	int ret;
	123
	124	mutex_lock(&ps->eeprom_mutex);
	125
966bce38 AL	126	ret = mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
	127	GLOBAL2_EEPROM_OP_READ \|
	128	(addr & GLOBAL2_EEPROM_OP_ADDR_MASK));
33b43df4 GR	129	if (ret < 0)
	130	goto error;
	131
f3044683	132	ret = mv88e6xxx_eeprom_busy_wait(ds);
33b43df4 GR	133	if (ret < 0)
	134	goto error;
	135
966bce38	136	ret = mv88e6xxx_reg_read(ds, REG_GLOBAL2, GLOBAL2_EEPROM_DATA);
33b43df4 GR	137	error:
	138	mutex_unlock(&ps->eeprom_mutex);
	139	return ret;
	140	}
	141
	142	static int mv88e6352_get_eeprom(struct dsa_switch *ds,
	143	struct ethtool_eeprom eeprom, u8 data)
	144	{
	145	int offset;
	146	int len;
	147	int ret;
	148
	149	offset = eeprom->offset;
	150	len = eeprom->len;
	151	eeprom->len = 0;
	152
	153	eeprom->magic = 0xc3ec4951;
	154
f3044683	155	ret = mv88e6xxx_eeprom_load_wait(ds);
33b43df4 GR	156	if (ret < 0)
	157	return ret;
	158
	159	if (offset & 1) {
	160	int word;
	161
	162	word = mv88e6352_read_eeprom_word(ds, offset >> 1);
	163	if (word < 0)
	164	return word;
	165
	166	*data++ = (word >> 8) & 0xff;
	167
	168	offset++;
	169	len--;
	170	eeprom->len++;
	171	}
	172
	173	while (len >= 2) {
	174	int word;
	175
	176	word = mv88e6352_read_eeprom_word(ds, offset >> 1);
	177	if (word < 0)
	178	return word;
	179
	180	*data++ = word & 0xff;
	181	*data++ = (word >> 8) & 0xff;
	182
	183	offset += 2;
	184	len -= 2;
	185	eeprom->len += 2;
	186	}
	187
	188	if (len) {
	189	int word;
	190
	191	word = mv88e6352_read_eeprom_word(ds, offset >> 1);
	192	if (word < 0)
	193	return word;
	194
	195	*data++ = word & 0xff;
	196
	197	offset++;
	198	len--;
	199	eeprom->len++;
	200	}
	201
	202	return 0;
	203	}
	204
	205	static int mv88e6352_eeprom_is_readonly(struct dsa_switch *ds)
	206	{
	207	int ret;
	208
966bce38	209	ret = mv88e6xxx_reg_read(ds, REG_GLOBAL2, GLOBAL2_EEPROM_OP);
33b43df4 GR	210	if (ret < 0)
	211	return ret;
	212
966bce38	213	if (!(ret & GLOBAL2_EEPROM_OP_WRITE_EN))
33b43df4 GR	214	return -EROFS;
	215
	216	return 0;
	217	}
	218
	219	static int mv88e6352_write_eeprom_word(struct dsa_switch *ds, int addr,
	220	u16 data)
	221	{
	222	struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
	223	int ret;
	224
	225	mutex_lock(&ps->eeprom_mutex);
	226
966bce38	227	ret = mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_EEPROM_DATA, data);
33b43df4 GR	228	if (ret < 0)
	229	goto error;
	230
966bce38 AL	231	ret = mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
	232	GLOBAL2_EEPROM_OP_WRITE \|
	233	(addr & GLOBAL2_EEPROM_OP_ADDR_MASK));
33b43df4 GR	234	if (ret < 0)
	235	goto error;
	236
f3044683	237	ret = mv88e6xxx_eeprom_busy_wait(ds);
33b43df4 GR	238	error:
	239	mutex_unlock(&ps->eeprom_mutex);
	240	return ret;
	241	}
	242
	243	static int mv88e6352_set_eeprom(struct dsa_switch *ds,
	244	struct ethtool_eeprom eeprom, u8 data)
	245	{
	246	int offset;
	247	int ret;
	248	int len;
	249
	250	if (eeprom->magic != 0xc3ec4951)
	251	return -EINVAL;
	252
	253	ret = mv88e6352_eeprom_is_readonly(ds);
	254	if (ret)
	255	return ret;
	256
	257	offset = eeprom->offset;
	258	len = eeprom->len;
	259	eeprom->len = 0;
	260
f3044683	261	ret = mv88e6xxx_eeprom_load_wait(ds);
33b43df4 GR	262	if (ret < 0)
	263	return ret;
	264
	265	if (offset & 1) {
	266	int word;
	267
	268	word = mv88e6352_read_eeprom_word(ds, offset >> 1);
	269	if (word < 0)
	270	return word;
	271
	272	word = (*data++ << 8) \| (word & 0xff);
	273
	274	ret = mv88e6352_write_eeprom_word(ds, offset >> 1, word);
	275	if (ret < 0)
	276	return ret;
	277
	278	offset++;
	279	len--;
	280	eeprom->len++;
	281	}
	282
	283	while (len >= 2) {
	284	int word;
	285
	286	word = *data++;
	287	word \|= *data++ << 8;
	288
	289	ret = mv88e6352_write_eeprom_word(ds, offset >> 1, word);
	290	if (ret < 0)
	291	return ret;
	292
	293	offset += 2;
	294	len -= 2;
	295	eeprom->len += 2;
	296	}
	297
	298	if (len) {
	299	int word;
	300
	301	word = mv88e6352_read_eeprom_word(ds, offset >> 1);
	302	if (word < 0)
	303	return word;
	304
	305	word = (word & 0xff00) \| *data++;
	306
	307	ret = mv88e6352_write_eeprom_word(ds, offset >> 1, word);
	308	if (ret < 0)
	309	return ret;
	310
	311	offset++;
	312	len--;
	313	eeprom->len++;
	314	}
	315
	316	return 0;
	317	}
	318
3ad50cca GR	319	struct dsa_switch_driver mv88e6352_switch_driver = {
	320	.tag_protocol = DSA_TAG_PROTO_EDSA,
	321	.priv_size = sizeof(struct mv88e6xxx_priv_state),
	322	.probe = mv88e6352_probe,
	323	.setup = mv88e6352_setup,
	324	.set_addr = mv88e6xxx_set_addr_indirect,
fd3a0ee4 AL	325	.phy_read = mv88e6xxx_phy_read_indirect,
fd3a0ee4 AL	326	.phy_write = mv88e6xxx_phy_write_indirect,
e413e7e1 AL	327	.get_strings = mv88e6xxx_get_strings,
	328	.get_ethtool_stats = mv88e6xxx_get_ethtool_stats,
	329	.get_sset_count = mv88e6xxx_get_sset_count,
dea87024	330	.adjust_link = mv88e6xxx_adjust_link,
04b0a80b GR	331	.set_eee = mv88e6xxx_set_eee,
04b0a80b GR	332	.get_eee = mv88e6xxx_get_eee,
276db3b1	333	#ifdef CONFIG_NET_DSA_HWMON
c22995c5 GR	334	.get_temp = mv88e6xxx_get_temp,
	335	.get_temp_limit = mv88e6xxx_get_temp_limit,
	336	.set_temp_limit = mv88e6xxx_set_temp_limit,
	337	.get_temp_alarm = mv88e6xxx_get_temp_alarm,
276db3b1	338	#endif
33b43df4 GR	339	.get_eeprom = mv88e6352_get_eeprom,
33b43df4 GR	340	.set_eeprom = mv88e6352_set_eeprom,
95d08b5a GR	341	.get_regs_len = mv88e6xxx_get_regs_len,
95d08b5a GR	342	.get_regs = mv88e6xxx_get_regs,
3f244abb GR	343	.port_join_bridge = mv88e6xxx_join_bridge,
	344	.port_leave_bridge = mv88e6xxx_leave_bridge,
	345	.port_stp_update = mv88e6xxx_port_stp_update,
b8fee957	346	.port_pvid_get = mv88e6xxx_port_pvid_get,
0d3b33e6 VD	347	.port_pvid_set = mv88e6xxx_port_pvid_set,
0d3b33e6 VD	348	.port_vlan_add = mv88e6xxx_port_vlan_add,
7dad08d7	349	.port_vlan_del = mv88e6xxx_port_vlan_del,
b8fee957	350	.vlan_getnext = mv88e6xxx_vlan_getnext,
2a778e1b VD	351	.port_fdb_add = mv88e6xxx_port_fdb_add,
	352	.port_fdb_del = mv88e6xxx_port_fdb_del,
	353	.port_fdb_getnext = mv88e6xxx_port_fdb_getnext,
3ad50cca GR	354	};
3ad50cca GR	355
1636d883	356	MODULE_ALIAS("platform:mv88e6172");
7c3d0d67 AK	357	MODULE_ALIAS("platform:mv88e6176");
	358	MODULE_ALIAS("platform:mv88e6320");
	359	MODULE_ALIAS("platform:mv88e6321");
	360	MODULE_ALIAS("platform:mv88e6352");