Commit | Line | Data |
---|---|---|
3ad50cca GR |
1 | /* |
2 | * net/dsa/mv88e6352.c - Marvell 88e6352 switch chip support | |
3 | * | |
4 | * Copyright (c) 2014 Guenter Roeck | |
5 | * | |
6 | * Derived from mv88e6123_61_65.c | |
7 | * Copyright (c) 2008-2009 Marvell Semiconductor | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation; either version 2 of the License, or | |
12 | * (at your option) any later version. | |
13 | */ | |
14 | ||
15 | #include <linux/delay.h> | |
16 | #include <linux/jiffies.h> | |
17 | #include <linux/list.h> | |
18 | #include <linux/module.h> | |
19 | #include <linux/netdevice.h> | |
20 | #include <linux/platform_device.h> | |
21 | #include <linux/phy.h> | |
22 | #include <net/dsa.h> | |
23 | #include "mv88e6xxx.h" | |
24 | ||
b8665c6c | 25 | static int mv88e6352_wait(struct dsa_switch *ds, int reg, int offset, u16 mask) |
3ad50cca GR |
26 | { |
27 | unsigned long timeout = jiffies + HZ / 10; | |
28 | ||
29 | while (time_before(jiffies, timeout)) { | |
30 | int ret; | |
31 | ||
b8665c6c | 32 | ret = REG_READ(reg, offset); |
33b43df4 | 33 | if (!(ret & mask)) |
3ad50cca GR |
34 | return 0; |
35 | ||
36 | usleep_range(1000, 2000); | |
37 | } | |
38 | return -ETIMEDOUT; | |
39 | } | |
40 | ||
33b43df4 GR |
41 | static inline int mv88e6352_phy_wait(struct dsa_switch *ds) |
42 | { | |
b8665c6c | 43 | return mv88e6352_wait(ds, REG_GLOBAL2, 0x18, 0x8000); |
33b43df4 GR |
44 | } |
45 | ||
46 | static inline int mv88e6352_eeprom_load_wait(struct dsa_switch *ds) | |
47 | { | |
b8665c6c | 48 | return mv88e6352_wait(ds, REG_GLOBAL2, 0x14, 0x0800); |
33b43df4 GR |
49 | } |
50 | ||
51 | static inline int mv88e6352_eeprom_busy_wait(struct dsa_switch *ds) | |
52 | { | |
b8665c6c | 53 | return mv88e6352_wait(ds, REG_GLOBAL2, 0x14, 0x8000); |
33b43df4 GR |
54 | } |
55 | ||
3ad50cca GR |
56 | static int __mv88e6352_phy_read(struct dsa_switch *ds, int addr, int regnum) |
57 | { | |
58 | int ret; | |
59 | ||
60 | REG_WRITE(REG_GLOBAL2, 0x18, 0x9800 | (addr << 5) | regnum); | |
61 | ||
62 | ret = mv88e6352_phy_wait(ds); | |
63 | if (ret < 0) | |
64 | return ret; | |
65 | ||
66 | return REG_READ(REG_GLOBAL2, 0x19); | |
67 | } | |
68 | ||
69 | static int __mv88e6352_phy_write(struct dsa_switch *ds, int addr, int regnum, | |
70 | u16 val) | |
71 | { | |
72 | REG_WRITE(REG_GLOBAL2, 0x19, val); | |
73 | REG_WRITE(REG_GLOBAL2, 0x18, 0x9400 | (addr << 5) | regnum); | |
74 | ||
75 | return mv88e6352_phy_wait(ds); | |
76 | } | |
77 | ||
78 | static char *mv88e6352_probe(struct device *host_dev, int sw_addr) | |
79 | { | |
80 | struct mii_bus *bus = dsa_host_dev_to_mii_bus(host_dev); | |
81 | int ret; | |
82 | ||
83 | if (bus == NULL) | |
84 | return NULL; | |
85 | ||
86 | ret = __mv88e6xxx_reg_read(bus, sw_addr, REG_PORT(0), 0x03); | |
87 | if (ret >= 0) { | |
2716777b GR |
88 | if ((ret & 0xfff0) == 0x1760) |
89 | return "Marvell 88E6176"; | |
3ad50cca GR |
90 | if (ret == 0x3521) |
91 | return "Marvell 88E6352 (A0)"; | |
92 | if (ret == 0x3522) | |
93 | return "Marvell 88E6352 (A1)"; | |
94 | if ((ret & 0xfff0) == 0x3520) | |
95 | return "Marvell 88E6352"; | |
96 | } | |
97 | ||
98 | return NULL; | |
99 | } | |
100 | ||
101 | static int mv88e6352_switch_reset(struct dsa_switch *ds) | |
102 | { | |
103 | unsigned long timeout; | |
104 | int ret; | |
105 | int i; | |
106 | ||
107 | /* Set all ports to the disabled state. */ | |
108 | for (i = 0; i < 7; i++) { | |
109 | ret = REG_READ(REG_PORT(i), 0x04); | |
110 | REG_WRITE(REG_PORT(i), 0x04, ret & 0xfffc); | |
111 | } | |
112 | ||
113 | /* Wait for transmit queues to drain. */ | |
114 | usleep_range(2000, 4000); | |
115 | ||
116 | /* Reset the switch. Keep PPU active (bit 14, undocumented). | |
117 | * The PPU needs to be active to support indirect phy register | |
118 | * accesses through global registers 0x18 and 0x19. | |
119 | */ | |
120 | REG_WRITE(REG_GLOBAL, 0x04, 0xc000); | |
121 | ||
122 | /* Wait up to one second for reset to complete. */ | |
123 | timeout = jiffies + 1 * HZ; | |
124 | while (time_before(jiffies, timeout)) { | |
125 | ret = REG_READ(REG_GLOBAL, 0x00); | |
126 | if ((ret & 0x8800) == 0x8800) | |
127 | break; | |
128 | usleep_range(1000, 2000); | |
129 | } | |
130 | if (time_after(jiffies, timeout)) | |
131 | return -ETIMEDOUT; | |
132 | ||
133 | return 0; | |
134 | } | |
135 | ||
136 | static int mv88e6352_setup_global(struct dsa_switch *ds) | |
137 | { | |
138 | int ret; | |
139 | int i; | |
140 | ||
141 | /* Discard packets with excessive collisions, | |
142 | * mask all interrupt sources, enable PPU (bit 14, undocumented). | |
143 | */ | |
144 | REG_WRITE(REG_GLOBAL, 0x04, 0x6000); | |
145 | ||
146 | /* Set the default address aging time to 5 minutes, and | |
147 | * enable address learn messages to be sent to all message | |
148 | * ports. | |
149 | */ | |
150 | REG_WRITE(REG_GLOBAL, 0x0a, 0x0148); | |
151 | ||
152 | /* Configure the priority mapping registers. */ | |
153 | ret = mv88e6xxx_config_prio(ds); | |
154 | if (ret < 0) | |
155 | return ret; | |
156 | ||
157 | /* Configure the upstream port, and configure the upstream | |
158 | * port as the port to which ingress and egress monitor frames | |
159 | * are to be sent. | |
160 | */ | |
161 | REG_WRITE(REG_GLOBAL, 0x1a, (dsa_upstream_port(ds) * 0x1110)); | |
162 | ||
163 | /* Disable remote management for now, and set the switch's | |
164 | * DSA device number. | |
165 | */ | |
166 | REG_WRITE(REG_GLOBAL, 0x1c, ds->index & 0x1f); | |
167 | ||
168 | /* Send all frames with destination addresses matching | |
169 | * 01:80:c2:00:00:2x to the CPU port. | |
170 | */ | |
171 | REG_WRITE(REG_GLOBAL2, 0x02, 0xffff); | |
172 | ||
173 | /* Send all frames with destination addresses matching | |
174 | * 01:80:c2:00:00:0x to the CPU port. | |
175 | */ | |
176 | REG_WRITE(REG_GLOBAL2, 0x03, 0xffff); | |
177 | ||
178 | /* Disable the loopback filter, disable flow control | |
179 | * messages, disable flood broadcast override, disable | |
180 | * removing of provider tags, disable ATU age violation | |
181 | * interrupts, disable tag flow control, force flow | |
182 | * control priority to the highest, and send all special | |
183 | * multicast frames to the CPU at the highest priority. | |
184 | */ | |
185 | REG_WRITE(REG_GLOBAL2, 0x05, 0x00ff); | |
186 | ||
187 | /* Program the DSA routing table. */ | |
188 | for (i = 0; i < 32; i++) { | |
189 | int nexthop = 0x1f; | |
190 | ||
191 | if (i != ds->index && i < ds->dst->pd->nr_chips) | |
192 | nexthop = ds->pd->rtable[i] & 0x1f; | |
193 | ||
194 | REG_WRITE(REG_GLOBAL2, 0x06, 0x8000 | (i << 8) | nexthop); | |
195 | } | |
196 | ||
197 | /* Clear all trunk masks. */ | |
198 | for (i = 0; i < 8; i++) | |
199 | REG_WRITE(REG_GLOBAL2, 0x07, 0x8000 | (i << 12) | 0x7f); | |
200 | ||
201 | /* Clear all trunk mappings. */ | |
202 | for (i = 0; i < 16; i++) | |
203 | REG_WRITE(REG_GLOBAL2, 0x08, 0x8000 | (i << 11)); | |
204 | ||
205 | /* Disable ingress rate limiting by resetting all ingress | |
206 | * rate limit registers to their initial state. | |
207 | */ | |
208 | for (i = 0; i < 7; i++) | |
209 | REG_WRITE(REG_GLOBAL2, 0x09, 0x9000 | (i << 8)); | |
210 | ||
211 | /* Initialise cross-chip port VLAN table to reset defaults. */ | |
212 | REG_WRITE(REG_GLOBAL2, 0x0b, 0x9000); | |
213 | ||
214 | /* Clear the priority override table. */ | |
215 | for (i = 0; i < 16; i++) | |
216 | REG_WRITE(REG_GLOBAL2, 0x0f, 0x8000 | (i << 8)); | |
217 | ||
218 | /* @@@ initialise AVB (22/23) watchdog (27) sdet (29) registers */ | |
219 | ||
220 | return 0; | |
221 | } | |
222 | ||
223 | static int mv88e6352_setup_port(struct dsa_switch *ds, int p) | |
224 | { | |
225 | int addr = REG_PORT(p); | |
226 | u16 val; | |
227 | ||
228 | /* MAC Forcing register: don't force link, speed, duplex | |
229 | * or flow control state to any particular values on physical | |
230 | * ports, but force the CPU port and all DSA ports to 1000 Mb/s | |
231 | * full duplex. | |
232 | */ | |
233 | if (dsa_is_cpu_port(ds, p) || ds->dsa_port_mask & (1 << p)) | |
234 | REG_WRITE(addr, 0x01, 0x003e); | |
235 | else | |
236 | REG_WRITE(addr, 0x01, 0x0003); | |
237 | ||
238 | /* Do not limit the period of time that this port can be | |
239 | * paused for by the remote end or the period of time that | |
240 | * this port can pause the remote end. | |
241 | */ | |
242 | REG_WRITE(addr, 0x02, 0x0000); | |
243 | ||
244 | /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock, | |
245 | * disable Header mode, enable IGMP/MLD snooping, disable VLAN | |
246 | * tunneling, determine priority by looking at 802.1p and IP | |
247 | * priority fields (IP prio has precedence), and set STP state | |
248 | * to Forwarding. | |
249 | * | |
250 | * If this is the CPU link, use DSA or EDSA tagging depending | |
251 | * on which tagging mode was configured. | |
252 | * | |
253 | * If this is a link to another switch, use DSA tagging mode. | |
254 | * | |
255 | * If this is the upstream port for this switch, enable | |
256 | * forwarding of unknown unicasts and multicasts. | |
257 | */ | |
258 | val = 0x0433; | |
259 | if (dsa_is_cpu_port(ds, p)) { | |
260 | if (ds->dst->tag_protocol == DSA_TAG_PROTO_EDSA) | |
261 | val |= 0x3300; | |
262 | else | |
263 | val |= 0x0100; | |
264 | } | |
265 | if (ds->dsa_port_mask & (1 << p)) | |
266 | val |= 0x0100; | |
267 | if (p == dsa_upstream_port(ds)) | |
268 | val |= 0x000c; | |
269 | REG_WRITE(addr, 0x04, val); | |
270 | ||
271 | /* Port Control 1: disable trunking. Also, if this is the | |
272 | * CPU port, enable learn messages to be sent to this port. | |
273 | */ | |
274 | REG_WRITE(addr, 0x05, dsa_is_cpu_port(ds, p) ? 0x8000 : 0x0000); | |
275 | ||
276 | /* Port based VLAN map: give each port its own address | |
277 | * database, allow the CPU port to talk to each of the 'real' | |
278 | * ports, and allow each of the 'real' ports to only talk to | |
279 | * the upstream port. | |
280 | */ | |
281 | val = (p & 0xf) << 12; | |
282 | if (dsa_is_cpu_port(ds, p)) | |
283 | val |= ds->phys_port_mask; | |
284 | else | |
285 | val |= 1 << dsa_upstream_port(ds); | |
286 | REG_WRITE(addr, 0x06, val); | |
287 | ||
288 | /* Default VLAN ID and priority: don't set a default VLAN | |
289 | * ID, and set the default packet priority to zero. | |
290 | */ | |
291 | REG_WRITE(addr, 0x07, 0x0000); | |
292 | ||
293 | /* Port Control 2: don't force a good FCS, set the maximum | |
294 | * frame size to 10240 bytes, don't let the switch add or | |
295 | * strip 802.1q tags, don't discard tagged or untagged frames | |
296 | * on this port, do a destination address lookup on all | |
297 | * received packets as usual, disable ARP mirroring and don't | |
298 | * send a copy of all transmitted/received frames on this port | |
299 | * to the CPU. | |
300 | */ | |
301 | REG_WRITE(addr, 0x08, 0x2080); | |
302 | ||
303 | /* Egress rate control: disable egress rate control. */ | |
304 | REG_WRITE(addr, 0x09, 0x0001); | |
305 | ||
306 | /* Egress rate control 2: disable egress rate control. */ | |
307 | REG_WRITE(addr, 0x0a, 0x0000); | |
308 | ||
309 | /* Port Association Vector: when learning source addresses | |
310 | * of packets, add the address to the address database using | |
311 | * a port bitmap that has only the bit for this port set and | |
312 | * the other bits clear. | |
313 | */ | |
314 | REG_WRITE(addr, 0x0b, 1 << p); | |
315 | ||
316 | /* Port ATU control: disable limiting the number of address | |
317 | * database entries that this port is allowed to use. | |
318 | */ | |
319 | REG_WRITE(addr, 0x0c, 0x0000); | |
320 | ||
321 | /* Priority Override: disable DA, SA and VTU priority override. */ | |
322 | REG_WRITE(addr, 0x0d, 0x0000); | |
323 | ||
324 | /* Port Ethertype: use the Ethertype DSA Ethertype value. */ | |
325 | REG_WRITE(addr, 0x0f, ETH_P_EDSA); | |
326 | ||
327 | /* Tag Remap: use an identity 802.1p prio -> switch prio | |
328 | * mapping. | |
329 | */ | |
330 | REG_WRITE(addr, 0x18, 0x3210); | |
331 | ||
332 | /* Tag Remap 2: use an identity 802.1p prio -> switch prio | |
333 | * mapping. | |
334 | */ | |
335 | REG_WRITE(addr, 0x19, 0x7654); | |
336 | ||
337 | return 0; | |
338 | } | |
339 | ||
276db3b1 GR |
340 | #ifdef CONFIG_NET_DSA_HWMON |
341 | ||
342 | static int mv88e6352_phy_page_read(struct dsa_switch *ds, | |
343 | int port, int page, int reg) | |
344 | { | |
345 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
346 | int ret; | |
347 | ||
348 | mutex_lock(&ps->phy_mutex); | |
349 | ret = __mv88e6352_phy_write(ds, port, 0x16, page); | |
350 | if (ret < 0) | |
351 | goto error; | |
352 | ret = __mv88e6352_phy_read(ds, port, reg); | |
353 | error: | |
354 | __mv88e6352_phy_write(ds, port, 0x16, 0x0); | |
355 | mutex_unlock(&ps->phy_mutex); | |
356 | return ret; | |
357 | } | |
358 | ||
359 | static int mv88e6352_phy_page_write(struct dsa_switch *ds, | |
360 | int port, int page, int reg, int val) | |
361 | { | |
362 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
363 | int ret; | |
364 | ||
365 | mutex_lock(&ps->phy_mutex); | |
366 | ret = __mv88e6352_phy_write(ds, port, 0x16, page); | |
367 | if (ret < 0) | |
368 | goto error; | |
369 | ||
370 | ret = __mv88e6352_phy_write(ds, port, reg, val); | |
371 | error: | |
372 | __mv88e6352_phy_write(ds, port, 0x16, 0x0); | |
373 | mutex_unlock(&ps->phy_mutex); | |
374 | return ret; | |
375 | } | |
376 | ||
377 | static int mv88e6352_get_temp(struct dsa_switch *ds, int *temp) | |
378 | { | |
379 | int ret; | |
380 | ||
381 | *temp = 0; | |
382 | ||
383 | ret = mv88e6352_phy_page_read(ds, 0, 6, 27); | |
384 | if (ret < 0) | |
385 | return ret; | |
386 | ||
387 | *temp = (ret & 0xff) - 25; | |
388 | ||
389 | return 0; | |
390 | } | |
391 | ||
392 | static int mv88e6352_get_temp_limit(struct dsa_switch *ds, int *temp) | |
393 | { | |
394 | int ret; | |
395 | ||
396 | *temp = 0; | |
397 | ||
398 | ret = mv88e6352_phy_page_read(ds, 0, 6, 26); | |
399 | if (ret < 0) | |
400 | return ret; | |
401 | ||
402 | *temp = (((ret >> 8) & 0x1f) * 5) - 25; | |
403 | ||
404 | return 0; | |
405 | } | |
406 | ||
407 | static int mv88e6352_set_temp_limit(struct dsa_switch *ds, int temp) | |
408 | { | |
409 | int ret; | |
410 | ||
411 | ret = mv88e6352_phy_page_read(ds, 0, 6, 26); | |
412 | if (ret < 0) | |
413 | return ret; | |
414 | temp = clamp_val(DIV_ROUND_CLOSEST(temp, 5) + 5, 0, 0x1f); | |
415 | return mv88e6352_phy_page_write(ds, 0, 6, 26, | |
416 | (ret & 0xe0ff) | (temp << 8)); | |
417 | } | |
418 | ||
419 | static int mv88e6352_get_temp_alarm(struct dsa_switch *ds, bool *alarm) | |
420 | { | |
421 | int ret; | |
422 | ||
423 | *alarm = false; | |
424 | ||
425 | ret = mv88e6352_phy_page_read(ds, 0, 6, 26); | |
426 | if (ret < 0) | |
427 | return ret; | |
428 | ||
429 | *alarm = !!(ret & 0x40); | |
430 | ||
431 | return 0; | |
432 | } | |
433 | #endif /* CONFIG_NET_DSA_HWMON */ | |
434 | ||
3ad50cca GR |
435 | static int mv88e6352_setup(struct dsa_switch *ds) |
436 | { | |
437 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
438 | int ret; | |
439 | int i; | |
440 | ||
441 | mutex_init(&ps->smi_mutex); | |
442 | mutex_init(&ps->stats_mutex); | |
443 | mutex_init(&ps->phy_mutex); | |
33b43df4 | 444 | mutex_init(&ps->eeprom_mutex); |
3ad50cca GR |
445 | |
446 | ps->id = REG_READ(REG_PORT(0), 0x03) & 0xfff0; | |
447 | ||
448 | ret = mv88e6352_switch_reset(ds); | |
449 | if (ret < 0) | |
450 | return ret; | |
451 | ||
452 | /* @@@ initialise vtu and atu */ | |
453 | ||
454 | ret = mv88e6352_setup_global(ds); | |
455 | if (ret < 0) | |
456 | return ret; | |
457 | ||
458 | for (i = 0; i < 7; i++) { | |
459 | ret = mv88e6352_setup_port(ds, i); | |
460 | if (ret < 0) | |
461 | return ret; | |
462 | } | |
463 | ||
464 | return 0; | |
465 | } | |
466 | ||
467 | static int mv88e6352_port_to_phy_addr(int port) | |
468 | { | |
469 | if (port >= 0 && port <= 4) | |
470 | return port; | |
471 | return -EINVAL; | |
472 | } | |
473 | ||
474 | static int | |
475 | mv88e6352_phy_read(struct dsa_switch *ds, int port, int regnum) | |
476 | { | |
477 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
478 | int addr = mv88e6352_port_to_phy_addr(port); | |
479 | int ret; | |
480 | ||
481 | if (addr < 0) | |
482 | return addr; | |
483 | ||
484 | mutex_lock(&ps->phy_mutex); | |
485 | ret = __mv88e6352_phy_read(ds, addr, regnum); | |
486 | mutex_unlock(&ps->phy_mutex); | |
487 | ||
488 | return ret; | |
489 | } | |
490 | ||
491 | static int | |
492 | mv88e6352_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val) | |
493 | { | |
494 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
495 | int addr = mv88e6352_port_to_phy_addr(port); | |
496 | int ret; | |
497 | ||
498 | if (addr < 0) | |
499 | return addr; | |
500 | ||
501 | mutex_lock(&ps->phy_mutex); | |
502 | ret = __mv88e6352_phy_write(ds, addr, regnum, val); | |
503 | mutex_unlock(&ps->phy_mutex); | |
504 | ||
505 | return ret; | |
506 | } | |
507 | ||
508 | static struct mv88e6xxx_hw_stat mv88e6352_hw_stats[] = { | |
509 | { "in_good_octets", 8, 0x00, }, | |
510 | { "in_bad_octets", 4, 0x02, }, | |
511 | { "in_unicast", 4, 0x04, }, | |
512 | { "in_broadcasts", 4, 0x06, }, | |
513 | { "in_multicasts", 4, 0x07, }, | |
514 | { "in_pause", 4, 0x16, }, | |
515 | { "in_undersize", 4, 0x18, }, | |
516 | { "in_fragments", 4, 0x19, }, | |
517 | { "in_oversize", 4, 0x1a, }, | |
518 | { "in_jabber", 4, 0x1b, }, | |
519 | { "in_rx_error", 4, 0x1c, }, | |
520 | { "in_fcs_error", 4, 0x1d, }, | |
521 | { "out_octets", 8, 0x0e, }, | |
522 | { "out_unicast", 4, 0x10, }, | |
523 | { "out_broadcasts", 4, 0x13, }, | |
524 | { "out_multicasts", 4, 0x12, }, | |
525 | { "out_pause", 4, 0x15, }, | |
526 | { "excessive", 4, 0x11, }, | |
527 | { "collisions", 4, 0x1e, }, | |
528 | { "deferred", 4, 0x05, }, | |
529 | { "single", 4, 0x14, }, | |
530 | { "multiple", 4, 0x17, }, | |
531 | { "out_fcs_error", 4, 0x03, }, | |
532 | { "late", 4, 0x1f, }, | |
533 | { "hist_64bytes", 4, 0x08, }, | |
534 | { "hist_65_127bytes", 4, 0x09, }, | |
535 | { "hist_128_255bytes", 4, 0x0a, }, | |
536 | { "hist_256_511bytes", 4, 0x0b, }, | |
537 | { "hist_512_1023bytes", 4, 0x0c, }, | |
538 | { "hist_1024_max_bytes", 4, 0x0d, }, | |
17ee3e04 GR |
539 | { "sw_in_discards", 4, 0x110, }, |
540 | { "sw_in_filtered", 2, 0x112, }, | |
541 | { "sw_out_filtered", 2, 0x113, }, | |
3ad50cca GR |
542 | }; |
543 | ||
33b43df4 GR |
544 | static int mv88e6352_read_eeprom_word(struct dsa_switch *ds, int addr) |
545 | { | |
546 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
547 | int ret; | |
548 | ||
549 | mutex_lock(&ps->eeprom_mutex); | |
550 | ||
551 | ret = mv88e6xxx_reg_write(ds, REG_GLOBAL2, 0x14, | |
552 | 0xc000 | (addr & 0xff)); | |
553 | if (ret < 0) | |
554 | goto error; | |
555 | ||
556 | ret = mv88e6352_eeprom_busy_wait(ds); | |
557 | if (ret < 0) | |
558 | goto error; | |
559 | ||
560 | ret = mv88e6xxx_reg_read(ds, REG_GLOBAL2, 0x15); | |
561 | error: | |
562 | mutex_unlock(&ps->eeprom_mutex); | |
563 | return ret; | |
564 | } | |
565 | ||
566 | static int mv88e6352_get_eeprom(struct dsa_switch *ds, | |
567 | struct ethtool_eeprom *eeprom, u8 *data) | |
568 | { | |
569 | int offset; | |
570 | int len; | |
571 | int ret; | |
572 | ||
573 | offset = eeprom->offset; | |
574 | len = eeprom->len; | |
575 | eeprom->len = 0; | |
576 | ||
577 | eeprom->magic = 0xc3ec4951; | |
578 | ||
579 | ret = mv88e6352_eeprom_load_wait(ds); | |
580 | if (ret < 0) | |
581 | return ret; | |
582 | ||
583 | if (offset & 1) { | |
584 | int word; | |
585 | ||
586 | word = mv88e6352_read_eeprom_word(ds, offset >> 1); | |
587 | if (word < 0) | |
588 | return word; | |
589 | ||
590 | *data++ = (word >> 8) & 0xff; | |
591 | ||
592 | offset++; | |
593 | len--; | |
594 | eeprom->len++; | |
595 | } | |
596 | ||
597 | while (len >= 2) { | |
598 | int word; | |
599 | ||
600 | word = mv88e6352_read_eeprom_word(ds, offset >> 1); | |
601 | if (word < 0) | |
602 | return word; | |
603 | ||
604 | *data++ = word & 0xff; | |
605 | *data++ = (word >> 8) & 0xff; | |
606 | ||
607 | offset += 2; | |
608 | len -= 2; | |
609 | eeprom->len += 2; | |
610 | } | |
611 | ||
612 | if (len) { | |
613 | int word; | |
614 | ||
615 | word = mv88e6352_read_eeprom_word(ds, offset >> 1); | |
616 | if (word < 0) | |
617 | return word; | |
618 | ||
619 | *data++ = word & 0xff; | |
620 | ||
621 | offset++; | |
622 | len--; | |
623 | eeprom->len++; | |
624 | } | |
625 | ||
626 | return 0; | |
627 | } | |
628 | ||
629 | static int mv88e6352_eeprom_is_readonly(struct dsa_switch *ds) | |
630 | { | |
631 | int ret; | |
632 | ||
633 | ret = mv88e6xxx_reg_read(ds, REG_GLOBAL2, 0x14); | |
634 | if (ret < 0) | |
635 | return ret; | |
636 | ||
637 | if (!(ret & 0x0400)) | |
638 | return -EROFS; | |
639 | ||
640 | return 0; | |
641 | } | |
642 | ||
643 | static int mv88e6352_write_eeprom_word(struct dsa_switch *ds, int addr, | |
644 | u16 data) | |
645 | { | |
646 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
647 | int ret; | |
648 | ||
649 | mutex_lock(&ps->eeprom_mutex); | |
650 | ||
651 | ret = mv88e6xxx_reg_write(ds, REG_GLOBAL2, 0x15, data); | |
652 | if (ret < 0) | |
653 | goto error; | |
654 | ||
655 | ret = mv88e6xxx_reg_write(ds, REG_GLOBAL2, 0x14, | |
656 | 0xb000 | (addr & 0xff)); | |
657 | if (ret < 0) | |
658 | goto error; | |
659 | ||
660 | ret = mv88e6352_eeprom_busy_wait(ds); | |
661 | error: | |
662 | mutex_unlock(&ps->eeprom_mutex); | |
663 | return ret; | |
664 | } | |
665 | ||
666 | static int mv88e6352_set_eeprom(struct dsa_switch *ds, | |
667 | struct ethtool_eeprom *eeprom, u8 *data) | |
668 | { | |
669 | int offset; | |
670 | int ret; | |
671 | int len; | |
672 | ||
673 | if (eeprom->magic != 0xc3ec4951) | |
674 | return -EINVAL; | |
675 | ||
676 | ret = mv88e6352_eeprom_is_readonly(ds); | |
677 | if (ret) | |
678 | return ret; | |
679 | ||
680 | offset = eeprom->offset; | |
681 | len = eeprom->len; | |
682 | eeprom->len = 0; | |
683 | ||
684 | ret = mv88e6352_eeprom_load_wait(ds); | |
685 | if (ret < 0) | |
686 | return ret; | |
687 | ||
688 | if (offset & 1) { | |
689 | int word; | |
690 | ||
691 | word = mv88e6352_read_eeprom_word(ds, offset >> 1); | |
692 | if (word < 0) | |
693 | return word; | |
694 | ||
695 | word = (*data++ << 8) | (word & 0xff); | |
696 | ||
697 | ret = mv88e6352_write_eeprom_word(ds, offset >> 1, word); | |
698 | if (ret < 0) | |
699 | return ret; | |
700 | ||
701 | offset++; | |
702 | len--; | |
703 | eeprom->len++; | |
704 | } | |
705 | ||
706 | while (len >= 2) { | |
707 | int word; | |
708 | ||
709 | word = *data++; | |
710 | word |= *data++ << 8; | |
711 | ||
712 | ret = mv88e6352_write_eeprom_word(ds, offset >> 1, word); | |
713 | if (ret < 0) | |
714 | return ret; | |
715 | ||
716 | offset += 2; | |
717 | len -= 2; | |
718 | eeprom->len += 2; | |
719 | } | |
720 | ||
721 | if (len) { | |
722 | int word; | |
723 | ||
724 | word = mv88e6352_read_eeprom_word(ds, offset >> 1); | |
725 | if (word < 0) | |
726 | return word; | |
727 | ||
728 | word = (word & 0xff00) | *data++; | |
729 | ||
730 | ret = mv88e6352_write_eeprom_word(ds, offset >> 1, word); | |
731 | if (ret < 0) | |
732 | return ret; | |
733 | ||
734 | offset++; | |
735 | len--; | |
736 | eeprom->len++; | |
737 | } | |
738 | ||
739 | return 0; | |
740 | } | |
741 | ||
3ad50cca GR |
742 | static void |
743 | mv88e6352_get_strings(struct dsa_switch *ds, int port, uint8_t *data) | |
744 | { | |
745 | mv88e6xxx_get_strings(ds, ARRAY_SIZE(mv88e6352_hw_stats), | |
746 | mv88e6352_hw_stats, port, data); | |
747 | } | |
748 | ||
749 | static void | |
750 | mv88e6352_get_ethtool_stats(struct dsa_switch *ds, int port, uint64_t *data) | |
751 | { | |
752 | mv88e6xxx_get_ethtool_stats(ds, ARRAY_SIZE(mv88e6352_hw_stats), | |
753 | mv88e6352_hw_stats, port, data); | |
754 | } | |
755 | ||
756 | static int mv88e6352_get_sset_count(struct dsa_switch *ds) | |
757 | { | |
758 | return ARRAY_SIZE(mv88e6352_hw_stats); | |
759 | } | |
760 | ||
761 | struct dsa_switch_driver mv88e6352_switch_driver = { | |
762 | .tag_protocol = DSA_TAG_PROTO_EDSA, | |
763 | .priv_size = sizeof(struct mv88e6xxx_priv_state), | |
764 | .probe = mv88e6352_probe, | |
765 | .setup = mv88e6352_setup, | |
766 | .set_addr = mv88e6xxx_set_addr_indirect, | |
767 | .phy_read = mv88e6352_phy_read, | |
768 | .phy_write = mv88e6352_phy_write, | |
769 | .poll_link = mv88e6xxx_poll_link, | |
770 | .get_strings = mv88e6352_get_strings, | |
771 | .get_ethtool_stats = mv88e6352_get_ethtool_stats, | |
772 | .get_sset_count = mv88e6352_get_sset_count, | |
276db3b1 GR |
773 | #ifdef CONFIG_NET_DSA_HWMON |
774 | .get_temp = mv88e6352_get_temp, | |
775 | .get_temp_limit = mv88e6352_get_temp_limit, | |
776 | .set_temp_limit = mv88e6352_set_temp_limit, | |
777 | .get_temp_alarm = mv88e6352_get_temp_alarm, | |
778 | #endif | |
33b43df4 GR |
779 | .get_eeprom = mv88e6352_get_eeprom, |
780 | .set_eeprom = mv88e6352_set_eeprom, | |
95d08b5a GR |
781 | .get_regs_len = mv88e6xxx_get_regs_len, |
782 | .get_regs = mv88e6xxx_get_regs, | |
3ad50cca GR |
783 | }; |
784 | ||
785 | MODULE_ALIAS("platform:mv88e6352"); |