[deliverable/linux.git] / drivers / net / dsa / mv88e6352.c

/*
 * net/dsa/mv88e6352.c - Marvell 88e6352 switch chip support
 *
 * Copyright (c) 2014 Guenter Roeck
 *
 * Derived from mv88e6123_61_65.c
 * Copyright (c) 2008-2009 Marvell Semiconductor
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#include <linux/delay.h>
#include <linux/jiffies.h>
#include <linux/list.h>
#include <linux/module.h>
#include <linux/netdevice.h>
#include <linux/platform_device.h>
#include <linux/phy.h>
#include <net/dsa.h>
#include "mv88e6xxx.h"

static const struct mv88e6xxx_switch_id mv88e6352_table[] = {
	{ PORT_SWITCH_ID_6172, "Marvell 88E6172" },
	{ PORT_SWITCH_ID_6176, "Marvell 88E6176" },
	{ PORT_SWITCH_ID_6240, "Marvell 88E6240" },
	{ PORT_SWITCH_ID_6320, "Marvell 88E6320" },
	{ PORT_SWITCH_ID_6320_A1, "Marvell 88E6320 (A1)" },
	{ PORT_SWITCH_ID_6320_A2, "Marvell 88e6320 (A2)" },
	{ PORT_SWITCH_ID_6321, "Marvell 88E6321" },
	{ PORT_SWITCH_ID_6321_A1, "Marvell 88E6321 (A1)" },
	{ PORT_SWITCH_ID_6321_A2, "Marvell 88e6321 (A2)" },
	{ PORT_SWITCH_ID_6352, "Marvell 88E6352" },
	{ PORT_SWITCH_ID_6352_A0, "Marvell 88E6352 (A0)" },
	{ PORT_SWITCH_ID_6352_A1, "Marvell 88E6352 (A1)" },
};

static char *mv88e6352_probe(struct device *dsa_dev, struct device *host_dev,
			     int sw_addr)
{
	return mv88e6xxx_lookup_name(host_dev, sw_addr, mv88e6352_table,
				     ARRAY_SIZE(mv88e6352_table));
}

static int mv88e6352_setup_global(struct dsa_switch *ds)
{
	u32 upstream_port = dsa_upstream_port(ds);
	int ret;
	u32 reg;

	ret = mv88e6xxx_setup_global(ds);
	if (ret)
		return ret;

	/* Discard packets with excessive collisions,
	 * mask all interrupt sources, enable PPU (bit 14, undocumented).
	 */
	REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL,
		  GLOBAL_CONTROL_PPU_ENABLE | GLOBAL_CONTROL_DISCARD_EXCESS);

	/* Configure the upstream port, and configure the upstream
	 * port as the port to which ingress and egress monitor frames
	 * are to be sent.
	 */
	reg = upstream_port << GLOBAL_MONITOR_CONTROL_INGRESS_SHIFT |
		upstream_port << GLOBAL_MONITOR_CONTROL_EGRESS_SHIFT |
		upstream_port << GLOBAL_MONITOR_CONTROL_ARP_SHIFT;
	REG_WRITE(REG_GLOBAL, GLOBAL_MONITOR_CONTROL, reg);

	/* Disable remote management for now, and set the switch's
	 * DSA device number.
	 */
	REG_WRITE(REG_GLOBAL, 0x1c, ds->index & 0x1f);

	return 0;
}

static int mv88e6352_setup(struct dsa_switch *ds)
{
	struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
	int ret;

	ret = mv88e6xxx_setup_common(ds);
	if (ret < 0)
		return ret;

	ps->num_ports = 7;

	mutex_init(&ps->eeprom_mutex);

	ret = mv88e6xxx_switch_reset(ds, true);
	if (ret < 0)
		return ret;

	ret = mv88e6352_setup_global(ds);
	if (ret < 0)
		return ret;

	return mv88e6xxx_setup_ports(ds);
}

static int mv88e6352_read_eeprom_word(struct dsa_switch *ds, int addr)
{
	struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
	int ret;

	mutex_lock(&ps->eeprom_mutex);

	ret = mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
				  GLOBAL2_EEPROM_OP_READ |
				  (addr & GLOBAL2_EEPROM_OP_ADDR_MASK));
	if (ret < 0)
		goto error;

	ret = mv88e6xxx_eeprom_busy_wait(ds);
	if (ret < 0)
		goto error;

	ret = mv88e6xxx_reg_read(ds, REG_GLOBAL2, GLOBAL2_EEPROM_DATA);
error:
	mutex_unlock(&ps->eeprom_mutex);
	return ret;
}

static int mv88e6352_get_eeprom(struct dsa_switch *ds,
				struct ethtool_eeprom *eeprom, u8 *data)
{
	int offset;
	int len;
	int ret;

	offset = eeprom->offset;
	len = eeprom->len;
	eeprom->len = 0;

	eeprom->magic = 0xc3ec4951;

	ret = mv88e6xxx_eeprom_load_wait(ds);
	if (ret < 0)
		return ret;

	if (offset & 1) {
		int word;

		word = mv88e6352_read_eeprom_word(ds, offset >> 1);
		if (word < 0)
			return word;

		*data++ = (word >> 8) & 0xff;

		offset++;
		len--;
		eeprom->len++;
	}

	while (len >= 2) {
		int word;

		word = mv88e6352_read_eeprom_word(ds, offset >> 1);
		if (word < 0)
			return word;

		*data++ = word & 0xff;
		*data++ = (word >> 8) & 0xff;

		offset += 2;
		len -= 2;
		eeprom->len += 2;
	}

	if (len) {
		int word;

		word = mv88e6352_read_eeprom_word(ds, offset >> 1);
		if (word < 0)
			return word;

		*data++ = word & 0xff;

		offset++;
		len--;
		eeprom->len++;
	}

	return 0;
}

static int mv88e6352_eeprom_is_readonly(struct dsa_switch *ds)
{
	int ret;

	ret = mv88e6xxx_reg_read(ds, REG_GLOBAL2, GLOBAL2_EEPROM_OP);
	if (ret < 0)
		return ret;

	if (!(ret & GLOBAL2_EEPROM_OP_WRITE_EN))
		return -EROFS;

	return 0;
}

static int mv88e6352_write_eeprom_word(struct dsa_switch *ds, int addr,
				       u16 data)
{
	struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
	int ret;

	mutex_lock(&ps->eeprom_mutex);

	ret = mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_EEPROM_DATA, data);
	if (ret < 0)
		goto error;

	ret = mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
				  GLOBAL2_EEPROM_OP_WRITE |
				  (addr & GLOBAL2_EEPROM_OP_ADDR_MASK));
	if (ret < 0)
		goto error;

	ret = mv88e6xxx_eeprom_busy_wait(ds);
error:
	mutex_unlock(&ps->eeprom_mutex);
	return ret;
}

static int mv88e6352_set_eeprom(struct dsa_switch *ds,
				struct ethtool_eeprom *eeprom, u8 *data)
{
	int offset;
	int ret;
	int len;

	if (eeprom->magic != 0xc3ec4951)
		return -EINVAL;

	ret = mv88e6352_eeprom_is_readonly(ds);
	if (ret)
		return ret;

	offset = eeprom->offset;
	len = eeprom->len;
	eeprom->len = 0;

	ret = mv88e6xxx_eeprom_load_wait(ds);
	if (ret < 0)
		return ret;

	if (offset & 1) {
		int word;

		word = mv88e6352_read_eeprom_word(ds, offset >> 1);
		if (word < 0)
			return word;

		word = (*data++ << 8) | (word & 0xff);

		ret = mv88e6352_write_eeprom_word(ds, offset >> 1, word);
		if (ret < 0)
			return ret;

		offset++;
		len--;
		eeprom->len++;
	}

	while (len >= 2) {
		int word;

		word = *data++;
		word |= *data++ << 8;

		ret = mv88e6352_write_eeprom_word(ds, offset >> 1, word);
		if (ret < 0)
			return ret;

		offset += 2;
		len -= 2;
		eeprom->len += 2;
	}

	if (len) {
		int word;

		word = mv88e6352_read_eeprom_word(ds, offset >> 1);
		if (word < 0)
			return word;

		word = (word & 0xff00) | *data++;

		ret = mv88e6352_write_eeprom_word(ds, offset >> 1, word);
		if (ret < 0)
			return ret;

		offset++;
		len--;
		eeprom->len++;
	}

	return 0;
}

struct dsa_switch_driver mv88e6352_switch_driver = {
	.tag_protocol		= DSA_TAG_PROTO_EDSA,
	.priv_size		= sizeof(struct mv88e6xxx_priv_state),
	.probe			= mv88e6352_probe,
	.setup			= mv88e6352_setup,
	.set_addr		= mv88e6xxx_set_addr_indirect,
	.phy_read		= mv88e6xxx_phy_read_indirect,
	.phy_write		= mv88e6xxx_phy_write_indirect,
	.get_strings		= mv88e6xxx_get_strings,
	.get_ethtool_stats	= mv88e6xxx_get_ethtool_stats,
	.get_sset_count		= mv88e6xxx_get_sset_count,
	.adjust_link		= mv88e6xxx_adjust_link,
	.set_eee		= mv88e6xxx_set_eee,
	.get_eee		= mv88e6xxx_get_eee,
#ifdef CONFIG_NET_DSA_HWMON
	.get_temp		= mv88e6xxx_get_temp,
	.get_temp_limit		= mv88e6xxx_get_temp_limit,
	.set_temp_limit		= mv88e6xxx_set_temp_limit,
	.get_temp_alarm		= mv88e6xxx_get_temp_alarm,
#endif
	.get_eeprom		= mv88e6352_get_eeprom,
	.set_eeprom		= mv88e6352_set_eeprom,
	.get_regs_len		= mv88e6xxx_get_regs_len,
	.get_regs		= mv88e6xxx_get_regs,
	.port_bridge_join	= mv88e6xxx_port_bridge_join,
	.port_bridge_leave	= mv88e6xxx_port_bridge_leave,
	.port_stp_state_set	= mv88e6xxx_port_stp_state_set,
	.port_vlan_filtering	= mv88e6xxx_port_vlan_filtering,
	.port_vlan_prepare	= mv88e6xxx_port_vlan_prepare,
	.port_vlan_add		= mv88e6xxx_port_vlan_add,
	.port_vlan_del		= mv88e6xxx_port_vlan_del,
	.port_vlan_dump		= mv88e6xxx_port_vlan_dump,
	.port_fdb_prepare	= mv88e6xxx_port_fdb_prepare,
	.port_fdb_add		= mv88e6xxx_port_fdb_add,
	.port_fdb_del		= mv88e6xxx_port_fdb_del,
	.port_fdb_dump		= mv88e6xxx_port_fdb_dump,
};

MODULE_ALIAS("platform:mv88e6172");
MODULE_ALIAS("platform:mv88e6176");
MODULE_ALIAS("platform:mv88e6320");
MODULE_ALIAS("platform:mv88e6321");
MODULE_ALIAS("platform:mv88e6352");
Commit	Line	Data
3ad50cca GR	1	/*
	2	* net/dsa/mv88e6352.c - Marvell 88e6352 switch chip support
	3	*
	4	* Copyright (c) 2014 Guenter Roeck
	5	*
	6	* Derived from mv88e6123_61_65.c
	7	* Copyright (c) 2008-2009 Marvell Semiconductor
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License as published by
	11	* the Free Software Foundation; either version 2 of the License, or
	12	* (at your option) any later version.
	13	*/
	14
	15	#include <linux/delay.h>
	16	#include <linux/jiffies.h>
	17	#include <linux/list.h>
	18	#include <linux/module.h>
	19	#include <linux/netdevice.h>
	20	#include <linux/platform_device.h>
	21	#include <linux/phy.h>
	22	#include <net/dsa.h>
	23	#include "mv88e6xxx.h"
	24
b9b37713 VD	25	static const struct mv88e6xxx_switch_id mv88e6352_table[] = {
	26	{ PORT_SWITCH_ID_6172, "Marvell 88E6172" },
	27	{ PORT_SWITCH_ID_6176, "Marvell 88E6176" },
bd16a724	28	{ PORT_SWITCH_ID_6240, "Marvell 88E6240" },
b9b37713 VD	29	{ PORT_SWITCH_ID_6320, "Marvell 88E6320" },
	30	{ PORT_SWITCH_ID_6320_A1, "Marvell 88E6320 (A1)" },
	31	{ PORT_SWITCH_ID_6320_A2, "Marvell 88e6320 (A2)" },
	32	{ PORT_SWITCH_ID_6321, "Marvell 88E6321" },
	33	{ PORT_SWITCH_ID_6321_A1, "Marvell 88E6321 (A1)" },
	34	{ PORT_SWITCH_ID_6321_A2, "Marvell 88e6321 (A2)" },
	35	{ PORT_SWITCH_ID_6352, "Marvell 88E6352" },
	36	{ PORT_SWITCH_ID_6352_A0, "Marvell 88E6352 (A0)" },
	37	{ PORT_SWITCH_ID_6352_A1, "Marvell 88E6352 (A1)" },
	38	};
	39
bbb8d793 AL	40	static char mv88e6352_probe(struct device dsa_dev, struct device *host_dev,
bbb8d793 AL	41	int sw_addr)
3ad50cca	42	{
b9b37713 VD	43	return mv88e6xxx_lookup_name(host_dev, sw_addr, mv88e6352_table,
b9b37713 VD	44	ARRAY_SIZE(mv88e6352_table));
3ad50cca GR	45	}
3ad50cca GR	46
3ad50cca GR	47	static int mv88e6352_setup_global(struct dsa_switch *ds)
3ad50cca GR	48	{
15966a2a	49	u32 upstream_port = dsa_upstream_port(ds);
3ad50cca	50	int ret;
15966a2a	51	u32 reg;
54d792f2 AL	52
	53	ret = mv88e6xxx_setup_global(ds);
	54	if (ret)
	55	return ret;
3ad50cca GR	56
	57	/* Discard packets with excessive collisions,
	58	* mask all interrupt sources, enable PPU (bit 14, undocumented).
	59	*/
15966a2a AL	60	REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL,
15966a2a AL	61	GLOBAL_CONTROL_PPU_ENABLE \| GLOBAL_CONTROL_DISCARD_EXCESS);
3ad50cca	62
3ad50cca GR	63	/* Configure the upstream port, and configure the upstream
	64	* port as the port to which ingress and egress monitor frames
	65	* are to be sent.
	66	*/
15966a2a AL	67	reg = upstream_port << GLOBAL_MONITOR_CONTROL_INGRESS_SHIFT \|
	68	upstream_port << GLOBAL_MONITOR_CONTROL_EGRESS_SHIFT \|
	69	upstream_port << GLOBAL_MONITOR_CONTROL_ARP_SHIFT;
	70	REG_WRITE(REG_GLOBAL, GLOBAL_MONITOR_CONTROL, reg);
3ad50cca GR	71
	72	/* Disable remote management for now, and set the switch's
	73	* DSA device number.
	74	*/
	75	REG_WRITE(REG_GLOBAL, 0x1c, ds->index & 0x1f);
	76
3ad50cca GR	77	return 0;
	78	}
	79
3ad50cca GR	80	static int mv88e6352_setup(struct dsa_switch *ds)
	81	{
	82	struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
	83	int ret;
3ad50cca	84
acdaffcc GR	85	ret = mv88e6xxx_setup_common(ds);
	86	if (ret < 0)
	87	return ret;
	88
44e50ddb AL	89	ps->num_ports = 7;
44e50ddb AL	90
33b43df4	91	mutex_init(&ps->eeprom_mutex);
3ad50cca	92
143a8307	93	ret = mv88e6xxx_switch_reset(ds, true);
3ad50cca GR	94	if (ret < 0)
	95	return ret;
	96
3ad50cca GR	97	ret = mv88e6352_setup_global(ds);
	98	if (ret < 0)
	99	return ret;
	100
dbde9e66	101	return mv88e6xxx_setup_ports(ds);
3ad50cca GR	102	}
3ad50cca GR	103
33b43df4 GR	104	static int mv88e6352_read_eeprom_word(struct dsa_switch *ds, int addr)
	105	{
	106	struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
	107	int ret;
	108
	109	mutex_lock(&ps->eeprom_mutex);
	110
966bce38 AL	111	ret = mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
	112	GLOBAL2_EEPROM_OP_READ \|
	113	(addr & GLOBAL2_EEPROM_OP_ADDR_MASK));
33b43df4 GR	114	if (ret < 0)
	115	goto error;
	116
f3044683	117	ret = mv88e6xxx_eeprom_busy_wait(ds);
33b43df4 GR	118	if (ret < 0)
	119	goto error;
	120
966bce38	121	ret = mv88e6xxx_reg_read(ds, REG_GLOBAL2, GLOBAL2_EEPROM_DATA);
33b43df4 GR	122	error:
	123	mutex_unlock(&ps->eeprom_mutex);
	124	return ret;
	125	}
	126
	127	static int mv88e6352_get_eeprom(struct dsa_switch *ds,
	128	struct ethtool_eeprom eeprom, u8 data)
	129	{
	130	int offset;
	131	int len;
	132	int ret;
	133
	134	offset = eeprom->offset;
	135	len = eeprom->len;
	136	eeprom->len = 0;
	137
	138	eeprom->magic = 0xc3ec4951;
	139
f3044683	140	ret = mv88e6xxx_eeprom_load_wait(ds);
33b43df4 GR	141	if (ret < 0)
	142	return ret;
	143
	144	if (offset & 1) {
	145	int word;
	146
	147	word = mv88e6352_read_eeprom_word(ds, offset >> 1);
	148	if (word < 0)
	149	return word;
	150
	151	*data++ = (word >> 8) & 0xff;
	152
	153	offset++;
	154	len--;
	155	eeprom->len++;
	156	}
	157
	158	while (len >= 2) {
	159	int word;
	160
	161	word = mv88e6352_read_eeprom_word(ds, offset >> 1);
	162	if (word < 0)
	163	return word;
	164
	165	*data++ = word & 0xff;
	166	*data++ = (word >> 8) & 0xff;
	167
	168	offset += 2;
	169	len -= 2;
	170	eeprom->len += 2;
	171	}
	172
	173	if (len) {
	174	int word;
	175
	176	word = mv88e6352_read_eeprom_word(ds, offset >> 1);
	177	if (word < 0)
	178	return word;
	179
	180	*data++ = word & 0xff;
	181
	182	offset++;
	183	len--;
	184	eeprom->len++;
	185	}
	186
	187	return 0;
	188	}
	189
	190	static int mv88e6352_eeprom_is_readonly(struct dsa_switch *ds)
	191	{
	192	int ret;
	193
966bce38	194	ret = mv88e6xxx_reg_read(ds, REG_GLOBAL2, GLOBAL2_EEPROM_OP);
33b43df4 GR	195	if (ret < 0)
	196	return ret;
	197
966bce38	198	if (!(ret & GLOBAL2_EEPROM_OP_WRITE_EN))
33b43df4 GR	199	return -EROFS;
	200
	201	return 0;
	202	}
	203
	204	static int mv88e6352_write_eeprom_word(struct dsa_switch *ds, int addr,
	205	u16 data)
	206	{
	207	struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
	208	int ret;
	209
	210	mutex_lock(&ps->eeprom_mutex);
	211
966bce38	212	ret = mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_EEPROM_DATA, data);
33b43df4 GR	213	if (ret < 0)
	214	goto error;
	215
966bce38 AL	216	ret = mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
	217	GLOBAL2_EEPROM_OP_WRITE \|
	218	(addr & GLOBAL2_EEPROM_OP_ADDR_MASK));
33b43df4 GR	219	if (ret < 0)
	220	goto error;
	221
f3044683	222	ret = mv88e6xxx_eeprom_busy_wait(ds);
33b43df4 GR	223	error:
	224	mutex_unlock(&ps->eeprom_mutex);
	225	return ret;
	226	}
	227
	228	static int mv88e6352_set_eeprom(struct dsa_switch *ds,
	229	struct ethtool_eeprom eeprom, u8 data)
	230	{
	231	int offset;
	232	int ret;
	233	int len;
	234
	235	if (eeprom->magic != 0xc3ec4951)
	236	return -EINVAL;
	237
	238	ret = mv88e6352_eeprom_is_readonly(ds);
	239	if (ret)
	240	return ret;
	241
	242	offset = eeprom->offset;
	243	len = eeprom->len;
	244	eeprom->len = 0;
	245
f3044683	246	ret = mv88e6xxx_eeprom_load_wait(ds);
33b43df4 GR	247	if (ret < 0)
	248	return ret;
	249
	250	if (offset & 1) {
	251	int word;
	252
	253	word = mv88e6352_read_eeprom_word(ds, offset >> 1);
	254	if (word < 0)
	255	return word;
	256
	257	word = (*data++ << 8) \| (word & 0xff);
	258
	259	ret = mv88e6352_write_eeprom_word(ds, offset >> 1, word);
	260	if (ret < 0)
	261	return ret;
	262
	263	offset++;
	264	len--;
	265	eeprom->len++;
	266	}
	267
	268	while (len >= 2) {
	269	int word;
	270
	271	word = *data++;
	272	word \|= *data++ << 8;
	273
	274	ret = mv88e6352_write_eeprom_word(ds, offset >> 1, word);
	275	if (ret < 0)
	276	return ret;
	277
	278	offset += 2;
	279	len -= 2;
	280	eeprom->len += 2;
	281	}
	282
	283	if (len) {
	284	int word;
	285
	286	word = mv88e6352_read_eeprom_word(ds, offset >> 1);
	287	if (word < 0)
	288	return word;
	289
	290	word = (word & 0xff00) \| *data++;
	291
	292	ret = mv88e6352_write_eeprom_word(ds, offset >> 1, word);
	293	if (ret < 0)
	294	return ret;
	295
	296	offset++;
	297	len--;
	298	eeprom->len++;
	299	}
	300
	301	return 0;
	302	}
	303
3ad50cca GR	304	struct dsa_switch_driver mv88e6352_switch_driver = {
	305	.tag_protocol = DSA_TAG_PROTO_EDSA,
	306	.priv_size = sizeof(struct mv88e6xxx_priv_state),
	307	.probe = mv88e6352_probe,
	308	.setup = mv88e6352_setup,
	309	.set_addr = mv88e6xxx_set_addr_indirect,
fd3a0ee4 AL	310	.phy_read = mv88e6xxx_phy_read_indirect,
fd3a0ee4 AL	311	.phy_write = mv88e6xxx_phy_write_indirect,
e413e7e1 AL	312	.get_strings = mv88e6xxx_get_strings,
	313	.get_ethtool_stats = mv88e6xxx_get_ethtool_stats,
	314	.get_sset_count = mv88e6xxx_get_sset_count,
dea87024	315	.adjust_link = mv88e6xxx_adjust_link,
04b0a80b GR	316	.set_eee = mv88e6xxx_set_eee,
04b0a80b GR	317	.get_eee = mv88e6xxx_get_eee,
276db3b1	318	#ifdef CONFIG_NET_DSA_HWMON
c22995c5 GR	319	.get_temp = mv88e6xxx_get_temp,
	320	.get_temp_limit = mv88e6xxx_get_temp_limit,
	321	.set_temp_limit = mv88e6xxx_set_temp_limit,
	322	.get_temp_alarm = mv88e6xxx_get_temp_alarm,
276db3b1	323	#endif
33b43df4 GR	324	.get_eeprom = mv88e6352_get_eeprom,
33b43df4 GR	325	.set_eeprom = mv88e6352_set_eeprom,
95d08b5a GR	326	.get_regs_len = mv88e6xxx_get_regs_len,
95d08b5a GR	327	.get_regs = mv88e6xxx_get_regs,
71327a4e VD	328	.port_bridge_join = mv88e6xxx_port_bridge_join,
71327a4e VD	329	.port_bridge_leave = mv88e6xxx_port_bridge_leave,
43c44a9f	330	.port_stp_state_set = mv88e6xxx_port_stp_state_set,
214cdb99	331	.port_vlan_filtering = mv88e6xxx_port_vlan_filtering,
76e398a6	332	.port_vlan_prepare = mv88e6xxx_port_vlan_prepare,
0d3b33e6	333	.port_vlan_add = mv88e6xxx_port_vlan_add,
7dad08d7	334	.port_vlan_del = mv88e6xxx_port_vlan_del,
ceff5eff	335	.port_vlan_dump = mv88e6xxx_port_vlan_dump,
146a3206	336	.port_fdb_prepare = mv88e6xxx_port_fdb_prepare,
2a778e1b VD	337	.port_fdb_add = mv88e6xxx_port_fdb_add,
2a778e1b VD	338	.port_fdb_del = mv88e6xxx_port_fdb_del,
f33475bd	339	.port_fdb_dump = mv88e6xxx_port_fdb_dump,
3ad50cca GR	340	};
3ad50cca GR	341
1636d883	342	MODULE_ALIAS("platform:mv88e6172");
7c3d0d67 AK	343	MODULE_ALIAS("platform:mv88e6176");
	344	MODULE_ALIAS("platform:mv88e6320");
	345	MODULE_ALIAS("platform:mv88e6321");
	346	MODULE_ALIAS("platform:mv88e6352");