Commit | Line | Data |
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91da11f8 LB |
1 | /* |
2 | * net/dsa/mv88e6xxx.c - Marvell 88e6xxx switch chip support | |
3 | * Copyright (c) 2008 Marvell Semiconductor | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation; either version 2 of the License, or | |
8 | * (at your option) any later version. | |
9 | */ | |
10 | ||
19b2f97e | 11 | #include <linux/delay.h> |
defb05b9 | 12 | #include <linux/etherdevice.h> |
facd95b2 | 13 | #include <linux/if_bridge.h> |
19b2f97e | 14 | #include <linux/jiffies.h> |
91da11f8 | 15 | #include <linux/list.h> |
2bbba277 | 16 | #include <linux/module.h> |
91da11f8 LB |
17 | #include <linux/netdevice.h> |
18 | #include <linux/phy.h> | |
c8f0b869 | 19 | #include <net/dsa.h> |
91da11f8 LB |
20 | #include "mv88e6xxx.h" |
21 | ||
16fe24fc AL |
22 | /* MDIO bus access can be nested in the case of PHYs connected to the |
23 | * internal MDIO bus of the switch, which is accessed via MDIO bus of | |
24 | * the Ethernet interface. Avoid lockdep false positives by using | |
25 | * mutex_lock_nested(). | |
26 | */ | |
27 | static int mv88e6xxx_mdiobus_read(struct mii_bus *bus, int addr, u32 regnum) | |
28 | { | |
29 | int ret; | |
30 | ||
31 | mutex_lock_nested(&bus->mdio_lock, SINGLE_DEPTH_NESTING); | |
32 | ret = bus->read(bus, addr, regnum); | |
33 | mutex_unlock(&bus->mdio_lock); | |
34 | ||
35 | return ret; | |
36 | } | |
37 | ||
38 | static int mv88e6xxx_mdiobus_write(struct mii_bus *bus, int addr, u32 regnum, | |
39 | u16 val) | |
40 | { | |
41 | int ret; | |
42 | ||
43 | mutex_lock_nested(&bus->mdio_lock, SINGLE_DEPTH_NESTING); | |
44 | ret = bus->write(bus, addr, regnum, val); | |
45 | mutex_unlock(&bus->mdio_lock); | |
46 | ||
47 | return ret; | |
48 | } | |
49 | ||
3675c8d7 | 50 | /* If the switch's ADDR[4:0] strap pins are strapped to zero, it will |
91da11f8 LB |
51 | * use all 32 SMI bus addresses on its SMI bus, and all switch registers |
52 | * will be directly accessible on some {device address,register address} | |
53 | * pair. If the ADDR[4:0] pins are not strapped to zero, the switch | |
54 | * will only respond to SMI transactions to that specific address, and | |
55 | * an indirect addressing mechanism needs to be used to access its | |
56 | * registers. | |
57 | */ | |
58 | static int mv88e6xxx_reg_wait_ready(struct mii_bus *bus, int sw_addr) | |
59 | { | |
60 | int ret; | |
61 | int i; | |
62 | ||
63 | for (i = 0; i < 16; i++) { | |
16fe24fc | 64 | ret = mv88e6xxx_mdiobus_read(bus, sw_addr, SMI_CMD); |
91da11f8 LB |
65 | if (ret < 0) |
66 | return ret; | |
67 | ||
cca8b133 | 68 | if ((ret & SMI_CMD_BUSY) == 0) |
91da11f8 LB |
69 | return 0; |
70 | } | |
71 | ||
72 | return -ETIMEDOUT; | |
73 | } | |
74 | ||
75 | int __mv88e6xxx_reg_read(struct mii_bus *bus, int sw_addr, int addr, int reg) | |
76 | { | |
77 | int ret; | |
78 | ||
79 | if (sw_addr == 0) | |
16fe24fc | 80 | return mv88e6xxx_mdiobus_read(bus, addr, reg); |
91da11f8 | 81 | |
3675c8d7 | 82 | /* Wait for the bus to become free. */ |
91da11f8 LB |
83 | ret = mv88e6xxx_reg_wait_ready(bus, sw_addr); |
84 | if (ret < 0) | |
85 | return ret; | |
86 | ||
3675c8d7 | 87 | /* Transmit the read command. */ |
16fe24fc AL |
88 | ret = mv88e6xxx_mdiobus_write(bus, sw_addr, SMI_CMD, |
89 | SMI_CMD_OP_22_READ | (addr << 5) | reg); | |
91da11f8 LB |
90 | if (ret < 0) |
91 | return ret; | |
92 | ||
3675c8d7 | 93 | /* Wait for the read command to complete. */ |
91da11f8 LB |
94 | ret = mv88e6xxx_reg_wait_ready(bus, sw_addr); |
95 | if (ret < 0) | |
96 | return ret; | |
97 | ||
3675c8d7 | 98 | /* Read the data. */ |
16fe24fc | 99 | ret = mv88e6xxx_mdiobus_read(bus, sw_addr, SMI_DATA); |
91da11f8 LB |
100 | if (ret < 0) |
101 | return ret; | |
102 | ||
103 | return ret & 0xffff; | |
104 | } | |
105 | ||
8d6d09e7 GR |
106 | /* Must be called with SMI mutex held */ |
107 | static int _mv88e6xxx_reg_read(struct dsa_switch *ds, int addr, int reg) | |
91da11f8 | 108 | { |
b184e497 | 109 | struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev); |
91da11f8 LB |
110 | int ret; |
111 | ||
b184e497 GR |
112 | if (bus == NULL) |
113 | return -EINVAL; | |
114 | ||
b184e497 | 115 | ret = __mv88e6xxx_reg_read(bus, ds->pd->sw_addr, addr, reg); |
bb92ea5e VD |
116 | if (ret < 0) |
117 | return ret; | |
118 | ||
119 | dev_dbg(ds->master_dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", | |
120 | addr, reg, ret); | |
121 | ||
91da11f8 LB |
122 | return ret; |
123 | } | |
124 | ||
8d6d09e7 GR |
125 | int mv88e6xxx_reg_read(struct dsa_switch *ds, int addr, int reg) |
126 | { | |
127 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
128 | int ret; | |
129 | ||
130 | mutex_lock(&ps->smi_mutex); | |
131 | ret = _mv88e6xxx_reg_read(ds, addr, reg); | |
132 | mutex_unlock(&ps->smi_mutex); | |
133 | ||
134 | return ret; | |
135 | } | |
136 | ||
91da11f8 LB |
137 | int __mv88e6xxx_reg_write(struct mii_bus *bus, int sw_addr, int addr, |
138 | int reg, u16 val) | |
139 | { | |
140 | int ret; | |
141 | ||
142 | if (sw_addr == 0) | |
16fe24fc | 143 | return mv88e6xxx_mdiobus_write(bus, addr, reg, val); |
91da11f8 | 144 | |
3675c8d7 | 145 | /* Wait for the bus to become free. */ |
91da11f8 LB |
146 | ret = mv88e6xxx_reg_wait_ready(bus, sw_addr); |
147 | if (ret < 0) | |
148 | return ret; | |
149 | ||
3675c8d7 | 150 | /* Transmit the data to write. */ |
16fe24fc | 151 | ret = mv88e6xxx_mdiobus_write(bus, sw_addr, SMI_DATA, val); |
91da11f8 LB |
152 | if (ret < 0) |
153 | return ret; | |
154 | ||
3675c8d7 | 155 | /* Transmit the write command. */ |
16fe24fc AL |
156 | ret = mv88e6xxx_mdiobus_write(bus, sw_addr, SMI_CMD, |
157 | SMI_CMD_OP_22_WRITE | (addr << 5) | reg); | |
91da11f8 LB |
158 | if (ret < 0) |
159 | return ret; | |
160 | ||
3675c8d7 | 161 | /* Wait for the write command to complete. */ |
91da11f8 LB |
162 | ret = mv88e6xxx_reg_wait_ready(bus, sw_addr); |
163 | if (ret < 0) | |
164 | return ret; | |
165 | ||
166 | return 0; | |
167 | } | |
168 | ||
8d6d09e7 GR |
169 | /* Must be called with SMI mutex held */ |
170 | static int _mv88e6xxx_reg_write(struct dsa_switch *ds, int addr, int reg, | |
171 | u16 val) | |
91da11f8 | 172 | { |
b184e497 | 173 | struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev); |
91da11f8 | 174 | |
b184e497 GR |
175 | if (bus == NULL) |
176 | return -EINVAL; | |
177 | ||
bb92ea5e VD |
178 | dev_dbg(ds->master_dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", |
179 | addr, reg, val); | |
180 | ||
8d6d09e7 GR |
181 | return __mv88e6xxx_reg_write(bus, ds->pd->sw_addr, addr, reg, val); |
182 | } | |
183 | ||
184 | int mv88e6xxx_reg_write(struct dsa_switch *ds, int addr, int reg, u16 val) | |
185 | { | |
186 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
187 | int ret; | |
188 | ||
91da11f8 | 189 | mutex_lock(&ps->smi_mutex); |
8d6d09e7 | 190 | ret = _mv88e6xxx_reg_write(ds, addr, reg, val); |
91da11f8 LB |
191 | mutex_unlock(&ps->smi_mutex); |
192 | ||
193 | return ret; | |
194 | } | |
195 | ||
2e5f0320 LB |
196 | int mv88e6xxx_set_addr_direct(struct dsa_switch *ds, u8 *addr) |
197 | { | |
cca8b133 AL |
198 | REG_WRITE(REG_GLOBAL, GLOBAL_MAC_01, (addr[0] << 8) | addr[1]); |
199 | REG_WRITE(REG_GLOBAL, GLOBAL_MAC_23, (addr[2] << 8) | addr[3]); | |
200 | REG_WRITE(REG_GLOBAL, GLOBAL_MAC_45, (addr[4] << 8) | addr[5]); | |
2e5f0320 LB |
201 | |
202 | return 0; | |
203 | } | |
204 | ||
91da11f8 LB |
205 | int mv88e6xxx_set_addr_indirect(struct dsa_switch *ds, u8 *addr) |
206 | { | |
207 | int i; | |
208 | int ret; | |
209 | ||
210 | for (i = 0; i < 6; i++) { | |
211 | int j; | |
212 | ||
3675c8d7 | 213 | /* Write the MAC address byte. */ |
cca8b133 AL |
214 | REG_WRITE(REG_GLOBAL2, GLOBAL2_SWITCH_MAC, |
215 | GLOBAL2_SWITCH_MAC_BUSY | (i << 8) | addr[i]); | |
91da11f8 | 216 | |
3675c8d7 | 217 | /* Wait for the write to complete. */ |
91da11f8 | 218 | for (j = 0; j < 16; j++) { |
cca8b133 AL |
219 | ret = REG_READ(REG_GLOBAL2, GLOBAL2_SWITCH_MAC); |
220 | if ((ret & GLOBAL2_SWITCH_MAC_BUSY) == 0) | |
91da11f8 LB |
221 | break; |
222 | } | |
223 | if (j == 16) | |
224 | return -ETIMEDOUT; | |
225 | } | |
226 | ||
227 | return 0; | |
228 | } | |
229 | ||
3898c148 | 230 | /* Must be called with SMI mutex held */ |
fd3a0ee4 | 231 | static int _mv88e6xxx_phy_read(struct dsa_switch *ds, int addr, int regnum) |
91da11f8 LB |
232 | { |
233 | if (addr >= 0) | |
3898c148 | 234 | return _mv88e6xxx_reg_read(ds, addr, regnum); |
91da11f8 LB |
235 | return 0xffff; |
236 | } | |
237 | ||
3898c148 | 238 | /* Must be called with SMI mutex held */ |
fd3a0ee4 AL |
239 | static int _mv88e6xxx_phy_write(struct dsa_switch *ds, int addr, int regnum, |
240 | u16 val) | |
91da11f8 LB |
241 | { |
242 | if (addr >= 0) | |
3898c148 | 243 | return _mv88e6xxx_reg_write(ds, addr, regnum, val); |
91da11f8 LB |
244 | return 0; |
245 | } | |
246 | ||
2e5f0320 LB |
247 | #ifdef CONFIG_NET_DSA_MV88E6XXX_NEED_PPU |
248 | static int mv88e6xxx_ppu_disable(struct dsa_switch *ds) | |
249 | { | |
250 | int ret; | |
19b2f97e | 251 | unsigned long timeout; |
2e5f0320 | 252 | |
cca8b133 AL |
253 | ret = REG_READ(REG_GLOBAL, GLOBAL_CONTROL); |
254 | REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL, | |
255 | ret & ~GLOBAL_CONTROL_PPU_ENABLE); | |
2e5f0320 | 256 | |
19b2f97e BG |
257 | timeout = jiffies + 1 * HZ; |
258 | while (time_before(jiffies, timeout)) { | |
cca8b133 | 259 | ret = REG_READ(REG_GLOBAL, GLOBAL_STATUS); |
19b2f97e | 260 | usleep_range(1000, 2000); |
cca8b133 AL |
261 | if ((ret & GLOBAL_STATUS_PPU_MASK) != |
262 | GLOBAL_STATUS_PPU_POLLING) | |
85686581 | 263 | return 0; |
2e5f0320 LB |
264 | } |
265 | ||
266 | return -ETIMEDOUT; | |
267 | } | |
268 | ||
269 | static int mv88e6xxx_ppu_enable(struct dsa_switch *ds) | |
270 | { | |
271 | int ret; | |
19b2f97e | 272 | unsigned long timeout; |
2e5f0320 | 273 | |
cca8b133 AL |
274 | ret = REG_READ(REG_GLOBAL, GLOBAL_CONTROL); |
275 | REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL, ret | GLOBAL_CONTROL_PPU_ENABLE); | |
2e5f0320 | 276 | |
19b2f97e BG |
277 | timeout = jiffies + 1 * HZ; |
278 | while (time_before(jiffies, timeout)) { | |
cca8b133 | 279 | ret = REG_READ(REG_GLOBAL, GLOBAL_STATUS); |
19b2f97e | 280 | usleep_range(1000, 2000); |
cca8b133 AL |
281 | if ((ret & GLOBAL_STATUS_PPU_MASK) == |
282 | GLOBAL_STATUS_PPU_POLLING) | |
85686581 | 283 | return 0; |
2e5f0320 LB |
284 | } |
285 | ||
286 | return -ETIMEDOUT; | |
287 | } | |
288 | ||
289 | static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly) | |
290 | { | |
291 | struct mv88e6xxx_priv_state *ps; | |
292 | ||
293 | ps = container_of(ugly, struct mv88e6xxx_priv_state, ppu_work); | |
294 | if (mutex_trylock(&ps->ppu_mutex)) { | |
85686581 | 295 | struct dsa_switch *ds = ((struct dsa_switch *)ps) - 1; |
2e5f0320 | 296 | |
85686581 BG |
297 | if (mv88e6xxx_ppu_enable(ds) == 0) |
298 | ps->ppu_disabled = 0; | |
299 | mutex_unlock(&ps->ppu_mutex); | |
2e5f0320 LB |
300 | } |
301 | } | |
302 | ||
303 | static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps) | |
304 | { | |
305 | struct mv88e6xxx_priv_state *ps = (void *)_ps; | |
306 | ||
307 | schedule_work(&ps->ppu_work); | |
308 | } | |
309 | ||
310 | static int mv88e6xxx_ppu_access_get(struct dsa_switch *ds) | |
311 | { | |
a22adce5 | 312 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); |
2e5f0320 LB |
313 | int ret; |
314 | ||
315 | mutex_lock(&ps->ppu_mutex); | |
316 | ||
3675c8d7 | 317 | /* If the PHY polling unit is enabled, disable it so that |
2e5f0320 LB |
318 | * we can access the PHY registers. If it was already |
319 | * disabled, cancel the timer that is going to re-enable | |
320 | * it. | |
321 | */ | |
322 | if (!ps->ppu_disabled) { | |
85686581 BG |
323 | ret = mv88e6xxx_ppu_disable(ds); |
324 | if (ret < 0) { | |
325 | mutex_unlock(&ps->ppu_mutex); | |
326 | return ret; | |
327 | } | |
328 | ps->ppu_disabled = 1; | |
2e5f0320 | 329 | } else { |
85686581 BG |
330 | del_timer(&ps->ppu_timer); |
331 | ret = 0; | |
2e5f0320 LB |
332 | } |
333 | ||
334 | return ret; | |
335 | } | |
336 | ||
337 | static void mv88e6xxx_ppu_access_put(struct dsa_switch *ds) | |
338 | { | |
a22adce5 | 339 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); |
2e5f0320 | 340 | |
3675c8d7 | 341 | /* Schedule a timer to re-enable the PHY polling unit. */ |
2e5f0320 LB |
342 | mod_timer(&ps->ppu_timer, jiffies + msecs_to_jiffies(10)); |
343 | mutex_unlock(&ps->ppu_mutex); | |
344 | } | |
345 | ||
346 | void mv88e6xxx_ppu_state_init(struct dsa_switch *ds) | |
347 | { | |
a22adce5 | 348 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); |
2e5f0320 LB |
349 | |
350 | mutex_init(&ps->ppu_mutex); | |
351 | INIT_WORK(&ps->ppu_work, mv88e6xxx_ppu_reenable_work); | |
352 | init_timer(&ps->ppu_timer); | |
353 | ps->ppu_timer.data = (unsigned long)ps; | |
354 | ps->ppu_timer.function = mv88e6xxx_ppu_reenable_timer; | |
355 | } | |
356 | ||
357 | int mv88e6xxx_phy_read_ppu(struct dsa_switch *ds, int addr, int regnum) | |
358 | { | |
359 | int ret; | |
360 | ||
361 | ret = mv88e6xxx_ppu_access_get(ds); | |
362 | if (ret >= 0) { | |
85686581 BG |
363 | ret = mv88e6xxx_reg_read(ds, addr, regnum); |
364 | mv88e6xxx_ppu_access_put(ds); | |
2e5f0320 LB |
365 | } |
366 | ||
367 | return ret; | |
368 | } | |
369 | ||
370 | int mv88e6xxx_phy_write_ppu(struct dsa_switch *ds, int addr, | |
371 | int regnum, u16 val) | |
372 | { | |
373 | int ret; | |
374 | ||
375 | ret = mv88e6xxx_ppu_access_get(ds); | |
376 | if (ret >= 0) { | |
85686581 BG |
377 | ret = mv88e6xxx_reg_write(ds, addr, regnum, val); |
378 | mv88e6xxx_ppu_access_put(ds); | |
2e5f0320 LB |
379 | } |
380 | ||
381 | return ret; | |
382 | } | |
383 | #endif | |
384 | ||
91da11f8 LB |
385 | void mv88e6xxx_poll_link(struct dsa_switch *ds) |
386 | { | |
387 | int i; | |
388 | ||
389 | for (i = 0; i < DSA_MAX_PORTS; i++) { | |
390 | struct net_device *dev; | |
2a9e7978 | 391 | int uninitialized_var(port_status); |
91da11f8 LB |
392 | int link; |
393 | int speed; | |
394 | int duplex; | |
395 | int fc; | |
396 | ||
397 | dev = ds->ports[i]; | |
398 | if (dev == NULL) | |
399 | continue; | |
400 | ||
401 | link = 0; | |
402 | if (dev->flags & IFF_UP) { | |
cca8b133 AL |
403 | port_status = mv88e6xxx_reg_read(ds, REG_PORT(i), |
404 | PORT_STATUS); | |
91da11f8 LB |
405 | if (port_status < 0) |
406 | continue; | |
407 | ||
cca8b133 | 408 | link = !!(port_status & PORT_STATUS_LINK); |
91da11f8 LB |
409 | } |
410 | ||
411 | if (!link) { | |
412 | if (netif_carrier_ok(dev)) { | |
ab381a93 | 413 | netdev_info(dev, "link down\n"); |
91da11f8 LB |
414 | netif_carrier_off(dev); |
415 | } | |
416 | continue; | |
417 | } | |
418 | ||
cca8b133 AL |
419 | switch (port_status & PORT_STATUS_SPEED_MASK) { |
420 | case PORT_STATUS_SPEED_10: | |
91da11f8 LB |
421 | speed = 10; |
422 | break; | |
cca8b133 | 423 | case PORT_STATUS_SPEED_100: |
91da11f8 LB |
424 | speed = 100; |
425 | break; | |
cca8b133 | 426 | case PORT_STATUS_SPEED_1000: |
91da11f8 LB |
427 | speed = 1000; |
428 | break; | |
429 | default: | |
430 | speed = -1; | |
431 | break; | |
432 | } | |
cca8b133 AL |
433 | duplex = (port_status & PORT_STATUS_DUPLEX) ? 1 : 0; |
434 | fc = (port_status & PORT_STATUS_PAUSE_EN) ? 1 : 0; | |
91da11f8 LB |
435 | |
436 | if (!netif_carrier_ok(dev)) { | |
ab381a93 BG |
437 | netdev_info(dev, |
438 | "link up, %d Mb/s, %s duplex, flow control %sabled\n", | |
439 | speed, | |
440 | duplex ? "full" : "half", | |
441 | fc ? "en" : "dis"); | |
91da11f8 LB |
442 | netif_carrier_on(dev); |
443 | } | |
444 | } | |
445 | } | |
446 | ||
54d792f2 AL |
447 | static bool mv88e6xxx_6065_family(struct dsa_switch *ds) |
448 | { | |
449 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
450 | ||
451 | switch (ps->id) { | |
452 | case PORT_SWITCH_ID_6031: | |
453 | case PORT_SWITCH_ID_6061: | |
454 | case PORT_SWITCH_ID_6035: | |
455 | case PORT_SWITCH_ID_6065: | |
456 | return true; | |
457 | } | |
458 | return false; | |
459 | } | |
460 | ||
461 | static bool mv88e6xxx_6095_family(struct dsa_switch *ds) | |
462 | { | |
463 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
464 | ||
465 | switch (ps->id) { | |
466 | case PORT_SWITCH_ID_6092: | |
467 | case PORT_SWITCH_ID_6095: | |
468 | return true; | |
469 | } | |
470 | return false; | |
471 | } | |
472 | ||
473 | static bool mv88e6xxx_6097_family(struct dsa_switch *ds) | |
474 | { | |
475 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
476 | ||
477 | switch (ps->id) { | |
478 | case PORT_SWITCH_ID_6046: | |
479 | case PORT_SWITCH_ID_6085: | |
480 | case PORT_SWITCH_ID_6096: | |
481 | case PORT_SWITCH_ID_6097: | |
482 | return true; | |
483 | } | |
484 | return false; | |
485 | } | |
486 | ||
487 | static bool mv88e6xxx_6165_family(struct dsa_switch *ds) | |
488 | { | |
489 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
490 | ||
491 | switch (ps->id) { | |
492 | case PORT_SWITCH_ID_6123: | |
493 | case PORT_SWITCH_ID_6161: | |
494 | case PORT_SWITCH_ID_6165: | |
495 | return true; | |
496 | } | |
497 | return false; | |
498 | } | |
499 | ||
500 | static bool mv88e6xxx_6185_family(struct dsa_switch *ds) | |
501 | { | |
502 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
503 | ||
504 | switch (ps->id) { | |
505 | case PORT_SWITCH_ID_6121: | |
506 | case PORT_SWITCH_ID_6122: | |
507 | case PORT_SWITCH_ID_6152: | |
508 | case PORT_SWITCH_ID_6155: | |
509 | case PORT_SWITCH_ID_6182: | |
510 | case PORT_SWITCH_ID_6185: | |
511 | case PORT_SWITCH_ID_6108: | |
512 | case PORT_SWITCH_ID_6131: | |
513 | return true; | |
514 | } | |
515 | return false; | |
516 | } | |
517 | ||
518 | static bool mv88e6xxx_6351_family(struct dsa_switch *ds) | |
519 | { | |
520 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
521 | ||
522 | switch (ps->id) { | |
523 | case PORT_SWITCH_ID_6171: | |
524 | case PORT_SWITCH_ID_6175: | |
525 | case PORT_SWITCH_ID_6350: | |
526 | case PORT_SWITCH_ID_6351: | |
527 | return true; | |
528 | } | |
529 | return false; | |
530 | } | |
531 | ||
f3a8b6b6 AL |
532 | static bool mv88e6xxx_6352_family(struct dsa_switch *ds) |
533 | { | |
534 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
535 | ||
536 | switch (ps->id) { | |
f3a8b6b6 AL |
537 | case PORT_SWITCH_ID_6172: |
538 | case PORT_SWITCH_ID_6176: | |
54d792f2 AL |
539 | case PORT_SWITCH_ID_6240: |
540 | case PORT_SWITCH_ID_6352: | |
f3a8b6b6 AL |
541 | return true; |
542 | } | |
543 | return false; | |
544 | } | |
545 | ||
31888234 AL |
546 | /* Must be called with SMI mutex held */ |
547 | static int _mv88e6xxx_stats_wait(struct dsa_switch *ds) | |
91da11f8 LB |
548 | { |
549 | int ret; | |
550 | int i; | |
551 | ||
552 | for (i = 0; i < 10; i++) { | |
31888234 | 553 | ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_STATS_OP); |
cca8b133 | 554 | if ((ret & GLOBAL_STATS_OP_BUSY) == 0) |
91da11f8 LB |
555 | return 0; |
556 | } | |
557 | ||
558 | return -ETIMEDOUT; | |
559 | } | |
560 | ||
31888234 AL |
561 | /* Must be called with SMI mutex held */ |
562 | static int _mv88e6xxx_stats_snapshot(struct dsa_switch *ds, int port) | |
91da11f8 LB |
563 | { |
564 | int ret; | |
565 | ||
f3a8b6b6 AL |
566 | if (mv88e6xxx_6352_family(ds)) |
567 | port = (port + 1) << 5; | |
568 | ||
3675c8d7 | 569 | /* Snapshot the hardware statistics counters for this port. */ |
31888234 AL |
570 | ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_STATS_OP, |
571 | GLOBAL_STATS_OP_CAPTURE_PORT | | |
572 | GLOBAL_STATS_OP_HIST_RX_TX | port); | |
573 | if (ret < 0) | |
574 | return ret; | |
91da11f8 | 575 | |
3675c8d7 | 576 | /* Wait for the snapshotting to complete. */ |
31888234 | 577 | ret = _mv88e6xxx_stats_wait(ds); |
91da11f8 LB |
578 | if (ret < 0) |
579 | return ret; | |
580 | ||
581 | return 0; | |
582 | } | |
583 | ||
31888234 AL |
584 | /* Must be called with SMI mutex held */ |
585 | static void _mv88e6xxx_stats_read(struct dsa_switch *ds, int stat, u32 *val) | |
91da11f8 LB |
586 | { |
587 | u32 _val; | |
588 | int ret; | |
589 | ||
590 | *val = 0; | |
591 | ||
31888234 AL |
592 | ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_STATS_OP, |
593 | GLOBAL_STATS_OP_READ_CAPTURED | | |
594 | GLOBAL_STATS_OP_HIST_RX_TX | stat); | |
91da11f8 LB |
595 | if (ret < 0) |
596 | return; | |
597 | ||
31888234 | 598 | ret = _mv88e6xxx_stats_wait(ds); |
91da11f8 LB |
599 | if (ret < 0) |
600 | return; | |
601 | ||
31888234 | 602 | ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_STATS_COUNTER_32); |
91da11f8 LB |
603 | if (ret < 0) |
604 | return; | |
605 | ||
606 | _val = ret << 16; | |
607 | ||
31888234 | 608 | ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_STATS_COUNTER_01); |
91da11f8 LB |
609 | if (ret < 0) |
610 | return; | |
611 | ||
612 | *val = _val | ret; | |
613 | } | |
614 | ||
e413e7e1 AL |
615 | static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = { |
616 | { "in_good_octets", 8, 0x00, }, | |
617 | { "in_bad_octets", 4, 0x02, }, | |
618 | { "in_unicast", 4, 0x04, }, | |
619 | { "in_broadcasts", 4, 0x06, }, | |
620 | { "in_multicasts", 4, 0x07, }, | |
621 | { "in_pause", 4, 0x16, }, | |
622 | { "in_undersize", 4, 0x18, }, | |
623 | { "in_fragments", 4, 0x19, }, | |
624 | { "in_oversize", 4, 0x1a, }, | |
625 | { "in_jabber", 4, 0x1b, }, | |
626 | { "in_rx_error", 4, 0x1c, }, | |
627 | { "in_fcs_error", 4, 0x1d, }, | |
628 | { "out_octets", 8, 0x0e, }, | |
629 | { "out_unicast", 4, 0x10, }, | |
630 | { "out_broadcasts", 4, 0x13, }, | |
631 | { "out_multicasts", 4, 0x12, }, | |
632 | { "out_pause", 4, 0x15, }, | |
633 | { "excessive", 4, 0x11, }, | |
634 | { "collisions", 4, 0x1e, }, | |
635 | { "deferred", 4, 0x05, }, | |
636 | { "single", 4, 0x14, }, | |
637 | { "multiple", 4, 0x17, }, | |
638 | { "out_fcs_error", 4, 0x03, }, | |
639 | { "late", 4, 0x1f, }, | |
640 | { "hist_64bytes", 4, 0x08, }, | |
641 | { "hist_65_127bytes", 4, 0x09, }, | |
642 | { "hist_128_255bytes", 4, 0x0a, }, | |
643 | { "hist_256_511bytes", 4, 0x0b, }, | |
644 | { "hist_512_1023bytes", 4, 0x0c, }, | |
645 | { "hist_1024_max_bytes", 4, 0x0d, }, | |
646 | /* Not all devices have the following counters */ | |
647 | { "sw_in_discards", 4, 0x110, }, | |
648 | { "sw_in_filtered", 2, 0x112, }, | |
649 | { "sw_out_filtered", 2, 0x113, }, | |
650 | ||
651 | }; | |
652 | ||
653 | static bool have_sw_in_discards(struct dsa_switch *ds) | |
654 | { | |
655 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
656 | ||
657 | switch (ps->id) { | |
cca8b133 AL |
658 | case PORT_SWITCH_ID_6095: case PORT_SWITCH_ID_6161: |
659 | case PORT_SWITCH_ID_6165: case PORT_SWITCH_ID_6171: | |
660 | case PORT_SWITCH_ID_6172: case PORT_SWITCH_ID_6176: | |
661 | case PORT_SWITCH_ID_6182: case PORT_SWITCH_ID_6185: | |
662 | case PORT_SWITCH_ID_6352: | |
e413e7e1 AL |
663 | return true; |
664 | default: | |
665 | return false; | |
666 | } | |
667 | } | |
668 | ||
669 | static void _mv88e6xxx_get_strings(struct dsa_switch *ds, | |
670 | int nr_stats, | |
671 | struct mv88e6xxx_hw_stat *stats, | |
672 | int port, uint8_t *data) | |
91da11f8 LB |
673 | { |
674 | int i; | |
675 | ||
676 | for (i = 0; i < nr_stats; i++) { | |
677 | memcpy(data + i * ETH_GSTRING_LEN, | |
678 | stats[i].string, ETH_GSTRING_LEN); | |
679 | } | |
680 | } | |
681 | ||
e413e7e1 AL |
682 | static void _mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, |
683 | int nr_stats, | |
684 | struct mv88e6xxx_hw_stat *stats, | |
685 | int port, uint64_t *data) | |
91da11f8 | 686 | { |
a22adce5 | 687 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); |
91da11f8 LB |
688 | int ret; |
689 | int i; | |
690 | ||
31888234 | 691 | mutex_lock(&ps->smi_mutex); |
91da11f8 | 692 | |
31888234 | 693 | ret = _mv88e6xxx_stats_snapshot(ds, port); |
91da11f8 | 694 | if (ret < 0) { |
31888234 | 695 | mutex_unlock(&ps->smi_mutex); |
91da11f8 LB |
696 | return; |
697 | } | |
698 | ||
3675c8d7 | 699 | /* Read each of the counters. */ |
91da11f8 LB |
700 | for (i = 0; i < nr_stats; i++) { |
701 | struct mv88e6xxx_hw_stat *s = stats + i; | |
702 | u32 low; | |
17ee3e04 GR |
703 | u32 high = 0; |
704 | ||
705 | if (s->reg >= 0x100) { | |
17ee3e04 GR |
706 | ret = mv88e6xxx_reg_read(ds, REG_PORT(port), |
707 | s->reg - 0x100); | |
708 | if (ret < 0) | |
709 | goto error; | |
710 | low = ret; | |
711 | if (s->sizeof_stat == 4) { | |
31888234 AL |
712 | ret = _mv88e6xxx_reg_read(ds, REG_PORT(port), |
713 | s->reg - 0x100 + 1); | |
17ee3e04 GR |
714 | if (ret < 0) |
715 | goto error; | |
716 | high = ret; | |
717 | } | |
718 | data[i] = (((u64)high) << 16) | low; | |
719 | continue; | |
720 | } | |
31888234 | 721 | _mv88e6xxx_stats_read(ds, s->reg, &low); |
91da11f8 | 722 | if (s->sizeof_stat == 8) |
31888234 | 723 | _mv88e6xxx_stats_read(ds, s->reg + 1, &high); |
91da11f8 LB |
724 | |
725 | data[i] = (((u64)high) << 32) | low; | |
726 | } | |
17ee3e04 | 727 | error: |
31888234 | 728 | mutex_unlock(&ps->smi_mutex); |
91da11f8 | 729 | } |
98e67308 | 730 | |
e413e7e1 AL |
731 | /* All the statistics in the table */ |
732 | void | |
733 | mv88e6xxx_get_strings(struct dsa_switch *ds, int port, uint8_t *data) | |
734 | { | |
735 | if (have_sw_in_discards(ds)) | |
736 | _mv88e6xxx_get_strings(ds, ARRAY_SIZE(mv88e6xxx_hw_stats), | |
737 | mv88e6xxx_hw_stats, port, data); | |
738 | else | |
739 | _mv88e6xxx_get_strings(ds, ARRAY_SIZE(mv88e6xxx_hw_stats) - 3, | |
740 | mv88e6xxx_hw_stats, port, data); | |
741 | } | |
742 | ||
743 | int mv88e6xxx_get_sset_count(struct dsa_switch *ds) | |
744 | { | |
745 | if (have_sw_in_discards(ds)) | |
746 | return ARRAY_SIZE(mv88e6xxx_hw_stats); | |
747 | return ARRAY_SIZE(mv88e6xxx_hw_stats) - 3; | |
748 | } | |
749 | ||
750 | void | |
751 | mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, | |
752 | int port, uint64_t *data) | |
753 | { | |
754 | if (have_sw_in_discards(ds)) | |
755 | _mv88e6xxx_get_ethtool_stats( | |
756 | ds, ARRAY_SIZE(mv88e6xxx_hw_stats), | |
757 | mv88e6xxx_hw_stats, port, data); | |
758 | else | |
759 | _mv88e6xxx_get_ethtool_stats( | |
760 | ds, ARRAY_SIZE(mv88e6xxx_hw_stats) - 3, | |
761 | mv88e6xxx_hw_stats, port, data); | |
762 | } | |
763 | ||
a1ab91f3 GR |
764 | int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port) |
765 | { | |
766 | return 32 * sizeof(u16); | |
767 | } | |
768 | ||
769 | void mv88e6xxx_get_regs(struct dsa_switch *ds, int port, | |
770 | struct ethtool_regs *regs, void *_p) | |
771 | { | |
772 | u16 *p = _p; | |
773 | int i; | |
774 | ||
775 | regs->version = 0; | |
776 | ||
777 | memset(p, 0xff, 32 * sizeof(u16)); | |
778 | ||
779 | for (i = 0; i < 32; i++) { | |
780 | int ret; | |
781 | ||
782 | ret = mv88e6xxx_reg_read(ds, REG_PORT(port), i); | |
783 | if (ret >= 0) | |
784 | p[i] = ret; | |
785 | } | |
786 | } | |
787 | ||
eaa23765 AL |
788 | #ifdef CONFIG_NET_DSA_HWMON |
789 | ||
790 | int mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp) | |
791 | { | |
792 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
793 | int ret; | |
794 | int val; | |
795 | ||
796 | *temp = 0; | |
797 | ||
3898c148 | 798 | mutex_lock(&ps->smi_mutex); |
eaa23765 | 799 | |
fd3a0ee4 | 800 | ret = _mv88e6xxx_phy_write(ds, 0x0, 0x16, 0x6); |
eaa23765 AL |
801 | if (ret < 0) |
802 | goto error; | |
803 | ||
804 | /* Enable temperature sensor */ | |
fd3a0ee4 | 805 | ret = _mv88e6xxx_phy_read(ds, 0x0, 0x1a); |
eaa23765 AL |
806 | if (ret < 0) |
807 | goto error; | |
808 | ||
fd3a0ee4 | 809 | ret = _mv88e6xxx_phy_write(ds, 0x0, 0x1a, ret | (1 << 5)); |
eaa23765 AL |
810 | if (ret < 0) |
811 | goto error; | |
812 | ||
813 | /* Wait for temperature to stabilize */ | |
814 | usleep_range(10000, 12000); | |
815 | ||
fd3a0ee4 | 816 | val = _mv88e6xxx_phy_read(ds, 0x0, 0x1a); |
eaa23765 AL |
817 | if (val < 0) { |
818 | ret = val; | |
819 | goto error; | |
820 | } | |
821 | ||
822 | /* Disable temperature sensor */ | |
fd3a0ee4 | 823 | ret = _mv88e6xxx_phy_write(ds, 0x0, 0x1a, ret & ~(1 << 5)); |
eaa23765 AL |
824 | if (ret < 0) |
825 | goto error; | |
826 | ||
827 | *temp = ((val & 0x1f) - 5) * 5; | |
828 | ||
829 | error: | |
fd3a0ee4 | 830 | _mv88e6xxx_phy_write(ds, 0x0, 0x16, 0x0); |
3898c148 | 831 | mutex_unlock(&ps->smi_mutex); |
eaa23765 AL |
832 | return ret; |
833 | } | |
834 | #endif /* CONFIG_NET_DSA_HWMON */ | |
835 | ||
3898c148 AL |
836 | /* Must be called with SMI lock held */ |
837 | static int _mv88e6xxx_wait(struct dsa_switch *ds, int reg, int offset, | |
838 | u16 mask) | |
f3044683 AL |
839 | { |
840 | unsigned long timeout = jiffies + HZ / 10; | |
841 | ||
842 | while (time_before(jiffies, timeout)) { | |
843 | int ret; | |
844 | ||
3898c148 AL |
845 | ret = _mv88e6xxx_reg_read(ds, reg, offset); |
846 | if (ret < 0) | |
847 | return ret; | |
f3044683 AL |
848 | if (!(ret & mask)) |
849 | return 0; | |
850 | ||
851 | usleep_range(1000, 2000); | |
852 | } | |
853 | return -ETIMEDOUT; | |
854 | } | |
855 | ||
3898c148 AL |
856 | static int mv88e6xxx_wait(struct dsa_switch *ds, int reg, int offset, u16 mask) |
857 | { | |
858 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
859 | int ret; | |
860 | ||
861 | mutex_lock(&ps->smi_mutex); | |
862 | ret = _mv88e6xxx_wait(ds, reg, offset, mask); | |
863 | mutex_unlock(&ps->smi_mutex); | |
864 | ||
865 | return ret; | |
866 | } | |
867 | ||
868 | static int _mv88e6xxx_phy_wait(struct dsa_switch *ds) | |
f3044683 | 869 | { |
3898c148 AL |
870 | return _mv88e6xxx_wait(ds, REG_GLOBAL2, GLOBAL2_SMI_OP, |
871 | GLOBAL2_SMI_OP_BUSY); | |
f3044683 AL |
872 | } |
873 | ||
874 | int mv88e6xxx_eeprom_load_wait(struct dsa_switch *ds) | |
875 | { | |
cca8b133 AL |
876 | return mv88e6xxx_wait(ds, REG_GLOBAL2, GLOBAL2_EEPROM_OP, |
877 | GLOBAL2_EEPROM_OP_LOAD); | |
f3044683 AL |
878 | } |
879 | ||
880 | int mv88e6xxx_eeprom_busy_wait(struct dsa_switch *ds) | |
881 | { | |
cca8b133 AL |
882 | return mv88e6xxx_wait(ds, REG_GLOBAL2, GLOBAL2_EEPROM_OP, |
883 | GLOBAL2_EEPROM_OP_BUSY); | |
f3044683 AL |
884 | } |
885 | ||
facd95b2 GR |
886 | /* Must be called with SMI lock held */ |
887 | static int _mv88e6xxx_atu_wait(struct dsa_switch *ds) | |
888 | { | |
cca8b133 AL |
889 | return _mv88e6xxx_wait(ds, REG_GLOBAL, GLOBAL_ATU_OP, |
890 | GLOBAL_ATU_OP_BUSY); | |
facd95b2 GR |
891 | } |
892 | ||
3898c148 | 893 | /* Must be called with SMI mutex held */ |
fd3a0ee4 AL |
894 | static int _mv88e6xxx_phy_read_indirect(struct dsa_switch *ds, int addr, |
895 | int regnum) | |
f3044683 AL |
896 | { |
897 | int ret; | |
898 | ||
3898c148 AL |
899 | ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_SMI_OP, |
900 | GLOBAL2_SMI_OP_22_READ | (addr << 5) | | |
901 | regnum); | |
902 | if (ret < 0) | |
903 | return ret; | |
f3044683 | 904 | |
3898c148 | 905 | ret = _mv88e6xxx_phy_wait(ds); |
f3044683 AL |
906 | if (ret < 0) |
907 | return ret; | |
908 | ||
3898c148 | 909 | return _mv88e6xxx_reg_read(ds, REG_GLOBAL2, GLOBAL2_SMI_DATA); |
f3044683 AL |
910 | } |
911 | ||
3898c148 | 912 | /* Must be called with SMI mutex held */ |
fd3a0ee4 AL |
913 | static int _mv88e6xxx_phy_write_indirect(struct dsa_switch *ds, int addr, |
914 | int regnum, u16 val) | |
f3044683 | 915 | { |
3898c148 AL |
916 | int ret; |
917 | ||
918 | ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_SMI_DATA, val); | |
919 | if (ret < 0) | |
920 | return ret; | |
f3044683 | 921 | |
3898c148 AL |
922 | ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_SMI_OP, |
923 | GLOBAL2_SMI_OP_22_WRITE | (addr << 5) | | |
924 | regnum); | |
925 | ||
926 | return _mv88e6xxx_phy_wait(ds); | |
f3044683 AL |
927 | } |
928 | ||
11b3b45d GR |
929 | int mv88e6xxx_get_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e) |
930 | { | |
2f40c698 | 931 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); |
11b3b45d GR |
932 | int reg; |
933 | ||
3898c148 | 934 | mutex_lock(&ps->smi_mutex); |
2f40c698 AL |
935 | |
936 | reg = _mv88e6xxx_phy_read_indirect(ds, port, 16); | |
11b3b45d | 937 | if (reg < 0) |
2f40c698 | 938 | goto out; |
11b3b45d GR |
939 | |
940 | e->eee_enabled = !!(reg & 0x0200); | |
941 | e->tx_lpi_enabled = !!(reg & 0x0100); | |
942 | ||
3898c148 | 943 | reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_STATUS); |
11b3b45d | 944 | if (reg < 0) |
2f40c698 | 945 | goto out; |
11b3b45d | 946 | |
cca8b133 | 947 | e->eee_active = !!(reg & PORT_STATUS_EEE); |
2f40c698 | 948 | reg = 0; |
11b3b45d | 949 | |
2f40c698 | 950 | out: |
3898c148 | 951 | mutex_unlock(&ps->smi_mutex); |
2f40c698 | 952 | return reg; |
11b3b45d GR |
953 | } |
954 | ||
955 | int mv88e6xxx_set_eee(struct dsa_switch *ds, int port, | |
956 | struct phy_device *phydev, struct ethtool_eee *e) | |
957 | { | |
2f40c698 AL |
958 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); |
959 | int reg; | |
11b3b45d GR |
960 | int ret; |
961 | ||
3898c148 | 962 | mutex_lock(&ps->smi_mutex); |
11b3b45d | 963 | |
2f40c698 AL |
964 | ret = _mv88e6xxx_phy_read_indirect(ds, port, 16); |
965 | if (ret < 0) | |
966 | goto out; | |
967 | ||
968 | reg = ret & ~0x0300; | |
969 | if (e->eee_enabled) | |
970 | reg |= 0x0200; | |
971 | if (e->tx_lpi_enabled) | |
972 | reg |= 0x0100; | |
973 | ||
974 | ret = _mv88e6xxx_phy_write_indirect(ds, port, 16, reg); | |
975 | out: | |
3898c148 | 976 | mutex_unlock(&ps->smi_mutex); |
2f40c698 AL |
977 | |
978 | return ret; | |
11b3b45d GR |
979 | } |
980 | ||
facd95b2 GR |
981 | static int _mv88e6xxx_atu_cmd(struct dsa_switch *ds, int fid, u16 cmd) |
982 | { | |
983 | int ret; | |
984 | ||
985 | ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, 0x01, fid); | |
986 | if (ret < 0) | |
987 | return ret; | |
988 | ||
cca8b133 | 989 | ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_OP, cmd); |
facd95b2 GR |
990 | if (ret < 0) |
991 | return ret; | |
992 | ||
993 | return _mv88e6xxx_atu_wait(ds); | |
994 | } | |
995 | ||
996 | static int _mv88e6xxx_flush_fid(struct dsa_switch *ds, int fid) | |
997 | { | |
998 | int ret; | |
999 | ||
1000 | ret = _mv88e6xxx_atu_wait(ds); | |
1001 | if (ret < 0) | |
1002 | return ret; | |
1003 | ||
cca8b133 | 1004 | return _mv88e6xxx_atu_cmd(ds, fid, GLOBAL_ATU_OP_FLUSH_NON_STATIC_DB); |
facd95b2 GR |
1005 | } |
1006 | ||
1007 | static int mv88e6xxx_set_port_state(struct dsa_switch *ds, int port, u8 state) | |
1008 | { | |
1009 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
c3ffe6d2 | 1010 | int reg, ret = 0; |
facd95b2 GR |
1011 | u8 oldstate; |
1012 | ||
1013 | mutex_lock(&ps->smi_mutex); | |
1014 | ||
cca8b133 | 1015 | reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_CONTROL); |
538cc282 GR |
1016 | if (reg < 0) { |
1017 | ret = reg; | |
facd95b2 | 1018 | goto abort; |
538cc282 | 1019 | } |
facd95b2 | 1020 | |
cca8b133 | 1021 | oldstate = reg & PORT_CONTROL_STATE_MASK; |
facd95b2 GR |
1022 | if (oldstate != state) { |
1023 | /* Flush forwarding database if we're moving a port | |
1024 | * from Learning or Forwarding state to Disabled or | |
1025 | * Blocking or Listening state. | |
1026 | */ | |
cca8b133 AL |
1027 | if (oldstate >= PORT_CONTROL_STATE_LEARNING && |
1028 | state <= PORT_CONTROL_STATE_BLOCKING) { | |
facd95b2 GR |
1029 | ret = _mv88e6xxx_flush_fid(ds, ps->fid[port]); |
1030 | if (ret) | |
1031 | goto abort; | |
1032 | } | |
cca8b133 AL |
1033 | reg = (reg & ~PORT_CONTROL_STATE_MASK) | state; |
1034 | ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_CONTROL, | |
1035 | reg); | |
facd95b2 GR |
1036 | } |
1037 | ||
1038 | abort: | |
1039 | mutex_unlock(&ps->smi_mutex); | |
1040 | return ret; | |
1041 | } | |
1042 | ||
1043 | /* Must be called with smi lock held */ | |
1044 | static int _mv88e6xxx_update_port_config(struct dsa_switch *ds, int port) | |
1045 | { | |
1046 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
1047 | u8 fid = ps->fid[port]; | |
1048 | u16 reg = fid << 12; | |
1049 | ||
1050 | if (dsa_is_cpu_port(ds, port)) | |
1051 | reg |= ds->phys_port_mask; | |
1052 | else | |
1053 | reg |= (ps->bridge_mask[fid] | | |
1054 | (1 << dsa_upstream_port(ds))) & ~(1 << port); | |
1055 | ||
cca8b133 | 1056 | return _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_BASE_VLAN, reg); |
facd95b2 GR |
1057 | } |
1058 | ||
1059 | /* Must be called with smi lock held */ | |
1060 | static int _mv88e6xxx_update_bridge_config(struct dsa_switch *ds, int fid) | |
1061 | { | |
1062 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
1063 | int port; | |
1064 | u32 mask; | |
1065 | int ret; | |
1066 | ||
1067 | mask = ds->phys_port_mask; | |
1068 | while (mask) { | |
1069 | port = __ffs(mask); | |
1070 | mask &= ~(1 << port); | |
1071 | if (ps->fid[port] != fid) | |
1072 | continue; | |
1073 | ||
1074 | ret = _mv88e6xxx_update_port_config(ds, port); | |
1075 | if (ret) | |
1076 | return ret; | |
1077 | } | |
1078 | ||
1079 | return _mv88e6xxx_flush_fid(ds, fid); | |
1080 | } | |
1081 | ||
1082 | /* Bridge handling functions */ | |
1083 | ||
1084 | int mv88e6xxx_join_bridge(struct dsa_switch *ds, int port, u32 br_port_mask) | |
1085 | { | |
1086 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
1087 | int ret = 0; | |
1088 | u32 nmask; | |
1089 | int fid; | |
1090 | ||
1091 | /* If the bridge group is not empty, join that group. | |
1092 | * Otherwise create a new group. | |
1093 | */ | |
1094 | fid = ps->fid[port]; | |
1095 | nmask = br_port_mask & ~(1 << port); | |
1096 | if (nmask) | |
1097 | fid = ps->fid[__ffs(nmask)]; | |
1098 | ||
1099 | nmask = ps->bridge_mask[fid] | (1 << port); | |
1100 | if (nmask != br_port_mask) { | |
1101 | netdev_err(ds->ports[port], | |
1102 | "join: Bridge port mask mismatch fid=%d mask=0x%x expected 0x%x\n", | |
1103 | fid, br_port_mask, nmask); | |
1104 | return -EINVAL; | |
1105 | } | |
1106 | ||
1107 | mutex_lock(&ps->smi_mutex); | |
1108 | ||
1109 | ps->bridge_mask[fid] = br_port_mask; | |
1110 | ||
1111 | if (fid != ps->fid[port]) { | |
1112 | ps->fid_mask |= 1 << ps->fid[port]; | |
1113 | ps->fid[port] = fid; | |
1114 | ret = _mv88e6xxx_update_bridge_config(ds, fid); | |
1115 | } | |
1116 | ||
1117 | mutex_unlock(&ps->smi_mutex); | |
1118 | ||
1119 | return ret; | |
1120 | } | |
1121 | ||
1122 | int mv88e6xxx_leave_bridge(struct dsa_switch *ds, int port, u32 br_port_mask) | |
1123 | { | |
1124 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
1125 | u8 fid, newfid; | |
1126 | int ret; | |
1127 | ||
1128 | fid = ps->fid[port]; | |
1129 | ||
1130 | if (ps->bridge_mask[fid] != br_port_mask) { | |
1131 | netdev_err(ds->ports[port], | |
1132 | "leave: Bridge port mask mismatch fid=%d mask=0x%x expected 0x%x\n", | |
1133 | fid, br_port_mask, ps->bridge_mask[fid]); | |
1134 | return -EINVAL; | |
1135 | } | |
1136 | ||
1137 | /* If the port was the last port of a bridge, we are done. | |
1138 | * Otherwise assign a new fid to the port, and fix up | |
1139 | * the bridge configuration. | |
1140 | */ | |
1141 | if (br_port_mask == (1 << port)) | |
1142 | return 0; | |
1143 | ||
1144 | mutex_lock(&ps->smi_mutex); | |
1145 | ||
1146 | newfid = __ffs(ps->fid_mask); | |
1147 | ps->fid[port] = newfid; | |
1148 | ps->fid_mask &= (1 << newfid); | |
1149 | ps->bridge_mask[fid] &= ~(1 << port); | |
1150 | ps->bridge_mask[newfid] = 1 << port; | |
1151 | ||
1152 | ret = _mv88e6xxx_update_bridge_config(ds, fid); | |
1153 | if (!ret) | |
1154 | ret = _mv88e6xxx_update_bridge_config(ds, newfid); | |
1155 | ||
1156 | mutex_unlock(&ps->smi_mutex); | |
1157 | ||
1158 | return ret; | |
1159 | } | |
1160 | ||
1161 | int mv88e6xxx_port_stp_update(struct dsa_switch *ds, int port, u8 state) | |
1162 | { | |
1163 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
1164 | int stp_state; | |
1165 | ||
1166 | switch (state) { | |
1167 | case BR_STATE_DISABLED: | |
cca8b133 | 1168 | stp_state = PORT_CONTROL_STATE_DISABLED; |
facd95b2 GR |
1169 | break; |
1170 | case BR_STATE_BLOCKING: | |
1171 | case BR_STATE_LISTENING: | |
cca8b133 | 1172 | stp_state = PORT_CONTROL_STATE_BLOCKING; |
facd95b2 GR |
1173 | break; |
1174 | case BR_STATE_LEARNING: | |
cca8b133 | 1175 | stp_state = PORT_CONTROL_STATE_LEARNING; |
facd95b2 GR |
1176 | break; |
1177 | case BR_STATE_FORWARDING: | |
1178 | default: | |
cca8b133 | 1179 | stp_state = PORT_CONTROL_STATE_FORWARDING; |
facd95b2 GR |
1180 | break; |
1181 | } | |
1182 | ||
1183 | netdev_dbg(ds->ports[port], "port state %d [%d]\n", state, stp_state); | |
1184 | ||
1185 | /* mv88e6xxx_port_stp_update may be called with softirqs disabled, | |
1186 | * so we can not update the port state directly but need to schedule it. | |
1187 | */ | |
1188 | ps->port_state[port] = stp_state; | |
1189 | set_bit(port, &ps->port_state_update_mask); | |
1190 | schedule_work(&ps->bridge_work); | |
1191 | ||
1192 | return 0; | |
1193 | } | |
1194 | ||
defb05b9 GR |
1195 | static int __mv88e6xxx_write_addr(struct dsa_switch *ds, |
1196 | const unsigned char *addr) | |
1197 | { | |
1198 | int i, ret; | |
1199 | ||
1200 | for (i = 0; i < 3; i++) { | |
cca8b133 AL |
1201 | ret = _mv88e6xxx_reg_write( |
1202 | ds, REG_GLOBAL, GLOBAL_ATU_MAC_01 + i, | |
1203 | (addr[i * 2] << 8) | addr[i * 2 + 1]); | |
defb05b9 GR |
1204 | if (ret < 0) |
1205 | return ret; | |
1206 | } | |
1207 | ||
1208 | return 0; | |
1209 | } | |
1210 | ||
1211 | static int __mv88e6xxx_read_addr(struct dsa_switch *ds, unsigned char *addr) | |
1212 | { | |
1213 | int i, ret; | |
1214 | ||
1215 | for (i = 0; i < 3; i++) { | |
cca8b133 AL |
1216 | ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, |
1217 | GLOBAL_ATU_MAC_01 + i); | |
defb05b9 GR |
1218 | if (ret < 0) |
1219 | return ret; | |
1220 | addr[i * 2] = ret >> 8; | |
1221 | addr[i * 2 + 1] = ret & 0xff; | |
1222 | } | |
1223 | ||
1224 | return 0; | |
1225 | } | |
1226 | ||
1227 | static int __mv88e6xxx_port_fdb_cmd(struct dsa_switch *ds, int port, | |
1228 | const unsigned char *addr, int state) | |
1229 | { | |
1230 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
1231 | u8 fid = ps->fid[port]; | |
1232 | int ret; | |
1233 | ||
1234 | ret = _mv88e6xxx_atu_wait(ds); | |
1235 | if (ret < 0) | |
1236 | return ret; | |
1237 | ||
1238 | ret = __mv88e6xxx_write_addr(ds, addr); | |
1239 | if (ret < 0) | |
1240 | return ret; | |
1241 | ||
cca8b133 | 1242 | ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_DATA, |
defb05b9 GR |
1243 | (0x10 << port) | state); |
1244 | if (ret) | |
1245 | return ret; | |
1246 | ||
cca8b133 | 1247 | ret = _mv88e6xxx_atu_cmd(ds, fid, GLOBAL_ATU_OP_LOAD_DB); |
defb05b9 GR |
1248 | |
1249 | return ret; | |
1250 | } | |
1251 | ||
1252 | int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port, | |
1253 | const unsigned char *addr, u16 vid) | |
1254 | { | |
1255 | int state = is_multicast_ether_addr(addr) ? | |
cca8b133 AL |
1256 | GLOBAL_ATU_DATA_STATE_MC_STATIC : |
1257 | GLOBAL_ATU_DATA_STATE_UC_STATIC; | |
defb05b9 GR |
1258 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); |
1259 | int ret; | |
1260 | ||
1261 | mutex_lock(&ps->smi_mutex); | |
1262 | ret = __mv88e6xxx_port_fdb_cmd(ds, port, addr, state); | |
1263 | mutex_unlock(&ps->smi_mutex); | |
1264 | ||
1265 | return ret; | |
1266 | } | |
1267 | ||
1268 | int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port, | |
1269 | const unsigned char *addr, u16 vid) | |
1270 | { | |
1271 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
1272 | int ret; | |
1273 | ||
1274 | mutex_lock(&ps->smi_mutex); | |
cca8b133 AL |
1275 | ret = __mv88e6xxx_port_fdb_cmd(ds, port, addr, |
1276 | GLOBAL_ATU_DATA_STATE_UNUSED); | |
defb05b9 GR |
1277 | mutex_unlock(&ps->smi_mutex); |
1278 | ||
1279 | return ret; | |
1280 | } | |
1281 | ||
1282 | static int __mv88e6xxx_port_getnext(struct dsa_switch *ds, int port, | |
1283 | unsigned char *addr, bool *is_static) | |
1284 | { | |
1285 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
1286 | u8 fid = ps->fid[port]; | |
1287 | int ret, state; | |
1288 | ||
1289 | ret = _mv88e6xxx_atu_wait(ds); | |
1290 | if (ret < 0) | |
1291 | return ret; | |
1292 | ||
1293 | ret = __mv88e6xxx_write_addr(ds, addr); | |
1294 | if (ret < 0) | |
1295 | return ret; | |
1296 | ||
1297 | do { | |
cca8b133 | 1298 | ret = _mv88e6xxx_atu_cmd(ds, fid, GLOBAL_ATU_OP_GET_NEXT_DB); |
defb05b9 GR |
1299 | if (ret < 0) |
1300 | return ret; | |
1301 | ||
cca8b133 | 1302 | ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_ATU_DATA); |
defb05b9 GR |
1303 | if (ret < 0) |
1304 | return ret; | |
cca8b133 AL |
1305 | state = ret & GLOBAL_ATU_DATA_STATE_MASK; |
1306 | if (state == GLOBAL_ATU_DATA_STATE_UNUSED) | |
defb05b9 GR |
1307 | return -ENOENT; |
1308 | } while (!(((ret >> 4) & 0xff) & (1 << port))); | |
1309 | ||
1310 | ret = __mv88e6xxx_read_addr(ds, addr); | |
1311 | if (ret < 0) | |
1312 | return ret; | |
1313 | ||
1314 | *is_static = state == (is_multicast_ether_addr(addr) ? | |
cca8b133 AL |
1315 | GLOBAL_ATU_DATA_STATE_MC_STATIC : |
1316 | GLOBAL_ATU_DATA_STATE_UC_STATIC); | |
defb05b9 GR |
1317 | |
1318 | return 0; | |
1319 | } | |
1320 | ||
1321 | /* get next entry for port */ | |
1322 | int mv88e6xxx_port_fdb_getnext(struct dsa_switch *ds, int port, | |
1323 | unsigned char *addr, bool *is_static) | |
1324 | { | |
1325 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
1326 | int ret; | |
1327 | ||
1328 | mutex_lock(&ps->smi_mutex); | |
1329 | ret = __mv88e6xxx_port_getnext(ds, port, addr, is_static); | |
1330 | mutex_unlock(&ps->smi_mutex); | |
1331 | ||
1332 | return ret; | |
1333 | } | |
1334 | ||
facd95b2 GR |
1335 | static void mv88e6xxx_bridge_work(struct work_struct *work) |
1336 | { | |
1337 | struct mv88e6xxx_priv_state *ps; | |
1338 | struct dsa_switch *ds; | |
1339 | int port; | |
1340 | ||
1341 | ps = container_of(work, struct mv88e6xxx_priv_state, bridge_work); | |
1342 | ds = ((struct dsa_switch *)ps) - 1; | |
1343 | ||
1344 | while (ps->port_state_update_mask) { | |
1345 | port = __ffs(ps->port_state_update_mask); | |
1346 | clear_bit(port, &ps->port_state_update_mask); | |
1347 | mv88e6xxx_set_port_state(ds, port, ps->port_state[port]); | |
1348 | } | |
1349 | } | |
1350 | ||
dbde9e66 | 1351 | static int mv88e6xxx_setup_port(struct dsa_switch *ds, int port) |
d827e88a GR |
1352 | { |
1353 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
facd95b2 | 1354 | int ret, fid; |
54d792f2 | 1355 | u16 reg; |
d827e88a GR |
1356 | |
1357 | mutex_lock(&ps->smi_mutex); | |
1358 | ||
54d792f2 AL |
1359 | if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) || |
1360 | mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) || | |
1361 | mv88e6xxx_6185_family(ds) || mv88e6xxx_6095_family(ds) || | |
1362 | mv88e6xxx_6065_family(ds)) { | |
1363 | /* MAC Forcing register: don't force link, speed, | |
1364 | * duplex or flow control state to any particular | |
1365 | * values on physical ports, but force the CPU port | |
1366 | * and all DSA ports to their maximum bandwidth and | |
1367 | * full duplex. | |
1368 | */ | |
1369 | reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_PCS_CTRL); | |
1370 | if (dsa_is_cpu_port(ds, port) || | |
1371 | ds->dsa_port_mask & (1 << port)) { | |
1372 | reg |= PORT_PCS_CTRL_FORCE_LINK | | |
1373 | PORT_PCS_CTRL_LINK_UP | | |
1374 | PORT_PCS_CTRL_DUPLEX_FULL | | |
1375 | PORT_PCS_CTRL_FORCE_DUPLEX; | |
1376 | if (mv88e6xxx_6065_family(ds)) | |
1377 | reg |= PORT_PCS_CTRL_100; | |
1378 | else | |
1379 | reg |= PORT_PCS_CTRL_1000; | |
1380 | } else { | |
1381 | reg |= PORT_PCS_CTRL_UNFORCED; | |
1382 | } | |
1383 | ||
1384 | ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), | |
1385 | PORT_PCS_CTRL, reg); | |
1386 | if (ret) | |
1387 | goto abort; | |
1388 | } | |
1389 | ||
1390 | /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock, | |
1391 | * disable Header mode, enable IGMP/MLD snooping, disable VLAN | |
1392 | * tunneling, determine priority by looking at 802.1p and IP | |
1393 | * priority fields (IP prio has precedence), and set STP state | |
1394 | * to Forwarding. | |
1395 | * | |
1396 | * If this is the CPU link, use DSA or EDSA tagging depending | |
1397 | * on which tagging mode was configured. | |
1398 | * | |
1399 | * If this is a link to another switch, use DSA tagging mode. | |
1400 | * | |
1401 | * If this is the upstream port for this switch, enable | |
1402 | * forwarding of unknown unicasts and multicasts. | |
1403 | */ | |
1404 | reg = 0; | |
1405 | if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) || | |
1406 | mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) || | |
1407 | mv88e6xxx_6095_family(ds) || mv88e6xxx_6065_family(ds) || | |
1408 | mv88e6xxx_6185_family(ds)) | |
1409 | reg = PORT_CONTROL_IGMP_MLD_SNOOP | | |
1410 | PORT_CONTROL_USE_TAG | PORT_CONTROL_USE_IP | | |
1411 | PORT_CONTROL_STATE_FORWARDING; | |
1412 | if (dsa_is_cpu_port(ds, port)) { | |
1413 | if (mv88e6xxx_6095_family(ds) || mv88e6xxx_6185_family(ds)) | |
1414 | reg |= PORT_CONTROL_DSA_TAG; | |
1415 | if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) || | |
1416 | mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds)) { | |
1417 | if (ds->dst->tag_protocol == DSA_TAG_PROTO_EDSA) | |
1418 | reg |= PORT_CONTROL_FRAME_ETHER_TYPE_DSA; | |
1419 | else | |
1420 | reg |= PORT_CONTROL_FRAME_MODE_DSA; | |
1421 | } | |
1422 | ||
1423 | if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) || | |
1424 | mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) || | |
1425 | mv88e6xxx_6095_family(ds) || mv88e6xxx_6065_family(ds) || | |
1426 | mv88e6xxx_6185_family(ds)) { | |
1427 | if (ds->dst->tag_protocol == DSA_TAG_PROTO_EDSA) | |
1428 | reg |= PORT_CONTROL_EGRESS_ADD_TAG; | |
1429 | } | |
1430 | } | |
1431 | if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) || | |
1432 | mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) || | |
1433 | mv88e6xxx_6095_family(ds) || mv88e6xxx_6065_family(ds)) { | |
1434 | if (ds->dsa_port_mask & (1 << port)) | |
1435 | reg |= PORT_CONTROL_FRAME_MODE_DSA; | |
1436 | if (port == dsa_upstream_port(ds)) | |
1437 | reg |= PORT_CONTROL_FORWARD_UNKNOWN | | |
1438 | PORT_CONTROL_FORWARD_UNKNOWN_MC; | |
1439 | } | |
1440 | if (reg) { | |
1441 | ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), | |
1442 | PORT_CONTROL, reg); | |
1443 | if (ret) | |
1444 | goto abort; | |
1445 | } | |
1446 | ||
1447 | /* Port Control 2: don't force a good FCS, set the maximum | |
1448 | * frame size to 10240 bytes, don't let the switch add or | |
1449 | * strip 802.1q tags, don't discard tagged or untagged frames | |
1450 | * on this port, do a destination address lookup on all | |
1451 | * received packets as usual, disable ARP mirroring and don't | |
1452 | * send a copy of all transmitted/received frames on this port | |
1453 | * to the CPU. | |
1454 | */ | |
1455 | reg = 0; | |
1456 | if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) || | |
1457 | mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) || | |
1458 | mv88e6xxx_6095_family(ds)) | |
1459 | reg = PORT_CONTROL_2_MAP_DA; | |
1460 | ||
1461 | if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) || | |
1462 | mv88e6xxx_6165_family(ds)) | |
1463 | reg |= PORT_CONTROL_2_JUMBO_10240; | |
1464 | ||
1465 | if (mv88e6xxx_6095_family(ds) || mv88e6xxx_6185_family(ds)) { | |
1466 | /* Set the upstream port this port should use */ | |
1467 | reg |= dsa_upstream_port(ds); | |
1468 | /* enable forwarding of unknown multicast addresses to | |
1469 | * the upstream port | |
1470 | */ | |
1471 | if (port == dsa_upstream_port(ds)) | |
1472 | reg |= PORT_CONTROL_2_FORWARD_UNKNOWN; | |
1473 | } | |
1474 | ||
1475 | if (reg) { | |
1476 | ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), | |
1477 | PORT_CONTROL_2, reg); | |
1478 | if (ret) | |
1479 | goto abort; | |
1480 | } | |
1481 | ||
1482 | /* Port Association Vector: when learning source addresses | |
1483 | * of packets, add the address to the address database using | |
1484 | * a port bitmap that has only the bit for this port set and | |
1485 | * the other bits clear. | |
1486 | */ | |
1487 | ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_ASSOC_VECTOR, | |
1488 | 1 << port); | |
1489 | if (ret) | |
1490 | goto abort; | |
1491 | ||
1492 | /* Egress rate control 2: disable egress rate control. */ | |
1493 | ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_RATE_CONTROL_2, | |
1494 | 0x0000); | |
1495 | if (ret) | |
1496 | goto abort; | |
1497 | ||
1498 | if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) || | |
1499 | mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds)) { | |
1500 | /* Do not limit the period of time that this port can | |
1501 | * be paused for by the remote end or the period of | |
1502 | * time that this port can pause the remote end. | |
1503 | */ | |
1504 | ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), | |
1505 | PORT_PAUSE_CTRL, 0x0000); | |
1506 | if (ret) | |
1507 | goto abort; | |
1508 | ||
1509 | /* Port ATU control: disable limiting the number of | |
1510 | * address database entries that this port is allowed | |
1511 | * to use. | |
1512 | */ | |
1513 | ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), | |
1514 | PORT_ATU_CONTROL, 0x0000); | |
1515 | /* Priority Override: disable DA, SA and VTU priority | |
1516 | * override. | |
1517 | */ | |
1518 | ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), | |
1519 | PORT_PRI_OVERRIDE, 0x0000); | |
1520 | if (ret) | |
1521 | goto abort; | |
1522 | ||
1523 | /* Port Ethertype: use the Ethertype DSA Ethertype | |
1524 | * value. | |
1525 | */ | |
1526 | ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), | |
1527 | PORT_ETH_TYPE, ETH_P_EDSA); | |
1528 | if (ret) | |
1529 | goto abort; | |
1530 | /* Tag Remap: use an identity 802.1p prio -> switch | |
1531 | * prio mapping. | |
1532 | */ | |
1533 | ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), | |
1534 | PORT_TAG_REGMAP_0123, 0x3210); | |
1535 | if (ret) | |
1536 | goto abort; | |
1537 | ||
1538 | /* Tag Remap 2: use an identity 802.1p prio -> switch | |
1539 | * prio mapping. | |
1540 | */ | |
1541 | ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), | |
1542 | PORT_TAG_REGMAP_4567, 0x7654); | |
1543 | if (ret) | |
1544 | goto abort; | |
1545 | } | |
1546 | ||
1547 | if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) || | |
1548 | mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) || | |
1549 | mv88e6xxx_6185_family(ds) || mv88e6xxx_6095_family(ds)) { | |
1550 | /* Rate Control: disable ingress rate limiting. */ | |
1551 | ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), | |
1552 | PORT_RATE_CONTROL, 0x0001); | |
1553 | if (ret) | |
1554 | goto abort; | |
1555 | } | |
1556 | ||
366f0a0f GR |
1557 | /* Port Control 1: disable trunking, disable sending |
1558 | * learning messages to this port. | |
d827e88a | 1559 | */ |
614f03fc | 1560 | ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_CONTROL_1, 0x0000); |
d827e88a GR |
1561 | if (ret) |
1562 | goto abort; | |
1563 | ||
1564 | /* Port based VLAN map: give each port its own address | |
1565 | * database, allow the CPU port to talk to each of the 'real' | |
1566 | * ports, and allow each of the 'real' ports to only talk to | |
1567 | * the upstream port. | |
1568 | */ | |
facd95b2 GR |
1569 | fid = __ffs(ps->fid_mask); |
1570 | ps->fid[port] = fid; | |
1571 | ps->fid_mask &= ~(1 << fid); | |
1572 | ||
1573 | if (!dsa_is_cpu_port(ds, port)) | |
1574 | ps->bridge_mask[fid] = 1 << port; | |
d827e88a | 1575 | |
facd95b2 | 1576 | ret = _mv88e6xxx_update_port_config(ds, port); |
d827e88a GR |
1577 | if (ret) |
1578 | goto abort; | |
1579 | ||
1580 | /* Default VLAN ID and priority: don't set a default VLAN | |
1581 | * ID, and set the default packet priority to zero. | |
1582 | */ | |
47cf1e65 VD |
1583 | ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_DEFAULT_VLAN, |
1584 | 0x0000); | |
d827e88a GR |
1585 | abort: |
1586 | mutex_unlock(&ps->smi_mutex); | |
1587 | return ret; | |
1588 | } | |
1589 | ||
dbde9e66 AL |
1590 | int mv88e6xxx_setup_ports(struct dsa_switch *ds) |
1591 | { | |
1592 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
1593 | int ret; | |
1594 | int i; | |
1595 | ||
1596 | for (i = 0; i < ps->num_ports; i++) { | |
1597 | ret = mv88e6xxx_setup_port(ds, i); | |
1598 | if (ret < 0) | |
1599 | return ret; | |
1600 | } | |
1601 | return 0; | |
1602 | } | |
1603 | ||
acdaffcc GR |
1604 | int mv88e6xxx_setup_common(struct dsa_switch *ds) |
1605 | { | |
1606 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
1607 | ||
1608 | mutex_init(&ps->smi_mutex); | |
acdaffcc | 1609 | |
cca8b133 | 1610 | ps->id = REG_READ(REG_PORT(0), PORT_SWITCH_ID) & 0xfff0; |
a8f064c6 | 1611 | |
facd95b2 GR |
1612 | ps->fid_mask = (1 << DSA_MAX_PORTS) - 1; |
1613 | ||
1614 | INIT_WORK(&ps->bridge_work, mv88e6xxx_bridge_work); | |
1615 | ||
acdaffcc GR |
1616 | return 0; |
1617 | } | |
1618 | ||
54d792f2 AL |
1619 | int mv88e6xxx_setup_global(struct dsa_switch *ds) |
1620 | { | |
1621 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
1622 | int i; | |
1623 | ||
1624 | /* Set the default address aging time to 5 minutes, and | |
1625 | * enable address learn messages to be sent to all message | |
1626 | * ports. | |
1627 | */ | |
1628 | REG_WRITE(REG_GLOBAL, GLOBAL_ATU_CONTROL, | |
1629 | 0x0140 | GLOBAL_ATU_CONTROL_LEARN2ALL); | |
1630 | ||
1631 | /* Configure the IP ToS mapping registers. */ | |
1632 | REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_0, 0x0000); | |
1633 | REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_1, 0x0000); | |
1634 | REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_2, 0x5555); | |
1635 | REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_3, 0x5555); | |
1636 | REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_4, 0xaaaa); | |
1637 | REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_5, 0xaaaa); | |
1638 | REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_6, 0xffff); | |
1639 | REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_7, 0xffff); | |
1640 | ||
1641 | /* Configure the IEEE 802.1p priority mapping register. */ | |
1642 | REG_WRITE(REG_GLOBAL, GLOBAL_IEEE_PRI, 0xfa41); | |
1643 | ||
1644 | /* Send all frames with destination addresses matching | |
1645 | * 01:80:c2:00:00:0x to the CPU port. | |
1646 | */ | |
1647 | REG_WRITE(REG_GLOBAL2, GLOBAL2_MGMT_EN_0X, 0xffff); | |
1648 | ||
1649 | /* Ignore removed tag data on doubly tagged packets, disable | |
1650 | * flow control messages, force flow control priority to the | |
1651 | * highest, and send all special multicast frames to the CPU | |
1652 | * port at the highest priority. | |
1653 | */ | |
1654 | REG_WRITE(REG_GLOBAL2, GLOBAL2_SWITCH_MGMT, | |
1655 | 0x7 | GLOBAL2_SWITCH_MGMT_RSVD2CPU | 0x70 | | |
1656 | GLOBAL2_SWITCH_MGMT_FORCE_FLOW_CTRL_PRI); | |
1657 | ||
1658 | /* Program the DSA routing table. */ | |
1659 | for (i = 0; i < 32; i++) { | |
1660 | int nexthop = 0x1f; | |
1661 | ||
1662 | if (ds->pd->rtable && | |
1663 | i != ds->index && i < ds->dst->pd->nr_chips) | |
1664 | nexthop = ds->pd->rtable[i] & 0x1f; | |
1665 | ||
1666 | REG_WRITE(REG_GLOBAL2, GLOBAL2_DEVICE_MAPPING, | |
1667 | GLOBAL2_DEVICE_MAPPING_UPDATE | | |
1668 | (i << GLOBAL2_DEVICE_MAPPING_TARGET_SHIFT) | | |
1669 | nexthop); | |
1670 | } | |
1671 | ||
1672 | /* Clear all trunk masks. */ | |
1673 | for (i = 0; i < 8; i++) | |
1674 | REG_WRITE(REG_GLOBAL2, GLOBAL2_TRUNK_MASK, | |
1675 | 0x8000 | (i << GLOBAL2_TRUNK_MASK_NUM_SHIFT) | | |
1676 | ((1 << ps->num_ports) - 1)); | |
1677 | ||
1678 | /* Clear all trunk mappings. */ | |
1679 | for (i = 0; i < 16; i++) | |
1680 | REG_WRITE(REG_GLOBAL2, GLOBAL2_TRUNK_MAPPING, | |
1681 | GLOBAL2_TRUNK_MAPPING_UPDATE | | |
1682 | (i << GLOBAL2_TRUNK_MAPPING_ID_SHIFT)); | |
1683 | ||
1684 | if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) || | |
1685 | mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds)) { | |
1686 | /* Send all frames with destination addresses matching | |
1687 | * 01:80:c2:00:00:2x to the CPU port. | |
1688 | */ | |
1689 | REG_WRITE(REG_GLOBAL2, GLOBAL2_MGMT_EN_2X, 0xffff); | |
1690 | ||
1691 | /* Initialise cross-chip port VLAN table to reset | |
1692 | * defaults. | |
1693 | */ | |
1694 | REG_WRITE(REG_GLOBAL2, GLOBAL2_PVT_ADDR, 0x9000); | |
1695 | ||
1696 | /* Clear the priority override table. */ | |
1697 | for (i = 0; i < 16; i++) | |
1698 | REG_WRITE(REG_GLOBAL2, GLOBAL2_PRIO_OVERRIDE, | |
1699 | 0x8000 | (i << 8)); | |
1700 | } | |
1701 | ||
1702 | if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) || | |
1703 | mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) || | |
1704 | mv88e6xxx_6185_family(ds) || mv88e6xxx_6095_family(ds)) { | |
1705 | /* Disable ingress rate limiting by resetting all | |
1706 | * ingress rate limit registers to their initial | |
1707 | * state. | |
1708 | */ | |
1709 | for (i = 0; i < ps->num_ports; i++) | |
1710 | REG_WRITE(REG_GLOBAL2, GLOBAL2_INGRESS_OP, | |
1711 | 0x9000 | (i << 8)); | |
1712 | } | |
1713 | ||
1714 | return 0; | |
1715 | } | |
1716 | ||
143a8307 AL |
1717 | int mv88e6xxx_switch_reset(struct dsa_switch *ds, bool ppu_active) |
1718 | { | |
1719 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
1720 | u16 is_reset = (ppu_active ? 0x8800 : 0xc800); | |
1721 | unsigned long timeout; | |
1722 | int ret; | |
1723 | int i; | |
1724 | ||
1725 | /* Set all ports to the disabled state. */ | |
1726 | for (i = 0; i < ps->num_ports; i++) { | |
cca8b133 AL |
1727 | ret = REG_READ(REG_PORT(i), PORT_CONTROL); |
1728 | REG_WRITE(REG_PORT(i), PORT_CONTROL, ret & 0xfffc); | |
143a8307 AL |
1729 | } |
1730 | ||
1731 | /* Wait for transmit queues to drain. */ | |
1732 | usleep_range(2000, 4000); | |
1733 | ||
1734 | /* Reset the switch. Keep the PPU active if requested. The PPU | |
1735 | * needs to be active to support indirect phy register access | |
1736 | * through global registers 0x18 and 0x19. | |
1737 | */ | |
1738 | if (ppu_active) | |
1739 | REG_WRITE(REG_GLOBAL, 0x04, 0xc000); | |
1740 | else | |
1741 | REG_WRITE(REG_GLOBAL, 0x04, 0xc400); | |
1742 | ||
1743 | /* Wait up to one second for reset to complete. */ | |
1744 | timeout = jiffies + 1 * HZ; | |
1745 | while (time_before(jiffies, timeout)) { | |
1746 | ret = REG_READ(REG_GLOBAL, 0x00); | |
1747 | if ((ret & is_reset) == is_reset) | |
1748 | break; | |
1749 | usleep_range(1000, 2000); | |
1750 | } | |
1751 | if (time_after(jiffies, timeout)) | |
1752 | return -ETIMEDOUT; | |
1753 | ||
1754 | return 0; | |
1755 | } | |
1756 | ||
49143585 AL |
1757 | int mv88e6xxx_phy_page_read(struct dsa_switch *ds, int port, int page, int reg) |
1758 | { | |
1759 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
1760 | int ret; | |
1761 | ||
3898c148 | 1762 | mutex_lock(&ps->smi_mutex); |
fd3a0ee4 | 1763 | ret = _mv88e6xxx_phy_write_indirect(ds, port, 0x16, page); |
49143585 AL |
1764 | if (ret < 0) |
1765 | goto error; | |
fd3a0ee4 | 1766 | ret = _mv88e6xxx_phy_read_indirect(ds, port, reg); |
49143585 | 1767 | error: |
fd3a0ee4 | 1768 | _mv88e6xxx_phy_write_indirect(ds, port, 0x16, 0x0); |
3898c148 | 1769 | mutex_unlock(&ps->smi_mutex); |
49143585 AL |
1770 | return ret; |
1771 | } | |
1772 | ||
1773 | int mv88e6xxx_phy_page_write(struct dsa_switch *ds, int port, int page, | |
1774 | int reg, int val) | |
1775 | { | |
1776 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
1777 | int ret; | |
1778 | ||
3898c148 | 1779 | mutex_lock(&ps->smi_mutex); |
fd3a0ee4 | 1780 | ret = _mv88e6xxx_phy_write_indirect(ds, port, 0x16, page); |
49143585 AL |
1781 | if (ret < 0) |
1782 | goto error; | |
1783 | ||
fd3a0ee4 | 1784 | ret = _mv88e6xxx_phy_write_indirect(ds, port, reg, val); |
49143585 | 1785 | error: |
fd3a0ee4 | 1786 | _mv88e6xxx_phy_write_indirect(ds, port, 0x16, 0x0); |
3898c148 | 1787 | mutex_unlock(&ps->smi_mutex); |
fd3a0ee4 AL |
1788 | return ret; |
1789 | } | |
1790 | ||
1791 | static int mv88e6xxx_port_to_phy_addr(struct dsa_switch *ds, int port) | |
1792 | { | |
1793 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
1794 | ||
1795 | if (port >= 0 && port < ps->num_ports) | |
1796 | return port; | |
1797 | return -EINVAL; | |
1798 | } | |
1799 | ||
1800 | int | |
1801 | mv88e6xxx_phy_read(struct dsa_switch *ds, int port, int regnum) | |
1802 | { | |
1803 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
1804 | int addr = mv88e6xxx_port_to_phy_addr(ds, port); | |
1805 | int ret; | |
1806 | ||
1807 | if (addr < 0) | |
1808 | return addr; | |
1809 | ||
3898c148 | 1810 | mutex_lock(&ps->smi_mutex); |
fd3a0ee4 | 1811 | ret = _mv88e6xxx_phy_read(ds, addr, regnum); |
3898c148 | 1812 | mutex_unlock(&ps->smi_mutex); |
fd3a0ee4 AL |
1813 | return ret; |
1814 | } | |
1815 | ||
1816 | int | |
1817 | mv88e6xxx_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val) | |
1818 | { | |
1819 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
1820 | int addr = mv88e6xxx_port_to_phy_addr(ds, port); | |
1821 | int ret; | |
1822 | ||
1823 | if (addr < 0) | |
1824 | return addr; | |
1825 | ||
3898c148 | 1826 | mutex_lock(&ps->smi_mutex); |
fd3a0ee4 | 1827 | ret = _mv88e6xxx_phy_write(ds, addr, regnum, val); |
3898c148 | 1828 | mutex_unlock(&ps->smi_mutex); |
fd3a0ee4 AL |
1829 | return ret; |
1830 | } | |
1831 | ||
1832 | int | |
1833 | mv88e6xxx_phy_read_indirect(struct dsa_switch *ds, int port, int regnum) | |
1834 | { | |
1835 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
1836 | int addr = mv88e6xxx_port_to_phy_addr(ds, port); | |
1837 | int ret; | |
1838 | ||
1839 | if (addr < 0) | |
1840 | return addr; | |
1841 | ||
3898c148 | 1842 | mutex_lock(&ps->smi_mutex); |
fd3a0ee4 | 1843 | ret = _mv88e6xxx_phy_read_indirect(ds, addr, regnum); |
3898c148 | 1844 | mutex_unlock(&ps->smi_mutex); |
fd3a0ee4 AL |
1845 | return ret; |
1846 | } | |
1847 | ||
1848 | int | |
1849 | mv88e6xxx_phy_write_indirect(struct dsa_switch *ds, int port, int regnum, | |
1850 | u16 val) | |
1851 | { | |
1852 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
1853 | int addr = mv88e6xxx_port_to_phy_addr(ds, port); | |
1854 | int ret; | |
1855 | ||
1856 | if (addr < 0) | |
1857 | return addr; | |
1858 | ||
3898c148 | 1859 | mutex_lock(&ps->smi_mutex); |
fd3a0ee4 | 1860 | ret = _mv88e6xxx_phy_write_indirect(ds, addr, regnum, val); |
3898c148 | 1861 | mutex_unlock(&ps->smi_mutex); |
49143585 AL |
1862 | return ret; |
1863 | } | |
1864 | ||
98e67308 BH |
1865 | static int __init mv88e6xxx_init(void) |
1866 | { | |
1867 | #if IS_ENABLED(CONFIG_NET_DSA_MV88E6131) | |
1868 | register_switch_driver(&mv88e6131_switch_driver); | |
1869 | #endif | |
1870 | #if IS_ENABLED(CONFIG_NET_DSA_MV88E6123_61_65) | |
1871 | register_switch_driver(&mv88e6123_61_65_switch_driver); | |
42f27253 | 1872 | #endif |
3ad50cca GR |
1873 | #if IS_ENABLED(CONFIG_NET_DSA_MV88E6352) |
1874 | register_switch_driver(&mv88e6352_switch_driver); | |
1875 | #endif | |
42f27253 AL |
1876 | #if IS_ENABLED(CONFIG_NET_DSA_MV88E6171) |
1877 | register_switch_driver(&mv88e6171_switch_driver); | |
98e67308 BH |
1878 | #endif |
1879 | return 0; | |
1880 | } | |
1881 | module_init(mv88e6xxx_init); | |
1882 | ||
1883 | static void __exit mv88e6xxx_cleanup(void) | |
1884 | { | |
42f27253 AL |
1885 | #if IS_ENABLED(CONFIG_NET_DSA_MV88E6171) |
1886 | unregister_switch_driver(&mv88e6171_switch_driver); | |
1887 | #endif | |
98e67308 BH |
1888 | #if IS_ENABLED(CONFIG_NET_DSA_MV88E6123_61_65) |
1889 | unregister_switch_driver(&mv88e6123_61_65_switch_driver); | |
1890 | #endif | |
1891 | #if IS_ENABLED(CONFIG_NET_DSA_MV88E6131) | |
1892 | unregister_switch_driver(&mv88e6131_switch_driver); | |
1893 | #endif | |
1894 | } | |
1895 | module_exit(mv88e6xxx_cleanup); | |
3d825ede BH |
1896 | |
1897 | MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>"); | |
1898 | MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips"); | |
1899 | MODULE_LICENSE("GPL"); |