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net: dsa: mv88e6131: add registers access
[deliverable/linux.git] / drivers / net / dsa / mv88e6xxx.c
CommitLineData
91da11f8
LB		 1/*
2 * net/dsa/mv88e6xxx.c - Marvell 88e6xxx switch chip support
3 * Copyright (c) 2008 Marvell Semiconductor
4 *
b8fee957
VD		 5 * Copyright (c) 2015 CMC Electronics, Inc.
6 * Added support for VLAN Table Unit operations
7 *
91da11f8
LB		 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
19b2f97e 14#include <linux/delay.h>
defb05b9 15#include <linux/etherdevice.h>
dea87024 16#include <linux/ethtool.h>
facd95b2 17#include <linux/if_bridge.h>
19b2f97e 18#include <linux/jiffies.h>
91da11f8 19#include <linux/list.h>
2bbba277 20#include <linux/module.h>
91da11f8 21#include <linux/netdevice.h>
c8c1b39a 22#include <linux/gpio/consumer.h>
91da11f8 23#include <linux/phy.h>
c8f0b869 24#include <net/dsa.h>
1f36faf2 25#include <net/switchdev.h>
91da11f8
LB		 26#include "mv88e6xxx.h"
27
158bc065 28static void assert_smi_lock(struct mv88e6xxx_priv_state *ps)
3996a4ff 29{
3996a4ff 30 if (unlikely(!mutex_is_locked(&ps->smi_mutex))) {
158bc065 31 dev_err(ps->dev, "SMI lock not held!\n");
3996a4ff
VD		 32 dump_stack();
33 }
34}
35
3675c8d7 36/* If the switch's ADDR[4:0] strap pins are strapped to zero, it will
91da11f8
LB		 37 * use all 32 SMI bus addresses on its SMI bus, and all switch registers
38 * will be directly accessible on some {device address,register address}
39 * pair. If the ADDR[4:0] pins are not strapped to zero, the switch
40 * will only respond to SMI transactions to that specific address, and
41 * an indirect addressing mechanism needs to be used to access its
42 * registers.
43 */
44static int mv88e6xxx_reg_wait_ready(struct mii_bus *bus, int sw_addr)
45{
46 int ret;
47 int i;
48
49 for (i = 0; i < 16; i++) {
6e899e6c 50 ret = mdiobus_read_nested(bus, sw_addr, SMI_CMD);
91da11f8
LB		 51 if (ret < 0)
52 return ret;
53
cca8b133 54 if ((ret & SMI_CMD_BUSY) == 0)
91da11f8
LB		 55 return 0;
56 }
57
58 return -ETIMEDOUT;
59}
60
b9b37713
VD		 61static int __mv88e6xxx_reg_read(struct mii_bus *bus, int sw_addr, int addr,
62 int reg)
91da11f8
LB		 63{
64 int ret;
65
66 if (sw_addr == 0)
6e899e6c 67 return mdiobus_read_nested(bus, addr, reg);
91da11f8 68
3675c8d7 69 /* Wait for the bus to become free. */
91da11f8
LB		 70 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
71 if (ret < 0)
72 return ret;
73
3675c8d7 74 /* Transmit the read command. */
6e899e6c
NA		 75 ret = mdiobus_write_nested(bus, sw_addr, SMI_CMD,
76 SMI_CMD_OP_22_READ | (addr << 5) | reg);
91da11f8
LB		 77 if (ret < 0)
78 return ret;
79
3675c8d7 80 /* Wait for the read command to complete. */
91da11f8
LB		 81 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
82 if (ret < 0)
83 return ret;
84
3675c8d7 85 /* Read the data. */
6e899e6c 86 ret = mdiobus_read_nested(bus, sw_addr, SMI_DATA);
91da11f8
LB		 87 if (ret < 0)
88 return ret;
89
90 return ret & 0xffff;
91}
92
158bc065
AL		 93static int _mv88e6xxx_reg_read(struct mv88e6xxx_priv_state *ps,
94 int addr, int reg)
91da11f8 95{
91da11f8
LB		 96 int ret;
97
158bc065 98 assert_smi_lock(ps);
3996a4ff 99
a77d43f1 100 ret = __mv88e6xxx_reg_read(ps->bus, ps->sw_addr, addr, reg);
bb92ea5e
VD		 101 if (ret < 0)
102 return ret;
103
158bc065 104 dev_dbg(ps->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
bb92ea5e
VD		 105 addr, reg, ret);
106
91da11f8
LB		 107 return ret;
108}
109
158bc065 110int mv88e6xxx_reg_read(struct mv88e6xxx_priv_state *ps, int addr, int reg)
8d6d09e7 111{
8d6d09e7
GR		 112 int ret;
113
114 mutex_lock(&ps->smi_mutex);
158bc065 115 ret = _mv88e6xxx_reg_read(ps, addr, reg);
8d6d09e7
GR		 116 mutex_unlock(&ps->smi_mutex);
117
118 return ret;
119}
120
b9b37713
VD		 121static int __mv88e6xxx_reg_write(struct mii_bus *bus, int sw_addr, int addr,
122 int reg, u16 val)
91da11f8
LB		 123{
124 int ret;
125
126 if (sw_addr == 0)
6e899e6c 127 return mdiobus_write_nested(bus, addr, reg, val);
91da11f8 128
3675c8d7 129 /* Wait for the bus to become free. */
91da11f8
LB		 130 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
131 if (ret < 0)
132 return ret;
133
3675c8d7 134 /* Transmit the data to write. */
6e899e6c 135 ret = mdiobus_write_nested(bus, sw_addr, SMI_DATA, val);
91da11f8
LB		 136 if (ret < 0)
137 return ret;
138
3675c8d7 139 /* Transmit the write command. */
6e899e6c
NA		 140 ret = mdiobus_write_nested(bus, sw_addr, SMI_CMD,
141 SMI_CMD_OP_22_WRITE | (addr << 5) | reg);
91da11f8
LB		 142 if (ret < 0)
143 return ret;
144
3675c8d7 145 /* Wait for the write command to complete. */
91da11f8
LB		 146 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
147 if (ret < 0)
148 return ret;
149
150 return 0;
151}
152
158bc065
AL		 153static int _mv88e6xxx_reg_write(struct mv88e6xxx_priv_state *ps, int addr,
154 int reg, u16 val)
91da11f8 155{
158bc065 156 assert_smi_lock(ps);
91da11f8 157
158bc065 158 dev_dbg(ps->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
bb92ea5e
VD		 159 addr, reg, val);
160
a77d43f1 161 return __mv88e6xxx_reg_write(ps->bus, ps->sw_addr, addr, reg, val);
8d6d09e7
GR		 162}
163
158bc065
AL		 164int mv88e6xxx_reg_write(struct mv88e6xxx_priv_state *ps, int addr,
165 int reg, u16 val)
8d6d09e7 166{
8d6d09e7
GR		 167 int ret;
168
91da11f8 169 mutex_lock(&ps->smi_mutex);
158bc065 170 ret = _mv88e6xxx_reg_write(ps, addr, reg, val);
91da11f8
LB		 171 mutex_unlock(&ps->smi_mutex);
172
173 return ret;
174}
175
1d13a06e 176static int mv88e6xxx_set_addr_direct(struct dsa_switch *ds, u8 *addr)
2e5f0320 177{
158bc065 178 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
48ace4ef 179 int err;
2e5f0320 180
158bc065 181 err = mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_MAC_01,
48ace4ef
AL		 182 (addr[0] << 8) | addr[1]);
183 if (err)
184 return err;
185
158bc065 186 err = mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_MAC_23,
48ace4ef
AL		 187 (addr[2] << 8) | addr[3]);
188 if (err)
189 return err;
190
158bc065 191 return mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_MAC_45,
48ace4ef 192 (addr[4] << 8) | addr[5]);
2e5f0320
LB		 193}
194
1d13a06e 195static int mv88e6xxx_set_addr_indirect(struct dsa_switch *ds, u8 *addr)
91da11f8 196{
158bc065 197 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
91da11f8 198 int ret;
48ace4ef 199 int i;
91da11f8
LB		 200
201 for (i = 0; i < 6; i++) {
202 int j;
203
3675c8d7 204 /* Write the MAC address byte. */
158bc065 205 ret = mv88e6xxx_reg_write(ps, REG_GLOBAL2, GLOBAL2_SWITCH_MAC,
48ace4ef
AL		 206 GLOBAL2_SWITCH_MAC_BUSY |
207 (i << 8) | addr[i]);
208 if (ret)
209 return ret;
91da11f8 210
3675c8d7 211 /* Wait for the write to complete. */
91da11f8 212 for (j = 0; j < 16; j++) {
158bc065 213 ret = mv88e6xxx_reg_read(ps, REG_GLOBAL2,
48ace4ef
AL		 214 GLOBAL2_SWITCH_MAC);
215 if (ret < 0)
216 return ret;
217
cca8b133 218 if ((ret & GLOBAL2_SWITCH_MAC_BUSY) == 0)
91da11f8
LB		 219 break;
220 }
221 if (j == 16)
222 return -ETIMEDOUT;
223 }
224
225 return 0;
226}
227
1d13a06e
VD		 228int mv88e6xxx_set_addr(struct dsa_switch *ds, u8 *addr)
229{
230 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
231
232 if (mv88e6xxx_has(ps, MV88E6XXX_FLAG_SWITCH_MAC))
233 return mv88e6xxx_set_addr_indirect(ds, addr);
234 else
235 return mv88e6xxx_set_addr_direct(ds, addr);
236}
237
158bc065
AL		 238static int _mv88e6xxx_phy_read(struct mv88e6xxx_priv_state *ps, int addr,
239 int regnum)
91da11f8
LB		 240{
241 if (addr >= 0)
158bc065 242 return _mv88e6xxx_reg_read(ps, addr, regnum);
91da11f8
LB		 243 return 0xffff;
244}
245
158bc065
AL		 246static int _mv88e6xxx_phy_write(struct mv88e6xxx_priv_state *ps, int addr,
247 int regnum, u16 val)
91da11f8
LB		 248{
249 if (addr >= 0)
158bc065 250 return _mv88e6xxx_reg_write(ps, addr, regnum, val);
91da11f8
LB		 251 return 0;
252}
253
158bc065 254static int mv88e6xxx_ppu_disable(struct mv88e6xxx_priv_state *ps)
2e5f0320
LB		 255{
256 int ret;
19b2f97e 257 unsigned long timeout;
2e5f0320 258
8c9983a2 259 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_CONTROL);
48ace4ef
AL		 260 if (ret < 0)
261 return ret;
262
8c9983a2
VD		 263 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_CONTROL,
264 ret & ~GLOBAL_CONTROL_PPU_ENABLE);
48ace4ef
AL		 265 if (ret)
266 return ret;
2e5f0320 267
19b2f97e
BG		 268 timeout = jiffies + 1 * HZ;
269 while (time_before(jiffies, timeout)) {
8c9983a2 270 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_STATUS);
48ace4ef
AL		 271 if (ret < 0)
272 return ret;
273
19b2f97e 274 usleep_range(1000, 2000);
cca8b133
AL		 275 if ((ret & GLOBAL_STATUS_PPU_MASK) !=
276 GLOBAL_STATUS_PPU_POLLING)
85686581 277 return 0;
2e5f0320
LB		 278 }
279
280 return -ETIMEDOUT;
281}
282
158bc065 283static int mv88e6xxx_ppu_enable(struct mv88e6xxx_priv_state *ps)
2e5f0320 284{
48ace4ef 285 int ret, err;
19b2f97e 286 unsigned long timeout;
2e5f0320 287
158bc065 288 ret = mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_CONTROL);
48ace4ef
AL		 289 if (ret < 0)
290 return ret;
291
158bc065 292 err = mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_CONTROL,
48ace4ef
AL		 293 ret | GLOBAL_CONTROL_PPU_ENABLE);
294 if (err)
295 return err;
2e5f0320 296
19b2f97e
BG		 297 timeout = jiffies + 1 * HZ;
298 while (time_before(jiffies, timeout)) {
158bc065 299 ret = mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_STATUS);
48ace4ef
AL		 300 if (ret < 0)
301 return ret;
302
19b2f97e 303 usleep_range(1000, 2000);
cca8b133
AL		 304 if ((ret & GLOBAL_STATUS_PPU_MASK) ==
305 GLOBAL_STATUS_PPU_POLLING)
85686581 306 return 0;
2e5f0320
LB		 307 }
308
309 return -ETIMEDOUT;
310}
311
312static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly)
313{
314 struct mv88e6xxx_priv_state *ps;
315
316 ps = container_of(ugly, struct mv88e6xxx_priv_state, ppu_work);
317 if (mutex_trylock(&ps->ppu_mutex)) {
158bc065 318 if (mv88e6xxx_ppu_enable(ps) == 0)
85686581
BG		 319 ps->ppu_disabled = 0;
320 mutex_unlock(&ps->ppu_mutex);
2e5f0320
LB		 321 }
322}
323
324static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps)
325{
326 struct mv88e6xxx_priv_state *ps = (void *)_ps;
327
328 schedule_work(&ps->ppu_work);
329}
330
158bc065 331static int mv88e6xxx_ppu_access_get(struct mv88e6xxx_priv_state *ps)
2e5f0320 332{
2e5f0320
LB		 333 int ret;
334
335 mutex_lock(&ps->ppu_mutex);
336
3675c8d7 337 /* If the PHY polling unit is enabled, disable it so that
2e5f0320
LB		 338 * we can access the PHY registers. If it was already
339 * disabled, cancel the timer that is going to re-enable
340 * it.
341 */
342 if (!ps->ppu_disabled) {
158bc065 343 ret = mv88e6xxx_ppu_disable(ps);
85686581
BG		 344 if (ret < 0) {
345 mutex_unlock(&ps->ppu_mutex);
346 return ret;
347 }
348 ps->ppu_disabled = 1;
2e5f0320 349 } else {
85686581
BG		 350 del_timer(&ps->ppu_timer);
351 ret = 0;
2e5f0320
LB		 352 }
353
354 return ret;
355}
356
158bc065 357static void mv88e6xxx_ppu_access_put(struct mv88e6xxx_priv_state *ps)
2e5f0320 358{
3675c8d7 359 /* Schedule a timer to re-enable the PHY polling unit. */
2e5f0320
LB		 360 mod_timer(&ps->ppu_timer, jiffies + msecs_to_jiffies(10));
361 mutex_unlock(&ps->ppu_mutex);
362}
363
158bc065 364void mv88e6xxx_ppu_state_init(struct mv88e6xxx_priv_state *ps)
2e5f0320 365{
2e5f0320
LB		 366 mutex_init(&ps->ppu_mutex);
367 INIT_WORK(&ps->ppu_work, mv88e6xxx_ppu_reenable_work);
368 init_timer(&ps->ppu_timer);
369 ps->ppu_timer.data = (unsigned long)ps;
370 ps->ppu_timer.function = mv88e6xxx_ppu_reenable_timer;
371}
372
8c9983a2
VD		 373static int mv88e6xxx_phy_read_ppu(struct mv88e6xxx_priv_state *ps, int addr,
374 int regnum)
2e5f0320
LB		 375{
376 int ret;
377
158bc065 378 ret = mv88e6xxx_ppu_access_get(ps);
2e5f0320 379 if (ret >= 0) {
8c9983a2 380 ret = _mv88e6xxx_reg_read(ps, addr, regnum);
158bc065 381 mv88e6xxx_ppu_access_put(ps);
2e5f0320
LB		 382 }
383
384 return ret;
385}
386
8c9983a2
VD		 387static int mv88e6xxx_phy_write_ppu(struct mv88e6xxx_priv_state *ps, int addr,
388 int regnum, u16 val)
2e5f0320
LB		 389{
390 int ret;
391
158bc065 392 ret = mv88e6xxx_ppu_access_get(ps);
2e5f0320 393 if (ret >= 0) {
8c9983a2 394 ret = _mv88e6xxx_reg_write(ps, addr, regnum, val);
158bc065 395 mv88e6xxx_ppu_access_put(ps);
2e5f0320
LB		 396 }
397
398 return ret;
399}
2e5f0320 400
158bc065 401static bool mv88e6xxx_6065_family(struct mv88e6xxx_priv_state *ps)
54d792f2 402{
22356476 403 return ps->info->family == MV88E6XXX_FAMILY_6065;
54d792f2
AL		 404}
405
158bc065 406static bool mv88e6xxx_6095_family(struct mv88e6xxx_priv_state *ps)
54d792f2 407{
22356476 408 return ps->info->family == MV88E6XXX_FAMILY_6095;
54d792f2
AL		 409}
410
158bc065 411static bool mv88e6xxx_6097_family(struct mv88e6xxx_priv_state *ps)
54d792f2 412{
22356476 413 return ps->info->family == MV88E6XXX_FAMILY_6097;
54d792f2
AL		 414}
415
158bc065 416static bool mv88e6xxx_6165_family(struct mv88e6xxx_priv_state *ps)
54d792f2 417{
22356476 418 return ps->info->family == MV88E6XXX_FAMILY_6165;
54d792f2
AL		 419}
420
158bc065 421static bool mv88e6xxx_6185_family(struct mv88e6xxx_priv_state *ps)
54d792f2 422{
22356476 423 return ps->info->family == MV88E6XXX_FAMILY_6185;
54d792f2
AL		 424}
425
158bc065 426static bool mv88e6xxx_6320_family(struct mv88e6xxx_priv_state *ps)
7c3d0d67 427{
22356476 428 return ps->info->family == MV88E6XXX_FAMILY_6320;
7c3d0d67
AK		 429}
430
158bc065 431static bool mv88e6xxx_6351_family(struct mv88e6xxx_priv_state *ps)
54d792f2 432{
22356476 433 return ps->info->family == MV88E6XXX_FAMILY_6351;
54d792f2
AL		 434}
435
158bc065 436static bool mv88e6xxx_6352_family(struct mv88e6xxx_priv_state *ps)
f3a8b6b6 437{
22356476 438 return ps->info->family == MV88E6XXX_FAMILY_6352;
f3a8b6b6
AL		 439}
440
158bc065 441static unsigned int mv88e6xxx_num_databases(struct mv88e6xxx_priv_state *ps)
f74df0be 442{
cd5a2c82 443 return ps->info->num_databases;
f74df0be
VD		 444}
445
158bc065 446static bool mv88e6xxx_has_fid_reg(struct mv88e6xxx_priv_state *ps)
b426e5f7
VD		 447{
448 /* Does the device have dedicated FID registers for ATU and VTU ops? */
158bc065
AL		 449 if (mv88e6xxx_6097_family(ps) || mv88e6xxx_6165_family(ps) ||
450 mv88e6xxx_6351_family(ps) || mv88e6xxx_6352_family(ps))
b426e5f7
VD		 451 return true;
452
453 return false;
454}
455
158bc065 456static bool mv88e6xxx_has_stu(struct mv88e6xxx_priv_state *ps)
2e7bd5ef
VD		 457{
458 /* Does the device have STU and dedicated SID registers for VTU ops? */
158bc065
AL		 459 if (mv88e6xxx_6097_family(ps) || mv88e6xxx_6165_family(ps) ||
460 mv88e6xxx_6351_family(ps) || mv88e6xxx_6352_family(ps))
2e7bd5ef
VD		 461 return true;
462
463 return false;
464}
465
dea87024
AL		 466/* We expect the switch to perform auto negotiation if there is a real
467 * phy. However, in the case of a fixed link phy, we force the port
468 * settings from the fixed link settings.
469 */
470void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
471 struct phy_device *phydev)
472{
473 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
49052871
AL		 474 u32 reg;
475 int ret;
dea87024
AL		 476
477 if (!phy_is_pseudo_fixed_link(phydev))
478 return;
479
480 mutex_lock(&ps->smi_mutex);
481
158bc065 482 ret = _mv88e6xxx_reg_read(ps, REG_PORT(port), PORT_PCS_CTRL);
dea87024
AL		 483 if (ret < 0)
484 goto out;
485
486 reg = ret & ~(PORT_PCS_CTRL_LINK_UP |
487 PORT_PCS_CTRL_FORCE_LINK |
488 PORT_PCS_CTRL_DUPLEX_FULL |
489 PORT_PCS_CTRL_FORCE_DUPLEX |
490 PORT_PCS_CTRL_UNFORCED);
491
492 reg |= PORT_PCS_CTRL_FORCE_LINK;
493 if (phydev->link)
494 reg |= PORT_PCS_CTRL_LINK_UP;
495
158bc065 496 if (mv88e6xxx_6065_family(ps) && phydev->speed > SPEED_100)
dea87024
AL		 497 goto out;
498
499 switch (phydev->speed) {
500 case SPEED_1000:
501 reg |= PORT_PCS_CTRL_1000;
502 break;
503 case SPEED_100:
504 reg |= PORT_PCS_CTRL_100;
505 break;
506 case SPEED_10:
507 reg |= PORT_PCS_CTRL_10;
508 break;
509 default:
510 pr_info("Unknown speed");
511 goto out;
512 }
513
514 reg |= PORT_PCS_CTRL_FORCE_DUPLEX;
515 if (phydev->duplex == DUPLEX_FULL)
516 reg |= PORT_PCS_CTRL_DUPLEX_FULL;
517
158bc065 518 if ((mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps)) &&
009a2b98 519 (port >= ps->info->num_ports - 2)) {
e7e72ac0
AL		 520 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
521 reg |= PORT_PCS_CTRL_RGMII_DELAY_RXCLK;
522 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
523 reg |= PORT_PCS_CTRL_RGMII_DELAY_TXCLK;
524 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
525 reg |= (PORT_PCS_CTRL_RGMII_DELAY_RXCLK |
526 PORT_PCS_CTRL_RGMII_DELAY_TXCLK);
527 }
158bc065 528 _mv88e6xxx_reg_write(ps, REG_PORT(port), PORT_PCS_CTRL, reg);
dea87024
AL		 529
530out:
531 mutex_unlock(&ps->smi_mutex);
532}
533
158bc065 534static int _mv88e6xxx_stats_wait(struct mv88e6xxx_priv_state *ps)
91da11f8
LB		 535{
536 int ret;
537 int i;
538
539 for (i = 0; i < 10; i++) {
158bc065 540 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_STATS_OP);
cca8b133 541 if ((ret & GLOBAL_STATS_OP_BUSY) == 0)
91da11f8
LB		 542 return 0;
543 }
544
545 return -ETIMEDOUT;
546}
547
158bc065
AL		 548static int _mv88e6xxx_stats_snapshot(struct mv88e6xxx_priv_state *ps,
549 int port)
91da11f8
LB		 550{
551 int ret;
552
158bc065 553 if (mv88e6xxx_6320_family(ps) || mv88e6xxx_6352_family(ps))
f3a8b6b6
AL		 554 port = (port + 1) << 5;
555
3675c8d7 556 /* Snapshot the hardware statistics counters for this port. */
158bc065 557 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_STATS_OP,
31888234
AL		 558 GLOBAL_STATS_OP_CAPTURE_PORT |
559 GLOBAL_STATS_OP_HIST_RX_TX | port);
560 if (ret < 0)
561 return ret;
91da11f8 562
3675c8d7 563 /* Wait for the snapshotting to complete. */
158bc065 564 ret = _mv88e6xxx_stats_wait(ps);
91da11f8
LB		 565 if (ret < 0)
566 return ret;
567
568 return 0;
569}
570
158bc065
AL		 571static void _mv88e6xxx_stats_read(struct mv88e6xxx_priv_state *ps,
572 int stat, u32 *val)
91da11f8
LB		 573{
574 u32 _val;
575 int ret;
576
577 *val = 0;
578
158bc065 579 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_STATS_OP,
31888234
AL		 580 GLOBAL_STATS_OP_READ_CAPTURED |
581 GLOBAL_STATS_OP_HIST_RX_TX | stat);
91da11f8
LB		 582 if (ret < 0)
583 return;
584
158bc065 585 ret = _mv88e6xxx_stats_wait(ps);
91da11f8
LB		 586 if (ret < 0)
587 return;
588
158bc065 589 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_STATS_COUNTER_32);
91da11f8
LB		 590 if (ret < 0)
591 return;
592
593 _val = ret << 16;
594
158bc065 595 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_STATS_COUNTER_01);
91da11f8
LB		 596 if (ret < 0)
597 return;
598
599 *val = _val | ret;
600}
601
e413e7e1 602static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
f5e2ed02
AL		 603 { "in_good_octets", 8, 0x00, BANK0, },
604 { "in_bad_octets", 4, 0x02, BANK0, },
605 { "in_unicast", 4, 0x04, BANK0, },
606 { "in_broadcasts", 4, 0x06, BANK0, },
607 { "in_multicasts", 4, 0x07, BANK0, },
608 { "in_pause", 4, 0x16, BANK0, },
609 { "in_undersize", 4, 0x18, BANK0, },
610 { "in_fragments", 4, 0x19, BANK0, },
611 { "in_oversize", 4, 0x1a, BANK0, },
612 { "in_jabber", 4, 0x1b, BANK0, },
613 { "in_rx_error", 4, 0x1c, BANK0, },
614 { "in_fcs_error", 4, 0x1d, BANK0, },
615 { "out_octets", 8, 0x0e, BANK0, },
616 { "out_unicast", 4, 0x10, BANK0, },
617 { "out_broadcasts", 4, 0x13, BANK0, },
618 { "out_multicasts", 4, 0x12, BANK0, },
619 { "out_pause", 4, 0x15, BANK0, },
620 { "excessive", 4, 0x11, BANK0, },
621 { "collisions", 4, 0x1e, BANK0, },
622 { "deferred", 4, 0x05, BANK0, },
623 { "single", 4, 0x14, BANK0, },
624 { "multiple", 4, 0x17, BANK0, },
625 { "out_fcs_error", 4, 0x03, BANK0, },
626 { "late", 4, 0x1f, BANK0, },
627 { "hist_64bytes", 4, 0x08, BANK0, },
628 { "hist_65_127bytes", 4, 0x09, BANK0, },
629 { "hist_128_255bytes", 4, 0x0a, BANK0, },
630 { "hist_256_511bytes", 4, 0x0b, BANK0, },
631 { "hist_512_1023bytes", 4, 0x0c, BANK0, },
632 { "hist_1024_max_bytes", 4, 0x0d, BANK0, },
633 { "sw_in_discards", 4, 0x10, PORT, },
634 { "sw_in_filtered", 2, 0x12, PORT, },
635 { "sw_out_filtered", 2, 0x13, PORT, },
636 { "in_discards", 4, 0x00 | GLOBAL_STATS_OP_BANK_1, BANK1, },
637 { "in_filtered", 4, 0x01 | GLOBAL_STATS_OP_BANK_1, BANK1, },
638 { "in_accepted", 4, 0x02 | GLOBAL_STATS_OP_BANK_1, BANK1, },
639 { "in_bad_accepted", 4, 0x03 | GLOBAL_STATS_OP_BANK_1, BANK1, },
640 { "in_good_avb_class_a", 4, 0x04 | GLOBAL_STATS_OP_BANK_1, BANK1, },
641 { "in_good_avb_class_b", 4, 0x05 | GLOBAL_STATS_OP_BANK_1, BANK1, },
642 { "in_bad_avb_class_a", 4, 0x06 | GLOBAL_STATS_OP_BANK_1, BANK1, },
643 { "in_bad_avb_class_b", 4, 0x07 | GLOBAL_STATS_OP_BANK_1, BANK1, },
644 { "tcam_counter_0", 4, 0x08 | GLOBAL_STATS_OP_BANK_1, BANK1, },
645 { "tcam_counter_1", 4, 0x09 | GLOBAL_STATS_OP_BANK_1, BANK1, },
646 { "tcam_counter_2", 4, 0x0a | GLOBAL_STATS_OP_BANK_1, BANK1, },
647 { "tcam_counter_3", 4, 0x0b | GLOBAL_STATS_OP_BANK_1, BANK1, },
648 { "in_da_unknown", 4, 0x0e | GLOBAL_STATS_OP_BANK_1, BANK1, },
649 { "in_management", 4, 0x0f | GLOBAL_STATS_OP_BANK_1, BANK1, },
650 { "out_queue_0", 4, 0x10 | GLOBAL_STATS_OP_BANK_1, BANK1, },
651 { "out_queue_1", 4, 0x11 | GLOBAL_STATS_OP_BANK_1, BANK1, },
652 { "out_queue_2", 4, 0x12 | GLOBAL_STATS_OP_BANK_1, BANK1, },
653 { "out_queue_3", 4, 0x13 | GLOBAL_STATS_OP_BANK_1, BANK1, },
654 { "out_queue_4", 4, 0x14 | GLOBAL_STATS_OP_BANK_1, BANK1, },
655 { "out_queue_5", 4, 0x15 | GLOBAL_STATS_OP_BANK_1, BANK1, },
656 { "out_queue_6", 4, 0x16 | GLOBAL_STATS_OP_BANK_1, BANK1, },
657 { "out_queue_7", 4, 0x17 | GLOBAL_STATS_OP_BANK_1, BANK1, },
658 { "out_cut_through", 4, 0x18 | GLOBAL_STATS_OP_BANK_1, BANK1, },
659 { "out_octets_a", 4, 0x1a | GLOBAL_STATS_OP_BANK_1, BANK1, },
660 { "out_octets_b", 4, 0x1b | GLOBAL_STATS_OP_BANK_1, BANK1, },
661 { "out_management", 4, 0x1f | GLOBAL_STATS_OP_BANK_1, BANK1, },
e413e7e1
AL		 662};
663
158bc065 664static bool mv88e6xxx_has_stat(struct mv88e6xxx_priv_state *ps,
f5e2ed02 665 struct mv88e6xxx_hw_stat *stat)
e413e7e1 666{
f5e2ed02
AL		 667 switch (stat->type) {
668 case BANK0:
e413e7e1 669 return true;
f5e2ed02 670 case BANK1:
158bc065 671 return mv88e6xxx_6320_family(ps);
f5e2ed02 672 case PORT:
158bc065
AL		 673 return mv88e6xxx_6095_family(ps) ||
674 mv88e6xxx_6185_family(ps) ||
675 mv88e6xxx_6097_family(ps) ||
676 mv88e6xxx_6165_family(ps) ||
677 mv88e6xxx_6351_family(ps) ||
678 mv88e6xxx_6352_family(ps);
91da11f8 679 }
f5e2ed02 680 return false;
91da11f8
LB		 681}
682
158bc065 683static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_priv_state *ps,
f5e2ed02 684 struct mv88e6xxx_hw_stat *s,
80c4627b
AL		 685 int port)
686{
80c4627b
AL		 687 u32 low;
688 u32 high = 0;
689 int ret;
690 u64 value;
691
f5e2ed02
AL		 692 switch (s->type) {
693 case PORT:
158bc065 694 ret = _mv88e6xxx_reg_read(ps, REG_PORT(port), s->reg);
80c4627b
AL		 695 if (ret < 0)
696 return UINT64_MAX;
697
698 low = ret;
699 if (s->sizeof_stat == 4) {
158bc065 700 ret = _mv88e6xxx_reg_read(ps, REG_PORT(port),
f5e2ed02 701 s->reg + 1);
80c4627b
AL		 702 if (ret < 0)
703 return UINT64_MAX;
704 high = ret;
705 }
f5e2ed02
AL		 706 break;
707 case BANK0:
708 case BANK1:
158bc065 709 _mv88e6xxx_stats_read(ps, s->reg, &low);
80c4627b 710 if (s->sizeof_stat == 8)
158bc065 711 _mv88e6xxx_stats_read(ps, s->reg + 1, &high);
80c4627b
AL		 712 }
713 value = (((u64)high) << 16) | low;
714 return value;
715}
716
f5e2ed02 717void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, uint8_t *data)
91da11f8 718{
158bc065 719 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
f5e2ed02
AL		 720 struct mv88e6xxx_hw_stat *stat;
721 int i, j;
91da11f8 722
f5e2ed02
AL		 723 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
724 stat = &mv88e6xxx_hw_stats[i];
158bc065 725 if (mv88e6xxx_has_stat(ps, stat)) {
f5e2ed02
AL		 726 memcpy(data + j * ETH_GSTRING_LEN, stat->string,
727 ETH_GSTRING_LEN);
728 j++;
729 }
91da11f8 730 }
e413e7e1
AL		 731}
732
733int mv88e6xxx_get_sset_count(struct dsa_switch *ds)
734{
158bc065 735 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
f5e2ed02
AL		 736 struct mv88e6xxx_hw_stat *stat;
737 int i, j;
738
739 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
740 stat = &mv88e6xxx_hw_stats[i];
158bc065 741 if (mv88e6xxx_has_stat(ps, stat))
f5e2ed02
AL		 742 j++;
743 }
744 return j;
e413e7e1
AL		 745}
746
747void
748mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds,
749 int port, uint64_t *data)
750{
f5e2ed02
AL		 751 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
752 struct mv88e6xxx_hw_stat *stat;
753 int ret;
754 int i, j;
755
756 mutex_lock(&ps->smi_mutex);
757
158bc065 758 ret = _mv88e6xxx_stats_snapshot(ps, port);
f5e2ed02
AL		 759 if (ret < 0) {
760 mutex_unlock(&ps->smi_mutex);
761 return;
762 }
763 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
764 stat = &mv88e6xxx_hw_stats[i];
158bc065
AL		 765 if (mv88e6xxx_has_stat(ps, stat)) {
766 data[j] = _mv88e6xxx_get_ethtool_stat(ps, stat, port);
f5e2ed02
AL		 767 j++;
768 }
769 }
770
771 mutex_unlock(&ps->smi_mutex);
e413e7e1
AL		 772}
773
a1ab91f3
GR		 774int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
775{
776 return 32 * sizeof(u16);
777}
778
779void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
780 struct ethtool_regs *regs, void *_p)
781{
158bc065 782 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
a1ab91f3
GR		 783 u16 *p = _p;
784 int i;
785
786 regs->version = 0;
787
788 memset(p, 0xff, 32 * sizeof(u16));
789
23062513
VD		 790 mutex_lock(&ps->smi_mutex);
791
a1ab91f3
GR		 792 for (i = 0; i < 32; i++) {
793 int ret;
794
23062513 795 ret = _mv88e6xxx_reg_read(ps, REG_PORT(port), i);
a1ab91f3
GR		 796 if (ret >= 0)
797 p[i] = ret;
798 }
23062513
VD		 799
800 mutex_unlock(&ps->smi_mutex);
a1ab91f3
GR		 801}
802
158bc065 803static int _mv88e6xxx_wait(struct mv88e6xxx_priv_state *ps, int reg, int offset,
3898c148 804 u16 mask)
f3044683
AL		 805{
806 unsigned long timeout = jiffies + HZ / 10;
807
808 while (time_before(jiffies, timeout)) {
809 int ret;
810
158bc065 811 ret = _mv88e6xxx_reg_read(ps, reg, offset);
3898c148
AL		 812 if (ret < 0)
813 return ret;
f3044683
AL		 814 if (!(ret & mask))
815 return 0;
816
817 usleep_range(1000, 2000);
818 }
819 return -ETIMEDOUT;
820}
821
158bc065
AL		 822static int mv88e6xxx_wait(struct mv88e6xxx_priv_state *ps, int reg,
823 int offset, u16 mask)
3898c148 824{
3898c148
AL		 825 int ret;
826
827 mutex_lock(&ps->smi_mutex);
158bc065 828 ret = _mv88e6xxx_wait(ps, reg, offset, mask);
3898c148
AL		 829 mutex_unlock(&ps->smi_mutex);
830
831 return ret;
832}
833
158bc065 834static int _mv88e6xxx_phy_wait(struct mv88e6xxx_priv_state *ps)
f3044683 835{
158bc065 836 return _mv88e6xxx_wait(ps, REG_GLOBAL2, GLOBAL2_SMI_OP,
3898c148 837 GLOBAL2_SMI_OP_BUSY);
f3044683
AL		 838}
839
d24645be 840static int mv88e6xxx_eeprom_load_wait(struct dsa_switch *ds)
f3044683 841{
158bc065
AL		 842 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
843
844 return mv88e6xxx_wait(ps, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
cca8b133 845 GLOBAL2_EEPROM_OP_LOAD);
f3044683
AL		 846}
847
d24645be 848static int mv88e6xxx_eeprom_busy_wait(struct dsa_switch *ds)
f3044683 849{
158bc065
AL		 850 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
851
852 return mv88e6xxx_wait(ps, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
cca8b133 853 GLOBAL2_EEPROM_OP_BUSY);
f3044683
AL		 854}
855
d24645be
VD		 856static int mv88e6xxx_read_eeprom_word(struct dsa_switch *ds, int addr)
857{
858 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
859 int ret;
860
861 mutex_lock(&ps->eeprom_mutex);
862
863 ret = mv88e6xxx_reg_write(ps, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
864 GLOBAL2_EEPROM_OP_READ |
865 (addr & GLOBAL2_EEPROM_OP_ADDR_MASK));
866 if (ret < 0)
867 goto error;
868
869 ret = mv88e6xxx_eeprom_busy_wait(ds);
870 if (ret < 0)
871 goto error;
872
873 ret = mv88e6xxx_reg_read(ps, REG_GLOBAL2, GLOBAL2_EEPROM_DATA);
874error:
875 mutex_unlock(&ps->eeprom_mutex);
876 return ret;
877}
878
879int mv88e6xxx_get_eeprom(struct dsa_switch *ds, struct ethtool_eeprom *eeprom,
880 u8 *data)
881{
882 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
883 int offset;
884 int len;
885 int ret;
886
887 if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_EEPROM))
888 return -EOPNOTSUPP;
889
890 offset = eeprom->offset;
891 len = eeprom->len;
892 eeprom->len = 0;
893
894 eeprom->magic = 0xc3ec4951;
895
896 ret = mv88e6xxx_eeprom_load_wait(ds);
897 if (ret < 0)
898 return ret;
899
900 if (offset & 1) {
901 int word;
902
903 word = mv88e6xxx_read_eeprom_word(ds, offset >> 1);
904 if (word < 0)
905 return word;
906
907 *data++ = (word >> 8) & 0xff;
908
909 offset++;
910 len--;
911 eeprom->len++;
912 }
913
914 while (len >= 2) {
915 int word;
916
917 word = mv88e6xxx_read_eeprom_word(ds, offset >> 1);
918 if (word < 0)
919 return word;
920
921 *data++ = word & 0xff;
922 *data++ = (word >> 8) & 0xff;
923
924 offset += 2;
925 len -= 2;
926 eeprom->len += 2;
927 }
928
929 if (len) {
930 int word;
931
932 word = mv88e6xxx_read_eeprom_word(ds, offset >> 1);
933 if (word < 0)
934 return word;
935
936 *data++ = word & 0xff;
937
938 offset++;
939 len--;
940 eeprom->len++;
941 }
942
943 return 0;
944}
945
946static int mv88e6xxx_eeprom_is_readonly(struct dsa_switch *ds)
947{
948 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
949 int ret;
950
951 ret = mv88e6xxx_reg_read(ps, REG_GLOBAL2, GLOBAL2_EEPROM_OP);
952 if (ret < 0)
953 return ret;
954
955 if (!(ret & GLOBAL2_EEPROM_OP_WRITE_EN))
956 return -EROFS;
957
958 return 0;
959}
960
961static int mv88e6xxx_write_eeprom_word(struct dsa_switch *ds, int addr,
962 u16 data)
963{
964 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
965 int ret;
966
967 mutex_lock(&ps->eeprom_mutex);
968
969 ret = mv88e6xxx_reg_write(ps, REG_GLOBAL2, GLOBAL2_EEPROM_DATA, data);
970 if (ret < 0)
971 goto error;
972
973 ret = mv88e6xxx_reg_write(ps, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
974 GLOBAL2_EEPROM_OP_WRITE |
975 (addr & GLOBAL2_EEPROM_OP_ADDR_MASK));
976 if (ret < 0)
977 goto error;
978
979 ret = mv88e6xxx_eeprom_busy_wait(ds);
980error:
981 mutex_unlock(&ps->eeprom_mutex);
982 return ret;
983}
984
985int mv88e6xxx_set_eeprom(struct dsa_switch *ds, struct ethtool_eeprom *eeprom,
986 u8 *data)
987{
988 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
989 int offset;
990 int ret;
991 int len;
992
993 if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_EEPROM))
994 return -EOPNOTSUPP;
995
996 if (eeprom->magic != 0xc3ec4951)
997 return -EINVAL;
998
999 ret = mv88e6xxx_eeprom_is_readonly(ds);
1000 if (ret)
1001 return ret;
1002
1003 offset = eeprom->offset;
1004 len = eeprom->len;
1005 eeprom->len = 0;
1006
1007 ret = mv88e6xxx_eeprom_load_wait(ds);
1008 if (ret < 0)
1009 return ret;
1010
1011 if (offset & 1) {
1012 int word;
1013
1014 word = mv88e6xxx_read_eeprom_word(ds, offset >> 1);
1015 if (word < 0)
1016 return word;
1017
1018 word = (*data++ << 8) | (word & 0xff);
1019
1020 ret = mv88e6xxx_write_eeprom_word(ds, offset >> 1, word);
1021 if (ret < 0)
1022 return ret;
1023
1024 offset++;
1025 len--;
1026 eeprom->len++;
1027 }
1028
1029 while (len >= 2) {
1030 int word;
1031
1032 word = *data++;
1033 word |= *data++ << 8;
1034
1035 ret = mv88e6xxx_write_eeprom_word(ds, offset >> 1, word);
1036 if (ret < 0)
1037 return ret;
1038
1039 offset += 2;
1040 len -= 2;
1041 eeprom->len += 2;
1042 }
1043
1044 if (len) {
1045 int word;
1046
1047 word = mv88e6xxx_read_eeprom_word(ds, offset >> 1);
1048 if (word < 0)
1049 return word;
1050
1051 word = (word & 0xff00) | *data++;
1052
1053 ret = mv88e6xxx_write_eeprom_word(ds, offset >> 1, word);
1054 if (ret < 0)
1055 return ret;
1056
1057 offset++;
1058 len--;
1059 eeprom->len++;
1060 }
1061
1062 return 0;
1063}
1064
158bc065 1065static int _mv88e6xxx_atu_wait(struct mv88e6xxx_priv_state *ps)
facd95b2 1066{
158bc065 1067 return _mv88e6xxx_wait(ps, REG_GLOBAL, GLOBAL_ATU_OP,
cca8b133 1068 GLOBAL_ATU_OP_BUSY);
facd95b2
GR		 1069}
1070
158bc065
AL		 1071static int _mv88e6xxx_phy_read_indirect(struct mv88e6xxx_priv_state *ps,
1072 int addr, int regnum)
f3044683
AL		 1073{
1074 int ret;
1075
158bc065 1076 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL2, GLOBAL2_SMI_OP,
3898c148
AL		 1077 GLOBAL2_SMI_OP_22_READ | (addr << 5) |
1078 regnum);
1079 if (ret < 0)
1080 return ret;
f3044683 1081
158bc065 1082 ret = _mv88e6xxx_phy_wait(ps);
f3044683
AL		 1083 if (ret < 0)
1084 return ret;
1085
158bc065
AL		 1086 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL2, GLOBAL2_SMI_DATA);
1087
1088 return ret;
f3044683
AL		 1089}
1090
158bc065
AL		 1091static int _mv88e6xxx_phy_write_indirect(struct mv88e6xxx_priv_state *ps,
1092 int addr, int regnum, u16 val)
f3044683 1093{
3898c148
AL		 1094 int ret;
1095
158bc065 1096 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL2, GLOBAL2_SMI_DATA, val);
3898c148
AL		 1097 if (ret < 0)
1098 return ret;
f3044683 1099
158bc065 1100 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL2, GLOBAL2_SMI_OP,
3898c148
AL		 1101 GLOBAL2_SMI_OP_22_WRITE | (addr << 5) |
1102 regnum);
1103
158bc065 1104 return _mv88e6xxx_phy_wait(ps);
f3044683
AL		 1105}
1106
11b3b45d
GR		 1107int mv88e6xxx_get_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e)
1108{
2f40c698 1109 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
11b3b45d
GR		 1110 int reg;
1111
aadbdb8a
VD		 1112 if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_EEE))
1113 return -EOPNOTSUPP;
1114
3898c148 1115 mutex_lock(&ps->smi_mutex);
2f40c698 1116
158bc065 1117 reg = _mv88e6xxx_phy_read_indirect(ps, port, 16);
11b3b45d 1118 if (reg < 0)
2f40c698 1119 goto out;
11b3b45d
GR		 1120
1121 e->eee_enabled = !!(reg & 0x0200);
1122 e->tx_lpi_enabled = !!(reg & 0x0100);
1123
158bc065 1124 reg = _mv88e6xxx_reg_read(ps, REG_PORT(port), PORT_STATUS);
11b3b45d 1125 if (reg < 0)
2f40c698 1126 goto out;
11b3b45d 1127
cca8b133 1128 e->eee_active = !!(reg & PORT_STATUS_EEE);
2f40c698 1129 reg = 0;
11b3b45d 1130
2f40c698 1131out:
3898c148 1132 mutex_unlock(&ps->smi_mutex);
2f40c698 1133 return reg;
11b3b45d
GR		 1134}
1135
1136int mv88e6xxx_set_eee(struct dsa_switch *ds, int port,
1137 struct phy_device *phydev, struct ethtool_eee *e)
1138{
2f40c698
AL		 1139 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1140 int reg;
11b3b45d
GR		 1141 int ret;
1142
aadbdb8a
VD		 1143 if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_EEE))
1144 return -EOPNOTSUPP;
1145
3898c148 1146 mutex_lock(&ps->smi_mutex);
11b3b45d 1147
158bc065 1148 ret = _mv88e6xxx_phy_read_indirect(ps, port, 16);
2f40c698
AL		 1149 if (ret < 0)
1150 goto out;
1151
1152 reg = ret & ~0x0300;
1153 if (e->eee_enabled)
1154 reg |= 0x0200;
1155 if (e->tx_lpi_enabled)
1156 reg |= 0x0100;
1157
158bc065 1158 ret = _mv88e6xxx_phy_write_indirect(ps, port, 16, reg);
2f40c698 1159out:
3898c148 1160 mutex_unlock(&ps->smi_mutex);
2f40c698
AL		 1161
1162 return ret;
11b3b45d
GR		 1163}
1164
158bc065 1165static int _mv88e6xxx_atu_cmd(struct mv88e6xxx_priv_state *ps, u16 fid, u16 cmd)
facd95b2
GR		 1166{
1167 int ret;
1168
158bc065
AL		 1169 if (mv88e6xxx_has_fid_reg(ps)) {
1170 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_ATU_FID, fid);
b426e5f7
VD		 1171 if (ret < 0)
1172 return ret;
158bc065 1173 } else if (mv88e6xxx_num_databases(ps) == 256) {
11ea809f 1174 /* ATU DBNum[7:4] are located in ATU Control 15:12 */
158bc065 1175 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_ATU_CONTROL);
11ea809f
VD		 1176 if (ret < 0)
1177 return ret;
1178
158bc065 1179 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_ATU_CONTROL,
11ea809f
VD		 1180 (ret & 0xfff) |
1181 ((fid << 8) & 0xf000));
1182 if (ret < 0)
1183 return ret;
1184
1185 /* ATU DBNum[3:0] are located in ATU Operation 3:0 */
1186 cmd |= fid & 0xf;
b426e5f7
VD		 1187 }
1188
158bc065 1189 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_ATU_OP, cmd);
facd95b2
GR		 1190 if (ret < 0)
1191 return ret;
1192
158bc065 1193 return _mv88e6xxx_atu_wait(ps);
facd95b2
GR		 1194}
1195
158bc065 1196static int _mv88e6xxx_atu_data_write(struct mv88e6xxx_priv_state *ps,
37705b73
VD		 1197 struct mv88e6xxx_atu_entry *entry)
1198{
1199 u16 data = entry->state & GLOBAL_ATU_DATA_STATE_MASK;
1200
1201 if (entry->state != GLOBAL_ATU_DATA_STATE_UNUSED) {
1202 unsigned int mask, shift;
1203
1204 if (entry->trunk) {
1205 data |= GLOBAL_ATU_DATA_TRUNK;
1206 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
1207 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
1208 } else {
1209 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
1210 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
1211 }
1212
1213 data |= (entry->portv_trunkid << shift) & mask;
1214 }
1215
158bc065 1216 return _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_ATU_DATA, data);
37705b73
VD		 1217}
1218
158bc065 1219static int _mv88e6xxx_atu_flush_move(struct mv88e6xxx_priv_state *ps,
7fb5e755
VD		 1220 struct mv88e6xxx_atu_entry *entry,
1221 bool static_too)
facd95b2 1222{
7fb5e755
VD		 1223 int op;
1224 int err;
facd95b2 1225
158bc065 1226 err = _mv88e6xxx_atu_wait(ps);
7fb5e755
VD		 1227 if (err)
1228 return err;
facd95b2 1229
158bc065 1230 err = _mv88e6xxx_atu_data_write(ps, entry);
7fb5e755
VD		 1231 if (err)
1232 return err;
1233
1234 if (entry->fid) {
7fb5e755
VD		 1235 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL_DB :
1236 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC_DB;
1237 } else {
1238 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL :
1239 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC;
1240 }
1241
158bc065 1242 return _mv88e6xxx_atu_cmd(ps, entry->fid, op);
7fb5e755
VD		 1243}
1244
158bc065
AL		 1245static int _mv88e6xxx_atu_flush(struct mv88e6xxx_priv_state *ps,
1246 u16 fid, bool static_too)
7fb5e755
VD		 1247{
1248 struct mv88e6xxx_atu_entry entry = {
1249 .fid = fid,
1250 .state = 0, /* EntryState bits must be 0 */
1251 };
70cc99d1 1252
158bc065 1253 return _mv88e6xxx_atu_flush_move(ps, &entry, static_too);
7fb5e755
VD		 1254}
1255
158bc065
AL		 1256static int _mv88e6xxx_atu_move(struct mv88e6xxx_priv_state *ps, u16 fid,
1257 int from_port, int to_port, bool static_too)
9f4d55d2
VD		 1258{
1259 struct mv88e6xxx_atu_entry entry = {
1260 .trunk = false,
1261 .fid = fid,
1262 };
1263
1264 /* EntryState bits must be 0xF */
1265 entry.state = GLOBAL_ATU_DATA_STATE_MASK;
1266
1267 /* ToPort and FromPort are respectively in PortVec bits 7:4 and 3:0 */
1268 entry.portv_trunkid = (to_port & 0x0f) << 4;
1269 entry.portv_trunkid |= from_port & 0x0f;
1270
158bc065 1271 return _mv88e6xxx_atu_flush_move(ps, &entry, static_too);
9f4d55d2
VD		 1272}
1273
158bc065
AL		 1274static int _mv88e6xxx_atu_remove(struct mv88e6xxx_priv_state *ps, u16 fid,
1275 int port, bool static_too)
9f4d55d2
VD		 1276{
1277 /* Destination port 0xF means remove the entries */
158bc065 1278 return _mv88e6xxx_atu_move(ps, fid, port, 0x0f, static_too);
9f4d55d2
VD		 1279}
1280
2d9deae4
VD		 1281static const char * const mv88e6xxx_port_state_names[] = {
1282 [PORT_CONTROL_STATE_DISABLED] = "Disabled",
1283 [PORT_CONTROL_STATE_BLOCKING] = "Blocking/Listening",
1284 [PORT_CONTROL_STATE_LEARNING] = "Learning",
1285 [PORT_CONTROL_STATE_FORWARDING] = "Forwarding",
1286};
1287
158bc065
AL		 1288static int _mv88e6xxx_port_state(struct mv88e6xxx_priv_state *ps, int port,
1289 u8 state)
facd95b2 1290{
158bc065 1291 struct dsa_switch *ds = ps->ds;
c3ffe6d2 1292 int reg, ret = 0;
facd95b2
GR		 1293 u8 oldstate;
1294
158bc065 1295 reg = _mv88e6xxx_reg_read(ps, REG_PORT(port), PORT_CONTROL);
2d9deae4
VD		 1296 if (reg < 0)
1297 return reg;
facd95b2 1298
cca8b133 1299 oldstate = reg & PORT_CONTROL_STATE_MASK;
2d9deae4 1300
facd95b2
GR		 1301 if (oldstate != state) {
1302 /* Flush forwarding database if we're moving a port
1303 * from Learning or Forwarding state to Disabled or
1304 * Blocking or Listening state.
1305 */
2d9deae4
VD		 1306 if ((oldstate == PORT_CONTROL_STATE_LEARNING ||
1307 oldstate == PORT_CONTROL_STATE_FORWARDING)
1308 && (state == PORT_CONTROL_STATE_DISABLED ||
1309 state == PORT_CONTROL_STATE_BLOCKING)) {
158bc065 1310 ret = _mv88e6xxx_atu_remove(ps, 0, port, false);
facd95b2 1311 if (ret)
2d9deae4 1312 return ret;
facd95b2 1313 }
2d9deae4 1314
cca8b133 1315 reg = (reg & ~PORT_CONTROL_STATE_MASK) | state;
158bc065 1316 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), PORT_CONTROL,
cca8b133 1317 reg);
2d9deae4
VD		 1318 if (ret)
1319 return ret;
1320
1321 netdev_dbg(ds->ports[port], "PortState %s (was %s)\n",
1322 mv88e6xxx_port_state_names[state],
1323 mv88e6xxx_port_state_names[oldstate]);
facd95b2
GR		 1324 }
1325
facd95b2
GR		 1326 return ret;
1327}
1328
158bc065
AL		 1329static int _mv88e6xxx_port_based_vlan_map(struct mv88e6xxx_priv_state *ps,
1330 int port)
facd95b2 1331{
b7666efe 1332 struct net_device *bridge = ps->ports[port].bridge_dev;
009a2b98 1333 const u16 mask = (1 << ps->info->num_ports) - 1;
158bc065 1334 struct dsa_switch *ds = ps->ds;
b7666efe 1335 u16 output_ports = 0;
ede8098d 1336 int reg;
b7666efe
VD		 1337 int i;
1338
1339 /* allow CPU port or DSA link(s) to send frames to every port */
1340 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
1341 output_ports = mask;
1342 } else {
009a2b98 1343 for (i = 0; i < ps->info->num_ports; ++i) {
b7666efe
VD		 1344 /* allow sending frames to every group member */
1345 if (bridge && ps->ports[i].bridge_dev == bridge)
1346 output_ports |= BIT(i);
1347
1348 /* allow sending frames to CPU port and DSA link(s) */
1349 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
1350 output_ports |= BIT(i);
1351 }
1352 }
1353
1354 /* prevent frames from going back out of the port they came in on */
1355 output_ports &= ~BIT(port);
facd95b2 1356
158bc065 1357 reg = _mv88e6xxx_reg_read(ps, REG_PORT(port), PORT_BASE_VLAN);
ede8098d
VD		 1358 if (reg < 0)
1359 return reg;
facd95b2 1360
ede8098d
VD		 1361 reg &= ~mask;
1362 reg |= output_ports & mask;
facd95b2 1363
158bc065 1364 return _mv88e6xxx_reg_write(ps, REG_PORT(port), PORT_BASE_VLAN, reg);
facd95b2
GR		 1365}
1366
43c44a9f 1367void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
facd95b2
GR		 1368{
1369 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1370 int stp_state;
1371
1372 switch (state) {
1373 case BR_STATE_DISABLED:
cca8b133 1374 stp_state = PORT_CONTROL_STATE_DISABLED;
facd95b2
GR		 1375 break;
1376 case BR_STATE_BLOCKING:
1377 case BR_STATE_LISTENING:
cca8b133 1378 stp_state = PORT_CONTROL_STATE_BLOCKING;
facd95b2
GR		 1379 break;
1380 case BR_STATE_LEARNING:
cca8b133 1381 stp_state = PORT_CONTROL_STATE_LEARNING;
facd95b2
GR		 1382 break;
1383 case BR_STATE_FORWARDING:
1384 default:
cca8b133 1385 stp_state = PORT_CONTROL_STATE_FORWARDING;
facd95b2
GR		 1386 break;
1387 }
1388
43c44a9f 1389 /* mv88e6xxx_port_stp_state_set may be called with softirqs disabled,
facd95b2
GR		 1390 * so we can not update the port state directly but need to schedule it.
1391 */
d715fa64 1392 ps->ports[port].state = stp_state;
2d9deae4 1393 set_bit(port, ps->port_state_update_mask);
facd95b2 1394 schedule_work(&ps->bridge_work);
facd95b2
GR		 1395}
1396
158bc065
AL		 1397static int _mv88e6xxx_port_pvid(struct mv88e6xxx_priv_state *ps, int port,
1398 u16 *new, u16 *old)
76e398a6 1399{
158bc065 1400 struct dsa_switch *ds = ps->ds;
5da96031 1401 u16 pvid;
76e398a6
VD		 1402 int ret;
1403
158bc065 1404 ret = _mv88e6xxx_reg_read(ps, REG_PORT(port), PORT_DEFAULT_VLAN);
76e398a6
VD		 1405 if (ret < 0)
1406 return ret;
1407
5da96031
VD		 1408 pvid = ret & PORT_DEFAULT_VLAN_MASK;
1409
1410 if (new) {
1411 ret &= ~PORT_DEFAULT_VLAN_MASK;
1412 ret |= *new & PORT_DEFAULT_VLAN_MASK;
1413
158bc065 1414 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port),
5da96031
VD		 1415 PORT_DEFAULT_VLAN, ret);
1416 if (ret < 0)
1417 return ret;
1418
1419 netdev_dbg(ds->ports[port], "DefaultVID %d (was %d)\n", *new,
1420 pvid);
1421 }
1422
1423 if (old)
1424 *old = pvid;
76e398a6
VD		 1425
1426 return 0;
1427}
1428
158bc065
AL		 1429static int _mv88e6xxx_port_pvid_get(struct mv88e6xxx_priv_state *ps,
1430 int port, u16 *pvid)
5da96031 1431{
158bc065 1432 return _mv88e6xxx_port_pvid(ps, port, NULL, pvid);
5da96031
VD		 1433}
1434
158bc065
AL		 1435static int _mv88e6xxx_port_pvid_set(struct mv88e6xxx_priv_state *ps,
1436 int port, u16 pvid)
0d3b33e6 1437{
158bc065 1438 return _mv88e6xxx_port_pvid(ps, port, &pvid, NULL);
0d3b33e6
VD		 1439}
1440
158bc065 1441static int _mv88e6xxx_vtu_wait(struct mv88e6xxx_priv_state *ps)
6b17e864 1442{
158bc065 1443 return _mv88e6xxx_wait(ps, REG_GLOBAL, GLOBAL_VTU_OP,
6b17e864
VD		 1444 GLOBAL_VTU_OP_BUSY);
1445}
1446
158bc065 1447static int _mv88e6xxx_vtu_cmd(struct mv88e6xxx_priv_state *ps, u16 op)
6b17e864
VD		 1448{
1449 int ret;
1450
158bc065 1451 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_VTU_OP, op);
6b17e864
VD		 1452 if (ret < 0)
1453 return ret;
1454
158bc065 1455 return _mv88e6xxx_vtu_wait(ps);
6b17e864
VD		 1456}
1457
158bc065 1458static int _mv88e6xxx_vtu_stu_flush(struct mv88e6xxx_priv_state *ps)
6b17e864
VD		 1459{
1460 int ret;
1461
158bc065 1462 ret = _mv88e6xxx_vtu_wait(ps);
6b17e864
VD		 1463 if (ret < 0)
1464 return ret;
1465
158bc065 1466 return _mv88e6xxx_vtu_cmd(ps, GLOBAL_VTU_OP_FLUSH_ALL);
6b17e864
VD		 1467}
1468
158bc065 1469static int _mv88e6xxx_vtu_stu_data_read(struct mv88e6xxx_priv_state *ps,
b8fee957
VD		 1470 struct mv88e6xxx_vtu_stu_entry *entry,
1471 unsigned int nibble_offset)
1472{
b8fee957
VD		 1473 u16 regs[3];
1474 int i;
1475 int ret;
1476
1477 for (i = 0; i < 3; ++i) {
158bc065 1478 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL,
b8fee957
VD		 1479 GLOBAL_VTU_DATA_0_3 + i);
1480 if (ret < 0)
1481 return ret;
1482
1483 regs[i] = ret;
1484 }
1485
009a2b98 1486 for (i = 0; i < ps->info->num_ports; ++i) {
b8fee957
VD		 1487 unsigned int shift = (i % 4) * 4 + nibble_offset;
1488 u16 reg = regs[i / 4];
1489
1490 entry->data[i] = (reg >> shift) & GLOBAL_VTU_STU_DATA_MASK;
1491 }
1492
1493 return 0;
1494}
1495
158bc065 1496static int _mv88e6xxx_vtu_stu_data_write(struct mv88e6xxx_priv_state *ps,
7dad08d7
VD		 1497 struct mv88e6xxx_vtu_stu_entry *entry,
1498 unsigned int nibble_offset)
1499{
7dad08d7
VD		 1500 u16 regs[3] = { 0 };
1501 int i;
1502 int ret;
1503
009a2b98 1504 for (i = 0; i < ps->info->num_ports; ++i) {
7dad08d7
VD		 1505 unsigned int shift = (i % 4) * 4 + nibble_offset;
1506 u8 data = entry->data[i];
1507
1508 regs[i / 4] |= (data & GLOBAL_VTU_STU_DATA_MASK) << shift;
1509 }
1510
1511 for (i = 0; i < 3; ++i) {
158bc065 1512 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL,
7dad08d7
VD		 1513 GLOBAL_VTU_DATA_0_3 + i, regs[i]);
1514 if (ret < 0)
1515 return ret;
1516 }
1517
1518 return 0;
1519}
1520
158bc065 1521static int _mv88e6xxx_vtu_vid_write(struct mv88e6xxx_priv_state *ps, u16 vid)
36d04ba1 1522{
158bc065 1523 return _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_VTU_VID,
36d04ba1
VD		 1524 vid & GLOBAL_VTU_VID_MASK);
1525}
1526
158bc065 1527static int _mv88e6xxx_vtu_getnext(struct mv88e6xxx_priv_state *ps,
b8fee957
VD		 1528 struct mv88e6xxx_vtu_stu_entry *entry)
1529{
1530 struct mv88e6xxx_vtu_stu_entry next = { 0 };
1531 int ret;
1532
158bc065 1533 ret = _mv88e6xxx_vtu_wait(ps);
b8fee957
VD		 1534 if (ret < 0)
1535 return ret;
1536
158bc065 1537 ret = _mv88e6xxx_vtu_cmd(ps, GLOBAL_VTU_OP_VTU_GET_NEXT);
b8fee957
VD		 1538 if (ret < 0)
1539 return ret;
1540
158bc065 1541 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_VTU_VID);
b8fee957
VD		 1542 if (ret < 0)
1543 return ret;
1544
1545 next.vid = ret & GLOBAL_VTU_VID_MASK;
1546 next.valid = !!(ret & GLOBAL_VTU_VID_VALID);
1547
1548 if (next.valid) {
158bc065 1549 ret = _mv88e6xxx_vtu_stu_data_read(ps, &next, 0);
b8fee957
VD		 1550 if (ret < 0)
1551 return ret;
1552
158bc065
AL		 1553 if (mv88e6xxx_has_fid_reg(ps)) {
1554 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL,
b8fee957
VD		 1555 GLOBAL_VTU_FID);
1556 if (ret < 0)
1557 return ret;
1558
1559 next.fid = ret & GLOBAL_VTU_FID_MASK;
158bc065 1560 } else if (mv88e6xxx_num_databases(ps) == 256) {
11ea809f
VD		 1561 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1562 * VTU DBNum[3:0] are located in VTU Operation 3:0
1563 */
158bc065 1564 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL,
11ea809f
VD		 1565 GLOBAL_VTU_OP);
1566 if (ret < 0)
1567 return ret;
1568
1569 next.fid = (ret & 0xf00) >> 4;
1570 next.fid |= ret & 0xf;
2e7bd5ef 1571 }
b8fee957 1572
158bc065
AL		 1573 if (mv88e6xxx_has_stu(ps)) {
1574 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL,
b8fee957
VD		 1575 GLOBAL_VTU_SID);
1576 if (ret < 0)
1577 return ret;
1578
1579 next.sid = ret & GLOBAL_VTU_SID_MASK;
1580 }
1581 }
1582
1583 *entry = next;
1584 return 0;
1585}
1586
ceff5eff
VD		 1587int mv88e6xxx_port_vlan_dump(struct dsa_switch *ds, int port,
1588 struct switchdev_obj_port_vlan *vlan,
1589 int (*cb)(struct switchdev_obj *obj))
1590{
1591 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1592 struct mv88e6xxx_vtu_stu_entry next;
1593 u16 pvid;
1594 int err;
1595
1596 mutex_lock(&ps->smi_mutex);
1597
158bc065 1598 err = _mv88e6xxx_port_pvid_get(ps, port, &pvid);
ceff5eff
VD		 1599 if (err)
1600 goto unlock;
1601
158bc065 1602 err = _mv88e6xxx_vtu_vid_write(ps, GLOBAL_VTU_VID_MASK);
ceff5eff
VD		 1603 if (err)
1604 goto unlock;
1605
1606 do {
158bc065 1607 err = _mv88e6xxx_vtu_getnext(ps, &next);
ceff5eff
VD		 1608 if (err)
1609 break;
1610
1611 if (!next.valid)
1612 break;
1613
1614 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1615 continue;
1616
1617 /* reinit and dump this VLAN obj */
1618 vlan->vid_begin = vlan->vid_end = next.vid;
1619 vlan->flags = 0;
1620
1621 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED)
1622 vlan->flags |= BRIDGE_VLAN_INFO_UNTAGGED;
1623
1624 if (next.vid == pvid)
1625 vlan->flags |= BRIDGE_VLAN_INFO_PVID;
1626
1627 err = cb(&vlan->obj);
1628 if (err)
1629 break;
1630 } while (next.vid < GLOBAL_VTU_VID_MASK);
1631
1632unlock:
1633 mutex_unlock(&ps->smi_mutex);
1634
1635 return err;
1636}
1637
158bc065 1638static int _mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_priv_state *ps,
7dad08d7
VD		 1639 struct mv88e6xxx_vtu_stu_entry *entry)
1640{
11ea809f 1641 u16 op = GLOBAL_VTU_OP_VTU_LOAD_PURGE;
7dad08d7
VD		 1642 u16 reg = 0;
1643 int ret;
1644
158bc065 1645 ret = _mv88e6xxx_vtu_wait(ps);
7dad08d7
VD		 1646 if (ret < 0)
1647 return ret;
1648
1649 if (!entry->valid)
1650 goto loadpurge;
1651
1652 /* Write port member tags */
158bc065 1653 ret = _mv88e6xxx_vtu_stu_data_write(ps, entry, 0);
7dad08d7
VD		 1654 if (ret < 0)
1655 return ret;
1656
158bc065 1657 if (mv88e6xxx_has_stu(ps)) {
7dad08d7 1658 reg = entry->sid & GLOBAL_VTU_SID_MASK;
158bc065 1659 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_VTU_SID, reg);
7dad08d7
VD		 1660 if (ret < 0)
1661 return ret;
b426e5f7 1662 }
7dad08d7 1663
158bc065 1664 if (mv88e6xxx_has_fid_reg(ps)) {
7dad08d7 1665 reg = entry->fid & GLOBAL_VTU_FID_MASK;
158bc065 1666 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_VTU_FID, reg);
7dad08d7
VD		 1667 if (ret < 0)
1668 return ret;
158bc065 1669 } else if (mv88e6xxx_num_databases(ps) == 256) {
11ea809f
VD		 1670 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1671 * VTU DBNum[3:0] are located in VTU Operation 3:0
1672 */
1673 op |= (entry->fid & 0xf0) << 8;
1674 op |= entry->fid & 0xf;
7dad08d7
VD		 1675 }
1676
1677 reg = GLOBAL_VTU_VID_VALID;
1678loadpurge:
1679 reg |= entry->vid & GLOBAL_VTU_VID_MASK;
158bc065 1680 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_VTU_VID, reg);
7dad08d7
VD		 1681 if (ret < 0)
1682 return ret;
1683
158bc065 1684 return _mv88e6xxx_vtu_cmd(ps, op);
7dad08d7
VD		 1685}
1686
158bc065 1687static int _mv88e6xxx_stu_getnext(struct mv88e6xxx_priv_state *ps, u8 sid,
0d3b33e6
VD		 1688 struct mv88e6xxx_vtu_stu_entry *entry)
1689{
1690 struct mv88e6xxx_vtu_stu_entry next = { 0 };
1691 int ret;
1692
158bc065 1693 ret = _mv88e6xxx_vtu_wait(ps);
0d3b33e6
VD		 1694 if (ret < 0)
1695 return ret;
1696
158bc065 1697 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_VTU_SID,
0d3b33e6
VD		 1698 sid & GLOBAL_VTU_SID_MASK);
1699 if (ret < 0)
1700 return ret;
1701
158bc065 1702 ret = _mv88e6xxx_vtu_cmd(ps, GLOBAL_VTU_OP_STU_GET_NEXT);
0d3b33e6
VD		 1703 if (ret < 0)
1704 return ret;
1705
158bc065 1706 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_VTU_SID);
0d3b33e6
VD		 1707 if (ret < 0)
1708 return ret;
1709
1710 next.sid = ret & GLOBAL_VTU_SID_MASK;
1711
158bc065 1712 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_VTU_VID);
0d3b33e6
VD		 1713 if (ret < 0)
1714 return ret;
1715
1716 next.valid = !!(ret & GLOBAL_VTU_VID_VALID);
1717
1718 if (next.valid) {
158bc065 1719 ret = _mv88e6xxx_vtu_stu_data_read(ps, &next, 2);
0d3b33e6
VD		 1720 if (ret < 0)
1721 return ret;
1722 }
1723
1724 *entry = next;
1725 return 0;
1726}
1727
158bc065 1728static int _mv88e6xxx_stu_loadpurge(struct mv88e6xxx_priv_state *ps,
0d3b33e6
VD		 1729 struct mv88e6xxx_vtu_stu_entry *entry)
1730{
1731 u16 reg = 0;
1732 int ret;
1733
158bc065 1734 ret = _mv88e6xxx_vtu_wait(ps);
0d3b33e6
VD		 1735 if (ret < 0)
1736 return ret;
1737
1738 if (!entry->valid)
1739 goto loadpurge;
1740
1741 /* Write port states */
158bc065 1742 ret = _mv88e6xxx_vtu_stu_data_write(ps, entry, 2);
0d3b33e6
VD		 1743 if (ret < 0)
1744 return ret;
1745
1746 reg = GLOBAL_VTU_VID_VALID;
1747loadpurge:
158bc065 1748 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_VTU_VID, reg);
0d3b33e6
VD		 1749 if (ret < 0)
1750 return ret;
1751
1752 reg = entry->sid & GLOBAL_VTU_SID_MASK;
158bc065 1753 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_VTU_SID, reg);
0d3b33e6
VD		 1754 if (ret < 0)
1755 return ret;
1756
158bc065 1757 return _mv88e6xxx_vtu_cmd(ps, GLOBAL_VTU_OP_STU_LOAD_PURGE);
0d3b33e6
VD		 1758}
1759
158bc065
AL		 1760static int _mv88e6xxx_port_fid(struct mv88e6xxx_priv_state *ps, int port,
1761 u16 *new, u16 *old)
2db9ce1f 1762{
158bc065 1763 struct dsa_switch *ds = ps->ds;
f74df0be 1764 u16 upper_mask;
2db9ce1f
VD		 1765 u16 fid;
1766 int ret;
1767
158bc065 1768 if (mv88e6xxx_num_databases(ps) == 4096)
f74df0be 1769 upper_mask = 0xff;
158bc065 1770 else if (mv88e6xxx_num_databases(ps) == 256)
11ea809f 1771 upper_mask = 0xf;
f74df0be
VD		 1772 else
1773 return -EOPNOTSUPP;
1774
2db9ce1f 1775 /* Port's default FID bits 3:0 are located in reg 0x06, offset 12 */
158bc065 1776 ret = _mv88e6xxx_reg_read(ps, REG_PORT(port), PORT_BASE_VLAN);
2db9ce1f
VD		 1777 if (ret < 0)
1778 return ret;
1779
1780 fid = (ret & PORT_BASE_VLAN_FID_3_0_MASK) >> 12;
1781
1782 if (new) {
1783 ret &= ~PORT_BASE_VLAN_FID_3_0_MASK;
1784 ret |= (*new << 12) & PORT_BASE_VLAN_FID_3_0_MASK;
1785
158bc065 1786 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), PORT_BASE_VLAN,
2db9ce1f
VD		 1787 ret);
1788 if (ret < 0)
1789 return ret;
1790 }
1791
1792 /* Port's default FID bits 11:4 are located in reg 0x05, offset 0 */
158bc065 1793 ret = _mv88e6xxx_reg_read(ps, REG_PORT(port), PORT_CONTROL_1);
2db9ce1f
VD		 1794 if (ret < 0)
1795 return ret;
1796
f74df0be 1797 fid |= (ret & upper_mask) << 4;
2db9ce1f
VD		 1798
1799 if (new) {
f74df0be
VD		 1800 ret &= ~upper_mask;
1801 ret |= (*new >> 4) & upper_mask;
2db9ce1f 1802
158bc065 1803 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), PORT_CONTROL_1,
2db9ce1f
VD		 1804 ret);
1805 if (ret < 0)
1806 return ret;
1807
1808 netdev_dbg(ds->ports[port], "FID %d (was %d)\n", *new, fid);
1809 }
1810
1811 if (old)
1812 *old = fid;
1813
1814 return 0;
1815}
1816
158bc065
AL		 1817static int _mv88e6xxx_port_fid_get(struct mv88e6xxx_priv_state *ps,
1818 int port, u16 *fid)
2db9ce1f 1819{
158bc065 1820 return _mv88e6xxx_port_fid(ps, port, NULL, fid);
2db9ce1f
VD		 1821}
1822
158bc065
AL		 1823static int _mv88e6xxx_port_fid_set(struct mv88e6xxx_priv_state *ps,
1824 int port, u16 fid)
2db9ce1f 1825{
158bc065 1826 return _mv88e6xxx_port_fid(ps, port, &fid, NULL);
2db9ce1f
VD		 1827}
1828
158bc065 1829static int _mv88e6xxx_fid_new(struct mv88e6xxx_priv_state *ps, u16 *fid)
3285f9e8
VD		 1830{
1831 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
1832 struct mv88e6xxx_vtu_stu_entry vlan;
2db9ce1f 1833 int i, err;
3285f9e8
VD		 1834
1835 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1836
2db9ce1f 1837 /* Set every FID bit used by the (un)bridged ports */
009a2b98 1838 for (i = 0; i < ps->info->num_ports; ++i) {
158bc065 1839 err = _mv88e6xxx_port_fid_get(ps, i, fid);
2db9ce1f
VD		 1840 if (err)
1841 return err;
1842
1843 set_bit(*fid, fid_bitmap);
1844 }
1845
3285f9e8 1846 /* Set every FID bit used by the VLAN entries */
158bc065 1847 err = _mv88e6xxx_vtu_vid_write(ps, GLOBAL_VTU_VID_MASK);
3285f9e8
VD		 1848 if (err)
1849 return err;
1850
1851 do {
158bc065 1852 err = _mv88e6xxx_vtu_getnext(ps, &vlan);
3285f9e8
VD		 1853 if (err)
1854 return err;
1855
1856 if (!vlan.valid)
1857 break;
1858
1859 set_bit(vlan.fid, fid_bitmap);
1860 } while (vlan.vid < GLOBAL_VTU_VID_MASK);
1861
1862 /* The reset value 0x000 is used to indicate that multiple address
1863 * databases are not needed. Return the next positive available.
1864 */
1865 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
158bc065 1866 if (unlikely(*fid >= mv88e6xxx_num_databases(ps)))
3285f9e8
VD		 1867 return -ENOSPC;
1868
1869 /* Clear the database */
158bc065 1870 return _mv88e6xxx_atu_flush(ps, *fid, true);
3285f9e8
VD		 1871}
1872
158bc065 1873static int _mv88e6xxx_vtu_new(struct mv88e6xxx_priv_state *ps, u16 vid,
2fb5ef09 1874 struct mv88e6xxx_vtu_stu_entry *entry)
0d3b33e6 1875{
158bc065 1876 struct dsa_switch *ds = ps->ds;
0d3b33e6
VD		 1877 struct mv88e6xxx_vtu_stu_entry vlan = {
1878 .valid = true,
1879 .vid = vid,
1880 };
3285f9e8
VD		 1881 int i, err;
1882
158bc065 1883 err = _mv88e6xxx_fid_new(ps, &vlan.fid);
3285f9e8
VD		 1884 if (err)
1885 return err;
0d3b33e6 1886
3d131f07 1887 /* exclude all ports except the CPU and DSA ports */
009a2b98 1888 for (i = 0; i < ps->info->num_ports; ++i)
3d131f07
VD		 1889 vlan.data[i] = dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i)
1890 ? GLOBAL_VTU_DATA_MEMBER_TAG_UNMODIFIED
1891 : GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
0d3b33e6 1892
158bc065
AL		 1893 if (mv88e6xxx_6097_family(ps) || mv88e6xxx_6165_family(ps) ||
1894 mv88e6xxx_6351_family(ps) || mv88e6xxx_6352_family(ps)) {
0d3b33e6 1895 struct mv88e6xxx_vtu_stu_entry vstp;
0d3b33e6
VD		 1896
1897 /* Adding a VTU entry requires a valid STU entry. As VSTP is not
1898 * implemented, only one STU entry is needed to cover all VTU
1899 * entries. Thus, validate the SID 0.
1900 */
1901 vlan.sid = 0;
158bc065 1902 err = _mv88e6xxx_stu_getnext(ps, GLOBAL_VTU_SID_MASK, &vstp);
0d3b33e6
VD		 1903 if (err)
1904 return err;
1905
1906 if (vstp.sid != vlan.sid || !vstp.valid) {
1907 memset(&vstp, 0, sizeof(vstp));
1908 vstp.valid = true;
1909 vstp.sid = vlan.sid;
1910
158bc065 1911 err = _mv88e6xxx_stu_loadpurge(ps, &vstp);
0d3b33e6
VD		 1912 if (err)
1913 return err;
1914 }
0d3b33e6
VD		 1915 }
1916
1917 *entry = vlan;
1918 return 0;
1919}
1920
158bc065 1921static int _mv88e6xxx_vtu_get(struct mv88e6xxx_priv_state *ps, u16 vid,
2fb5ef09
VD		 1922 struct mv88e6xxx_vtu_stu_entry *entry, bool creat)
1923{
1924 int err;
1925
1926 if (!vid)
1927 return -EINVAL;
1928
158bc065 1929 err = _mv88e6xxx_vtu_vid_write(ps, vid - 1);
2fb5ef09
VD		 1930 if (err)
1931 return err;
1932
158bc065 1933 err = _mv88e6xxx_vtu_getnext(ps, entry);
2fb5ef09
VD		 1934 if (err)
1935 return err;
1936
1937 if (entry->vid != vid || !entry->valid) {
1938 if (!creat)
1939 return -EOPNOTSUPP;
1940 /* -ENOENT would've been more appropriate, but switchdev expects
1941 * -EOPNOTSUPP to inform bridge about an eventual software VLAN.
1942 */
1943
158bc065 1944 err = _mv88e6xxx_vtu_new(ps, vid, entry);
2fb5ef09
VD		 1945 }
1946
1947 return err;
1948}
1949
da9c359e
VD		 1950static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
1951 u16 vid_begin, u16 vid_end)
1952{
1953 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1954 struct mv88e6xxx_vtu_stu_entry vlan;
1955 int i, err;
1956
1957 if (!vid_begin)
1958 return -EOPNOTSUPP;
1959
1960 mutex_lock(&ps->smi_mutex);
1961
158bc065 1962 err = _mv88e6xxx_vtu_vid_write(ps, vid_begin - 1);
da9c359e
VD		 1963 if (err)
1964 goto unlock;
1965
1966 do {
158bc065 1967 err = _mv88e6xxx_vtu_getnext(ps, &vlan);
da9c359e
VD		 1968 if (err)
1969 goto unlock;
1970
1971 if (!vlan.valid)
1972 break;
1973
1974 if (vlan.vid > vid_end)
1975 break;
1976
009a2b98 1977 for (i = 0; i < ps->info->num_ports; ++i) {
da9c359e
VD		 1978 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
1979 continue;
1980
1981 if (vlan.data[i] ==
1982 GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1983 continue;
1984
1985 if (ps->ports[i].bridge_dev ==
1986 ps->ports[port].bridge_dev)
1987 break; /* same bridge, check next VLAN */
1988
1989 netdev_warn(ds->ports[port],
1990 "hardware VLAN %d already used by %s\n",
1991 vlan.vid,
1992 netdev_name(ps->ports[i].bridge_dev));
1993 err = -EOPNOTSUPP;
1994 goto unlock;
1995 }
1996 } while (vlan.vid < vid_end);
1997
1998unlock:
1999 mutex_unlock(&ps->smi_mutex);
2000
2001 return err;
2002}
2003
214cdb99
VD		 2004static const char * const mv88e6xxx_port_8021q_mode_names[] = {
2005 [PORT_CONTROL_2_8021Q_DISABLED] = "Disabled",
2006 [PORT_CONTROL_2_8021Q_FALLBACK] = "Fallback",
2007 [PORT_CONTROL_2_8021Q_CHECK] = "Check",
2008 [PORT_CONTROL_2_8021Q_SECURE] = "Secure",
2009};
2010
2011int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
2012 bool vlan_filtering)
2013{
2014 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2015 u16 old, new = vlan_filtering ? PORT_CONTROL_2_8021Q_SECURE :
2016 PORT_CONTROL_2_8021Q_DISABLED;
2017 int ret;
2018
2019 mutex_lock(&ps->smi_mutex);
2020
158bc065 2021 ret = _mv88e6xxx_reg_read(ps, REG_PORT(port), PORT_CONTROL_2);
214cdb99
VD		 2022 if (ret < 0)
2023 goto unlock;
2024
2025 old = ret & PORT_CONTROL_2_8021Q_MASK;
2026
5220ef1e
VD		 2027 if (new != old) {
2028 ret &= ~PORT_CONTROL_2_8021Q_MASK;
2029 ret |= new & PORT_CONTROL_2_8021Q_MASK;
214cdb99 2030
158bc065 2031 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), PORT_CONTROL_2,
5220ef1e
VD		 2032 ret);
2033 if (ret < 0)
2034 goto unlock;
2035
2036 netdev_dbg(ds->ports[port], "802.1Q Mode %s (was %s)\n",
2037 mv88e6xxx_port_8021q_mode_names[new],
2038 mv88e6xxx_port_8021q_mode_names[old]);
2039 }
214cdb99 2040
5220ef1e 2041 ret = 0;
214cdb99
VD		 2042unlock:
2043 mutex_unlock(&ps->smi_mutex);
2044
2045 return ret;
2046}
2047
76e398a6
VD		 2048int mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
2049 const struct switchdev_obj_port_vlan *vlan,
2050 struct switchdev_trans *trans)
2051{
da9c359e
VD		 2052 int err;
2053
da9c359e
VD		 2054 /* If the requested port doesn't belong to the same bridge as the VLAN
2055 * members, do not support it (yet) and fallback to software VLAN.
2056 */
2057 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin,
2058 vlan->vid_end);
2059 if (err)
2060 return err;
2061
76e398a6
VD		 2062 /* We don't need any dynamic resource from the kernel (yet),
2063 * so skip the prepare phase.
2064 */
2065 return 0;
2066}
2067
158bc065
AL		 2068static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_priv_state *ps, int port,
2069 u16 vid, bool untagged)
0d3b33e6 2070{
0d3b33e6
VD		 2071 struct mv88e6xxx_vtu_stu_entry vlan;
2072 int err;
2073
158bc065 2074 err = _mv88e6xxx_vtu_get(ps, vid, &vlan, true);
0d3b33e6 2075 if (err)
76e398a6 2076 return err;
0d3b33e6 2077
0d3b33e6
VD		 2078 vlan.data[port] = untagged ?
2079 GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED :
2080 GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED;
2081
158bc065 2082 return _mv88e6xxx_vtu_loadpurge(ps, &vlan);
76e398a6
VD		 2083}
2084
4d5770b3
VD		 2085void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
2086 const struct switchdev_obj_port_vlan *vlan,
2087 struct switchdev_trans *trans)
76e398a6
VD		 2088{
2089 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2090 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
2091 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
2092 u16 vid;
76e398a6
VD		 2093
2094 mutex_lock(&ps->smi_mutex);
2095
4d5770b3 2096 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid)
158bc065 2097 if (_mv88e6xxx_port_vlan_add(ps, port, vid, untagged))
4d5770b3
VD		 2098 netdev_err(ds->ports[port], "failed to add VLAN %d%c\n",
2099 vid, untagged ? 'u' : 't');
76e398a6 2100
158bc065 2101 if (pvid && _mv88e6xxx_port_pvid_set(ps, port, vlan->vid_end))
4d5770b3
VD		 2102 netdev_err(ds->ports[port], "failed to set PVID %d\n",
2103 vlan->vid_end);
0d3b33e6 2104
4d5770b3 2105 mutex_unlock(&ps->smi_mutex);
0d3b33e6
VD		 2106}
2107
158bc065
AL		 2108static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_priv_state *ps,
2109 int port, u16 vid)
7dad08d7 2110{
158bc065 2111 struct dsa_switch *ds = ps->ds;
7dad08d7 2112 struct mv88e6xxx_vtu_stu_entry vlan;
7dad08d7
VD		 2113 int i, err;
2114
158bc065 2115 err = _mv88e6xxx_vtu_get(ps, vid, &vlan, false);
7dad08d7 2116 if (err)
76e398a6 2117 return err;
7dad08d7 2118
2fb5ef09
VD		 2119 /* Tell switchdev if this VLAN is handled in software */
2120 if (vlan.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
3c06f08b 2121 return -EOPNOTSUPP;
7dad08d7
VD		 2122
2123 vlan.data[port] = GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
2124
2125 /* keep the VLAN unless all ports are excluded */
f02bdffc 2126 vlan.valid = false;
009a2b98 2127 for (i = 0; i < ps->info->num_ports; ++i) {
3d131f07 2128 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
7dad08d7
VD		 2129 continue;
2130
2131 if (vlan.data[i] != GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
f02bdffc 2132 vlan.valid = true;
7dad08d7
VD		 2133 break;
2134 }
2135 }
2136
158bc065 2137 err = _mv88e6xxx_vtu_loadpurge(ps, &vlan);
76e398a6
VD		 2138 if (err)
2139 return err;
2140
158bc065 2141 return _mv88e6xxx_atu_remove(ps, vlan.fid, port, false);
76e398a6
VD		 2142}
2143
2144int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
2145 const struct switchdev_obj_port_vlan *vlan)
2146{
2147 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2148 u16 pvid, vid;
2149 int err = 0;
2150
2151 mutex_lock(&ps->smi_mutex);
2152
158bc065 2153 err = _mv88e6xxx_port_pvid_get(ps, port, &pvid);
7dad08d7
VD		 2154 if (err)
2155 goto unlock;
2156
76e398a6 2157 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
158bc065 2158 err = _mv88e6xxx_port_vlan_del(ps, port, vid);
76e398a6
VD		 2159 if (err)
2160 goto unlock;
2161
2162 if (vid == pvid) {
158bc065 2163 err = _mv88e6xxx_port_pvid_set(ps, port, 0);
76e398a6
VD		 2164 if (err)
2165 goto unlock;
2166 }
2167 }
2168
7dad08d7
VD		 2169unlock:
2170 mutex_unlock(&ps->smi_mutex);
2171
2172 return err;
2173}
2174
158bc065 2175static int _mv88e6xxx_atu_mac_write(struct mv88e6xxx_priv_state *ps,
c5723ac5 2176 const unsigned char *addr)
defb05b9
GR		 2177{
2178 int i, ret;
2179
2180 for (i = 0; i < 3; i++) {
cca8b133 2181 ret = _mv88e6xxx_reg_write(
158bc065 2182 ps, REG_GLOBAL, GLOBAL_ATU_MAC_01 + i,
cca8b133 2183 (addr[i * 2] << 8) | addr[i * 2 + 1]);
defb05b9
GR		 2184 if (ret < 0)
2185 return ret;
2186 }
2187
2188 return 0;
2189}
2190
158bc065
AL		 2191static int _mv88e6xxx_atu_mac_read(struct mv88e6xxx_priv_state *ps,
2192 unsigned char *addr)
defb05b9
GR		 2193{
2194 int i, ret;
2195
2196 for (i = 0; i < 3; i++) {
158bc065 2197 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL,
cca8b133 2198 GLOBAL_ATU_MAC_01 + i);
defb05b9
GR		 2199 if (ret < 0)
2200 return ret;
2201 addr[i * 2] = ret >> 8;
2202 addr[i * 2 + 1] = ret & 0xff;
2203 }
2204
2205 return 0;
2206}
2207
158bc065 2208static int _mv88e6xxx_atu_load(struct mv88e6xxx_priv_state *ps,
fd231c82 2209 struct mv88e6xxx_atu_entry *entry)
defb05b9 2210{
6630e236
VD		 2211 int ret;
2212
158bc065 2213 ret = _mv88e6xxx_atu_wait(ps);
defb05b9
GR		 2214 if (ret < 0)
2215 return ret;
2216
158bc065 2217 ret = _mv88e6xxx_atu_mac_write(ps, entry->mac);
defb05b9
GR		 2218 if (ret < 0)
2219 return ret;
2220
158bc065 2221 ret = _mv88e6xxx_atu_data_write(ps, entry);
fd231c82 2222 if (ret < 0)
87820510
VD		 2223 return ret;
2224
158bc065 2225 return _mv88e6xxx_atu_cmd(ps, entry->fid, GLOBAL_ATU_OP_LOAD_DB);
fd231c82 2226}
87820510 2227
158bc065 2228static int _mv88e6xxx_port_fdb_load(struct mv88e6xxx_priv_state *ps, int port,
fd231c82
VD		 2229 const unsigned char *addr, u16 vid,
2230 u8 state)
2231{
2232 struct mv88e6xxx_atu_entry entry = { 0 };
3285f9e8
VD		 2233 struct mv88e6xxx_vtu_stu_entry vlan;
2234 int err;
2235
2db9ce1f
VD		 2236 /* Null VLAN ID corresponds to the port private database */
2237 if (vid == 0)
158bc065 2238 err = _mv88e6xxx_port_fid_get(ps, port, &vlan.fid);
2db9ce1f 2239 else
158bc065 2240 err = _mv88e6xxx_vtu_get(ps, vid, &vlan, false);
3285f9e8
VD		 2241 if (err)
2242 return err;
fd231c82 2243
3285f9e8 2244 entry.fid = vlan.fid;
fd231c82
VD		 2245 entry.state = state;
2246 ether_addr_copy(entry.mac, addr);
2247 if (state != GLOBAL_ATU_DATA_STATE_UNUSED) {
2248 entry.trunk = false;
2249 entry.portv_trunkid = BIT(port);
2250 }
2251
158bc065 2252 return _mv88e6xxx_atu_load(ps, &entry);
87820510
VD		 2253}
2254
146a3206
VD		 2255int mv88e6xxx_port_fdb_prepare(struct dsa_switch *ds, int port,
2256 const struct switchdev_obj_port_fdb *fdb,
2257 struct switchdev_trans *trans)
2258{
2259 /* We don't need any dynamic resource from the kernel (yet),
2260 * so skip the prepare phase.
2261 */
2262 return 0;
2263}
2264
8497aa61
VD		 2265void mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
2266 const struct switchdev_obj_port_fdb *fdb,
2267 struct switchdev_trans *trans)
87820510 2268{
1f36faf2 2269 int state = is_multicast_ether_addr(fdb->addr) ?
87820510
VD		 2270 GLOBAL_ATU_DATA_STATE_MC_STATIC :
2271 GLOBAL_ATU_DATA_STATE_UC_STATIC;
cdf09697 2272 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
87820510
VD		 2273
2274 mutex_lock(&ps->smi_mutex);
158bc065 2275 if (_mv88e6xxx_port_fdb_load(ps, port, fdb->addr, fdb->vid, state))
8497aa61 2276 netdev_err(ds->ports[port], "failed to load MAC address\n");
87820510 2277 mutex_unlock(&ps->smi_mutex);
87820510
VD		 2278}
2279
cdf09697 2280int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
8057b3e7 2281 const struct switchdev_obj_port_fdb *fdb)
87820510
VD		 2282{
2283 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
87820510
VD		 2284 int ret;
2285
2286 mutex_lock(&ps->smi_mutex);
158bc065 2287 ret = _mv88e6xxx_port_fdb_load(ps, port, fdb->addr, fdb->vid,
cdf09697 2288 GLOBAL_ATU_DATA_STATE_UNUSED);
87820510
VD		 2289 mutex_unlock(&ps->smi_mutex);
2290
2291 return ret;
2292}
2293
158bc065 2294static int _mv88e6xxx_atu_getnext(struct mv88e6xxx_priv_state *ps, u16 fid,
1d194046 2295 struct mv88e6xxx_atu_entry *entry)
6630e236 2296{
1d194046
VD		 2297 struct mv88e6xxx_atu_entry next = { 0 };
2298 int ret;
2299
2300 next.fid = fid;
defb05b9 2301
158bc065 2302 ret = _mv88e6xxx_atu_wait(ps);
cdf09697
DM		 2303 if (ret < 0)
2304 return ret;
6630e236 2305
158bc065 2306 ret = _mv88e6xxx_atu_cmd(ps, fid, GLOBAL_ATU_OP_GET_NEXT_DB);
1d194046
VD		 2307 if (ret < 0)
2308 return ret;
6630e236 2309
158bc065 2310 ret = _mv88e6xxx_atu_mac_read(ps, next.mac);
1d194046
VD		 2311 if (ret < 0)
2312 return ret;
6630e236 2313
158bc065 2314 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_ATU_DATA);
cdf09697
DM		 2315 if (ret < 0)
2316 return ret;
6630e236 2317
1d194046
VD		 2318 next.state = ret & GLOBAL_ATU_DATA_STATE_MASK;
2319 if (next.state != GLOBAL_ATU_DATA_STATE_UNUSED) {
2320 unsigned int mask, shift;
2321
2322 if (ret & GLOBAL_ATU_DATA_TRUNK) {
2323 next.trunk = true;
2324 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
2325 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
2326 } else {
2327 next.trunk = false;
2328 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
2329 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
2330 }
2331
2332 next.portv_trunkid = (ret & mask) >> shift;
2333 }
cdf09697 2334
1d194046 2335 *entry = next;
cdf09697
DM		 2336 return 0;
2337}
2338
158bc065
AL		 2339static int _mv88e6xxx_port_fdb_dump_one(struct mv88e6xxx_priv_state *ps,
2340 u16 fid, u16 vid, int port,
74b6ba0d
VD		 2341 struct switchdev_obj_port_fdb *fdb,
2342 int (*cb)(struct switchdev_obj *obj))
2343{
2344 struct mv88e6xxx_atu_entry addr = {
2345 .mac = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff },
2346 };
2347 int err;
2348
158bc065 2349 err = _mv88e6xxx_atu_mac_write(ps, addr.mac);
74b6ba0d
VD		 2350 if (err)
2351 return err;
2352
2353 do {
158bc065 2354 err = _mv88e6xxx_atu_getnext(ps, fid, &addr);
74b6ba0d
VD		 2355 if (err)
2356 break;
2357
2358 if (addr.state == GLOBAL_ATU_DATA_STATE_UNUSED)
2359 break;
2360
2361 if (!addr.trunk && addr.portv_trunkid & BIT(port)) {
2362 bool is_static = addr.state ==
2363 (is_multicast_ether_addr(addr.mac) ?
2364 GLOBAL_ATU_DATA_STATE_MC_STATIC :
2365 GLOBAL_ATU_DATA_STATE_UC_STATIC);
2366
2367 fdb->vid = vid;
2368 ether_addr_copy(fdb->addr, addr.mac);
2369 fdb->ndm_state = is_static ? NUD_NOARP : NUD_REACHABLE;
2370
2371 err = cb(&fdb->obj);
2372 if (err)
2373 break;
2374 }
2375 } while (!is_broadcast_ether_addr(addr.mac));
2376
2377 return err;
2378}
2379
f33475bd
VD		 2380int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
2381 struct switchdev_obj_port_fdb *fdb,
2382 int (*cb)(struct switchdev_obj *obj))
2383{
2384 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2385 struct mv88e6xxx_vtu_stu_entry vlan = {
2386 .vid = GLOBAL_VTU_VID_MASK, /* all ones */
2387 };
2db9ce1f 2388 u16 fid;
f33475bd
VD		 2389 int err;
2390
2391 mutex_lock(&ps->smi_mutex);
2392
2db9ce1f 2393 /* Dump port's default Filtering Information Database (VLAN ID 0) */
158bc065 2394 err = _mv88e6xxx_port_fid_get(ps, port, &fid);
2db9ce1f
VD		 2395 if (err)
2396 goto unlock;
2397
158bc065 2398 err = _mv88e6xxx_port_fdb_dump_one(ps, fid, 0, port, fdb, cb);
2db9ce1f
VD		 2399 if (err)
2400 goto unlock;
2401
74b6ba0d 2402 /* Dump VLANs' Filtering Information Databases */
158bc065 2403 err = _mv88e6xxx_vtu_vid_write(ps, vlan.vid);
f33475bd
VD		 2404 if (err)
2405 goto unlock;
2406
2407 do {
158bc065 2408 err = _mv88e6xxx_vtu_getnext(ps, &vlan);
f33475bd 2409 if (err)
74b6ba0d 2410 break;
f33475bd
VD		 2411
2412 if (!vlan.valid)
2413 break;
2414
158bc065 2415 err = _mv88e6xxx_port_fdb_dump_one(ps, vlan.fid, vlan.vid, port,
74b6ba0d 2416 fdb, cb);
f33475bd 2417 if (err)
74b6ba0d 2418 break;
f33475bd
VD		 2419 } while (vlan.vid < GLOBAL_VTU_VID_MASK);
2420
2421unlock:
2422 mutex_unlock(&ps->smi_mutex);
2423
2424 return err;
2425}
2426
a6692754
VD		 2427int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
2428 struct net_device *bridge)
e79a8bcb 2429{
a6692754 2430 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1d9619d5 2431 int i, err = 0;
466dfa07
VD		 2432
2433 mutex_lock(&ps->smi_mutex);
2434
b7666efe 2435 /* Assign the bridge and remap each port's VLANTable */
a6692754 2436 ps->ports[port].bridge_dev = bridge;
b7666efe 2437
009a2b98 2438 for (i = 0; i < ps->info->num_ports; ++i) {
b7666efe 2439 if (ps->ports[i].bridge_dev == bridge) {
158bc065 2440 err = _mv88e6xxx_port_based_vlan_map(ps, i);
b7666efe
VD		 2441 if (err)
2442 break;
2443 }
2444 }
2445
466dfa07 2446 mutex_unlock(&ps->smi_mutex);
a6692754 2447
466dfa07 2448 return err;
e79a8bcb
VD		 2449}
2450
16bfa702 2451void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port)
66d9cd0f 2452{
a6692754 2453 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
b7666efe 2454 struct net_device *bridge = ps->ports[port].bridge_dev;
16bfa702 2455 int i;
466dfa07
VD		 2456
2457 mutex_lock(&ps->smi_mutex);
2458
b7666efe 2459 /* Unassign the bridge and remap each port's VLANTable */
a6692754 2460 ps->ports[port].bridge_dev = NULL;
b7666efe 2461
009a2b98 2462 for (i = 0; i < ps->info->num_ports; ++i)
16bfa702 2463 if (i == port || ps->ports[i].bridge_dev == bridge)
158bc065 2464 if (_mv88e6xxx_port_based_vlan_map(ps, i))
16bfa702 2465 netdev_warn(ds->ports[i], "failed to remap\n");
b7666efe 2466
466dfa07 2467 mutex_unlock(&ps->smi_mutex);
66d9cd0f
VD		 2468}
2469
facd95b2
GR		 2470static void mv88e6xxx_bridge_work(struct work_struct *work)
2471{
2472 struct mv88e6xxx_priv_state *ps;
2473 struct dsa_switch *ds;
2474 int port;
2475
2476 ps = container_of(work, struct mv88e6xxx_priv_state, bridge_work);
7543a6d5 2477 ds = ps->ds;
facd95b2 2478
2d9deae4
VD		 2479 mutex_lock(&ps->smi_mutex);
2480
009a2b98 2481 for (port = 0; port < ps->info->num_ports; ++port)
2d9deae4 2482 if (test_and_clear_bit(port, ps->port_state_update_mask) &&
158bc065
AL		 2483 _mv88e6xxx_port_state(ps, port, ps->ports[port].state))
2484 netdev_warn(ds->ports[port],
2485 "failed to update state to %s\n",
2d9deae4
VD		 2486 mv88e6xxx_port_state_names[ps->ports[port].state]);
2487
2488 mutex_unlock(&ps->smi_mutex);
facd95b2
GR		 2489}
2490
158bc065
AL		 2491static int _mv88e6xxx_phy_page_write(struct mv88e6xxx_priv_state *ps,
2492 int port, int page, int reg, int val)
75baacf0
PU		 2493{
2494 int ret;
2495
158bc065 2496 ret = _mv88e6xxx_phy_write_indirect(ps, port, 0x16, page);
75baacf0
PU		 2497 if (ret < 0)
2498 goto restore_page_0;
2499
158bc065 2500 ret = _mv88e6xxx_phy_write_indirect(ps, port, reg, val);
75baacf0 2501restore_page_0:
158bc065 2502 _mv88e6xxx_phy_write_indirect(ps, port, 0x16, 0x0);
75baacf0
PU		 2503
2504 return ret;
2505}
2506
158bc065
AL		 2507static int _mv88e6xxx_phy_page_read(struct mv88e6xxx_priv_state *ps,
2508 int port, int page, int reg)
75baacf0
PU		 2509{
2510 int ret;
2511
158bc065 2512 ret = _mv88e6xxx_phy_write_indirect(ps, port, 0x16, page);
75baacf0
PU		 2513 if (ret < 0)
2514 goto restore_page_0;
2515
158bc065 2516 ret = _mv88e6xxx_phy_read_indirect(ps, port, reg);
75baacf0 2517restore_page_0:
158bc065 2518 _mv88e6xxx_phy_write_indirect(ps, port, 0x16, 0x0);
75baacf0
PU		 2519
2520 return ret;
2521}
2522
158bc065 2523static int mv88e6xxx_power_on_serdes(struct mv88e6xxx_priv_state *ps)
13a7ebb3
PU		 2524{
2525 int ret;
2526
158bc065 2527 ret = _mv88e6xxx_phy_page_read(ps, REG_FIBER_SERDES, PAGE_FIBER_SERDES,
13a7ebb3
PU		 2528 MII_BMCR);
2529 if (ret < 0)
2530 return ret;
2531
2532 if (ret & BMCR_PDOWN) {
2533 ret &= ~BMCR_PDOWN;
158bc065 2534 ret = _mv88e6xxx_phy_page_write(ps, REG_FIBER_SERDES,
13a7ebb3
PU		 2535 PAGE_FIBER_SERDES, MII_BMCR,
2536 ret);
2537 }
2538
2539 return ret;
2540}
2541
dbde9e66 2542static int mv88e6xxx_setup_port(struct dsa_switch *ds, int port)
d827e88a
GR		 2543{
2544 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
f02bdffc 2545 int ret;
54d792f2 2546 u16 reg;
d827e88a
GR		 2547
2548 mutex_lock(&ps->smi_mutex);
2549
158bc065
AL		 2550 if (mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps) ||
2551 mv88e6xxx_6165_family(ps) || mv88e6xxx_6097_family(ps) ||
2552 mv88e6xxx_6185_family(ps) || mv88e6xxx_6095_family(ps) ||
2553 mv88e6xxx_6065_family(ps) || mv88e6xxx_6320_family(ps)) {
54d792f2
AL		 2554 /* MAC Forcing register: don't force link, speed,
2555 * duplex or flow control state to any particular
2556 * values on physical ports, but force the CPU port
2557 * and all DSA ports to their maximum bandwidth and
2558 * full duplex.
2559 */
158bc065 2560 reg = _mv88e6xxx_reg_read(ps, REG_PORT(port), PORT_PCS_CTRL);
60045cbf 2561 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
53adc9e8 2562 reg &= ~PORT_PCS_CTRL_UNFORCED;
54d792f2
AL		 2563 reg |= PORT_PCS_CTRL_FORCE_LINK |
2564 PORT_PCS_CTRL_LINK_UP |
2565 PORT_PCS_CTRL_DUPLEX_FULL |
2566 PORT_PCS_CTRL_FORCE_DUPLEX;
158bc065 2567 if (mv88e6xxx_6065_family(ps))
54d792f2
AL		 2568 reg |= PORT_PCS_CTRL_100;
2569 else
2570 reg |= PORT_PCS_CTRL_1000;
2571 } else {
2572 reg |= PORT_PCS_CTRL_UNFORCED;
2573 }
2574
158bc065 2575 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port),
54d792f2
AL		 2576 PORT_PCS_CTRL, reg);
2577 if (ret)
2578 goto abort;
2579 }
2580
2581 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
2582 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
2583 * tunneling, determine priority by looking at 802.1p and IP
2584 * priority fields (IP prio has precedence), and set STP state
2585 * to Forwarding.
2586 *
2587 * If this is the CPU link, use DSA or EDSA tagging depending
2588 * on which tagging mode was configured.
2589 *
2590 * If this is a link to another switch, use DSA tagging mode.
2591 *
2592 * If this is the upstream port for this switch, enable
2593 * forwarding of unknown unicasts and multicasts.
2594 */
2595 reg = 0;
158bc065
AL		 2596 if (mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps) ||
2597 mv88e6xxx_6165_family(ps) || mv88e6xxx_6097_family(ps) ||
2598 mv88e6xxx_6095_family(ps) || mv88e6xxx_6065_family(ps) ||
2599 mv88e6xxx_6185_family(ps) || mv88e6xxx_6320_family(ps))
54d792f2
AL		 2600 reg = PORT_CONTROL_IGMP_MLD_SNOOP |
2601 PORT_CONTROL_USE_TAG | PORT_CONTROL_USE_IP |
2602 PORT_CONTROL_STATE_FORWARDING;
2603 if (dsa_is_cpu_port(ds, port)) {
158bc065 2604 if (mv88e6xxx_6095_family(ps) || mv88e6xxx_6185_family(ps))
54d792f2 2605 reg |= PORT_CONTROL_DSA_TAG;
158bc065
AL		 2606 if (mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps) ||
2607 mv88e6xxx_6165_family(ps) || mv88e6xxx_6097_family(ps) ||
2608 mv88e6xxx_6320_family(ps)) {
54d792f2
AL		 2609 if (ds->dst->tag_protocol == DSA_TAG_PROTO_EDSA)
2610 reg |= PORT_CONTROL_FRAME_ETHER_TYPE_DSA;
2611 else
2612 reg |= PORT_CONTROL_FRAME_MODE_DSA;
c047a1f9
AL		 2613 reg |= PORT_CONTROL_FORWARD_UNKNOWN |
2614 PORT_CONTROL_FORWARD_UNKNOWN_MC;
54d792f2
AL		 2615 }
2616
158bc065
AL		 2617 if (mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps) ||
2618 mv88e6xxx_6165_family(ps) || mv88e6xxx_6097_family(ps) ||
2619 mv88e6xxx_6095_family(ps) || mv88e6xxx_6065_family(ps) ||
2620 mv88e6xxx_6185_family(ps) || mv88e6xxx_6320_family(ps)) {
54d792f2
AL		 2621 if (ds->dst->tag_protocol == DSA_TAG_PROTO_EDSA)
2622 reg |= PORT_CONTROL_EGRESS_ADD_TAG;
2623 }
2624 }
6083ce71 2625 if (dsa_is_dsa_port(ds, port)) {
158bc065 2626 if (mv88e6xxx_6095_family(ps) || mv88e6xxx_6185_family(ps))
6083ce71 2627 reg |= PORT_CONTROL_DSA_TAG;
158bc065
AL		 2628 if (mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps) ||
2629 mv88e6xxx_6165_family(ps) || mv88e6xxx_6097_family(ps) ||
2630 mv88e6xxx_6320_family(ps)) {
54d792f2 2631 reg |= PORT_CONTROL_FRAME_MODE_DSA;
6083ce71
AL		 2632 }
2633
54d792f2
AL		 2634 if (port == dsa_upstream_port(ds))
2635 reg |= PORT_CONTROL_FORWARD_UNKNOWN |
2636 PORT_CONTROL_FORWARD_UNKNOWN_MC;
2637 }
2638 if (reg) {
158bc065 2639 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port),
54d792f2
AL		 2640 PORT_CONTROL, reg);
2641 if (ret)
2642 goto abort;
2643 }
2644
13a7ebb3
PU		 2645 /* If this port is connected to a SerDes, make sure the SerDes is not
2646 * powered down.
2647 */
158bc065
AL		 2648 if (mv88e6xxx_6352_family(ps)) {
2649 ret = _mv88e6xxx_reg_read(ps, REG_PORT(port), PORT_STATUS);
13a7ebb3
PU		 2650 if (ret < 0)
2651 goto abort;
2652 ret &= PORT_STATUS_CMODE_MASK;
2653 if ((ret == PORT_STATUS_CMODE_100BASE_X) ||
2654 (ret == PORT_STATUS_CMODE_1000BASE_X) ||
2655 (ret == PORT_STATUS_CMODE_SGMII)) {
158bc065 2656 ret = mv88e6xxx_power_on_serdes(ps);
13a7ebb3
PU		 2657 if (ret < 0)
2658 goto abort;
2659 }
2660 }
2661
8efdda4a 2662 /* Port Control 2: don't force a good FCS, set the maximum frame size to
46fbe5e5 2663 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
8efdda4a
VD		 2664 * untagged frames on this port, do a destination address lookup on all
2665 * received packets as usual, disable ARP mirroring and don't send a
2666 * copy of all transmitted/received frames on this port to the CPU.
54d792f2
AL		 2667 */
2668 reg = 0;
158bc065
AL		 2669 if (mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps) ||
2670 mv88e6xxx_6165_family(ps) || mv88e6xxx_6097_family(ps) ||
2671 mv88e6xxx_6095_family(ps) || mv88e6xxx_6320_family(ps) ||
2672 mv88e6xxx_6185_family(ps))
54d792f2
AL		 2673 reg = PORT_CONTROL_2_MAP_DA;
2674
158bc065
AL		 2675 if (mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps) ||
2676 mv88e6xxx_6165_family(ps) || mv88e6xxx_6320_family(ps))
54d792f2
AL		 2677 reg |= PORT_CONTROL_2_JUMBO_10240;
2678
158bc065 2679 if (mv88e6xxx_6095_family(ps) || mv88e6xxx_6185_family(ps)) {
54d792f2
AL		 2680 /* Set the upstream port this port should use */
2681 reg |= dsa_upstream_port(ds);
2682 /* enable forwarding of unknown multicast addresses to
2683 * the upstream port
2684 */
2685 if (port == dsa_upstream_port(ds))
2686 reg |= PORT_CONTROL_2_FORWARD_UNKNOWN;
2687 }
2688
46fbe5e5 2689 reg |= PORT_CONTROL_2_8021Q_DISABLED;
8efdda4a 2690
54d792f2 2691 if (reg) {
158bc065 2692 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port),
54d792f2
AL		 2693 PORT_CONTROL_2, reg);
2694 if (ret)
2695 goto abort;
2696 }
2697
2698 /* Port Association Vector: when learning source addresses
2699 * of packets, add the address to the address database using
2700 * a port bitmap that has only the bit for this port set and
2701 * the other bits clear.
2702 */
4c7ea3c0 2703 reg = 1 << port;
996ecb82
VD		 2704 /* Disable learning for CPU port */
2705 if (dsa_is_cpu_port(ds, port))
65fa4027 2706 reg = 0;
4c7ea3c0 2707
158bc065 2708 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), PORT_ASSOC_VECTOR, reg);
54d792f2
AL		 2709 if (ret)
2710 goto abort;
2711
2712 /* Egress rate control 2: disable egress rate control. */
158bc065 2713 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), PORT_RATE_CONTROL_2,
54d792f2
AL		 2714 0x0000);
2715 if (ret)
2716 goto abort;
2717
158bc065
AL		 2718 if (mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps) ||
2719 mv88e6xxx_6165_family(ps) || mv88e6xxx_6097_family(ps) ||
2720 mv88e6xxx_6320_family(ps)) {
54d792f2
AL		 2721 /* Do not limit the period of time that this port can
2722 * be paused for by the remote end or the period of
2723 * time that this port can pause the remote end.
2724 */
158bc065 2725 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port),
54d792f2
AL		 2726 PORT_PAUSE_CTRL, 0x0000);
2727 if (ret)
2728 goto abort;
2729
2730 /* Port ATU control: disable limiting the number of
2731 * address database entries that this port is allowed
2732 * to use.
2733 */
158bc065 2734 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port),
54d792f2
AL		 2735 PORT_ATU_CONTROL, 0x0000);
2736 /* Priority Override: disable DA, SA and VTU priority
2737 * override.
2738 */
158bc065 2739 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port),
54d792f2
AL		 2740 PORT_PRI_OVERRIDE, 0x0000);
2741 if (ret)
2742 goto abort;
2743
2744 /* Port Ethertype: use the Ethertype DSA Ethertype
2745 * value.
2746 */
158bc065 2747 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port),
54d792f2
AL		 2748 PORT_ETH_TYPE, ETH_P_EDSA);
2749 if (ret)
2750 goto abort;
2751 /* Tag Remap: use an identity 802.1p prio -> switch
2752 * prio mapping.
2753 */
158bc065 2754 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port),
54d792f2
AL		 2755 PORT_TAG_REGMAP_0123, 0x3210);
2756 if (ret)
2757 goto abort;
2758
2759 /* Tag Remap 2: use an identity 802.1p prio -> switch
2760 * prio mapping.
2761 */
158bc065 2762 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port),
54d792f2
AL		 2763 PORT_TAG_REGMAP_4567, 0x7654);
2764 if (ret)
2765 goto abort;
2766 }
2767
158bc065
AL		 2768 if (mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps) ||
2769 mv88e6xxx_6165_family(ps) || mv88e6xxx_6097_family(ps) ||
2770 mv88e6xxx_6185_family(ps) || mv88e6xxx_6095_family(ps) ||
2771 mv88e6xxx_6320_family(ps)) {
54d792f2 2772 /* Rate Control: disable ingress rate limiting. */
158bc065 2773 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port),
54d792f2
AL		 2774 PORT_RATE_CONTROL, 0x0001);
2775 if (ret)
2776 goto abort;
2777 }
2778
366f0a0f
GR		 2779 /* Port Control 1: disable trunking, disable sending
2780 * learning messages to this port.
d827e88a 2781 */
158bc065 2782 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), PORT_CONTROL_1, 0x0000);
d827e88a
GR		 2783 if (ret)
2784 goto abort;
2785
207afda1 2786 /* Port based VLAN map: give each port the same default address
b7666efe
VD		 2787 * database, and allow bidirectional communication between the
2788 * CPU and DSA port(s), and the other ports.
d827e88a 2789 */
158bc065 2790 ret = _mv88e6xxx_port_fid_set(ps, port, 0);
2db9ce1f
VD		 2791 if (ret)
2792 goto abort;
2793
158bc065 2794 ret = _mv88e6xxx_port_based_vlan_map(ps, port);
d827e88a
GR		 2795 if (ret)
2796 goto abort;
2797
2798 /* Default VLAN ID and priority: don't set a default VLAN
2799 * ID, and set the default packet priority to zero.
2800 */
158bc065 2801 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), PORT_DEFAULT_VLAN,
47cf1e65 2802 0x0000);
d827e88a
GR		 2803abort:
2804 mutex_unlock(&ps->smi_mutex);
2805 return ret;
2806}
2807
dbde9e66
AL		 2808int mv88e6xxx_setup_ports(struct dsa_switch *ds)
2809{
2810 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2811 int ret;
2812 int i;
2813
009a2b98 2814 for (i = 0; i < ps->info->num_ports; i++) {
dbde9e66
AL		 2815 ret = mv88e6xxx_setup_port(ds, i);
2816 if (ret < 0)
2817 return ret;
2818 }
2819 return 0;
2820}
2821
158bc065 2822int mv88e6xxx_setup_common(struct mv88e6xxx_priv_state *ps)
acdaffcc 2823{
acdaffcc 2824 mutex_init(&ps->smi_mutex);
acdaffcc 2825
facd95b2
GR		 2826 INIT_WORK(&ps->bridge_work, mv88e6xxx_bridge_work);
2827
d24645be
VD		 2828 if (mv88e6xxx_has(ps, MV88E6XXX_FLAG_EEPROM))
2829 mutex_init(&ps->eeprom_mutex);
2830
8c9983a2
VD		 2831 if (mv88e6xxx_has(ps, MV88E6XXX_FLAG_PPU))
2832 mv88e6xxx_ppu_state_init(ps);
2833
acdaffcc
GR		 2834 return 0;
2835}
2836
54d792f2
AL		 2837int mv88e6xxx_setup_global(struct dsa_switch *ds)
2838{
2839 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
48ace4ef 2840 int err;
54d792f2
AL		 2841 int i;
2842
48ace4ef 2843 mutex_lock(&ps->smi_mutex);
54d792f2
AL		 2844 /* Set the default address aging time to 5 minutes, and
2845 * enable address learn messages to be sent to all message
2846 * ports.
2847 */
158bc065 2848 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_ATU_CONTROL,
48ace4ef
AL		 2849 0x0140 | GLOBAL_ATU_CONTROL_LEARN2ALL);
2850 if (err)
2851 goto unlock;
54d792f2
AL		 2852
2853 /* Configure the IP ToS mapping registers. */
158bc065 2854 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_IP_PRI_0, 0x0000);
48ace4ef
AL		 2855 if (err)
2856 goto unlock;
158bc065 2857 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_IP_PRI_1, 0x0000);
48ace4ef
AL		 2858 if (err)
2859 goto unlock;
158bc065 2860 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_IP_PRI_2, 0x5555);
48ace4ef
AL		 2861 if (err)
2862 goto unlock;
158bc065 2863 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_IP_PRI_3, 0x5555);
48ace4ef
AL		 2864 if (err)
2865 goto unlock;
158bc065 2866 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_IP_PRI_4, 0xaaaa);
48ace4ef
AL		 2867 if (err)
2868 goto unlock;
158bc065 2869 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_IP_PRI_5, 0xaaaa);
48ace4ef
AL		 2870 if (err)
2871 goto unlock;
158bc065 2872 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_IP_PRI_6, 0xffff);
48ace4ef
AL		 2873 if (err)
2874 goto unlock;
158bc065 2875 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_IP_PRI_7, 0xffff);
48ace4ef
AL		 2876 if (err)
2877 goto unlock;
54d792f2
AL		 2878
2879 /* Configure the IEEE 802.1p priority mapping register. */
158bc065 2880 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_IEEE_PRI, 0xfa41);
48ace4ef
AL		 2881 if (err)
2882 goto unlock;
54d792f2
AL		 2883
2884 /* Send all frames with destination addresses matching
2885 * 01:80:c2:00:00:0x to the CPU port.
2886 */
158bc065 2887 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL2, GLOBAL2_MGMT_EN_0X, 0xffff);
48ace4ef
AL		 2888 if (err)
2889 goto unlock;
54d792f2
AL		 2890
2891 /* Ignore removed tag data on doubly tagged packets, disable
2892 * flow control messages, force flow control priority to the
2893 * highest, and send all special multicast frames to the CPU
2894 * port at the highest priority.
2895 */
158bc065 2896 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL2, GLOBAL2_SWITCH_MGMT,
48ace4ef
AL		 2897 0x7 | GLOBAL2_SWITCH_MGMT_RSVD2CPU | 0x70 |
2898 GLOBAL2_SWITCH_MGMT_FORCE_FLOW_CTRL_PRI);
2899 if (err)
2900 goto unlock;
54d792f2
AL		 2901
2902 /* Program the DSA routing table. */
2903 for (i = 0; i < 32; i++) {
2904 int nexthop = 0x1f;
2905
2906 if (ds->pd->rtable &&
2907 i != ds->index && i < ds->dst->pd->nr_chips)
2908 nexthop = ds->pd->rtable[i] & 0x1f;
2909
48ace4ef 2910 err = _mv88e6xxx_reg_write(
158bc065 2911 ps, REG_GLOBAL2,
48ace4ef
AL		 2912 GLOBAL2_DEVICE_MAPPING,
2913 GLOBAL2_DEVICE_MAPPING_UPDATE |
2914 (i << GLOBAL2_DEVICE_MAPPING_TARGET_SHIFT) | nexthop);
2915 if (err)
2916 goto unlock;
54d792f2
AL		 2917 }
2918
2919 /* Clear all trunk masks. */
48ace4ef 2920 for (i = 0; i < 8; i++) {
158bc065 2921 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL2, GLOBAL2_TRUNK_MASK,
48ace4ef
AL		 2922 0x8000 |
2923 (i << GLOBAL2_TRUNK_MASK_NUM_SHIFT) |
009a2b98 2924 ((1 << ps->info->num_ports) - 1));
48ace4ef
AL		 2925 if (err)
2926 goto unlock;
2927 }
54d792f2
AL		 2928
2929 /* Clear all trunk mappings. */
48ace4ef
AL		 2930 for (i = 0; i < 16; i++) {
2931 err = _mv88e6xxx_reg_write(
158bc065 2932 ps, REG_GLOBAL2,
48ace4ef
AL		 2933 GLOBAL2_TRUNK_MAPPING,
2934 GLOBAL2_TRUNK_MAPPING_UPDATE |
2935 (i << GLOBAL2_TRUNK_MAPPING_ID_SHIFT));
2936 if (err)
2937 goto unlock;
2938 }
54d792f2 2939
158bc065
AL		 2940 if (mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps) ||
2941 mv88e6xxx_6165_family(ps) || mv88e6xxx_6097_family(ps) ||
2942 mv88e6xxx_6320_family(ps)) {
54d792f2
AL		 2943 /* Send all frames with destination addresses matching
2944 * 01:80:c2:00:00:2x to the CPU port.
2945 */
158bc065 2946 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL2,
48ace4ef
AL		 2947 GLOBAL2_MGMT_EN_2X, 0xffff);
2948 if (err)
2949 goto unlock;
54d792f2
AL		 2950
2951 /* Initialise cross-chip port VLAN table to reset
2952 * defaults.
2953 */
158bc065 2954 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL2,
48ace4ef
AL		 2955 GLOBAL2_PVT_ADDR, 0x9000);
2956 if (err)
2957 goto unlock;
54d792f2
AL		 2958
2959 /* Clear the priority override table. */
48ace4ef 2960 for (i = 0; i < 16; i++) {
158bc065 2961 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL2,
48ace4ef
AL		 2962 GLOBAL2_PRIO_OVERRIDE,
2963 0x8000 | (i << 8));
2964 if (err)
2965 goto unlock;
2966 }
54d792f2
AL		 2967 }
2968
158bc065
AL		 2969 if (mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps) ||
2970 mv88e6xxx_6165_family(ps) || mv88e6xxx_6097_family(ps) ||
2971 mv88e6xxx_6185_family(ps) || mv88e6xxx_6095_family(ps) ||
2972 mv88e6xxx_6320_family(ps)) {
54d792f2
AL		 2973 /* Disable ingress rate limiting by resetting all
2974 * ingress rate limit registers to their initial
2975 * state.
2976 */
009a2b98 2977 for (i = 0; i < ps->info->num_ports; i++) {
158bc065 2978 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL2,
48ace4ef
AL		 2979 GLOBAL2_INGRESS_OP,
2980 0x9000 | (i << 8));
2981 if (err)
2982 goto unlock;
2983 }
54d792f2
AL		 2984 }
2985
db687a56 2986 /* Clear the statistics counters for all ports */
158bc065 2987 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_STATS_OP,
48ace4ef
AL		 2988 GLOBAL_STATS_OP_FLUSH_ALL);
2989 if (err)
2990 goto unlock;
db687a56
AL		 2991
2992 /* Wait for the flush to complete. */
158bc065 2993 err = _mv88e6xxx_stats_wait(ps);
48ace4ef 2994 if (err < 0)
6b17e864
VD		 2995 goto unlock;
2996
c161d0a5 2997 /* Clear all ATU entries */
158bc065 2998 err = _mv88e6xxx_atu_flush(ps, 0, true);
48ace4ef 2999 if (err < 0)
c161d0a5
VD		 3000 goto unlock;
3001
6b17e864 3002 /* Clear all the VTU and STU entries */
158bc065 3003 err = _mv88e6xxx_vtu_stu_flush(ps);
6b17e864 3004unlock:
24751e29 3005 mutex_unlock(&ps->smi_mutex);
db687a56 3006
48ace4ef 3007 return err;
54d792f2
AL		 3008}
3009
158bc065 3010int mv88e6xxx_switch_reset(struct mv88e6xxx_priv_state *ps, bool ppu_active)
143a8307 3011{
143a8307 3012 u16 is_reset = (ppu_active ? 0x8800 : 0xc800);
158bc065 3013 struct gpio_desc *gpiod = ps->ds->pd->reset;
143a8307
AL		 3014 unsigned long timeout;
3015 int ret;
3016 int i;
3017
48ace4ef
AL		 3018 mutex_lock(&ps->smi_mutex);
3019
143a8307 3020 /* Set all ports to the disabled state. */
009a2b98 3021 for (i = 0; i < ps->info->num_ports; i++) {
158bc065 3022 ret = _mv88e6xxx_reg_read(ps, REG_PORT(i), PORT_CONTROL);
48ace4ef
AL		 3023 if (ret < 0)
3024 goto unlock;
3025
158bc065 3026 ret = _mv88e6xxx_reg_write(ps, REG_PORT(i), PORT_CONTROL,
48ace4ef
AL		 3027 ret & 0xfffc);
3028 if (ret)
3029 goto unlock;
143a8307
AL		 3030 }
3031
3032 /* Wait for transmit queues to drain. */
3033 usleep_range(2000, 4000);
3034
c8c1b39a
AL		 3035 /* If there is a gpio connected to the reset pin, toggle it */
3036 if (gpiod) {
3037 gpiod_set_value_cansleep(gpiod, 1);
3038 usleep_range(10000, 20000);
3039 gpiod_set_value_cansleep(gpiod, 0);
3040 usleep_range(10000, 20000);
3041 }
3042
143a8307
AL		 3043 /* Reset the switch. Keep the PPU active if requested. The PPU
3044 * needs to be active to support indirect phy register access
3045 * through global registers 0x18 and 0x19.
3046 */
3047 if (ppu_active)
158bc065 3048 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, 0x04, 0xc000);
143a8307 3049 else
158bc065 3050 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, 0x04, 0xc400);
48ace4ef
AL		 3051 if (ret)
3052 goto unlock;
143a8307
AL		 3053
3054 /* Wait up to one second for reset to complete. */
3055 timeout = jiffies + 1 * HZ;
3056 while (time_before(jiffies, timeout)) {
158bc065 3057 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, 0x00);
48ace4ef
AL		 3058 if (ret < 0)
3059 goto unlock;
3060
143a8307
AL		 3061 if ((ret & is_reset) == is_reset)
3062 break;
3063 usleep_range(1000, 2000);
3064 }
3065 if (time_after(jiffies, timeout))
48ace4ef
AL		 3066 ret = -ETIMEDOUT;
3067 else
3068 ret = 0;
3069unlock:
3070 mutex_unlock(&ps->smi_mutex);
143a8307 3071
48ace4ef 3072 return ret;
143a8307
AL		 3073}
3074
49143585
AL		 3075int mv88e6xxx_phy_page_read(struct dsa_switch *ds, int port, int page, int reg)
3076{
3077 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
3078 int ret;
3079
3898c148 3080 mutex_lock(&ps->smi_mutex);
158bc065 3081 ret = _mv88e6xxx_phy_page_read(ps, port, page, reg);
3898c148 3082 mutex_unlock(&ps->smi_mutex);
75baacf0 3083
49143585
AL		 3084 return ret;
3085}
3086
3087int mv88e6xxx_phy_page_write(struct dsa_switch *ds, int port, int page,
3088 int reg, int val)
3089{
3090 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
3091 int ret;
3092
3898c148 3093 mutex_lock(&ps->smi_mutex);
158bc065 3094 ret = _mv88e6xxx_phy_page_write(ps, port, page, reg, val);
3898c148 3095 mutex_unlock(&ps->smi_mutex);
75baacf0 3096
fd3a0ee4
AL		 3097 return ret;
3098}
3099
158bc065
AL		 3100static int mv88e6xxx_port_to_phy_addr(struct mv88e6xxx_priv_state *ps,
3101 int port)
fd3a0ee4 3102{
009a2b98 3103 if (port >= 0 && port < ps->info->num_ports)
fd3a0ee4
AL		 3104 return port;
3105 return -EINVAL;
3106}
3107
3108int
3109mv88e6xxx_phy_read(struct dsa_switch *ds, int port, int regnum)
3110{
3111 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
158bc065 3112 int addr = mv88e6xxx_port_to_phy_addr(ps, port);
fd3a0ee4
AL		 3113 int ret;
3114
3115 if (addr < 0)
158bc065 3116 return 0xffff;
fd3a0ee4 3117
3898c148 3118 mutex_lock(&ps->smi_mutex);
8c9983a2
VD		 3119
3120 if (mv88e6xxx_has(ps, MV88E6XXX_FLAG_PPU))
3121 ret = mv88e6xxx_phy_read_ppu(ps, addr, regnum);
6d5834a1
VD		 3122 else if (mv88e6xxx_has(ps, MV88E6XXX_FLAG_SMI_PHY))
3123 ret = _mv88e6xxx_phy_read_indirect(ps, addr, regnum);
8c9983a2
VD		 3124 else
3125 ret = _mv88e6xxx_phy_read(ps, addr, regnum);
3126
3898c148 3127 mutex_unlock(&ps->smi_mutex);
fd3a0ee4
AL		 3128 return ret;
3129}
3130
3131int
3132mv88e6xxx_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val)
3133{
3134 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
158bc065 3135 int addr = mv88e6xxx_port_to_phy_addr(ps, port);
fd3a0ee4
AL		 3136 int ret;
3137
3138 if (addr < 0)
158bc065 3139 return 0xffff;
fd3a0ee4 3140
3898c148 3141 mutex_lock(&ps->smi_mutex);
8c9983a2
VD		 3142
3143 if (mv88e6xxx_has(ps, MV88E6XXX_FLAG_PPU))
3144 ret = mv88e6xxx_phy_write_ppu(ps, addr, regnum, val);
6d5834a1
VD		 3145 else if (mv88e6xxx_has(ps, MV88E6XXX_FLAG_SMI_PHY))
3146 ret = _mv88e6xxx_phy_write_indirect(ps, addr, regnum, val);
8c9983a2
VD		 3147 else
3148 ret = _mv88e6xxx_phy_write(ps, addr, regnum, val);
3149
3898c148 3150 mutex_unlock(&ps->smi_mutex);
fd3a0ee4
AL		 3151 return ret;
3152}
3153
c22995c5
GR		 3154#ifdef CONFIG_NET_DSA_HWMON
3155
3156static int mv88e61xx_get_temp(struct dsa_switch *ds, int *temp)
3157{
3158 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
3159 int ret;
3160 int val;
3161
3162 *temp = 0;
3163
3164 mutex_lock(&ps->smi_mutex);
3165
158bc065 3166 ret = _mv88e6xxx_phy_write(ps, 0x0, 0x16, 0x6);
c22995c5
GR		 3167 if (ret < 0)
3168 goto error;
3169
3170 /* Enable temperature sensor */
158bc065 3171 ret = _mv88e6xxx_phy_read(ps, 0x0, 0x1a);
c22995c5
GR		 3172 if (ret < 0)
3173 goto error;
3174
158bc065 3175 ret = _mv88e6xxx_phy_write(ps, 0x0, 0x1a, ret | (1 << 5));
c22995c5
GR		 3176 if (ret < 0)
3177 goto error;
3178
3179 /* Wait for temperature to stabilize */
3180 usleep_range(10000, 12000);
3181
158bc065 3182 val = _mv88e6xxx_phy_read(ps, 0x0, 0x1a);
c22995c5
GR		 3183 if (val < 0) {
3184 ret = val;
3185 goto error;
3186 }
3187
3188 /* Disable temperature sensor */
158bc065 3189 ret = _mv88e6xxx_phy_write(ps, 0x0, 0x1a, ret & ~(1 << 5));
c22995c5
GR		 3190 if (ret < 0)
3191 goto error;
3192
3193 *temp = ((val & 0x1f) - 5) * 5;
3194
3195error:
158bc065 3196 _mv88e6xxx_phy_write(ps, 0x0, 0x16, 0x0);
c22995c5
GR		 3197 mutex_unlock(&ps->smi_mutex);
3198 return ret;
3199}
3200
3201static int mv88e63xx_get_temp(struct dsa_switch *ds, int *temp)
3202{
158bc065
AL		 3203 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
3204 int phy = mv88e6xxx_6320_family(ps) ? 3 : 0;
c22995c5
GR		 3205 int ret;
3206
3207 *temp = 0;
3208
3209 ret = mv88e6xxx_phy_page_read(ds, phy, 6, 27);
3210 if (ret < 0)
3211 return ret;
3212
3213 *temp = (ret & 0xff) - 25;
3214
3215 return 0;
3216}
3217
3218int mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp)
3219{
158bc065
AL		 3220 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
3221
6594f615
VD		 3222 if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_TEMP))
3223 return -EOPNOTSUPP;
3224
158bc065 3225 if (mv88e6xxx_6320_family(ps) || mv88e6xxx_6352_family(ps))
c22995c5
GR		 3226 return mv88e63xx_get_temp(ds, temp);
3227
3228 return mv88e61xx_get_temp(ds, temp);
3229}
3230
3231int mv88e6xxx_get_temp_limit(struct dsa_switch *ds, int *temp)
3232{
158bc065
AL		 3233 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
3234 int phy = mv88e6xxx_6320_family(ps) ? 3 : 0;
c22995c5
GR		 3235 int ret;
3236
6594f615 3237 if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_TEMP_LIMIT))
c22995c5
GR		 3238 return -EOPNOTSUPP;
3239
3240 *temp = 0;
3241
3242 ret = mv88e6xxx_phy_page_read(ds, phy, 6, 26);
3243 if (ret < 0)
3244 return ret;
3245
3246 *temp = (((ret >> 8) & 0x1f) * 5) - 25;
3247
3248 return 0;
3249}
3250
3251int mv88e6xxx_set_temp_limit(struct dsa_switch *ds, int temp)
3252{
158bc065
AL		 3253 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
3254 int phy = mv88e6xxx_6320_family(ps) ? 3 : 0;
c22995c5
GR		 3255 int ret;
3256
6594f615 3257 if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_TEMP_LIMIT))
c22995c5
GR		 3258 return -EOPNOTSUPP;
3259
3260 ret = mv88e6xxx_phy_page_read(ds, phy, 6, 26);
3261 if (ret < 0)
3262 return ret;
3263 temp = clamp_val(DIV_ROUND_CLOSEST(temp, 5) + 5, 0, 0x1f);
3264 return mv88e6xxx_phy_page_write(ds, phy, 6, 26,
3265 (ret & 0xe0ff) | (temp << 8));
3266}
3267
3268int mv88e6xxx_get_temp_alarm(struct dsa_switch *ds, bool *alarm)
3269{
158bc065
AL		 3270 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
3271 int phy = mv88e6xxx_6320_family(ps) ? 3 : 0;
c22995c5
GR		 3272 int ret;
3273
6594f615 3274 if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_TEMP_LIMIT))
c22995c5
GR		 3275 return -EOPNOTSUPP;
3276
3277 *alarm = false;
3278
3279 ret = mv88e6xxx_phy_page_read(ds, phy, 6, 26);
3280 if (ret < 0)
3281 return ret;
3282
3283 *alarm = !!(ret & 0x40);
3284
3285 return 0;
3286}
3287#endif /* CONFIG_NET_DSA_HWMON */
3288
f6271e67
VD		 3289static const struct mv88e6xxx_info *
3290mv88e6xxx_lookup_info(unsigned int prod_num, const struct mv88e6xxx_info *table,
0209d144 3291 unsigned int num)
b9b37713 3292{
a439c061 3293 int i;
b9b37713 3294
b9b37713 3295 for (i = 0; i < num; ++i)
f6271e67
VD		 3296 if (table[i].prod_num == prod_num)
3297 return &table[i];
b9b37713 3298
b9b37713
VD		 3299 return NULL;
3300}
3301
0209d144
VD		 3302const char *mv88e6xxx_drv_probe(struct device *dsa_dev, struct device *host_dev,
3303 int sw_addr, void **priv,
f6271e67 3304 const struct mv88e6xxx_info *table,
0209d144 3305 unsigned int num)
a77d43f1 3306{
f6271e67 3307 const struct mv88e6xxx_info *info;
a77d43f1 3308 struct mv88e6xxx_priv_state *ps;
a439c061 3309 struct mii_bus *bus;
0209d144 3310 const char *name;
a439c061 3311 int id, prod_num, rev;
a77d43f1 3312
a439c061 3313 bus = dsa_host_dev_to_mii_bus(host_dev);
c156913b
AL		 3314 if (!bus)
3315 return NULL;
3316
a439c061
VD		 3317 id = __mv88e6xxx_reg_read(bus, sw_addr, REG_PORT(0), PORT_SWITCH_ID);
3318 if (id < 0)
3319 return NULL;
3320
3321 prod_num = (id & 0xfff0) >> 4;
3322 rev = id & 0x000f;
3323
f6271e67
VD		 3324 info = mv88e6xxx_lookup_info(prod_num, table, num);
3325 if (!info)
a439c061
VD		 3326 return NULL;
3327
f6271e67
VD		 3328 name = info->name;
3329
a439c061
VD		 3330 ps = devm_kzalloc(dsa_dev, sizeof(*ps), GFP_KERNEL);
3331 if (!ps)
3332 return NULL;
3333
3334 ps->bus = bus;
3335 ps->sw_addr = sw_addr;
f6271e67 3336 ps->info = info;
a439c061
VD		 3337
3338 *priv = ps;
3339
3340 dev_info(&ps->bus->dev, "switch 0x%x probed: %s, revision %u\n",
3341 prod_num, name, rev);
3342
a77d43f1
AL		 3343 return name;
3344}
3345
98e67308
BH		 3346static int __init mv88e6xxx_init(void)
3347{
3348#if IS_ENABLED(CONFIG_NET_DSA_MV88E6131)
3349 register_switch_driver(&mv88e6131_switch_driver);
3350#endif
ca3dfa51
AL		 3351#if IS_ENABLED(CONFIG_NET_DSA_MV88E6123)
3352 register_switch_driver(&mv88e6123_switch_driver);
42f27253 3353#endif
3ad50cca
GR		 3354#if IS_ENABLED(CONFIG_NET_DSA_MV88E6352)
3355 register_switch_driver(&mv88e6352_switch_driver);
3356#endif
42f27253
AL		 3357#if IS_ENABLED(CONFIG_NET_DSA_MV88E6171)
3358 register_switch_driver(&mv88e6171_switch_driver);
98e67308
BH		 3359#endif
3360 return 0;
3361}
3362module_init(mv88e6xxx_init);
3363
3364static void __exit mv88e6xxx_cleanup(void)
3365{
42f27253
AL		 3366#if IS_ENABLED(CONFIG_NET_DSA_MV88E6171)
3367 unregister_switch_driver(&mv88e6171_switch_driver);
3368#endif
4212b543
VD		 3369#if IS_ENABLED(CONFIG_NET_DSA_MV88E6352)
3370 unregister_switch_driver(&mv88e6352_switch_driver);
3371#endif
ca3dfa51
AL		 3372#if IS_ENABLED(CONFIG_NET_DSA_MV88E6123)
3373 unregister_switch_driver(&mv88e6123_switch_driver);
98e67308
BH		 3374#endif
3375#if IS_ENABLED(CONFIG_NET_DSA_MV88E6131)
3376 unregister_switch_driver(&mv88e6131_switch_driver);
3377#endif
3378}
3379module_exit(mv88e6xxx_cleanup);
3d825ede
BH		 3380
3381MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
3382MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
3383MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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