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Merge branch 'sh_eth-fixes'
[deliverable/linux.git] / drivers / net / dsa / mv88e6xxx.c
CommitLineData
91da11f8
LB		 1/*
2 * net/dsa/mv88e6xxx.c - Marvell 88e6xxx switch chip support
3 * Copyright (c) 2008 Marvell Semiconductor
4 *
b8fee957
VD		 5 * Copyright (c) 2015 CMC Electronics, Inc.
6 * Added support for VLAN Table Unit operations
7 *
91da11f8
LB		 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
19b2f97e 14#include <linux/delay.h>
defb05b9 15#include <linux/etherdevice.h>
dea87024 16#include <linux/ethtool.h>
facd95b2 17#include <linux/if_bridge.h>
19b2f97e 18#include <linux/jiffies.h>
91da11f8 19#include <linux/list.h>
2bbba277 20#include <linux/module.h>
91da11f8 21#include <linux/netdevice.h>
c8c1b39a 22#include <linux/gpio/consumer.h>
91da11f8 23#include <linux/phy.h>
c8f0b869 24#include <net/dsa.h>
1f36faf2 25#include <net/switchdev.h>
91da11f8
LB		 26#include "mv88e6xxx.h"
27
3996a4ff
VD		 28static void assert_smi_lock(struct dsa_switch *ds)
29{
30 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
31
32 if (unlikely(!mutex_is_locked(&ps->smi_mutex))) {
33 dev_err(ds->master_dev, "SMI lock not held!\n");
34 dump_stack();
35 }
36}
37
3675c8d7 38/* If the switch's ADDR[4:0] strap pins are strapped to zero, it will
91da11f8
LB		 39 * use all 32 SMI bus addresses on its SMI bus, and all switch registers
40 * will be directly accessible on some {device address,register address}
41 * pair. If the ADDR[4:0] pins are not strapped to zero, the switch
42 * will only respond to SMI transactions to that specific address, and
43 * an indirect addressing mechanism needs to be used to access its
44 * registers.
45 */
46static int mv88e6xxx_reg_wait_ready(struct mii_bus *bus, int sw_addr)
47{
48 int ret;
49 int i;
50
51 for (i = 0; i < 16; i++) {
6e899e6c 52 ret = mdiobus_read_nested(bus, sw_addr, SMI_CMD);
91da11f8
LB		 53 if (ret < 0)
54 return ret;
55
cca8b133 56 if ((ret & SMI_CMD_BUSY) == 0)
91da11f8
LB		 57 return 0;
58 }
59
60 return -ETIMEDOUT;
61}
62
b9b37713
VD		 63static int __mv88e6xxx_reg_read(struct mii_bus *bus, int sw_addr, int addr,
64 int reg)
91da11f8
LB		 65{
66 int ret;
67
68 if (sw_addr == 0)
6e899e6c 69 return mdiobus_read_nested(bus, addr, reg);
91da11f8 70
3675c8d7 71 /* Wait for the bus to become free. */
91da11f8
LB		 72 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
73 if (ret < 0)
74 return ret;
75
3675c8d7 76 /* Transmit the read command. */
6e899e6c
NA		 77 ret = mdiobus_write_nested(bus, sw_addr, SMI_CMD,
78 SMI_CMD_OP_22_READ | (addr << 5) | reg);
91da11f8
LB		 79 if (ret < 0)
80 return ret;
81
3675c8d7 82 /* Wait for the read command to complete. */
91da11f8
LB		 83 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
84 if (ret < 0)
85 return ret;
86
3675c8d7 87 /* Read the data. */
6e899e6c 88 ret = mdiobus_read_nested(bus, sw_addr, SMI_DATA);
91da11f8
LB		 89 if (ret < 0)
90 return ret;
91
92 return ret & 0xffff;
93}
94
8d6d09e7 95static int _mv88e6xxx_reg_read(struct dsa_switch *ds, int addr, int reg)
91da11f8 96{
b184e497 97 struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);
91da11f8
LB		 98 int ret;
99
3996a4ff
VD		 100 assert_smi_lock(ds);
101
b184e497
GR		 102 if (bus == NULL)
103 return -EINVAL;
104
b184e497 105 ret = __mv88e6xxx_reg_read(bus, ds->pd->sw_addr, addr, reg);
bb92ea5e
VD		 106 if (ret < 0)
107 return ret;
108
109 dev_dbg(ds->master_dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
110 addr, reg, ret);
111
91da11f8
LB		 112 return ret;
113}
114
8d6d09e7
GR		 115int mv88e6xxx_reg_read(struct dsa_switch *ds, int addr, int reg)
116{
117 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
118 int ret;
119
120 mutex_lock(&ps->smi_mutex);
121 ret = _mv88e6xxx_reg_read(ds, addr, reg);
122 mutex_unlock(&ps->smi_mutex);
123
124 return ret;
125}
126
b9b37713
VD		 127static int __mv88e6xxx_reg_write(struct mii_bus *bus, int sw_addr, int addr,
128 int reg, u16 val)
91da11f8
LB		 129{
130 int ret;
131
132 if (sw_addr == 0)
6e899e6c 133 return mdiobus_write_nested(bus, addr, reg, val);
91da11f8 134
3675c8d7 135 /* Wait for the bus to become free. */
91da11f8
LB		 136 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
137 if (ret < 0)
138 return ret;
139
3675c8d7 140 /* Transmit the data to write. */
6e899e6c 141 ret = mdiobus_write_nested(bus, sw_addr, SMI_DATA, val);
91da11f8
LB		 142 if (ret < 0)
143 return ret;
144
3675c8d7 145 /* Transmit the write command. */
6e899e6c
NA		 146 ret = mdiobus_write_nested(bus, sw_addr, SMI_CMD,
147 SMI_CMD_OP_22_WRITE | (addr << 5) | reg);
91da11f8
LB		 148 if (ret < 0)
149 return ret;
150
3675c8d7 151 /* Wait for the write command to complete. */
91da11f8
LB		 152 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
153 if (ret < 0)
154 return ret;
155
156 return 0;
157}
158
8d6d09e7
GR		 159static int _mv88e6xxx_reg_write(struct dsa_switch *ds, int addr, int reg,
160 u16 val)
91da11f8 161{
b184e497 162 struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);
91da11f8 163
3996a4ff
VD		 164 assert_smi_lock(ds);
165
b184e497
GR		 166 if (bus == NULL)
167 return -EINVAL;
168
bb92ea5e
VD		 169 dev_dbg(ds->master_dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
170 addr, reg, val);
171
8d6d09e7
GR		 172 return __mv88e6xxx_reg_write(bus, ds->pd->sw_addr, addr, reg, val);
173}
174
175int mv88e6xxx_reg_write(struct dsa_switch *ds, int addr, int reg, u16 val)
176{
177 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
178 int ret;
179
91da11f8 180 mutex_lock(&ps->smi_mutex);
8d6d09e7 181 ret = _mv88e6xxx_reg_write(ds, addr, reg, val);
91da11f8
LB		 182 mutex_unlock(&ps->smi_mutex);
183
184 return ret;
185}
186
2e5f0320
LB		 187int mv88e6xxx_set_addr_direct(struct dsa_switch *ds, u8 *addr)
188{
cca8b133
AL		 189 REG_WRITE(REG_GLOBAL, GLOBAL_MAC_01, (addr[0] << 8) | addr[1]);
190 REG_WRITE(REG_GLOBAL, GLOBAL_MAC_23, (addr[2] << 8) | addr[3]);
191 REG_WRITE(REG_GLOBAL, GLOBAL_MAC_45, (addr[4] << 8) | addr[5]);
2e5f0320
LB		 192
193 return 0;
194}
195
91da11f8
LB		 196int mv88e6xxx_set_addr_indirect(struct dsa_switch *ds, u8 *addr)
197{
198 int i;
199 int ret;
200
201 for (i = 0; i < 6; i++) {
202 int j;
203
3675c8d7 204 /* Write the MAC address byte. */
cca8b133
AL		 205 REG_WRITE(REG_GLOBAL2, GLOBAL2_SWITCH_MAC,
206 GLOBAL2_SWITCH_MAC_BUSY | (i << 8) | addr[i]);
91da11f8 207
3675c8d7 208 /* Wait for the write to complete. */
91da11f8 209 for (j = 0; j < 16; j++) {
cca8b133
AL		 210 ret = REG_READ(REG_GLOBAL2, GLOBAL2_SWITCH_MAC);
211 if ((ret & GLOBAL2_SWITCH_MAC_BUSY) == 0)
91da11f8
LB		 212 break;
213 }
214 if (j == 16)
215 return -ETIMEDOUT;
216 }
217
218 return 0;
219}
220
fd3a0ee4 221static int _mv88e6xxx_phy_read(struct dsa_switch *ds, int addr, int regnum)
91da11f8
LB		 222{
223 if (addr >= 0)
3898c148 224 return _mv88e6xxx_reg_read(ds, addr, regnum);
91da11f8
LB		 225 return 0xffff;
226}
227
fd3a0ee4
AL		 228static int _mv88e6xxx_phy_write(struct dsa_switch *ds, int addr, int regnum,
229 u16 val)
91da11f8
LB		 230{
231 if (addr >= 0)
3898c148 232 return _mv88e6xxx_reg_write(ds, addr, regnum, val);
91da11f8
LB		 233 return 0;
234}
235
2e5f0320
LB		 236#ifdef CONFIG_NET_DSA_MV88E6XXX_NEED_PPU
237static int mv88e6xxx_ppu_disable(struct dsa_switch *ds)
238{
239 int ret;
19b2f97e 240 unsigned long timeout;
2e5f0320 241
cca8b133
AL		 242 ret = REG_READ(REG_GLOBAL, GLOBAL_CONTROL);
243 REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL,
244 ret & ~GLOBAL_CONTROL_PPU_ENABLE);
2e5f0320 245
19b2f97e
BG		 246 timeout = jiffies + 1 * HZ;
247 while (time_before(jiffies, timeout)) {
cca8b133 248 ret = REG_READ(REG_GLOBAL, GLOBAL_STATUS);
19b2f97e 249 usleep_range(1000, 2000);
cca8b133
AL		 250 if ((ret & GLOBAL_STATUS_PPU_MASK) !=
251 GLOBAL_STATUS_PPU_POLLING)
85686581 252 return 0;
2e5f0320
LB		 253 }
254
255 return -ETIMEDOUT;
256}
257
258static int mv88e6xxx_ppu_enable(struct dsa_switch *ds)
259{
260 int ret;
19b2f97e 261 unsigned long timeout;
2e5f0320 262
cca8b133
AL		 263 ret = REG_READ(REG_GLOBAL, GLOBAL_CONTROL);
264 REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL, ret | GLOBAL_CONTROL_PPU_ENABLE);
2e5f0320 265
19b2f97e
BG		 266 timeout = jiffies + 1 * HZ;
267 while (time_before(jiffies, timeout)) {
cca8b133 268 ret = REG_READ(REG_GLOBAL, GLOBAL_STATUS);
19b2f97e 269 usleep_range(1000, 2000);
cca8b133
AL		 270 if ((ret & GLOBAL_STATUS_PPU_MASK) ==
271 GLOBAL_STATUS_PPU_POLLING)
85686581 272 return 0;
2e5f0320
LB		 273 }
274
275 return -ETIMEDOUT;
276}
277
278static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly)
279{
280 struct mv88e6xxx_priv_state *ps;
281
282 ps = container_of(ugly, struct mv88e6xxx_priv_state, ppu_work);
283 if (mutex_trylock(&ps->ppu_mutex)) {
85686581 284 struct dsa_switch *ds = ((struct dsa_switch *)ps) - 1;
2e5f0320 285
85686581
BG		 286 if (mv88e6xxx_ppu_enable(ds) == 0)
287 ps->ppu_disabled = 0;
288 mutex_unlock(&ps->ppu_mutex);
2e5f0320
LB		 289 }
290}
291
292static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps)
293{
294 struct mv88e6xxx_priv_state *ps = (void *)_ps;
295
296 schedule_work(&ps->ppu_work);
297}
298
299static int mv88e6xxx_ppu_access_get(struct dsa_switch *ds)
300{
a22adce5 301 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2e5f0320
LB		 302 int ret;
303
304 mutex_lock(&ps->ppu_mutex);
305
3675c8d7 306 /* If the PHY polling unit is enabled, disable it so that
2e5f0320
LB		 307 * we can access the PHY registers. If it was already
308 * disabled, cancel the timer that is going to re-enable
309 * it.
310 */
311 if (!ps->ppu_disabled) {
85686581
BG		 312 ret = mv88e6xxx_ppu_disable(ds);
313 if (ret < 0) {
314 mutex_unlock(&ps->ppu_mutex);
315 return ret;
316 }
317 ps->ppu_disabled = 1;
2e5f0320 318 } else {
85686581
BG		 319 del_timer(&ps->ppu_timer);
320 ret = 0;
2e5f0320
LB		 321 }
322
323 return ret;
324}
325
326static void mv88e6xxx_ppu_access_put(struct dsa_switch *ds)
327{
a22adce5 328 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2e5f0320 329
3675c8d7 330 /* Schedule a timer to re-enable the PHY polling unit. */
2e5f0320
LB		 331 mod_timer(&ps->ppu_timer, jiffies + msecs_to_jiffies(10));
332 mutex_unlock(&ps->ppu_mutex);
333}
334
335void mv88e6xxx_ppu_state_init(struct dsa_switch *ds)
336{
a22adce5 337 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2e5f0320
LB		 338
339 mutex_init(&ps->ppu_mutex);
340 INIT_WORK(&ps->ppu_work, mv88e6xxx_ppu_reenable_work);
341 init_timer(&ps->ppu_timer);
342 ps->ppu_timer.data = (unsigned long)ps;
343 ps->ppu_timer.function = mv88e6xxx_ppu_reenable_timer;
344}
345
346int mv88e6xxx_phy_read_ppu(struct dsa_switch *ds, int addr, int regnum)
347{
348 int ret;
349
350 ret = mv88e6xxx_ppu_access_get(ds);
351 if (ret >= 0) {
85686581
BG		 352 ret = mv88e6xxx_reg_read(ds, addr, regnum);
353 mv88e6xxx_ppu_access_put(ds);
2e5f0320
LB		 354 }
355
356 return ret;
357}
358
359int mv88e6xxx_phy_write_ppu(struct dsa_switch *ds, int addr,
360 int regnum, u16 val)
361{
362 int ret;
363
364 ret = mv88e6xxx_ppu_access_get(ds);
365 if (ret >= 0) {
85686581
BG		 366 ret = mv88e6xxx_reg_write(ds, addr, regnum, val);
367 mv88e6xxx_ppu_access_put(ds);
2e5f0320
LB		 368 }
369
370 return ret;
371}
372#endif
373
54d792f2
AL		 374static bool mv88e6xxx_6065_family(struct dsa_switch *ds)
375{
376 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
377
378 switch (ps->id) {
379 case PORT_SWITCH_ID_6031:
380 case PORT_SWITCH_ID_6061:
381 case PORT_SWITCH_ID_6035:
382 case PORT_SWITCH_ID_6065:
383 return true;
384 }
385 return false;
386}
387
388static bool mv88e6xxx_6095_family(struct dsa_switch *ds)
389{
390 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
391
392 switch (ps->id) {
393 case PORT_SWITCH_ID_6092:
394 case PORT_SWITCH_ID_6095:
395 return true;
396 }
397 return false;
398}
399
400static bool mv88e6xxx_6097_family(struct dsa_switch *ds)
401{
402 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
403
404 switch (ps->id) {
405 case PORT_SWITCH_ID_6046:
406 case PORT_SWITCH_ID_6085:
407 case PORT_SWITCH_ID_6096:
408 case PORT_SWITCH_ID_6097:
409 return true;
410 }
411 return false;
412}
413
414static bool mv88e6xxx_6165_family(struct dsa_switch *ds)
415{
416 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
417
418 switch (ps->id) {
419 case PORT_SWITCH_ID_6123:
420 case PORT_SWITCH_ID_6161:
421 case PORT_SWITCH_ID_6165:
422 return true;
423 }
424 return false;
425}
426
427static bool mv88e6xxx_6185_family(struct dsa_switch *ds)
428{
429 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
430
431 switch (ps->id) {
432 case PORT_SWITCH_ID_6121:
433 case PORT_SWITCH_ID_6122:
434 case PORT_SWITCH_ID_6152:
435 case PORT_SWITCH_ID_6155:
436 case PORT_SWITCH_ID_6182:
437 case PORT_SWITCH_ID_6185:
438 case PORT_SWITCH_ID_6108:
439 case PORT_SWITCH_ID_6131:
440 return true;
441 }
442 return false;
443}
444
c22995c5 445static bool mv88e6xxx_6320_family(struct dsa_switch *ds)
7c3d0d67
AK		 446{
447 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
448
449 switch (ps->id) {
450 case PORT_SWITCH_ID_6320:
451 case PORT_SWITCH_ID_6321:
452 return true;
453 }
454 return false;
455}
456
54d792f2
AL		 457static bool mv88e6xxx_6351_family(struct dsa_switch *ds)
458{
459 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
460
461 switch (ps->id) {
462 case PORT_SWITCH_ID_6171:
463 case PORT_SWITCH_ID_6175:
464 case PORT_SWITCH_ID_6350:
465 case PORT_SWITCH_ID_6351:
466 return true;
467 }
468 return false;
469}
470
f3a8b6b6
AL		 471static bool mv88e6xxx_6352_family(struct dsa_switch *ds)
472{
473 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
474
475 switch (ps->id) {
f3a8b6b6
AL		 476 case PORT_SWITCH_ID_6172:
477 case PORT_SWITCH_ID_6176:
54d792f2
AL		 478 case PORT_SWITCH_ID_6240:
479 case PORT_SWITCH_ID_6352:
f3a8b6b6
AL		 480 return true;
481 }
482 return false;
483}
484
dea87024
AL		 485/* We expect the switch to perform auto negotiation if there is a real
486 * phy. However, in the case of a fixed link phy, we force the port
487 * settings from the fixed link settings.
488 */
489void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
490 struct phy_device *phydev)
491{
492 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
49052871
AL		 493 u32 reg;
494 int ret;
dea87024
AL		 495
496 if (!phy_is_pseudo_fixed_link(phydev))
497 return;
498
499 mutex_lock(&ps->smi_mutex);
500
501 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_PCS_CTRL);
502 if (ret < 0)
503 goto out;
504
505 reg = ret & ~(PORT_PCS_CTRL_LINK_UP |
506 PORT_PCS_CTRL_FORCE_LINK |
507 PORT_PCS_CTRL_DUPLEX_FULL |
508 PORT_PCS_CTRL_FORCE_DUPLEX |
509 PORT_PCS_CTRL_UNFORCED);
510
511 reg |= PORT_PCS_CTRL_FORCE_LINK;
512 if (phydev->link)
513 reg |= PORT_PCS_CTRL_LINK_UP;
514
515 if (mv88e6xxx_6065_family(ds) && phydev->speed > SPEED_100)
516 goto out;
517
518 switch (phydev->speed) {
519 case SPEED_1000:
520 reg |= PORT_PCS_CTRL_1000;
521 break;
522 case SPEED_100:
523 reg |= PORT_PCS_CTRL_100;
524 break;
525 case SPEED_10:
526 reg |= PORT_PCS_CTRL_10;
527 break;
528 default:
529 pr_info("Unknown speed");
530 goto out;
531 }
532
533 reg |= PORT_PCS_CTRL_FORCE_DUPLEX;
534 if (phydev->duplex == DUPLEX_FULL)
535 reg |= PORT_PCS_CTRL_DUPLEX_FULL;
536
e7e72ac0
AL		 537 if ((mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds)) &&
538 (port >= ps->num_ports - 2)) {
539 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
540 reg |= PORT_PCS_CTRL_RGMII_DELAY_RXCLK;
541 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
542 reg |= PORT_PCS_CTRL_RGMII_DELAY_TXCLK;
543 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
544 reg |= (PORT_PCS_CTRL_RGMII_DELAY_RXCLK |
545 PORT_PCS_CTRL_RGMII_DELAY_TXCLK);
546 }
dea87024
AL		 547 _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_PCS_CTRL, reg);
548
549out:
550 mutex_unlock(&ps->smi_mutex);
551}
552
31888234 553static int _mv88e6xxx_stats_wait(struct dsa_switch *ds)
91da11f8
LB		 554{
555 int ret;
556 int i;
557
558 for (i = 0; i < 10; i++) {
31888234 559 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_STATS_OP);
cca8b133 560 if ((ret & GLOBAL_STATS_OP_BUSY) == 0)
91da11f8
LB		 561 return 0;
562 }
563
564 return -ETIMEDOUT;
565}
566
31888234 567static int _mv88e6xxx_stats_snapshot(struct dsa_switch *ds, int port)
91da11f8
LB		 568{
569 int ret;
570
7c3d0d67 571 if (mv88e6xxx_6320_family(ds) || mv88e6xxx_6352_family(ds))
f3a8b6b6
AL		 572 port = (port + 1) << 5;
573
3675c8d7 574 /* Snapshot the hardware statistics counters for this port. */
31888234
AL		 575 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_STATS_OP,
576 GLOBAL_STATS_OP_CAPTURE_PORT |
577 GLOBAL_STATS_OP_HIST_RX_TX | port);
578 if (ret < 0)
579 return ret;
91da11f8 580
3675c8d7 581 /* Wait for the snapshotting to complete. */
31888234 582 ret = _mv88e6xxx_stats_wait(ds);
91da11f8
LB		 583 if (ret < 0)
584 return ret;
585
586 return 0;
587}
588
31888234 589static void _mv88e6xxx_stats_read(struct dsa_switch *ds, int stat, u32 *val)
91da11f8
LB		 590{
591 u32 _val;
592 int ret;
593
594 *val = 0;
595
31888234
AL		 596 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_STATS_OP,
597 GLOBAL_STATS_OP_READ_CAPTURED |
598 GLOBAL_STATS_OP_HIST_RX_TX | stat);
91da11f8
LB		 599 if (ret < 0)
600 return;
601
31888234 602 ret = _mv88e6xxx_stats_wait(ds);
91da11f8
LB		 603 if (ret < 0)
604 return;
605
31888234 606 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_STATS_COUNTER_32);
91da11f8
LB		 607 if (ret < 0)
608 return;
609
610 _val = ret << 16;
611
31888234 612 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_STATS_COUNTER_01);
91da11f8
LB		 613 if (ret < 0)
614 return;
615
616 *val = _val | ret;
617}
618
e413e7e1 619static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
f5e2ed02
AL		 620 { "in_good_octets", 8, 0x00, BANK0, },
621 { "in_bad_octets", 4, 0x02, BANK0, },
622 { "in_unicast", 4, 0x04, BANK0, },
623 { "in_broadcasts", 4, 0x06, BANK0, },
624 { "in_multicasts", 4, 0x07, BANK0, },
625 { "in_pause", 4, 0x16, BANK0, },
626 { "in_undersize", 4, 0x18, BANK0, },
627 { "in_fragments", 4, 0x19, BANK0, },
628 { "in_oversize", 4, 0x1a, BANK0, },
629 { "in_jabber", 4, 0x1b, BANK0, },
630 { "in_rx_error", 4, 0x1c, BANK0, },
631 { "in_fcs_error", 4, 0x1d, BANK0, },
632 { "out_octets", 8, 0x0e, BANK0, },
633 { "out_unicast", 4, 0x10, BANK0, },
634 { "out_broadcasts", 4, 0x13, BANK0, },
635 { "out_multicasts", 4, 0x12, BANK0, },
636 { "out_pause", 4, 0x15, BANK0, },
637 { "excessive", 4, 0x11, BANK0, },
638 { "collisions", 4, 0x1e, BANK0, },
639 { "deferred", 4, 0x05, BANK0, },
640 { "single", 4, 0x14, BANK0, },
641 { "multiple", 4, 0x17, BANK0, },
642 { "out_fcs_error", 4, 0x03, BANK0, },
643 { "late", 4, 0x1f, BANK0, },
644 { "hist_64bytes", 4, 0x08, BANK0, },
645 { "hist_65_127bytes", 4, 0x09, BANK0, },
646 { "hist_128_255bytes", 4, 0x0a, BANK0, },
647 { "hist_256_511bytes", 4, 0x0b, BANK0, },
648 { "hist_512_1023bytes", 4, 0x0c, BANK0, },
649 { "hist_1024_max_bytes", 4, 0x0d, BANK0, },
650 { "sw_in_discards", 4, 0x10, PORT, },
651 { "sw_in_filtered", 2, 0x12, PORT, },
652 { "sw_out_filtered", 2, 0x13, PORT, },
653 { "in_discards", 4, 0x00 | GLOBAL_STATS_OP_BANK_1, BANK1, },
654 { "in_filtered", 4, 0x01 | GLOBAL_STATS_OP_BANK_1, BANK1, },
655 { "in_accepted", 4, 0x02 | GLOBAL_STATS_OP_BANK_1, BANK1, },
656 { "in_bad_accepted", 4, 0x03 | GLOBAL_STATS_OP_BANK_1, BANK1, },
657 { "in_good_avb_class_a", 4, 0x04 | GLOBAL_STATS_OP_BANK_1, BANK1, },
658 { "in_good_avb_class_b", 4, 0x05 | GLOBAL_STATS_OP_BANK_1, BANK1, },
659 { "in_bad_avb_class_a", 4, 0x06 | GLOBAL_STATS_OP_BANK_1, BANK1, },
660 { "in_bad_avb_class_b", 4, 0x07 | GLOBAL_STATS_OP_BANK_1, BANK1, },
661 { "tcam_counter_0", 4, 0x08 | GLOBAL_STATS_OP_BANK_1, BANK1, },
662 { "tcam_counter_1", 4, 0x09 | GLOBAL_STATS_OP_BANK_1, BANK1, },
663 { "tcam_counter_2", 4, 0x0a | GLOBAL_STATS_OP_BANK_1, BANK1, },
664 { "tcam_counter_3", 4, 0x0b | GLOBAL_STATS_OP_BANK_1, BANK1, },
665 { "in_da_unknown", 4, 0x0e | GLOBAL_STATS_OP_BANK_1, BANK1, },
666 { "in_management", 4, 0x0f | GLOBAL_STATS_OP_BANK_1, BANK1, },
667 { "out_queue_0", 4, 0x10 | GLOBAL_STATS_OP_BANK_1, BANK1, },
668 { "out_queue_1", 4, 0x11 | GLOBAL_STATS_OP_BANK_1, BANK1, },
669 { "out_queue_2", 4, 0x12 | GLOBAL_STATS_OP_BANK_1, BANK1, },
670 { "out_queue_3", 4, 0x13 | GLOBAL_STATS_OP_BANK_1, BANK1, },
671 { "out_queue_4", 4, 0x14 | GLOBAL_STATS_OP_BANK_1, BANK1, },
672 { "out_queue_5", 4, 0x15 | GLOBAL_STATS_OP_BANK_1, BANK1, },
673 { "out_queue_6", 4, 0x16 | GLOBAL_STATS_OP_BANK_1, BANK1, },
674 { "out_queue_7", 4, 0x17 | GLOBAL_STATS_OP_BANK_1, BANK1, },
675 { "out_cut_through", 4, 0x18 | GLOBAL_STATS_OP_BANK_1, BANK1, },
676 { "out_octets_a", 4, 0x1a | GLOBAL_STATS_OP_BANK_1, BANK1, },
677 { "out_octets_b", 4, 0x1b | GLOBAL_STATS_OP_BANK_1, BANK1, },
678 { "out_management", 4, 0x1f | GLOBAL_STATS_OP_BANK_1, BANK1, },
e413e7e1
AL		 679};
680
f5e2ed02
AL		 681static bool mv88e6xxx_has_stat(struct dsa_switch *ds,
682 struct mv88e6xxx_hw_stat *stat)
e413e7e1 683{
f5e2ed02
AL		 684 switch (stat->type) {
685 case BANK0:
e413e7e1 686 return true;
f5e2ed02
AL		 687 case BANK1:
688 return mv88e6xxx_6320_family(ds);
689 case PORT:
690 return mv88e6xxx_6095_family(ds) ||
691 mv88e6xxx_6185_family(ds) ||
692 mv88e6xxx_6097_family(ds) ||
693 mv88e6xxx_6165_family(ds) ||
694 mv88e6xxx_6351_family(ds) ||
695 mv88e6xxx_6352_family(ds);
91da11f8 696 }
f5e2ed02 697 return false;
91da11f8
LB		 698}
699
80c4627b 700static uint64_t _mv88e6xxx_get_ethtool_stat(struct dsa_switch *ds,
f5e2ed02 701 struct mv88e6xxx_hw_stat *s,
80c4627b
AL		 702 int port)
703{
80c4627b
AL		 704 u32 low;
705 u32 high = 0;
706 int ret;
707 u64 value;
708
f5e2ed02
AL		 709 switch (s->type) {
710 case PORT:
711 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port), s->reg);
80c4627b
AL		 712 if (ret < 0)
713 return UINT64_MAX;
714
715 low = ret;
716 if (s->sizeof_stat == 4) {
717 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port),
f5e2ed02 718 s->reg + 1);
80c4627b
AL		 719 if (ret < 0)
720 return UINT64_MAX;
721 high = ret;
722 }
f5e2ed02
AL		 723 break;
724 case BANK0:
725 case BANK1:
80c4627b
AL		 726 _mv88e6xxx_stats_read(ds, s->reg, &low);
727 if (s->sizeof_stat == 8)
728 _mv88e6xxx_stats_read(ds, s->reg + 1, &high);
729 }
730 value = (((u64)high) << 16) | low;
731 return value;
732}
733
f5e2ed02 734void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, uint8_t *data)
91da11f8 735{
f5e2ed02
AL		 736 struct mv88e6xxx_hw_stat *stat;
737 int i, j;
91da11f8 738
f5e2ed02
AL		 739 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
740 stat = &mv88e6xxx_hw_stats[i];
741 if (mv88e6xxx_has_stat(ds, stat)) {
742 memcpy(data + j * ETH_GSTRING_LEN, stat->string,
743 ETH_GSTRING_LEN);
744 j++;
745 }
91da11f8 746 }
e413e7e1
AL		 747}
748
749int mv88e6xxx_get_sset_count(struct dsa_switch *ds)
750{
f5e2ed02
AL		 751 struct mv88e6xxx_hw_stat *stat;
752 int i, j;
753
754 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
755 stat = &mv88e6xxx_hw_stats[i];
756 if (mv88e6xxx_has_stat(ds, stat))
757 j++;
758 }
759 return j;
e413e7e1
AL		 760}
761
762void
763mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds,
764 int port, uint64_t *data)
765{
f5e2ed02
AL		 766 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
767 struct mv88e6xxx_hw_stat *stat;
768 int ret;
769 int i, j;
770
771 mutex_lock(&ps->smi_mutex);
772
773 ret = _mv88e6xxx_stats_snapshot(ds, port);
774 if (ret < 0) {
775 mutex_unlock(&ps->smi_mutex);
776 return;
777 }
778 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
779 stat = &mv88e6xxx_hw_stats[i];
780 if (mv88e6xxx_has_stat(ds, stat)) {
781 data[j] = _mv88e6xxx_get_ethtool_stat(ds, stat, port);
782 j++;
783 }
784 }
785
786 mutex_unlock(&ps->smi_mutex);
e413e7e1
AL		 787}
788
a1ab91f3
GR		 789int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
790{
791 return 32 * sizeof(u16);
792}
793
794void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
795 struct ethtool_regs *regs, void *_p)
796{
797 u16 *p = _p;
798 int i;
799
800 regs->version = 0;
801
802 memset(p, 0xff, 32 * sizeof(u16));
803
804 for (i = 0; i < 32; i++) {
805 int ret;
806
807 ret = mv88e6xxx_reg_read(ds, REG_PORT(port), i);
808 if (ret >= 0)
809 p[i] = ret;
810 }
811}
812
3898c148
AL		 813static int _mv88e6xxx_wait(struct dsa_switch *ds, int reg, int offset,
814 u16 mask)
f3044683
AL		 815{
816 unsigned long timeout = jiffies + HZ / 10;
817
818 while (time_before(jiffies, timeout)) {
819 int ret;
820
3898c148
AL		 821 ret = _mv88e6xxx_reg_read(ds, reg, offset);
822 if (ret < 0)
823 return ret;
f3044683
AL		 824 if (!(ret & mask))
825 return 0;
826
827 usleep_range(1000, 2000);
828 }
829 return -ETIMEDOUT;
830}
831
3898c148
AL		 832static int mv88e6xxx_wait(struct dsa_switch *ds, int reg, int offset, u16 mask)
833{
834 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
835 int ret;
836
837 mutex_lock(&ps->smi_mutex);
838 ret = _mv88e6xxx_wait(ds, reg, offset, mask);
839 mutex_unlock(&ps->smi_mutex);
840
841 return ret;
842}
843
844static int _mv88e6xxx_phy_wait(struct dsa_switch *ds)
f3044683 845{
3898c148
AL		 846 return _mv88e6xxx_wait(ds, REG_GLOBAL2, GLOBAL2_SMI_OP,
847 GLOBAL2_SMI_OP_BUSY);
f3044683
AL		 848}
849
850int mv88e6xxx_eeprom_load_wait(struct dsa_switch *ds)
851{
cca8b133
AL		 852 return mv88e6xxx_wait(ds, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
853 GLOBAL2_EEPROM_OP_LOAD);
f3044683
AL		 854}
855
856int mv88e6xxx_eeprom_busy_wait(struct dsa_switch *ds)
857{
cca8b133
AL		 858 return mv88e6xxx_wait(ds, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
859 GLOBAL2_EEPROM_OP_BUSY);
f3044683
AL		 860}
861
facd95b2
GR		 862static int _mv88e6xxx_atu_wait(struct dsa_switch *ds)
863{
cca8b133
AL		 864 return _mv88e6xxx_wait(ds, REG_GLOBAL, GLOBAL_ATU_OP,
865 GLOBAL_ATU_OP_BUSY);
facd95b2
GR		 866}
867
fd3a0ee4
AL		 868static int _mv88e6xxx_phy_read_indirect(struct dsa_switch *ds, int addr,
869 int regnum)
f3044683
AL		 870{
871 int ret;
872
3898c148
AL		 873 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_SMI_OP,
874 GLOBAL2_SMI_OP_22_READ | (addr << 5) |
875 regnum);
876 if (ret < 0)
877 return ret;
f3044683 878
3898c148 879 ret = _mv88e6xxx_phy_wait(ds);
f3044683
AL		 880 if (ret < 0)
881 return ret;
882
3898c148 883 return _mv88e6xxx_reg_read(ds, REG_GLOBAL2, GLOBAL2_SMI_DATA);
f3044683
AL		 884}
885
fd3a0ee4
AL		 886static int _mv88e6xxx_phy_write_indirect(struct dsa_switch *ds, int addr,
887 int regnum, u16 val)
f3044683 888{
3898c148
AL		 889 int ret;
890
891 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_SMI_DATA, val);
892 if (ret < 0)
893 return ret;
f3044683 894
3898c148
AL		 895 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_SMI_OP,
896 GLOBAL2_SMI_OP_22_WRITE | (addr << 5) |
897 regnum);
898
899 return _mv88e6xxx_phy_wait(ds);
f3044683
AL		 900}
901
11b3b45d
GR		 902int mv88e6xxx_get_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e)
903{
2f40c698 904 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
11b3b45d
GR		 905 int reg;
906
3898c148 907 mutex_lock(&ps->smi_mutex);
2f40c698
AL		 908
909 reg = _mv88e6xxx_phy_read_indirect(ds, port, 16);
11b3b45d 910 if (reg < 0)
2f40c698 911 goto out;
11b3b45d
GR		 912
913 e->eee_enabled = !!(reg & 0x0200);
914 e->tx_lpi_enabled = !!(reg & 0x0100);
915
3898c148 916 reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_STATUS);
11b3b45d 917 if (reg < 0)
2f40c698 918 goto out;
11b3b45d 919
cca8b133 920 e->eee_active = !!(reg & PORT_STATUS_EEE);
2f40c698 921 reg = 0;
11b3b45d 922
2f40c698 923out:
3898c148 924 mutex_unlock(&ps->smi_mutex);
2f40c698 925 return reg;
11b3b45d
GR		 926}
927
928int mv88e6xxx_set_eee(struct dsa_switch *ds, int port,
929 struct phy_device *phydev, struct ethtool_eee *e)
930{
2f40c698
AL		 931 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
932 int reg;
11b3b45d
GR		 933 int ret;
934
3898c148 935 mutex_lock(&ps->smi_mutex);
11b3b45d 936
2f40c698
AL		 937 ret = _mv88e6xxx_phy_read_indirect(ds, port, 16);
938 if (ret < 0)
939 goto out;
940
941 reg = ret & ~0x0300;
942 if (e->eee_enabled)
943 reg |= 0x0200;
944 if (e->tx_lpi_enabled)
945 reg |= 0x0100;
946
947 ret = _mv88e6xxx_phy_write_indirect(ds, port, 16, reg);
948out:
3898c148 949 mutex_unlock(&ps->smi_mutex);
2f40c698
AL		 950
951 return ret;
11b3b45d
GR		 952}
953
70cc99d1 954static int _mv88e6xxx_atu_cmd(struct dsa_switch *ds, u16 cmd)
facd95b2
GR		 955{
956 int ret;
957
cca8b133 958 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_OP, cmd);
facd95b2
GR		 959 if (ret < 0)
960 return ret;
961
962 return _mv88e6xxx_atu_wait(ds);
963}
964
37705b73
VD		 965static int _mv88e6xxx_atu_data_write(struct dsa_switch *ds,
966 struct mv88e6xxx_atu_entry *entry)
967{
968 u16 data = entry->state & GLOBAL_ATU_DATA_STATE_MASK;
969
970 if (entry->state != GLOBAL_ATU_DATA_STATE_UNUSED) {
971 unsigned int mask, shift;
972
973 if (entry->trunk) {
974 data |= GLOBAL_ATU_DATA_TRUNK;
975 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
976 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
977 } else {
978 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
979 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
980 }
981
982 data |= (entry->portv_trunkid << shift) & mask;
983 }
984
985 return _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_DATA, data);
986}
987
7fb5e755
VD		 988static int _mv88e6xxx_atu_flush_move(struct dsa_switch *ds,
989 struct mv88e6xxx_atu_entry *entry,
990 bool static_too)
facd95b2 991{
7fb5e755
VD		 992 int op;
993 int err;
facd95b2 994
7fb5e755
VD		 995 err = _mv88e6xxx_atu_wait(ds);
996 if (err)
997 return err;
facd95b2 998
7fb5e755
VD		 999 err = _mv88e6xxx_atu_data_write(ds, entry);
1000 if (err)
1001 return err;
1002
1003 if (entry->fid) {
1004 err = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_FID,
1005 entry->fid);
1006 if (err)
1007 return err;
1008
1009 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL_DB :
1010 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC_DB;
1011 } else {
1012 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL :
1013 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC;
1014 }
1015
1016 return _mv88e6xxx_atu_cmd(ds, op);
1017}
1018
1019static int _mv88e6xxx_atu_flush(struct dsa_switch *ds, u16 fid, bool static_too)
1020{
1021 struct mv88e6xxx_atu_entry entry = {
1022 .fid = fid,
1023 .state = 0, /* EntryState bits must be 0 */
1024 };
70cc99d1 1025
7fb5e755
VD		 1026 return _mv88e6xxx_atu_flush_move(ds, &entry, static_too);
1027}
1028
9f4d55d2
VD		 1029static int _mv88e6xxx_atu_move(struct dsa_switch *ds, u16 fid, int from_port,
1030 int to_port, bool static_too)
1031{
1032 struct mv88e6xxx_atu_entry entry = {
1033 .trunk = false,
1034 .fid = fid,
1035 };
1036
1037 /* EntryState bits must be 0xF */
1038 entry.state = GLOBAL_ATU_DATA_STATE_MASK;
1039
1040 /* ToPort and FromPort are respectively in PortVec bits 7:4 and 3:0 */
1041 entry.portv_trunkid = (to_port & 0x0f) << 4;
1042 entry.portv_trunkid |= from_port & 0x0f;
1043
1044 return _mv88e6xxx_atu_flush_move(ds, &entry, static_too);
1045}
1046
1047static int _mv88e6xxx_atu_remove(struct dsa_switch *ds, u16 fid, int port,
1048 bool static_too)
1049{
1050 /* Destination port 0xF means remove the entries */
1051 return _mv88e6xxx_atu_move(ds, fid, port, 0x0f, static_too);
1052}
1053
facd95b2
GR		 1054static int mv88e6xxx_set_port_state(struct dsa_switch *ds, int port, u8 state)
1055{
1056 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
c3ffe6d2 1057 int reg, ret = 0;
facd95b2
GR		 1058 u8 oldstate;
1059
1060 mutex_lock(&ps->smi_mutex);
1061
cca8b133 1062 reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_CONTROL);
538cc282
GR		 1063 if (reg < 0) {
1064 ret = reg;
facd95b2 1065 goto abort;
538cc282 1066 }
facd95b2 1067
cca8b133 1068 oldstate = reg & PORT_CONTROL_STATE_MASK;
facd95b2
GR		 1069 if (oldstate != state) {
1070 /* Flush forwarding database if we're moving a port
1071 * from Learning or Forwarding state to Disabled or
1072 * Blocking or Listening state.
1073 */
cca8b133
AL		 1074 if (oldstate >= PORT_CONTROL_STATE_LEARNING &&
1075 state <= PORT_CONTROL_STATE_BLOCKING) {
2b8157b1 1076 ret = _mv88e6xxx_atu_remove(ds, 0, port, false);
facd95b2
GR		 1077 if (ret)
1078 goto abort;
1079 }
cca8b133
AL		 1080 reg = (reg & ~PORT_CONTROL_STATE_MASK) | state;
1081 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_CONTROL,
1082 reg);
facd95b2
GR		 1083 }
1084
1085abort:
1086 mutex_unlock(&ps->smi_mutex);
1087 return ret;
1088}
1089
b7666efe 1090static int _mv88e6xxx_port_based_vlan_map(struct dsa_switch *ds, int port)
facd95b2
GR		 1091{
1092 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
b7666efe 1093 struct net_device *bridge = ps->ports[port].bridge_dev;
ede8098d 1094 const u16 mask = (1 << ps->num_ports) - 1;
b7666efe 1095 u16 output_ports = 0;
ede8098d 1096 int reg;
b7666efe
VD		 1097 int i;
1098
1099 /* allow CPU port or DSA link(s) to send frames to every port */
1100 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
1101 output_ports = mask;
1102 } else {
1103 for (i = 0; i < ps->num_ports; ++i) {
1104 /* allow sending frames to every group member */
1105 if (bridge && ps->ports[i].bridge_dev == bridge)
1106 output_ports |= BIT(i);
1107
1108 /* allow sending frames to CPU port and DSA link(s) */
1109 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
1110 output_ports |= BIT(i);
1111 }
1112 }
1113
1114 /* prevent frames from going back out of the port they came in on */
1115 output_ports &= ~BIT(port);
facd95b2 1116
ede8098d
VD		 1117 reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_BASE_VLAN);
1118 if (reg < 0)
1119 return reg;
facd95b2 1120
ede8098d
VD		 1121 reg &= ~mask;
1122 reg |= output_ports & mask;
facd95b2 1123
ede8098d 1124 return _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_BASE_VLAN, reg);
facd95b2
GR		 1125}
1126
facd95b2
GR		 1127int mv88e6xxx_port_stp_update(struct dsa_switch *ds, int port, u8 state)
1128{
1129 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1130 int stp_state;
1131
1132 switch (state) {
1133 case BR_STATE_DISABLED:
cca8b133 1134 stp_state = PORT_CONTROL_STATE_DISABLED;
facd95b2
GR		 1135 break;
1136 case BR_STATE_BLOCKING:
1137 case BR_STATE_LISTENING:
cca8b133 1138 stp_state = PORT_CONTROL_STATE_BLOCKING;
facd95b2
GR		 1139 break;
1140 case BR_STATE_LEARNING:
cca8b133 1141 stp_state = PORT_CONTROL_STATE_LEARNING;
facd95b2
GR		 1142 break;
1143 case BR_STATE_FORWARDING:
1144 default:
cca8b133 1145 stp_state = PORT_CONTROL_STATE_FORWARDING;
facd95b2
GR		 1146 break;
1147 }
1148
1149 netdev_dbg(ds->ports[port], "port state %d [%d]\n", state, stp_state);
1150
1151 /* mv88e6xxx_port_stp_update may be called with softirqs disabled,
1152 * so we can not update the port state directly but need to schedule it.
1153 */
d715fa64 1154 ps->ports[port].state = stp_state;
facd95b2
GR		 1155 set_bit(port, &ps->port_state_update_mask);
1156 schedule_work(&ps->bridge_work);
1157
1158 return 0;
1159}
1160
76e398a6
VD		 1161static int _mv88e6xxx_port_pvid_get(struct dsa_switch *ds, int port, u16 *pvid)
1162{
1163 int ret;
1164
1165 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_DEFAULT_VLAN);
1166 if (ret < 0)
1167 return ret;
1168
1169 *pvid = ret & PORT_DEFAULT_VLAN_MASK;
1170
1171 return 0;
1172}
1173
76e398a6 1174static int _mv88e6xxx_port_pvid_set(struct dsa_switch *ds, int port, u16 pvid)
0d3b33e6 1175{
76e398a6 1176 return _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_DEFAULT_VLAN,
0d3b33e6
VD		 1177 pvid & PORT_DEFAULT_VLAN_MASK);
1178}
1179
6b17e864
VD		 1180static int _mv88e6xxx_vtu_wait(struct dsa_switch *ds)
1181{
1182 return _mv88e6xxx_wait(ds, REG_GLOBAL, GLOBAL_VTU_OP,
1183 GLOBAL_VTU_OP_BUSY);
1184}
1185
1186static int _mv88e6xxx_vtu_cmd(struct dsa_switch *ds, u16 op)
1187{
1188 int ret;
1189
1190 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_OP, op);
1191 if (ret < 0)
1192 return ret;
1193
1194 return _mv88e6xxx_vtu_wait(ds);
1195}
1196
1197static int _mv88e6xxx_vtu_stu_flush(struct dsa_switch *ds)
1198{
1199 int ret;
1200
1201 ret = _mv88e6xxx_vtu_wait(ds);
1202 if (ret < 0)
1203 return ret;
1204
1205 return _mv88e6xxx_vtu_cmd(ds, GLOBAL_VTU_OP_FLUSH_ALL);
1206}
1207
b8fee957
VD		 1208static int _mv88e6xxx_vtu_stu_data_read(struct dsa_switch *ds,
1209 struct mv88e6xxx_vtu_stu_entry *entry,
1210 unsigned int nibble_offset)
1211{
1212 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1213 u16 regs[3];
1214 int i;
1215 int ret;
1216
1217 for (i = 0; i < 3; ++i) {
1218 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL,
1219 GLOBAL_VTU_DATA_0_3 + i);
1220 if (ret < 0)
1221 return ret;
1222
1223 regs[i] = ret;
1224 }
1225
1226 for (i = 0; i < ps->num_ports; ++i) {
1227 unsigned int shift = (i % 4) * 4 + nibble_offset;
1228 u16 reg = regs[i / 4];
1229
1230 entry->data[i] = (reg >> shift) & GLOBAL_VTU_STU_DATA_MASK;
1231 }
1232
1233 return 0;
1234}
1235
7dad08d7
VD		 1236static int _mv88e6xxx_vtu_stu_data_write(struct dsa_switch *ds,
1237 struct mv88e6xxx_vtu_stu_entry *entry,
1238 unsigned int nibble_offset)
1239{
1240 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1241 u16 regs[3] = { 0 };
1242 int i;
1243 int ret;
1244
1245 for (i = 0; i < ps->num_ports; ++i) {
1246 unsigned int shift = (i % 4) * 4 + nibble_offset;
1247 u8 data = entry->data[i];
1248
1249 regs[i / 4] |= (data & GLOBAL_VTU_STU_DATA_MASK) << shift;
1250 }
1251
1252 for (i = 0; i < 3; ++i) {
1253 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL,
1254 GLOBAL_VTU_DATA_0_3 + i, regs[i]);
1255 if (ret < 0)
1256 return ret;
1257 }
1258
1259 return 0;
1260}
1261
36d04ba1
VD		 1262static int _mv88e6xxx_vtu_vid_write(struct dsa_switch *ds, u16 vid)
1263{
1264 return _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_VID,
1265 vid & GLOBAL_VTU_VID_MASK);
1266}
1267
1268static int _mv88e6xxx_vtu_getnext(struct dsa_switch *ds,
b8fee957
VD		 1269 struct mv88e6xxx_vtu_stu_entry *entry)
1270{
1271 struct mv88e6xxx_vtu_stu_entry next = { 0 };
1272 int ret;
1273
1274 ret = _mv88e6xxx_vtu_wait(ds);
1275 if (ret < 0)
1276 return ret;
1277
b8fee957
VD		 1278 ret = _mv88e6xxx_vtu_cmd(ds, GLOBAL_VTU_OP_VTU_GET_NEXT);
1279 if (ret < 0)
1280 return ret;
1281
1282 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_VTU_VID);
1283 if (ret < 0)
1284 return ret;
1285
1286 next.vid = ret & GLOBAL_VTU_VID_MASK;
1287 next.valid = !!(ret & GLOBAL_VTU_VID_VALID);
1288
1289 if (next.valid) {
1290 ret = _mv88e6xxx_vtu_stu_data_read(ds, &next, 0);
1291 if (ret < 0)
1292 return ret;
1293
1294 if (mv88e6xxx_6097_family(ds) || mv88e6xxx_6165_family(ds) ||
1295 mv88e6xxx_6351_family(ds) || mv88e6xxx_6352_family(ds)) {
1296 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL,
1297 GLOBAL_VTU_FID);
1298 if (ret < 0)
1299 return ret;
1300
1301 next.fid = ret & GLOBAL_VTU_FID_MASK;
1302
1303 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL,
1304 GLOBAL_VTU_SID);
1305 if (ret < 0)
1306 return ret;
1307
1308 next.sid = ret & GLOBAL_VTU_SID_MASK;
1309 }
1310 }
1311
1312 *entry = next;
1313 return 0;
1314}
1315
ceff5eff
VD		 1316int mv88e6xxx_port_vlan_dump(struct dsa_switch *ds, int port,
1317 struct switchdev_obj_port_vlan *vlan,
1318 int (*cb)(struct switchdev_obj *obj))
1319{
1320 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1321 struct mv88e6xxx_vtu_stu_entry next;
1322 u16 pvid;
1323 int err;
1324
1325 mutex_lock(&ps->smi_mutex);
1326
1327 err = _mv88e6xxx_port_pvid_get(ds, port, &pvid);
1328 if (err)
1329 goto unlock;
1330
1331 err = _mv88e6xxx_vtu_vid_write(ds, GLOBAL_VTU_VID_MASK);
1332 if (err)
1333 goto unlock;
1334
1335 do {
1336 err = _mv88e6xxx_vtu_getnext(ds, &next);
1337 if (err)
1338 break;
1339
1340 if (!next.valid)
1341 break;
1342
1343 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1344 continue;
1345
1346 /* reinit and dump this VLAN obj */
1347 vlan->vid_begin = vlan->vid_end = next.vid;
1348 vlan->flags = 0;
1349
1350 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED)
1351 vlan->flags |= BRIDGE_VLAN_INFO_UNTAGGED;
1352
1353 if (next.vid == pvid)
1354 vlan->flags |= BRIDGE_VLAN_INFO_PVID;
1355
1356 err = cb(&vlan->obj);
1357 if (err)
1358 break;
1359 } while (next.vid < GLOBAL_VTU_VID_MASK);
1360
1361unlock:
1362 mutex_unlock(&ps->smi_mutex);
1363
1364 return err;
1365}
1366
7dad08d7
VD		 1367static int _mv88e6xxx_vtu_loadpurge(struct dsa_switch *ds,
1368 struct mv88e6xxx_vtu_stu_entry *entry)
1369{
1370 u16 reg = 0;
1371 int ret;
1372
1373 ret = _mv88e6xxx_vtu_wait(ds);
1374 if (ret < 0)
1375 return ret;
1376
1377 if (!entry->valid)
1378 goto loadpurge;
1379
1380 /* Write port member tags */
1381 ret = _mv88e6xxx_vtu_stu_data_write(ds, entry, 0);
1382 if (ret < 0)
1383 return ret;
1384
1385 if (mv88e6xxx_6097_family(ds) || mv88e6xxx_6165_family(ds) ||
1386 mv88e6xxx_6351_family(ds) || mv88e6xxx_6352_family(ds)) {
1387 reg = entry->sid & GLOBAL_VTU_SID_MASK;
1388 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_SID, reg);
1389 if (ret < 0)
1390 return ret;
1391
1392 reg = entry->fid & GLOBAL_VTU_FID_MASK;
1393 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_FID, reg);
1394 if (ret < 0)
1395 return ret;
1396 }
1397
1398 reg = GLOBAL_VTU_VID_VALID;
1399loadpurge:
1400 reg |= entry->vid & GLOBAL_VTU_VID_MASK;
1401 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_VID, reg);
1402 if (ret < 0)
1403 return ret;
1404
1405 return _mv88e6xxx_vtu_cmd(ds, GLOBAL_VTU_OP_VTU_LOAD_PURGE);
1406}
1407
0d3b33e6
VD		 1408static int _mv88e6xxx_stu_getnext(struct dsa_switch *ds, u8 sid,
1409 struct mv88e6xxx_vtu_stu_entry *entry)
1410{
1411 struct mv88e6xxx_vtu_stu_entry next = { 0 };
1412 int ret;
1413
1414 ret = _mv88e6xxx_vtu_wait(ds);
1415 if (ret < 0)
1416 return ret;
1417
1418 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_SID,
1419 sid & GLOBAL_VTU_SID_MASK);
1420 if (ret < 0)
1421 return ret;
1422
1423 ret = _mv88e6xxx_vtu_cmd(ds, GLOBAL_VTU_OP_STU_GET_NEXT);
1424 if (ret < 0)
1425 return ret;
1426
1427 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_VTU_SID);
1428 if (ret < 0)
1429 return ret;
1430
1431 next.sid = ret & GLOBAL_VTU_SID_MASK;
1432
1433 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_VTU_VID);
1434 if (ret < 0)
1435 return ret;
1436
1437 next.valid = !!(ret & GLOBAL_VTU_VID_VALID);
1438
1439 if (next.valid) {
1440 ret = _mv88e6xxx_vtu_stu_data_read(ds, &next, 2);
1441 if (ret < 0)
1442 return ret;
1443 }
1444
1445 *entry = next;
1446 return 0;
1447}
1448
1449static int _mv88e6xxx_stu_loadpurge(struct dsa_switch *ds,
1450 struct mv88e6xxx_vtu_stu_entry *entry)
1451{
1452 u16 reg = 0;
1453 int ret;
1454
1455 ret = _mv88e6xxx_vtu_wait(ds);
1456 if (ret < 0)
1457 return ret;
1458
1459 if (!entry->valid)
1460 goto loadpurge;
1461
1462 /* Write port states */
1463 ret = _mv88e6xxx_vtu_stu_data_write(ds, entry, 2);
1464 if (ret < 0)
1465 return ret;
1466
1467 reg = GLOBAL_VTU_VID_VALID;
1468loadpurge:
1469 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_VID, reg);
1470 if (ret < 0)
1471 return ret;
1472
1473 reg = entry->sid & GLOBAL_VTU_SID_MASK;
1474 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_SID, reg);
1475 if (ret < 0)
1476 return ret;
1477
1478 return _mv88e6xxx_vtu_cmd(ds, GLOBAL_VTU_OP_STU_LOAD_PURGE);
1479}
1480
2db9ce1f
VD		 1481static int _mv88e6xxx_port_fid(struct dsa_switch *ds, int port, u16 *new,
1482 u16 *old)
1483{
1484 u16 fid;
1485 int ret;
1486
1487 /* Port's default FID bits 3:0 are located in reg 0x06, offset 12 */
1488 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_BASE_VLAN);
1489 if (ret < 0)
1490 return ret;
1491
1492 fid = (ret & PORT_BASE_VLAN_FID_3_0_MASK) >> 12;
1493
1494 if (new) {
1495 ret &= ~PORT_BASE_VLAN_FID_3_0_MASK;
1496 ret |= (*new << 12) & PORT_BASE_VLAN_FID_3_0_MASK;
1497
1498 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_BASE_VLAN,
1499 ret);
1500 if (ret < 0)
1501 return ret;
1502 }
1503
1504 /* Port's default FID bits 11:4 are located in reg 0x05, offset 0 */
1505 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_CONTROL_1);
1506 if (ret < 0)
1507 return ret;
1508
1509 fid |= (ret & PORT_CONTROL_1_FID_11_4_MASK) << 4;
1510
1511 if (new) {
1512 ret &= ~PORT_CONTROL_1_FID_11_4_MASK;
1513 ret |= (*new >> 4) & PORT_CONTROL_1_FID_11_4_MASK;
1514
1515 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_CONTROL_1,
1516 ret);
1517 if (ret < 0)
1518 return ret;
1519
1520 netdev_dbg(ds->ports[port], "FID %d (was %d)\n", *new, fid);
1521 }
1522
1523 if (old)
1524 *old = fid;
1525
1526 return 0;
1527}
1528
1529static int _mv88e6xxx_port_fid_get(struct dsa_switch *ds, int port, u16 *fid)
1530{
1531 return _mv88e6xxx_port_fid(ds, port, NULL, fid);
1532}
1533
1534static int _mv88e6xxx_port_fid_set(struct dsa_switch *ds, int port, u16 fid)
1535{
1536 return _mv88e6xxx_port_fid(ds, port, &fid, NULL);
1537}
1538
3285f9e8
VD		 1539static int _mv88e6xxx_fid_new(struct dsa_switch *ds, u16 *fid)
1540{
2db9ce1f 1541 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
3285f9e8
VD		 1542 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
1543 struct mv88e6xxx_vtu_stu_entry vlan;
2db9ce1f 1544 int i, err;
3285f9e8
VD		 1545
1546 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1547
2db9ce1f
VD		 1548 /* Set every FID bit used by the (un)bridged ports */
1549 for (i = 0; i < ps->num_ports; ++i) {
1550 err = _mv88e6xxx_port_fid_get(ds, i, fid);
1551 if (err)
1552 return err;
1553
1554 set_bit(*fid, fid_bitmap);
1555 }
1556
3285f9e8
VD		 1557 /* Set every FID bit used by the VLAN entries */
1558 err = _mv88e6xxx_vtu_vid_write(ds, GLOBAL_VTU_VID_MASK);
1559 if (err)
1560 return err;
1561
1562 do {
1563 err = _mv88e6xxx_vtu_getnext(ds, &vlan);
1564 if (err)
1565 return err;
1566
1567 if (!vlan.valid)
1568 break;
1569
1570 set_bit(vlan.fid, fid_bitmap);
1571 } while (vlan.vid < GLOBAL_VTU_VID_MASK);
1572
1573 /* The reset value 0x000 is used to indicate that multiple address
1574 * databases are not needed. Return the next positive available.
1575 */
1576 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
1577 if (unlikely(*fid == MV88E6XXX_N_FID))
1578 return -ENOSPC;
1579
1580 /* Clear the database */
1581 return _mv88e6xxx_atu_flush(ds, *fid, true);
1582}
1583
2fb5ef09
VD		 1584static int _mv88e6xxx_vtu_new(struct dsa_switch *ds, u16 vid,
1585 struct mv88e6xxx_vtu_stu_entry *entry)
0d3b33e6
VD		 1586{
1587 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1588 struct mv88e6xxx_vtu_stu_entry vlan = {
1589 .valid = true,
1590 .vid = vid,
1591 };
3285f9e8
VD		 1592 int i, err;
1593
1594 err = _mv88e6xxx_fid_new(ds, &vlan.fid);
1595 if (err)
1596 return err;
0d3b33e6 1597
3d131f07 1598 /* exclude all ports except the CPU and DSA ports */
0d3b33e6 1599 for (i = 0; i < ps->num_ports; ++i)
3d131f07
VD		 1600 vlan.data[i] = dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i)
1601 ? GLOBAL_VTU_DATA_MEMBER_TAG_UNMODIFIED
1602 : GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
0d3b33e6
VD		 1603
1604 if (mv88e6xxx_6097_family(ds) || mv88e6xxx_6165_family(ds) ||
1605 mv88e6xxx_6351_family(ds) || mv88e6xxx_6352_family(ds)) {
1606 struct mv88e6xxx_vtu_stu_entry vstp;
0d3b33e6
VD		 1607
1608 /* Adding a VTU entry requires a valid STU entry. As VSTP is not
1609 * implemented, only one STU entry is needed to cover all VTU
1610 * entries. Thus, validate the SID 0.
1611 */
1612 vlan.sid = 0;
1613 err = _mv88e6xxx_stu_getnext(ds, GLOBAL_VTU_SID_MASK, &vstp);
1614 if (err)
1615 return err;
1616
1617 if (vstp.sid != vlan.sid || !vstp.valid) {
1618 memset(&vstp, 0, sizeof(vstp));
1619 vstp.valid = true;
1620 vstp.sid = vlan.sid;
1621
1622 err = _mv88e6xxx_stu_loadpurge(ds, &vstp);
1623 if (err)
1624 return err;
1625 }
0d3b33e6
VD		 1626 }
1627
1628 *entry = vlan;
1629 return 0;
1630}
1631
2fb5ef09
VD		 1632static int _mv88e6xxx_vtu_get(struct dsa_switch *ds, u16 vid,
1633 struct mv88e6xxx_vtu_stu_entry *entry, bool creat)
1634{
1635 int err;
1636
1637 if (!vid)
1638 return -EINVAL;
1639
1640 err = _mv88e6xxx_vtu_vid_write(ds, vid - 1);
1641 if (err)
1642 return err;
1643
1644 err = _mv88e6xxx_vtu_getnext(ds, entry);
1645 if (err)
1646 return err;
1647
1648 if (entry->vid != vid || !entry->valid) {
1649 if (!creat)
1650 return -EOPNOTSUPP;
1651 /* -ENOENT would've been more appropriate, but switchdev expects
1652 * -EOPNOTSUPP to inform bridge about an eventual software VLAN.
1653 */
1654
1655 err = _mv88e6xxx_vtu_new(ds, vid, entry);
1656 }
1657
1658 return err;
1659}
1660
da9c359e
VD		 1661static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
1662 u16 vid_begin, u16 vid_end)
1663{
1664 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1665 struct mv88e6xxx_vtu_stu_entry vlan;
1666 int i, err;
1667
1668 if (!vid_begin)
1669 return -EOPNOTSUPP;
1670
1671 mutex_lock(&ps->smi_mutex);
1672
1673 err = _mv88e6xxx_vtu_vid_write(ds, vid_begin - 1);
1674 if (err)
1675 goto unlock;
1676
1677 do {
1678 err = _mv88e6xxx_vtu_getnext(ds, &vlan);
1679 if (err)
1680 goto unlock;
1681
1682 if (!vlan.valid)
1683 break;
1684
1685 if (vlan.vid > vid_end)
1686 break;
1687
1688 for (i = 0; i < ps->num_ports; ++i) {
1689 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
1690 continue;
1691
1692 if (vlan.data[i] ==
1693 GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1694 continue;
1695
1696 if (ps->ports[i].bridge_dev ==
1697 ps->ports[port].bridge_dev)
1698 break; /* same bridge, check next VLAN */
1699
1700 netdev_warn(ds->ports[port],
1701 "hardware VLAN %d already used by %s\n",
1702 vlan.vid,
1703 netdev_name(ps->ports[i].bridge_dev));
1704 err = -EOPNOTSUPP;
1705 goto unlock;
1706 }
1707 } while (vlan.vid < vid_end);
1708
1709unlock:
1710 mutex_unlock(&ps->smi_mutex);
1711
1712 return err;
1713}
1714
214cdb99
VD		 1715static const char * const mv88e6xxx_port_8021q_mode_names[] = {
1716 [PORT_CONTROL_2_8021Q_DISABLED] = "Disabled",
1717 [PORT_CONTROL_2_8021Q_FALLBACK] = "Fallback",
1718 [PORT_CONTROL_2_8021Q_CHECK] = "Check",
1719 [PORT_CONTROL_2_8021Q_SECURE] = "Secure",
1720};
1721
1722int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
1723 bool vlan_filtering)
1724{
1725 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1726 u16 old, new = vlan_filtering ? PORT_CONTROL_2_8021Q_SECURE :
1727 PORT_CONTROL_2_8021Q_DISABLED;
1728 int ret;
1729
1730 mutex_lock(&ps->smi_mutex);
1731
1732 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_CONTROL_2);
1733 if (ret < 0)
1734 goto unlock;
1735
1736 old = ret & PORT_CONTROL_2_8021Q_MASK;
1737
1738 ret &= ~PORT_CONTROL_2_8021Q_MASK;
1739 ret |= new & PORT_CONTROL_2_8021Q_MASK;
1740
1741 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_CONTROL_2, ret);
1742 if (ret < 0)
1743 goto unlock;
1744
1745 netdev_dbg(ds->ports[port], "802.1Q Mode: %s (was %s)\n",
1746 mv88e6xxx_port_8021q_mode_names[new],
1747 mv88e6xxx_port_8021q_mode_names[old]);
1748unlock:
1749 mutex_unlock(&ps->smi_mutex);
1750
1751 return ret;
1752}
1753
76e398a6
VD		 1754int mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
1755 const struct switchdev_obj_port_vlan *vlan,
1756 struct switchdev_trans *trans)
1757{
da9c359e
VD		 1758 int err;
1759
da9c359e
VD		 1760 /* If the requested port doesn't belong to the same bridge as the VLAN
1761 * members, do not support it (yet) and fallback to software VLAN.
1762 */
1763 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin,
1764 vlan->vid_end);
1765 if (err)
1766 return err;
1767
76e398a6
VD		 1768 /* We don't need any dynamic resource from the kernel (yet),
1769 * so skip the prepare phase.
1770 */
1771 return 0;
1772}
1773
1774static int _mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, u16 vid,
1775 bool untagged)
0d3b33e6 1776{
0d3b33e6
VD		 1777 struct mv88e6xxx_vtu_stu_entry vlan;
1778 int err;
1779
2fb5ef09 1780 err = _mv88e6xxx_vtu_get(ds, vid, &vlan, true);
0d3b33e6 1781 if (err)
76e398a6 1782 return err;
0d3b33e6 1783
0d3b33e6
VD		 1784 vlan.data[port] = untagged ?
1785 GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED :
1786 GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED;
1787
76e398a6
VD		 1788 return _mv88e6xxx_vtu_loadpurge(ds, &vlan);
1789}
1790
1791int mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
1792 const struct switchdev_obj_port_vlan *vlan,
1793 struct switchdev_trans *trans)
1794{
1795 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1796 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1797 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1798 u16 vid;
1799 int err = 0;
1800
1801 mutex_lock(&ps->smi_mutex);
1802
1803 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1804 err = _mv88e6xxx_port_vlan_add(ds, port, vid, untagged);
1805 if (err)
1806 goto unlock;
1807 }
1808
1809 /* no PVID with ranges, otherwise it's a bug */
1810 if (pvid)
db0e51af 1811 err = _mv88e6xxx_port_pvid_set(ds, port, vlan->vid_end);
0d3b33e6
VD		 1812unlock:
1813 mutex_unlock(&ps->smi_mutex);
1814
1815 return err;
1816}
1817
76e398a6 1818static int _mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, u16 vid)
7dad08d7
VD		 1819{
1820 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1821 struct mv88e6xxx_vtu_stu_entry vlan;
7dad08d7
VD		 1822 int i, err;
1823
2fb5ef09 1824 err = _mv88e6xxx_vtu_get(ds, vid, &vlan, false);
7dad08d7 1825 if (err)
76e398a6 1826 return err;
7dad08d7 1827
2fb5ef09
VD		 1828 /* Tell switchdev if this VLAN is handled in software */
1829 if (vlan.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
3c06f08b 1830 return -EOPNOTSUPP;
7dad08d7
VD		 1831
1832 vlan.data[port] = GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1833
1834 /* keep the VLAN unless all ports are excluded */
f02bdffc 1835 vlan.valid = false;
7dad08d7 1836 for (i = 0; i < ps->num_ports; ++i) {
3d131f07 1837 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
7dad08d7
VD		 1838 continue;
1839
1840 if (vlan.data[i] != GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
f02bdffc 1841 vlan.valid = true;
7dad08d7
VD		 1842 break;
1843 }
1844 }
1845
7dad08d7 1846 err = _mv88e6xxx_vtu_loadpurge(ds, &vlan);
76e398a6
VD		 1847 if (err)
1848 return err;
1849
1850 return _mv88e6xxx_atu_remove(ds, vlan.fid, port, false);
1851}
1852
1853int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
1854 const struct switchdev_obj_port_vlan *vlan)
1855{
1856 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1857 u16 pvid, vid;
1858 int err = 0;
1859
1860 mutex_lock(&ps->smi_mutex);
1861
1862 err = _mv88e6xxx_port_pvid_get(ds, port, &pvid);
7dad08d7
VD		 1863 if (err)
1864 goto unlock;
1865
76e398a6
VD		 1866 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1867 err = _mv88e6xxx_port_vlan_del(ds, port, vid);
1868 if (err)
1869 goto unlock;
1870
1871 if (vid == pvid) {
46fbe5e5 1872 err = _mv88e6xxx_port_pvid_set(ds, port, 0);
76e398a6
VD		 1873 if (err)
1874 goto unlock;
1875 }
1876 }
1877
7dad08d7
VD		 1878unlock:
1879 mutex_unlock(&ps->smi_mutex);
1880
1881 return err;
1882}
1883
c5723ac5
VD		 1884static int _mv88e6xxx_atu_mac_write(struct dsa_switch *ds,
1885 const unsigned char *addr)
defb05b9
GR		 1886{
1887 int i, ret;
1888
1889 for (i = 0; i < 3; i++) {
cca8b133
AL		 1890 ret = _mv88e6xxx_reg_write(
1891 ds, REG_GLOBAL, GLOBAL_ATU_MAC_01 + i,
1892 (addr[i * 2] << 8) | addr[i * 2 + 1]);
defb05b9
GR		 1893 if (ret < 0)
1894 return ret;
1895 }
1896
1897 return 0;
1898}
1899
c5723ac5 1900static int _mv88e6xxx_atu_mac_read(struct dsa_switch *ds, unsigned char *addr)
defb05b9
GR		 1901{
1902 int i, ret;
1903
1904 for (i = 0; i < 3; i++) {
cca8b133
AL		 1905 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL,
1906 GLOBAL_ATU_MAC_01 + i);
defb05b9
GR		 1907 if (ret < 0)
1908 return ret;
1909 addr[i * 2] = ret >> 8;
1910 addr[i * 2 + 1] = ret & 0xff;
1911 }
1912
1913 return 0;
1914}
1915
fd231c82
VD		 1916static int _mv88e6xxx_atu_load(struct dsa_switch *ds,
1917 struct mv88e6xxx_atu_entry *entry)
defb05b9 1918{
6630e236
VD		 1919 int ret;
1920
defb05b9
GR		 1921 ret = _mv88e6xxx_atu_wait(ds);
1922 if (ret < 0)
1923 return ret;
1924
fd231c82 1925 ret = _mv88e6xxx_atu_mac_write(ds, entry->mac);
defb05b9
GR		 1926 if (ret < 0)
1927 return ret;
1928
37705b73 1929 ret = _mv88e6xxx_atu_data_write(ds, entry);
fd231c82 1930 if (ret < 0)
87820510
VD		 1931 return ret;
1932
70cc99d1
VD		 1933 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_FID, entry->fid);
1934 if (ret < 0)
1935 return ret;
1936
1937 return _mv88e6xxx_atu_cmd(ds, GLOBAL_ATU_OP_LOAD_DB);
fd231c82 1938}
87820510 1939
fd231c82
VD		 1940static int _mv88e6xxx_port_fdb_load(struct dsa_switch *ds, int port,
1941 const unsigned char *addr, u16 vid,
1942 u8 state)
1943{
1944 struct mv88e6xxx_atu_entry entry = { 0 };
3285f9e8
VD		 1945 struct mv88e6xxx_vtu_stu_entry vlan;
1946 int err;
1947
2db9ce1f
VD		 1948 /* Null VLAN ID corresponds to the port private database */
1949 if (vid == 0)
1950 err = _mv88e6xxx_port_fid_get(ds, port, &vlan.fid);
1951 else
1952 err = _mv88e6xxx_vtu_get(ds, vid, &vlan, false);
3285f9e8
VD		 1953 if (err)
1954 return err;
fd231c82 1955
3285f9e8 1956 entry.fid = vlan.fid;
fd231c82
VD		 1957 entry.state = state;
1958 ether_addr_copy(entry.mac, addr);
1959 if (state != GLOBAL_ATU_DATA_STATE_UNUSED) {
1960 entry.trunk = false;
1961 entry.portv_trunkid = BIT(port);
1962 }
1963
1964 return _mv88e6xxx_atu_load(ds, &entry);
87820510
VD		 1965}
1966
146a3206
VD		 1967int mv88e6xxx_port_fdb_prepare(struct dsa_switch *ds, int port,
1968 const struct switchdev_obj_port_fdb *fdb,
1969 struct switchdev_trans *trans)
1970{
1971 /* We don't need any dynamic resource from the kernel (yet),
1972 * so skip the prepare phase.
1973 */
1974 return 0;
1975}
1976
cdf09697 1977int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
1f36faf2
VD		 1978 const struct switchdev_obj_port_fdb *fdb,
1979 struct switchdev_trans *trans)
87820510 1980{
1f36faf2 1981 int state = is_multicast_ether_addr(fdb->addr) ?
87820510
VD		 1982 GLOBAL_ATU_DATA_STATE_MC_STATIC :
1983 GLOBAL_ATU_DATA_STATE_UC_STATIC;
cdf09697 1984 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
87820510
VD		 1985 int ret;
1986
1987 mutex_lock(&ps->smi_mutex);
1f36faf2 1988 ret = _mv88e6xxx_port_fdb_load(ds, port, fdb->addr, fdb->vid, state);
87820510
VD		 1989 mutex_unlock(&ps->smi_mutex);
1990
1991 return ret;
1992}
1993
cdf09697 1994int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
8057b3e7 1995 const struct switchdev_obj_port_fdb *fdb)
87820510
VD		 1996{
1997 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
87820510
VD		 1998 int ret;
1999
2000 mutex_lock(&ps->smi_mutex);
8057b3e7 2001 ret = _mv88e6xxx_port_fdb_load(ds, port, fdb->addr, fdb->vid,
cdf09697 2002 GLOBAL_ATU_DATA_STATE_UNUSED);
87820510
VD		 2003 mutex_unlock(&ps->smi_mutex);
2004
2005 return ret;
2006}
2007
1d194046 2008static int _mv88e6xxx_atu_getnext(struct dsa_switch *ds, u16 fid,
1d194046 2009 struct mv88e6xxx_atu_entry *entry)
6630e236 2010{
1d194046
VD		 2011 struct mv88e6xxx_atu_entry next = { 0 };
2012 int ret;
2013
2014 next.fid = fid;
defb05b9 2015
cdf09697
DM		 2016 ret = _mv88e6xxx_atu_wait(ds);
2017 if (ret < 0)
2018 return ret;
6630e236 2019
70cc99d1
VD		 2020 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_FID, fid);
2021 if (ret < 0)
2022 return ret;
2023
2024 ret = _mv88e6xxx_atu_cmd(ds, GLOBAL_ATU_OP_GET_NEXT_DB);
1d194046
VD		 2025 if (ret < 0)
2026 return ret;
6630e236 2027
1d194046
VD		 2028 ret = _mv88e6xxx_atu_mac_read(ds, next.mac);
2029 if (ret < 0)
2030 return ret;
6630e236 2031
1d194046 2032 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_ATU_DATA);
cdf09697
DM		 2033 if (ret < 0)
2034 return ret;
6630e236 2035
1d194046
VD		 2036 next.state = ret & GLOBAL_ATU_DATA_STATE_MASK;
2037 if (next.state != GLOBAL_ATU_DATA_STATE_UNUSED) {
2038 unsigned int mask, shift;
2039
2040 if (ret & GLOBAL_ATU_DATA_TRUNK) {
2041 next.trunk = true;
2042 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
2043 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
2044 } else {
2045 next.trunk = false;
2046 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
2047 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
2048 }
2049
2050 next.portv_trunkid = (ret & mask) >> shift;
2051 }
cdf09697 2052
1d194046 2053 *entry = next;
cdf09697
DM		 2054 return 0;
2055}
2056
74b6ba0d
VD		 2057static int _mv88e6xxx_port_fdb_dump_one(struct dsa_switch *ds, u16 fid, u16 vid,
2058 int port,
2059 struct switchdev_obj_port_fdb *fdb,
2060 int (*cb)(struct switchdev_obj *obj))
2061{
2062 struct mv88e6xxx_atu_entry addr = {
2063 .mac = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff },
2064 };
2065 int err;
2066
2067 err = _mv88e6xxx_atu_mac_write(ds, addr.mac);
2068 if (err)
2069 return err;
2070
2071 do {
2072 err = _mv88e6xxx_atu_getnext(ds, fid, &addr);
2073 if (err)
2074 break;
2075
2076 if (addr.state == GLOBAL_ATU_DATA_STATE_UNUSED)
2077 break;
2078
2079 if (!addr.trunk && addr.portv_trunkid & BIT(port)) {
2080 bool is_static = addr.state ==
2081 (is_multicast_ether_addr(addr.mac) ?
2082 GLOBAL_ATU_DATA_STATE_MC_STATIC :
2083 GLOBAL_ATU_DATA_STATE_UC_STATIC);
2084
2085 fdb->vid = vid;
2086 ether_addr_copy(fdb->addr, addr.mac);
2087 fdb->ndm_state = is_static ? NUD_NOARP : NUD_REACHABLE;
2088
2089 err = cb(&fdb->obj);
2090 if (err)
2091 break;
2092 }
2093 } while (!is_broadcast_ether_addr(addr.mac));
2094
2095 return err;
2096}
2097
f33475bd
VD		 2098int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
2099 struct switchdev_obj_port_fdb *fdb,
2100 int (*cb)(struct switchdev_obj *obj))
2101{
2102 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2103 struct mv88e6xxx_vtu_stu_entry vlan = {
2104 .vid = GLOBAL_VTU_VID_MASK, /* all ones */
2105 };
2db9ce1f 2106 u16 fid;
f33475bd
VD		 2107 int err;
2108
2109 mutex_lock(&ps->smi_mutex);
2110
2db9ce1f
VD		 2111 /* Dump port's default Filtering Information Database (VLAN ID 0) */
2112 err = _mv88e6xxx_port_fid_get(ds, port, &fid);
2113 if (err)
2114 goto unlock;
2115
2116 err = _mv88e6xxx_port_fdb_dump_one(ds, fid, 0, port, fdb, cb);
2117 if (err)
2118 goto unlock;
2119
74b6ba0d 2120 /* Dump VLANs' Filtering Information Databases */
f33475bd
VD		 2121 err = _mv88e6xxx_vtu_vid_write(ds, vlan.vid);
2122 if (err)
2123 goto unlock;
2124
2125 do {
f33475bd
VD		 2126 err = _mv88e6xxx_vtu_getnext(ds, &vlan);
2127 if (err)
74b6ba0d 2128 break;
f33475bd
VD		 2129
2130 if (!vlan.valid)
2131 break;
2132
74b6ba0d
VD		 2133 err = _mv88e6xxx_port_fdb_dump_one(ds, vlan.fid, vlan.vid, port,
2134 fdb, cb);
f33475bd 2135 if (err)
74b6ba0d 2136 break;
f33475bd
VD		 2137 } while (vlan.vid < GLOBAL_VTU_VID_MASK);
2138
2139unlock:
2140 mutex_unlock(&ps->smi_mutex);
2141
2142 return err;
2143}
2144
a6692754
VD		 2145int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
2146 struct net_device *bridge)
e79a8bcb 2147{
a6692754 2148 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
466dfa07
VD		 2149 u16 fid;
2150 int i, err;
2151
2152 mutex_lock(&ps->smi_mutex);
2153
2154 /* Get or create the bridge FID and assign it to the port */
2155 for (i = 0; i < ps->num_ports; ++i)
2156 if (ps->ports[i].bridge_dev == bridge)
2157 break;
2158
2159 if (i < ps->num_ports)
2160 err = _mv88e6xxx_port_fid_get(ds, i, &fid);
2161 else
2162 err = _mv88e6xxx_fid_new(ds, &fid);
2163 if (err)
2164 goto unlock;
2165
2166 err = _mv88e6xxx_port_fid_set(ds, port, fid);
2167 if (err)
2168 goto unlock;
a6692754 2169
b7666efe 2170 /* Assign the bridge and remap each port's VLANTable */
a6692754 2171 ps->ports[port].bridge_dev = bridge;
b7666efe
VD		 2172
2173 for (i = 0; i < ps->num_ports; ++i) {
2174 if (ps->ports[i].bridge_dev == bridge) {
2175 err = _mv88e6xxx_port_based_vlan_map(ds, i);
2176 if (err)
2177 break;
2178 }
2179 }
2180
466dfa07
VD		 2181unlock:
2182 mutex_unlock(&ps->smi_mutex);
a6692754 2183
466dfa07 2184 return err;
e79a8bcb
VD		 2185}
2186
a6692754 2187int mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port)
66d9cd0f 2188{
a6692754 2189 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
b7666efe 2190 struct net_device *bridge = ps->ports[port].bridge_dev;
466dfa07 2191 u16 fid;
b7666efe 2192 int i, err;
466dfa07
VD		 2193
2194 mutex_lock(&ps->smi_mutex);
2195
2196 /* Give the port a fresh Filtering Information Database */
2197 err = _mv88e6xxx_fid_new(ds, &fid);
2198 if (err)
2199 goto unlock;
2200
2201 err = _mv88e6xxx_port_fid_set(ds, port, fid);
2202 if (err)
2203 goto unlock;
a6692754 2204
b7666efe 2205 /* Unassign the bridge and remap each port's VLANTable */
a6692754 2206 ps->ports[port].bridge_dev = NULL;
b7666efe
VD		 2207
2208 for (i = 0; i < ps->num_ports; ++i) {
2209 if (i == port || ps->ports[i].bridge_dev == bridge) {
2210 err = _mv88e6xxx_port_based_vlan_map(ds, i);
2211 if (err)
2212 break;
2213 }
2214 }
2215
466dfa07
VD		 2216unlock:
2217 mutex_unlock(&ps->smi_mutex);
a6692754 2218
466dfa07 2219 return err;
66d9cd0f
VD		 2220}
2221
facd95b2
GR		 2222static void mv88e6xxx_bridge_work(struct work_struct *work)
2223{
2224 struct mv88e6xxx_priv_state *ps;
2225 struct dsa_switch *ds;
2226 int port;
2227
2228 ps = container_of(work, struct mv88e6xxx_priv_state, bridge_work);
2229 ds = ((struct dsa_switch *)ps) - 1;
2230
2231 while (ps->port_state_update_mask) {
2232 port = __ffs(ps->port_state_update_mask);
2233 clear_bit(port, &ps->port_state_update_mask);
d715fa64 2234 mv88e6xxx_set_port_state(ds, port, ps->ports[port].state);
facd95b2
GR		 2235 }
2236}
2237
dbde9e66 2238static int mv88e6xxx_setup_port(struct dsa_switch *ds, int port)
d827e88a
GR		 2239{
2240 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
f02bdffc 2241 int ret;
54d792f2 2242 u16 reg;
d827e88a
GR		 2243
2244 mutex_lock(&ps->smi_mutex);
2245
54d792f2
AL		 2246 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2247 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2248 mv88e6xxx_6185_family(ds) || mv88e6xxx_6095_family(ds) ||
7c3d0d67 2249 mv88e6xxx_6065_family(ds) || mv88e6xxx_6320_family(ds)) {
54d792f2
AL		 2250 /* MAC Forcing register: don't force link, speed,
2251 * duplex or flow control state to any particular
2252 * values on physical ports, but force the CPU port
2253 * and all DSA ports to their maximum bandwidth and
2254 * full duplex.
2255 */
2256 reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_PCS_CTRL);
60045cbf 2257 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
53adc9e8 2258 reg &= ~PORT_PCS_CTRL_UNFORCED;
54d792f2
AL		 2259 reg |= PORT_PCS_CTRL_FORCE_LINK |
2260 PORT_PCS_CTRL_LINK_UP |
2261 PORT_PCS_CTRL_DUPLEX_FULL |
2262 PORT_PCS_CTRL_FORCE_DUPLEX;
2263 if (mv88e6xxx_6065_family(ds))
2264 reg |= PORT_PCS_CTRL_100;
2265 else
2266 reg |= PORT_PCS_CTRL_1000;
2267 } else {
2268 reg |= PORT_PCS_CTRL_UNFORCED;
2269 }
2270
2271 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2272 PORT_PCS_CTRL, reg);
2273 if (ret)
2274 goto abort;
2275 }
2276
2277 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
2278 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
2279 * tunneling, determine priority by looking at 802.1p and IP
2280 * priority fields (IP prio has precedence), and set STP state
2281 * to Forwarding.
2282 *
2283 * If this is the CPU link, use DSA or EDSA tagging depending
2284 * on which tagging mode was configured.
2285 *
2286 * If this is a link to another switch, use DSA tagging mode.
2287 *
2288 * If this is the upstream port for this switch, enable
2289 * forwarding of unknown unicasts and multicasts.
2290 */
2291 reg = 0;
2292 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2293 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2294 mv88e6xxx_6095_family(ds) || mv88e6xxx_6065_family(ds) ||
7c3d0d67 2295 mv88e6xxx_6185_family(ds) || mv88e6xxx_6320_family(ds))
54d792f2
AL		 2296 reg = PORT_CONTROL_IGMP_MLD_SNOOP |
2297 PORT_CONTROL_USE_TAG | PORT_CONTROL_USE_IP |
2298 PORT_CONTROL_STATE_FORWARDING;
2299 if (dsa_is_cpu_port(ds, port)) {
2300 if (mv88e6xxx_6095_family(ds) || mv88e6xxx_6185_family(ds))
2301 reg |= PORT_CONTROL_DSA_TAG;
2302 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
7c3d0d67
AK		 2303 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2304 mv88e6xxx_6320_family(ds)) {
54d792f2
AL		 2305 if (ds->dst->tag_protocol == DSA_TAG_PROTO_EDSA)
2306 reg |= PORT_CONTROL_FRAME_ETHER_TYPE_DSA;
2307 else
2308 reg |= PORT_CONTROL_FRAME_MODE_DSA;
c047a1f9
AL		 2309 reg |= PORT_CONTROL_FORWARD_UNKNOWN |
2310 PORT_CONTROL_FORWARD_UNKNOWN_MC;
54d792f2
AL		 2311 }
2312
2313 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2314 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2315 mv88e6xxx_6095_family(ds) || mv88e6xxx_6065_family(ds) ||
7c3d0d67 2316 mv88e6xxx_6185_family(ds) || mv88e6xxx_6320_family(ds)) {
54d792f2
AL		 2317 if (ds->dst->tag_protocol == DSA_TAG_PROTO_EDSA)
2318 reg |= PORT_CONTROL_EGRESS_ADD_TAG;
2319 }
2320 }
6083ce71
AL		 2321 if (dsa_is_dsa_port(ds, port)) {
2322 if (mv88e6xxx_6095_family(ds) || mv88e6xxx_6185_family(ds))
2323 reg |= PORT_CONTROL_DSA_TAG;
2324 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2325 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2326 mv88e6xxx_6320_family(ds)) {
54d792f2 2327 reg |= PORT_CONTROL_FRAME_MODE_DSA;
6083ce71
AL		 2328 }
2329
54d792f2
AL		 2330 if (port == dsa_upstream_port(ds))
2331 reg |= PORT_CONTROL_FORWARD_UNKNOWN |
2332 PORT_CONTROL_FORWARD_UNKNOWN_MC;
2333 }
2334 if (reg) {
2335 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2336 PORT_CONTROL, reg);
2337 if (ret)
2338 goto abort;
2339 }
2340
8efdda4a 2341 /* Port Control 2: don't force a good FCS, set the maximum frame size to
46fbe5e5 2342 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
8efdda4a
VD		 2343 * untagged frames on this port, do a destination address lookup on all
2344 * received packets as usual, disable ARP mirroring and don't send a
2345 * copy of all transmitted/received frames on this port to the CPU.
54d792f2
AL		 2346 */
2347 reg = 0;
2348 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2349 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
7c3d0d67 2350 mv88e6xxx_6095_family(ds) || mv88e6xxx_6320_family(ds))
54d792f2
AL		 2351 reg = PORT_CONTROL_2_MAP_DA;
2352
2353 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
7c3d0d67 2354 mv88e6xxx_6165_family(ds) || mv88e6xxx_6320_family(ds))
54d792f2
AL		 2355 reg |= PORT_CONTROL_2_JUMBO_10240;
2356
2357 if (mv88e6xxx_6095_family(ds) || mv88e6xxx_6185_family(ds)) {
2358 /* Set the upstream port this port should use */
2359 reg |= dsa_upstream_port(ds);
2360 /* enable forwarding of unknown multicast addresses to
2361 * the upstream port
2362 */
2363 if (port == dsa_upstream_port(ds))
2364 reg |= PORT_CONTROL_2_FORWARD_UNKNOWN;
2365 }
2366
46fbe5e5 2367 reg |= PORT_CONTROL_2_8021Q_DISABLED;
8efdda4a 2368
54d792f2
AL		 2369 if (reg) {
2370 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2371 PORT_CONTROL_2, reg);
2372 if (ret)
2373 goto abort;
2374 }
2375
2376 /* Port Association Vector: when learning source addresses
2377 * of packets, add the address to the address database using
2378 * a port bitmap that has only the bit for this port set and
2379 * the other bits clear.
2380 */
4c7ea3c0
AL		 2381 reg = 1 << port;
2382 /* Disable learning for DSA and CPU ports */
2383 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
2384 reg = PORT_ASSOC_VECTOR_LOCKED_PORT;
2385
2386 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_ASSOC_VECTOR, reg);
54d792f2
AL		 2387 if (ret)
2388 goto abort;
2389
2390 /* Egress rate control 2: disable egress rate control. */
2391 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_RATE_CONTROL_2,
2392 0x0000);
2393 if (ret)
2394 goto abort;
2395
2396 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
7c3d0d67
AK		 2397 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2398 mv88e6xxx_6320_family(ds)) {
54d792f2
AL		 2399 /* Do not limit the period of time that this port can
2400 * be paused for by the remote end or the period of
2401 * time that this port can pause the remote end.
2402 */
2403 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2404 PORT_PAUSE_CTRL, 0x0000);
2405 if (ret)
2406 goto abort;
2407
2408 /* Port ATU control: disable limiting the number of
2409 * address database entries that this port is allowed
2410 * to use.
2411 */
2412 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2413 PORT_ATU_CONTROL, 0x0000);
2414 /* Priority Override: disable DA, SA and VTU priority
2415 * override.
2416 */
2417 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2418 PORT_PRI_OVERRIDE, 0x0000);
2419 if (ret)
2420 goto abort;
2421
2422 /* Port Ethertype: use the Ethertype DSA Ethertype
2423 * value.
2424 */
2425 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2426 PORT_ETH_TYPE, ETH_P_EDSA);
2427 if (ret)
2428 goto abort;
2429 /* Tag Remap: use an identity 802.1p prio -> switch
2430 * prio mapping.
2431 */
2432 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2433 PORT_TAG_REGMAP_0123, 0x3210);
2434 if (ret)
2435 goto abort;
2436
2437 /* Tag Remap 2: use an identity 802.1p prio -> switch
2438 * prio mapping.
2439 */
2440 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2441 PORT_TAG_REGMAP_4567, 0x7654);
2442 if (ret)
2443 goto abort;
2444 }
2445
2446 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2447 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
7c3d0d67
AK		 2448 mv88e6xxx_6185_family(ds) || mv88e6xxx_6095_family(ds) ||
2449 mv88e6xxx_6320_family(ds)) {
54d792f2
AL		 2450 /* Rate Control: disable ingress rate limiting. */
2451 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2452 PORT_RATE_CONTROL, 0x0001);
2453 if (ret)
2454 goto abort;
2455 }
2456
366f0a0f
GR		 2457 /* Port Control 1: disable trunking, disable sending
2458 * learning messages to this port.
d827e88a 2459 */
614f03fc 2460 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_CONTROL_1, 0x0000);
d827e88a
GR		 2461 if (ret)
2462 goto abort;
2463
2db9ce1f 2464 /* Port based VLAN map: give each port its own address
b7666efe
VD		 2465 * database, and allow bidirectional communication between the
2466 * CPU and DSA port(s), and the other ports.
d827e88a 2467 */
2db9ce1f
VD		 2468 ret = _mv88e6xxx_port_fid_set(ds, port, port + 1);
2469 if (ret)
2470 goto abort;
2471
b7666efe 2472 ret = _mv88e6xxx_port_based_vlan_map(ds, port);
d827e88a
GR		 2473 if (ret)
2474 goto abort;
2475
2476 /* Default VLAN ID and priority: don't set a default VLAN
2477 * ID, and set the default packet priority to zero.
2478 */
47cf1e65
VD		 2479 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_DEFAULT_VLAN,
2480 0x0000);
d827e88a
GR		 2481abort:
2482 mutex_unlock(&ps->smi_mutex);
2483 return ret;
2484}
2485
dbde9e66
AL		 2486int mv88e6xxx_setup_ports(struct dsa_switch *ds)
2487{
2488 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2489 int ret;
2490 int i;
2491
2492 for (i = 0; i < ps->num_ports; i++) {
2493 ret = mv88e6xxx_setup_port(ds, i);
2494 if (ret < 0)
2495 return ret;
2496 }
2497 return 0;
2498}
2499
acdaffcc
GR		 2500int mv88e6xxx_setup_common(struct dsa_switch *ds)
2501{
2502 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2503
2504 mutex_init(&ps->smi_mutex);
acdaffcc 2505
cca8b133 2506 ps->id = REG_READ(REG_PORT(0), PORT_SWITCH_ID) & 0xfff0;
a8f064c6 2507
facd95b2
GR		 2508 INIT_WORK(&ps->bridge_work, mv88e6xxx_bridge_work);
2509
acdaffcc
GR		 2510 return 0;
2511}
2512
54d792f2
AL		 2513int mv88e6xxx_setup_global(struct dsa_switch *ds)
2514{
2515 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
24751e29 2516 int ret;
54d792f2
AL		 2517 int i;
2518
2519 /* Set the default address aging time to 5 minutes, and
2520 * enable address learn messages to be sent to all message
2521 * ports.
2522 */
2523 REG_WRITE(REG_GLOBAL, GLOBAL_ATU_CONTROL,
2524 0x0140 | GLOBAL_ATU_CONTROL_LEARN2ALL);
2525
2526 /* Configure the IP ToS mapping registers. */
2527 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_0, 0x0000);
2528 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_1, 0x0000);
2529 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_2, 0x5555);
2530 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_3, 0x5555);
2531 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_4, 0xaaaa);
2532 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_5, 0xaaaa);
2533 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_6, 0xffff);
2534 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_7, 0xffff);
2535
2536 /* Configure the IEEE 802.1p priority mapping register. */
2537 REG_WRITE(REG_GLOBAL, GLOBAL_IEEE_PRI, 0xfa41);
2538
2539 /* Send all frames with destination addresses matching
2540 * 01:80:c2:00:00:0x to the CPU port.
2541 */
2542 REG_WRITE(REG_GLOBAL2, GLOBAL2_MGMT_EN_0X, 0xffff);
2543
2544 /* Ignore removed tag data on doubly tagged packets, disable
2545 * flow control messages, force flow control priority to the
2546 * highest, and send all special multicast frames to the CPU
2547 * port at the highest priority.
2548 */
2549 REG_WRITE(REG_GLOBAL2, GLOBAL2_SWITCH_MGMT,
2550 0x7 | GLOBAL2_SWITCH_MGMT_RSVD2CPU | 0x70 |
2551 GLOBAL2_SWITCH_MGMT_FORCE_FLOW_CTRL_PRI);
2552
2553 /* Program the DSA routing table. */
2554 for (i = 0; i < 32; i++) {
2555 int nexthop = 0x1f;
2556
2557 if (ds->pd->rtable &&
2558 i != ds->index && i < ds->dst->pd->nr_chips)
2559 nexthop = ds->pd->rtable[i] & 0x1f;
2560
2561 REG_WRITE(REG_GLOBAL2, GLOBAL2_DEVICE_MAPPING,
2562 GLOBAL2_DEVICE_MAPPING_UPDATE |
2563 (i << GLOBAL2_DEVICE_MAPPING_TARGET_SHIFT) |
2564 nexthop);
2565 }
2566
2567 /* Clear all trunk masks. */
2568 for (i = 0; i < 8; i++)
2569 REG_WRITE(REG_GLOBAL2, GLOBAL2_TRUNK_MASK,
2570 0x8000 | (i << GLOBAL2_TRUNK_MASK_NUM_SHIFT) |
2571 ((1 << ps->num_ports) - 1));
2572
2573 /* Clear all trunk mappings. */
2574 for (i = 0; i < 16; i++)
2575 REG_WRITE(REG_GLOBAL2, GLOBAL2_TRUNK_MAPPING,
2576 GLOBAL2_TRUNK_MAPPING_UPDATE |
2577 (i << GLOBAL2_TRUNK_MAPPING_ID_SHIFT));
2578
2579 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
7c3d0d67
AK		 2580 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2581 mv88e6xxx_6320_family(ds)) {
54d792f2
AL		 2582 /* Send all frames with destination addresses matching
2583 * 01:80:c2:00:00:2x to the CPU port.
2584 */
2585 REG_WRITE(REG_GLOBAL2, GLOBAL2_MGMT_EN_2X, 0xffff);
2586
2587 /* Initialise cross-chip port VLAN table to reset
2588 * defaults.
2589 */
2590 REG_WRITE(REG_GLOBAL2, GLOBAL2_PVT_ADDR, 0x9000);
2591
2592 /* Clear the priority override table. */
2593 for (i = 0; i < 16; i++)
2594 REG_WRITE(REG_GLOBAL2, GLOBAL2_PRIO_OVERRIDE,
2595 0x8000 | (i << 8));
2596 }
2597
2598 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2599 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
7c3d0d67
AK		 2600 mv88e6xxx_6185_family(ds) || mv88e6xxx_6095_family(ds) ||
2601 mv88e6xxx_6320_family(ds)) {
54d792f2
AL		 2602 /* Disable ingress rate limiting by resetting all
2603 * ingress rate limit registers to their initial
2604 * state.
2605 */
2606 for (i = 0; i < ps->num_ports; i++)
2607 REG_WRITE(REG_GLOBAL2, GLOBAL2_INGRESS_OP,
2608 0x9000 | (i << 8));
2609 }
2610
db687a56
AL		 2611 /* Clear the statistics counters for all ports */
2612 REG_WRITE(REG_GLOBAL, GLOBAL_STATS_OP, GLOBAL_STATS_OP_FLUSH_ALL);
2613
2614 /* Wait for the flush to complete. */
24751e29
VD		 2615 mutex_lock(&ps->smi_mutex);
2616 ret = _mv88e6xxx_stats_wait(ds);
6b17e864
VD		 2617 if (ret < 0)
2618 goto unlock;
2619
c161d0a5
VD		 2620 /* Clear all ATU entries */
2621 ret = _mv88e6xxx_atu_flush(ds, 0, true);
2622 if (ret < 0)
2623 goto unlock;
2624
6b17e864
VD		 2625 /* Clear all the VTU and STU entries */
2626 ret = _mv88e6xxx_vtu_stu_flush(ds);
2627unlock:
24751e29 2628 mutex_unlock(&ps->smi_mutex);
db687a56 2629
24751e29 2630 return ret;
54d792f2
AL		 2631}
2632
143a8307
AL		 2633int mv88e6xxx_switch_reset(struct dsa_switch *ds, bool ppu_active)
2634{
2635 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2636 u16 is_reset = (ppu_active ? 0x8800 : 0xc800);
c8c1b39a 2637 struct gpio_desc *gpiod = ds->pd->reset;
143a8307
AL		 2638 unsigned long timeout;
2639 int ret;
2640 int i;
2641
2642 /* Set all ports to the disabled state. */
2643 for (i = 0; i < ps->num_ports; i++) {
cca8b133
AL		 2644 ret = REG_READ(REG_PORT(i), PORT_CONTROL);
2645 REG_WRITE(REG_PORT(i), PORT_CONTROL, ret & 0xfffc);
143a8307
AL		 2646 }
2647
2648 /* Wait for transmit queues to drain. */
2649 usleep_range(2000, 4000);
2650
c8c1b39a
AL		 2651 /* If there is a gpio connected to the reset pin, toggle it */
2652 if (gpiod) {
2653 gpiod_set_value_cansleep(gpiod, 1);
2654 usleep_range(10000, 20000);
2655 gpiod_set_value_cansleep(gpiod, 0);
2656 usleep_range(10000, 20000);
2657 }
2658
143a8307
AL		 2659 /* Reset the switch. Keep the PPU active if requested. The PPU
2660 * needs to be active to support indirect phy register access
2661 * through global registers 0x18 and 0x19.
2662 */
2663 if (ppu_active)
2664 REG_WRITE(REG_GLOBAL, 0x04, 0xc000);
2665 else
2666 REG_WRITE(REG_GLOBAL, 0x04, 0xc400);
2667
2668 /* Wait up to one second for reset to complete. */
2669 timeout = jiffies + 1 * HZ;
2670 while (time_before(jiffies, timeout)) {
2671 ret = REG_READ(REG_GLOBAL, 0x00);
2672 if ((ret & is_reset) == is_reset)
2673 break;
2674 usleep_range(1000, 2000);
2675 }
2676 if (time_after(jiffies, timeout))
2677 return -ETIMEDOUT;
2678
2679 return 0;
2680}
2681
49143585
AL		 2682int mv88e6xxx_phy_page_read(struct dsa_switch *ds, int port, int page, int reg)
2683{
2684 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2685 int ret;
2686
3898c148 2687 mutex_lock(&ps->smi_mutex);
fd3a0ee4 2688 ret = _mv88e6xxx_phy_write_indirect(ds, port, 0x16, page);
49143585
AL		 2689 if (ret < 0)
2690 goto error;
fd3a0ee4 2691 ret = _mv88e6xxx_phy_read_indirect(ds, port, reg);
49143585 2692error:
fd3a0ee4 2693 _mv88e6xxx_phy_write_indirect(ds, port, 0x16, 0x0);
3898c148 2694 mutex_unlock(&ps->smi_mutex);
49143585
AL		 2695 return ret;
2696}
2697
2698int mv88e6xxx_phy_page_write(struct dsa_switch *ds, int port, int page,
2699 int reg, int val)
2700{
2701 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2702 int ret;
2703
3898c148 2704 mutex_lock(&ps->smi_mutex);
fd3a0ee4 2705 ret = _mv88e6xxx_phy_write_indirect(ds, port, 0x16, page);
49143585
AL		 2706 if (ret < 0)
2707 goto error;
2708
fd3a0ee4 2709 ret = _mv88e6xxx_phy_write_indirect(ds, port, reg, val);
49143585 2710error:
fd3a0ee4 2711 _mv88e6xxx_phy_write_indirect(ds, port, 0x16, 0x0);
3898c148 2712 mutex_unlock(&ps->smi_mutex);
fd3a0ee4
AL		 2713 return ret;
2714}
2715
2716static int mv88e6xxx_port_to_phy_addr(struct dsa_switch *ds, int port)
2717{
2718 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2719
2720 if (port >= 0 && port < ps->num_ports)
2721 return port;
2722 return -EINVAL;
2723}
2724
2725int
2726mv88e6xxx_phy_read(struct dsa_switch *ds, int port, int regnum)
2727{
2728 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2729 int addr = mv88e6xxx_port_to_phy_addr(ds, port);
2730 int ret;
2731
2732 if (addr < 0)
2733 return addr;
2734
3898c148 2735 mutex_lock(&ps->smi_mutex);
fd3a0ee4 2736 ret = _mv88e6xxx_phy_read(ds, addr, regnum);
3898c148 2737 mutex_unlock(&ps->smi_mutex);
fd3a0ee4
AL		 2738 return ret;
2739}
2740
2741int
2742mv88e6xxx_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val)
2743{
2744 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2745 int addr = mv88e6xxx_port_to_phy_addr(ds, port);
2746 int ret;
2747
2748 if (addr < 0)
2749 return addr;
2750
3898c148 2751 mutex_lock(&ps->smi_mutex);
fd3a0ee4 2752 ret = _mv88e6xxx_phy_write(ds, addr, regnum, val);
3898c148 2753 mutex_unlock(&ps->smi_mutex);
fd3a0ee4
AL		 2754 return ret;
2755}
2756
2757int
2758mv88e6xxx_phy_read_indirect(struct dsa_switch *ds, int port, int regnum)
2759{
2760 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2761 int addr = mv88e6xxx_port_to_phy_addr(ds, port);
2762 int ret;
2763
2764 if (addr < 0)
2765 return addr;
2766
3898c148 2767 mutex_lock(&ps->smi_mutex);
fd3a0ee4 2768 ret = _mv88e6xxx_phy_read_indirect(ds, addr, regnum);
3898c148 2769 mutex_unlock(&ps->smi_mutex);
fd3a0ee4
AL		 2770 return ret;
2771}
2772
2773int
2774mv88e6xxx_phy_write_indirect(struct dsa_switch *ds, int port, int regnum,
2775 u16 val)
2776{
2777 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2778 int addr = mv88e6xxx_port_to_phy_addr(ds, port);
2779 int ret;
2780
2781 if (addr < 0)
2782 return addr;
2783
3898c148 2784 mutex_lock(&ps->smi_mutex);
fd3a0ee4 2785 ret = _mv88e6xxx_phy_write_indirect(ds, addr, regnum, val);
3898c148 2786 mutex_unlock(&ps->smi_mutex);
49143585
AL		 2787 return ret;
2788}
2789
c22995c5
GR		 2790#ifdef CONFIG_NET_DSA_HWMON
2791
2792static int mv88e61xx_get_temp(struct dsa_switch *ds, int *temp)
2793{
2794 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2795 int ret;
2796 int val;
2797
2798 *temp = 0;
2799
2800 mutex_lock(&ps->smi_mutex);
2801
2802 ret = _mv88e6xxx_phy_write(ds, 0x0, 0x16, 0x6);
2803 if (ret < 0)
2804 goto error;
2805
2806 /* Enable temperature sensor */
2807 ret = _mv88e6xxx_phy_read(ds, 0x0, 0x1a);
2808 if (ret < 0)
2809 goto error;
2810
2811 ret = _mv88e6xxx_phy_write(ds, 0x0, 0x1a, ret | (1 << 5));
2812 if (ret < 0)
2813 goto error;
2814
2815 /* Wait for temperature to stabilize */
2816 usleep_range(10000, 12000);
2817
2818 val = _mv88e6xxx_phy_read(ds, 0x0, 0x1a);
2819 if (val < 0) {
2820 ret = val;
2821 goto error;
2822 }
2823
2824 /* Disable temperature sensor */
2825 ret = _mv88e6xxx_phy_write(ds, 0x0, 0x1a, ret & ~(1 << 5));
2826 if (ret < 0)
2827 goto error;
2828
2829 *temp = ((val & 0x1f) - 5) * 5;
2830
2831error:
2832 _mv88e6xxx_phy_write(ds, 0x0, 0x16, 0x0);
2833 mutex_unlock(&ps->smi_mutex);
2834 return ret;
2835}
2836
2837static int mv88e63xx_get_temp(struct dsa_switch *ds, int *temp)
2838{
2839 int phy = mv88e6xxx_6320_family(ds) ? 3 : 0;
2840 int ret;
2841
2842 *temp = 0;
2843
2844 ret = mv88e6xxx_phy_page_read(ds, phy, 6, 27);
2845 if (ret < 0)
2846 return ret;
2847
2848 *temp = (ret & 0xff) - 25;
2849
2850 return 0;
2851}
2852
2853int mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp)
2854{
2855 if (mv88e6xxx_6320_family(ds) || mv88e6xxx_6352_family(ds))
2856 return mv88e63xx_get_temp(ds, temp);
2857
2858 return mv88e61xx_get_temp(ds, temp);
2859}
2860
2861int mv88e6xxx_get_temp_limit(struct dsa_switch *ds, int *temp)
2862{
2863 int phy = mv88e6xxx_6320_family(ds) ? 3 : 0;
2864 int ret;
2865
2866 if (!mv88e6xxx_6320_family(ds) && !mv88e6xxx_6352_family(ds))
2867 return -EOPNOTSUPP;
2868
2869 *temp = 0;
2870
2871 ret = mv88e6xxx_phy_page_read(ds, phy, 6, 26);
2872 if (ret < 0)
2873 return ret;
2874
2875 *temp = (((ret >> 8) & 0x1f) * 5) - 25;
2876
2877 return 0;
2878}
2879
2880int mv88e6xxx_set_temp_limit(struct dsa_switch *ds, int temp)
2881{
2882 int phy = mv88e6xxx_6320_family(ds) ? 3 : 0;
2883 int ret;
2884
2885 if (!mv88e6xxx_6320_family(ds) && !mv88e6xxx_6352_family(ds))
2886 return -EOPNOTSUPP;
2887
2888 ret = mv88e6xxx_phy_page_read(ds, phy, 6, 26);
2889 if (ret < 0)
2890 return ret;
2891 temp = clamp_val(DIV_ROUND_CLOSEST(temp, 5) + 5, 0, 0x1f);
2892 return mv88e6xxx_phy_page_write(ds, phy, 6, 26,
2893 (ret & 0xe0ff) | (temp << 8));
2894}
2895
2896int mv88e6xxx_get_temp_alarm(struct dsa_switch *ds, bool *alarm)
2897{
2898 int phy = mv88e6xxx_6320_family(ds) ? 3 : 0;
2899 int ret;
2900
2901 if (!mv88e6xxx_6320_family(ds) && !mv88e6xxx_6352_family(ds))
2902 return -EOPNOTSUPP;
2903
2904 *alarm = false;
2905
2906 ret = mv88e6xxx_phy_page_read(ds, phy, 6, 26);
2907 if (ret < 0)
2908 return ret;
2909
2910 *alarm = !!(ret & 0x40);
2911
2912 return 0;
2913}
2914#endif /* CONFIG_NET_DSA_HWMON */
2915
b9b37713
VD		 2916char *mv88e6xxx_lookup_name(struct device *host_dev, int sw_addr,
2917 const struct mv88e6xxx_switch_id *table,
2918 unsigned int num)
2919{
2920 struct mii_bus *bus = dsa_host_dev_to_mii_bus(host_dev);
2921 int i, ret;
2922
2923 if (!bus)
2924 return NULL;
2925
2926 ret = __mv88e6xxx_reg_read(bus, sw_addr, REG_PORT(0), PORT_SWITCH_ID);
2927 if (ret < 0)
2928 return NULL;
2929
2930 /* Look up the exact switch ID */
2931 for (i = 0; i < num; ++i)
2932 if (table[i].id == ret)
2933 return table[i].name;
2934
2935 /* Look up only the product number */
2936 for (i = 0; i < num; ++i) {
2937 if (table[i].id == (ret & PORT_SWITCH_ID_PROD_NUM_MASK)) {
2938 dev_warn(host_dev, "unknown revision %d, using base switch 0x%x\n",
2939 ret & PORT_SWITCH_ID_REV_MASK,
2940 ret & PORT_SWITCH_ID_PROD_NUM_MASK);
2941 return table[i].name;
2942 }
2943 }
2944
2945 return NULL;
2946}
2947
98e67308
BH		 2948static int __init mv88e6xxx_init(void)
2949{
2950#if IS_ENABLED(CONFIG_NET_DSA_MV88E6131)
2951 register_switch_driver(&mv88e6131_switch_driver);
2952#endif
2953#if IS_ENABLED(CONFIG_NET_DSA_MV88E6123_61_65)
2954 register_switch_driver(&mv88e6123_61_65_switch_driver);
42f27253 2955#endif
3ad50cca
GR		 2956#if IS_ENABLED(CONFIG_NET_DSA_MV88E6352)
2957 register_switch_driver(&mv88e6352_switch_driver);
2958#endif
42f27253
AL		 2959#if IS_ENABLED(CONFIG_NET_DSA_MV88E6171)
2960 register_switch_driver(&mv88e6171_switch_driver);
98e67308
BH		 2961#endif
2962 return 0;
2963}
2964module_init(mv88e6xxx_init);
2965
2966static void __exit mv88e6xxx_cleanup(void)
2967{
42f27253
AL		 2968#if IS_ENABLED(CONFIG_NET_DSA_MV88E6171)
2969 unregister_switch_driver(&mv88e6171_switch_driver);
2970#endif
4212b543
VD		 2971#if IS_ENABLED(CONFIG_NET_DSA_MV88E6352)
2972 unregister_switch_driver(&mv88e6352_switch_driver);
2973#endif
98e67308
BH		 2974#if IS_ENABLED(CONFIG_NET_DSA_MV88E6123_61_65)
2975 unregister_switch_driver(&mv88e6123_61_65_switch_driver);
2976#endif
2977#if IS_ENABLED(CONFIG_NET_DSA_MV88E6131)
2978 unregister_switch_driver(&mv88e6131_switch_driver);
2979#endif
2980}
2981module_exit(mv88e6xxx_cleanup);
3d825ede
BH		 2982
2983MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
2984MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
2985MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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