Commit | Line | Data |
---|---|---|
91da11f8 LB |
1 | /* |
2 | * net/dsa/mv88e6xxx.c - Marvell 88e6xxx switch chip support | |
3 | * Copyright (c) 2008 Marvell Semiconductor | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation; either version 2 of the License, or | |
8 | * (at your option) any later version. | |
9 | */ | |
10 | ||
19b2f97e | 11 | #include <linux/delay.h> |
defb05b9 | 12 | #include <linux/etherdevice.h> |
facd95b2 | 13 | #include <linux/if_bridge.h> |
19b2f97e | 14 | #include <linux/jiffies.h> |
91da11f8 | 15 | #include <linux/list.h> |
2bbba277 | 16 | #include <linux/module.h> |
91da11f8 LB |
17 | #include <linux/netdevice.h> |
18 | #include <linux/phy.h> | |
c8f0b869 | 19 | #include <net/dsa.h> |
91da11f8 LB |
20 | #include "mv88e6xxx.h" |
21 | ||
3675c8d7 | 22 | /* If the switch's ADDR[4:0] strap pins are strapped to zero, it will |
91da11f8 LB |
23 | * use all 32 SMI bus addresses on its SMI bus, and all switch registers |
24 | * will be directly accessible on some {device address,register address} | |
25 | * pair. If the ADDR[4:0] pins are not strapped to zero, the switch | |
26 | * will only respond to SMI transactions to that specific address, and | |
27 | * an indirect addressing mechanism needs to be used to access its | |
28 | * registers. | |
29 | */ | |
30 | static int mv88e6xxx_reg_wait_ready(struct mii_bus *bus, int sw_addr) | |
31 | { | |
32 | int ret; | |
33 | int i; | |
34 | ||
35 | for (i = 0; i < 16; i++) { | |
cca8b133 | 36 | ret = mdiobus_read(bus, sw_addr, SMI_CMD); |
91da11f8 LB |
37 | if (ret < 0) |
38 | return ret; | |
39 | ||
cca8b133 | 40 | if ((ret & SMI_CMD_BUSY) == 0) |
91da11f8 LB |
41 | return 0; |
42 | } | |
43 | ||
44 | return -ETIMEDOUT; | |
45 | } | |
46 | ||
47 | int __mv88e6xxx_reg_read(struct mii_bus *bus, int sw_addr, int addr, int reg) | |
48 | { | |
49 | int ret; | |
50 | ||
51 | if (sw_addr == 0) | |
52 | return mdiobus_read(bus, addr, reg); | |
53 | ||
3675c8d7 | 54 | /* Wait for the bus to become free. */ |
91da11f8 LB |
55 | ret = mv88e6xxx_reg_wait_ready(bus, sw_addr); |
56 | if (ret < 0) | |
57 | return ret; | |
58 | ||
3675c8d7 | 59 | /* Transmit the read command. */ |
cca8b133 AL |
60 | ret = mdiobus_write(bus, sw_addr, SMI_CMD, |
61 | SMI_CMD_OP_22_READ | (addr << 5) | reg); | |
91da11f8 LB |
62 | if (ret < 0) |
63 | return ret; | |
64 | ||
3675c8d7 | 65 | /* Wait for the read command to complete. */ |
91da11f8 LB |
66 | ret = mv88e6xxx_reg_wait_ready(bus, sw_addr); |
67 | if (ret < 0) | |
68 | return ret; | |
69 | ||
3675c8d7 | 70 | /* Read the data. */ |
cca8b133 | 71 | ret = mdiobus_read(bus, sw_addr, SMI_DATA); |
91da11f8 LB |
72 | if (ret < 0) |
73 | return ret; | |
74 | ||
75 | return ret & 0xffff; | |
76 | } | |
77 | ||
8d6d09e7 GR |
78 | /* Must be called with SMI mutex held */ |
79 | static int _mv88e6xxx_reg_read(struct dsa_switch *ds, int addr, int reg) | |
91da11f8 | 80 | { |
b184e497 | 81 | struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev); |
91da11f8 LB |
82 | int ret; |
83 | ||
b184e497 GR |
84 | if (bus == NULL) |
85 | return -EINVAL; | |
86 | ||
b184e497 | 87 | ret = __mv88e6xxx_reg_read(bus, ds->pd->sw_addr, addr, reg); |
bb92ea5e VD |
88 | if (ret < 0) |
89 | return ret; | |
90 | ||
91 | dev_dbg(ds->master_dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", | |
92 | addr, reg, ret); | |
93 | ||
91da11f8 LB |
94 | return ret; |
95 | } | |
96 | ||
8d6d09e7 GR |
97 | int mv88e6xxx_reg_read(struct dsa_switch *ds, int addr, int reg) |
98 | { | |
99 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
100 | int ret; | |
101 | ||
102 | mutex_lock(&ps->smi_mutex); | |
103 | ret = _mv88e6xxx_reg_read(ds, addr, reg); | |
104 | mutex_unlock(&ps->smi_mutex); | |
105 | ||
106 | return ret; | |
107 | } | |
108 | ||
91da11f8 LB |
109 | int __mv88e6xxx_reg_write(struct mii_bus *bus, int sw_addr, int addr, |
110 | int reg, u16 val) | |
111 | { | |
112 | int ret; | |
113 | ||
114 | if (sw_addr == 0) | |
115 | return mdiobus_write(bus, addr, reg, val); | |
116 | ||
3675c8d7 | 117 | /* Wait for the bus to become free. */ |
91da11f8 LB |
118 | ret = mv88e6xxx_reg_wait_ready(bus, sw_addr); |
119 | if (ret < 0) | |
120 | return ret; | |
121 | ||
3675c8d7 | 122 | /* Transmit the data to write. */ |
cca8b133 | 123 | ret = mdiobus_write(bus, sw_addr, SMI_DATA, val); |
91da11f8 LB |
124 | if (ret < 0) |
125 | return ret; | |
126 | ||
3675c8d7 | 127 | /* Transmit the write command. */ |
cca8b133 AL |
128 | ret = mdiobus_write(bus, sw_addr, SMI_CMD, |
129 | SMI_CMD_OP_22_WRITE | (addr << 5) | reg); | |
91da11f8 LB |
130 | if (ret < 0) |
131 | return ret; | |
132 | ||
3675c8d7 | 133 | /* Wait for the write command to complete. */ |
91da11f8 LB |
134 | ret = mv88e6xxx_reg_wait_ready(bus, sw_addr); |
135 | if (ret < 0) | |
136 | return ret; | |
137 | ||
138 | return 0; | |
139 | } | |
140 | ||
8d6d09e7 GR |
141 | /* Must be called with SMI mutex held */ |
142 | static int _mv88e6xxx_reg_write(struct dsa_switch *ds, int addr, int reg, | |
143 | u16 val) | |
91da11f8 | 144 | { |
b184e497 | 145 | struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev); |
91da11f8 | 146 | |
b184e497 GR |
147 | if (bus == NULL) |
148 | return -EINVAL; | |
149 | ||
bb92ea5e VD |
150 | dev_dbg(ds->master_dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", |
151 | addr, reg, val); | |
152 | ||
8d6d09e7 GR |
153 | return __mv88e6xxx_reg_write(bus, ds->pd->sw_addr, addr, reg, val); |
154 | } | |
155 | ||
156 | int mv88e6xxx_reg_write(struct dsa_switch *ds, int addr, int reg, u16 val) | |
157 | { | |
158 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
159 | int ret; | |
160 | ||
91da11f8 | 161 | mutex_lock(&ps->smi_mutex); |
8d6d09e7 | 162 | ret = _mv88e6xxx_reg_write(ds, addr, reg, val); |
91da11f8 LB |
163 | mutex_unlock(&ps->smi_mutex); |
164 | ||
165 | return ret; | |
166 | } | |
167 | ||
2e5f0320 LB |
168 | int mv88e6xxx_set_addr_direct(struct dsa_switch *ds, u8 *addr) |
169 | { | |
cca8b133 AL |
170 | REG_WRITE(REG_GLOBAL, GLOBAL_MAC_01, (addr[0] << 8) | addr[1]); |
171 | REG_WRITE(REG_GLOBAL, GLOBAL_MAC_23, (addr[2] << 8) | addr[3]); | |
172 | REG_WRITE(REG_GLOBAL, GLOBAL_MAC_45, (addr[4] << 8) | addr[5]); | |
2e5f0320 LB |
173 | |
174 | return 0; | |
175 | } | |
176 | ||
91da11f8 LB |
177 | int mv88e6xxx_set_addr_indirect(struct dsa_switch *ds, u8 *addr) |
178 | { | |
179 | int i; | |
180 | int ret; | |
181 | ||
182 | for (i = 0; i < 6; i++) { | |
183 | int j; | |
184 | ||
3675c8d7 | 185 | /* Write the MAC address byte. */ |
cca8b133 AL |
186 | REG_WRITE(REG_GLOBAL2, GLOBAL2_SWITCH_MAC, |
187 | GLOBAL2_SWITCH_MAC_BUSY | (i << 8) | addr[i]); | |
91da11f8 | 188 | |
3675c8d7 | 189 | /* Wait for the write to complete. */ |
91da11f8 | 190 | for (j = 0; j < 16; j++) { |
cca8b133 AL |
191 | ret = REG_READ(REG_GLOBAL2, GLOBAL2_SWITCH_MAC); |
192 | if ((ret & GLOBAL2_SWITCH_MAC_BUSY) == 0) | |
91da11f8 LB |
193 | break; |
194 | } | |
195 | if (j == 16) | |
196 | return -ETIMEDOUT; | |
197 | } | |
198 | ||
199 | return 0; | |
200 | } | |
201 | ||
3898c148 | 202 | /* Must be called with SMI mutex held */ |
fd3a0ee4 | 203 | static int _mv88e6xxx_phy_read(struct dsa_switch *ds, int addr, int regnum) |
91da11f8 LB |
204 | { |
205 | if (addr >= 0) | |
3898c148 | 206 | return _mv88e6xxx_reg_read(ds, addr, regnum); |
91da11f8 LB |
207 | return 0xffff; |
208 | } | |
209 | ||
3898c148 | 210 | /* Must be called with SMI mutex held */ |
fd3a0ee4 AL |
211 | static int _mv88e6xxx_phy_write(struct dsa_switch *ds, int addr, int regnum, |
212 | u16 val) | |
91da11f8 LB |
213 | { |
214 | if (addr >= 0) | |
3898c148 | 215 | return _mv88e6xxx_reg_write(ds, addr, regnum, val); |
91da11f8 LB |
216 | return 0; |
217 | } | |
218 | ||
2e5f0320 LB |
219 | #ifdef CONFIG_NET_DSA_MV88E6XXX_NEED_PPU |
220 | static int mv88e6xxx_ppu_disable(struct dsa_switch *ds) | |
221 | { | |
222 | int ret; | |
19b2f97e | 223 | unsigned long timeout; |
2e5f0320 | 224 | |
cca8b133 AL |
225 | ret = REG_READ(REG_GLOBAL, GLOBAL_CONTROL); |
226 | REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL, | |
227 | ret & ~GLOBAL_CONTROL_PPU_ENABLE); | |
2e5f0320 | 228 | |
19b2f97e BG |
229 | timeout = jiffies + 1 * HZ; |
230 | while (time_before(jiffies, timeout)) { | |
cca8b133 | 231 | ret = REG_READ(REG_GLOBAL, GLOBAL_STATUS); |
19b2f97e | 232 | usleep_range(1000, 2000); |
cca8b133 AL |
233 | if ((ret & GLOBAL_STATUS_PPU_MASK) != |
234 | GLOBAL_STATUS_PPU_POLLING) | |
85686581 | 235 | return 0; |
2e5f0320 LB |
236 | } |
237 | ||
238 | return -ETIMEDOUT; | |
239 | } | |
240 | ||
241 | static int mv88e6xxx_ppu_enable(struct dsa_switch *ds) | |
242 | { | |
243 | int ret; | |
19b2f97e | 244 | unsigned long timeout; |
2e5f0320 | 245 | |
cca8b133 AL |
246 | ret = REG_READ(REG_GLOBAL, GLOBAL_CONTROL); |
247 | REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL, ret | GLOBAL_CONTROL_PPU_ENABLE); | |
2e5f0320 | 248 | |
19b2f97e BG |
249 | timeout = jiffies + 1 * HZ; |
250 | while (time_before(jiffies, timeout)) { | |
cca8b133 | 251 | ret = REG_READ(REG_GLOBAL, GLOBAL_STATUS); |
19b2f97e | 252 | usleep_range(1000, 2000); |
cca8b133 AL |
253 | if ((ret & GLOBAL_STATUS_PPU_MASK) == |
254 | GLOBAL_STATUS_PPU_POLLING) | |
85686581 | 255 | return 0; |
2e5f0320 LB |
256 | } |
257 | ||
258 | return -ETIMEDOUT; | |
259 | } | |
260 | ||
261 | static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly) | |
262 | { | |
263 | struct mv88e6xxx_priv_state *ps; | |
264 | ||
265 | ps = container_of(ugly, struct mv88e6xxx_priv_state, ppu_work); | |
266 | if (mutex_trylock(&ps->ppu_mutex)) { | |
85686581 | 267 | struct dsa_switch *ds = ((struct dsa_switch *)ps) - 1; |
2e5f0320 | 268 | |
85686581 BG |
269 | if (mv88e6xxx_ppu_enable(ds) == 0) |
270 | ps->ppu_disabled = 0; | |
271 | mutex_unlock(&ps->ppu_mutex); | |
2e5f0320 LB |
272 | } |
273 | } | |
274 | ||
275 | static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps) | |
276 | { | |
277 | struct mv88e6xxx_priv_state *ps = (void *)_ps; | |
278 | ||
279 | schedule_work(&ps->ppu_work); | |
280 | } | |
281 | ||
282 | static int mv88e6xxx_ppu_access_get(struct dsa_switch *ds) | |
283 | { | |
a22adce5 | 284 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); |
2e5f0320 LB |
285 | int ret; |
286 | ||
287 | mutex_lock(&ps->ppu_mutex); | |
288 | ||
3675c8d7 | 289 | /* If the PHY polling unit is enabled, disable it so that |
2e5f0320 LB |
290 | * we can access the PHY registers. If it was already |
291 | * disabled, cancel the timer that is going to re-enable | |
292 | * it. | |
293 | */ | |
294 | if (!ps->ppu_disabled) { | |
85686581 BG |
295 | ret = mv88e6xxx_ppu_disable(ds); |
296 | if (ret < 0) { | |
297 | mutex_unlock(&ps->ppu_mutex); | |
298 | return ret; | |
299 | } | |
300 | ps->ppu_disabled = 1; | |
2e5f0320 | 301 | } else { |
85686581 BG |
302 | del_timer(&ps->ppu_timer); |
303 | ret = 0; | |
2e5f0320 LB |
304 | } |
305 | ||
306 | return ret; | |
307 | } | |
308 | ||
309 | static void mv88e6xxx_ppu_access_put(struct dsa_switch *ds) | |
310 | { | |
a22adce5 | 311 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); |
2e5f0320 | 312 | |
3675c8d7 | 313 | /* Schedule a timer to re-enable the PHY polling unit. */ |
2e5f0320 LB |
314 | mod_timer(&ps->ppu_timer, jiffies + msecs_to_jiffies(10)); |
315 | mutex_unlock(&ps->ppu_mutex); | |
316 | } | |
317 | ||
318 | void mv88e6xxx_ppu_state_init(struct dsa_switch *ds) | |
319 | { | |
a22adce5 | 320 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); |
2e5f0320 LB |
321 | |
322 | mutex_init(&ps->ppu_mutex); | |
323 | INIT_WORK(&ps->ppu_work, mv88e6xxx_ppu_reenable_work); | |
324 | init_timer(&ps->ppu_timer); | |
325 | ps->ppu_timer.data = (unsigned long)ps; | |
326 | ps->ppu_timer.function = mv88e6xxx_ppu_reenable_timer; | |
327 | } | |
328 | ||
329 | int mv88e6xxx_phy_read_ppu(struct dsa_switch *ds, int addr, int regnum) | |
330 | { | |
331 | int ret; | |
332 | ||
333 | ret = mv88e6xxx_ppu_access_get(ds); | |
334 | if (ret >= 0) { | |
85686581 BG |
335 | ret = mv88e6xxx_reg_read(ds, addr, regnum); |
336 | mv88e6xxx_ppu_access_put(ds); | |
2e5f0320 LB |
337 | } |
338 | ||
339 | return ret; | |
340 | } | |
341 | ||
342 | int mv88e6xxx_phy_write_ppu(struct dsa_switch *ds, int addr, | |
343 | int regnum, u16 val) | |
344 | { | |
345 | int ret; | |
346 | ||
347 | ret = mv88e6xxx_ppu_access_get(ds); | |
348 | if (ret >= 0) { | |
85686581 BG |
349 | ret = mv88e6xxx_reg_write(ds, addr, regnum, val); |
350 | mv88e6xxx_ppu_access_put(ds); | |
2e5f0320 LB |
351 | } |
352 | ||
353 | return ret; | |
354 | } | |
355 | #endif | |
356 | ||
91da11f8 LB |
357 | void mv88e6xxx_poll_link(struct dsa_switch *ds) |
358 | { | |
359 | int i; | |
360 | ||
361 | for (i = 0; i < DSA_MAX_PORTS; i++) { | |
362 | struct net_device *dev; | |
2a9e7978 | 363 | int uninitialized_var(port_status); |
91da11f8 LB |
364 | int link; |
365 | int speed; | |
366 | int duplex; | |
367 | int fc; | |
368 | ||
369 | dev = ds->ports[i]; | |
370 | if (dev == NULL) | |
371 | continue; | |
372 | ||
373 | link = 0; | |
374 | if (dev->flags & IFF_UP) { | |
cca8b133 AL |
375 | port_status = mv88e6xxx_reg_read(ds, REG_PORT(i), |
376 | PORT_STATUS); | |
91da11f8 LB |
377 | if (port_status < 0) |
378 | continue; | |
379 | ||
cca8b133 | 380 | link = !!(port_status & PORT_STATUS_LINK); |
91da11f8 LB |
381 | } |
382 | ||
383 | if (!link) { | |
384 | if (netif_carrier_ok(dev)) { | |
ab381a93 | 385 | netdev_info(dev, "link down\n"); |
91da11f8 LB |
386 | netif_carrier_off(dev); |
387 | } | |
388 | continue; | |
389 | } | |
390 | ||
cca8b133 AL |
391 | switch (port_status & PORT_STATUS_SPEED_MASK) { |
392 | case PORT_STATUS_SPEED_10: | |
91da11f8 LB |
393 | speed = 10; |
394 | break; | |
cca8b133 | 395 | case PORT_STATUS_SPEED_100: |
91da11f8 LB |
396 | speed = 100; |
397 | break; | |
cca8b133 | 398 | case PORT_STATUS_SPEED_1000: |
91da11f8 LB |
399 | speed = 1000; |
400 | break; | |
401 | default: | |
402 | speed = -1; | |
403 | break; | |
404 | } | |
cca8b133 AL |
405 | duplex = (port_status & PORT_STATUS_DUPLEX) ? 1 : 0; |
406 | fc = (port_status & PORT_STATUS_PAUSE_EN) ? 1 : 0; | |
91da11f8 LB |
407 | |
408 | if (!netif_carrier_ok(dev)) { | |
ab381a93 BG |
409 | netdev_info(dev, |
410 | "link up, %d Mb/s, %s duplex, flow control %sabled\n", | |
411 | speed, | |
412 | duplex ? "full" : "half", | |
413 | fc ? "en" : "dis"); | |
91da11f8 LB |
414 | netif_carrier_on(dev); |
415 | } | |
416 | } | |
417 | } | |
418 | ||
54d792f2 AL |
419 | static bool mv88e6xxx_6065_family(struct dsa_switch *ds) |
420 | { | |
421 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
422 | ||
423 | switch (ps->id) { | |
424 | case PORT_SWITCH_ID_6031: | |
425 | case PORT_SWITCH_ID_6061: | |
426 | case PORT_SWITCH_ID_6035: | |
427 | case PORT_SWITCH_ID_6065: | |
428 | return true; | |
429 | } | |
430 | return false; | |
431 | } | |
432 | ||
433 | static bool mv88e6xxx_6095_family(struct dsa_switch *ds) | |
434 | { | |
435 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
436 | ||
437 | switch (ps->id) { | |
438 | case PORT_SWITCH_ID_6092: | |
439 | case PORT_SWITCH_ID_6095: | |
440 | return true; | |
441 | } | |
442 | return false; | |
443 | } | |
444 | ||
445 | static bool mv88e6xxx_6097_family(struct dsa_switch *ds) | |
446 | { | |
447 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
448 | ||
449 | switch (ps->id) { | |
450 | case PORT_SWITCH_ID_6046: | |
451 | case PORT_SWITCH_ID_6085: | |
452 | case PORT_SWITCH_ID_6096: | |
453 | case PORT_SWITCH_ID_6097: | |
454 | return true; | |
455 | } | |
456 | return false; | |
457 | } | |
458 | ||
459 | static bool mv88e6xxx_6165_family(struct dsa_switch *ds) | |
460 | { | |
461 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
462 | ||
463 | switch (ps->id) { | |
464 | case PORT_SWITCH_ID_6123: | |
465 | case PORT_SWITCH_ID_6161: | |
466 | case PORT_SWITCH_ID_6165: | |
467 | return true; | |
468 | } | |
469 | return false; | |
470 | } | |
471 | ||
472 | static bool mv88e6xxx_6185_family(struct dsa_switch *ds) | |
473 | { | |
474 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
475 | ||
476 | switch (ps->id) { | |
477 | case PORT_SWITCH_ID_6121: | |
478 | case PORT_SWITCH_ID_6122: | |
479 | case PORT_SWITCH_ID_6152: | |
480 | case PORT_SWITCH_ID_6155: | |
481 | case PORT_SWITCH_ID_6182: | |
482 | case PORT_SWITCH_ID_6185: | |
483 | case PORT_SWITCH_ID_6108: | |
484 | case PORT_SWITCH_ID_6131: | |
485 | return true; | |
486 | } | |
487 | return false; | |
488 | } | |
489 | ||
490 | static bool mv88e6xxx_6351_family(struct dsa_switch *ds) | |
491 | { | |
492 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
493 | ||
494 | switch (ps->id) { | |
495 | case PORT_SWITCH_ID_6171: | |
496 | case PORT_SWITCH_ID_6175: | |
497 | case PORT_SWITCH_ID_6350: | |
498 | case PORT_SWITCH_ID_6351: | |
499 | return true; | |
500 | } | |
501 | return false; | |
502 | } | |
503 | ||
f3a8b6b6 AL |
504 | static bool mv88e6xxx_6352_family(struct dsa_switch *ds) |
505 | { | |
506 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
507 | ||
508 | switch (ps->id) { | |
f3a8b6b6 AL |
509 | case PORT_SWITCH_ID_6172: |
510 | case PORT_SWITCH_ID_6176: | |
54d792f2 AL |
511 | case PORT_SWITCH_ID_6240: |
512 | case PORT_SWITCH_ID_6352: | |
f3a8b6b6 AL |
513 | return true; |
514 | } | |
515 | return false; | |
516 | } | |
517 | ||
91da11f8 LB |
518 | static int mv88e6xxx_stats_wait(struct dsa_switch *ds) |
519 | { | |
520 | int ret; | |
521 | int i; | |
522 | ||
523 | for (i = 0; i < 10; i++) { | |
cca8b133 AL |
524 | ret = REG_READ(REG_GLOBAL, GLOBAL_STATS_OP); |
525 | if ((ret & GLOBAL_STATS_OP_BUSY) == 0) | |
91da11f8 LB |
526 | return 0; |
527 | } | |
528 | ||
529 | return -ETIMEDOUT; | |
530 | } | |
531 | ||
532 | static int mv88e6xxx_stats_snapshot(struct dsa_switch *ds, int port) | |
533 | { | |
534 | int ret; | |
535 | ||
f3a8b6b6 AL |
536 | if (mv88e6xxx_6352_family(ds)) |
537 | port = (port + 1) << 5; | |
538 | ||
3675c8d7 | 539 | /* Snapshot the hardware statistics counters for this port. */ |
cca8b133 AL |
540 | REG_WRITE(REG_GLOBAL, GLOBAL_STATS_OP, |
541 | GLOBAL_STATS_OP_CAPTURE_PORT | | |
542 | GLOBAL_STATS_OP_HIST_RX_TX | port); | |
91da11f8 | 543 | |
3675c8d7 | 544 | /* Wait for the snapshotting to complete. */ |
91da11f8 LB |
545 | ret = mv88e6xxx_stats_wait(ds); |
546 | if (ret < 0) | |
547 | return ret; | |
548 | ||
549 | return 0; | |
550 | } | |
551 | ||
552 | static void mv88e6xxx_stats_read(struct dsa_switch *ds, int stat, u32 *val) | |
553 | { | |
554 | u32 _val; | |
555 | int ret; | |
556 | ||
557 | *val = 0; | |
558 | ||
cca8b133 AL |
559 | ret = mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_STATS_OP, |
560 | GLOBAL_STATS_OP_READ_CAPTURED | | |
561 | GLOBAL_STATS_OP_HIST_RX_TX | stat); | |
91da11f8 LB |
562 | if (ret < 0) |
563 | return; | |
564 | ||
565 | ret = mv88e6xxx_stats_wait(ds); | |
566 | if (ret < 0) | |
567 | return; | |
568 | ||
cca8b133 | 569 | ret = mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_STATS_COUNTER_32); |
91da11f8 LB |
570 | if (ret < 0) |
571 | return; | |
572 | ||
573 | _val = ret << 16; | |
574 | ||
cca8b133 | 575 | ret = mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_STATS_COUNTER_01); |
91da11f8 LB |
576 | if (ret < 0) |
577 | return; | |
578 | ||
579 | *val = _val | ret; | |
580 | } | |
581 | ||
e413e7e1 AL |
582 | static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = { |
583 | { "in_good_octets", 8, 0x00, }, | |
584 | { "in_bad_octets", 4, 0x02, }, | |
585 | { "in_unicast", 4, 0x04, }, | |
586 | { "in_broadcasts", 4, 0x06, }, | |
587 | { "in_multicasts", 4, 0x07, }, | |
588 | { "in_pause", 4, 0x16, }, | |
589 | { "in_undersize", 4, 0x18, }, | |
590 | { "in_fragments", 4, 0x19, }, | |
591 | { "in_oversize", 4, 0x1a, }, | |
592 | { "in_jabber", 4, 0x1b, }, | |
593 | { "in_rx_error", 4, 0x1c, }, | |
594 | { "in_fcs_error", 4, 0x1d, }, | |
595 | { "out_octets", 8, 0x0e, }, | |
596 | { "out_unicast", 4, 0x10, }, | |
597 | { "out_broadcasts", 4, 0x13, }, | |
598 | { "out_multicasts", 4, 0x12, }, | |
599 | { "out_pause", 4, 0x15, }, | |
600 | { "excessive", 4, 0x11, }, | |
601 | { "collisions", 4, 0x1e, }, | |
602 | { "deferred", 4, 0x05, }, | |
603 | { "single", 4, 0x14, }, | |
604 | { "multiple", 4, 0x17, }, | |
605 | { "out_fcs_error", 4, 0x03, }, | |
606 | { "late", 4, 0x1f, }, | |
607 | { "hist_64bytes", 4, 0x08, }, | |
608 | { "hist_65_127bytes", 4, 0x09, }, | |
609 | { "hist_128_255bytes", 4, 0x0a, }, | |
610 | { "hist_256_511bytes", 4, 0x0b, }, | |
611 | { "hist_512_1023bytes", 4, 0x0c, }, | |
612 | { "hist_1024_max_bytes", 4, 0x0d, }, | |
613 | /* Not all devices have the following counters */ | |
614 | { "sw_in_discards", 4, 0x110, }, | |
615 | { "sw_in_filtered", 2, 0x112, }, | |
616 | { "sw_out_filtered", 2, 0x113, }, | |
617 | ||
618 | }; | |
619 | ||
620 | static bool have_sw_in_discards(struct dsa_switch *ds) | |
621 | { | |
622 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
623 | ||
624 | switch (ps->id) { | |
cca8b133 AL |
625 | case PORT_SWITCH_ID_6095: case PORT_SWITCH_ID_6161: |
626 | case PORT_SWITCH_ID_6165: case PORT_SWITCH_ID_6171: | |
627 | case PORT_SWITCH_ID_6172: case PORT_SWITCH_ID_6176: | |
628 | case PORT_SWITCH_ID_6182: case PORT_SWITCH_ID_6185: | |
629 | case PORT_SWITCH_ID_6352: | |
e413e7e1 AL |
630 | return true; |
631 | default: | |
632 | return false; | |
633 | } | |
634 | } | |
635 | ||
636 | static void _mv88e6xxx_get_strings(struct dsa_switch *ds, | |
637 | int nr_stats, | |
638 | struct mv88e6xxx_hw_stat *stats, | |
639 | int port, uint8_t *data) | |
91da11f8 LB |
640 | { |
641 | int i; | |
642 | ||
643 | for (i = 0; i < nr_stats; i++) { | |
644 | memcpy(data + i * ETH_GSTRING_LEN, | |
645 | stats[i].string, ETH_GSTRING_LEN); | |
646 | } | |
647 | } | |
648 | ||
e413e7e1 AL |
649 | static void _mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, |
650 | int nr_stats, | |
651 | struct mv88e6xxx_hw_stat *stats, | |
652 | int port, uint64_t *data) | |
91da11f8 | 653 | { |
a22adce5 | 654 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); |
91da11f8 LB |
655 | int ret; |
656 | int i; | |
657 | ||
658 | mutex_lock(&ps->stats_mutex); | |
659 | ||
660 | ret = mv88e6xxx_stats_snapshot(ds, port); | |
661 | if (ret < 0) { | |
662 | mutex_unlock(&ps->stats_mutex); | |
663 | return; | |
664 | } | |
665 | ||
3675c8d7 | 666 | /* Read each of the counters. */ |
91da11f8 LB |
667 | for (i = 0; i < nr_stats; i++) { |
668 | struct mv88e6xxx_hw_stat *s = stats + i; | |
669 | u32 low; | |
17ee3e04 GR |
670 | u32 high = 0; |
671 | ||
672 | if (s->reg >= 0x100) { | |
17ee3e04 GR |
673 | ret = mv88e6xxx_reg_read(ds, REG_PORT(port), |
674 | s->reg - 0x100); | |
675 | if (ret < 0) | |
676 | goto error; | |
677 | low = ret; | |
678 | if (s->sizeof_stat == 4) { | |
679 | ret = mv88e6xxx_reg_read(ds, REG_PORT(port), | |
680 | s->reg - 0x100 + 1); | |
681 | if (ret < 0) | |
682 | goto error; | |
683 | high = ret; | |
684 | } | |
685 | data[i] = (((u64)high) << 16) | low; | |
686 | continue; | |
687 | } | |
91da11f8 LB |
688 | mv88e6xxx_stats_read(ds, s->reg, &low); |
689 | if (s->sizeof_stat == 8) | |
690 | mv88e6xxx_stats_read(ds, s->reg + 1, &high); | |
91da11f8 LB |
691 | |
692 | data[i] = (((u64)high) << 32) | low; | |
693 | } | |
17ee3e04 | 694 | error: |
91da11f8 LB |
695 | mutex_unlock(&ps->stats_mutex); |
696 | } | |
98e67308 | 697 | |
e413e7e1 AL |
698 | /* All the statistics in the table */ |
699 | void | |
700 | mv88e6xxx_get_strings(struct dsa_switch *ds, int port, uint8_t *data) | |
701 | { | |
702 | if (have_sw_in_discards(ds)) | |
703 | _mv88e6xxx_get_strings(ds, ARRAY_SIZE(mv88e6xxx_hw_stats), | |
704 | mv88e6xxx_hw_stats, port, data); | |
705 | else | |
706 | _mv88e6xxx_get_strings(ds, ARRAY_SIZE(mv88e6xxx_hw_stats) - 3, | |
707 | mv88e6xxx_hw_stats, port, data); | |
708 | } | |
709 | ||
710 | int mv88e6xxx_get_sset_count(struct dsa_switch *ds) | |
711 | { | |
712 | if (have_sw_in_discards(ds)) | |
713 | return ARRAY_SIZE(mv88e6xxx_hw_stats); | |
714 | return ARRAY_SIZE(mv88e6xxx_hw_stats) - 3; | |
715 | } | |
716 | ||
717 | void | |
718 | mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, | |
719 | int port, uint64_t *data) | |
720 | { | |
721 | if (have_sw_in_discards(ds)) | |
722 | _mv88e6xxx_get_ethtool_stats( | |
723 | ds, ARRAY_SIZE(mv88e6xxx_hw_stats), | |
724 | mv88e6xxx_hw_stats, port, data); | |
725 | else | |
726 | _mv88e6xxx_get_ethtool_stats( | |
727 | ds, ARRAY_SIZE(mv88e6xxx_hw_stats) - 3, | |
728 | mv88e6xxx_hw_stats, port, data); | |
729 | } | |
730 | ||
a1ab91f3 GR |
731 | int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port) |
732 | { | |
733 | return 32 * sizeof(u16); | |
734 | } | |
735 | ||
736 | void mv88e6xxx_get_regs(struct dsa_switch *ds, int port, | |
737 | struct ethtool_regs *regs, void *_p) | |
738 | { | |
739 | u16 *p = _p; | |
740 | int i; | |
741 | ||
742 | regs->version = 0; | |
743 | ||
744 | memset(p, 0xff, 32 * sizeof(u16)); | |
745 | ||
746 | for (i = 0; i < 32; i++) { | |
747 | int ret; | |
748 | ||
749 | ret = mv88e6xxx_reg_read(ds, REG_PORT(port), i); | |
750 | if (ret >= 0) | |
751 | p[i] = ret; | |
752 | } | |
753 | } | |
754 | ||
eaa23765 AL |
755 | #ifdef CONFIG_NET_DSA_HWMON |
756 | ||
757 | int mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp) | |
758 | { | |
759 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
760 | int ret; | |
761 | int val; | |
762 | ||
763 | *temp = 0; | |
764 | ||
3898c148 | 765 | mutex_lock(&ps->smi_mutex); |
eaa23765 | 766 | |
fd3a0ee4 | 767 | ret = _mv88e6xxx_phy_write(ds, 0x0, 0x16, 0x6); |
eaa23765 AL |
768 | if (ret < 0) |
769 | goto error; | |
770 | ||
771 | /* Enable temperature sensor */ | |
fd3a0ee4 | 772 | ret = _mv88e6xxx_phy_read(ds, 0x0, 0x1a); |
eaa23765 AL |
773 | if (ret < 0) |
774 | goto error; | |
775 | ||
fd3a0ee4 | 776 | ret = _mv88e6xxx_phy_write(ds, 0x0, 0x1a, ret | (1 << 5)); |
eaa23765 AL |
777 | if (ret < 0) |
778 | goto error; | |
779 | ||
780 | /* Wait for temperature to stabilize */ | |
781 | usleep_range(10000, 12000); | |
782 | ||
fd3a0ee4 | 783 | val = _mv88e6xxx_phy_read(ds, 0x0, 0x1a); |
eaa23765 AL |
784 | if (val < 0) { |
785 | ret = val; | |
786 | goto error; | |
787 | } | |
788 | ||
789 | /* Disable temperature sensor */ | |
fd3a0ee4 | 790 | ret = _mv88e6xxx_phy_write(ds, 0x0, 0x1a, ret & ~(1 << 5)); |
eaa23765 AL |
791 | if (ret < 0) |
792 | goto error; | |
793 | ||
794 | *temp = ((val & 0x1f) - 5) * 5; | |
795 | ||
796 | error: | |
fd3a0ee4 | 797 | _mv88e6xxx_phy_write(ds, 0x0, 0x16, 0x0); |
3898c148 | 798 | mutex_unlock(&ps->smi_mutex); |
eaa23765 AL |
799 | return ret; |
800 | } | |
801 | #endif /* CONFIG_NET_DSA_HWMON */ | |
802 | ||
3898c148 AL |
803 | /* Must be called with SMI lock held */ |
804 | static int _mv88e6xxx_wait(struct dsa_switch *ds, int reg, int offset, | |
805 | u16 mask) | |
f3044683 AL |
806 | { |
807 | unsigned long timeout = jiffies + HZ / 10; | |
808 | ||
809 | while (time_before(jiffies, timeout)) { | |
810 | int ret; | |
811 | ||
3898c148 AL |
812 | ret = _mv88e6xxx_reg_read(ds, reg, offset); |
813 | if (ret < 0) | |
814 | return ret; | |
f3044683 AL |
815 | if (!(ret & mask)) |
816 | return 0; | |
817 | ||
818 | usleep_range(1000, 2000); | |
819 | } | |
820 | return -ETIMEDOUT; | |
821 | } | |
822 | ||
3898c148 AL |
823 | static int mv88e6xxx_wait(struct dsa_switch *ds, int reg, int offset, u16 mask) |
824 | { | |
825 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
826 | int ret; | |
827 | ||
828 | mutex_lock(&ps->smi_mutex); | |
829 | ret = _mv88e6xxx_wait(ds, reg, offset, mask); | |
830 | mutex_unlock(&ps->smi_mutex); | |
831 | ||
832 | return ret; | |
833 | } | |
834 | ||
835 | static int _mv88e6xxx_phy_wait(struct dsa_switch *ds) | |
f3044683 | 836 | { |
3898c148 AL |
837 | return _mv88e6xxx_wait(ds, REG_GLOBAL2, GLOBAL2_SMI_OP, |
838 | GLOBAL2_SMI_OP_BUSY); | |
f3044683 AL |
839 | } |
840 | ||
841 | int mv88e6xxx_eeprom_load_wait(struct dsa_switch *ds) | |
842 | { | |
cca8b133 AL |
843 | return mv88e6xxx_wait(ds, REG_GLOBAL2, GLOBAL2_EEPROM_OP, |
844 | GLOBAL2_EEPROM_OP_LOAD); | |
f3044683 AL |
845 | } |
846 | ||
847 | int mv88e6xxx_eeprom_busy_wait(struct dsa_switch *ds) | |
848 | { | |
cca8b133 AL |
849 | return mv88e6xxx_wait(ds, REG_GLOBAL2, GLOBAL2_EEPROM_OP, |
850 | GLOBAL2_EEPROM_OP_BUSY); | |
f3044683 AL |
851 | } |
852 | ||
facd95b2 GR |
853 | /* Must be called with SMI lock held */ |
854 | static int _mv88e6xxx_atu_wait(struct dsa_switch *ds) | |
855 | { | |
cca8b133 AL |
856 | return _mv88e6xxx_wait(ds, REG_GLOBAL, GLOBAL_ATU_OP, |
857 | GLOBAL_ATU_OP_BUSY); | |
facd95b2 GR |
858 | } |
859 | ||
3898c148 | 860 | /* Must be called with SMI mutex held */ |
fd3a0ee4 AL |
861 | static int _mv88e6xxx_phy_read_indirect(struct dsa_switch *ds, int addr, |
862 | int regnum) | |
f3044683 AL |
863 | { |
864 | int ret; | |
865 | ||
3898c148 AL |
866 | ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_SMI_OP, |
867 | GLOBAL2_SMI_OP_22_READ | (addr << 5) | | |
868 | regnum); | |
869 | if (ret < 0) | |
870 | return ret; | |
f3044683 | 871 | |
3898c148 | 872 | ret = _mv88e6xxx_phy_wait(ds); |
f3044683 AL |
873 | if (ret < 0) |
874 | return ret; | |
875 | ||
3898c148 | 876 | return _mv88e6xxx_reg_read(ds, REG_GLOBAL2, GLOBAL2_SMI_DATA); |
f3044683 AL |
877 | } |
878 | ||
3898c148 | 879 | /* Must be called with SMI mutex held */ |
fd3a0ee4 AL |
880 | static int _mv88e6xxx_phy_write_indirect(struct dsa_switch *ds, int addr, |
881 | int regnum, u16 val) | |
f3044683 | 882 | { |
3898c148 AL |
883 | int ret; |
884 | ||
885 | ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_SMI_DATA, val); | |
886 | if (ret < 0) | |
887 | return ret; | |
f3044683 | 888 | |
3898c148 AL |
889 | ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_SMI_OP, |
890 | GLOBAL2_SMI_OP_22_WRITE | (addr << 5) | | |
891 | regnum); | |
892 | ||
893 | return _mv88e6xxx_phy_wait(ds); | |
f3044683 AL |
894 | } |
895 | ||
11b3b45d GR |
896 | int mv88e6xxx_get_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e) |
897 | { | |
2f40c698 | 898 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); |
11b3b45d GR |
899 | int reg; |
900 | ||
3898c148 | 901 | mutex_lock(&ps->smi_mutex); |
2f40c698 AL |
902 | |
903 | reg = _mv88e6xxx_phy_read_indirect(ds, port, 16); | |
11b3b45d | 904 | if (reg < 0) |
2f40c698 | 905 | goto out; |
11b3b45d GR |
906 | |
907 | e->eee_enabled = !!(reg & 0x0200); | |
908 | e->tx_lpi_enabled = !!(reg & 0x0100); | |
909 | ||
3898c148 | 910 | reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_STATUS); |
11b3b45d | 911 | if (reg < 0) |
2f40c698 | 912 | goto out; |
11b3b45d | 913 | |
cca8b133 | 914 | e->eee_active = !!(reg & PORT_STATUS_EEE); |
2f40c698 | 915 | reg = 0; |
11b3b45d | 916 | |
2f40c698 | 917 | out: |
3898c148 | 918 | mutex_unlock(&ps->smi_mutex); |
2f40c698 | 919 | return reg; |
11b3b45d GR |
920 | } |
921 | ||
922 | int mv88e6xxx_set_eee(struct dsa_switch *ds, int port, | |
923 | struct phy_device *phydev, struct ethtool_eee *e) | |
924 | { | |
2f40c698 AL |
925 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); |
926 | int reg; | |
11b3b45d GR |
927 | int ret; |
928 | ||
3898c148 | 929 | mutex_lock(&ps->smi_mutex); |
11b3b45d | 930 | |
2f40c698 AL |
931 | ret = _mv88e6xxx_phy_read_indirect(ds, port, 16); |
932 | if (ret < 0) | |
933 | goto out; | |
934 | ||
935 | reg = ret & ~0x0300; | |
936 | if (e->eee_enabled) | |
937 | reg |= 0x0200; | |
938 | if (e->tx_lpi_enabled) | |
939 | reg |= 0x0100; | |
940 | ||
941 | ret = _mv88e6xxx_phy_write_indirect(ds, port, 16, reg); | |
942 | out: | |
3898c148 | 943 | mutex_unlock(&ps->smi_mutex); |
2f40c698 AL |
944 | |
945 | return ret; | |
11b3b45d GR |
946 | } |
947 | ||
facd95b2 GR |
948 | static int _mv88e6xxx_atu_cmd(struct dsa_switch *ds, int fid, u16 cmd) |
949 | { | |
950 | int ret; | |
951 | ||
952 | ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, 0x01, fid); | |
953 | if (ret < 0) | |
954 | return ret; | |
955 | ||
cca8b133 | 956 | ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_OP, cmd); |
facd95b2 GR |
957 | if (ret < 0) |
958 | return ret; | |
959 | ||
960 | return _mv88e6xxx_atu_wait(ds); | |
961 | } | |
962 | ||
963 | static int _mv88e6xxx_flush_fid(struct dsa_switch *ds, int fid) | |
964 | { | |
965 | int ret; | |
966 | ||
967 | ret = _mv88e6xxx_atu_wait(ds); | |
968 | if (ret < 0) | |
969 | return ret; | |
970 | ||
cca8b133 | 971 | return _mv88e6xxx_atu_cmd(ds, fid, GLOBAL_ATU_OP_FLUSH_NON_STATIC_DB); |
facd95b2 GR |
972 | } |
973 | ||
974 | static int mv88e6xxx_set_port_state(struct dsa_switch *ds, int port, u8 state) | |
975 | { | |
976 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
c3ffe6d2 | 977 | int reg, ret = 0; |
facd95b2 GR |
978 | u8 oldstate; |
979 | ||
980 | mutex_lock(&ps->smi_mutex); | |
981 | ||
cca8b133 | 982 | reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_CONTROL); |
538cc282 GR |
983 | if (reg < 0) { |
984 | ret = reg; | |
facd95b2 | 985 | goto abort; |
538cc282 | 986 | } |
facd95b2 | 987 | |
cca8b133 | 988 | oldstate = reg & PORT_CONTROL_STATE_MASK; |
facd95b2 GR |
989 | if (oldstate != state) { |
990 | /* Flush forwarding database if we're moving a port | |
991 | * from Learning or Forwarding state to Disabled or | |
992 | * Blocking or Listening state. | |
993 | */ | |
cca8b133 AL |
994 | if (oldstate >= PORT_CONTROL_STATE_LEARNING && |
995 | state <= PORT_CONTROL_STATE_BLOCKING) { | |
facd95b2 GR |
996 | ret = _mv88e6xxx_flush_fid(ds, ps->fid[port]); |
997 | if (ret) | |
998 | goto abort; | |
999 | } | |
cca8b133 AL |
1000 | reg = (reg & ~PORT_CONTROL_STATE_MASK) | state; |
1001 | ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_CONTROL, | |
1002 | reg); | |
facd95b2 GR |
1003 | } |
1004 | ||
1005 | abort: | |
1006 | mutex_unlock(&ps->smi_mutex); | |
1007 | return ret; | |
1008 | } | |
1009 | ||
1010 | /* Must be called with smi lock held */ | |
1011 | static int _mv88e6xxx_update_port_config(struct dsa_switch *ds, int port) | |
1012 | { | |
1013 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
1014 | u8 fid = ps->fid[port]; | |
1015 | u16 reg = fid << 12; | |
1016 | ||
1017 | if (dsa_is_cpu_port(ds, port)) | |
1018 | reg |= ds->phys_port_mask; | |
1019 | else | |
1020 | reg |= (ps->bridge_mask[fid] | | |
1021 | (1 << dsa_upstream_port(ds))) & ~(1 << port); | |
1022 | ||
cca8b133 | 1023 | return _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_BASE_VLAN, reg); |
facd95b2 GR |
1024 | } |
1025 | ||
1026 | /* Must be called with smi lock held */ | |
1027 | static int _mv88e6xxx_update_bridge_config(struct dsa_switch *ds, int fid) | |
1028 | { | |
1029 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
1030 | int port; | |
1031 | u32 mask; | |
1032 | int ret; | |
1033 | ||
1034 | mask = ds->phys_port_mask; | |
1035 | while (mask) { | |
1036 | port = __ffs(mask); | |
1037 | mask &= ~(1 << port); | |
1038 | if (ps->fid[port] != fid) | |
1039 | continue; | |
1040 | ||
1041 | ret = _mv88e6xxx_update_port_config(ds, port); | |
1042 | if (ret) | |
1043 | return ret; | |
1044 | } | |
1045 | ||
1046 | return _mv88e6xxx_flush_fid(ds, fid); | |
1047 | } | |
1048 | ||
1049 | /* Bridge handling functions */ | |
1050 | ||
1051 | int mv88e6xxx_join_bridge(struct dsa_switch *ds, int port, u32 br_port_mask) | |
1052 | { | |
1053 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
1054 | int ret = 0; | |
1055 | u32 nmask; | |
1056 | int fid; | |
1057 | ||
1058 | /* If the bridge group is not empty, join that group. | |
1059 | * Otherwise create a new group. | |
1060 | */ | |
1061 | fid = ps->fid[port]; | |
1062 | nmask = br_port_mask & ~(1 << port); | |
1063 | if (nmask) | |
1064 | fid = ps->fid[__ffs(nmask)]; | |
1065 | ||
1066 | nmask = ps->bridge_mask[fid] | (1 << port); | |
1067 | if (nmask != br_port_mask) { | |
1068 | netdev_err(ds->ports[port], | |
1069 | "join: Bridge port mask mismatch fid=%d mask=0x%x expected 0x%x\n", | |
1070 | fid, br_port_mask, nmask); | |
1071 | return -EINVAL; | |
1072 | } | |
1073 | ||
1074 | mutex_lock(&ps->smi_mutex); | |
1075 | ||
1076 | ps->bridge_mask[fid] = br_port_mask; | |
1077 | ||
1078 | if (fid != ps->fid[port]) { | |
1079 | ps->fid_mask |= 1 << ps->fid[port]; | |
1080 | ps->fid[port] = fid; | |
1081 | ret = _mv88e6xxx_update_bridge_config(ds, fid); | |
1082 | } | |
1083 | ||
1084 | mutex_unlock(&ps->smi_mutex); | |
1085 | ||
1086 | return ret; | |
1087 | } | |
1088 | ||
1089 | int mv88e6xxx_leave_bridge(struct dsa_switch *ds, int port, u32 br_port_mask) | |
1090 | { | |
1091 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
1092 | u8 fid, newfid; | |
1093 | int ret; | |
1094 | ||
1095 | fid = ps->fid[port]; | |
1096 | ||
1097 | if (ps->bridge_mask[fid] != br_port_mask) { | |
1098 | netdev_err(ds->ports[port], | |
1099 | "leave: Bridge port mask mismatch fid=%d mask=0x%x expected 0x%x\n", | |
1100 | fid, br_port_mask, ps->bridge_mask[fid]); | |
1101 | return -EINVAL; | |
1102 | } | |
1103 | ||
1104 | /* If the port was the last port of a bridge, we are done. | |
1105 | * Otherwise assign a new fid to the port, and fix up | |
1106 | * the bridge configuration. | |
1107 | */ | |
1108 | if (br_port_mask == (1 << port)) | |
1109 | return 0; | |
1110 | ||
1111 | mutex_lock(&ps->smi_mutex); | |
1112 | ||
1113 | newfid = __ffs(ps->fid_mask); | |
1114 | ps->fid[port] = newfid; | |
1115 | ps->fid_mask &= (1 << newfid); | |
1116 | ps->bridge_mask[fid] &= ~(1 << port); | |
1117 | ps->bridge_mask[newfid] = 1 << port; | |
1118 | ||
1119 | ret = _mv88e6xxx_update_bridge_config(ds, fid); | |
1120 | if (!ret) | |
1121 | ret = _mv88e6xxx_update_bridge_config(ds, newfid); | |
1122 | ||
1123 | mutex_unlock(&ps->smi_mutex); | |
1124 | ||
1125 | return ret; | |
1126 | } | |
1127 | ||
1128 | int mv88e6xxx_port_stp_update(struct dsa_switch *ds, int port, u8 state) | |
1129 | { | |
1130 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
1131 | int stp_state; | |
1132 | ||
1133 | switch (state) { | |
1134 | case BR_STATE_DISABLED: | |
cca8b133 | 1135 | stp_state = PORT_CONTROL_STATE_DISABLED; |
facd95b2 GR |
1136 | break; |
1137 | case BR_STATE_BLOCKING: | |
1138 | case BR_STATE_LISTENING: | |
cca8b133 | 1139 | stp_state = PORT_CONTROL_STATE_BLOCKING; |
facd95b2 GR |
1140 | break; |
1141 | case BR_STATE_LEARNING: | |
cca8b133 | 1142 | stp_state = PORT_CONTROL_STATE_LEARNING; |
facd95b2 GR |
1143 | break; |
1144 | case BR_STATE_FORWARDING: | |
1145 | default: | |
cca8b133 | 1146 | stp_state = PORT_CONTROL_STATE_FORWARDING; |
facd95b2 GR |
1147 | break; |
1148 | } | |
1149 | ||
1150 | netdev_dbg(ds->ports[port], "port state %d [%d]\n", state, stp_state); | |
1151 | ||
1152 | /* mv88e6xxx_port_stp_update may be called with softirqs disabled, | |
1153 | * so we can not update the port state directly but need to schedule it. | |
1154 | */ | |
1155 | ps->port_state[port] = stp_state; | |
1156 | set_bit(port, &ps->port_state_update_mask); | |
1157 | schedule_work(&ps->bridge_work); | |
1158 | ||
1159 | return 0; | |
1160 | } | |
1161 | ||
defb05b9 GR |
1162 | static int __mv88e6xxx_write_addr(struct dsa_switch *ds, |
1163 | const unsigned char *addr) | |
1164 | { | |
1165 | int i, ret; | |
1166 | ||
1167 | for (i = 0; i < 3; i++) { | |
cca8b133 AL |
1168 | ret = _mv88e6xxx_reg_write( |
1169 | ds, REG_GLOBAL, GLOBAL_ATU_MAC_01 + i, | |
1170 | (addr[i * 2] << 8) | addr[i * 2 + 1]); | |
defb05b9 GR |
1171 | if (ret < 0) |
1172 | return ret; | |
1173 | } | |
1174 | ||
1175 | return 0; | |
1176 | } | |
1177 | ||
1178 | static int __mv88e6xxx_read_addr(struct dsa_switch *ds, unsigned char *addr) | |
1179 | { | |
1180 | int i, ret; | |
1181 | ||
1182 | for (i = 0; i < 3; i++) { | |
cca8b133 AL |
1183 | ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, |
1184 | GLOBAL_ATU_MAC_01 + i); | |
defb05b9 GR |
1185 | if (ret < 0) |
1186 | return ret; | |
1187 | addr[i * 2] = ret >> 8; | |
1188 | addr[i * 2 + 1] = ret & 0xff; | |
1189 | } | |
1190 | ||
1191 | return 0; | |
1192 | } | |
1193 | ||
1194 | static int __mv88e6xxx_port_fdb_cmd(struct dsa_switch *ds, int port, | |
1195 | const unsigned char *addr, int state) | |
1196 | { | |
1197 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
1198 | u8 fid = ps->fid[port]; | |
1199 | int ret; | |
1200 | ||
1201 | ret = _mv88e6xxx_atu_wait(ds); | |
1202 | if (ret < 0) | |
1203 | return ret; | |
1204 | ||
1205 | ret = __mv88e6xxx_write_addr(ds, addr); | |
1206 | if (ret < 0) | |
1207 | return ret; | |
1208 | ||
cca8b133 | 1209 | ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_DATA, |
defb05b9 GR |
1210 | (0x10 << port) | state); |
1211 | if (ret) | |
1212 | return ret; | |
1213 | ||
cca8b133 | 1214 | ret = _mv88e6xxx_atu_cmd(ds, fid, GLOBAL_ATU_OP_LOAD_DB); |
defb05b9 GR |
1215 | |
1216 | return ret; | |
1217 | } | |
1218 | ||
1219 | int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port, | |
1220 | const unsigned char *addr, u16 vid) | |
1221 | { | |
1222 | int state = is_multicast_ether_addr(addr) ? | |
cca8b133 AL |
1223 | GLOBAL_ATU_DATA_STATE_MC_STATIC : |
1224 | GLOBAL_ATU_DATA_STATE_UC_STATIC; | |
defb05b9 GR |
1225 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); |
1226 | int ret; | |
1227 | ||
1228 | mutex_lock(&ps->smi_mutex); | |
1229 | ret = __mv88e6xxx_port_fdb_cmd(ds, port, addr, state); | |
1230 | mutex_unlock(&ps->smi_mutex); | |
1231 | ||
1232 | return ret; | |
1233 | } | |
1234 | ||
1235 | int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port, | |
1236 | const unsigned char *addr, u16 vid) | |
1237 | { | |
1238 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
1239 | int ret; | |
1240 | ||
1241 | mutex_lock(&ps->smi_mutex); | |
cca8b133 AL |
1242 | ret = __mv88e6xxx_port_fdb_cmd(ds, port, addr, |
1243 | GLOBAL_ATU_DATA_STATE_UNUSED); | |
defb05b9 GR |
1244 | mutex_unlock(&ps->smi_mutex); |
1245 | ||
1246 | return ret; | |
1247 | } | |
1248 | ||
1249 | static int __mv88e6xxx_port_getnext(struct dsa_switch *ds, int port, | |
1250 | unsigned char *addr, bool *is_static) | |
1251 | { | |
1252 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
1253 | u8 fid = ps->fid[port]; | |
1254 | int ret, state; | |
1255 | ||
1256 | ret = _mv88e6xxx_atu_wait(ds); | |
1257 | if (ret < 0) | |
1258 | return ret; | |
1259 | ||
1260 | ret = __mv88e6xxx_write_addr(ds, addr); | |
1261 | if (ret < 0) | |
1262 | return ret; | |
1263 | ||
1264 | do { | |
cca8b133 | 1265 | ret = _mv88e6xxx_atu_cmd(ds, fid, GLOBAL_ATU_OP_GET_NEXT_DB); |
defb05b9 GR |
1266 | if (ret < 0) |
1267 | return ret; | |
1268 | ||
cca8b133 | 1269 | ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_ATU_DATA); |
defb05b9 GR |
1270 | if (ret < 0) |
1271 | return ret; | |
cca8b133 AL |
1272 | state = ret & GLOBAL_ATU_DATA_STATE_MASK; |
1273 | if (state == GLOBAL_ATU_DATA_STATE_UNUSED) | |
defb05b9 GR |
1274 | return -ENOENT; |
1275 | } while (!(((ret >> 4) & 0xff) & (1 << port))); | |
1276 | ||
1277 | ret = __mv88e6xxx_read_addr(ds, addr); | |
1278 | if (ret < 0) | |
1279 | return ret; | |
1280 | ||
1281 | *is_static = state == (is_multicast_ether_addr(addr) ? | |
cca8b133 AL |
1282 | GLOBAL_ATU_DATA_STATE_MC_STATIC : |
1283 | GLOBAL_ATU_DATA_STATE_UC_STATIC); | |
defb05b9 GR |
1284 | |
1285 | return 0; | |
1286 | } | |
1287 | ||
1288 | /* get next entry for port */ | |
1289 | int mv88e6xxx_port_fdb_getnext(struct dsa_switch *ds, int port, | |
1290 | unsigned char *addr, bool *is_static) | |
1291 | { | |
1292 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
1293 | int ret; | |
1294 | ||
1295 | mutex_lock(&ps->smi_mutex); | |
1296 | ret = __mv88e6xxx_port_getnext(ds, port, addr, is_static); | |
1297 | mutex_unlock(&ps->smi_mutex); | |
1298 | ||
1299 | return ret; | |
1300 | } | |
1301 | ||
facd95b2 GR |
1302 | static void mv88e6xxx_bridge_work(struct work_struct *work) |
1303 | { | |
1304 | struct mv88e6xxx_priv_state *ps; | |
1305 | struct dsa_switch *ds; | |
1306 | int port; | |
1307 | ||
1308 | ps = container_of(work, struct mv88e6xxx_priv_state, bridge_work); | |
1309 | ds = ((struct dsa_switch *)ps) - 1; | |
1310 | ||
1311 | while (ps->port_state_update_mask) { | |
1312 | port = __ffs(ps->port_state_update_mask); | |
1313 | clear_bit(port, &ps->port_state_update_mask); | |
1314 | mv88e6xxx_set_port_state(ds, port, ps->port_state[port]); | |
1315 | } | |
1316 | } | |
1317 | ||
dbde9e66 | 1318 | static int mv88e6xxx_setup_port(struct dsa_switch *ds, int port) |
d827e88a GR |
1319 | { |
1320 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
facd95b2 | 1321 | int ret, fid; |
54d792f2 | 1322 | u16 reg; |
d827e88a GR |
1323 | |
1324 | mutex_lock(&ps->smi_mutex); | |
1325 | ||
54d792f2 AL |
1326 | if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) || |
1327 | mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) || | |
1328 | mv88e6xxx_6185_family(ds) || mv88e6xxx_6095_family(ds) || | |
1329 | mv88e6xxx_6065_family(ds)) { | |
1330 | /* MAC Forcing register: don't force link, speed, | |
1331 | * duplex or flow control state to any particular | |
1332 | * values on physical ports, but force the CPU port | |
1333 | * and all DSA ports to their maximum bandwidth and | |
1334 | * full duplex. | |
1335 | */ | |
1336 | reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_PCS_CTRL); | |
1337 | if (dsa_is_cpu_port(ds, port) || | |
1338 | ds->dsa_port_mask & (1 << port)) { | |
1339 | reg |= PORT_PCS_CTRL_FORCE_LINK | | |
1340 | PORT_PCS_CTRL_LINK_UP | | |
1341 | PORT_PCS_CTRL_DUPLEX_FULL | | |
1342 | PORT_PCS_CTRL_FORCE_DUPLEX; | |
1343 | if (mv88e6xxx_6065_family(ds)) | |
1344 | reg |= PORT_PCS_CTRL_100; | |
1345 | else | |
1346 | reg |= PORT_PCS_CTRL_1000; | |
1347 | } else { | |
1348 | reg |= PORT_PCS_CTRL_UNFORCED; | |
1349 | } | |
1350 | ||
1351 | ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), | |
1352 | PORT_PCS_CTRL, reg); | |
1353 | if (ret) | |
1354 | goto abort; | |
1355 | } | |
1356 | ||
1357 | /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock, | |
1358 | * disable Header mode, enable IGMP/MLD snooping, disable VLAN | |
1359 | * tunneling, determine priority by looking at 802.1p and IP | |
1360 | * priority fields (IP prio has precedence), and set STP state | |
1361 | * to Forwarding. | |
1362 | * | |
1363 | * If this is the CPU link, use DSA or EDSA tagging depending | |
1364 | * on which tagging mode was configured. | |
1365 | * | |
1366 | * If this is a link to another switch, use DSA tagging mode. | |
1367 | * | |
1368 | * If this is the upstream port for this switch, enable | |
1369 | * forwarding of unknown unicasts and multicasts. | |
1370 | */ | |
1371 | reg = 0; | |
1372 | if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) || | |
1373 | mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) || | |
1374 | mv88e6xxx_6095_family(ds) || mv88e6xxx_6065_family(ds) || | |
1375 | mv88e6xxx_6185_family(ds)) | |
1376 | reg = PORT_CONTROL_IGMP_MLD_SNOOP | | |
1377 | PORT_CONTROL_USE_TAG | PORT_CONTROL_USE_IP | | |
1378 | PORT_CONTROL_STATE_FORWARDING; | |
1379 | if (dsa_is_cpu_port(ds, port)) { | |
1380 | if (mv88e6xxx_6095_family(ds) || mv88e6xxx_6185_family(ds)) | |
1381 | reg |= PORT_CONTROL_DSA_TAG; | |
1382 | if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) || | |
1383 | mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds)) { | |
1384 | if (ds->dst->tag_protocol == DSA_TAG_PROTO_EDSA) | |
1385 | reg |= PORT_CONTROL_FRAME_ETHER_TYPE_DSA; | |
1386 | else | |
1387 | reg |= PORT_CONTROL_FRAME_MODE_DSA; | |
1388 | } | |
1389 | ||
1390 | if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) || | |
1391 | mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) || | |
1392 | mv88e6xxx_6095_family(ds) || mv88e6xxx_6065_family(ds) || | |
1393 | mv88e6xxx_6185_family(ds)) { | |
1394 | if (ds->dst->tag_protocol == DSA_TAG_PROTO_EDSA) | |
1395 | reg |= PORT_CONTROL_EGRESS_ADD_TAG; | |
1396 | } | |
1397 | } | |
1398 | if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) || | |
1399 | mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) || | |
1400 | mv88e6xxx_6095_family(ds) || mv88e6xxx_6065_family(ds)) { | |
1401 | if (ds->dsa_port_mask & (1 << port)) | |
1402 | reg |= PORT_CONTROL_FRAME_MODE_DSA; | |
1403 | if (port == dsa_upstream_port(ds)) | |
1404 | reg |= PORT_CONTROL_FORWARD_UNKNOWN | | |
1405 | PORT_CONTROL_FORWARD_UNKNOWN_MC; | |
1406 | } | |
1407 | if (reg) { | |
1408 | ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), | |
1409 | PORT_CONTROL, reg); | |
1410 | if (ret) | |
1411 | goto abort; | |
1412 | } | |
1413 | ||
1414 | /* Port Control 2: don't force a good FCS, set the maximum | |
1415 | * frame size to 10240 bytes, don't let the switch add or | |
1416 | * strip 802.1q tags, don't discard tagged or untagged frames | |
1417 | * on this port, do a destination address lookup on all | |
1418 | * received packets as usual, disable ARP mirroring and don't | |
1419 | * send a copy of all transmitted/received frames on this port | |
1420 | * to the CPU. | |
1421 | */ | |
1422 | reg = 0; | |
1423 | if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) || | |
1424 | mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) || | |
1425 | mv88e6xxx_6095_family(ds)) | |
1426 | reg = PORT_CONTROL_2_MAP_DA; | |
1427 | ||
1428 | if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) || | |
1429 | mv88e6xxx_6165_family(ds)) | |
1430 | reg |= PORT_CONTROL_2_JUMBO_10240; | |
1431 | ||
1432 | if (mv88e6xxx_6095_family(ds) || mv88e6xxx_6185_family(ds)) { | |
1433 | /* Set the upstream port this port should use */ | |
1434 | reg |= dsa_upstream_port(ds); | |
1435 | /* enable forwarding of unknown multicast addresses to | |
1436 | * the upstream port | |
1437 | */ | |
1438 | if (port == dsa_upstream_port(ds)) | |
1439 | reg |= PORT_CONTROL_2_FORWARD_UNKNOWN; | |
1440 | } | |
1441 | ||
1442 | if (reg) { | |
1443 | ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), | |
1444 | PORT_CONTROL_2, reg); | |
1445 | if (ret) | |
1446 | goto abort; | |
1447 | } | |
1448 | ||
1449 | /* Port Association Vector: when learning source addresses | |
1450 | * of packets, add the address to the address database using | |
1451 | * a port bitmap that has only the bit for this port set and | |
1452 | * the other bits clear. | |
1453 | */ | |
1454 | ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_ASSOC_VECTOR, | |
1455 | 1 << port); | |
1456 | if (ret) | |
1457 | goto abort; | |
1458 | ||
1459 | /* Egress rate control 2: disable egress rate control. */ | |
1460 | ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_RATE_CONTROL_2, | |
1461 | 0x0000); | |
1462 | if (ret) | |
1463 | goto abort; | |
1464 | ||
1465 | if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) || | |
1466 | mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds)) { | |
1467 | /* Do not limit the period of time that this port can | |
1468 | * be paused for by the remote end or the period of | |
1469 | * time that this port can pause the remote end. | |
1470 | */ | |
1471 | ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), | |
1472 | PORT_PAUSE_CTRL, 0x0000); | |
1473 | if (ret) | |
1474 | goto abort; | |
1475 | ||
1476 | /* Port ATU control: disable limiting the number of | |
1477 | * address database entries that this port is allowed | |
1478 | * to use. | |
1479 | */ | |
1480 | ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), | |
1481 | PORT_ATU_CONTROL, 0x0000); | |
1482 | /* Priority Override: disable DA, SA and VTU priority | |
1483 | * override. | |
1484 | */ | |
1485 | ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), | |
1486 | PORT_PRI_OVERRIDE, 0x0000); | |
1487 | if (ret) | |
1488 | goto abort; | |
1489 | ||
1490 | /* Port Ethertype: use the Ethertype DSA Ethertype | |
1491 | * value. | |
1492 | */ | |
1493 | ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), | |
1494 | PORT_ETH_TYPE, ETH_P_EDSA); | |
1495 | if (ret) | |
1496 | goto abort; | |
1497 | /* Tag Remap: use an identity 802.1p prio -> switch | |
1498 | * prio mapping. | |
1499 | */ | |
1500 | ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), | |
1501 | PORT_TAG_REGMAP_0123, 0x3210); | |
1502 | if (ret) | |
1503 | goto abort; | |
1504 | ||
1505 | /* Tag Remap 2: use an identity 802.1p prio -> switch | |
1506 | * prio mapping. | |
1507 | */ | |
1508 | ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), | |
1509 | PORT_TAG_REGMAP_4567, 0x7654); | |
1510 | if (ret) | |
1511 | goto abort; | |
1512 | } | |
1513 | ||
1514 | if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) || | |
1515 | mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) || | |
1516 | mv88e6xxx_6185_family(ds) || mv88e6xxx_6095_family(ds)) { | |
1517 | /* Rate Control: disable ingress rate limiting. */ | |
1518 | ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), | |
1519 | PORT_RATE_CONTROL, 0x0001); | |
1520 | if (ret) | |
1521 | goto abort; | |
1522 | } | |
1523 | ||
366f0a0f GR |
1524 | /* Port Control 1: disable trunking, disable sending |
1525 | * learning messages to this port. | |
d827e88a | 1526 | */ |
614f03fc | 1527 | ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_CONTROL_1, 0x0000); |
d827e88a GR |
1528 | if (ret) |
1529 | goto abort; | |
1530 | ||
1531 | /* Port based VLAN map: give each port its own address | |
1532 | * database, allow the CPU port to talk to each of the 'real' | |
1533 | * ports, and allow each of the 'real' ports to only talk to | |
1534 | * the upstream port. | |
1535 | */ | |
facd95b2 GR |
1536 | fid = __ffs(ps->fid_mask); |
1537 | ps->fid[port] = fid; | |
1538 | ps->fid_mask &= ~(1 << fid); | |
1539 | ||
1540 | if (!dsa_is_cpu_port(ds, port)) | |
1541 | ps->bridge_mask[fid] = 1 << port; | |
d827e88a | 1542 | |
facd95b2 | 1543 | ret = _mv88e6xxx_update_port_config(ds, port); |
d827e88a GR |
1544 | if (ret) |
1545 | goto abort; | |
1546 | ||
1547 | /* Default VLAN ID and priority: don't set a default VLAN | |
1548 | * ID, and set the default packet priority to zero. | |
1549 | */ | |
47cf1e65 VD |
1550 | ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_DEFAULT_VLAN, |
1551 | 0x0000); | |
d827e88a GR |
1552 | abort: |
1553 | mutex_unlock(&ps->smi_mutex); | |
1554 | return ret; | |
1555 | } | |
1556 | ||
dbde9e66 AL |
1557 | int mv88e6xxx_setup_ports(struct dsa_switch *ds) |
1558 | { | |
1559 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
1560 | int ret; | |
1561 | int i; | |
1562 | ||
1563 | for (i = 0; i < ps->num_ports; i++) { | |
1564 | ret = mv88e6xxx_setup_port(ds, i); | |
1565 | if (ret < 0) | |
1566 | return ret; | |
1567 | } | |
1568 | return 0; | |
1569 | } | |
1570 | ||
acdaffcc GR |
1571 | int mv88e6xxx_setup_common(struct dsa_switch *ds) |
1572 | { | |
1573 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
1574 | ||
1575 | mutex_init(&ps->smi_mutex); | |
1576 | mutex_init(&ps->stats_mutex); | |
acdaffcc | 1577 | |
cca8b133 | 1578 | ps->id = REG_READ(REG_PORT(0), PORT_SWITCH_ID) & 0xfff0; |
a8f064c6 | 1579 | |
facd95b2 GR |
1580 | ps->fid_mask = (1 << DSA_MAX_PORTS) - 1; |
1581 | ||
1582 | INIT_WORK(&ps->bridge_work, mv88e6xxx_bridge_work); | |
1583 | ||
acdaffcc GR |
1584 | return 0; |
1585 | } | |
1586 | ||
54d792f2 AL |
1587 | int mv88e6xxx_setup_global(struct dsa_switch *ds) |
1588 | { | |
1589 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
1590 | int i; | |
1591 | ||
1592 | /* Set the default address aging time to 5 minutes, and | |
1593 | * enable address learn messages to be sent to all message | |
1594 | * ports. | |
1595 | */ | |
1596 | REG_WRITE(REG_GLOBAL, GLOBAL_ATU_CONTROL, | |
1597 | 0x0140 | GLOBAL_ATU_CONTROL_LEARN2ALL); | |
1598 | ||
1599 | /* Configure the IP ToS mapping registers. */ | |
1600 | REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_0, 0x0000); | |
1601 | REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_1, 0x0000); | |
1602 | REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_2, 0x5555); | |
1603 | REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_3, 0x5555); | |
1604 | REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_4, 0xaaaa); | |
1605 | REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_5, 0xaaaa); | |
1606 | REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_6, 0xffff); | |
1607 | REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_7, 0xffff); | |
1608 | ||
1609 | /* Configure the IEEE 802.1p priority mapping register. */ | |
1610 | REG_WRITE(REG_GLOBAL, GLOBAL_IEEE_PRI, 0xfa41); | |
1611 | ||
1612 | /* Send all frames with destination addresses matching | |
1613 | * 01:80:c2:00:00:0x to the CPU port. | |
1614 | */ | |
1615 | REG_WRITE(REG_GLOBAL2, GLOBAL2_MGMT_EN_0X, 0xffff); | |
1616 | ||
1617 | /* Ignore removed tag data on doubly tagged packets, disable | |
1618 | * flow control messages, force flow control priority to the | |
1619 | * highest, and send all special multicast frames to the CPU | |
1620 | * port at the highest priority. | |
1621 | */ | |
1622 | REG_WRITE(REG_GLOBAL2, GLOBAL2_SWITCH_MGMT, | |
1623 | 0x7 | GLOBAL2_SWITCH_MGMT_RSVD2CPU | 0x70 | | |
1624 | GLOBAL2_SWITCH_MGMT_FORCE_FLOW_CTRL_PRI); | |
1625 | ||
1626 | /* Program the DSA routing table. */ | |
1627 | for (i = 0; i < 32; i++) { | |
1628 | int nexthop = 0x1f; | |
1629 | ||
1630 | if (ds->pd->rtable && | |
1631 | i != ds->index && i < ds->dst->pd->nr_chips) | |
1632 | nexthop = ds->pd->rtable[i] & 0x1f; | |
1633 | ||
1634 | REG_WRITE(REG_GLOBAL2, GLOBAL2_DEVICE_MAPPING, | |
1635 | GLOBAL2_DEVICE_MAPPING_UPDATE | | |
1636 | (i << GLOBAL2_DEVICE_MAPPING_TARGET_SHIFT) | | |
1637 | nexthop); | |
1638 | } | |
1639 | ||
1640 | /* Clear all trunk masks. */ | |
1641 | for (i = 0; i < 8; i++) | |
1642 | REG_WRITE(REG_GLOBAL2, GLOBAL2_TRUNK_MASK, | |
1643 | 0x8000 | (i << GLOBAL2_TRUNK_MASK_NUM_SHIFT) | | |
1644 | ((1 << ps->num_ports) - 1)); | |
1645 | ||
1646 | /* Clear all trunk mappings. */ | |
1647 | for (i = 0; i < 16; i++) | |
1648 | REG_WRITE(REG_GLOBAL2, GLOBAL2_TRUNK_MAPPING, | |
1649 | GLOBAL2_TRUNK_MAPPING_UPDATE | | |
1650 | (i << GLOBAL2_TRUNK_MAPPING_ID_SHIFT)); | |
1651 | ||
1652 | if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) || | |
1653 | mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds)) { | |
1654 | /* Send all frames with destination addresses matching | |
1655 | * 01:80:c2:00:00:2x to the CPU port. | |
1656 | */ | |
1657 | REG_WRITE(REG_GLOBAL2, GLOBAL2_MGMT_EN_2X, 0xffff); | |
1658 | ||
1659 | /* Initialise cross-chip port VLAN table to reset | |
1660 | * defaults. | |
1661 | */ | |
1662 | REG_WRITE(REG_GLOBAL2, GLOBAL2_PVT_ADDR, 0x9000); | |
1663 | ||
1664 | /* Clear the priority override table. */ | |
1665 | for (i = 0; i < 16; i++) | |
1666 | REG_WRITE(REG_GLOBAL2, GLOBAL2_PRIO_OVERRIDE, | |
1667 | 0x8000 | (i << 8)); | |
1668 | } | |
1669 | ||
1670 | if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) || | |
1671 | mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) || | |
1672 | mv88e6xxx_6185_family(ds) || mv88e6xxx_6095_family(ds)) { | |
1673 | /* Disable ingress rate limiting by resetting all | |
1674 | * ingress rate limit registers to their initial | |
1675 | * state. | |
1676 | */ | |
1677 | for (i = 0; i < ps->num_ports; i++) | |
1678 | REG_WRITE(REG_GLOBAL2, GLOBAL2_INGRESS_OP, | |
1679 | 0x9000 | (i << 8)); | |
1680 | } | |
1681 | ||
1682 | return 0; | |
1683 | } | |
1684 | ||
143a8307 AL |
1685 | int mv88e6xxx_switch_reset(struct dsa_switch *ds, bool ppu_active) |
1686 | { | |
1687 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
1688 | u16 is_reset = (ppu_active ? 0x8800 : 0xc800); | |
1689 | unsigned long timeout; | |
1690 | int ret; | |
1691 | int i; | |
1692 | ||
1693 | /* Set all ports to the disabled state. */ | |
1694 | for (i = 0; i < ps->num_ports; i++) { | |
cca8b133 AL |
1695 | ret = REG_READ(REG_PORT(i), PORT_CONTROL); |
1696 | REG_WRITE(REG_PORT(i), PORT_CONTROL, ret & 0xfffc); | |
143a8307 AL |
1697 | } |
1698 | ||
1699 | /* Wait for transmit queues to drain. */ | |
1700 | usleep_range(2000, 4000); | |
1701 | ||
1702 | /* Reset the switch. Keep the PPU active if requested. The PPU | |
1703 | * needs to be active to support indirect phy register access | |
1704 | * through global registers 0x18 and 0x19. | |
1705 | */ | |
1706 | if (ppu_active) | |
1707 | REG_WRITE(REG_GLOBAL, 0x04, 0xc000); | |
1708 | else | |
1709 | REG_WRITE(REG_GLOBAL, 0x04, 0xc400); | |
1710 | ||
1711 | /* Wait up to one second for reset to complete. */ | |
1712 | timeout = jiffies + 1 * HZ; | |
1713 | while (time_before(jiffies, timeout)) { | |
1714 | ret = REG_READ(REG_GLOBAL, 0x00); | |
1715 | if ((ret & is_reset) == is_reset) | |
1716 | break; | |
1717 | usleep_range(1000, 2000); | |
1718 | } | |
1719 | if (time_after(jiffies, timeout)) | |
1720 | return -ETIMEDOUT; | |
1721 | ||
1722 | return 0; | |
1723 | } | |
1724 | ||
49143585 AL |
1725 | int mv88e6xxx_phy_page_read(struct dsa_switch *ds, int port, int page, int reg) |
1726 | { | |
1727 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
1728 | int ret; | |
1729 | ||
3898c148 | 1730 | mutex_lock(&ps->smi_mutex); |
fd3a0ee4 | 1731 | ret = _mv88e6xxx_phy_write_indirect(ds, port, 0x16, page); |
49143585 AL |
1732 | if (ret < 0) |
1733 | goto error; | |
fd3a0ee4 | 1734 | ret = _mv88e6xxx_phy_read_indirect(ds, port, reg); |
49143585 | 1735 | error: |
fd3a0ee4 | 1736 | _mv88e6xxx_phy_write_indirect(ds, port, 0x16, 0x0); |
3898c148 | 1737 | mutex_unlock(&ps->smi_mutex); |
49143585 AL |
1738 | return ret; |
1739 | } | |
1740 | ||
1741 | int mv88e6xxx_phy_page_write(struct dsa_switch *ds, int port, int page, | |
1742 | int reg, int val) | |
1743 | { | |
1744 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
1745 | int ret; | |
1746 | ||
3898c148 | 1747 | mutex_lock(&ps->smi_mutex); |
fd3a0ee4 | 1748 | ret = _mv88e6xxx_phy_write_indirect(ds, port, 0x16, page); |
49143585 AL |
1749 | if (ret < 0) |
1750 | goto error; | |
1751 | ||
fd3a0ee4 | 1752 | ret = _mv88e6xxx_phy_write_indirect(ds, port, reg, val); |
49143585 | 1753 | error: |
fd3a0ee4 | 1754 | _mv88e6xxx_phy_write_indirect(ds, port, 0x16, 0x0); |
3898c148 | 1755 | mutex_unlock(&ps->smi_mutex); |
fd3a0ee4 AL |
1756 | return ret; |
1757 | } | |
1758 | ||
1759 | static int mv88e6xxx_port_to_phy_addr(struct dsa_switch *ds, int port) | |
1760 | { | |
1761 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
1762 | ||
1763 | if (port >= 0 && port < ps->num_ports) | |
1764 | return port; | |
1765 | return -EINVAL; | |
1766 | } | |
1767 | ||
1768 | int | |
1769 | mv88e6xxx_phy_read(struct dsa_switch *ds, int port, int regnum) | |
1770 | { | |
1771 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
1772 | int addr = mv88e6xxx_port_to_phy_addr(ds, port); | |
1773 | int ret; | |
1774 | ||
1775 | if (addr < 0) | |
1776 | return addr; | |
1777 | ||
3898c148 | 1778 | mutex_lock(&ps->smi_mutex); |
fd3a0ee4 | 1779 | ret = _mv88e6xxx_phy_read(ds, addr, regnum); |
3898c148 | 1780 | mutex_unlock(&ps->smi_mutex); |
fd3a0ee4 AL |
1781 | return ret; |
1782 | } | |
1783 | ||
1784 | int | |
1785 | mv88e6xxx_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val) | |
1786 | { | |
1787 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
1788 | int addr = mv88e6xxx_port_to_phy_addr(ds, port); | |
1789 | int ret; | |
1790 | ||
1791 | if (addr < 0) | |
1792 | return addr; | |
1793 | ||
3898c148 | 1794 | mutex_lock(&ps->smi_mutex); |
fd3a0ee4 | 1795 | ret = _mv88e6xxx_phy_write(ds, addr, regnum, val); |
3898c148 | 1796 | mutex_unlock(&ps->smi_mutex); |
fd3a0ee4 AL |
1797 | return ret; |
1798 | } | |
1799 | ||
1800 | int | |
1801 | mv88e6xxx_phy_read_indirect(struct dsa_switch *ds, int port, int regnum) | |
1802 | { | |
1803 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
1804 | int addr = mv88e6xxx_port_to_phy_addr(ds, port); | |
1805 | int ret; | |
1806 | ||
1807 | if (addr < 0) | |
1808 | return addr; | |
1809 | ||
3898c148 | 1810 | mutex_lock(&ps->smi_mutex); |
fd3a0ee4 | 1811 | ret = _mv88e6xxx_phy_read_indirect(ds, addr, regnum); |
3898c148 | 1812 | mutex_unlock(&ps->smi_mutex); |
fd3a0ee4 AL |
1813 | return ret; |
1814 | } | |
1815 | ||
1816 | int | |
1817 | mv88e6xxx_phy_write_indirect(struct dsa_switch *ds, int port, int regnum, | |
1818 | u16 val) | |
1819 | { | |
1820 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
1821 | int addr = mv88e6xxx_port_to_phy_addr(ds, port); | |
1822 | int ret; | |
1823 | ||
1824 | if (addr < 0) | |
1825 | return addr; | |
1826 | ||
3898c148 | 1827 | mutex_lock(&ps->smi_mutex); |
fd3a0ee4 | 1828 | ret = _mv88e6xxx_phy_write_indirect(ds, addr, regnum, val); |
3898c148 | 1829 | mutex_unlock(&ps->smi_mutex); |
49143585 AL |
1830 | return ret; |
1831 | } | |
1832 | ||
98e67308 BH |
1833 | static int __init mv88e6xxx_init(void) |
1834 | { | |
1835 | #if IS_ENABLED(CONFIG_NET_DSA_MV88E6131) | |
1836 | register_switch_driver(&mv88e6131_switch_driver); | |
1837 | #endif | |
1838 | #if IS_ENABLED(CONFIG_NET_DSA_MV88E6123_61_65) | |
1839 | register_switch_driver(&mv88e6123_61_65_switch_driver); | |
42f27253 | 1840 | #endif |
3ad50cca GR |
1841 | #if IS_ENABLED(CONFIG_NET_DSA_MV88E6352) |
1842 | register_switch_driver(&mv88e6352_switch_driver); | |
1843 | #endif | |
42f27253 AL |
1844 | #if IS_ENABLED(CONFIG_NET_DSA_MV88E6171) |
1845 | register_switch_driver(&mv88e6171_switch_driver); | |
98e67308 BH |
1846 | #endif |
1847 | return 0; | |
1848 | } | |
1849 | module_init(mv88e6xxx_init); | |
1850 | ||
1851 | static void __exit mv88e6xxx_cleanup(void) | |
1852 | { | |
42f27253 AL |
1853 | #if IS_ENABLED(CONFIG_NET_DSA_MV88E6171) |
1854 | unregister_switch_driver(&mv88e6171_switch_driver); | |
1855 | #endif | |
98e67308 BH |
1856 | #if IS_ENABLED(CONFIG_NET_DSA_MV88E6123_61_65) |
1857 | unregister_switch_driver(&mv88e6123_61_65_switch_driver); | |
1858 | #endif | |
1859 | #if IS_ENABLED(CONFIG_NET_DSA_MV88E6131) | |
1860 | unregister_switch_driver(&mv88e6131_switch_driver); | |
1861 | #endif | |
1862 | } | |
1863 | module_exit(mv88e6xxx_cleanup); | |
3d825ede BH |
1864 | |
1865 | MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>"); | |
1866 | MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips"); | |
1867 | MODULE_LICENSE("GPL"); |